drivers/net/wireless/ath/ath9k/hw.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <linux/io.h>
  18 #include <linux/slab.h>
  19 #include <asm/unaligned.h>
  20
  21 #include "hw.h"
  22 #include "hw-ops.h"
  23 #include "rc.h"
  24 #include "ar9003_mac.h"
  25
  26 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  27
  28 MODULE_AUTHOR("Atheros Communications");
  29 MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  30 MODULE_SUPPORTED_DEVICE("Atheros 802.11n WLAN cards");
  31 MODULE_LICENSE("Dual BSD/GPL");
  32
  33 static int __init ath9k_init(void)
  34 {
  35         return 0;
  36 }
  37 module_init(ath9k_init);
  38
  39 static void __exit ath9k_exit(void)
  40 {
  41         return;
  42 }
  43 module_exit(ath9k_exit);
  44
  45 /* Private hardware callbacks */
  46
  47 static void ath9k_hw_init_cal_settings(struct ath_hw *ah)
  48 {
  49         ath9k_hw_private_ops(ah)->init_cal_settings(ah);
  50 }
  51
  52 static void ath9k_hw_init_mode_regs(struct ath_hw *ah)
  53 {
  54         ath9k_hw_private_ops(ah)->init_mode_regs(ah);
  55 }
  56
  57 static bool ath9k_hw_macversion_supported(struct ath_hw *ah)
  58 {
  59         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
  60
  61         return priv_ops->macversion_supported(ah->hw_version.macVersion);
  62 }
  63
  64 static u32 ath9k_hw_compute_pll_control(struct ath_hw *ah,
  65                                         struct ath9k_channel *chan)
  66 {
  67         return ath9k_hw_private_ops(ah)->compute_pll_control(ah, chan);
  68 }
  69
  70 static void ath9k_hw_init_mode_gain_regs(struct ath_hw *ah)
  71 {
  72         if (!ath9k_hw_private_ops(ah)->init_mode_gain_regs)
  73                 return;
  74
  75         ath9k_hw_private_ops(ah)->init_mode_gain_regs(ah);
  76 }
  77
  78 static void ath9k_hw_ani_cache_ini_regs(struct ath_hw *ah)
  79 {
  80         /* You will not have this callback if using the old ANI */
  81         if (!ath9k_hw_private_ops(ah)->ani_cache_ini_regs)
  82                 return;
  83
  84         ath9k_hw_private_ops(ah)->ani_cache_ini_regs(ah);
  85 }
  86
  87 /********************/
  88 /* Helper Functions */
  89 /********************/
  90
  91 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
  92 {
  93         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
  94
  95         if (!ah->curchan) /* should really check for CCK instead */
  96                 return usecs *ATH9K_CLOCK_RATE_CCK;
  97         if (conf->channel->band == IEEE80211_BAND_2GHZ)
  98                 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
  99
 100         if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
 101                 return usecs * ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
 102         else
 103                 return usecs * ATH9K_CLOCK_RATE_5GHZ_OFDM;
 104 }
 105
 106 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
 107 {
 108         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 109
 110         if (conf_is_ht40(conf))
 111                 return ath9k_hw_mac_clks(ah, usecs) * 2;
 112         else
 113                 return ath9k_hw_mac_clks(ah, usecs);
 114 }
 115
 116 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
 117 {
 118         int i;
 119
 120         BUG_ON(timeout < AH_TIME_QUANTUM);
 121
 122         for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
 123                 if ((REG_READ(ah, reg) & mask) == val)
 124                         return true;
 125
 126                 udelay(AH_TIME_QUANTUM);
 127         }
 128
 129         ath_print(ath9k_hw_common(ah), ATH_DBG_ANY,
 130                   "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
 131                   timeout, reg, REG_READ(ah, reg), mask, val);
 132
 133         return false;
 134 }
 135 EXPORT_SYMBOL(ath9k_hw_wait);
 136
 137 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 138 {
 139         u32 retval;
 140         int i;
 141
 142         for (i = 0, retval = 0; i < n; i++) {
 143                 retval = (retval << 1) | (val & 1);
 144                 val >>= 1;
 145         }
 146         return retval;
 147 }
 148
 149 bool ath9k_get_channel_edges(struct ath_hw *ah,
 150                              u16 flags, u16 *low,
 151                              u16 *high)
 152 {
 153         struct ath9k_hw_capabilities *pCap = &ah->caps;
 154
 155         if (flags & CHANNEL_5GHZ) {
 156                 *low = pCap->low_5ghz_chan;
 157                 *high = pCap->high_5ghz_chan;
 158                 return true;
 159         }
 160         if ((flags & CHANNEL_2GHZ)) {
 161                 *low = pCap->low_2ghz_chan;
 162                 *high = pCap->high_2ghz_chan;
 163                 return true;
 164         }
 165         return false;
 166 }
 167
 168 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 169                            u8 phy, int kbps,
 170                            u32 frameLen, u16 rateix,
 171                            bool shortPreamble)
 172 {
 173         u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 174
 175         if (kbps == 0)
 176                 return 0;
 177
 178         switch (phy) {
 179         case WLAN_RC_PHY_CCK:
 180                 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 181                 if (shortPreamble)
 182                         phyTime >>= 1;
 183                 numBits = frameLen << 3;
 184                 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 185                 break;
 186         case WLAN_RC_PHY_OFDM:
 187                 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 188                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 189                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 190                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 191                         txTime = OFDM_SIFS_TIME_QUARTER
 192                                 + OFDM_PREAMBLE_TIME_QUARTER
 193                                 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 194                 } else if (ah->curchan &&
 195                            IS_CHAN_HALF_RATE(ah->curchan)) {
 196                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
 197                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 198                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 199                         txTime = OFDM_SIFS_TIME_HALF +
 200                                 OFDM_PREAMBLE_TIME_HALF
 201                                 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
 202                 } else {
 203                         bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 204                         numBits = OFDM_PLCP_BITS + (frameLen << 3);
 205                         numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 206                         txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 207                                 + (numSymbols * OFDM_SYMBOL_TIME);
 208                 }
 209                 break;
 210         default:
 211                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 212                           "Unknown phy %u (rate ix %u)\n", phy, rateix);
 213                 txTime = 0;
 214                 break;
 215         }
 216
 217         return txTime;
 218 }
 219 EXPORT_SYMBOL(ath9k_hw_computetxtime);
 220
 221 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 222                                   struct ath9k_channel *chan,
 223                                   struct chan_centers *centers)
 224 {
 225         int8_t extoff;
 226
 227         if (!IS_CHAN_HT40(chan)) {
 228                 centers->ctl_center = centers->ext_center =
 229                         centers->synth_center = chan->channel;
 230                 return;
 231         }
 232
 233         if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 234             (chan->chanmode == CHANNEL_G_HT40PLUS)) {
 235                 centers->synth_center =
 236                         chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 237                 extoff = 1;
 238         } else {
 239                 centers->synth_center =
 240                         chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 241                 extoff = -1;
 242         }
 243
 244         centers->ctl_center =
 245                 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 246         /* 25 MHz spacing is supported by hw but not on upper layers */
 247         centers->ext_center =
 248                 centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 249 }
 250
 251 /******************/
 252 /* Chip Revisions */
 253 /******************/
 254
 255 static void ath9k_hw_read_revisions(struct ath_hw *ah)
 256 {
 257         u32 val;
 258
 259         val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
 260
 261         if (val == 0xFF) {
 262                 val = REG_READ(ah, AR_SREV);
 263                 ah->hw_version.macVersion =
 264                         (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 265                 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 266                 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 267         } else {
 268                 if (!AR_SREV_9100(ah))
 269                         ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 270
 271                 ah->hw_version.macRev = val & AR_SREV_REVISION;
 272
 273                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 274                         ah->is_pciexpress = true;
 275         }
 276 }
 277
 278 /************************************/
 279 /* HW Attach, Detach, Init Routines */
 280 /************************************/
 281
 282 static void ath9k_hw_disablepcie(struct ath_hw *ah)
 283 {
 284         if (AR_SREV_9100(ah))
 285                 return;
 286
 287         ENABLE_REGWRITE_BUFFER(ah);
 288
 289         REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 290         REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 291         REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 292         REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 293         REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 294         REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 295         REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 296         REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 297         REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 298
 299         REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 300
 301         REGWRITE_BUFFER_FLUSH(ah);
 302         DISABLE_REGWRITE_BUFFER(ah);
 303 }
 304
 305 /* This should work for all families including legacy */
 306 static bool ath9k_hw_chip_test(struct ath_hw *ah)
 307 {
 308         struct ath_common *common = ath9k_hw_common(ah);
 309         u32 regAddr[2] = { AR_STA_ID0 };
 310         u32 regHold[2];
 311         u32 patternData[4] = { 0x55555555,
 312                                0xaaaaaaaa,
 313                                0x66666666,
 314                                0x99999999 };
 315         int i, j, loop_max;
 316
 317         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 318                 loop_max = 2;
 319                 regAddr[1] = AR_PHY_BASE + (8 << 2);
 320         } else
 321                 loop_max = 1;
 322
 323         for (i = 0; i < loop_max; i++) {
 324                 u32 addr = regAddr[i];
 325                 u32 wrData, rdData;
 326
 327                 regHold[i] = REG_READ(ah, addr);
 328                 for (j = 0; j < 0x100; j++) {
 329                         wrData = (j << 16) | j;
 330                         REG_WRITE(ah, addr, wrData);
 331                         rdData = REG_READ(ah, addr);
 332                         if (rdData != wrData) {
 333                                 ath_print(common, ATH_DBG_FATAL,
 334                                           "address test failed "
 335                                           "addr: 0x%08x - wr:0x%08x != "
 336                                           "rd:0x%08x\n",
 337                                           addr, wrData, rdData);
 338                                 return false;
 339                         }
 340                 }
 341                 for (j = 0; j < 4; j++) {
 342                         wrData = patternData[j];
 343                         REG_WRITE(ah, addr, wrData);
 344                         rdData = REG_READ(ah, addr);
 345                         if (wrData != rdData) {
 346                                 ath_print(common, ATH_DBG_FATAL,
 347                                           "address test failed "
 348                                           "addr: 0x%08x - wr:0x%08x != "
 349                                           "rd:0x%08x\n",
 350                                           addr, wrData, rdData);
 351                                 return false;
 352                         }
 353                 }
 354                 REG_WRITE(ah, regAddr[i], regHold[i]);
 355         }
 356         udelay(100);
 357
 358         return true;
 359 }
 360
 361 static void ath9k_hw_init_config(struct ath_hw *ah)
 362 {
 363         int i;
 364
 365         ah->config.dma_beacon_response_time = 2;
 366         ah->config.sw_beacon_response_time = 10;
 367         ah->config.additional_swba_backoff = 0;
 368         ah->config.ack_6mb = 0x0;
 369         ah->config.cwm_ignore_extcca = 0;
 370         ah->config.pcie_powersave_enable = 0;
 371         ah->config.pcie_clock_req = 0;
 372         ah->config.pcie_waen = 0;
 373         ah->config.analog_shiftreg = 1;
 374         ah->config.ofdm_trig_low = 200;
 375         ah->config.ofdm_trig_high = 500;
 376         ah->config.cck_trig_high = 200;
 377         ah->config.cck_trig_low = 100;
 378         ah->config.enable_ani = true;
 379
 380         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 381                 ah->config.spurchans[i][0] = AR_NO_SPUR;
 382                 ah->config.spurchans[i][1] = AR_NO_SPUR;
 383         }
 384
 385         if (ah->hw_version.devid != AR2427_DEVID_PCIE)
 386                 ah->config.ht_enable = 1;
 387         else
 388                 ah->config.ht_enable = 0;
 389
 390         ah->config.rx_intr_mitigation = true;
 391
 392         /*
 393          * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 394          * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 395          * This means we use it for all AR5416 devices, and the few
 396          * minor PCI AR9280 devices out there.
 397          *
 398          * Serialization is required because these devices do not handle
 399          * well the case of two concurrent reads/writes due to the latency
 400          * involved. During one read/write another read/write can be issued
 401          * on another CPU while the previous read/write may still be working
 402          * on our hardware, if we hit this case the hardware poops in a loop.
 403          * We prevent this by serializing reads and writes.
 404          *
 405          * This issue is not present on PCI-Express devices or pre-AR5416
 406          * devices (legacy, 802.11abg).
 407          */
 408         if (num_possible_cpus() > 1)
 409                 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 410 }
 411
 412 static void ath9k_hw_init_defaults(struct ath_hw *ah)
 413 {
 414         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 415
 416         regulatory->country_code = CTRY_DEFAULT;
 417         regulatory->power_limit = MAX_RATE_POWER;
 418         regulatory->tp_scale = ATH9K_TP_SCALE_MAX;
 419
 420         ah->hw_version.magic = AR5416_MAGIC;
 421         ah->hw_version.subvendorid = 0;
 422
 423         ah->ah_flags = 0;
 424         if (!AR_SREV_9100(ah))
 425                 ah->ah_flags = AH_USE_EEPROM;
 426
 427         ah->atim_window = 0;
 428         ah->sta_id1_defaults =
 429                 AR_STA_ID1_CRPT_MIC_ENABLE |
 430                 AR_STA_ID1_MCAST_KSRCH;
 431         ah->beacon_interval = 100;
 432         ah->enable_32kHz_clock = DONT_USE_32KHZ;
 433         ah->slottime = (u32) -1;
 434         ah->globaltxtimeout = (u32) -1;
 435         ah->power_mode = ATH9K_PM_UNDEFINED;
 436 }
 437
 438 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
 439 {
 440         struct ath_common *common = ath9k_hw_common(ah);
 441         u32 sum;
 442         int i;
 443         u16 eeval;
 444         u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 445
 446         sum = 0;
 447         for (i = 0; i < 3; i++) {
 448                 eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
 449                 sum += eeval;
 450                 common->macaddr[2 * i] = eeval >> 8;
 451                 common->macaddr[2 * i + 1] = eeval & 0xff;
 452         }
 453         if (sum == 0 || sum == 0xffff * 3)
 454                 return -EADDRNOTAVAIL;
 455
 456         return 0;
 457 }
 458
 459 static int ath9k_hw_post_init(struct ath_hw *ah)
 460 {
 461         int ecode;
 462
 463         if (!AR_SREV_9271(ah)) {
 464                 if (!ath9k_hw_chip_test(ah))
 465                         return -ENODEV;
 466         }
 467
 468         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 469                 ecode = ar9002_hw_rf_claim(ah);
 470                 if (ecode != 0)
 471                         return ecode;
 472         }
 473
 474         ecode = ath9k_hw_eeprom_init(ah);
 475         if (ecode != 0)
 476                 return ecode;
 477
 478         ath_print(ath9k_hw_common(ah), ATH_DBG_CONFIG,
 479                   "Eeprom VER: %d, REV: %d\n",
 480                   ah->eep_ops->get_eeprom_ver(ah),
 481                   ah->eep_ops->get_eeprom_rev(ah));
 482
 483         ecode = ath9k_hw_rf_alloc_ext_banks(ah);
 484         if (ecode) {
 485                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 486                           "Failed allocating banks for "
 487                           "external radio\n");
 488                 return ecode;
 489         }
 490
 491         if (!AR_SREV_9100(ah)) {
 492                 ath9k_hw_ani_setup(ah);
 493                 ath9k_hw_ani_init(ah);
 494         }
 495
 496         return 0;
 497 }
 498
 499 static void ath9k_hw_attach_ops(struct ath_hw *ah)
 500 {
 501         if (AR_SREV_9300_20_OR_LATER(ah))
 502                 ar9003_hw_attach_ops(ah);
 503         else
 504                 ar9002_hw_attach_ops(ah);
 505 }
 506
 507 /* Called for all hardware families */
 508 static int __ath9k_hw_init(struct ath_hw *ah)
 509 {
 510         struct ath_common *common = ath9k_hw_common(ah);
 511         int r = 0;
 512
 513         if (ah->hw_version.devid == AR5416_AR9100_DEVID)
 514                 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 515
 516         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 517                 ath_print(common, ATH_DBG_FATAL,
 518                           "Couldn't reset chip\n");
 519                 return -EIO;
 520         }
 521
 522         ath9k_hw_init_defaults(ah);
 523         ath9k_hw_init_config(ah);
 524
 525         ath9k_hw_attach_ops(ah);
 526
 527         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 528                 ath_print(common, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
 529                 return -EIO;
 530         }
 531
 532         if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 533                 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 534                     (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
 535                         ah->config.serialize_regmode =
 536                                 SER_REG_MODE_ON;
 537                 } else {
 538                         ah->config.serialize_regmode =
 539                                 SER_REG_MODE_OFF;
 540                 }
 541         }
 542
 543         ath_print(common, ATH_DBG_RESET, "serialize_regmode is %d\n",
 544                 ah->config.serialize_regmode);
 545
 546         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 547                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 548         else
 549                 ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 550
 551         if (!ath9k_hw_macversion_supported(ah)) {
 552                 ath_print(common, ATH_DBG_FATAL,
 553                           "Mac Chip Rev 0x%02x.%x is not supported by "
 554                           "this driver\n", ah->hw_version.macVersion,
 555                           ah->hw_version.macRev);
 556                 return -EOPNOTSUPP;
 557         }
 558
 559         if (AR_SREV_9271(ah) || AR_SREV_9100(ah))
 560                 ah->is_pciexpress = false;
 561
 562         ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 563         ath9k_hw_init_cal_settings(ah);
 564
 565         ah->ani_function = ATH9K_ANI_ALL;
 566         if (AR_SREV_9280_10_OR_LATER(ah) && !AR_SREV_9300_20_OR_LATER(ah))
 567                 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
 568         if (!AR_SREV_9300_20_OR_LATER(ah))
 569                 ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
 570
 571         ath9k_hw_init_mode_regs(ah);
 572
 573         /*
 574          * Configire PCIE after Ini init. SERDES values now come from ini file
 575          * This enables PCIe low power mode.
 576          */
 577         if (AR_SREV_9300_20_OR_LATER(ah)) {
 578                 u32 regval;
 579                 unsigned int i;
 580
 581                 /* Set Bits 16 and 17 in the AR_WA register. */
 582                 regval = REG_READ(ah, AR_WA);
 583                 regval |= 0x00030000;
 584                 REG_WRITE(ah, AR_WA, regval);
 585
 586                 for (i = 0; i < ah->iniPcieSerdesLowPower.ia_rows; i++) {
 587                         REG_WRITE(ah,
 588                                   INI_RA(&ah->iniPcieSerdesLowPower, i, 0),
 589                                   INI_RA(&ah->iniPcieSerdesLowPower, i, 1));
 590                 }
 591         }
 592
 593         if (ah->is_pciexpress)
 594                 ath9k_hw_configpcipowersave(ah, 0, 0);
 595         else
 596                 ath9k_hw_disablepcie(ah);
 597
 598         if (!AR_SREV_9300_20_OR_LATER(ah))
 599                 ar9002_hw_cck_chan14_spread(ah);
 600
 601         r = ath9k_hw_post_init(ah);
 602         if (r)
 603                 return r;
 604
 605         ath9k_hw_init_mode_gain_regs(ah);
 606         r = ath9k_hw_fill_cap_info(ah);
 607         if (r)
 608                 return r;
 609
 610         r = ath9k_hw_init_macaddr(ah);
 611         if (r) {
 612                 ath_print(common, ATH_DBG_FATAL,
 613                           "Failed to initialize MAC address\n");
 614                 return r;
 615         }
 616
 617         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 618                 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 619         else
 620                 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 621
 622         if (AR_SREV_9300_20_OR_LATER(ah))
 623                 ar9003_hw_set_nf_limits(ah);
 624
 625         ath9k_init_nfcal_hist_buffer(ah);
 626         ah->bb_watchdog_timeout_ms = 25;
 627
 628         common->state = ATH_HW_INITIALIZED;
 629
 630         return 0;
 631 }
 632
 633 int ath9k_hw_init(struct ath_hw *ah)
 634 {
 635         int ret;
 636         struct ath_common *common = ath9k_hw_common(ah);
 637
 638         /* These are all the AR5008/AR9001/AR9002 hardware family of chipsets */
 639         switch (ah->hw_version.devid) {
 640         case AR5416_DEVID_PCI:
 641         case AR5416_DEVID_PCIE:
 642         case AR5416_AR9100_DEVID:
 643         case AR9160_DEVID_PCI:
 644         case AR9280_DEVID_PCI:
 645         case AR9280_DEVID_PCIE:
 646         case AR9285_DEVID_PCIE:
 647         case AR9287_DEVID_PCI:
 648         case AR9287_DEVID_PCIE:
 649         case AR2427_DEVID_PCIE:
 650         case AR9300_DEVID_PCIE:
 651                 break;
 652         default:
 653                 if (common->bus_ops->ath_bus_type == ATH_USB)
 654                         break;
 655                 ath_print(common, ATH_DBG_FATAL,
 656                           "Hardware device ID 0x%04x not supported\n",
 657                           ah->hw_version.devid);
 658                 return -EOPNOTSUPP;
 659         }
 660
 661         ret = __ath9k_hw_init(ah);
 662         if (ret) {
 663                 ath_print(common, ATH_DBG_FATAL,
 664                           "Unable to initialize hardware; "
 665                           "initialization status: %d\n", ret);
 666                 return ret;
 667         }
 668
 669         return 0;
 670 }
 671 EXPORT_SYMBOL(ath9k_hw_init);
 672
 673 static void ath9k_hw_init_qos(struct ath_hw *ah)
 674 {
 675         ENABLE_REGWRITE_BUFFER(ah);
 676
 677         REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 678         REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 679
 680         REG_WRITE(ah, AR_QOS_NO_ACK,
 681                   SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 682                   SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 683                   SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 684
 685         REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 686         REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 687         REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 688         REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 689         REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 690
 691         REGWRITE_BUFFER_FLUSH(ah);
 692         DISABLE_REGWRITE_BUFFER(ah);
 693 }
 694
 695 static void ath9k_hw_init_pll(struct ath_hw *ah,
 696                               struct ath9k_channel *chan)
 697 {
 698         u32 pll = ath9k_hw_compute_pll_control(ah, chan);
 699
 700         REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
 701
 702         /* Switch the core clock for ar9271 to 117Mhz */
 703         if (AR_SREV_9271(ah)) {
 704                 udelay(500);
 705                 REG_WRITE(ah, 0x50040, 0x304);
 706         }
 707
 708         udelay(RTC_PLL_SETTLE_DELAY);
 709
 710         REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
 711 }
 712
 713 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 714                                           enum nl80211_iftype opmode)
 715 {
 716         u32 imr_reg = AR_IMR_TXERR |
 717                 AR_IMR_TXURN |
 718                 AR_IMR_RXERR |
 719                 AR_IMR_RXORN |
 720                 AR_IMR_BCNMISC;
 721
 722         if (AR_SREV_9300_20_OR_LATER(ah)) {
 723                 imr_reg |= AR_IMR_RXOK_HP;
 724                 if (ah->config.rx_intr_mitigation)
 725                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 726                 else
 727                         imr_reg |= AR_IMR_RXOK_LP;
 728
 729         } else {
 730                 if (ah->config.rx_intr_mitigation)
 731                         imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 732                 else
 733                         imr_reg |= AR_IMR_RXOK;
 734         }
 735
 736         if (ah->config.tx_intr_mitigation)
 737                 imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
 738         else
 739                 imr_reg |= AR_IMR_TXOK;
 740
 741         if (opmode == NL80211_IFTYPE_AP)
 742                 imr_reg |= AR_IMR_MIB;
 743
 744         ENABLE_REGWRITE_BUFFER(ah);
 745
 746         REG_WRITE(ah, AR_IMR, imr_reg);
 747         ah->imrs2_reg |= AR_IMR_S2_GTT;
 748         REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 749
 750         if (!AR_SREV_9100(ah)) {
 751                 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
 752                 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
 753                 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
 754         }
 755
 756         REGWRITE_BUFFER_FLUSH(ah);
 757         DISABLE_REGWRITE_BUFFER(ah);
 758
 759         if (AR_SREV_9300_20_OR_LATER(ah)) {
 760                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE, 0);
 761                 REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK, 0);
 762                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE, 0);
 763                 REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK, 0);
 764         }
 765 }
 766
 767 static void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
 768 {
 769         u32 val = ath9k_hw_mac_to_clks(ah, us);
 770         val = min(val, (u32) 0xFFFF);
 771         REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
 772 }
 773
 774 static void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
 775 {
 776         u32 val = ath9k_hw_mac_to_clks(ah, us);
 777         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
 778         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
 779 }
 780
 781 static void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
 782 {
 783         u32 val = ath9k_hw_mac_to_clks(ah, us);
 784         val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
 785         REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
 786 }
 787
 788 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
 789 {
 790         if (tu > 0xFFFF) {
 791                 ath_print(ath9k_hw_common(ah), ATH_DBG_XMIT,
 792                           "bad global tx timeout %u\n", tu);
 793                 ah->globaltxtimeout = (u32) -1;
 794                 return false;
 795         } else {
 796                 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
 797                 ah->globaltxtimeout = tu;
 798                 return true;
 799         }
 800 }
 801
 802 void ath9k_hw_init_global_settings(struct ath_hw *ah)
 803 {
 804         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
 805         int acktimeout;
 806         int slottime;
 807         int sifstime;
 808
 809         ath_print(ath9k_hw_common(ah), ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
 810                   ah->misc_mode);
 811
 812         if (ah->misc_mode != 0)
 813                 REG_WRITE(ah, AR_PCU_MISC,
 814                           REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
 815
 816         if (conf->channel && conf->channel->band == IEEE80211_BAND_5GHZ)
 817                 sifstime = 16;
 818         else
 819                 sifstime = 10;
 820
 821         /* As defined by IEEE 802.11-2007 17.3.8.6 */
 822         slottime = ah->slottime + 3 * ah->coverage_class;
 823         acktimeout = slottime + sifstime;
 824
 825         /*
 826          * Workaround for early ACK timeouts, add an offset to match the
 827          * initval's 64us ack timeout value.
 828          * This was initially only meant to work around an issue with delayed
 829          * BA frames in some implementations, but it has been found to fix ACK
 830          * timeout issues in other cases as well.
 831          */
 832         if (conf->channel && conf->channel->band == IEEE80211_BAND_2GHZ)
 833                 acktimeout += 64 - sifstime - ah->slottime;
 834
 835         ath9k_hw_setslottime(ah, slottime);
 836         ath9k_hw_set_ack_timeout(ah, acktimeout);
 837         ath9k_hw_set_cts_timeout(ah, acktimeout);
 838         if (ah->globaltxtimeout != (u32) -1)
 839                 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
 840 }
 841 EXPORT_SYMBOL(ath9k_hw_init_global_settings);
 842
 843 void ath9k_hw_deinit(struct ath_hw *ah)
 844 {
 845         struct ath_common *common = ath9k_hw_common(ah);
 846
 847         if (common->state < ATH_HW_INITIALIZED)
 848                 goto free_hw;
 849
 850         ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
 851
 852 free_hw:
 853         ath9k_hw_rf_free_ext_banks(ah);
 854 }
 855 EXPORT_SYMBOL(ath9k_hw_deinit);
 856
 857 /*******/
 858 /* INI */
 859 /*******/
 860
 861 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 862 {
 863         u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
 864
 865         if (IS_CHAN_B(chan))
 866                 ctl |= CTL_11B;
 867         else if (IS_CHAN_G(chan))
 868                 ctl |= CTL_11G;
 869         else
 870                 ctl |= CTL_11A;
 871
 872         return ctl;
 873 }
 874
 875 /****************************************/
 876 /* Reset and Channel Switching Routines */
 877 /****************************************/
 878
 879 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 880 {
 881         struct ath_common *common = ath9k_hw_common(ah);
 882         u32 regval;
 883
 884         ENABLE_REGWRITE_BUFFER(ah);
 885
 886         /*
 887          * set AHB_MODE not to do cacheline prefetches
 888         */
 889         if (!AR_SREV_9300_20_OR_LATER(ah)) {
 890                 regval = REG_READ(ah, AR_AHB_MODE);
 891                 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
 892         }
 893
 894         /*
 895          * let mac dma reads be in 128 byte chunks
 896          */
 897         regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
 898         REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
 899
 900         REGWRITE_BUFFER_FLUSH(ah);
 901         DISABLE_REGWRITE_BUFFER(ah);
 902
 903         /*
 904          * Restore TX Trigger Level to its pre-reset value.
 905          * The initial value depends on whether aggregation is enabled, and is
 906          * adjusted whenever underruns are detected.
 907          */
 908         if (!AR_SREV_9300_20_OR_LATER(ah))
 909                 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
 910
 911         ENABLE_REGWRITE_BUFFER(ah);
 912
 913         /*
 914          * let mac dma writes be in 128 byte chunks
 915          */
 916         regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
 917         REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
 918
 919         /*
 920          * Setup receive FIFO threshold to hold off TX activities
 921          */
 922         REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
 923
 924         if (AR_SREV_9300_20_OR_LATER(ah)) {
 925                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
 926                 REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
 927
 928                 ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
 929                         ah->caps.rx_status_len);
 930         }
 931
 932         /*
 933          * reduce the number of usable entries in PCU TXBUF to avoid
 934          * wrap around issues.
 935          */
 936         if (AR_SREV_9285(ah)) {
 937                 /* For AR9285 the number of Fifos are reduced to half.
 938                  * So set the usable tx buf size also to half to
 939                  * avoid data/delimiter underruns
 940                  */
 941                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 942                           AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
 943         } else if (!AR_SREV_9271(ah)) {
 944                 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
 945                           AR_PCU_TXBUF_CTRL_USABLE_SIZE);
 946         }
 947
 948         REGWRITE_BUFFER_FLUSH(ah);
 949         DISABLE_REGWRITE_BUFFER(ah);
 950
 951         if (AR_SREV_9300_20_OR_LATER(ah))
 952                 ath9k_hw_reset_txstatus_ring(ah);
 953 }
 954
 955 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
 956 {
 957         u32 val;
 958
 959         val = REG_READ(ah, AR_STA_ID1);
 960         val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
 961         switch (opmode) {
 962         case NL80211_IFTYPE_AP:
 963                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
 964                           | AR_STA_ID1_KSRCH_MODE);
 965                 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 966                 break;
 967         case NL80211_IFTYPE_ADHOC:
 968         case NL80211_IFTYPE_MESH_POINT:
 969                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
 970                           | AR_STA_ID1_KSRCH_MODE);
 971                 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
 972                 break;
 973         case NL80211_IFTYPE_STATION:
 974         case NL80211_IFTYPE_MONITOR:
 975                 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
 976                 break;
 977         }
 978 }
 979
 980 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
 981                                    u32 *coef_mantissa, u32 *coef_exponent)
 982 {
 983         u32 coef_exp, coef_man;
 984
 985         for (coef_exp = 31; coef_exp > 0; coef_exp--)
 986                 if ((coef_scaled >> coef_exp) & 0x1)
 987                         break;
 988
 989         coef_exp = 14 - (coef_exp - COEF_SCALE_S);
 990
 991         coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
 992
 993         *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
 994         *coef_exponent = coef_exp - 16;
 995 }
 996
 997 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
 998 {
 999         u32 rst_flags;
1000         u32 tmpReg;
1001
1002         if (AR_SREV_9100(ah)) {
1003                 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1004                 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1005                 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1006                 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1007                 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1008         }
1009
1010         ENABLE_REGWRITE_BUFFER(ah);
1011
1012         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1013                   AR_RTC_FORCE_WAKE_ON_INT);
1014
1015         if (AR_SREV_9100(ah)) {
1016                 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1017                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1018         } else {
1019                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1020                 if (tmpReg &
1021                     (AR_INTR_SYNC_LOCAL_TIMEOUT |
1022                      AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1023                         u32 val;
1024                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1025
1026                         val = AR_RC_HOSTIF;
1027                         if (!AR_SREV_9300_20_OR_LATER(ah))
1028                                 val |= AR_RC_AHB;
1029                         REG_WRITE(ah, AR_RC, val);
1030
1031                 } else if (!AR_SREV_9300_20_OR_LATER(ah))
1032                         REG_WRITE(ah, AR_RC, AR_RC_AHB);
1033
1034                 rst_flags = AR_RTC_RC_MAC_WARM;
1035                 if (type == ATH9K_RESET_COLD)
1036                         rst_flags |= AR_RTC_RC_MAC_COLD;
1037         }
1038
1039         REG_WRITE(ah, AR_RTC_RC, rst_flags);
1040
1041         REGWRITE_BUFFER_FLUSH(ah);
1042         DISABLE_REGWRITE_BUFFER(ah);
1043
1044         udelay(50);
1045
1046         REG_WRITE(ah, AR_RTC_RC, 0);
1047         if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1048                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1049                           "RTC stuck in MAC reset\n");
1050                 return false;
1051         }
1052
1053         if (!AR_SREV_9100(ah))
1054                 REG_WRITE(ah, AR_RC, 0);
1055
1056         if (AR_SREV_9100(ah))
1057                 udelay(50);
1058
1059         return true;
1060 }
1061
1062 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1063 {
1064         ENABLE_REGWRITE_BUFFER(ah);
1065
1066         REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1067                   AR_RTC_FORCE_WAKE_ON_INT);
1068
1069         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1070                 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1071
1072         REG_WRITE(ah, AR_RTC_RESET, 0);
1073
1074         REGWRITE_BUFFER_FLUSH(ah);
1075         DISABLE_REGWRITE_BUFFER(ah);
1076
1077         if (!AR_SREV_9300_20_OR_LATER(ah))
1078                 udelay(2);
1079
1080         if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1081                 REG_WRITE(ah, AR_RC, 0);
1082
1083         REG_WRITE(ah, AR_RTC_RESET, 1);
1084
1085         if (!ath9k_hw_wait(ah,
1086                            AR_RTC_STATUS,
1087                            AR_RTC_STATUS_M,
1088                            AR_RTC_STATUS_ON,
1089                            AH_WAIT_TIMEOUT)) {
1090                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
1091                           "RTC not waking up\n");
1092                 return false;
1093         }
1094
1095         ath9k_hw_read_revisions(ah);
1096
1097         return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1098 }
1099
1100 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1101 {
1102         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1103                   AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1104
1105         switch (type) {
1106         case ATH9K_RESET_POWER_ON:
1107                 return ath9k_hw_set_reset_power_on(ah);
1108         case ATH9K_RESET_WARM:
1109         case ATH9K_RESET_COLD:
1110                 return ath9k_hw_set_reset(ah, type);
1111         default:
1112                 return false;
1113         }
1114 }
1115
1116 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1117                                 struct ath9k_channel *chan)
1118 {
1119         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) {
1120                 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1121                         return false;
1122         } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1123                 return false;
1124
1125         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1126                 return false;
1127
1128         ah->chip_fullsleep = false;
1129         ath9k_hw_init_pll(ah, chan);
1130         ath9k_hw_set_rfmode(ah, chan);
1131
1132         return true;
1133 }
1134
1135 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1136                                     struct ath9k_channel *chan)
1137 {
1138         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
1139         struct ath_common *common = ath9k_hw_common(ah);
1140         struct ieee80211_channel *channel = chan->chan;
1141         u32 qnum;
1142         int r;
1143
1144         for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1145                 if (ath9k_hw_numtxpending(ah, qnum)) {
1146                         ath_print(common, ATH_DBG_QUEUE,
1147                                   "Transmit frames pending on "
1148                                   "queue %d\n", qnum);
1149                         return false;
1150                 }
1151         }
1152
1153         if (!ath9k_hw_rfbus_req(ah)) {
1154                 ath_print(common, ATH_DBG_FATAL,
1155                           "Could not kill baseband RX\n");
1156                 return false;
1157         }
1158
1159         ath9k_hw_set_channel_regs(ah, chan);
1160
1161         r = ath9k_hw_rf_set_freq(ah, chan);
1162         if (r) {
1163                 ath_print(common, ATH_DBG_FATAL,
1164                           "Failed to set channel\n");
1165                 return false;
1166         }
1167
1168         ah->eep_ops->set_txpower(ah, chan,
1169                              ath9k_regd_get_ctl(regulatory, chan),
1170                              channel->max_antenna_gain * 2,
1171                              channel->max_power * 2,
1172                              min((u32) MAX_RATE_POWER,
1173                              (u32) regulatory->power_limit));
1174
1175         ath9k_hw_rfbus_done(ah);
1176
1177         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1178                 ath9k_hw_set_delta_slope(ah, chan);
1179
1180         ath9k_hw_spur_mitigate_freq(ah, chan);
1181
1182         if (!chan->oneTimeCalsDone)
1183                 chan->oneTimeCalsDone = true;
1184
1185         return true;
1186 }
1187
1188 bool ath9k_hw_check_alive(struct ath_hw *ah)
1189 {
1190         int count = 50;
1191         u32 reg;
1192
1193         if (AR_SREV_9285_10_OR_LATER(ah))
1194                 return true;
1195
1196         do {
1197                 reg = REG_READ(ah, AR_OBS_BUS_1);
1198
1199                 if ((reg & 0x7E7FFFEF) == 0x00702400)
1200                         continue;
1201
1202                 switch (reg & 0x7E000B00) {
1203                 case 0x1E000000:
1204                 case 0x52000B00:
1205                 case 0x18000B00:
1206                         continue;
1207                 default:
1208                         return true;
1209                 }
1210         } while (count-- > 0);
1211
1212         return false;
1213 }
1214 EXPORT_SYMBOL(ath9k_hw_check_alive);
1215
1216 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1217                     bool bChannelChange)
1218 {
1219         struct ath_common *common = ath9k_hw_common(ah);
1220         u32 saveLedState;
1221         struct ath9k_channel *curchan = ah->curchan;
1222         u32 saveDefAntenna;
1223         u32 macStaId1;
1224         u64 tsf = 0;
1225         int i, r;
1226
1227         ah->txchainmask = common->tx_chainmask;
1228         ah->rxchainmask = common->rx_chainmask;
1229
1230         if (!ah->chip_fullsleep) {
1231                 ath9k_hw_abortpcurecv(ah);
1232                 if (!ath9k_hw_stopdmarecv(ah))
1233                         ath_print(common, ATH_DBG_XMIT,
1234                                 "Failed to stop receive dma\n");
1235         }
1236
1237         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1238                 return -EIO;
1239
1240         if (curchan && !ah->chip_fullsleep)
1241                 ath9k_hw_getnf(ah, curchan);
1242
1243         if (bChannelChange &&
1244             (ah->chip_fullsleep != true) &&
1245             (ah->curchan != NULL) &&
1246             (chan->channel != ah->curchan->channel) &&
1247             ((chan->channelFlags & CHANNEL_ALL) ==
1248              (ah->curchan->channelFlags & CHANNEL_ALL)) &&
1249             !AR_SREV_9280(ah)) {
1250
1251                 if (ath9k_hw_channel_change(ah, chan)) {
1252                         ath9k_hw_loadnf(ah, ah->curchan);
1253                         ath9k_hw_start_nfcal(ah);
1254                         return 0;
1255                 }
1256         }
1257
1258         saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1259         if (saveDefAntenna == 0)
1260                 saveDefAntenna = 1;
1261
1262         macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1263
1264         /* For chips on which RTC reset is done, save TSF before it gets cleared */
1265         if (AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1266                 tsf = ath9k_hw_gettsf64(ah);
1267
1268         saveLedState = REG_READ(ah, AR_CFG_LED) &
1269                 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1270                  AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1271
1272         ath9k_hw_mark_phy_inactive(ah);
1273
1274         /* Only required on the first reset */
1275         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1276                 REG_WRITE(ah,
1277                           AR9271_RESET_POWER_DOWN_CONTROL,
1278                           AR9271_RADIO_RF_RST);
1279                 udelay(50);
1280         }
1281
1282         if (!ath9k_hw_chip_reset(ah, chan)) {
1283                 ath_print(common, ATH_DBG_FATAL, "Chip reset failed\n");
1284                 return -EINVAL;
1285         }
1286
1287         /* Only required on the first reset */
1288         if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1289                 ah->htc_reset_init = false;
1290                 REG_WRITE(ah,
1291                           AR9271_RESET_POWER_DOWN_CONTROL,
1292                           AR9271_GATE_MAC_CTL);
1293                 udelay(50);
1294         }
1295
1296         /* Restore TSF */
1297         if (tsf && AR_SREV_9280(ah) && ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1298                 ath9k_hw_settsf64(ah, tsf);
1299
1300         if (AR_SREV_9280_10_OR_LATER(ah))
1301                 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
1302
1303         if (!AR_SREV_9300_20_OR_LATER(ah))
1304                 ar9002_hw_enable_async_fifo(ah);
1305
1306         r = ath9k_hw_process_ini(ah, chan);
1307         if (r)
1308                 return r;
1309
1310         /* Setup MFP options for CCMP */
1311         if (AR_SREV_9280_20_OR_LATER(ah)) {
1312                 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1313                  * frames when constructing CCMP AAD. */
1314                 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1315                               0xc7ff);
1316                 ah->sw_mgmt_crypto = false;
1317         } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1318                 /* Disable hardware crypto for management frames */
1319                 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1320                             AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1321                 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1322                             AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1323                 ah->sw_mgmt_crypto = true;
1324         } else
1325                 ah->sw_mgmt_crypto = true;
1326
1327         if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1328                 ath9k_hw_set_delta_slope(ah, chan);
1329
1330         ath9k_hw_spur_mitigate_freq(ah, chan);
1331         ah->eep_ops->set_board_values(ah, chan);
1332
1333         ath9k_hw_set_operating_mode(ah, ah->opmode);
1334
1335         ENABLE_REGWRITE_BUFFER(ah);
1336
1337         REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(common->macaddr));
1338         REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(common->macaddr + 4)
1339                   | macStaId1
1340                   | AR_STA_ID1_RTS_USE_DEF
1341                   | (ah->config.
1342                      ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
1343                   | ah->sta_id1_defaults);
1344         ath_hw_setbssidmask(common);
1345         REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1346         ath9k_hw_write_associd(ah);
1347         REG_WRITE(ah, AR_ISR, ~0);
1348         REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1349
1350         REGWRITE_BUFFER_FLUSH(ah);
1351         DISABLE_REGWRITE_BUFFER(ah);
1352
1353         r = ath9k_hw_rf_set_freq(ah, chan);
1354         if (r)
1355                 return r;
1356
1357         ENABLE_REGWRITE_BUFFER(ah);
1358
1359         for (i = 0; i < AR_NUM_DCU; i++)
1360                 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1361
1362         REGWRITE_BUFFER_FLUSH(ah);
1363         DISABLE_REGWRITE_BUFFER(ah);
1364
1365         ah->intr_txqs = 0;
1366         for (i = 0; i < ah->caps.total_queues; i++)
1367                 ath9k_hw_resettxqueue(ah, i);
1368
1369         ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1370         ath9k_hw_ani_cache_ini_regs(ah);
1371         ath9k_hw_init_qos(ah);
1372
1373         if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1374                 ath9k_enable_rfkill(ah);
1375
1376         ath9k_hw_init_global_settings(ah);
1377
1378         if (!AR_SREV_9300_20_OR_LATER(ah)) {
1379                 ar9002_hw_update_async_fifo(ah);
1380                 ar9002_hw_enable_wep_aggregation(ah);
1381         }
1382
1383         REG_WRITE(ah, AR_STA_ID1,
1384                   REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
1385
1386         ath9k_hw_set_dma(ah);
1387
1388         REG_WRITE(ah, AR_OBS, 8);
1389
1390         if (ah->config.rx_intr_mitigation) {
1391                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
1392                 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
1393         }
1394
1395         if (ah->config.tx_intr_mitigation) {
1396                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
1397                 REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
1398         }
1399
1400         ath9k_hw_init_bb(ah, chan);
1401
1402         if (!ath9k_hw_init_cal(ah, chan))
1403                 return -EIO;
1404
1405         ENABLE_REGWRITE_BUFFER(ah);
1406
1407         ath9k_hw_restore_chainmask(ah);
1408         REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
1409
1410         REGWRITE_BUFFER_FLUSH(ah);
1411         DISABLE_REGWRITE_BUFFER(ah);
1412
1413         /*
1414          * For big endian systems turn on swapping for descriptors
1415          */
1416         if (AR_SREV_9100(ah)) {
1417                 u32 mask;
1418                 mask = REG_READ(ah, AR_CFG);
1419                 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1420                         ath_print(common, ATH_DBG_RESET,
1421                                 "CFG Byte Swap Set 0x%x\n", mask);
1422                 } else {
1423                         mask =
1424                                 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1425                         REG_WRITE(ah, AR_CFG, mask);
1426                         ath_print(common, ATH_DBG_RESET,
1427                                 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
1428                 }
1429         } else {
1430                 if (common->bus_ops->ath_bus_type == ATH_USB) {
1431                         /* Configure AR9271 target WLAN */
1432                         if (AR_SREV_9271(ah))
1433                                 REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1434                         else
1435                                 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1436                 }
1437 #ifdef __BIG_ENDIAN
1438                 else
1439                         REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1440 #endif
1441         }
1442
1443         if (ah->btcoex_hw.enabled)
1444                 ath9k_hw_btcoex_enable(ah);
1445
1446         if (AR_SREV_9300_20_OR_LATER(ah)) {
1447                 ath9k_hw_loadnf(ah, curchan);
1448                 ath9k_hw_start_nfcal(ah);
1449                 ar9003_hw_bb_watchdog_config(ah);
1450         }
1451
1452         return 0;
1453 }
1454 EXPORT_SYMBOL(ath9k_hw_reset);
1455
1456 /************************/
1457 /* Key Cache Management */
1458 /************************/
1459
1460 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
1461 {
1462         u32 keyType;
1463
1464         if (entry >= ah->caps.keycache_size) {
1465                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1466                           "keychache entry %u out of range\n", entry);
1467                 return false;
1468         }
1469
1470         keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
1471
1472         REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
1473         REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
1474         REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
1475         REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
1476         REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
1477         REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
1478         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
1479         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
1480
1481         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1482                 u16 micentry = entry + 64;
1483
1484                 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
1485                 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1486                 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
1487                 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1488
1489         }
1490
1491         return true;
1492 }
1493 EXPORT_SYMBOL(ath9k_hw_keyreset);
1494
1495 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
1496 {
1497         u32 macHi, macLo;
1498         u32 unicast_flag = AR_KEYTABLE_VALID;
1499
1500         if (entry >= ah->caps.keycache_size) {
1501                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1502                           "keychache entry %u out of range\n", entry);
1503                 return false;
1504         }
1505
1506         if (mac != NULL) {
1507                 /*
1508                  * AR_KEYTABLE_VALID indicates that the address is a unicast
1509                  * address, which must match the transmitter address for
1510                  * decrypting frames.
1511                  * Not setting this bit allows the hardware to use the key
1512                  * for multicast frame decryption.
1513                  */
1514                 if (mac[0] & 0x01)
1515                         unicast_flag = 0;
1516
1517                 macHi = (mac[5] << 8) | mac[4];
1518                 macLo = (mac[3] << 24) |
1519                         (mac[2] << 16) |
1520                         (mac[1] << 8) |
1521                         mac[0];
1522                 macLo >>= 1;
1523                 macLo |= (macHi & 1) << 31;
1524                 macHi >>= 1;
1525         } else {
1526                 macLo = macHi = 0;
1527         }
1528         REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
1529         REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | unicast_flag);
1530
1531         return true;
1532 }
1533 EXPORT_SYMBOL(ath9k_hw_keysetmac);
1534
1535 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
1536                                  const struct ath9k_keyval *k,
1537                                  const u8 *mac)
1538 {
1539         const struct ath9k_hw_capabilities *pCap = &ah->caps;
1540         struct ath_common *common = ath9k_hw_common(ah);
1541         u32 key0, key1, key2, key3, key4;
1542         u32 keyType;
1543
1544         if (entry >= pCap->keycache_size) {
1545                 ath_print(common, ATH_DBG_FATAL,
1546                           "keycache entry %u out of range\n", entry);
1547                 return false;
1548         }
1549
1550         switch (k->kv_type) {
1551         case ATH9K_CIPHER_AES_OCB:
1552                 keyType = AR_KEYTABLE_TYPE_AES;
1553                 break;
1554         case ATH9K_CIPHER_AES_CCM:
1555                 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
1556                         ath_print(common, ATH_DBG_ANY,
1557                                   "AES-CCM not supported by mac rev 0x%x\n",
1558                                   ah->hw_version.macRev);
1559                         return false;
1560                 }
1561                 keyType = AR_KEYTABLE_TYPE_CCM;
1562                 break;
1563         case ATH9K_CIPHER_TKIP:
1564                 keyType = AR_KEYTABLE_TYPE_TKIP;
1565                 if (ATH9K_IS_MIC_ENABLED(ah)
1566                     && entry + 64 >= pCap->keycache_size) {
1567                         ath_print(common, ATH_DBG_ANY,
1568                                   "entry %u inappropriate for TKIP\n", entry);
1569                         return false;
1570                 }
1571                 break;
1572         case ATH9K_CIPHER_WEP:
1573                 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
1574                         ath_print(common, ATH_DBG_ANY,
1575                                   "WEP key length %u too small\n", k->kv_len);
1576                         return false;
1577                 }
1578                 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
1579                         keyType = AR_KEYTABLE_TYPE_40;
1580                 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1581                         keyType = AR_KEYTABLE_TYPE_104;
1582                 else
1583                         keyType = AR_KEYTABLE_TYPE_128;
1584                 break;
1585         case ATH9K_CIPHER_CLR:
1586                 keyType = AR_KEYTABLE_TYPE_CLR;
1587                 break;
1588         default:
1589                 ath_print(common, ATH_DBG_FATAL,
1590                           "cipher %u not supported\n", k->kv_type);
1591                 return false;
1592         }
1593
1594         key0 = get_unaligned_le32(k->kv_val + 0);
1595         key1 = get_unaligned_le16(k->kv_val + 4);
1596         key2 = get_unaligned_le32(k->kv_val + 6);
1597         key3 = get_unaligned_le16(k->kv_val + 10);
1598         key4 = get_unaligned_le32(k->kv_val + 12);
1599         if (k->kv_len <= WLAN_KEY_LEN_WEP104)
1600                 key4 &= 0xff;
1601
1602         /*
1603          * Note: Key cache registers access special memory area that requires
1604          * two 32-bit writes to actually update the values in the internal
1605          * memory. Consequently, the exact order and pairs used here must be
1606          * maintained.
1607          */
1608
1609         if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
1610                 u16 micentry = entry + 64;
1611
1612                 /*
1613                  * Write inverted key[47:0] first to avoid Michael MIC errors
1614                  * on frames that could be sent or received at the same time.
1615                  * The correct key will be written in the end once everything
1616                  * else is ready.
1617                  */
1618                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
1619                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
1620
1621                 /* Write key[95:48] */
1622                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1623                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1624
1625                 /* Write key[127:96] and key type */
1626                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1627                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1628
1629                 /* Write MAC address for the entry */
1630                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1631
1632                 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
1633                         /*
1634                          * TKIP uses two key cache entries:
1635                          * Michael MIC TX/RX keys in the same key cache entry
1636                          * (idx = main index + 64):
1637                          * key0 [31:0] = RX key [31:0]
1638                          * key1 [15:0] = TX key [31:16]
1639                          * key1 [31:16] = reserved
1640                          * key2 [31:0] = RX key [63:32]
1641                          * key3 [15:0] = TX key [15:0]
1642                          * key3 [31:16] = reserved
1643                          * key4 [31:0] = TX key [63:32]
1644                          */
1645                         u32 mic0, mic1, mic2, mic3, mic4;
1646
1647                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1648                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1649                         mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
1650                         mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
1651                         mic4 = get_unaligned_le32(k->kv_txmic + 4);
1652
1653                         /* Write RX[31:0] and TX[31:16] */
1654                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1655                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
1656
1657                         /* Write RX[63:32] and TX[15:0] */
1658                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1659                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
1660
1661                         /* Write TX[63:32] and keyType(reserved) */
1662                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
1663                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1664                                   AR_KEYTABLE_TYPE_CLR);
1665
1666                 } else {
1667                         /*
1668                          * TKIP uses four key cache entries (two for group
1669                          * keys):
1670                          * Michael MIC TX/RX keys are in different key cache
1671                          * entries (idx = main index + 64 for TX and
1672                          * main index + 32 + 96 for RX):
1673                          * key0 [31:0] = TX/RX MIC key [31:0]
1674                          * key1 [31:0] = reserved
1675                          * key2 [31:0] = TX/RX MIC key [63:32]
1676                          * key3 [31:0] = reserved
1677                          * key4 [31:0] = reserved
1678                          *
1679                          * Upper layer code will call this function separately
1680                          * for TX and RX keys when these registers offsets are
1681                          * used.
1682                          */
1683                         u32 mic0, mic2;
1684
1685                         mic0 = get_unaligned_le32(k->kv_mic + 0);
1686                         mic2 = get_unaligned_le32(k->kv_mic + 4);
1687
1688                         /* Write MIC key[31:0] */
1689                         REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
1690                         REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
1691
1692                         /* Write MIC key[63:32] */
1693                         REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
1694                         REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
1695
1696                         /* Write TX[63:32] and keyType(reserved) */
1697                         REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
1698                         REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
1699                                   AR_KEYTABLE_TYPE_CLR);
1700                 }
1701
1702                 /* MAC address registers are reserved for the MIC entry */
1703                 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
1704                 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
1705
1706                 /*
1707                  * Write the correct (un-inverted) key[47:0] last to enable
1708                  * TKIP now that all other registers are set with correct
1709                  * values.
1710                  */
1711                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1712                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1713         } else {
1714                 /* Write key[47:0] */
1715                 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
1716                 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
1717
1718                 /* Write key[95:48] */
1719                 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
1720                 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
1721
1722                 /* Write key[127:96] and key type */
1723                 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
1724                 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
1725
1726                 /* Write MAC address for the entry */
1727                 (void) ath9k_hw_keysetmac(ah, entry, mac);
1728         }
1729
1730         return true;
1731 }
1732 EXPORT_SYMBOL(ath9k_hw_set_keycache_entry);
1733
1734 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
1735 {
1736         if (entry < ah->caps.keycache_size) {
1737                 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
1738                 if (val & AR_KEYTABLE_VALID)
1739                         return true;
1740         }
1741         return false;
1742 }
1743 EXPORT_SYMBOL(ath9k_hw_keyisvalid);
1744
1745 /******************************/
1746 /* Power Management (Chipset) */
1747 /******************************/
1748
1749 /*
1750  * Notify Power Mgt is disabled in self-generated frames.
1751  * If requested, force chip to sleep.
1752  */
1753 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
1754 {
1755         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1756         if (setChip) {
1757                 /*
1758                  * Clear the RTC force wake bit to allow the
1759                  * mac to go to sleep.
1760                  */
1761                 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1762                             AR_RTC_FORCE_WAKE_EN);
1763                 if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1764                         REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1765
1766                 /* Shutdown chip. Active low */
1767                 if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah))
1768                         REG_CLR_BIT(ah, (AR_RTC_RESET),
1769                                     AR_RTC_RESET_EN);
1770         }
1771 }
1772
1773 /*
1774  * Notify Power Management is enabled in self-generating
1775  * frames. If request, set power mode of chip to
1776  * auto/normal.  Duration in units of 128us (1/8 TU).
1777  */
1778 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
1779 {
1780         REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1781         if (setChip) {
1782                 struct ath9k_hw_capabilities *pCap = &ah->caps;
1783
1784                 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
1785                         /* Set WakeOnInterrupt bit; clear ForceWake bit */
1786                         REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1787                                   AR_RTC_FORCE_WAKE_ON_INT);
1788                 } else {
1789                         /*
1790                          * Clear the RTC force wake bit to allow the
1791                          * mac to go to sleep.
1792                          */
1793                         REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
1794                                     AR_RTC_FORCE_WAKE_EN);
1795                 }
1796         }
1797 }
1798
1799 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
1800 {
1801         u32 val;
1802         int i;
1803
1804         if (setChip) {
1805                 if ((REG_READ(ah, AR_RTC_STATUS) &
1806                      AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
1807                         if (ath9k_hw_set_reset_reg(ah,
1808                                            ATH9K_RESET_POWER_ON) != true) {
1809                                 return false;
1810                         }
1811                         if (!AR_SREV_9300_20_OR_LATER(ah))
1812                                 ath9k_hw_init_pll(ah, NULL);
1813                 }
1814                 if (AR_SREV_9100(ah))
1815                         REG_SET_BIT(ah, AR_RTC_RESET,
1816                                     AR_RTC_RESET_EN);
1817
1818                 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1819                             AR_RTC_FORCE_WAKE_EN);
1820                 udelay(50);
1821
1822                 for (i = POWER_UP_TIME / 50; i > 0; i--) {
1823                         val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
1824                         if (val == AR_RTC_STATUS_ON)
1825                                 break;
1826                         udelay(50);
1827                         REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
1828                                     AR_RTC_FORCE_WAKE_EN);
1829                 }
1830                 if (i == 0) {
1831                         ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
1832                                   "Failed to wakeup in %uus\n",
1833                                   POWER_UP_TIME / 20);
1834                         return false;
1835                 }
1836         }
1837
1838         REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
1839
1840         return true;
1841 }
1842
1843 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
1844 {
1845         struct ath_common *common = ath9k_hw_common(ah);
1846         int status = true, setChip = true;
1847         static const char *modes[] = {
1848                 "AWAKE",
1849                 "FULL-SLEEP",
1850                 "NETWORK SLEEP",
1851                 "UNDEFINED"
1852         };
1853
1854         if (ah->power_mode == mode)
1855                 return status;
1856
1857         ath_print(common, ATH_DBG_RESET, "%s -> %s\n",
1858                   modes[ah->power_mode], modes[mode]);
1859
1860         switch (mode) {
1861         case ATH9K_PM_AWAKE:
1862                 status = ath9k_hw_set_power_awake(ah, setChip);
1863                 break;
1864         case ATH9K_PM_FULL_SLEEP:
1865                 ath9k_set_power_sleep(ah, setChip);
1866                 ah->chip_fullsleep = true;
1867                 break;
1868         case ATH9K_PM_NETWORK_SLEEP:
1869                 ath9k_set_power_network_sleep(ah, setChip);
1870                 break;
1871         default:
1872                 ath_print(common, ATH_DBG_FATAL,
1873                           "Unknown power mode %u\n", mode);
1874                 return false;
1875         }
1876         ah->power_mode = mode;
1877
1878         return status;
1879 }
1880 EXPORT_SYMBOL(ath9k_hw_setpower);
1881
1882 /*******************/
1883 /* Beacon Handling */
1884 /*******************/
1885
1886 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
1887 {
1888         int flags = 0;
1889
1890         ah->beacon_interval = beacon_period;
1891
1892         ENABLE_REGWRITE_BUFFER(ah);
1893
1894         switch (ah->opmode) {
1895         case NL80211_IFTYPE_STATION:
1896         case NL80211_IFTYPE_MONITOR:
1897                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1898                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
1899                 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
1900                 flags |= AR_TBTT_TIMER_EN;
1901                 break;
1902         case NL80211_IFTYPE_ADHOC:
1903         case NL80211_IFTYPE_MESH_POINT:
1904                 REG_SET_BIT(ah, AR_TXCFG,
1905                             AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
1906                 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
1907                           TU_TO_USEC(next_beacon +
1908                                      (ah->atim_window ? ah->
1909                                       atim_window : 1)));
1910                 flags |= AR_NDP_TIMER_EN;
1911         case NL80211_IFTYPE_AP:
1912                 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
1913                 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
1914                           TU_TO_USEC(next_beacon -
1915                                      ah->config.
1916                                      dma_beacon_response_time));
1917                 REG_WRITE(ah, AR_NEXT_SWBA,
1918                           TU_TO_USEC(next_beacon -
1919                                      ah->config.
1920                                      sw_beacon_response_time));
1921                 flags |=
1922                         AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
1923                 break;
1924         default:
1925                 ath_print(ath9k_hw_common(ah), ATH_DBG_BEACON,
1926                           "%s: unsupported opmode: %d\n",
1927                           __func__, ah->opmode);
1928                 return;
1929                 break;
1930         }
1931
1932         REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1933         REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
1934         REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
1935         REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
1936
1937         REGWRITE_BUFFER_FLUSH(ah);
1938         DISABLE_REGWRITE_BUFFER(ah);
1939
1940         beacon_period &= ~ATH9K_BEACON_ENA;
1941         if (beacon_period & ATH9K_BEACON_RESET_TSF) {
1942                 ath9k_hw_reset_tsf(ah);
1943         }
1944
1945         REG_SET_BIT(ah, AR_TIMER_MODE, flags);
1946 }
1947 EXPORT_SYMBOL(ath9k_hw_beaconinit);
1948
1949 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
1950                                     const struct ath9k_beacon_state *bs)
1951 {
1952         u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
1953         struct ath9k_hw_capabilities *pCap = &ah->caps;
1954         struct ath_common *common = ath9k_hw_common(ah);
1955
1956         ENABLE_REGWRITE_BUFFER(ah);
1957
1958         REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
1959
1960         REG_WRITE(ah, AR_BEACON_PERIOD,
1961                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1962         REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
1963                   TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
1964
1965         REGWRITE_BUFFER_FLUSH(ah);
1966         DISABLE_REGWRITE_BUFFER(ah);
1967
1968         REG_RMW_FIELD(ah, AR_RSSI_THR,
1969                       AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
1970
1971         beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
1972
1973         if (bs->bs_sleepduration > beaconintval)
1974                 beaconintval = bs->bs_sleepduration;
1975
1976         dtimperiod = bs->bs_dtimperiod;
1977         if (bs->bs_sleepduration > dtimperiod)
1978                 dtimperiod = bs->bs_sleepduration;
1979
1980         if (beaconintval == dtimperiod)
1981                 nextTbtt = bs->bs_nextdtim;
1982         else
1983                 nextTbtt = bs->bs_nexttbtt;
1984
1985         ath_print(common, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
1986         ath_print(common, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
1987         ath_print(common, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
1988         ath_print(common, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
1989
1990         ENABLE_REGWRITE_BUFFER(ah);
1991
1992         REG_WRITE(ah, AR_NEXT_DTIM,
1993                   TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
1994         REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
1995
1996         REG_WRITE(ah, AR_SLEEP1,
1997                   SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
1998                   | AR_SLEEP1_ASSUME_DTIM);
1999
2000         if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2001                 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2002         else
2003                 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2004
2005         REG_WRITE(ah, AR_SLEEP2,
2006                   SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2007
2008         REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
2009         REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
2010
2011         REGWRITE_BUFFER_FLUSH(ah);
2012         DISABLE_REGWRITE_BUFFER(ah);
2013
2014         REG_SET_BIT(ah, AR_TIMER_MODE,
2015                     AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2016                     AR_DTIM_TIMER_EN);
2017
2018         /* TSF Out of Range Threshold */
2019         REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2020 }
2021 EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2022
2023 /*******************/
2024 /* HW Capabilities */
2025 /*******************/
2026
2027 int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2028 {
2029         struct ath9k_hw_capabilities *pCap = &ah->caps;
2030         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2031         struct ath_common *common = ath9k_hw_common(ah);
2032         struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw;
2033
2034         u16 capField = 0, eeval;
2035
2036         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2037         regulatory->current_rd = eeval;
2038
2039         eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
2040         if (AR_SREV_9285_10_OR_LATER(ah))
2041                 eeval |= AR9285_RDEXT_DEFAULT;
2042         regulatory->current_rd_ext = eeval;
2043
2044         capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
2045
2046         if (ah->opmode != NL80211_IFTYPE_AP &&
2047             ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2048                 if (regulatory->current_rd == 0x64 ||
2049                     regulatory->current_rd == 0x65)
2050                         regulatory->current_rd += 5;
2051                 else if (regulatory->current_rd == 0x41)
2052                         regulatory->current_rd = 0x43;
2053                 ath_print(common, ATH_DBG_REGULATORY,
2054                           "regdomain mapped to 0x%x\n", regulatory->current_rd);
2055         }
2056
2057         eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2058         if ((eeval & (AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A)) == 0) {
2059                 ath_print(common, ATH_DBG_FATAL,
2060                           "no band has been marked as supported in EEPROM.\n");
2061                 return -EINVAL;
2062         }
2063
2064         bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
2065
2066         if (eeval & AR5416_OPFLAGS_11A) {
2067                 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
2068                 if (ah->config.ht_enable) {
2069                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
2070                                 set_bit(ATH9K_MODE_11NA_HT20,
2071                                         pCap->wireless_modes);
2072                         if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
2073                                 set_bit(ATH9K_MODE_11NA_HT40PLUS,
2074                                         pCap->wireless_modes);
2075                                 set_bit(ATH9K_MODE_11NA_HT40MINUS,
2076                                         pCap->wireless_modes);
2077                         }
2078                 }
2079         }
2080
2081         if (eeval & AR5416_OPFLAGS_11G) {
2082                 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
2083                 if (ah->config.ht_enable) {
2084                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
2085                                 set_bit(ATH9K_MODE_11NG_HT20,
2086                                         pCap->wireless_modes);
2087                         if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
2088                                 set_bit(ATH9K_MODE_11NG_HT40PLUS,
2089                                         pCap->wireless_modes);
2090                                 set_bit(ATH9K_MODE_11NG_HT40MINUS,
2091                                         pCap->wireless_modes);
2092                         }
2093                 }
2094         }
2095
2096         pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2097         /*
2098          * For AR9271 we will temporarilly uses the rx chainmax as read from
2099          * the EEPROM.
2100          */
2101         if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2102             !(eeval & AR5416_OPFLAGS_11A) &&
2103             !(AR_SREV_9271(ah)))
2104                 /* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2105                 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2106         else
2107                 /* Use rx_chainmask from EEPROM. */
2108                 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2109
2110         if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
2111                 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2112
2113         pCap->low_2ghz_chan = 2312;
2114         pCap->high_2ghz_chan = 2732;
2115
2116         pCap->low_5ghz_chan = 4920;
2117         pCap->high_5ghz_chan = 6100;
2118
2119         pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
2120         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
2121         pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
2122
2123         pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
2124         pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
2125         pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
2126
2127         if (ah->config.ht_enable)
2128                 pCap->hw_caps |= ATH9K_HW_CAP_HT;
2129         else
2130                 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2131
2132         pCap->hw_caps |= ATH9K_HW_CAP_GTT;
2133         pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
2134         pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
2135         pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
2136
2137         if (capField & AR_EEPROM_EEPCAP_MAXQCU)
2138                 pCap->total_queues =
2139                         MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
2140         else
2141                 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
2142
2143         if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
2144                 pCap->keycache_size =
2145                         1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
2146         else
2147                 pCap->keycache_size = AR_KEYTABLE_SIZE;
2148
2149         pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
2150
2151         if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
2152                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD >> 1;
2153         else
2154                 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
2155
2156         if (AR_SREV_9271(ah))
2157                 pCap->num_gpio_pins = AR9271_NUM_GPIO;
2158         else if (AR_SREV_9285_10_OR_LATER(ah))
2159                 pCap->num_gpio_pins = AR9285_NUM_GPIO;
2160         else if (AR_SREV_9280_10_OR_LATER(ah))
2161                 pCap->num_gpio_pins = AR928X_NUM_GPIO;
2162         else
2163                 pCap->num_gpio_pins = AR_NUM_GPIO;
2164
2165         if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
2166                 pCap->hw_caps |= ATH9K_HW_CAP_CST;
2167                 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2168         } else {
2169                 pCap->rts_aggr_limit = (8 * 1024);
2170         }
2171
2172         pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
2173
2174 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
2175         ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2176         if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2177                 ah->rfkill_gpio =
2178                         MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2179                 ah->rfkill_polarity =
2180                         MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2181
2182                 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2183         }
2184 #endif
2185         if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2186                 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2187         else
2188                 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2189
2190         if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2191                 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2192         else
2193                 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2194
2195         if (regulatory->current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
2196                 pCap->reg_cap =
2197                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2198                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
2199                         AR_EEPROM_EEREGCAP_EN_KK_U2 |
2200                         AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
2201         } else {
2202                 pCap->reg_cap =
2203                         AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
2204                         AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
2205         }
2206
2207         /* Advertise midband for AR5416 with FCC midband set in eeprom */
2208         if (regulatory->current_rd_ext & (1 << REG_EXT_FCC_MIDBAND) &&
2209             AR_SREV_5416(ah))
2210                 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
2211
2212         pCap->num_antcfg_5ghz =
2213                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
2214         pCap->num_antcfg_2ghz =
2215                 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
2216
2217         if (AR_SREV_9280_10_OR_LATER(ah) &&
2218             ath9k_hw_btcoex_supported(ah)) {
2219                 btcoex_hw->btactive_gpio = ATH_BTACTIVE_GPIO;
2220                 btcoex_hw->wlanactive_gpio = ATH_WLANACTIVE_GPIO;
2221
2222                 if (AR_SREV_9285(ah)) {
2223                         btcoex_hw->scheme = ATH_BTCOEX_CFG_3WIRE;
2224                         btcoex_hw->btpriority_gpio = ATH_BTPRIORITY_GPIO;
2225                 } else {
2226                         btcoex_hw->scheme = ATH_BTCOEX_CFG_2WIRE;
2227                 }
2228         } else {
2229                 btcoex_hw->scheme = ATH_BTCOEX_CFG_NONE;
2230         }
2231
2232         if (AR_SREV_9300_20_OR_LATER(ah)) {
2233                 pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_LDPC |
2234                                  ATH9K_HW_CAP_FASTCLOCK;
2235                 pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2236                 pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2237                 pCap->rx_status_len = sizeof(struct ar9003_rxs);
2238                 pCap->tx_desc_len = sizeof(struct ar9003_txc);
2239                 pCap->txs_len = sizeof(struct ar9003_txs);
2240                 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2241                         pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2242         } else {
2243                 pCap->tx_desc_len = sizeof(struct ath_desc);
2244                 if (AR_SREV_9280_20(ah) &&
2245                     ((ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) <=
2246                       AR5416_EEP_MINOR_VER_16) ||
2247                      ah->eep_ops->get_eeprom(ah, EEP_FSTCLK_5G)))
2248                         pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2249         }
2250
2251         if (AR_SREV_9300_20_OR_LATER(ah))
2252                 pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2253
2254         if (AR_SREV_9287_10_OR_LATER(ah) || AR_SREV_9271(ah))
2255                 pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2256
2257         return 0;
2258 }
2259
2260 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
2261                             u32 capability, u32 *result)
2262 {
2263         switch (type) {
2264         case ATH9K_CAP_DS:
2265                 return (AR_SREV_9280_20_OR_LATER(ah) &&
2266                         (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
2267                         ? false : true;
2268         default:
2269                 return false;
2270         }
2271 }
2272 EXPORT_SYMBOL(ath9k_hw_getcapability);
2273
2274
2275 /****************************/
2276 /* GPIO / RFKILL / Antennae */
2277 /****************************/
2278
2279 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
2280                                          u32 gpio, u32 type)
2281 {
2282         int addr;
2283         u32 gpio_shift, tmp;
2284
2285         if (gpio > 11)
2286                 addr = AR_GPIO_OUTPUT_MUX3;
2287         else if (gpio > 5)
2288                 addr = AR_GPIO_OUTPUT_MUX2;
2289         else
2290                 addr = AR_GPIO_OUTPUT_MUX1;
2291
2292         gpio_shift = (gpio % 6) * 5;
2293
2294         if (AR_SREV_9280_20_OR_LATER(ah)
2295             || (addr != AR_GPIO_OUTPUT_MUX1)) {
2296                 REG_RMW(ah, addr, (type << gpio_shift),
2297                         (0x1f << gpio_shift));
2298         } else {
2299                 tmp = REG_READ(ah, addr);
2300                 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2301                 tmp &= ~(0x1f << gpio_shift);
2302                 tmp |= (type << gpio_shift);
2303                 REG_WRITE(ah, addr, tmp);
2304         }
2305 }
2306
2307 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
2308 {
2309         u32 gpio_shift;
2310
2311         BUG_ON(gpio >= ah->caps.num_gpio_pins);
2312
2313         gpio_shift = gpio << 1;
2314
2315         REG_RMW(ah,
2316                 AR_GPIO_OE_OUT,
2317                 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
2318                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2319 }
2320 EXPORT_SYMBOL(ath9k_hw_cfg_gpio_input);
2321
2322 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2323 {
2324 #define MS_REG_READ(x, y) \
2325         (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
2326
2327         if (gpio >= ah->caps.num_gpio_pins)
2328                 return 0xffffffff;
2329
2330         if (AR_SREV_9300_20_OR_LATER(ah))
2331                 return MS_REG_READ(AR9300, gpio) != 0;
2332         else if (AR_SREV_9271(ah))
2333                 return MS_REG_READ(AR9271, gpio) != 0;
2334         else if (AR_SREV_9287_10_OR_LATER(ah))
2335                 return MS_REG_READ(AR9287, gpio) != 0;
2336         else if (AR_SREV_9285_10_OR_LATER(ah))
2337                 return MS_REG_READ(AR9285, gpio) != 0;
2338         else if (AR_SREV_9280_10_OR_LATER(ah))
2339                 return MS_REG_READ(AR928X, gpio) != 0;
2340         else
2341                 return MS_REG_READ(AR, gpio) != 0;
2342 }
2343 EXPORT_SYMBOL(ath9k_hw_gpio_get);
2344
2345 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
2346                          u32 ah_signal_type)
2347 {
2348         u32 gpio_shift;
2349
2350         ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2351
2352         gpio_shift = 2 * gpio;
2353
2354         REG_RMW(ah,
2355                 AR_GPIO_OE_OUT,
2356                 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2357                 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2358 }
2359 EXPORT_SYMBOL(ath9k_hw_cfg_output);
2360
2361 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2362 {
2363         if (AR_SREV_9271(ah))
2364                 val = ~val;
2365
2366         REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2367                 AR_GPIO_BIT(gpio));
2368 }
2369 EXPORT_SYMBOL(ath9k_hw_set_gpio);
2370
2371 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
2372 {
2373         return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
2374 }
2375 EXPORT_SYMBOL(ath9k_hw_getdefantenna);
2376
2377 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2378 {
2379         REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2380 }
2381 EXPORT_SYMBOL(ath9k_hw_setantenna);
2382
2383 /*********************/
2384 /* General Operation */
2385 /*********************/
2386
2387 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2388 {
2389         u32 bits = REG_READ(ah, AR_RX_FILTER);
2390         u32 phybits = REG_READ(ah, AR_PHY_ERR);
2391
2392         if (phybits & AR_PHY_ERR_RADAR)
2393                 bits |= ATH9K_RX_FILTER_PHYRADAR;
2394         if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2395                 bits |= ATH9K_RX_FILTER_PHYERR;
2396
2397         return bits;
2398 }
2399 EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2400
2401 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2402 {
2403         u32 phybits;
2404
2405         ENABLE_REGWRITE_BUFFER(ah);
2406
2407         REG_WRITE(ah, AR_RX_FILTER, bits);
2408
2409         phybits = 0;
2410         if (bits & ATH9K_RX_FILTER_PHYRADAR)
2411                 phybits |= AR_PHY_ERR_RADAR;
2412         if (bits & ATH9K_RX_FILTER_PHYERR)
2413                 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2414         REG_WRITE(ah, AR_PHY_ERR, phybits);
2415
2416         if (phybits)
2417                 REG_WRITE(ah, AR_RXCFG,
2418                           REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
2419         else
2420                 REG_WRITE(ah, AR_RXCFG,
2421                           REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
2422
2423         REGWRITE_BUFFER_FLUSH(ah);
2424         DISABLE_REGWRITE_BUFFER(ah);
2425 }
2426 EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2427
2428 bool ath9k_hw_phy_disable(struct ath_hw *ah)
2429 {
2430         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2431                 return false;
2432
2433         ath9k_hw_init_pll(ah, NULL);
2434         return true;
2435 }
2436 EXPORT_SYMBOL(ath9k_hw_phy_disable);
2437
2438 bool ath9k_hw_disable(struct ath_hw *ah)
2439 {
2440         if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2441                 return false;
2442
2443         if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2444                 return false;
2445
2446         ath9k_hw_init_pll(ah, NULL);
2447         return true;
2448 }
2449 EXPORT_SYMBOL(ath9k_hw_disable);
2450
2451 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
2452 {
2453         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2454         struct ath9k_channel *chan = ah->curchan;
2455         struct ieee80211_channel *channel = chan->chan;
2456
2457         regulatory->power_limit = min(limit, (u32) MAX_RATE_POWER);
2458
2459         ah->eep_ops->set_txpower(ah, chan,
2460                                  ath9k_regd_get_ctl(regulatory, chan),
2461                                  channel->max_antenna_gain * 2,
2462                                  channel->max_power * 2,
2463                                  min((u32) MAX_RATE_POWER,
2464                                  (u32) regulatory->power_limit));
2465 }
2466 EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2467
2468 void ath9k_hw_setopmode(struct ath_hw *ah)
2469 {
2470         ath9k_hw_set_operating_mode(ah, ah->opmode);
2471 }
2472 EXPORT_SYMBOL(ath9k_hw_setopmode);
2473
2474 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2475 {
2476         REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2477         REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2478 }
2479 EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2480
2481 void ath9k_hw_write_associd(struct ath_hw *ah)
2482 {
2483         struct ath_common *common = ath9k_hw_common(ah);
2484
2485         REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
2486         REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
2487                   ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2488 }
2489 EXPORT_SYMBOL(ath9k_hw_write_associd);
2490
2491 #define ATH9K_MAX_TSF_READ 10
2492
2493 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
2494 {
2495         u32 tsf_lower, tsf_upper1, tsf_upper2;
2496         int i;
2497
2498         tsf_upper1 = REG_READ(ah, AR_TSF_U32);
2499         for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
2500                 tsf_lower = REG_READ(ah, AR_TSF_L32);
2501                 tsf_upper2 = REG_READ(ah, AR_TSF_U32);
2502                 if (tsf_upper2 == tsf_upper1)
2503                         break;
2504                 tsf_upper1 = tsf_upper2;
2505         }
2506
2507         WARN_ON( i == ATH9K_MAX_TSF_READ );
2508
2509         return (((u64)tsf_upper1 << 32) | tsf_lower);
2510 }
2511 EXPORT_SYMBOL(ath9k_hw_gettsf64);
2512
2513 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
2514 {
2515         REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
2516         REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
2517 }
2518 EXPORT_SYMBOL(ath9k_hw_settsf64);
2519
2520 void ath9k_hw_reset_tsf(struct ath_hw *ah)
2521 {
2522         if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
2523                            AH_TSF_WRITE_TIMEOUT))
2524                 ath_print(ath9k_hw_common(ah), ATH_DBG_RESET,
2525                           "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
2526
2527         REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
2528 }
2529 EXPORT_SYMBOL(ath9k_hw_reset_tsf);
2530
2531 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
2532 {
2533         if (setting)
2534                 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
2535         else
2536                 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
2537 }
2538 EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
2539
2540 void ath9k_hw_set11nmac2040(struct ath_hw *ah)
2541 {
2542         struct ieee80211_conf *conf = &ath9k_hw_common(ah)->hw->conf;
2543         u32 macmode;
2544
2545         if (conf_is_ht40(conf) && !ah->config.cwm_ignore_extcca)
2546                 macmode = AR_2040_JOINED_RX_CLEAR;
2547         else
2548                 macmode = 0;
2549
2550         REG_WRITE(ah, AR_2040_MODE, macmode);
2551 }
2552
2553 /* HW Generic timers configuration */
2554
2555 static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
2556 {
2557         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2558         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2559         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2560         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2561         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2562         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2563         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2564         {AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
2565         {AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
2566         {AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
2567                                 AR_NDP2_TIMER_MODE, 0x0002},
2568         {AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
2569                                 AR_NDP2_TIMER_MODE, 0x0004},
2570         {AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
2571                                 AR_NDP2_TIMER_MODE, 0x0008},
2572         {AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
2573                                 AR_NDP2_TIMER_MODE, 0x0010},
2574         {AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
2575                                 AR_NDP2_TIMER_MODE, 0x0020},
2576         {AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
2577                                 AR_NDP2_TIMER_MODE, 0x0040},
2578         {AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
2579                                 AR_NDP2_TIMER_MODE, 0x0080}
2580 };
2581
2582 /* HW generic timer primitives */
2583
2584 /* compute and clear index of rightmost 1 */
2585 static u32 rightmost_index(struct ath_gen_timer_table *timer_table, u32 *mask)
2586 {
2587         u32 b;
2588
2589         b = *mask;
2590         b &= (0-b);
2591         *mask &= ~b;
2592         b *= debruijn32;
2593         b >>= 27;
2594
2595         return timer_table->gen_timer_index[b];
2596 }
2597
2598 u32 ath9k_hw_gettsf32(struct ath_hw *ah)
2599 {
2600         return REG_READ(ah, AR_TSF_L32);
2601 }
2602 EXPORT_SYMBOL(ath9k_hw_gettsf32);
2603
2604 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
2605                                           void (*trigger)(void *),
2606                                           void (*overflow)(void *),
2607                                           void *arg,
2608                                           u8 timer_index)
2609 {
2610         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2611         struct ath_gen_timer *timer;
2612
2613         timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
2614
2615         if (timer == NULL) {
2616                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
2617                           "Failed to allocate memory"
2618                           "for hw timer[%d]\n", timer_index);
2619                 return NULL;
2620         }
2621
2622         /* allocate a hardware generic timer slot */
2623         timer_table->timers[timer_index] = timer;
2624         timer->index = timer_index;
2625         timer->trigger = trigger;
2626         timer->overflow = overflow;
2627         timer->arg = arg;
2628
2629         return timer;
2630 }
2631 EXPORT_SYMBOL(ath_gen_timer_alloc);
2632
2633 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
2634                               struct ath_gen_timer *timer,
2635                               u32 timer_next,
2636                               u32 timer_period)
2637 {
2638         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2639         u32 tsf;
2640
2641         BUG_ON(!timer_period);
2642
2643         set_bit(timer->index, &timer_table->timer_mask.timer_bits);
2644
2645         tsf = ath9k_hw_gettsf32(ah);
2646
2647         ath_print(ath9k_hw_common(ah), ATH_DBG_HWTIMER,
2648                   "curent tsf %x period %x"
2649                   "timer_next %x\n", tsf, timer_period, timer_next);
2650
2651         /*
2652          * Pull timer_next forward if the current TSF already passed it
2653          * because of software latency
2654          */
2655         if (timer_next < tsf)
2656                 timer_next = tsf + timer_period;
2657
2658         /*
2659          * Program generic timer registers
2660          */
2661         REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
2662                  timer_next);
2663         REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
2664                   timer_period);
2665         REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2666                     gen_tmr_configuration[timer->index].mode_mask);
2667
2668         /* Enable both trigger and thresh interrupt masks */
2669         REG_SET_BIT(ah, AR_IMR_S5,
2670                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2671                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2672 }
2673 EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
2674
2675 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
2676 {
2677         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2678
2679         if ((timer->index < AR_FIRST_NDP_TIMER) ||
2680                 (timer->index >= ATH_MAX_GEN_TIMER)) {
2681                 return;
2682         }
2683
2684         /* Clear generic timer enable bits. */
2685         REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
2686                         gen_tmr_configuration[timer->index].mode_mask);
2687
2688         /* Disable both trigger and thresh interrupt masks */
2689         REG_CLR_BIT(ah, AR_IMR_S5,
2690                 (SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
2691                 SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
2692
2693         clear_bit(timer->index, &timer_table->timer_mask.timer_bits);
2694 }
2695 EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
2696
2697 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
2698 {
2699         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2700
2701         /* free the hardware generic timer slot */
2702         timer_table->timers[timer->index] = NULL;
2703         kfree(timer);
2704 }
2705 EXPORT_SYMBOL(ath_gen_timer_free);
2706
2707 /*
2708  * Generic Timer Interrupts handling
2709  */
2710 void ath_gen_timer_isr(struct ath_hw *ah)
2711 {
2712         struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
2713         struct ath_gen_timer *timer;
2714         struct ath_common *common = ath9k_hw_common(ah);
2715         u32 trigger_mask, thresh_mask, index;
2716
2717         /* get hardware generic timer interrupt status */
2718         trigger_mask = ah->intr_gen_timer_trigger;
2719         thresh_mask = ah->intr_gen_timer_thresh;
2720         trigger_mask &= timer_table->timer_mask.val;
2721         thresh_mask &= timer_table->timer_mask.val;
2722
2723         trigger_mask &= ~thresh_mask;
2724
2725         while (thresh_mask) {
2726                 index = rightmost_index(timer_table, &thresh_mask);
2727                 timer = timer_table->timers[index];
2728                 BUG_ON(!timer);
2729                 ath_print(common, ATH_DBG_HWTIMER,
2730                           "TSF overflow for Gen timer %d\n", index);
2731                 timer->overflow(timer->arg);
2732         }
2733
2734         while (trigger_mask) {
2735                 index = rightmost_index(timer_table, &trigger_mask);
2736                 timer = timer_table->timers[index];
2737                 BUG_ON(!timer);
2738                 ath_print(common, ATH_DBG_HWTIMER,
2739                           "Gen timer[%d] trigger\n", index);
2740                 timer->trigger(timer->arg);
2741         }
2742 }
2743 EXPORT_SYMBOL(ath_gen_timer_isr);
2744
2745 /********/
2746 /* HTC  */
2747 /********/
2748
2749 void ath9k_hw_htc_resetinit(struct ath_hw *ah)
2750 {
2751         ah->htc_reset_init = true;
2752 }
2753 EXPORT_SYMBOL(ath9k_hw_htc_resetinit);
2754
2755 static struct {
2756         u32 version;
2757         const char * name;
2758 } ath_mac_bb_names[] = {
2759         /* Devices with external radios */
2760         { AR_SREV_VERSION_5416_PCI,     "5416" },
2761         { AR_SREV_VERSION_5416_PCIE,    "5418" },
2762         { AR_SREV_VERSION_9100,         "9100" },
2763         { AR_SREV_VERSION_9160,         "9160" },
2764         /* Single-chip solutions */
2765         { AR_SREV_VERSION_9280,         "9280" },
2766         { AR_SREV_VERSION_9285,         "9285" },
2767         { AR_SREV_VERSION_9287,         "9287" },
2768         { AR_SREV_VERSION_9271,         "9271" },
2769         { AR_SREV_VERSION_9300,         "9300" },
2770 };
2771
2772 /* For devices with external radios */
2773 static struct {
2774         u16 version;
2775         const char * name;
2776 } ath_rf_names[] = {
2777         { 0,                            "5133" },
2778         { AR_RAD5133_SREV_MAJOR,        "5133" },
2779         { AR_RAD5122_SREV_MAJOR,        "5122" },
2780         { AR_RAD2133_SREV_MAJOR,        "2133" },
2781         { AR_RAD2122_SREV_MAJOR,        "2122" }
2782 };
2783
2784 /*
2785  * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
2786  */
2787 static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
2788 {
2789         int i;
2790
2791         for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
2792                 if (ath_mac_bb_names[i].version == mac_bb_version) {
2793                         return ath_mac_bb_names[i].name;
2794                 }
2795         }
2796
2797         return "????";
2798 }
2799
2800 /*
2801  * Return the RF name. "????" is returned if the RF is unknown.
2802  * Used for devices with external radios.
2803  */
2804 static const char *ath9k_hw_rf_name(u16 rf_version)
2805 {
2806         int i;
2807
2808         for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
2809                 if (ath_rf_names[i].version == rf_version) {
2810                         return ath_rf_names[i].name;
2811                 }
2812         }
2813
2814         return "????";
2815 }
2816
2817 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
2818 {
2819         int used;
2820
2821         /* chipsets >= AR9280 are single-chip */
2822         if (AR_SREV_9280_10_OR_LATER(ah)) {
2823                 used = snprintf(hw_name, len,
2824                                "Atheros AR%s Rev:%x",
2825                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2826                                ah->hw_version.macRev);
2827         }
2828         else {
2829                 used = snprintf(hw_name, len,
2830                                "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
2831                                ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
2832                                ah->hw_version.macRev,
2833                                ath9k_hw_rf_name((ah->hw_version.analog5GhzRev &
2834                                                 AR_RADIO_SREV_MAJOR)),
2835                                ah->hw_version.phyRev);
2836         }
2837
2838         hw_name[used] = '\0';
2839 }
2840 EXPORT_SYMBOL(ath9k_hw_name);