drivers/net/wireless/ath/ath9k/eeprom_4k.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <asm/unaligned.h>
  18 #include "hw.h"
  19 #include "ar9002_phy.h"
  20
  21 static int ath9k_hw_4k_get_eeprom_ver(struct ath_hw *ah)
  22 {
  23         return ((ah->eeprom.map4k.baseEepHeader.version >> 12) & 0xF);
  24 }
  25
  26 static int ath9k_hw_4k_get_eeprom_rev(struct ath_hw *ah)
  27 {
  28         return ((ah->eeprom.map4k.baseEepHeader.version) & 0xFFF);
  29 }
  30
  31 #define SIZE_EEPROM_4K (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  32
  33 static bool __ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  34 {
  35         struct ath_common *common = ath9k_hw_common(ah);
  36         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  37         int addr, eep_start_loc = 64;
  38
  39         for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
  40                 if (!ath9k_hw_nvram_read(common, addr + eep_start_loc, eep_data)) {
  41                         ath_dbg(common, ATH_DBG_EEPROM,
  42                                 "Unable to read eeprom region\n");
  43                         return false;
  44                 }
  45                 eep_data++;
  46         }
  47
  48         return true;
  49 }
  50
  51 static bool __ath9k_hw_usb_4k_fill_eeprom(struct ath_hw *ah)
  52 {
  53         u16 *eep_data = (u16 *)&ah->eeprom.map4k;
  54
  55         ath9k_hw_usb_gen_fill_eeprom(ah, eep_data, 64, SIZE_EEPROM_4K);
  56
  57         return true;
  58 }
  59
  60 static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
  61 {
  62         struct ath_common *common = ath9k_hw_common(ah);
  63
  64         if (!ath9k_hw_use_flash(ah)) {
  65                 ath_dbg(common, ATH_DBG_EEPROM,
  66                         "Reading from EEPROM, not flash\n");
  67         }
  68
  69         if (common->bus_ops->ath_bus_type == ATH_USB)
  70                 return __ath9k_hw_usb_4k_fill_eeprom(ah);
  71         else
  72                 return __ath9k_hw_4k_fill_eeprom(ah);
  73 }
  74
  75 #undef SIZE_EEPROM_4K
  76
  77 static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
  78 {
  79 #define EEPROM_4K_SIZE (sizeof(struct ar5416_eeprom_4k) / sizeof(u16))
  80         struct ath_common *common = ath9k_hw_common(ah);
  81         struct ar5416_eeprom_4k *eep =
  82                 (struct ar5416_eeprom_4k *) &ah->eeprom.map4k;
  83         u16 *eepdata, temp, magic, magic2;
  84         u32 sum = 0, el;
  85         bool need_swap = false;
  86         int i, addr;
  87
  88
  89         if (!ath9k_hw_use_flash(ah)) {
  90                 if (!ath9k_hw_nvram_read(common, AR5416_EEPROM_MAGIC_OFFSET,
  91                                          &magic)) {
  92                         ath_err(common, "Reading Magic # failed\n");
  93                         return false;
  94                 }
  95
  96                 ath_dbg(common, ATH_DBG_EEPROM,
  97                         "Read Magic = 0x%04X\n", magic);
  98
  99                 if (magic != AR5416_EEPROM_MAGIC) {
 100                         magic2 = swab16(magic);
 101
 102                         if (magic2 == AR5416_EEPROM_MAGIC) {
 103                                 need_swap = true;
 104                                 eepdata = (u16 *) (&ah->eeprom);
 105
 106                                 for (addr = 0; addr < EEPROM_4K_SIZE; addr++) {
 107                                         temp = swab16(*eepdata);
 108                                         *eepdata = temp;
 109                                         eepdata++;
 110                                 }
 111                         } else {
 112                                 ath_err(common,
 113                                         "Invalid EEPROM Magic. Endianness mismatch.\n");
 114                                 return -EINVAL;
 115                         }
 116                 }
 117         }
 118
 119         ath_dbg(common, ATH_DBG_EEPROM, "need_swap = %s.\n",
 120                 need_swap ? "True" : "False");
 121
 122         if (need_swap)
 123                 el = swab16(ah->eeprom.map4k.baseEepHeader.length);
 124         else
 125                 el = ah->eeprom.map4k.baseEepHeader.length;
 126
 127         if (el > sizeof(struct ar5416_eeprom_4k))
 128                 el = sizeof(struct ar5416_eeprom_4k) / sizeof(u16);
 129         else
 130                 el = el / sizeof(u16);
 131
 132         eepdata = (u16 *)(&ah->eeprom);
 133
 134         for (i = 0; i < el; i++)
 135                 sum ^= *eepdata++;
 136
 137         if (need_swap) {
 138                 u32 integer;
 139                 u16 word;
 140
 141                 ath_dbg(common, ATH_DBG_EEPROM,
 142                         "EEPROM Endianness is not native.. Changing\n");
 143
 144                 word = swab16(eep->baseEepHeader.length);
 145                 eep->baseEepHeader.length = word;
 146
 147                 word = swab16(eep->baseEepHeader.checksum);
 148                 eep->baseEepHeader.checksum = word;
 149
 150                 word = swab16(eep->baseEepHeader.version);
 151                 eep->baseEepHeader.version = word;
 152
 153                 word = swab16(eep->baseEepHeader.regDmn[0]);
 154                 eep->baseEepHeader.regDmn[0] = word;
 155
 156                 word = swab16(eep->baseEepHeader.regDmn[1]);
 157                 eep->baseEepHeader.regDmn[1] = word;
 158
 159                 word = swab16(eep->baseEepHeader.rfSilent);
 160                 eep->baseEepHeader.rfSilent = word;
 161
 162                 word = swab16(eep->baseEepHeader.blueToothOptions);
 163                 eep->baseEepHeader.blueToothOptions = word;
 164
 165                 word = swab16(eep->baseEepHeader.deviceCap);
 166                 eep->baseEepHeader.deviceCap = word;
 167
 168                 integer = swab32(eep->modalHeader.antCtrlCommon);
 169                 eep->modalHeader.antCtrlCommon = integer;
 170
 171                 for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 172                         integer = swab32(eep->modalHeader.antCtrlChain[i]);
 173                         eep->modalHeader.antCtrlChain[i] = integer;
 174                 }
 175
 176                 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 177                         word = swab16(eep->modalHeader.spurChans[i].spurChan);
 178                         eep->modalHeader.spurChans[i].spurChan = word;
 179                 }
 180         }
 181
 182         if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
 183             ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
 184                 ath_err(common, "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
 185                         sum, ah->eep_ops->get_eeprom_ver(ah));
 186                 return -EINVAL;
 187         }
 188
 189         return 0;
 190 #undef EEPROM_4K_SIZE
 191 }
 192
 193 static u32 ath9k_hw_4k_get_eeprom(struct ath_hw *ah,
 194                                   enum eeprom_param param)
 195 {
 196         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 197         struct modal_eep_4k_header *pModal = &eep->modalHeader;
 198         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 199         u16 ver_minor;
 200
 201         ver_minor = pBase->version & AR5416_EEP_VER_MINOR_MASK;
 202
 203         switch (param) {
 204         case EEP_NFTHRESH_2:
 205                 return pModal->noiseFloorThreshCh[0];
 206         case EEP_MAC_LSW:
 207                 return get_unaligned_be16(pBase->macAddr);
 208         case EEP_MAC_MID:
 209                 return get_unaligned_be16(pBase->macAddr + 2);
 210         case EEP_MAC_MSW:
 211                 return get_unaligned_be16(pBase->macAddr + 4);
 212         case EEP_REG_0:
 213                 return pBase->regDmn[0];
 214         case EEP_REG_1:
 215                 return pBase->regDmn[1];
 216         case EEP_OP_CAP:
 217                 return pBase->deviceCap;
 218         case EEP_OP_MODE:
 219                 return pBase->opCapFlags;
 220         case EEP_RF_SILENT:
 221                 return pBase->rfSilent;
 222         case EEP_OB_2:
 223                 return pModal->ob_0;
 224         case EEP_DB_2:
 225                 return pModal->db1_1;
 226         case EEP_MINOR_REV:
 227                 return ver_minor;
 228         case EEP_TX_MASK:
 229                 return pBase->txMask;
 230         case EEP_RX_MASK:
 231                 return pBase->rxMask;
 232         case EEP_FRAC_N_5G:
 233                 return 0;
 234         case EEP_PWR_TABLE_OFFSET:
 235                 return AR5416_PWR_TABLE_OFFSET_DB;
 236         case EEP_MODAL_VER:
 237                 return pModal->version;
 238         case EEP_ANT_DIV_CTL1:
 239                 return pModal->antdiv_ctl1;
 240         case EEP_TXGAIN_TYPE:
 241                 if (ver_minor >= AR5416_EEP_MINOR_VER_19)
 242                         return pBase->txGainType;
 243                 else
 244                         return AR5416_EEP_TXGAIN_ORIGINAL;
 245         default:
 246                 return 0;
 247         }
 248 }
 249
 250 static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
 251                                   struct ath9k_channel *chan)
 252 {
 253         struct ath_common *common = ath9k_hw_common(ah);
 254         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 255         struct cal_data_per_freq_4k *pRawDataset;
 256         u8 *pCalBChans = NULL;
 257         u16 pdGainOverlap_t2;
 258         static u8 pdadcValues[AR5416_NUM_PDADC_VALUES];
 259         u16 gainBoundaries[AR5416_PD_GAINS_IN_MASK];
 260         u16 numPiers, i, j;
 261         u16 numXpdGain, xpdMask;
 262         u16 xpdGainValues[AR5416_EEP4K_NUM_PD_GAINS] = { 0, 0 };
 263         u32 reg32, regOffset, regChainOffset;
 264
 265         xpdMask = pEepData->modalHeader.xpdGain;
 266
 267         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 268             AR5416_EEP_MINOR_VER_2) {
 269                 pdGainOverlap_t2 =
 270                         pEepData->modalHeader.pdGainOverlap;
 271         } else {
 272                 pdGainOverlap_t2 = (u16)(MS(REG_READ(ah, AR_PHY_TPCRG5),
 273                                             AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
 274         }
 275
 276         pCalBChans = pEepData->calFreqPier2G;
 277         numPiers = AR5416_EEP4K_NUM_2G_CAL_PIERS;
 278
 279         numXpdGain = 0;
 280
 281         for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
 282                 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
 283                         if (numXpdGain >= AR5416_EEP4K_NUM_PD_GAINS)
 284                                 break;
 285                         xpdGainValues[numXpdGain] =
 286                                 (u16)(AR5416_PD_GAINS_IN_MASK - i);
 287                         numXpdGain++;
 288                 }
 289         }
 290
 291         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
 292                       (numXpdGain - 1) & 0x3);
 293         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
 294                       xpdGainValues[0]);
 295         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
 296                       xpdGainValues[1]);
 297         REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3, 0);
 298
 299         for (i = 0; i < AR5416_EEP4K_MAX_CHAINS; i++) {
 300                 if (AR_SREV_5416_20_OR_LATER(ah) &&
 301                     (ah->rxchainmask == 5 || ah->txchainmask == 5) &&
 302                     (i != 0)) {
 303                         regChainOffset = (i == 1) ? 0x2000 : 0x1000;
 304                 } else
 305                         regChainOffset = i * 0x1000;
 306
 307                 if (pEepData->baseEepHeader.txMask & (1 << i)) {
 308                         pRawDataset = pEepData->calPierData2G[i];
 309
 310                         ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
 311                                             pRawDataset, pCalBChans,
 312                                             numPiers, pdGainOverlap_t2,
 313                                             gainBoundaries,
 314                                             pdadcValues, numXpdGain);
 315
 316                         ENABLE_REGWRITE_BUFFER(ah);
 317
 318                         if ((i == 0) || AR_SREV_5416_20_OR_LATER(ah)) {
 319                                 REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset,
 320                                           SM(pdGainOverlap_t2,
 321                                              AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
 322                                           | SM(gainBoundaries[0],
 323                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
 324                                           | SM(gainBoundaries[1],
 325                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
 326                                           | SM(gainBoundaries[2],
 327                                                AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
 328                                           | SM(gainBoundaries[3],
 329                                        AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
 330                         }
 331
 332                         regOffset = AR_PHY_BASE + (672 << 2) + regChainOffset;
 333                         for (j = 0; j < 32; j++) {
 334                                 reg32 = get_unaligned_le32(&pdadcValues[4 * j]);
 335                                 REG_WRITE(ah, regOffset, reg32);
 336
 337                                 ath_dbg(common, ATH_DBG_EEPROM,
 338                                         "PDADC (%d,%4x): %4.4x %8.8x\n",
 339                                         i, regChainOffset, regOffset,
 340                                         reg32);
 341                                 ath_dbg(common, ATH_DBG_EEPROM,
 342                                         "PDADC: Chain %d | "
 343                                         "PDADC %3d Value %3d | "
 344                                         "PDADC %3d Value %3d | "
 345                                         "PDADC %3d Value %3d | "
 346                                         "PDADC %3d Value %3d |\n",
 347                                         i, 4 * j, pdadcValues[4 * j],
 348                                         4 * j + 1, pdadcValues[4 * j + 1],
 349                                         4 * j + 2, pdadcValues[4 * j + 2],
 350                                         4 * j + 3, pdadcValues[4 * j + 3]);
 351
 352                                 regOffset += 4;
 353                         }
 354
 355                         REGWRITE_BUFFER_FLUSH(ah);
 356                 }
 357         }
 358 }
 359
 360 static void ath9k_hw_set_4k_power_per_rate_table(struct ath_hw *ah,
 361                                                  struct ath9k_channel *chan,
 362                                                  int16_t *ratesArray,
 363                                                  u16 cfgCtl,
 364                                                  u16 AntennaReduction,
 365                                                  u16 twiceMaxRegulatoryPower,
 366                                                  u16 powerLimit)
 367 {
 368 #define CMP_TEST_GRP \
 369         (((cfgCtl & ~CTL_MODE_M)| (pCtlMode[ctlMode] & CTL_MODE_M)) ==  \
 370          pEepData->ctlIndex[i])                                         \
 371         || (((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == \
 372             ((pEepData->ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))
 373
 374         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 375         int i;
 376         int16_t twiceLargestAntenna;
 377         u16 twiceMinEdgePower;
 378         u16 twiceMaxEdgePower = MAX_RATE_POWER;
 379         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
 380         u16 numCtlModes;
 381         const u16 *pCtlMode;
 382         u16 ctlMode, freq;
 383         struct chan_centers centers;
 384         struct cal_ctl_data_4k *rep;
 385         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 386         static const u16 tpScaleReductionTable[5] =
 387                 { 0, 3, 6, 9, MAX_RATE_POWER };
 388         struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
 389                 0, { 0, 0, 0, 0}
 390         };
 391         struct cal_target_power_leg targetPowerOfdmExt = {
 392                 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
 393                 0, { 0, 0, 0, 0 }
 394         };
 395         struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
 396                 0, {0, 0, 0, 0}
 397         };
 398         static const u16 ctlModesFor11g[] = {
 399                 CTL_11B, CTL_11G, CTL_2GHT20,
 400                 CTL_11B_EXT, CTL_11G_EXT, CTL_2GHT40
 401         };
 402
 403         ath9k_hw_get_channel_centers(ah, chan, &centers);
 404
 405         twiceLargestAntenna = pEepData->modalHeader.antennaGainCh[0];
 406         twiceLargestAntenna = (int16_t)min(AntennaReduction -
 407                                            twiceLargestAntenna, 0);
 408
 409         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
 410         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
 411                 maxRegAllowedPower -=
 412                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
 413         }
 414
 415         scaledPower = min(powerLimit, maxRegAllowedPower);
 416         scaledPower = max((u16)0, scaledPower);
 417
 418         numCtlModes = ARRAY_SIZE(ctlModesFor11g) - SUB_NUM_CTL_MODES_AT_2G_40;
 419         pCtlMode = ctlModesFor11g;
 420
 421         ath9k_hw_get_legacy_target_powers(ah, chan,
 422                         pEepData->calTargetPowerCck,
 423                         AR5416_NUM_2G_CCK_TARGET_POWERS,
 424                         &targetPowerCck, 4, false);
 425         ath9k_hw_get_legacy_target_powers(ah, chan,
 426                         pEepData->calTargetPower2G,
 427                         AR5416_NUM_2G_20_TARGET_POWERS,
 428                         &targetPowerOfdm, 4, false);
 429         ath9k_hw_get_target_powers(ah, chan,
 430                         pEepData->calTargetPower2GHT20,
 431                         AR5416_NUM_2G_20_TARGET_POWERS,
 432                         &targetPowerHt20, 8, false);
 433
 434         if (IS_CHAN_HT40(chan)) {
 435                 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
 436                 ath9k_hw_get_target_powers(ah, chan,
 437                                 pEepData->calTargetPower2GHT40,
 438                                 AR5416_NUM_2G_40_TARGET_POWERS,
 439                                 &targetPowerHt40, 8, true);
 440                 ath9k_hw_get_legacy_target_powers(ah, chan,
 441                                 pEepData->calTargetPowerCck,
 442                                 AR5416_NUM_2G_CCK_TARGET_POWERS,
 443                                 &targetPowerCckExt, 4, true);
 444                 ath9k_hw_get_legacy_target_powers(ah, chan,
 445                                 pEepData->calTargetPower2G,
 446                                 AR5416_NUM_2G_20_TARGET_POWERS,
 447                                 &targetPowerOfdmExt, 4, true);
 448         }
 449
 450         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
 451                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
 452                         (pCtlMode[ctlMode] == CTL_2GHT40);
 453
 454                 if (isHt40CtlMode)
 455                         freq = centers.synth_center;
 456                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
 457                         freq = centers.ext_center;
 458                 else
 459                         freq = centers.ctl_center;
 460
 461                 if (ah->eep_ops->get_eeprom_ver(ah) == 14 &&
 462                     ah->eep_ops->get_eeprom_rev(ah) <= 2)
 463                         twiceMaxEdgePower = MAX_RATE_POWER;
 464
 465                 for (i = 0; (i < AR5416_EEP4K_NUM_CTLS) &&
 466                              pEepData->ctlIndex[i]; i++) {
 467
 468                         if (CMP_TEST_GRP) {
 469                                 rep = &(pEepData->ctlData[i]);
 470
 471                                 twiceMinEdgePower = ath9k_hw_get_max_edge_power(
 472                                         freq,
 473                                         rep->ctlEdges[
 474                                         ar5416_get_ntxchains(ah->txchainmask) - 1],
 475                                         IS_CHAN_2GHZ(chan),
 476                                         AR5416_EEP4K_NUM_BAND_EDGES);
 477
 478                                 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
 479                                         twiceMaxEdgePower =
 480                                                 min(twiceMaxEdgePower,
 481                                                     twiceMinEdgePower);
 482                                 } else {
 483                                         twiceMaxEdgePower = twiceMinEdgePower;
 484                                         break;
 485                                 }
 486                         }
 487                 }
 488
 489                 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
 490
 491                 switch (pCtlMode[ctlMode]) {
 492                 case CTL_11B:
 493                         for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x); i++) {
 494                                 targetPowerCck.tPow2x[i] =
 495                                         min((u16)targetPowerCck.tPow2x[i],
 496                                             minCtlPower);
 497                         }
 498                         break;
 499                 case CTL_11G:
 500                         for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x); i++) {
 501                                 targetPowerOfdm.tPow2x[i] =
 502                                         min((u16)targetPowerOfdm.tPow2x[i],
 503                                             minCtlPower);
 504                         }
 505                         break;
 506                 case CTL_2GHT20:
 507                         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++) {
 508                                 targetPowerHt20.tPow2x[i] =
 509                                         min((u16)targetPowerHt20.tPow2x[i],
 510                                             minCtlPower);
 511                         }
 512                         break;
 513                 case CTL_11B_EXT:
 514                         targetPowerCckExt.tPow2x[0] =
 515                                 min((u16)targetPowerCckExt.tPow2x[0],
 516                                     minCtlPower);
 517                         break;
 518                 case CTL_11G_EXT:
 519                         targetPowerOfdmExt.tPow2x[0] =
 520                                 min((u16)targetPowerOfdmExt.tPow2x[0],
 521                                     minCtlPower);
 522                         break;
 523                 case CTL_2GHT40:
 524                         for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 525                                 targetPowerHt40.tPow2x[i] =
 526                                         min((u16)targetPowerHt40.tPow2x[i],
 527                                             minCtlPower);
 528                         }
 529                         break;
 530                 default:
 531                         break;
 532                 }
 533         }
 534
 535         ratesArray[rate6mb] =
 536         ratesArray[rate9mb] =
 537         ratesArray[rate12mb] =
 538         ratesArray[rate18mb] =
 539         ratesArray[rate24mb] =
 540         targetPowerOfdm.tPow2x[0];
 541
 542         ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
 543         ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
 544         ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
 545         ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
 546
 547         for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
 548                 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
 549
 550         ratesArray[rate1l] = targetPowerCck.tPow2x[0];
 551         ratesArray[rate2s] = ratesArray[rate2l] = targetPowerCck.tPow2x[1];
 552         ratesArray[rate5_5s] = ratesArray[rate5_5l] = targetPowerCck.tPow2x[2];
 553         ratesArray[rate11s] = ratesArray[rate11l] = targetPowerCck.tPow2x[3];
 554
 555         if (IS_CHAN_HT40(chan)) {
 556                 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
 557                         ratesArray[rateHt40_0 + i] =
 558                                 targetPowerHt40.tPow2x[i];
 559                 }
 560                 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
 561                 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
 562                 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
 563                 ratesArray[rateExtCck] = targetPowerCckExt.tPow2x[0];
 564         }
 565
 566 #undef CMP_TEST_GRP
 567 }
 568
 569 static void ath9k_hw_4k_set_txpower(struct ath_hw *ah,
 570                                     struct ath9k_channel *chan,
 571                                     u16 cfgCtl,
 572                                     u8 twiceAntennaReduction,
 573                                     u8 twiceMaxRegulatoryPower,
 574                                     u8 powerLimit, bool test)
 575 {
 576         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 577         struct ar5416_eeprom_4k *pEepData = &ah->eeprom.map4k;
 578         struct modal_eep_4k_header *pModal = &pEepData->modalHeader;
 579         int16_t ratesArray[Ar5416RateSize];
 580         u8 ht40PowerIncForPdadc = 2;
 581         int i;
 582
 583         memset(ratesArray, 0, sizeof(ratesArray));
 584
 585         if ((pEepData->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 586             AR5416_EEP_MINOR_VER_2) {
 587                 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
 588         }
 589
 590         ath9k_hw_set_4k_power_per_rate_table(ah, chan,
 591                                              &ratesArray[0], cfgCtl,
 592                                              twiceAntennaReduction,
 593                                              twiceMaxRegulatoryPower,
 594                                              powerLimit);
 595
 596         ath9k_hw_set_4k_power_cal_table(ah, chan);
 597
 598         regulatory->max_power_level = 0;
 599         for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
 600                 if (ratesArray[i] > MAX_RATE_POWER)
 601                         ratesArray[i] = MAX_RATE_POWER;
 602
 603                 if (ratesArray[i] > regulatory->max_power_level)
 604                         regulatory->max_power_level = ratesArray[i];
 605         }
 606
 607         if (test)
 608             return;
 609
 610         if (AR_SREV_9280_20_OR_LATER(ah)) {
 611                 for (i = 0; i < Ar5416RateSize; i++)
 612                         ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2;
 613         }
 614
 615         ENABLE_REGWRITE_BUFFER(ah);
 616
 617         /* OFDM power per rate */
 618         REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
 619                   ATH9K_POW_SM(ratesArray[rate18mb], 24)
 620                   | ATH9K_POW_SM(ratesArray[rate12mb], 16)
 621                   | ATH9K_POW_SM(ratesArray[rate9mb], 8)
 622                   | ATH9K_POW_SM(ratesArray[rate6mb], 0));
 623         REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
 624                   ATH9K_POW_SM(ratesArray[rate54mb], 24)
 625                   | ATH9K_POW_SM(ratesArray[rate48mb], 16)
 626                   | ATH9K_POW_SM(ratesArray[rate36mb], 8)
 627                   | ATH9K_POW_SM(ratesArray[rate24mb], 0));
 628
 629         /* CCK power per rate */
 630         REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
 631                   ATH9K_POW_SM(ratesArray[rate2s], 24)
 632                   | ATH9K_POW_SM(ratesArray[rate2l], 16)
 633                   | ATH9K_POW_SM(ratesArray[rateXr], 8)
 634                   | ATH9K_POW_SM(ratesArray[rate1l], 0));
 635         REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
 636                   ATH9K_POW_SM(ratesArray[rate11s], 24)
 637                   | ATH9K_POW_SM(ratesArray[rate11l], 16)
 638                   | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
 639                   | ATH9K_POW_SM(ratesArray[rate5_5l], 0));
 640
 641         /* HT20 power per rate */
 642         REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
 643                   ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
 644                   | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
 645                   | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
 646                   | ATH9K_POW_SM(ratesArray[rateHt20_0], 0));
 647         REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
 648                   ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
 649                   | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
 650                   | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
 651                   | ATH9K_POW_SM(ratesArray[rateHt20_4], 0));
 652
 653         /* HT40 power per rate */
 654         if (IS_CHAN_HT40(chan)) {
 655                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
 656                           ATH9K_POW_SM(ratesArray[rateHt40_3] +
 657                                        ht40PowerIncForPdadc, 24)
 658                           | ATH9K_POW_SM(ratesArray[rateHt40_2] +
 659                                          ht40PowerIncForPdadc, 16)
 660                           | ATH9K_POW_SM(ratesArray[rateHt40_1] +
 661                                          ht40PowerIncForPdadc, 8)
 662                           | ATH9K_POW_SM(ratesArray[rateHt40_0] +
 663                                          ht40PowerIncForPdadc, 0));
 664                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
 665                           ATH9K_POW_SM(ratesArray[rateHt40_7] +
 666                                        ht40PowerIncForPdadc, 24)
 667                           | ATH9K_POW_SM(ratesArray[rateHt40_6] +
 668                                          ht40PowerIncForPdadc, 16)
 669                           | ATH9K_POW_SM(ratesArray[rateHt40_5] +
 670                                          ht40PowerIncForPdadc, 8)
 671                           | ATH9K_POW_SM(ratesArray[rateHt40_4] +
 672                                          ht40PowerIncForPdadc, 0));
 673                 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
 674                           ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
 675                           | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
 676                           | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
 677                           | ATH9K_POW_SM(ratesArray[rateDupCck], 0));
 678         }
 679
 680         REGWRITE_BUFFER_FLUSH(ah);
 681 }
 682
 683 static void ath9k_hw_4k_set_addac(struct ath_hw *ah,
 684                                   struct ath9k_channel *chan)
 685 {
 686         struct modal_eep_4k_header *pModal;
 687         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 688         u8 biaslevel;
 689
 690         if (ah->hw_version.macVersion != AR_SREV_VERSION_9160)
 691                 return;
 692
 693         if (ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_MINOR_VER_7)
 694                 return;
 695
 696         pModal = &eep->modalHeader;
 697
 698         if (pModal->xpaBiasLvl != 0xff) {
 699                 biaslevel = pModal->xpaBiasLvl;
 700                 INI_RA(&ah->iniAddac, 7, 1) =
 701                   (INI_RA(&ah->iniAddac, 7, 1) & (~0x18)) | biaslevel << 3;
 702         }
 703 }
 704
 705 static void ath9k_hw_4k_set_gain(struct ath_hw *ah,
 706                                  struct modal_eep_4k_header *pModal,
 707                                  struct ar5416_eeprom_4k *eep,
 708                                  u8 txRxAttenLocal)
 709 {
 710         REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0,
 711                   pModal->antCtrlChain[0]);
 712
 713         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0),
 714                   (REG_READ(ah, AR_PHY_TIMING_CTRL4(0)) &
 715                    ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
 716                      AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
 717                   SM(pModal->iqCalICh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
 718                   SM(pModal->iqCalQCh[0], AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
 719
 720         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 721             AR5416_EEP_MINOR_VER_3) {
 722                 txRxAttenLocal = pModal->txRxAttenCh[0];
 723
 724                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 725                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, pModal->bswMargin[0]);
 726                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 727                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 728                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 729                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 730                               pModal->xatten2Margin[0]);
 731                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ,
 732                               AR_PHY_GAIN_2GHZ_XATTEN2_DB, pModal->xatten2Db[0]);
 733
 734                 /* Set the block 1 value to block 0 value */
 735                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 736                               AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
 737                               pModal->bswMargin[0]);
 738                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 739                               AR_PHY_GAIN_2GHZ_XATTEN1_DB, pModal->bswAtten[0]);
 740                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 741                               AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
 742                               pModal->xatten2Margin[0]);
 743                 REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + 0x1000,
 744                               AR_PHY_GAIN_2GHZ_XATTEN2_DB,
 745                               pModal->xatten2Db[0]);
 746         }
 747
 748         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 749                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 750         REG_RMW_FIELD(ah, AR_PHY_RXGAIN,
 751                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 752
 753         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 754                       AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAttenLocal);
 755         REG_RMW_FIELD(ah, AR_PHY_RXGAIN + 0x1000,
 756                       AR9280_PHY_RXGAIN_TXRX_MARGIN, pModal->rxTxMarginCh[0]);
 757 }
 758
 759 /*
 760  * Read EEPROM header info and program the device for correct operation
 761  * given the channel value.
 762  */
 763 static void ath9k_hw_4k_set_board_values(struct ath_hw *ah,
 764                                          struct ath9k_channel *chan)
 765 {
 766         struct modal_eep_4k_header *pModal;
 767         struct ar5416_eeprom_4k *eep = &ah->eeprom.map4k;
 768         struct base_eep_header_4k *pBase = &eep->baseEepHeader;
 769         u8 txRxAttenLocal;
 770         u8 ob[5], db1[5], db2[5];
 771         u8 ant_div_control1, ant_div_control2;
 772         u32 regVal;
 773
 774         pModal = &eep->modalHeader;
 775         txRxAttenLocal = 23;
 776
 777         REG_WRITE(ah, AR_PHY_SWITCH_COM, pModal->antCtrlCommon);
 778
 779         /* Single chain for 4K EEPROM*/
 780         ath9k_hw_4k_set_gain(ah, pModal, eep, txRxAttenLocal);
 781
 782         /* Initialize Ant Diversity settings from EEPROM */
 783         if (pModal->version >= 3) {
 784                 ant_div_control1 = pModal->antdiv_ctl1;
 785                 ant_div_control2 = pModal->antdiv_ctl2;
 786
 787                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 788                 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL));
 789
 790                 regVal |= SM(ant_div_control1,
 791                              AR_PHY_9285_ANT_DIV_CTL);
 792                 regVal |= SM(ant_div_control2,
 793                              AR_PHY_9285_ANT_DIV_ALT_LNACONF);
 794                 regVal |= SM((ant_div_control2 >> 2),
 795                              AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
 796                 regVal |= SM((ant_div_control1 >> 1),
 797                              AR_PHY_9285_ANT_DIV_ALT_GAINTB);
 798                 regVal |= SM((ant_div_control1 >> 2),
 799                              AR_PHY_9285_ANT_DIV_MAIN_GAINTB);
 800
 801
 802                 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal);
 803                 regVal = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
 804                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 805                 regVal &= (~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 806                 regVal |= SM((ant_div_control1 >> 3),
 807                              AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV);
 808
 809                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regVal);
 810                 regVal = REG_READ(ah, AR_PHY_CCK_DETECT);
 811         }
 812
 813         if (pModal->version >= 2) {
 814                 ob[0] = pModal->ob_0;
 815                 ob[1] = pModal->ob_1;
 816                 ob[2] = pModal->ob_2;
 817                 ob[3] = pModal->ob_3;
 818                 ob[4] = pModal->ob_4;
 819
 820                 db1[0] = pModal->db1_0;
 821                 db1[1] = pModal->db1_1;
 822                 db1[2] = pModal->db1_2;
 823                 db1[3] = pModal->db1_3;
 824                 db1[4] = pModal->db1_4;
 825
 826                 db2[0] = pModal->db2_0;
 827                 db2[1] = pModal->db2_1;
 828                 db2[2] = pModal->db2_2;
 829                 db2[3] = pModal->db2_3;
 830                 db2[4] = pModal->db2_4;
 831         } else if (pModal->version == 1) {
 832                 ob[0] = pModal->ob_0;
 833                 ob[1] = ob[2] = ob[3] = ob[4] = pModal->ob_1;
 834                 db1[0] = pModal->db1_0;
 835                 db1[1] = db1[2] = db1[3] = db1[4] = pModal->db1_1;
 836                 db2[0] = pModal->db2_0;
 837                 db2[1] = db2[2] = db2[3] = db2[4] = pModal->db2_1;
 838         } else {
 839                 int i;
 840
 841                 for (i = 0; i < 5; i++) {
 842                         ob[i] = pModal->ob_0;
 843                         db1[i] = pModal->db1_0;
 844                         db2[i] = pModal->db1_0;
 845                 }
 846         }
 847
 848         if (AR_SREV_9271(ah)) {
 849                 ath9k_hw_analog_shift_rmw(ah,
 850                                           AR9285_AN_RF2G3,
 851                                           AR9271_AN_RF2G3_OB_cck,
 852                                           AR9271_AN_RF2G3_OB_cck_S,
 853                                           ob[0]);
 854                 ath9k_hw_analog_shift_rmw(ah,
 855                                           AR9285_AN_RF2G3,
 856                                           AR9271_AN_RF2G3_OB_psk,
 857                                           AR9271_AN_RF2G3_OB_psk_S,
 858                                           ob[1]);
 859                 ath9k_hw_analog_shift_rmw(ah,
 860                                           AR9285_AN_RF2G3,
 861                                           AR9271_AN_RF2G3_OB_qam,
 862                                           AR9271_AN_RF2G3_OB_qam_S,
 863                                           ob[2]);
 864                 ath9k_hw_analog_shift_rmw(ah,
 865                                           AR9285_AN_RF2G3,
 866                                           AR9271_AN_RF2G3_DB_1,
 867                                           AR9271_AN_RF2G3_DB_1_S,
 868                                           db1[0]);
 869                 ath9k_hw_analog_shift_rmw(ah,
 870                                           AR9285_AN_RF2G4,
 871                                           AR9271_AN_RF2G4_DB_2,
 872                                           AR9271_AN_RF2G4_DB_2_S,
 873                                           db2[0]);
 874         } else {
 875                 ath9k_hw_analog_shift_rmw(ah,
 876                                           AR9285_AN_RF2G3,
 877                                           AR9285_AN_RF2G3_OB_0,
 878                                           AR9285_AN_RF2G3_OB_0_S,
 879                                           ob[0]);
 880                 ath9k_hw_analog_shift_rmw(ah,
 881                                           AR9285_AN_RF2G3,
 882                                           AR9285_AN_RF2G3_OB_1,
 883                                           AR9285_AN_RF2G3_OB_1_S,
 884                                           ob[1]);
 885                 ath9k_hw_analog_shift_rmw(ah,
 886                                           AR9285_AN_RF2G3,
 887                                           AR9285_AN_RF2G3_OB_2,
 888                                           AR9285_AN_RF2G3_OB_2_S,
 889                                           ob[2]);
 890                 ath9k_hw_analog_shift_rmw(ah,
 891                                           AR9285_AN_RF2G3,
 892                                           AR9285_AN_RF2G3_OB_3,
 893                                           AR9285_AN_RF2G3_OB_3_S,
 894                                           ob[3]);
 895                 ath9k_hw_analog_shift_rmw(ah,
 896                                           AR9285_AN_RF2G3,
 897                                           AR9285_AN_RF2G3_OB_4,
 898                                           AR9285_AN_RF2G3_OB_4_S,
 899                                           ob[4]);
 900
 901                 ath9k_hw_analog_shift_rmw(ah,
 902                                           AR9285_AN_RF2G3,
 903                                           AR9285_AN_RF2G3_DB1_0,
 904                                           AR9285_AN_RF2G3_DB1_0_S,
 905                                           db1[0]);
 906                 ath9k_hw_analog_shift_rmw(ah,
 907                                           AR9285_AN_RF2G3,
 908                                           AR9285_AN_RF2G3_DB1_1,
 909                                           AR9285_AN_RF2G3_DB1_1_S,
 910                                           db1[1]);
 911                 ath9k_hw_analog_shift_rmw(ah,
 912                                           AR9285_AN_RF2G3,
 913                                           AR9285_AN_RF2G3_DB1_2,
 914                                           AR9285_AN_RF2G3_DB1_2_S,
 915                                           db1[2]);
 916                 ath9k_hw_analog_shift_rmw(ah,
 917                                           AR9285_AN_RF2G4,
 918                                           AR9285_AN_RF2G4_DB1_3,
 919                                           AR9285_AN_RF2G4_DB1_3_S,
 920                                           db1[3]);
 921                 ath9k_hw_analog_shift_rmw(ah,
 922                                           AR9285_AN_RF2G4,
 923                                           AR9285_AN_RF2G4_DB1_4,
 924                                           AR9285_AN_RF2G4_DB1_4_S, db1[4]);
 925
 926                 ath9k_hw_analog_shift_rmw(ah,
 927                                           AR9285_AN_RF2G4,
 928                                           AR9285_AN_RF2G4_DB2_0,
 929                                           AR9285_AN_RF2G4_DB2_0_S,
 930                                           db2[0]);
 931                 ath9k_hw_analog_shift_rmw(ah,
 932                                           AR9285_AN_RF2G4,
 933                                           AR9285_AN_RF2G4_DB2_1,
 934                                           AR9285_AN_RF2G4_DB2_1_S,
 935                                           db2[1]);
 936                 ath9k_hw_analog_shift_rmw(ah,
 937                                           AR9285_AN_RF2G4,
 938                                           AR9285_AN_RF2G4_DB2_2,
 939                                           AR9285_AN_RF2G4_DB2_2_S,
 940                                           db2[2]);
 941                 ath9k_hw_analog_shift_rmw(ah,
 942                                           AR9285_AN_RF2G4,
 943                                           AR9285_AN_RF2G4_DB2_3,
 944                                           AR9285_AN_RF2G4_DB2_3_S,
 945                                           db2[3]);
 946                 ath9k_hw_analog_shift_rmw(ah,
 947                                           AR9285_AN_RF2G4,
 948                                           AR9285_AN_RF2G4_DB2_4,
 949                                           AR9285_AN_RF2G4_DB2_4_S,
 950                                           db2[4]);
 951         }
 952
 953
 954         REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
 955                       pModal->switchSettling);
 956         REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
 957                       pModal->adcDesiredSize);
 958
 959         REG_WRITE(ah, AR_PHY_RF_CTL4,
 960                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF) |
 961                   SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAB_OFF) |
 962                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAA_ON)  |
 963                   SM(pModal->txFrameToXpaOn, AR_PHY_RF_CTL4_FRAME_XPAB_ON));
 964
 965         REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 966                       pModal->txEndToRxOn);
 967
 968         if (AR_SREV_9271_10(ah))
 969                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
 970                               pModal->txEndToRxOn);
 971         REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
 972                       pModal->thresh62);
 973         REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0, AR_PHY_EXT_CCA0_THRESH62,
 974                       pModal->thresh62);
 975
 976         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 977                                                 AR5416_EEP_MINOR_VER_2) {
 978                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_DATA_START,
 979                               pModal->txFrameToDataStart);
 980                 REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
 981                               pModal->txFrameToPaOn);
 982         }
 983
 984         if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
 985                                                 AR5416_EEP_MINOR_VER_3) {
 986                 if (IS_CHAN_HT40(chan))
 987                         REG_RMW_FIELD(ah, AR_PHY_SETTLING,
 988                                       AR_PHY_SETTLING_SWITCH,
 989                                       pModal->swSettleHt40);
 990         }
 991         if (AR_SREV_9271(ah) || AR_SREV_9285(ah)) {
 992                 u8 bb_desired_scale = (pModal->bb_scale_smrt_antenna &
 993                                 EEP_4K_BB_DESIRED_SCALE_MASK);
 994                 if ((pBase->txGainType == 0) && (bb_desired_scale != 0)) {
 995                         u32 pwrctrl, mask, clr;
 996
 997                         mask = BIT(0)|BIT(5)|BIT(10)|BIT(15)|BIT(20)|BIT(25);
 998                         pwrctrl = mask * bb_desired_scale;
 999                         clr = mask * 0x1f;
1000                         REG_RMW(ah, AR_PHY_TX_PWRCTRL8, pwrctrl, clr);
1001                         REG_RMW(ah, AR_PHY_TX_PWRCTRL10, pwrctrl, clr);
1002                         REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL12, pwrctrl, clr);
1003
1004                         mask = BIT(0)|BIT(5)|BIT(15);
1005                         pwrctrl = mask * bb_desired_scale;
1006                         clr = mask * 0x1f;
1007                         REG_RMW(ah, AR_PHY_TX_PWRCTRL9, pwrctrl, clr);
1008
1009                         mask = BIT(0)|BIT(5);
1010                         pwrctrl = mask * bb_desired_scale;
1011                         clr = mask * 0x1f;
1012                         REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL11, pwrctrl, clr);
1013                         REG_RMW(ah, AR_PHY_CH0_TX_PWRCTRL13, pwrctrl, clr);
1014                 }
1015         }
1016 }
1017
1018 static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1019 {
1020 #define EEP_MAP4K_SPURCHAN \
1021         (ah->eeprom.map4k.modalHeader.spurChans[i].spurChan)
1022         struct ath_common *common = ath9k_hw_common(ah);
1023
1024         u16 spur_val = AR_NO_SPUR;
1025
1026         ath_dbg(common, ATH_DBG_ANI,
1027                 "Getting spur idx:%d is2Ghz:%d val:%x\n",
1028                 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1029
1030         switch (ah->config.spurmode) {
1031         case SPUR_DISABLE:
1032                 break;
1033         case SPUR_ENABLE_IOCTL:
1034                 spur_val = ah->config.spurchans[i][is2GHz];
1035                 ath_dbg(common, ATH_DBG_ANI,
1036                         "Getting spur val from new loc. %d\n", spur_val);
1037                 break;
1038         case SPUR_ENABLE_EEPROM:
1039                 spur_val = EEP_MAP4K_SPURCHAN;
1040                 break;
1041         }
1042
1043         return spur_val;
1044
1045 #undef EEP_MAP4K_SPURCHAN
1046 }
1047
1048 const struct eeprom_ops eep_4k_ops = {
1049         .check_eeprom           = ath9k_hw_4k_check_eeprom,
1050         .get_eeprom             = ath9k_hw_4k_get_eeprom,
1051         .fill_eeprom            = ath9k_hw_4k_fill_eeprom,
1052         .get_eeprom_ver         = ath9k_hw_4k_get_eeprom_ver,
1053         .get_eeprom_rev         = ath9k_hw_4k_get_eeprom_rev,
1054         .set_board_values       = ath9k_hw_4k_set_board_values,
1055         .set_addac              = ath9k_hw_4k_set_addac,
1056         .set_txpower            = ath9k_hw_4k_set_txpower,
1057         .get_spur_channel       = ath9k_hw_4k_get_spur_channel
1058 };