2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <net/cfg80211.h>
22 #define AH_USE_EEPROM 0x1
25 #define AR5416_EEPROM_MAGIC 0x5aa5
27 #define AR5416_EEPROM_MAGIC 0xa55a
30 #define CTRY_DEBUG 0x1ff
31 #define CTRY_DEFAULT 0
33 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
34 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
35 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
36 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
37 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
38 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
39 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
40 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
41 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
43 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
44 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
45 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
46 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
47 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
48 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
50 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
51 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
53 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
54 #define AR5416_EEPROM_S 2
55 #define AR5416_EEPROM_OFFSET 0x2000
56 #define AR5416_EEPROM_MAX 0xae0
58 #define AR5416_EEPROM_START_ADDR \
59 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
61 #define SD_NO_CTL 0xE0
72 #define EXT_ADDITIVE (0x8000)
73 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
74 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
75 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
77 #define SUB_NUM_CTL_MODES_AT_5G_40 2
78 #define SUB_NUM_CTL_MODES_AT_2G_40 3
80 #define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
81 #define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
84 * For AR9285 and later chipsets, the following bits are not being programmed
85 * in EEPROM and so need to be enabled always.
89 * Bit 2: en_fcc_dfs_ht40
91 * Bit 4: en_jap_dfs_ht40
93 #define AR9285_RDEXT_DEFAULT 0x1F
95 #define AR_EEPROM_MAC(i) (0x1d+(i))
96 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
97 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
98 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
100 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
101 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
102 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
103 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_10_OR_LATER(ah) && \
104 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
106 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
107 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
108 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
109 #define AR_EEPROM_RFSILENT_POLARITY_S 1
111 #define EEP_RFSILENT_ENABLED 0x0001
112 #define EEP_RFSILENT_ENABLED_S 0
113 #define EEP_RFSILENT_POLARITY 0x0002
114 #define EEP_RFSILENT_POLARITY_S 1
115 #define EEP_RFSILENT_GPIO_SEL 0x001c
116 #define EEP_RFSILENT_GPIO_SEL_S 2
118 #define AR5416_OPFLAGS_11A 0x01
119 #define AR5416_OPFLAGS_11G 0x02
120 #define AR5416_OPFLAGS_N_5G_HT40 0x04
121 #define AR5416_OPFLAGS_N_2G_HT40 0x08
122 #define AR5416_OPFLAGS_N_5G_HT20 0x10
123 #define AR5416_OPFLAGS_N_2G_HT20 0x20
125 #define AR5416_EEP_NO_BACK_VER 0x1
126 #define AR5416_EEP_VER 0xE
127 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
128 #define AR5416_EEP_MINOR_VER_2 0x2
129 #define AR5416_EEP_MINOR_VER_3 0x3
130 #define AR5416_EEP_MINOR_VER_7 0x7
131 #define AR5416_EEP_MINOR_VER_9 0x9
132 #define AR5416_EEP_MINOR_VER_16 0x10
133 #define AR5416_EEP_MINOR_VER_17 0x11
134 #define AR5416_EEP_MINOR_VER_19 0x13
135 #define AR5416_EEP_MINOR_VER_20 0x14
136 #define AR5416_EEP_MINOR_VER_22 0x16
138 #define AR5416_NUM_5G_CAL_PIERS 8
139 #define AR5416_NUM_2G_CAL_PIERS 4
140 #define AR5416_NUM_5G_20_TARGET_POWERS 8
141 #define AR5416_NUM_5G_40_TARGET_POWERS 8
142 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
143 #define AR5416_NUM_2G_20_TARGET_POWERS 4
144 #define AR5416_NUM_2G_40_TARGET_POWERS 4
145 #define AR5416_NUM_CTLS 24
146 #define AR5416_NUM_BAND_EDGES 8
147 #define AR5416_NUM_PD_GAINS 4
148 #define AR5416_PD_GAINS_IN_MASK 4
149 #define AR5416_PD_GAIN_ICEPTS 5
150 #define AR5416_EEPROM_MODAL_SPURS 5
151 #define AR5416_MAX_RATE_POWER 63
152 #define AR5416_NUM_PDADC_VALUES 128
153 #define AR5416_BCHAN_UNUSED 0xFF
154 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
155 #define AR5416_MAX_CHAINS 3
156 #define AR5416_PWR_TABLE_OFFSET -5
158 /* Rx gain type values */
159 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
160 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
161 #define AR5416_EEP_RXGAIN_ORIG 2
163 /* Tx gain type values */
164 #define AR5416_EEP_TXGAIN_ORIGINAL 0
165 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
167 #define AR5416_EEP4K_START_LOC 64
168 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
169 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
170 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
171 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
172 #define AR5416_EEP4K_NUM_CTLS 12
173 #define AR5416_EEP4K_NUM_BAND_EDGES 4
174 #define AR5416_EEP4K_NUM_PD_GAINS 2
175 #define AR5416_EEP4K_PD_GAINS_IN_MASK 4
176 #define AR5416_EEP4K_PD_GAIN_ICEPTS 5
177 #define AR5416_EEP4K_MAX_CHAINS 1
179 #define AR9280_TX_GAIN_TABLE_SIZE 22
181 #define AR9287_EEP_VER 0xE
182 #define AR9287_EEP_VER_MINOR_MASK 0xFFF
183 #define AR9287_EEP_MINOR_VER_1 0x1
184 #define AR9287_EEP_MINOR_VER_2 0x2
185 #define AR9287_EEP_MINOR_VER_3 0x3
186 #define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3
187 #define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER
188 #define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1
190 #define AR9287_EEP_START_LOC 128
191 #define AR9287_NUM_2G_CAL_PIERS 3
192 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
193 #define AR9287_NUM_2G_20_TARGET_POWERS 3
194 #define AR9287_NUM_2G_40_TARGET_POWERS 3
195 #define AR9287_NUM_CTLS 12
196 #define AR9287_NUM_BAND_EDGES 4
197 #define AR9287_NUM_PD_GAINS 4
198 #define AR9287_PD_GAINS_IN_MASK 4
199 #define AR9287_PD_GAIN_ICEPTS 1
200 #define AR9287_EEPROM_MODAL_SPURS 5
201 #define AR9287_MAX_RATE_POWER 63
202 #define AR9287_NUM_PDADC_VALUES 128
203 #define AR9287_NUM_RATES 16
204 #define AR9287_BCHAN_UNUSED 0xFF
205 #define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
206 #define AR9287_OPFLAGS_11A 0x01
207 #define AR9287_OPFLAGS_11G 0x02
208 #define AR9287_OPFLAGS_2G_HT40 0x08
209 #define AR9287_OPFLAGS_2G_HT20 0x20
210 #define AR9287_OPFLAGS_5G_HT40 0x04
211 #define AR9287_OPFLAGS_5G_HT20 0x10
212 #define AR9287_EEPMISC_BIG_ENDIAN 0x01
213 #define AR9287_EEPMISC_WOW 0x02
214 #define AR9287_MAX_CHAINS 2
215 #define AR9287_ANT_16S 32
216 #define AR9287_custdatasize 20
218 #define AR9287_NUM_ANT_CHAIN_FIELDS 6
219 #define AR9287_NUM_ANT_COMMON_FIELDS 4
220 #define AR9287_SIZE_ANT_CHAIN_FIELD 2
221 #define AR9287_SIZE_ANT_COMMON_FIELD 4
222 #define AR9287_ANT_CHAIN_MASK 0x3
223 #define AR9287_ANT_COMMON_MASK 0xf
224 #define AR9287_CHAIN_0_IDX 0
225 #define AR9287_CHAIN_1_IDX 1
226 #define AR9287_DATA_SZ 32
228 #define AR9287_PWR_TABLE_OFFSET_DB -5
230 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
258 EEP_TEMPSENSE_SLOPE_PAL_ON,
263 rate6mb, rate9mb, rate12mb, rate18mb,
264 rate24mb, rate36mb, rate48mb, rate54mb,
265 rate1l, rate2l, rate2s, rate5_5l,
266 rate5_5s, rate11l, rate11s, rateXr,
267 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
268 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
269 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
270 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
271 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
275 enum ath9k_hal_freq_band {
276 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
277 ATH9K_HAL_FREQ_BAND_2GHZ = 1
280 struct base_eep_header {
291 u16 blueToothOptions;
304 u8 power_table_offset;
309 struct base_eep_header_4k {
320 u16 blueToothOptions;
334 struct modal_eep_header {
335 u32 antCtrlChain[AR5416_MAX_CHAINS];
337 u8 antennaGainCh[AR5416_MAX_CHAINS];
339 u8 txRxAttenCh[AR5416_MAX_CHAINS];
340 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
343 u8 xlnaGainCh[AR5416_MAX_CHAINS];
348 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
351 u8 iqCalICh[AR5416_MAX_CHAINS];
352 u8 iqCalQCh[AR5416_MAX_CHAINS];
357 u8 pwrDecreaseFor2Chain;
358 u8 pwrDecreaseFor3Chain;
359 u8 txFrameToDataStart;
361 u8 ht40PowerIncForPdadc;
362 u8 bswAtten[AR5416_MAX_CHAINS];
363 u8 bswMargin[AR5416_MAX_CHAINS];
365 u8 xatten2Db[AR5416_MAX_CHAINS];
366 u8 xatten2Margin[AR5416_MAX_CHAINS];
372 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
374 u16 xpaBiasLvlFreq[3];
377 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
380 struct calDataPerFreqOpLoop {
387 struct modal_eep_4k_header {
388 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
390 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
392 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
393 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
396 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
401 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
404 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
405 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
410 u8 txFrameToDataStart;
412 u8 ht40PowerIncForPdadc;
413 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
414 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
416 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
417 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
425 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
428 struct base_eep_ar9287_header {
439 u16 blueToothOptions;
444 int8_t pwrTableOffset;
445 int8_t tempSensSlope;
446 int8_t tempSensSlopePalOn;
450 struct modal_eep_ar9287_header {
451 u32 antCtrlChain[AR9287_MAX_CHAINS];
453 int8_t antennaGainCh[AR9287_MAX_CHAINS];
455 u8 txRxAttenCh[AR9287_MAX_CHAINS];
456 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
457 int8_t adcDesiredSize;
462 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
465 int8_t iqCalICh[AR9287_MAX_CHAINS];
466 int8_t iqCalQCh[AR9287_MAX_CHAINS];
469 u8 txFrameToDataStart;
471 u8 ht40PowerIncForPdadc;
472 u8 bswAtten[AR9287_MAX_CHAINS];
473 u8 bswMargin[AR9287_MAX_CHAINS];
483 struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
488 struct cal_data_per_freq {
489 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
490 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
493 struct cal_data_per_freq_4k {
494 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
495 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
498 struct cal_target_power_leg {
503 struct cal_target_power_ht {
509 #ifdef __BIG_ENDIAN_BITFIELD
510 struct cal_ctl_edges {
515 struct cal_ctl_edges {
521 struct cal_data_op_loop_ar9287 {
529 struct cal_data_per_freq_ar9287 {
530 u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
531 u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
534 union cal_data_per_freq_ar9287_u {
535 struct cal_data_op_loop_ar9287 calDataOpen;
536 struct cal_data_per_freq_ar9287 calDataClose;
539 struct cal_ctl_data_ar9287 {
541 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
544 struct cal_ctl_data {
546 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
549 struct cal_ctl_data_4k {
551 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
554 struct ar5416_eeprom_def {
555 struct base_eep_header baseEepHeader;
557 struct modal_eep_header modalHeader[2];
558 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
559 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
560 struct cal_data_per_freq
561 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
562 struct cal_data_per_freq
563 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
564 struct cal_target_power_leg
565 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
566 struct cal_target_power_ht
567 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
568 struct cal_target_power_ht
569 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
570 struct cal_target_power_leg
571 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
572 struct cal_target_power_leg
573 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
574 struct cal_target_power_ht
575 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
576 struct cal_target_power_ht
577 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
578 u8 ctlIndex[AR5416_NUM_CTLS];
579 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
583 struct ar5416_eeprom_4k {
584 struct base_eep_header_4k baseEepHeader;
586 struct modal_eep_4k_header modalHeader;
587 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
588 struct cal_data_per_freq_4k
589 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
590 struct cal_target_power_leg
591 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
592 struct cal_target_power_leg
593 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
594 struct cal_target_power_ht
595 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
596 struct cal_target_power_ht
597 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
598 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
599 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
603 struct ar9287_eeprom_t {
604 struct base_eep_ar9287_header baseEepHeader;
605 u8 custData[AR9287_DATA_SZ];
606 struct modal_eep_ar9287_header modalHeader;
607 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
608 union cal_data_per_freq_ar9287_u
609 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
610 struct cal_target_power_leg
611 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
612 struct cal_target_power_leg
613 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
614 struct cal_target_power_ht
615 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
616 struct cal_target_power_ht
617 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
618 u8 ctlIndex[AR9287_NUM_CTLS];
619 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
624 enum reg_ext_bitmap {
625 REG_EXT_JAPAN_MIDBAND = 1,
626 REG_EXT_FCC_DFS_HT40 = 2,
627 REG_EXT_JAPAN_NONDFS_HT40 = 3,
628 REG_EXT_JAPAN_DFS_HT40 = 4
631 struct ath9k_country_entry {
641 EEP_MAP_DEFAULT = 0x0,
648 int (*check_eeprom)(struct ath_hw *hw);
649 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
650 bool (*fill_eeprom)(struct ath_hw *hw);
651 int (*get_eeprom_ver)(struct ath_hw *hw);
652 int (*get_eeprom_rev)(struct ath_hw *hw);
653 u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
654 u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
655 struct ath9k_channel *chan);
656 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
657 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
658 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
659 u16 cfgCtl, u8 twiceAntennaReduction,
660 u8 twiceMaxRegulatoryPower, u8 powerLimit);
661 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
664 #define ar5416_get_ntxchains(_txchainmask) \
665 (((_txchainmask >> 2) & 1) + \
666 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
668 int ath9k_hw_eeprom_attach(struct ath_hw *ah);
670 #endif /* EEPROM_H */