2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #include <net/cfg80211.h>
22 #include "ar9003_eeprom.h"
24 #define AH_USE_EEPROM 0x1
27 #define AR5416_EEPROM_MAGIC 0x5aa5
29 #define AR5416_EEPROM_MAGIC 0xa55a
32 #define CTRY_DEBUG 0x1ff
33 #define CTRY_DEFAULT 0
35 #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
36 #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
37 #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
38 #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
39 #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
40 #define AR_EEPROM_EEPCAP_MAXQCU_S 4
41 #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
42 #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
43 #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
45 #define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
46 #define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
47 #define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
48 #define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
49 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
50 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
52 #define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
53 #define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
55 #define AR5416_EEPROM_MAGIC_OFFSET 0x0
56 #define AR5416_EEPROM_S 2
57 #define AR5416_EEPROM_OFFSET 0x2000
58 #define AR5416_EEPROM_MAX 0xae0
60 #define AR5416_EEPROM_START_ADDR \
61 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
63 #define SD_NO_CTL 0xE0
74 #define EXT_ADDITIVE (0x8000)
75 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
76 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
77 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
79 #define SUB_NUM_CTL_MODES_AT_5G_40 2
80 #define SUB_NUM_CTL_MODES_AT_2G_40 3
82 #define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */
83 #define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */
86 * For AR9285 and later chipsets, the following bits are not being programmed
87 * in EEPROM and so need to be enabled always.
91 * Bit 2: en_fcc_dfs_ht40
93 * Bit 4: en_jap_dfs_ht40
95 #define AR9285_RDEXT_DEFAULT 0x1F
97 #define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
98 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
99 #define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
101 #define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK)
102 #define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \
103 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
104 #define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_10_OR_LATER(ah) && \
105 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
107 #define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
108 #define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
109 #define AR_EEPROM_RFSILENT_POLARITY 0x0002
110 #define AR_EEPROM_RFSILENT_POLARITY_S 1
112 #define EEP_RFSILENT_ENABLED 0x0001
113 #define EEP_RFSILENT_ENABLED_S 0
114 #define EEP_RFSILENT_POLARITY 0x0002
115 #define EEP_RFSILENT_POLARITY_S 1
116 #define EEP_RFSILENT_GPIO_SEL 0x001c
117 #define EEP_RFSILENT_GPIO_SEL_S 2
119 #define AR5416_OPFLAGS_11A 0x01
120 #define AR5416_OPFLAGS_11G 0x02
121 #define AR5416_OPFLAGS_N_5G_HT40 0x04
122 #define AR5416_OPFLAGS_N_2G_HT40 0x08
123 #define AR5416_OPFLAGS_N_5G_HT20 0x10
124 #define AR5416_OPFLAGS_N_2G_HT20 0x20
126 #define AR5416_EEP_NO_BACK_VER 0x1
127 #define AR5416_EEP_VER 0xE
128 #define AR5416_EEP_VER_MINOR_MASK 0x0FFF
129 #define AR5416_EEP_MINOR_VER_2 0x2
130 #define AR5416_EEP_MINOR_VER_3 0x3
131 #define AR5416_EEP_MINOR_VER_7 0x7
132 #define AR5416_EEP_MINOR_VER_9 0x9
133 #define AR5416_EEP_MINOR_VER_16 0x10
134 #define AR5416_EEP_MINOR_VER_17 0x11
135 #define AR5416_EEP_MINOR_VER_19 0x13
136 #define AR5416_EEP_MINOR_VER_20 0x14
137 #define AR5416_EEP_MINOR_VER_21 0x15
138 #define AR5416_EEP_MINOR_VER_22 0x16
140 #define AR5416_NUM_5G_CAL_PIERS 8
141 #define AR5416_NUM_2G_CAL_PIERS 4
142 #define AR5416_NUM_5G_20_TARGET_POWERS 8
143 #define AR5416_NUM_5G_40_TARGET_POWERS 8
144 #define AR5416_NUM_2G_CCK_TARGET_POWERS 3
145 #define AR5416_NUM_2G_20_TARGET_POWERS 4
146 #define AR5416_NUM_2G_40_TARGET_POWERS 4
147 #define AR5416_NUM_CTLS 24
148 #define AR5416_NUM_BAND_EDGES 8
149 #define AR5416_NUM_PD_GAINS 4
150 #define AR5416_PD_GAINS_IN_MASK 4
151 #define AR5416_PD_GAIN_ICEPTS 5
152 #define AR5416_EEPROM_MODAL_SPURS 5
153 #define AR5416_MAX_RATE_POWER 63
154 #define AR5416_NUM_PDADC_VALUES 128
155 #define AR5416_BCHAN_UNUSED 0xFF
156 #define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
157 #define AR5416_MAX_CHAINS 3
158 #define AR9300_MAX_CHAINS 3
159 #define AR5416_PWR_TABLE_OFFSET_DB -5
161 /* Rx gain type values */
162 #define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
163 #define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
164 #define AR5416_EEP_RXGAIN_ORIG 2
166 /* Tx gain type values */
167 #define AR5416_EEP_TXGAIN_ORIGINAL 0
168 #define AR5416_EEP_TXGAIN_HIGH_POWER 1
170 #define AR5416_EEP4K_START_LOC 64
171 #define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
172 #define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
173 #define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
174 #define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
175 #define AR5416_EEP4K_NUM_CTLS 12
176 #define AR5416_EEP4K_NUM_BAND_EDGES 4
177 #define AR5416_EEP4K_NUM_PD_GAINS 2
178 #define AR5416_EEP4K_PD_GAINS_IN_MASK 4
179 #define AR5416_EEP4K_PD_GAIN_ICEPTS 5
180 #define AR5416_EEP4K_MAX_CHAINS 1
182 #define AR9280_TX_GAIN_TABLE_SIZE 22
184 #define AR9287_EEP_VER 0xE
185 #define AR9287_EEP_VER_MINOR_MASK 0xFFF
186 #define AR9287_EEP_MINOR_VER_1 0x1
187 #define AR9287_EEP_MINOR_VER_2 0x2
188 #define AR9287_EEP_MINOR_VER_3 0x3
189 #define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3
190 #define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER
191 #define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1
193 #define AR9287_EEP_START_LOC 128
194 #define AR9287_HTC_EEP_START_LOC 256
195 #define AR9287_NUM_2G_CAL_PIERS 3
196 #define AR9287_NUM_2G_CCK_TARGET_POWERS 3
197 #define AR9287_NUM_2G_20_TARGET_POWERS 3
198 #define AR9287_NUM_2G_40_TARGET_POWERS 3
199 #define AR9287_NUM_CTLS 12
200 #define AR9287_NUM_BAND_EDGES 4
201 #define AR9287_NUM_PD_GAINS 4
202 #define AR9287_PD_GAINS_IN_MASK 4
203 #define AR9287_PD_GAIN_ICEPTS 1
204 #define AR9287_EEPROM_MODAL_SPURS 5
205 #define AR9287_MAX_RATE_POWER 63
206 #define AR9287_NUM_PDADC_VALUES 128
207 #define AR9287_NUM_RATES 16
208 #define AR9287_BCHAN_UNUSED 0xFF
209 #define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64
210 #define AR9287_OPFLAGS_11A 0x01
211 #define AR9287_OPFLAGS_11G 0x02
212 #define AR9287_OPFLAGS_2G_HT40 0x08
213 #define AR9287_OPFLAGS_2G_HT20 0x20
214 #define AR9287_OPFLAGS_5G_HT40 0x04
215 #define AR9287_OPFLAGS_5G_HT20 0x10
216 #define AR9287_EEPMISC_BIG_ENDIAN 0x01
217 #define AR9287_EEPMISC_WOW 0x02
218 #define AR9287_MAX_CHAINS 2
219 #define AR9287_ANT_16S 32
220 #define AR9287_custdatasize 20
222 #define AR9287_NUM_ANT_CHAIN_FIELDS 6
223 #define AR9287_NUM_ANT_COMMON_FIELDS 4
224 #define AR9287_SIZE_ANT_CHAIN_FIELD 2
225 #define AR9287_SIZE_ANT_COMMON_FIELD 4
226 #define AR9287_ANT_CHAIN_MASK 0x3
227 #define AR9287_ANT_COMMON_MASK 0xf
228 #define AR9287_CHAIN_0_IDX 0
229 #define AR9287_CHAIN_1_IDX 1
230 #define AR9287_DATA_SZ 32
232 #define AR9287_PWR_TABLE_OFFSET_DB -5
234 #define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1)
263 EEP_TEMPSENSE_SLOPE_PAL_ON,
264 EEP_PWR_TABLE_OFFSET,
266 EEP_INTERNAL_REGULATOR,
272 rate6mb, rate9mb, rate12mb, rate18mb,
273 rate24mb, rate36mb, rate48mb, rate54mb,
274 rate1l, rate2l, rate2s, rate5_5l,
275 rate5_5s, rate11l, rate11s, rateXr,
276 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
277 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
278 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
279 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
280 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
284 enum ath9k_hal_freq_band {
285 ATH9K_HAL_FREQ_BAND_5GHZ = 0,
286 ATH9K_HAL_FREQ_BAND_2GHZ = 1
289 struct base_eep_header {
300 u16 blueToothOptions;
319 struct base_eep_header_4k {
330 u16 blueToothOptions;
344 struct modal_eep_header {
345 u32 antCtrlChain[AR5416_MAX_CHAINS];
347 u8 antennaGainCh[AR5416_MAX_CHAINS];
349 u8 txRxAttenCh[AR5416_MAX_CHAINS];
350 u8 rxTxMarginCh[AR5416_MAX_CHAINS];
353 u8 xlnaGainCh[AR5416_MAX_CHAINS];
358 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
361 u8 iqCalICh[AR5416_MAX_CHAINS];
362 u8 iqCalQCh[AR5416_MAX_CHAINS];
367 u8 pwrDecreaseFor2Chain;
368 u8 pwrDecreaseFor3Chain;
369 u8 txFrameToDataStart;
371 u8 ht40PowerIncForPdadc;
372 u8 bswAtten[AR5416_MAX_CHAINS];
373 u8 bswMargin[AR5416_MAX_CHAINS];
375 u8 xatten2Db[AR5416_MAX_CHAINS];
376 u8 xatten2Margin[AR5416_MAX_CHAINS];
382 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
384 u16 xpaBiasLvlFreq[3];
387 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
390 struct calDataPerFreqOpLoop {
397 struct modal_eep_4k_header {
398 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
400 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
402 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
403 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
406 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
411 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
414 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
415 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
417 #ifdef __BIG_ENDIAN_BITFIELD
425 u8 txFrameToDataStart;
427 u8 ht40PowerIncForPdadc;
428 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
429 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
431 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
432 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
433 #ifdef __BIG_ENDIAN_BITFIELD
439 #ifdef __BIG_ENDIAN_BITFIELD
441 u8 antdiv_ctl1:4, ob_4:4;
443 u8 antdiv_ctl2:4, db1_4:4;
445 u8 reserved:4, db2_4:4;
448 u8 ob_4:4, antdiv_ctl1:4;
450 u8 db1_4:4, antdiv_ctl2:4;
452 u8 db2_4:4, reserved:4;
455 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
458 struct base_eep_ar9287_header {
469 u16 blueToothOptions;
474 int8_t pwrTableOffset;
475 int8_t tempSensSlope;
476 int8_t tempSensSlopePalOn;
480 struct modal_eep_ar9287_header {
481 u32 antCtrlChain[AR9287_MAX_CHAINS];
483 int8_t antennaGainCh[AR9287_MAX_CHAINS];
485 u8 txRxAttenCh[AR9287_MAX_CHAINS];
486 u8 rxTxMarginCh[AR9287_MAX_CHAINS];
487 int8_t adcDesiredSize;
492 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS];
495 int8_t iqCalICh[AR9287_MAX_CHAINS];
496 int8_t iqCalQCh[AR9287_MAX_CHAINS];
499 u8 txFrameToDataStart;
501 u8 ht40PowerIncForPdadc;
502 u8 bswAtten[AR9287_MAX_CHAINS];
503 u8 bswMargin[AR9287_MAX_CHAINS];
513 struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS];
516 struct cal_data_per_freq {
517 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
518 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
521 struct cal_data_per_freq_4k {
522 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
523 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
526 struct cal_target_power_leg {
531 struct cal_target_power_ht {
537 #ifdef __BIG_ENDIAN_BITFIELD
538 struct cal_ctl_edges {
543 struct cal_ctl_edges {
549 struct cal_data_op_loop_ar9287 {
556 struct cal_data_per_freq_ar9287 {
557 u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
558 u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS];
561 union cal_data_per_freq_ar9287_u {
562 struct cal_data_op_loop_ar9287 calDataOpen;
563 struct cal_data_per_freq_ar9287 calDataClose;
566 struct cal_ctl_data_ar9287 {
568 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES];
571 struct cal_ctl_data {
573 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
576 struct cal_ctl_data_4k {
578 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
581 struct ar5416_eeprom_def {
582 struct base_eep_header baseEepHeader;
584 struct modal_eep_header modalHeader[2];
585 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
586 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
587 struct cal_data_per_freq
588 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
589 struct cal_data_per_freq
590 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
591 struct cal_target_power_leg
592 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
593 struct cal_target_power_ht
594 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
595 struct cal_target_power_ht
596 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
597 struct cal_target_power_leg
598 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
599 struct cal_target_power_leg
600 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
601 struct cal_target_power_ht
602 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
603 struct cal_target_power_ht
604 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
605 u8 ctlIndex[AR5416_NUM_CTLS];
606 struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
610 struct ar5416_eeprom_4k {
611 struct base_eep_header_4k baseEepHeader;
613 struct modal_eep_4k_header modalHeader;
614 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
615 struct cal_data_per_freq_4k
616 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
617 struct cal_target_power_leg
618 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
619 struct cal_target_power_leg
620 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
621 struct cal_target_power_ht
622 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
623 struct cal_target_power_ht
624 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
625 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
626 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
630 struct ar9287_eeprom {
631 struct base_eep_ar9287_header baseEepHeader;
632 u8 custData[AR9287_DATA_SZ];
633 struct modal_eep_ar9287_header modalHeader;
634 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS];
635 union cal_data_per_freq_ar9287_u
636 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS];
637 struct cal_target_power_leg
638 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS];
639 struct cal_target_power_leg
640 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS];
641 struct cal_target_power_ht
642 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS];
643 struct cal_target_power_ht
644 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS];
645 u8 ctlIndex[AR9287_NUM_CTLS];
646 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS];
650 enum reg_ext_bitmap {
651 REG_EXT_FCC_MIDBAND = 0,
652 REG_EXT_JAPAN_MIDBAND = 1,
653 REG_EXT_FCC_DFS_HT40 = 2,
654 REG_EXT_JAPAN_NONDFS_HT40 = 3,
655 REG_EXT_JAPAN_DFS_HT40 = 4
658 struct ath9k_country_entry {
668 int (*check_eeprom)(struct ath_hw *hw);
669 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
670 bool (*fill_eeprom)(struct ath_hw *hw);
671 int (*get_eeprom_ver)(struct ath_hw *hw);
672 int (*get_eeprom_rev)(struct ath_hw *hw);
673 u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
674 u32 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
675 struct ath9k_channel *chan);
676 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
677 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
678 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
679 u16 cfgCtl, u8 twiceAntennaReduction,
680 u8 twiceMaxRegulatoryPower, u8 powerLimit);
681 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
684 void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val);
685 void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask,
687 int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight,
689 int16_t targetRight);
690 bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize,
691 u16 *indexL, u16 *indexR);
692 bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data);
693 void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList,
694 u8 *pVpdList, u16 numIntercepts,
696 void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah,
697 struct ath9k_channel *chan,
698 struct cal_target_power_leg *powInfo,
700 struct cal_target_power_leg *pNewPower,
701 u16 numRates, bool isExtTarget);
702 void ath9k_hw_get_target_powers(struct ath_hw *ah,
703 struct ath9k_channel *chan,
704 struct cal_target_power_ht *powInfo,
706 struct cal_target_power_ht *pNewPower,
707 u16 numRates, bool isHt40Target);
708 u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower,
709 bool is2GHz, int num_band_edges);
710 void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah);
711 int ath9k_hw_eeprom_init(struct ath_hw *ah);
713 #define ar5416_get_ntxchains(_txchainmask) \
714 (((_txchainmask >> 2) & 1) + \
715 ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
717 extern const struct eeprom_ops eep_def_ops;
718 extern const struct eeprom_ops eep_4k_ops;
719 extern const struct eeprom_ops eep_ar9287_ops;
720 extern const struct eeprom_ops eep_ar9287_ops;
721 extern const struct eeprom_ops eep_ar9300_ops;
723 #endif /* EEPROM_H */