2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
26 #ifdef CONFIG_ATH9K_DEBUGFS
27 #define TX_STAT_INC(q, c) sc->debug.stats.txstats[q].c++
29 #define TX_STAT_INC(q, c) do { } while (0)
32 #ifdef CONFIG_ATH9K_DEBUGFS
35 * struct ath_interrupt_stats - Contains statistics about interrupts
36 * @total: Total no. of interrupts generated so far
37 * @rxok: RX with no errors
38 * @rxlp: RX with low priority RX
39 * @rxhp: RX with high priority, uapsd only
40 * @rxeol: RX with no more RXDESC available
41 * @rxorn: RX FIFO overrun
42 * @txok: TX completed at the requested rate
43 * @txurn: TX FIFO underrun
44 * @mib: MIB regs reaching its threshold
45 * @rxphyerr: RX with phy errors
46 * @rx_keycache_miss: RX with key cache misses
47 * @swba: Software Beacon Alert
49 * @bnr: Beacon Not Ready
50 * @cst: Carrier Sense TImeout
51 * @gtt: Global TX Timeout
52 * @tim: RX beacon TIM occurrence
53 * @cabend: RX End of CAB traffic
54 * @dtimsync: DTIM sync lossage
55 * @dtim: RX Beacon with DTIM
56 * @bb_watchdog: Baseband watchdog
57 * @tsfoor: TSF out of range, indicates that the corrected TSF received
58 * from a beacon differs from the PCU's internal TSF by more than a
59 * (programmable) threshold
61 struct ath_interrupt_stats {
88 * struct ath_tx_stats - Statistics about TX
89 * @tx_pkts_all: No. of total frames transmitted, including ones that
91 * @tx_bytes_all: No. of total bytes transmitted, including ones that
93 * @queued: Total MPDUs (non-aggr) queued
94 * @completed: Total MPDUs (non-aggr) completed
95 * @a_aggr: Total no. of aggregates queued
96 * @a_queued_hw: Total AMPDUs queued to hardware
97 * @a_queued_sw: Total AMPDUs queued to software queues
98 * @a_completed: Total AMPDUs completed
99 * @a_retries: No. of AMPDUs retried (SW)
100 * @a_xretries: No. of AMPDUs dropped due to xretries
101 * @fifo_underrun: FIFO underrun occurrences
103 - non-aggregate condition.
104 - first packet of aggregate.
105 * @xtxop: No. of frames filtered because of TXOP limit
106 * @timer_exp: Transmit timer expiry
107 * @desc_cfg_err: Descriptor configuration errors
108 * @data_urn: TX data underrun errors
109 * @delim_urn: TX delimiter underrun errors
110 * @puttxbuf: Number of times hardware was given txbuf to write.
111 * @txstart: Number of times hardware was told to start tx.
112 * @txprocdesc: Number of times tx descriptor was processed
114 struct ath_tx_stats {
138 * struct ath_rx_stats - RX Statistics
139 * @rx_pkts_all: No. of total frames received, including ones that
141 * @rx_bytes_all: No. of total bytes received, including ones that
143 * @crc_err: No. of frames with incorrect CRC value
144 * @decrypt_crc_err: No. of frames whose CRC check failed after
145 decryption process completed
146 * @phy_err: No. of frames whose reception failed because the PHY
148 * @mic_err: No. of frames with incorrect TKIP MIC verification failure
149 * @pre_delim_crc_err: Pre-Frame delimiter CRC error detections
150 * @post_delim_crc_err: Post-Frame delimiter CRC error detections
151 * @decrypt_busy_err: Decryption interruptions counter
152 * @phy_err_stats: Individual PHY error statistics
154 struct ath_rx_stats {
161 u32 pre_delim_crc_err;
162 u32 post_delim_crc_err;
163 u32 decrypt_busy_err;
164 u32 phy_err_stats[ATH9K_PHYERR_MAX];
175 struct ath_interrupt_stats istats;
176 struct ath_tx_stats txstats[ATH9K_NUM_TX_QUEUES];
177 struct ath_rx_stats rxstats;
180 #define ATH_DBG_MAX_SAMPLES 10
181 struct ath_dbg_bb_mac_samp {
182 u32 dma_dbg_reg_vals[ATH9K_NUM_DMA_DEBUG_REGS];
183 u32 pcu_obs, pcu_cr, noise;
199 } ts[ATH_DBG_MAX_SAMPLES];
212 } rs[ATH_DBG_MAX_SAMPLES];
213 struct ath_cycle_counters cc;
214 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
218 struct dentry *debugfs_phy;
220 struct ath_stats stats;
221 spinlock_t samp_lock;
222 struct ath_dbg_bb_mac_samp bb_mac_samp[ATH_DBG_MAX_SAMPLES];
228 int ath9k_init_debug(struct ath_hw *ah);
230 void ath9k_debug_samp_bb_mac(struct ath_softc *sc);
231 void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
232 void ath_debug_stat_tx(struct ath_softc *sc, struct ath_buf *bf,
233 struct ath_tx_status *ts, struct ath_txq *txq,
235 void ath_debug_stat_rx(struct ath_softc *sc, struct ath_rx_status *rs);
239 static inline int ath9k_init_debug(struct ath_hw *ah)
244 static inline void ath9k_debug_samp_bb_mac(struct ath_softc *sc)
248 static inline void ath_debug_stat_interrupt(struct ath_softc *sc,
249 enum ath9k_int status)
253 static inline void ath_debug_stat_tx(struct ath_softc *sc,
255 struct ath_tx_status *ts,
261 static inline void ath_debug_stat_rx(struct ath_softc *sc,
262 struct ath_rx_status *rs)
266 #endif /* CONFIG_ATH9K_DEBUGFS */