drivers/net/wireless/ath/ath9k/ar9003_phy.c

   1 /*
   2  * Copyright (c) 2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_phy.h"
  19
  20 /**
  21  * ar9003_hw_set_channel - set channel on single-chip device
  22  * @ah: atheros hardware structure
  23  * @chan:
  24  *
  25  * This is the function to change channel on single-chip devices, that is
  26  * all devices after ar9280.
  27  *
  28  * This function takes the channel value in MHz and sets
  29  * hardware channel value. Assumes writes have been enabled to analog bus.
  30  *
  31  * Actual Expression,
  32  *
  33  * For 2GHz channel,
  34  * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  35  * (freq_ref = 40MHz)
  36  *
  37  * For 5GHz channel,
  38  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
  39  * (freq_ref = 40MHz/(24>>amodeRefSel))
  40  *
  41  * For 5GHz channels which are 5MHz spaced,
  42  * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
  43  * (freq_ref = 40MHz)
  44  */
  45 static int ar9003_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
  46 {
  47         u16 bMode, fracMode = 0, aModeRefSel = 0;
  48         u32 freq, channelSel = 0, reg32 = 0;
  49         struct chan_centers centers;
  50         int loadSynthChannel;
  51
  52         ath9k_hw_get_channel_centers(ah, chan, &centers);
  53         freq = centers.synth_center;
  54
  55         if (freq < 4800) {     /* 2 GHz, fractional mode */
  56                 channelSel = CHANSEL_2G(freq);
  57                 /* Set to 2G mode */
  58                 bMode = 1;
  59         } else {
  60                 channelSel = CHANSEL_5G(freq);
  61                 /* Doubler is ON, so, divide channelSel by 2. */
  62                 channelSel >>= 1;
  63                 /* Set to 5G mode */
  64                 bMode = 0;
  65         }
  66
  67         /* Enable fractional mode for all channels */
  68         fracMode = 1;
  69         aModeRefSel = 0;
  70         loadSynthChannel = 0;
  71
  72         reg32 = (bMode << 29);
  73         REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
  74
  75         /* Enable Long shift Select for Synthesizer */
  76         REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_SYNTH4,
  77                       AR_PHY_SYNTH4_LONG_SHIFT_SELECT, 1);
  78
  79         /* Program Synth. setting */
  80         reg32 = (channelSel << 2) | (fracMode << 30) |
  81                 (aModeRefSel << 28) | (loadSynthChannel << 31);
  82         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
  83
  84         /* Toggle Load Synth channel bit */
  85         loadSynthChannel = 1;
  86         reg32 = (channelSel << 2) | (fracMode << 30) |
  87                 (aModeRefSel << 28) | (loadSynthChannel << 31);
  88         REG_WRITE(ah, AR_PHY_65NM_CH0_SYNTH7, reg32);
  89
  90         ah->curchan = chan;
  91         ah->curchan_rad_index = -1;
  92
  93         return 0;
  94 }
  95
  96 /**
  97  * ar9003_hw_spur_mitigate - convert baseband spur frequency
  98  * @ah: atheros hardware structure
  99  * @chan:
 100  *
 101  * For single-chip solutions. Converts to baseband spur frequency given the
 102  * input channel frequency and compute register settings below.
 103  *
 104  * Spur mitigation for MRC CCK
 105  */
 106 static void ar9003_hw_spur_mitigate_mrc_cck(struct ath_hw *ah,
 107                                             struct ath9k_channel *chan)
 108 {
 109         u32 spur_freq[4] = { 2420, 2440, 2464, 2480 };
 110         int cur_bb_spur, negative = 0, cck_spur_freq;
 111         int i;
 112
 113         /*
 114          * Need to verify range +/- 10 MHz in control channel, otherwise spur
 115          * is out-of-band and can be ignored.
 116          */
 117
 118         for (i = 0; i < 4; i++) {
 119                 negative = 0;
 120                 cur_bb_spur = spur_freq[i] - chan->channel;
 121
 122                 if (cur_bb_spur < 0) {
 123                         negative = 1;
 124                         cur_bb_spur = -cur_bb_spur;
 125                 }
 126                 if (cur_bb_spur < 10) {
 127                         cck_spur_freq = (int)((cur_bb_spur << 19) / 11);
 128
 129                         if (negative == 1)
 130                                 cck_spur_freq = -cck_spur_freq;
 131
 132                         cck_spur_freq = cck_spur_freq & 0xfffff;
 133
 134                         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 135                                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x7);
 136                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 137                                       AR_PHY_CCK_SPUR_MIT_SPUR_RSSI_THR, 0x7f);
 138                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 139                                       AR_PHY_CCK_SPUR_MIT_SPUR_FILTER_TYPE,
 140                                       0x2);
 141                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 142                                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT,
 143                                       0x1);
 144                         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 145                                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ,
 146                                       cck_spur_freq);
 147
 148                         return;
 149                 }
 150         }
 151
 152         REG_RMW_FIELD(ah, AR_PHY_AGC_CONTROL,
 153                       AR_PHY_AGC_CONTROL_YCOK_MAX, 0x5);
 154         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 155                       AR_PHY_CCK_SPUR_MIT_USE_CCK_SPUR_MIT, 0x0);
 156         REG_RMW_FIELD(ah, AR_PHY_CCK_SPUR_MIT,
 157                       AR_PHY_CCK_SPUR_MIT_CCK_SPUR_FREQ, 0x0);
 158 }
 159
 160 /* Clean all spur register fields */
 161 static void ar9003_hw_spur_ofdm_clear(struct ath_hw *ah)
 162 {
 163         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 164                       AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0);
 165         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 166                       AR_PHY_TIMING11_SPUR_FREQ_SD, 0);
 167         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 168                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, 0);
 169         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 170                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, 0);
 171         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 172                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0);
 173         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 174                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0);
 175         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 176                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0);
 177         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 178                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 0);
 179         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 180                       AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 0);
 181
 182         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 183                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0);
 184         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 185                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0);
 186         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 187                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0);
 188         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 189                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, 0);
 190         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 191                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, 0);
 192         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 193                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, 0);
 194         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 195                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0);
 196         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 197                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0);
 198         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 199                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0);
 200         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 201                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0);
 202 }
 203
 204 static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
 205                                 int freq_offset,
 206                                 int spur_freq_sd,
 207                                 int spur_delta_phase,
 208                                 int spur_subchannel_sd)
 209 {
 210         int mask_index = 0;
 211
 212         /* OFDM Spur mitigation */
 213         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 214                  AR_PHY_TIMING4_ENABLE_SPUR_FILTER, 0x1);
 215         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 216                       AR_PHY_TIMING11_SPUR_FREQ_SD, spur_freq_sd);
 217         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 218                       AR_PHY_TIMING11_SPUR_DELTA_PHASE, spur_delta_phase);
 219         REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 220                       AR_PHY_SFCORR_EXT_SPUR_SUBCHANNEL_SD, spur_subchannel_sd);
 221         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 222                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_AGC, 0x1);
 223         REG_RMW_FIELD(ah, AR_PHY_TIMING11,
 224                       AR_PHY_TIMING11_USE_SPUR_FILTER_IN_SELFCOR, 0x1);
 225         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 226                       AR_PHY_TIMING4_ENABLE_SPUR_RSSI, 0x1);
 227         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 228                       AR_PHY_SPUR_REG_SPUR_RSSI_THRESH, 34);
 229         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 230                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 231
 232         if (REG_READ_FIELD(ah, AR_PHY_MODE,
 233                            AR_PHY_MODE_DYNAMIC) == 0x1)
 234                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 235                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
 236
 237         mask_index = (freq_offset << 4) / 5;
 238         if (mask_index < 0)
 239                 mask_index = mask_index - 1;
 240
 241         mask_index = mask_index & 0x7f;
 242
 243         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 244                       AR_PHY_SPUR_REG_ENABLE_MASK_PPM, 0x1);
 245         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 246                       AR_PHY_TIMING4_ENABLE_PILOT_MASK, 0x1);
 247         REG_RMW_FIELD(ah, AR_PHY_TIMING4,
 248                       AR_PHY_TIMING4_ENABLE_CHAN_MASK, 0x1);
 249         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 250                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A, mask_index);
 251         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 252                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_IDX_A, mask_index);
 253         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 254                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A, mask_index);
 255         REG_RMW_FIELD(ah, AR_PHY_PILOT_SPUR_MASK,
 256                       AR_PHY_PILOT_SPUR_MASK_CF_PILOT_MASK_A, 0xc);
 257         REG_RMW_FIELD(ah, AR_PHY_CHAN_SPUR_MASK,
 258                       AR_PHY_CHAN_SPUR_MASK_CF_CHAN_MASK_A, 0xc);
 259         REG_RMW_FIELD(ah, AR_PHY_SPUR_MASK_A,
 260                       AR_PHY_SPUR_MASK_A_CF_PUNC_MASK_A, 0xa0);
 261         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
 262                       AR_PHY_SPUR_REG_MASK_RATE_CNTL, 0xff);
 263 }
 264
 265 static void ar9003_hw_spur_ofdm_work(struct ath_hw *ah,
 266                                      struct ath9k_channel *chan,
 267                                      int freq_offset)
 268 {
 269         int spur_freq_sd = 0;
 270         int spur_subchannel_sd = 0;
 271         int spur_delta_phase = 0;
 272
 273         if (IS_CHAN_HT40(chan)) {
 274                 if (freq_offset < 0) {
 275                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 276                                            AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 277                                 spur_subchannel_sd = 1;
 278                         else
 279                                 spur_subchannel_sd = 0;
 280
 281                         spur_freq_sd = ((freq_offset + 10) << 9) / 11;
 282
 283                 } else {
 284                         if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 285                             AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 286                                 spur_subchannel_sd = 0;
 287                         else
 288                                 spur_subchannel_sd = 1;
 289
 290                         spur_freq_sd = ((freq_offset - 10) << 9) / 11;
 291
 292                 }
 293
 294                 spur_delta_phase = (freq_offset << 17) / 5;
 295
 296         } else {
 297                 spur_subchannel_sd = 0;
 298                 spur_freq_sd = (freq_offset << 9) /11;
 299                 spur_delta_phase = (freq_offset << 18) / 5;
 300         }
 301
 302         spur_freq_sd = spur_freq_sd & 0x3ff;
 303         spur_delta_phase = spur_delta_phase & 0xfffff;
 304
 305         ar9003_hw_spur_ofdm(ah,
 306                             freq_offset,
 307                             spur_freq_sd,
 308                             spur_delta_phase,
 309                             spur_subchannel_sd);
 310 }
 311
 312 /* Spur mitigation for OFDM */
 313 static void ar9003_hw_spur_mitigate_ofdm(struct ath_hw *ah,
 314                                          struct ath9k_channel *chan)
 315 {
 316         int synth_freq;
 317         int range = 10;
 318         int freq_offset = 0;
 319         int mode;
 320         u8* spurChansPtr;
 321         unsigned int i;
 322         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
 323
 324         if (IS_CHAN_5GHZ(chan)) {
 325                 spurChansPtr = &(eep->modalHeader5G.spurChans[0]);
 326                 mode = 0;
 327         }
 328         else {
 329                 spurChansPtr = &(eep->modalHeader2G.spurChans[0]);
 330                 mode = 1;
 331         }
 332
 333         if (spurChansPtr[0] == 0)
 334                 return; /* No spur in the mode */
 335
 336         if (IS_CHAN_HT40(chan)) {
 337                 range = 19;
 338                 if (REG_READ_FIELD(ah, AR_PHY_GEN_CTRL,
 339                                    AR_PHY_GC_DYN2040_PRI_CH) == 0x0)
 340                         synth_freq = chan->channel - 10;
 341                 else
 342                         synth_freq = chan->channel + 10;
 343         } else {
 344                 range = 10;
 345                 synth_freq = chan->channel;
 346         }
 347
 348         ar9003_hw_spur_ofdm_clear(ah);
 349
 350         for (i = 0; spurChansPtr[i] && i < 5; i++) {
 351                 freq_offset = FBIN2FREQ(spurChansPtr[i], mode) - synth_freq;
 352                 if (abs(freq_offset) < range) {
 353                         ar9003_hw_spur_ofdm_work(ah, chan, freq_offset);
 354                         break;
 355                 }
 356         }
 357 }
 358
 359 static void ar9003_hw_spur_mitigate(struct ath_hw *ah,
 360                                     struct ath9k_channel *chan)
 361 {
 362         ar9003_hw_spur_mitigate_mrc_cck(ah, chan);
 363         ar9003_hw_spur_mitigate_ofdm(ah, chan);
 364 }
 365
 366 static u32 ar9003_hw_compute_pll_control(struct ath_hw *ah,
 367                                          struct ath9k_channel *chan)
 368 {
 369         u32 pll;
 370
 371         pll = SM(0x5, AR_RTC_9300_PLL_REFDIV);
 372
 373         if (chan && IS_CHAN_HALF_RATE(chan))
 374                 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL);
 375         else if (chan && IS_CHAN_QUARTER_RATE(chan))
 376                 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL);
 377
 378         if (chan && IS_CHAN_5GHZ(chan)) {
 379                 pll |= SM(0x28, AR_RTC_9300_PLL_DIV);
 380
 381                 /*
 382                  * When doing fast clock, set PLL to 0x142c
 383                  */
 384                 if (IS_CHAN_A_5MHZ_SPACED(chan))
 385                         pll = 0x142c;
 386         } else
 387                 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV);
 388
 389         return pll;
 390 }
 391
 392 static void ar9003_hw_set_channel_regs(struct ath_hw *ah,
 393                                        struct ath9k_channel *chan)
 394 {
 395         u32 phymode;
 396         u32 enableDacFifo = 0;
 397
 398         enableDacFifo =
 399                 (REG_READ(ah, AR_PHY_GEN_CTRL) & AR_PHY_GC_ENABLE_DAC_FIFO);
 400
 401         /* Enable 11n HT, 20 MHz */
 402         phymode = AR_PHY_GC_HT_EN | AR_PHY_GC_SINGLE_HT_LTF1 | AR_PHY_GC_WALSH |
 403                   AR_PHY_GC_SHORT_GI_40 | enableDacFifo;
 404
 405         /* Configure baseband for dynamic 20/40 operation */
 406         if (IS_CHAN_HT40(chan)) {
 407                 phymode |= AR_PHY_GC_DYN2040_EN;
 408                 /* Configure control (primary) channel at +-10MHz */
 409                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 410                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 411                         phymode |= AR_PHY_GC_DYN2040_PRI_CH;
 412
 413         }
 414
 415         /* make sure we preserve INI settings */
 416         phymode |= REG_READ(ah, AR_PHY_GEN_CTRL);
 417         /* turn off Green Field detection for STA for now */
 418         phymode &= ~AR_PHY_GC_GF_DETECT_EN;
 419
 420         REG_WRITE(ah, AR_PHY_GEN_CTRL, phymode);
 421
 422         /* Configure MAC for 20/40 operation */
 423         ath9k_hw_set11nmac2040(ah);
 424
 425         /* global transmit timeout (25 TUs default)*/
 426         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 427         /* carrier sense timeout */
 428         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 429 }
 430
 431 static void ar9003_hw_init_bb(struct ath_hw *ah,
 432                               struct ath9k_channel *chan)
 433 {
 434         u32 synthDelay;
 435
 436         /*
 437          * Wait for the frequency synth to settle (synth goes on
 438          * via AR_PHY_ACTIVE_EN).  Read the phy active delay register.
 439          * Value is in 100ns increments.
 440          */
 441         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 442         if (IS_CHAN_B(chan))
 443                 synthDelay = (4 * synthDelay) / 22;
 444         else
 445                 synthDelay /= 10;
 446
 447         /* Activate the PHY (includes baseband activate + synthesizer on) */
 448         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 449
 450         /*
 451          * There is an issue if the AP starts the calibration before
 452          * the base band timeout completes.  This could result in the
 453          * rx_clear false triggering.  As a workaround we add delay an
 454          * extra BASE_ACTIVATE_DELAY usecs to ensure this condition
 455          * does not happen.
 456          */
 457         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 458 }
 459
 460 void ar9003_hw_set_chain_masks(struct ath_hw *ah, u8 rx, u8 tx)
 461 {
 462         switch (rx) {
 463         case 0x5:
 464                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 465                             AR_PHY_SWAP_ALT_CHAIN);
 466         case 0x3:
 467         case 0x1:
 468         case 0x2:
 469         case 0x7:
 470                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx);
 471                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx);
 472                 break;
 473         default:
 474                 break;
 475         }
 476
 477         REG_WRITE(ah, AR_SELFGEN_MASK, tx);
 478         if (tx == 0x5) {
 479                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 480                             AR_PHY_SWAP_ALT_CHAIN);
 481         }
 482 }
 483
 484 /*
 485  * Override INI values with chip specific configuration.
 486  */
 487 static void ar9003_hw_override_ini(struct ath_hw *ah)
 488 {
 489         u32 val;
 490
 491         /*
 492          * Set the RX_ABORT and RX_DIS and clear it only after
 493          * RXE is set for MAC. This prevents frames with
 494          * corrupted descriptor status.
 495          */
 496         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 497
 498         /*
 499          * For AR9280 and above, there is a new feature that allows
 500          * Multicast search based on both MAC Address and Key ID. By default,
 501          * this feature is enabled. But since the driver is not using this
 502          * feature, we switch it off; otherwise multicast search based on
 503          * MAC addr only will fail.
 504          */
 505         val = REG_READ(ah, AR_PCU_MISC_MODE2) & (~AR_ADHOC_MCAST_KEYID_ENABLE);
 506         REG_WRITE(ah, AR_PCU_MISC_MODE2,
 507                   val | AR_AGG_WEP_ENABLE_FIX | AR_AGG_WEP_ENABLE);
 508 }
 509
 510 static void ar9003_hw_prog_ini(struct ath_hw *ah,
 511                                struct ar5416IniArray *iniArr,
 512                                int column)
 513 {
 514         unsigned int i, regWrites = 0;
 515
 516         /* New INI format: Array may be undefined (pre, core, post arrays) */
 517         if (!iniArr->ia_array)
 518                 return;
 519
 520         /*
 521          * New INI format: Pre, core, and post arrays for a given subsystem
 522          * may be modal (> 2 columns) or non-modal (2 columns). Determine if
 523          * the array is non-modal and force the column to 1.
 524          */
 525         if (column >= iniArr->ia_columns)
 526                 column = 1;
 527
 528         for (i = 0; i < iniArr->ia_rows; i++) {
 529                 u32 reg = INI_RA(iniArr, i, 0);
 530                 u32 val = INI_RA(iniArr, i, column);
 531
 532                 REG_WRITE(ah, reg, val);
 533
 534                 /*
 535                  * Determine if this is a shift register value, and insert the
 536                  * configured delay if so.
 537                  */
 538                 if (reg >= 0x16000 && reg < 0x17000
 539                     && ah->config.analog_shiftreg)
 540                         udelay(100);
 541
 542                 DO_DELAY(regWrites);
 543         }
 544 }
 545
 546 static int ar9003_hw_process_ini(struct ath_hw *ah,
 547                                  struct ath9k_channel *chan)
 548 {
 549         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 550         unsigned int regWrites = 0, i;
 551         struct ieee80211_channel *channel = chan->chan;
 552         u32 modesIndex, freqIndex;
 553
 554         switch (chan->chanmode) {
 555         case CHANNEL_A:
 556         case CHANNEL_A_HT20:
 557                 modesIndex = 1;
 558                 freqIndex = 1;
 559                 break;
 560         case CHANNEL_A_HT40PLUS:
 561         case CHANNEL_A_HT40MINUS:
 562                 modesIndex = 2;
 563                 freqIndex = 1;
 564                 break;
 565         case CHANNEL_G:
 566         case CHANNEL_G_HT20:
 567         case CHANNEL_B:
 568                 modesIndex = 4;
 569                 freqIndex = 2;
 570                 break;
 571         case CHANNEL_G_HT40PLUS:
 572         case CHANNEL_G_HT40MINUS:
 573                 modesIndex = 3;
 574                 freqIndex = 2;
 575                 break;
 576
 577         default:
 578                 return -EINVAL;
 579         }
 580
 581         for (i = 0; i < ATH_INI_NUM_SPLIT; i++) {
 582                 ar9003_hw_prog_ini(ah, &ah->iniSOC[i], modesIndex);
 583                 ar9003_hw_prog_ini(ah, &ah->iniMac[i], modesIndex);
 584                 ar9003_hw_prog_ini(ah, &ah->iniBB[i], modesIndex);
 585                 ar9003_hw_prog_ini(ah, &ah->iniRadio[i], modesIndex);
 586         }
 587
 588         REG_WRITE_ARRAY(&ah->iniModesRxGain, 1, regWrites);
 589         REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 590
 591         /*
 592          * For 5GHz channels requiring Fast Clock, apply
 593          * different modal values.
 594          */
 595         if (IS_CHAN_A_5MHZ_SPACED(chan))
 596                 REG_WRITE_ARRAY(&ah->iniModesAdditional,
 597                                 modesIndex, regWrites);
 598
 599         ar9003_hw_override_ini(ah);
 600         ar9003_hw_set_channel_regs(ah, chan);
 601         ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask);
 602
 603         /* Set TX power */
 604         ah->eep_ops->set_txpower(ah, chan,
 605                                  ath9k_regd_get_ctl(regulatory, chan),
 606                                  channel->max_antenna_gain * 2,
 607                                  channel->max_power * 2,
 608                                  min((u32) MAX_RATE_POWER,
 609                                  (u32) regulatory->power_limit));
 610
 611         return 0;
 612 }
 613
 614 static void ar9003_hw_set_rfmode(struct ath_hw *ah,
 615                                  struct ath9k_channel *chan)
 616 {
 617         u32 rfMode = 0;
 618
 619         if (chan == NULL)
 620                 return;
 621
 622         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 623                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 624
 625         if (IS_CHAN_A_5MHZ_SPACED(chan))
 626                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 627
 628         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 629 }
 630
 631 static void ar9003_hw_mark_phy_inactive(struct ath_hw *ah)
 632 {
 633         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 634 }
 635
 636 static void ar9003_hw_set_delta_slope(struct ath_hw *ah,
 637                                       struct ath9k_channel *chan)
 638 {
 639         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 640         u32 clockMhzScaled = 0x64000000;
 641         struct chan_centers centers;
 642
 643         /*
 644          * half and quarter rate can divide the scaled clock by 2 or 4
 645          * scale for selected channel bandwidth
 646          */
 647         if (IS_CHAN_HALF_RATE(chan))
 648                 clockMhzScaled = clockMhzScaled >> 1;
 649         else if (IS_CHAN_QUARTER_RATE(chan))
 650                 clockMhzScaled = clockMhzScaled >> 2;
 651
 652         /*
 653          * ALGO -> coef = 1e8/fcarrier*fclock/40;
 654          * scaled coef to provide precision for this floating calculation
 655          */
 656         ath9k_hw_get_channel_centers(ah, chan, &centers);
 657         coef_scaled = clockMhzScaled / centers.synth_center;
 658
 659         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 660                                       &ds_coef_exp);
 661
 662         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 663                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 664         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 665                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 666
 667         /*
 668          * For Short GI,
 669          * scaled coeff is 9/10 that of normal coeff
 670          */
 671         coef_scaled = (9 * coef_scaled) / 10;
 672
 673         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 674                                       &ds_coef_exp);
 675
 676         /* for short gi */
 677         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 678                       AR_PHY_SGI_DSC_MAN, ds_coef_man);
 679         REG_RMW_FIELD(ah, AR_PHY_SGI_DELTA,
 680                       AR_PHY_SGI_DSC_EXP, ds_coef_exp);
 681 }
 682
 683 static bool ar9003_hw_rfbus_req(struct ath_hw *ah)
 684 {
 685         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 686         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 687                              AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 688 }
 689
 690 /*
 691  * Wait for the frequency synth to settle (synth goes on via PHY_ACTIVE_EN).
 692  * Read the phy active delay register. Value is in 100ns increments.
 693  */
 694 static void ar9003_hw_rfbus_done(struct ath_hw *ah)
 695 {
 696         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 697         if (IS_CHAN_B(ah->curchan))
 698                 synthDelay = (4 * synthDelay) / 22;
 699         else
 700                 synthDelay /= 10;
 701
 702         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 703
 704         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 705 }
 706
 707 /*
 708  * Set the interrupt and GPIO values so the ISR can disable RF
 709  * on a switch signal.  Assumes GPIO port and interrupt polarity
 710  * are set prior to call.
 711  */
 712 static void ar9003_hw_enable_rfkill(struct ath_hw *ah)
 713 {
 714         /* Connect rfsilent_bb_l to baseband */
 715         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
 716                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
 717         /* Set input mux for rfsilent_bb_l to GPIO #0 */
 718         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
 719                     AR_GPIO_INPUT_MUX2_RFSILENT);
 720
 721         /*
 722          * Configure the desired GPIO port for input and
 723          * enable baseband rf silence.
 724          */
 725         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
 726         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
 727 }
 728
 729 static void ar9003_hw_set_diversity(struct ath_hw *ah, bool value)
 730 {
 731         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
 732         if (value)
 733                 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 734         else
 735                 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 736         REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
 737 }
 738
 739 static bool ar9003_hw_ani_control(struct ath_hw *ah,
 740                                   enum ath9k_ani_cmd cmd, int param)
 741 {
 742         struct ar5416AniState *aniState = ah->curani;
 743         struct ath_common *common = ath9k_hw_common(ah);
 744
 745         switch (cmd & ah->ani_function) {
 746         case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
 747                 u32 level = param;
 748
 749                 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
 750                         ath_print(common, ATH_DBG_ANI,
 751                                   "level out of range (%u > %u)\n",
 752                                   level,
 753                                   (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
 754                         return false;
 755                 }
 756
 757                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
 758                               AR_PHY_DESIRED_SZ_TOT_DES,
 759                               ah->totalSizeDesired[level]);
 760                 REG_RMW_FIELD(ah, AR_PHY_AGC,
 761                               AR_PHY_AGC_COARSE_LOW,
 762                               ah->coarse_low[level]);
 763                 REG_RMW_FIELD(ah, AR_PHY_AGC,
 764                               AR_PHY_AGC_COARSE_HIGH,
 765                               ah->coarse_high[level]);
 766                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
 767                               AR_PHY_FIND_SIG_FIRPWR, ah->firpwr[level]);
 768
 769                 if (level > aniState->noiseImmunityLevel)
 770                         ah->stats.ast_ani_niup++;
 771                 else if (level < aniState->noiseImmunityLevel)
 772                         ah->stats.ast_ani_nidown++;
 773                 aniState->noiseImmunityLevel = level;
 774                 break;
 775         }
 776         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
 777                 const int m1ThreshLow[] = { 127, 50 };
 778                 const int m2ThreshLow[] = { 127, 40 };
 779                 const int m1Thresh[] = { 127, 0x4d };
 780                 const int m2Thresh[] = { 127, 0x40 };
 781                 const int m2CountThr[] = { 31, 16 };
 782                 const int m2CountThrLow[] = { 63, 48 };
 783                 u32 on = param ? 1 : 0;
 784
 785                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 786                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
 787                               m1ThreshLow[on]);
 788                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 789                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
 790                               m2ThreshLow[on]);
 791                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 792                               AR_PHY_SFCORR_M1_THRESH, m1Thresh[on]);
 793                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 794                               AR_PHY_SFCORR_M2_THRESH, m2Thresh[on]);
 795                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
 796                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr[on]);
 797                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
 798                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
 799                               m2CountThrLow[on]);
 800
 801                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 802                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLow[on]);
 803                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 804                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLow[on]);
 805                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 806                               AR_PHY_SFCORR_EXT_M1_THRESH, m1Thresh[on]);
 807                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
 808                               AR_PHY_SFCORR_EXT_M2_THRESH, m2Thresh[on]);
 809
 810                 if (on)
 811                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
 812                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 813                 else
 814                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
 815                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
 816
 817                 if (!on != aniState->ofdmWeakSigDetectOff) {
 818                         if (on)
 819                                 ah->stats.ast_ani_ofdmon++;
 820                         else
 821                                 ah->stats.ast_ani_ofdmoff++;
 822                         aniState->ofdmWeakSigDetectOff = !on;
 823                 }
 824                 break;
 825         }
 826         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
 827                 const int weakSigThrCck[] = { 8, 6 };
 828                 u32 high = param ? 1 : 0;
 829
 830                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
 831                               AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
 832                               weakSigThrCck[high]);
 833                 if (high != aniState->cckWeakSigThreshold) {
 834                         if (high)
 835                                 ah->stats.ast_ani_cckhigh++;
 836                         else
 837                                 ah->stats.ast_ani_ccklow++;
 838                         aniState->cckWeakSigThreshold = high;
 839                 }
 840                 break;
 841         }
 842         case ATH9K_ANI_FIRSTEP_LEVEL:{
 843                 const int firstep[] = { 0, 4, 8 };
 844                 u32 level = param;
 845
 846                 if (level >= ARRAY_SIZE(firstep)) {
 847                         ath_print(common, ATH_DBG_ANI,
 848                                   "level out of range (%u > %u)\n",
 849                                   level,
 850                                   (unsigned) ARRAY_SIZE(firstep));
 851                         return false;
 852                 }
 853                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
 854                               AR_PHY_FIND_SIG_FIRSTEP,
 855                               firstep[level]);
 856                 if (level > aniState->firstepLevel)
 857                         ah->stats.ast_ani_stepup++;
 858                 else if (level < aniState->firstepLevel)
 859                         ah->stats.ast_ani_stepdown++;
 860                 aniState->firstepLevel = level;
 861                 break;
 862         }
 863         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
 864                 const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
 865                 u32 level = param;
 866
 867                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
 868                         ath_print(common, ATH_DBG_ANI,
 869                                   "level out of range (%u > %u)\n",
 870                                   level,
 871                                   (unsigned) ARRAY_SIZE(cycpwrThr1));
 872                         return false;
 873                 }
 874                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
 875                               AR_PHY_TIMING5_CYCPWR_THR1,
 876                               cycpwrThr1[level]);
 877                 if (level > aniState->spurImmunityLevel)
 878                         ah->stats.ast_ani_spurup++;
 879                 else if (level < aniState->spurImmunityLevel)
 880                         ah->stats.ast_ani_spurdown++;
 881                 aniState->spurImmunityLevel = level;
 882                 break;
 883         }
 884         case ATH9K_ANI_PRESENT:
 885                 break;
 886         default:
 887                 ath_print(common, ATH_DBG_ANI,
 888                           "invalid cmd %u\n", cmd);
 889                 return false;
 890         }
 891
 892         ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
 893         ath_print(common, ATH_DBG_ANI,
 894                   "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
 895                   "ofdmWeakSigDetectOff=%d\n",
 896                   aniState->noiseImmunityLevel,
 897                   aniState->spurImmunityLevel,
 898                   !aniState->ofdmWeakSigDetectOff);
 899         ath_print(common, ATH_DBG_ANI,
 900                   "cckWeakSigThreshold=%d, "
 901                   "firstepLevel=%d, listenTime=%d\n",
 902                   aniState->cckWeakSigThreshold,
 903                   aniState->firstepLevel,
 904                   aniState->listenTime);
 905         ath_print(common, ATH_DBG_ANI,
 906                 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
 907                 aniState->cycleCount,
 908                 aniState->ofdmPhyErrCount,
 909                 aniState->cckPhyErrCount);
 910
 911         return true;
 912 }
 913
 914 static void ar9003_hw_nf_sanitize_2g(struct ath_hw *ah, s16 *nf)
 915 {
 916         struct ath_common *common = ath9k_hw_common(ah);
 917
 918         if (*nf > ah->nf_2g_max) {
 919                 ath_print(common, ATH_DBG_CALIBRATE,
 920                           "2 GHz NF (%d) > MAX (%d), "
 921                           "correcting to MAX",
 922                           *nf, ah->nf_2g_max);
 923                 *nf = ah->nf_2g_max;
 924         } else if (*nf < ah->nf_2g_min) {
 925                 ath_print(common, ATH_DBG_CALIBRATE,
 926                           "2 GHz NF (%d) < MIN (%d), "
 927                           "correcting to MIN",
 928                           *nf, ah->nf_2g_min);
 929                 *nf = ah->nf_2g_min;
 930         }
 931 }
 932
 933 static void ar9003_hw_nf_sanitize_5g(struct ath_hw *ah, s16 *nf)
 934 {
 935         struct ath_common *common = ath9k_hw_common(ah);
 936
 937         if (*nf > ah->nf_5g_max) {
 938                 ath_print(common, ATH_DBG_CALIBRATE,
 939                           "5 GHz NF (%d) > MAX (%d), "
 940                           "correcting to MAX",
 941                           *nf, ah->nf_5g_max);
 942                 *nf = ah->nf_5g_max;
 943         } else if (*nf < ah->nf_5g_min) {
 944                 ath_print(common, ATH_DBG_CALIBRATE,
 945                           "5 GHz NF (%d) < MIN (%d), "
 946                           "correcting to MIN",
 947                           *nf, ah->nf_5g_min);
 948                 *nf = ah->nf_5g_min;
 949         }
 950 }
 951
 952 static void ar9003_hw_nf_sanitize(struct ath_hw *ah, s16 *nf)
 953 {
 954         if (IS_CHAN_2GHZ(ah->curchan))
 955                 ar9003_hw_nf_sanitize_2g(ah, nf);
 956         else
 957                 ar9003_hw_nf_sanitize_5g(ah, nf);
 958 }
 959
 960 static void ar9003_hw_do_getnf(struct ath_hw *ah,
 961                               int16_t nfarray[NUM_NF_READINGS])
 962 {
 963         struct ath_common *common = ath9k_hw_common(ah);
 964         int16_t nf;
 965
 966         nf = MS(REG_READ(ah, AR_PHY_CCA_0), AR_PHY_MINCCA_PWR);
 967         if (nf & 0x100)
 968                 nf = 0 - ((nf ^ 0x1ff) + 1);
 969         ar9003_hw_nf_sanitize(ah, &nf);
 970         ath_print(common, ATH_DBG_CALIBRATE,
 971                   "NF calibrated [ctl] [chain 0] is %d\n", nf);
 972         nfarray[0] = nf;
 973
 974         nf = MS(REG_READ(ah, AR_PHY_CCA_1), AR_PHY_CH1_MINCCA_PWR);
 975         if (nf & 0x100)
 976                 nf = 0 - ((nf ^ 0x1ff) + 1);
 977         ar9003_hw_nf_sanitize(ah, &nf);
 978         ath_print(common, ATH_DBG_CALIBRATE,
 979                   "NF calibrated [ctl] [chain 1] is %d\n", nf);
 980         nfarray[1] = nf;
 981
 982         nf = MS(REG_READ(ah, AR_PHY_CCA_2), AR_PHY_CH2_MINCCA_PWR);
 983         if (nf & 0x100)
 984                 nf = 0 - ((nf ^ 0x1ff) + 1);
 985         ar9003_hw_nf_sanitize(ah, &nf);
 986         ath_print(common, ATH_DBG_CALIBRATE,
 987                   "NF calibrated [ctl] [chain 2] is %d\n", nf);
 988         nfarray[2] = nf;
 989
 990         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
 991         if (nf & 0x100)
 992                 nf = 0 - ((nf ^ 0x1ff) + 1);
 993         ar9003_hw_nf_sanitize(ah, &nf);
 994         ath_print(common, ATH_DBG_CALIBRATE,
 995                   "NF calibrated [ext] [chain 0] is %d\n", nf);
 996         nfarray[3] = nf;
 997
 998         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_1), AR_PHY_CH1_EXT_MINCCA_PWR);
 999         if (nf & 0x100)
1000                 nf = 0 - ((nf ^ 0x1ff) + 1);
1001         ar9003_hw_nf_sanitize(ah, &nf);
1002         ath_print(common, ATH_DBG_CALIBRATE,
1003                   "NF calibrated [ext] [chain 1] is %d\n", nf);
1004         nfarray[4] = nf;
1005
1006         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA_2), AR_PHY_CH2_EXT_MINCCA_PWR);
1007         if (nf & 0x100)
1008                 nf = 0 - ((nf ^ 0x1ff) + 1);
1009         ar9003_hw_nf_sanitize(ah, &nf);
1010         ath_print(common, ATH_DBG_CALIBRATE,
1011                   "NF calibrated [ext] [chain 2] is %d\n", nf);
1012         nfarray[5] = nf;
1013 }
1014
1015 void ar9003_hw_set_nf_limits(struct ath_hw *ah)
1016 {
1017         ah->nf_2g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_2GHZ;
1018         ah->nf_2g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_2GHZ;
1019         ah->nf_5g_max = AR_PHY_CCA_MAX_GOOD_VAL_9300_5GHZ;
1020         ah->nf_5g_min = AR_PHY_CCA_MIN_GOOD_VAL_9300_5GHZ;
1021 }
1022
1023 /*
1024  * Find out which of the RX chains are enabled
1025  */
1026 static u32 ar9003_hw_get_rx_chainmask(struct ath_hw *ah)
1027 {
1028         u32 chain = REG_READ(ah, AR_PHY_RX_CHAINMASK);
1029         /*
1030          * The bits [2:0] indicate the rx chain mask and are to be
1031          * interpreted as follows:
1032          * 00x => Only chain 0 is enabled
1033          * 01x => Chain 1 and 0 enabled
1034          * 1xx => Chain 2,1 and 0 enabled
1035          */
1036         return chain & 0x7;
1037 }
1038
1039 static void ar9003_hw_loadnf(struct ath_hw *ah, struct ath9k_channel *chan)
1040 {
1041         struct ath9k_nfcal_hist *h;
1042         unsigned i, j;
1043         int32_t val;
1044         const u32 ar9300_cca_regs[6] = {
1045                 AR_PHY_CCA_0,
1046                 AR_PHY_CCA_1,
1047                 AR_PHY_CCA_2,
1048                 AR_PHY_EXT_CCA,
1049                 AR_PHY_EXT_CCA_1,
1050                 AR_PHY_EXT_CCA_2,
1051         };
1052         u8 chainmask, rx_chain_status;
1053         struct ath_common *common = ath9k_hw_common(ah);
1054
1055         rx_chain_status = ar9003_hw_get_rx_chainmask(ah);
1056
1057         chainmask = 0x3F;
1058         h = ah->nfCalHist;
1059
1060         for (i = 0; i < NUM_NF_READINGS; i++) {
1061                 if (chainmask & (1 << i)) {
1062                         val = REG_READ(ah, ar9300_cca_regs[i]);
1063                         val &= 0xFFFFFE00;
1064                         val |= (((u32) (h[i].privNF) << 1) & 0x1ff);
1065                         REG_WRITE(ah, ar9300_cca_regs[i], val);
1066                 }
1067         }
1068
1069         /*
1070          * Load software filtered NF value into baseband internal minCCApwr
1071          * variable.
1072          */
1073         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1074                     AR_PHY_AGC_CONTROL_ENABLE_NF);
1075         REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1076                     AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1077         REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1078
1079         /*
1080          * Wait for load to complete, should be fast, a few 10s of us.
1081          * The max delay was changed from an original 250us to 10000us
1082          * since 250us often results in NF load timeout and causes deaf
1083          * condition during stress testing 12/12/2009
1084          */
1085         for (j = 0; j < 1000; j++) {
1086                 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1087                      AR_PHY_AGC_CONTROL_NF) == 0)
1088                         break;
1089                 udelay(10);
1090         }
1091
1092         /*
1093          * We timed out waiting for the noisefloor to load, probably due to an
1094          * in-progress rx. Simply return here and allow the load plenty of time
1095          * to complete before the next calibration interval.  We need to avoid
1096          * trying to load -50 (which happens below) while the previous load is
1097          * still in progress as this can cause rx deafness. Instead by returning
1098          * here, the baseband nf cal will just be capped by our present
1099          * noisefloor until the next calibration timer.
1100          */
1101         if (j == 1000) {
1102                 ath_print(common, ATH_DBG_ANY, "Timeout while waiting for nf "
1103                           "to load: AR_PHY_AGC_CONTROL=0x%x\n",
1104                           REG_READ(ah, AR_PHY_AGC_CONTROL));
1105         }
1106
1107         /*
1108          * Restore maxCCAPower register parameter again so that we're not capped
1109          * by the median we just loaded.  This will be initial (and max) value
1110          * of next noise floor calibration the baseband does.
1111          */
1112         for (i = 0; i < NUM_NF_READINGS; i++) {
1113                 if (chainmask & (1 << i)) {
1114                         val = REG_READ(ah, ar9300_cca_regs[i]);
1115                         val &= 0xFFFFFE00;
1116                         val |= (((u32) (-50) << 1) & 0x1ff);
1117                         REG_WRITE(ah, ar9300_cca_regs[i], val);
1118                 }
1119         }
1120 }
1121
1122 void ar9003_hw_attach_phy_ops(struct ath_hw *ah)
1123 {
1124         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1125
1126         priv_ops->rf_set_freq = ar9003_hw_set_channel;
1127         priv_ops->spur_mitigate_freq = ar9003_hw_spur_mitigate;
1128         priv_ops->compute_pll_control = ar9003_hw_compute_pll_control;
1129         priv_ops->set_channel_regs = ar9003_hw_set_channel_regs;
1130         priv_ops->init_bb = ar9003_hw_init_bb;
1131         priv_ops->process_ini = ar9003_hw_process_ini;
1132         priv_ops->set_rfmode = ar9003_hw_set_rfmode;
1133         priv_ops->mark_phy_inactive = ar9003_hw_mark_phy_inactive;
1134         priv_ops->set_delta_slope = ar9003_hw_set_delta_slope;
1135         priv_ops->rfbus_req = ar9003_hw_rfbus_req;
1136         priv_ops->rfbus_done = ar9003_hw_rfbus_done;
1137         priv_ops->enable_rfkill = ar9003_hw_enable_rfkill;
1138         priv_ops->set_diversity = ar9003_hw_set_diversity;
1139         priv_ops->ani_control = ar9003_hw_ani_control;
1140         priv_ops->do_getnf = ar9003_hw_do_getnf;
1141         priv_ops->loadnf = ar9003_hw_loadnf;
1142 }