drivers/net/wireless/ath/ath9k/ar9003_hw.c

   1 /*
   2  * Copyright (c) 2008-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_mac.h"
  19 #include "ar9003_2p2_initvals.h"
  20 #include "ar9485_initvals.h"
  21 #include "ar9340_initvals.h"
  22 #include "ar9330_1p1_initvals.h"
  23 #include "ar9330_1p2_initvals.h"
  24 #include "ar9580_1p0_initvals.h"
  25 #include "ar9462_2p0_initvals.h"
  26
  27 /* General hardware code for the AR9003 hadware family */
  28
  29 /*
  30  * The AR9003 family uses a new INI format (pre, core, post
  31  * arrays per subsystem). This provides support for the
  32  * AR9003 2.2 chipsets.
  33  */
  34 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
  35 {
  36 #define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
  37                 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
  38
  39 #define AR9462_BB_CTX_COEFJ(x)  \
  40                 ar9462_##x##_baseband_core_txfir_coeff_japan_2484
  41
  42 #define AR9462_BBC_TXIFR_COEFFJ \
  43                 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
  44         if (AR_SREV_9330_11(ah)) {
  45                 /* mac */
  46                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
  47                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
  48                                 ar9331_1p1_mac_core,
  49                                 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
  50                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
  51                                 ar9331_1p1_mac_postamble,
  52                                 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
  53
  54                 /* bb */
  55                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
  56                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
  57                                 ar9331_1p1_baseband_core,
  58                                 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
  59                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
  60                                 ar9331_1p1_baseband_postamble,
  61                                 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
  62
  63                 /* radio */
  64                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
  65                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
  66                                 ar9331_1p1_radio_core,
  67                                 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
  68                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
  69
  70                 /* soc */
  71                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
  72                                 ar9331_1p1_soc_preamble,
  73                                 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
  74                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
  75                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
  76                                 ar9331_1p1_soc_postamble,
  77                                 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
  78
  79                 /* rx/tx gain */
  80                 INIT_INI_ARRAY(&ah->iniModesRxGain,
  81                                 ar9331_common_rx_gain_1p1,
  82                                 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
  83                 INIT_INI_ARRAY(&ah->iniModesTxGain,
  84                         ar9331_modes_lowest_ob_db_tx_gain_1p1,
  85                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
  86                         5);
  87
  88                 /* additional clock settings */
  89                 if (ah->is_clk_25mhz)
  90                         INIT_INI_ARRAY(&ah->iniAdditional,
  91                                         ar9331_1p1_xtal_25M,
  92                                         ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
  93                 else
  94                         INIT_INI_ARRAY(&ah->iniAdditional,
  95                                         ar9331_1p1_xtal_40M,
  96                                         ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
  97         } else if (AR_SREV_9330_12(ah)) {
  98                 /* mac */
  99                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 100                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 101                                 ar9331_1p2_mac_core,
 102                                 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
 103                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 104                                 ar9331_1p2_mac_postamble,
 105                                 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
 106
 107                 /* bb */
 108                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 109                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 110                                 ar9331_1p2_baseband_core,
 111                                 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
 112                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 113                                 ar9331_1p2_baseband_postamble,
 114                                 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
 115
 116                 /* radio */
 117                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 118                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 119                                 ar9331_1p2_radio_core,
 120                                 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
 121                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
 122
 123                 /* soc */
 124                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 125                                 ar9331_1p2_soc_preamble,
 126                                 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
 127                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 128                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 129                                 ar9331_1p2_soc_postamble,
 130                                 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
 131
 132                 /* rx/tx gain */
 133                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 134                                 ar9331_common_rx_gain_1p2,
 135                                 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
 136                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 137                         ar9331_modes_lowest_ob_db_tx_gain_1p2,
 138                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
 139                         5);
 140
 141                 /* additional clock settings */
 142                 if (ah->is_clk_25mhz)
 143                         INIT_INI_ARRAY(&ah->iniAdditional,
 144                                         ar9331_1p2_xtal_25M,
 145                                         ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
 146                 else
 147                         INIT_INI_ARRAY(&ah->iniAdditional,
 148                                         ar9331_1p2_xtal_40M,
 149                                         ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
 150         } else if (AR_SREV_9340(ah)) {
 151                 /* mac */
 152                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 153                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 154                                 ar9340_1p0_mac_core,
 155                                 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
 156                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 157                                 ar9340_1p0_mac_postamble,
 158                                 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
 159
 160                 /* bb */
 161                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 162                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 163                                 ar9340_1p0_baseband_core,
 164                                 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
 165                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 166                                 ar9340_1p0_baseband_postamble,
 167                                 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
 168
 169                 /* radio */
 170                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 171                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 172                                 ar9340_1p0_radio_core,
 173                                 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
 174                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 175                                 ar9340_1p0_radio_postamble,
 176                                 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
 177
 178                 /* soc */
 179                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 180                                 ar9340_1p0_soc_preamble,
 181                                 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
 182                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 183                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 184                                 ar9340_1p0_soc_postamble,
 185                                 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
 186
 187                 /* rx/tx gain */
 188                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 189                                 ar9340Common_wo_xlna_rx_gain_table_1p0,
 190                                 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
 191                                 5);
 192                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 193                                 ar9340Modes_high_ob_db_tx_gain_table_1p0,
 194                                 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
 195                                 5);
 196
 197                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 198                                 ar9340Modes_fast_clock_1p0,
 199                                 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
 200                                 3);
 201
 202                 if (!ah->is_clk_25mhz)
 203                         INIT_INI_ARRAY(&ah->iniAdditional,
 204                                        ar9340_1p0_radio_core_40M,
 205                                        ARRAY_SIZE(ar9340_1p0_radio_core_40M),
 206                                        2);
 207         } else if (AR_SREV_9485_11(ah)) {
 208                 /* mac */
 209                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 210                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 211                                 ar9485_1_1_mac_core,
 212                                 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
 213                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 214                                 ar9485_1_1_mac_postamble,
 215                                 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
 216
 217                 /* bb */
 218                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
 219                                 ARRAY_SIZE(ar9485_1_1), 2);
 220                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 221                                 ar9485_1_1_baseband_core,
 222                                 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
 223                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 224                                 ar9485_1_1_baseband_postamble,
 225                                 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
 226
 227                 /* radio */
 228                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 229                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 230                                 ar9485_1_1_radio_core,
 231                                 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
 232                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 233                                 ar9485_1_1_radio_postamble,
 234                                 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
 235
 236                 /* soc */
 237                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 238                                 ar9485_1_1_soc_preamble,
 239                                 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
 240                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 241                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
 242
 243                 /* rx/tx gain */
 244                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 245                                 ar9485Common_wo_xlna_rx_gain_1_1,
 246                                 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
 247                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 248                                 ar9485_modes_lowest_ob_db_tx_gain_1_1,
 249                                 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 250                                 5);
 251
 252                 /* Load PCIE SERDES settings from INI */
 253
 254                 /* Awake Setting */
 255
 256                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 257                                 ar9485_1_1_pcie_phy_clkreq_disable_L1,
 258                                 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 259                                 2);
 260
 261                 /* Sleep Setting */
 262
 263                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 264                                 ar9485_1_1_pcie_phy_clkreq_disable_L1,
 265                                 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
 266                                 2);
 267         } else if (AR_SREV_9462_20(ah)) {
 268
 269                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 270                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
 271                                 ARRAY_SIZE(ar9462_2p0_mac_core), 2);
 272                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 273                                 ar9462_2p0_mac_postamble,
 274                                 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
 275
 276                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 277                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 278                                 ar9462_2p0_baseband_core,
 279                                 ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
 280                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 281                                 ar9462_2p0_baseband_postamble,
 282                                 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
 283
 284                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 285                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 286                                 ar9462_2p0_radio_core,
 287                                 ARRAY_SIZE(ar9462_2p0_radio_core), 2);
 288                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 289                                 ar9462_2p0_radio_postamble,
 290                                 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
 291                 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
 292                                 ar9462_2p0_radio_postamble_sys2ant,
 293                                 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
 294                                 5);
 295
 296                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 297                                 ar9462_2p0_soc_preamble,
 298                                 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
 299                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 300                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 301                                 ar9462_2p0_soc_postamble,
 302                                 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
 303
 304                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 305                                 ar9462_common_rx_gain_table_2p0,
 306                                 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
 307
 308                 /* Awake -> Sleep Setting */
 309                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 310                                 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
 311                                 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
 312                                 2);
 313                 /* Sleep -> Awake Setting */
 314                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 315                                 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
 316                                 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
 317                                 2);
 318
 319                 /* Fast clock modal settings */
 320                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 321                                 ar9462_modes_fast_clock_2p0,
 322                                 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
 323
 324                 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
 325                                 AR9462_BB_CTX_COEFJ(2p0),
 326                                 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
 327
 328                 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
 329                                 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
 330
 331         } else if (AR_SREV_9580(ah)) {
 332                 /* mac */
 333                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 334                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 335                                 ar9580_1p0_mac_core,
 336                                 ARRAY_SIZE(ar9580_1p0_mac_core), 2);
 337                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 338                                 ar9580_1p0_mac_postamble,
 339                                 ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
 340
 341                 /* bb */
 342                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 343                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 344                                 ar9580_1p0_baseband_core,
 345                                 ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
 346                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 347                                 ar9580_1p0_baseband_postamble,
 348                                 ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
 349
 350                 /* radio */
 351                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 352                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 353                                 ar9580_1p0_radio_core,
 354                                 ARRAY_SIZE(ar9580_1p0_radio_core), 2);
 355                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 356                                 ar9580_1p0_radio_postamble,
 357                                 ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
 358
 359                 /* soc */
 360                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 361                                 ar9580_1p0_soc_preamble,
 362                                 ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
 363                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 364                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 365                                 ar9580_1p0_soc_postamble,
 366                                 ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
 367
 368                 /* rx/tx gain */
 369                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 370                                 ar9580_1p0_rx_gain_table,
 371                                 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
 372                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 373                                 ar9580_1p0_low_ob_db_tx_gain_table,
 374                                 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
 375                                 5);
 376
 377                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 378                                 ar9580_1p0_modes_fast_clock,
 379                                 ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
 380                                 3);
 381         } else {
 382                 /* mac */
 383                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
 384                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
 385                                 ar9300_2p2_mac_core,
 386                                 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
 387                 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
 388                                 ar9300_2p2_mac_postamble,
 389                                 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
 390
 391                 /* bb */
 392                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
 393                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
 394                                 ar9300_2p2_baseband_core,
 395                                 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
 396                 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
 397                                 ar9300_2p2_baseband_postamble,
 398                                 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
 399
 400                 /* radio */
 401                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
 402                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
 403                                 ar9300_2p2_radio_core,
 404                                 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
 405                 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
 406                                 ar9300_2p2_radio_postamble,
 407                                 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
 408
 409                 /* soc */
 410                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
 411                                 ar9300_2p2_soc_preamble,
 412                                 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
 413                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
 414                 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
 415                                 ar9300_2p2_soc_postamble,
 416                                 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
 417
 418                 /* rx/tx gain */
 419                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 420                                 ar9300Common_rx_gain_table_2p2,
 421                                 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
 422                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 423                                 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
 424                                 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
 425                                 5);
 426
 427                 /* Load PCIE SERDES settings from INI */
 428
 429                 /* Awake Setting */
 430
 431                 INIT_INI_ARRAY(&ah->iniPcieSerdes,
 432                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
 433                                 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
 434                                 2);
 435
 436                 /* Sleep Setting */
 437
 438                 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
 439                                 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
 440                                 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
 441                                 2);
 442
 443                 /* Fast clock modal settings */
 444                 INIT_INI_ARRAY(&ah->iniModesFastClock,
 445                                 ar9300Modes_fast_clock_2p2,
 446                                 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
 447                                 3);
 448         }
 449 }
 450
 451 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
 452 {
 453         if (AR_SREV_9330_12(ah))
 454                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 455                         ar9331_modes_lowest_ob_db_tx_gain_1p2,
 456                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
 457                         5);
 458         else if (AR_SREV_9330_11(ah))
 459                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 460                         ar9331_modes_lowest_ob_db_tx_gain_1p1,
 461                         ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
 462                         5);
 463         else if (AR_SREV_9340(ah))
 464                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 465                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 466                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 467                         5);
 468         else if (AR_SREV_9485_11(ah))
 469                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 470                         ar9485_modes_lowest_ob_db_tx_gain_1_1,
 471                         ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
 472                         5);
 473         else if (AR_SREV_9580(ah))
 474                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 475                         ar9580_1p0_lowest_ob_db_tx_gain_table,
 476                         ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
 477                         5);
 478         else if (AR_SREV_9462_20(ah))
 479                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 480                         ar9462_modes_low_ob_db_tx_gain_table_2p0,
 481                         ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
 482                         5);
 483         else
 484                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 485                         ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
 486                         ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
 487                         5);
 488 }
 489
 490 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
 491 {
 492         if (AR_SREV_9330_12(ah))
 493                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 494                         ar9331_modes_high_ob_db_tx_gain_1p2,
 495                         ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
 496                         5);
 497         else if (AR_SREV_9330_11(ah))
 498                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 499                         ar9331_modes_high_ob_db_tx_gain_1p1,
 500                         ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
 501                         5);
 502         else if (AR_SREV_9340(ah))
 503                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 504                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 505                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 506                         5);
 507         else if (AR_SREV_9485_11(ah))
 508                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 509                         ar9485Modes_high_ob_db_tx_gain_1_1,
 510                         ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
 511                         5);
 512         else if (AR_SREV_9580(ah))
 513                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 514                         ar9580_1p0_high_ob_db_tx_gain_table,
 515                         ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
 516                         5);
 517         else if (AR_SREV_9462_20(ah))
 518                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 519                         ar9462_modes_high_ob_db_tx_gain_table_2p0,
 520                         ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
 521                         5);
 522         else
 523                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 524                         ar9300Modes_high_ob_db_tx_gain_table_2p2,
 525                         ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
 526                         5);
 527 }
 528
 529 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
 530 {
 531         if (AR_SREV_9330_12(ah))
 532                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 533                         ar9331_modes_low_ob_db_tx_gain_1p2,
 534                         ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
 535                         5);
 536         else if (AR_SREV_9330_11(ah))
 537                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 538                         ar9331_modes_low_ob_db_tx_gain_1p1,
 539                         ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
 540                         5);
 541         else if (AR_SREV_9340(ah))
 542                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 543                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 544                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 545                         5);
 546         else if (AR_SREV_9485_11(ah))
 547                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 548                         ar9485Modes_low_ob_db_tx_gain_1_1,
 549                         ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
 550                         5);
 551         else if (AR_SREV_9580(ah))
 552                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 553                         ar9580_1p0_low_ob_db_tx_gain_table,
 554                         ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
 555                         5);
 556         else
 557                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 558                         ar9300Modes_low_ob_db_tx_gain_table_2p2,
 559                         ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
 560                         5);
 561 }
 562
 563 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
 564 {
 565         if (AR_SREV_9330_12(ah))
 566                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 567                         ar9331_modes_high_power_tx_gain_1p2,
 568                         ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
 569                         5);
 570         else if (AR_SREV_9330_11(ah))
 571                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 572                         ar9331_modes_high_power_tx_gain_1p1,
 573                         ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
 574                         5);
 575         else if (AR_SREV_9340(ah))
 576                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 577                         ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
 578                         ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
 579                         5);
 580         else if (AR_SREV_9485_11(ah))
 581                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 582                         ar9485Modes_high_power_tx_gain_1_1,
 583                         ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
 584                         5);
 585         else if (AR_SREV_9580(ah))
 586                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 587                         ar9580_1p0_high_power_tx_gain_table,
 588                         ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
 589                         5);
 590         else
 591                 INIT_INI_ARRAY(&ah->iniModesTxGain,
 592                         ar9300Modes_high_power_tx_gain_table_2p2,
 593                         ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
 594                         5);
 595 }
 596
 597 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
 598 {
 599         switch (ar9003_hw_get_tx_gain_idx(ah)) {
 600         case 0:
 601         default:
 602                 ar9003_tx_gain_table_mode0(ah);
 603                 break;
 604         case 1:
 605                 ar9003_tx_gain_table_mode1(ah);
 606                 break;
 607         case 2:
 608                 ar9003_tx_gain_table_mode2(ah);
 609                 break;
 610         case 3:
 611                 ar9003_tx_gain_table_mode3(ah);
 612                 break;
 613         }
 614 }
 615
 616 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
 617 {
 618         if (AR_SREV_9330_12(ah))
 619                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 620                                 ar9331_common_rx_gain_1p2,
 621                                 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
 622                                 2);
 623         else if (AR_SREV_9330_11(ah))
 624                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 625                                 ar9331_common_rx_gain_1p1,
 626                                 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
 627                                 2);
 628         else if (AR_SREV_9340(ah))
 629                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 630                                 ar9340Common_rx_gain_table_1p0,
 631                                 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
 632                                 2);
 633         else if (AR_SREV_9485_11(ah))
 634                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 635                                 ar9485Common_wo_xlna_rx_gain_1_1,
 636                                 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
 637                                 2);
 638         else if (AR_SREV_9580(ah))
 639                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 640                                 ar9580_1p0_rx_gain_table,
 641                                 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
 642                                 2);
 643         else if (AR_SREV_9462_20(ah))
 644                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 645                                 ar9462_common_rx_gain_table_2p0,
 646                                 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
 647                                 2);
 648         else
 649                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 650                                 ar9300Common_rx_gain_table_2p2,
 651                                 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
 652                                 2);
 653 }
 654
 655 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
 656 {
 657         if (AR_SREV_9330_12(ah))
 658                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 659                         ar9331_common_wo_xlna_rx_gain_1p2,
 660                         ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
 661                         2);
 662         else if (AR_SREV_9330_11(ah))
 663                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 664                         ar9331_common_wo_xlna_rx_gain_1p1,
 665                         ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
 666                         2);
 667         else if (AR_SREV_9340(ah))
 668                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 669                         ar9340Common_wo_xlna_rx_gain_table_1p0,
 670                         ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
 671                         2);
 672         else if (AR_SREV_9485_11(ah))
 673                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 674                         ar9485Common_wo_xlna_rx_gain_1_1,
 675                         ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
 676                         2);
 677         else if (AR_SREV_9462_20(ah))
 678                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 679                         ar9462_common_wo_xlna_rx_gain_table_2p0,
 680                         ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
 681                         2);
 682         else if (AR_SREV_9580(ah))
 683                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 684                         ar9580_1p0_wo_xlna_rx_gain_table,
 685                         ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
 686                         2);
 687         else
 688                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 689                         ar9300Common_wo_xlna_rx_gain_table_2p2,
 690                         ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
 691                         2);
 692 }
 693
 694 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
 695 {
 696         if (AR_SREV_9462_20(ah))
 697                 INIT_INI_ARRAY(&ah->iniModesRxGain,
 698                                ar9462_common_mixed_rx_gain_table_2p0,
 699                                ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
 700 }
 701
 702 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
 703 {
 704         switch (ar9003_hw_get_rx_gain_idx(ah)) {
 705         case 0:
 706         default:
 707                 ar9003_rx_gain_table_mode0(ah);
 708                 break;
 709         case 1:
 710                 ar9003_rx_gain_table_mode1(ah);
 711                 break;
 712         case 2:
 713                 ar9003_rx_gain_table_mode2(ah);
 714                 break;
 715         }
 716 }
 717
 718 /* set gain table pointers according to values read from the eeprom */
 719 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
 720 {
 721         ar9003_tx_gain_table_apply(ah);
 722         ar9003_rx_gain_table_apply(ah);
 723 }
 724
 725 /*
 726  * Helper for ASPM support.
 727  *
 728  * Disable PLL when in L0s as well as receiver clock when in L1.
 729  * This power saving option must be enabled through the SerDes.
 730  *
 731  * Programming the SerDes must go through the same 288 bit serial shift
 732  * register as the other analog registers.  Hence the 9 writes.
 733  */
 734 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
 735                                          bool power_off)
 736 {
 737         /* Nothing to do on restore for 11N */
 738         if (!power_off /* !restore */) {
 739                 /* set bit 19 to allow forcing of pcie core into L1 state */
 740                 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
 741
 742                 /* Several PCIe massages to ensure proper behaviour */
 743                 if (ah->config.pcie_waen)
 744                         REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
 745                 else
 746                         REG_WRITE(ah, AR_WA, ah->WARegVal);
 747         }
 748
 749         /*
 750          * Configire PCIE after Ini init. SERDES values now come from ini file
 751          * This enables PCIe low power mode.
 752          */
 753         if (ah->config.pcieSerDesWrite) {
 754                 unsigned int i;
 755                 struct ar5416IniArray *array;
 756
 757                 array = power_off ? &ah->iniPcieSerdes :
 758                                     &ah->iniPcieSerdesLowPower;
 759
 760                 for (i = 0; i < array->ia_rows; i++) {
 761                         REG_WRITE(ah,
 762                                   INI_RA(array, i, 0),
 763                                   INI_RA(array, i, 1));
 764                 }
 765         }
 766 }
 767
 768 /* Sets up the AR9003 hardware familiy callbacks */
 769 void ar9003_hw_attach_ops(struct ath_hw *ah)
 770 {
 771         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
 772         struct ath_hw_ops *ops = ath9k_hw_ops(ah);
 773
 774         priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
 775         priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
 776
 777         ops->config_pci_powersave = ar9003_hw_configpcipowersave;
 778
 779         ar9003_hw_attach_phy_ops(ah);
 780         ar9003_hw_attach_calib_ops(ah);
 781         ar9003_hw_attach_mac_ops(ah);
 782 }