2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 #include "ar9003_mac.h"
19 #include "ar9003_2p2_initvals.h"
20 #include "ar9485_initvals.h"
21 #include "ar9340_initvals.h"
22 #include "ar9330_1p1_initvals.h"
23 #include "ar9330_1p2_initvals.h"
24 #include "ar9580_1p0_initvals.h"
25 #include "ar9462_2p0_initvals.h"
27 /* General hardware code for the AR9003 hadware family */
30 * The AR9003 family uses a new INI format (pre, core, post
31 * arrays per subsystem). This provides support for the
32 * AR9003 2.2 chipsets.
34 static void ar9003_hw_init_mode_regs(struct ath_hw *ah)
36 #define PCIE_PLL_ON_CREQ_DIS_L1_2P0 \
37 ar9462_pciephy_pll_on_clkreq_disable_L1_2p0
39 #define AR9462_BB_CTX_COEFJ(x) \
40 ar9462_##x##_baseband_core_txfir_coeff_japan_2484
42 #define AR9462_BBC_TXIFR_COEFFJ \
43 ar9462_2p0_baseband_core_txfir_coeff_japan_2484
44 if (AR_SREV_9330_11(ah)) {
46 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
47 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
49 ARRAY_SIZE(ar9331_1p1_mac_core), 2);
50 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
51 ar9331_1p1_mac_postamble,
52 ARRAY_SIZE(ar9331_1p1_mac_postamble), 5);
55 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
56 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
57 ar9331_1p1_baseband_core,
58 ARRAY_SIZE(ar9331_1p1_baseband_core), 2);
59 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
60 ar9331_1p1_baseband_postamble,
61 ARRAY_SIZE(ar9331_1p1_baseband_postamble), 5);
64 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
65 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
66 ar9331_1p1_radio_core,
67 ARRAY_SIZE(ar9331_1p1_radio_core), 2);
68 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
71 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
72 ar9331_1p1_soc_preamble,
73 ARRAY_SIZE(ar9331_1p1_soc_preamble), 2);
74 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
75 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
76 ar9331_1p1_soc_postamble,
77 ARRAY_SIZE(ar9331_1p1_soc_postamble), 2);
80 INIT_INI_ARRAY(&ah->iniModesRxGain,
81 ar9331_common_rx_gain_1p1,
82 ARRAY_SIZE(ar9331_common_rx_gain_1p1), 2);
83 INIT_INI_ARRAY(&ah->iniModesTxGain,
84 ar9331_modes_lowest_ob_db_tx_gain_1p1,
85 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
88 /* additional clock settings */
90 INIT_INI_ARRAY(&ah->iniAdditional,
92 ARRAY_SIZE(ar9331_1p1_xtal_25M), 2);
94 INIT_INI_ARRAY(&ah->iniAdditional,
96 ARRAY_SIZE(ar9331_1p1_xtal_40M), 2);
97 } else if (AR_SREV_9330_12(ah)) {
99 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
100 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
102 ARRAY_SIZE(ar9331_1p2_mac_core), 2);
103 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
104 ar9331_1p2_mac_postamble,
105 ARRAY_SIZE(ar9331_1p2_mac_postamble), 5);
108 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
109 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
110 ar9331_1p2_baseband_core,
111 ARRAY_SIZE(ar9331_1p2_baseband_core), 2);
112 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
113 ar9331_1p2_baseband_postamble,
114 ARRAY_SIZE(ar9331_1p2_baseband_postamble), 5);
117 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
118 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
119 ar9331_1p2_radio_core,
120 ARRAY_SIZE(ar9331_1p2_radio_core), 2);
121 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST], NULL, 0, 0);
124 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
125 ar9331_1p2_soc_preamble,
126 ARRAY_SIZE(ar9331_1p2_soc_preamble), 2);
127 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
128 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
129 ar9331_1p2_soc_postamble,
130 ARRAY_SIZE(ar9331_1p2_soc_postamble), 2);
133 INIT_INI_ARRAY(&ah->iniModesRxGain,
134 ar9331_common_rx_gain_1p2,
135 ARRAY_SIZE(ar9331_common_rx_gain_1p2), 2);
136 INIT_INI_ARRAY(&ah->iniModesTxGain,
137 ar9331_modes_lowest_ob_db_tx_gain_1p2,
138 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
141 /* additional clock settings */
142 if (ah->is_clk_25mhz)
143 INIT_INI_ARRAY(&ah->iniAdditional,
145 ARRAY_SIZE(ar9331_1p2_xtal_25M), 2);
147 INIT_INI_ARRAY(&ah->iniAdditional,
149 ARRAY_SIZE(ar9331_1p2_xtal_40M), 2);
150 } else if (AR_SREV_9340(ah)) {
152 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
153 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
155 ARRAY_SIZE(ar9340_1p0_mac_core), 2);
156 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
157 ar9340_1p0_mac_postamble,
158 ARRAY_SIZE(ar9340_1p0_mac_postamble), 5);
161 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
162 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
163 ar9340_1p0_baseband_core,
164 ARRAY_SIZE(ar9340_1p0_baseband_core), 2);
165 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
166 ar9340_1p0_baseband_postamble,
167 ARRAY_SIZE(ar9340_1p0_baseband_postamble), 5);
170 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
171 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
172 ar9340_1p0_radio_core,
173 ARRAY_SIZE(ar9340_1p0_radio_core), 2);
174 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
175 ar9340_1p0_radio_postamble,
176 ARRAY_SIZE(ar9340_1p0_radio_postamble), 5);
179 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
180 ar9340_1p0_soc_preamble,
181 ARRAY_SIZE(ar9340_1p0_soc_preamble), 2);
182 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
183 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
184 ar9340_1p0_soc_postamble,
185 ARRAY_SIZE(ar9340_1p0_soc_postamble), 5);
188 INIT_INI_ARRAY(&ah->iniModesRxGain,
189 ar9340Common_wo_xlna_rx_gain_table_1p0,
190 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
192 INIT_INI_ARRAY(&ah->iniModesTxGain,
193 ar9340Modes_high_ob_db_tx_gain_table_1p0,
194 ARRAY_SIZE(ar9340Modes_high_ob_db_tx_gain_table_1p0),
197 INIT_INI_ARRAY(&ah->iniModesFastClock,
198 ar9340Modes_fast_clock_1p0,
199 ARRAY_SIZE(ar9340Modes_fast_clock_1p0),
202 if (!ah->is_clk_25mhz)
203 INIT_INI_ARRAY(&ah->iniAdditional,
204 ar9340_1p0_radio_core_40M,
205 ARRAY_SIZE(ar9340_1p0_radio_core_40M),
207 } else if (AR_SREV_9485_11(ah)) {
209 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
210 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
212 ARRAY_SIZE(ar9485_1_1_mac_core), 2);
213 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
214 ar9485_1_1_mac_postamble,
215 ARRAY_SIZE(ar9485_1_1_mac_postamble), 5);
218 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], ar9485_1_1,
219 ARRAY_SIZE(ar9485_1_1), 2);
220 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
221 ar9485_1_1_baseband_core,
222 ARRAY_SIZE(ar9485_1_1_baseband_core), 2);
223 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
224 ar9485_1_1_baseband_postamble,
225 ARRAY_SIZE(ar9485_1_1_baseband_postamble), 5);
228 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
229 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
230 ar9485_1_1_radio_core,
231 ARRAY_SIZE(ar9485_1_1_radio_core), 2);
232 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
233 ar9485_1_1_radio_postamble,
234 ARRAY_SIZE(ar9485_1_1_radio_postamble), 2);
237 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
238 ar9485_1_1_soc_preamble,
239 ARRAY_SIZE(ar9485_1_1_soc_preamble), 2);
240 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
241 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST], NULL, 0, 0);
244 INIT_INI_ARRAY(&ah->iniModesRxGain,
245 ar9485Common_wo_xlna_rx_gain_1_1,
246 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1), 2);
247 INIT_INI_ARRAY(&ah->iniModesTxGain,
248 ar9485_modes_lowest_ob_db_tx_gain_1_1,
249 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
252 /* Load PCIE SERDES settings from INI */
256 INIT_INI_ARRAY(&ah->iniPcieSerdes,
257 ar9485_1_1_pcie_phy_clkreq_disable_L1,
258 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
263 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
264 ar9485_1_1_pcie_phy_clkreq_disable_L1,
265 ARRAY_SIZE(ar9485_1_1_pcie_phy_clkreq_disable_L1),
267 } else if (AR_SREV_9462_20(ah)) {
269 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
270 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE], ar9462_2p0_mac_core,
271 ARRAY_SIZE(ar9462_2p0_mac_core), 2);
272 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
273 ar9462_2p0_mac_postamble,
274 ARRAY_SIZE(ar9462_2p0_mac_postamble), 5);
276 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
277 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
278 ar9462_2p0_baseband_core,
279 ARRAY_SIZE(ar9462_2p0_baseband_core), 2);
280 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
281 ar9462_2p0_baseband_postamble,
282 ARRAY_SIZE(ar9462_2p0_baseband_postamble), 5);
284 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
285 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
286 ar9462_2p0_radio_core,
287 ARRAY_SIZE(ar9462_2p0_radio_core), 2);
288 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
289 ar9462_2p0_radio_postamble,
290 ARRAY_SIZE(ar9462_2p0_radio_postamble), 5);
291 INIT_INI_ARRAY(&ah->ini_radio_post_sys2ant,
292 ar9462_2p0_radio_postamble_sys2ant,
293 ARRAY_SIZE(ar9462_2p0_radio_postamble_sys2ant),
296 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
297 ar9462_2p0_soc_preamble,
298 ARRAY_SIZE(ar9462_2p0_soc_preamble), 2);
299 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
300 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
301 ar9462_2p0_soc_postamble,
302 ARRAY_SIZE(ar9462_2p0_soc_postamble), 5);
304 INIT_INI_ARRAY(&ah->iniModesRxGain,
305 ar9462_common_rx_gain_table_2p0,
306 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
308 /* Awake -> Sleep Setting */
309 INIT_INI_ARRAY(&ah->iniPcieSerdes,
310 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
311 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
313 /* Sleep -> Awake Setting */
314 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
315 PCIE_PLL_ON_CREQ_DIS_L1_2P0,
316 ARRAY_SIZE(PCIE_PLL_ON_CREQ_DIS_L1_2P0),
319 /* Fast clock modal settings */
320 INIT_INI_ARRAY(&ah->iniModesFastClock,
321 ar9462_modes_fast_clock_2p0,
322 ARRAY_SIZE(ar9462_modes_fast_clock_2p0), 3);
324 INIT_INI_ARRAY(&ah->iniCckfirJapan2484,
325 AR9462_BB_CTX_COEFJ(2p0),
326 ARRAY_SIZE(AR9462_BB_CTX_COEFJ(2p0)), 2);
328 INIT_INI_ARRAY(&ah->ini_japan2484, AR9462_BBC_TXIFR_COEFFJ,
329 ARRAY_SIZE(AR9462_BBC_TXIFR_COEFFJ), 2);
331 } else if (AR_SREV_9580(ah)) {
333 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
334 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
336 ARRAY_SIZE(ar9580_1p0_mac_core), 2);
337 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
338 ar9580_1p0_mac_postamble,
339 ARRAY_SIZE(ar9580_1p0_mac_postamble), 5);
342 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
343 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
344 ar9580_1p0_baseband_core,
345 ARRAY_SIZE(ar9580_1p0_baseband_core), 2);
346 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
347 ar9580_1p0_baseband_postamble,
348 ARRAY_SIZE(ar9580_1p0_baseband_postamble), 5);
351 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
352 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
353 ar9580_1p0_radio_core,
354 ARRAY_SIZE(ar9580_1p0_radio_core), 2);
355 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
356 ar9580_1p0_radio_postamble,
357 ARRAY_SIZE(ar9580_1p0_radio_postamble), 5);
360 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
361 ar9580_1p0_soc_preamble,
362 ARRAY_SIZE(ar9580_1p0_soc_preamble), 2);
363 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
364 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
365 ar9580_1p0_soc_postamble,
366 ARRAY_SIZE(ar9580_1p0_soc_postamble), 5);
369 INIT_INI_ARRAY(&ah->iniModesRxGain,
370 ar9580_1p0_rx_gain_table,
371 ARRAY_SIZE(ar9580_1p0_rx_gain_table), 2);
372 INIT_INI_ARRAY(&ah->iniModesTxGain,
373 ar9580_1p0_low_ob_db_tx_gain_table,
374 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
377 INIT_INI_ARRAY(&ah->iniModesFastClock,
378 ar9580_1p0_modes_fast_clock,
379 ARRAY_SIZE(ar9580_1p0_modes_fast_clock),
383 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_PRE], NULL, 0, 0);
384 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_CORE],
386 ARRAY_SIZE(ar9300_2p2_mac_core), 2);
387 INIT_INI_ARRAY(&ah->iniMac[ATH_INI_POST],
388 ar9300_2p2_mac_postamble,
389 ARRAY_SIZE(ar9300_2p2_mac_postamble), 5);
392 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_PRE], NULL, 0, 0);
393 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_CORE],
394 ar9300_2p2_baseband_core,
395 ARRAY_SIZE(ar9300_2p2_baseband_core), 2);
396 INIT_INI_ARRAY(&ah->iniBB[ATH_INI_POST],
397 ar9300_2p2_baseband_postamble,
398 ARRAY_SIZE(ar9300_2p2_baseband_postamble), 5);
401 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_PRE], NULL, 0, 0);
402 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_CORE],
403 ar9300_2p2_radio_core,
404 ARRAY_SIZE(ar9300_2p2_radio_core), 2);
405 INIT_INI_ARRAY(&ah->iniRadio[ATH_INI_POST],
406 ar9300_2p2_radio_postamble,
407 ARRAY_SIZE(ar9300_2p2_radio_postamble), 5);
410 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_PRE],
411 ar9300_2p2_soc_preamble,
412 ARRAY_SIZE(ar9300_2p2_soc_preamble), 2);
413 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_CORE], NULL, 0, 0);
414 INIT_INI_ARRAY(&ah->iniSOC[ATH_INI_POST],
415 ar9300_2p2_soc_postamble,
416 ARRAY_SIZE(ar9300_2p2_soc_postamble), 5);
419 INIT_INI_ARRAY(&ah->iniModesRxGain,
420 ar9300Common_rx_gain_table_2p2,
421 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2), 2);
422 INIT_INI_ARRAY(&ah->iniModesTxGain,
423 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
424 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
427 /* Load PCIE SERDES settings from INI */
431 INIT_INI_ARRAY(&ah->iniPcieSerdes,
432 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
433 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
438 INIT_INI_ARRAY(&ah->iniPcieSerdesLowPower,
439 ar9300PciePhy_pll_on_clkreq_disable_L1_2p2,
440 ARRAY_SIZE(ar9300PciePhy_pll_on_clkreq_disable_L1_2p2),
443 /* Fast clock modal settings */
444 INIT_INI_ARRAY(&ah->iniModesFastClock,
445 ar9300Modes_fast_clock_2p2,
446 ARRAY_SIZE(ar9300Modes_fast_clock_2p2),
451 static void ar9003_tx_gain_table_mode0(struct ath_hw *ah)
453 if (AR_SREV_9330_12(ah))
454 INIT_INI_ARRAY(&ah->iniModesTxGain,
455 ar9331_modes_lowest_ob_db_tx_gain_1p2,
456 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p2),
458 else if (AR_SREV_9330_11(ah))
459 INIT_INI_ARRAY(&ah->iniModesTxGain,
460 ar9331_modes_lowest_ob_db_tx_gain_1p1,
461 ARRAY_SIZE(ar9331_modes_lowest_ob_db_tx_gain_1p1),
463 else if (AR_SREV_9340(ah))
464 INIT_INI_ARRAY(&ah->iniModesTxGain,
465 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
466 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
468 else if (AR_SREV_9485_11(ah))
469 INIT_INI_ARRAY(&ah->iniModesTxGain,
470 ar9485_modes_lowest_ob_db_tx_gain_1_1,
471 ARRAY_SIZE(ar9485_modes_lowest_ob_db_tx_gain_1_1),
473 else if (AR_SREV_9580(ah))
474 INIT_INI_ARRAY(&ah->iniModesTxGain,
475 ar9580_1p0_lowest_ob_db_tx_gain_table,
476 ARRAY_SIZE(ar9580_1p0_lowest_ob_db_tx_gain_table),
478 else if (AR_SREV_9462_20(ah))
479 INIT_INI_ARRAY(&ah->iniModesTxGain,
480 ar9462_modes_low_ob_db_tx_gain_table_2p0,
481 ARRAY_SIZE(ar9462_modes_low_ob_db_tx_gain_table_2p0),
484 INIT_INI_ARRAY(&ah->iniModesTxGain,
485 ar9300Modes_lowest_ob_db_tx_gain_table_2p2,
486 ARRAY_SIZE(ar9300Modes_lowest_ob_db_tx_gain_table_2p2),
490 static void ar9003_tx_gain_table_mode1(struct ath_hw *ah)
492 if (AR_SREV_9330_12(ah))
493 INIT_INI_ARRAY(&ah->iniModesTxGain,
494 ar9331_modes_high_ob_db_tx_gain_1p2,
495 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p2),
497 else if (AR_SREV_9330_11(ah))
498 INIT_INI_ARRAY(&ah->iniModesTxGain,
499 ar9331_modes_high_ob_db_tx_gain_1p1,
500 ARRAY_SIZE(ar9331_modes_high_ob_db_tx_gain_1p1),
502 else if (AR_SREV_9340(ah))
503 INIT_INI_ARRAY(&ah->iniModesTxGain,
504 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
505 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
507 else if (AR_SREV_9485_11(ah))
508 INIT_INI_ARRAY(&ah->iniModesTxGain,
509 ar9485Modes_high_ob_db_tx_gain_1_1,
510 ARRAY_SIZE(ar9485Modes_high_ob_db_tx_gain_1_1),
512 else if (AR_SREV_9580(ah))
513 INIT_INI_ARRAY(&ah->iniModesTxGain,
514 ar9580_1p0_high_ob_db_tx_gain_table,
515 ARRAY_SIZE(ar9580_1p0_high_ob_db_tx_gain_table),
517 else if (AR_SREV_9462_20(ah))
518 INIT_INI_ARRAY(&ah->iniModesTxGain,
519 ar9462_modes_high_ob_db_tx_gain_table_2p0,
520 ARRAY_SIZE(ar9462_modes_high_ob_db_tx_gain_table_2p0),
523 INIT_INI_ARRAY(&ah->iniModesTxGain,
524 ar9300Modes_high_ob_db_tx_gain_table_2p2,
525 ARRAY_SIZE(ar9300Modes_high_ob_db_tx_gain_table_2p2),
529 static void ar9003_tx_gain_table_mode2(struct ath_hw *ah)
531 if (AR_SREV_9330_12(ah))
532 INIT_INI_ARRAY(&ah->iniModesTxGain,
533 ar9331_modes_low_ob_db_tx_gain_1p2,
534 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p2),
536 else if (AR_SREV_9330_11(ah))
537 INIT_INI_ARRAY(&ah->iniModesTxGain,
538 ar9331_modes_low_ob_db_tx_gain_1p1,
539 ARRAY_SIZE(ar9331_modes_low_ob_db_tx_gain_1p1),
541 else if (AR_SREV_9340(ah))
542 INIT_INI_ARRAY(&ah->iniModesTxGain,
543 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
544 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
546 else if (AR_SREV_9485_11(ah))
547 INIT_INI_ARRAY(&ah->iniModesTxGain,
548 ar9485Modes_low_ob_db_tx_gain_1_1,
549 ARRAY_SIZE(ar9485Modes_low_ob_db_tx_gain_1_1),
551 else if (AR_SREV_9580(ah))
552 INIT_INI_ARRAY(&ah->iniModesTxGain,
553 ar9580_1p0_low_ob_db_tx_gain_table,
554 ARRAY_SIZE(ar9580_1p0_low_ob_db_tx_gain_table),
557 INIT_INI_ARRAY(&ah->iniModesTxGain,
558 ar9300Modes_low_ob_db_tx_gain_table_2p2,
559 ARRAY_SIZE(ar9300Modes_low_ob_db_tx_gain_table_2p2),
563 static void ar9003_tx_gain_table_mode3(struct ath_hw *ah)
565 if (AR_SREV_9330_12(ah))
566 INIT_INI_ARRAY(&ah->iniModesTxGain,
567 ar9331_modes_high_power_tx_gain_1p2,
568 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p2),
570 else if (AR_SREV_9330_11(ah))
571 INIT_INI_ARRAY(&ah->iniModesTxGain,
572 ar9331_modes_high_power_tx_gain_1p1,
573 ARRAY_SIZE(ar9331_modes_high_power_tx_gain_1p1),
575 else if (AR_SREV_9340(ah))
576 INIT_INI_ARRAY(&ah->iniModesTxGain,
577 ar9340Modes_lowest_ob_db_tx_gain_table_1p0,
578 ARRAY_SIZE(ar9340Modes_lowest_ob_db_tx_gain_table_1p0),
580 else if (AR_SREV_9485_11(ah))
581 INIT_INI_ARRAY(&ah->iniModesTxGain,
582 ar9485Modes_high_power_tx_gain_1_1,
583 ARRAY_SIZE(ar9485Modes_high_power_tx_gain_1_1),
585 else if (AR_SREV_9580(ah))
586 INIT_INI_ARRAY(&ah->iniModesTxGain,
587 ar9580_1p0_high_power_tx_gain_table,
588 ARRAY_SIZE(ar9580_1p0_high_power_tx_gain_table),
591 INIT_INI_ARRAY(&ah->iniModesTxGain,
592 ar9300Modes_high_power_tx_gain_table_2p2,
593 ARRAY_SIZE(ar9300Modes_high_power_tx_gain_table_2p2),
597 static void ar9003_tx_gain_table_apply(struct ath_hw *ah)
599 switch (ar9003_hw_get_tx_gain_idx(ah)) {
602 ar9003_tx_gain_table_mode0(ah);
605 ar9003_tx_gain_table_mode1(ah);
608 ar9003_tx_gain_table_mode2(ah);
611 ar9003_tx_gain_table_mode3(ah);
616 static void ar9003_rx_gain_table_mode0(struct ath_hw *ah)
618 if (AR_SREV_9330_12(ah))
619 INIT_INI_ARRAY(&ah->iniModesRxGain,
620 ar9331_common_rx_gain_1p2,
621 ARRAY_SIZE(ar9331_common_rx_gain_1p2),
623 else if (AR_SREV_9330_11(ah))
624 INIT_INI_ARRAY(&ah->iniModesRxGain,
625 ar9331_common_rx_gain_1p1,
626 ARRAY_SIZE(ar9331_common_rx_gain_1p1),
628 else if (AR_SREV_9340(ah))
629 INIT_INI_ARRAY(&ah->iniModesRxGain,
630 ar9340Common_rx_gain_table_1p0,
631 ARRAY_SIZE(ar9340Common_rx_gain_table_1p0),
633 else if (AR_SREV_9485_11(ah))
634 INIT_INI_ARRAY(&ah->iniModesRxGain,
635 ar9485Common_wo_xlna_rx_gain_1_1,
636 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
638 else if (AR_SREV_9580(ah))
639 INIT_INI_ARRAY(&ah->iniModesRxGain,
640 ar9580_1p0_rx_gain_table,
641 ARRAY_SIZE(ar9580_1p0_rx_gain_table),
643 else if (AR_SREV_9462_20(ah))
644 INIT_INI_ARRAY(&ah->iniModesRxGain,
645 ar9462_common_rx_gain_table_2p0,
646 ARRAY_SIZE(ar9462_common_rx_gain_table_2p0),
649 INIT_INI_ARRAY(&ah->iniModesRxGain,
650 ar9300Common_rx_gain_table_2p2,
651 ARRAY_SIZE(ar9300Common_rx_gain_table_2p2),
655 static void ar9003_rx_gain_table_mode1(struct ath_hw *ah)
657 if (AR_SREV_9330_12(ah))
658 INIT_INI_ARRAY(&ah->iniModesRxGain,
659 ar9331_common_wo_xlna_rx_gain_1p2,
660 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p2),
662 else if (AR_SREV_9330_11(ah))
663 INIT_INI_ARRAY(&ah->iniModesRxGain,
664 ar9331_common_wo_xlna_rx_gain_1p1,
665 ARRAY_SIZE(ar9331_common_wo_xlna_rx_gain_1p1),
667 else if (AR_SREV_9340(ah))
668 INIT_INI_ARRAY(&ah->iniModesRxGain,
669 ar9340Common_wo_xlna_rx_gain_table_1p0,
670 ARRAY_SIZE(ar9340Common_wo_xlna_rx_gain_table_1p0),
672 else if (AR_SREV_9485_11(ah))
673 INIT_INI_ARRAY(&ah->iniModesRxGain,
674 ar9485Common_wo_xlna_rx_gain_1_1,
675 ARRAY_SIZE(ar9485Common_wo_xlna_rx_gain_1_1),
677 else if (AR_SREV_9462_20(ah))
678 INIT_INI_ARRAY(&ah->iniModesRxGain,
679 ar9462_common_wo_xlna_rx_gain_table_2p0,
680 ARRAY_SIZE(ar9462_common_wo_xlna_rx_gain_table_2p0),
682 else if (AR_SREV_9580(ah))
683 INIT_INI_ARRAY(&ah->iniModesRxGain,
684 ar9580_1p0_wo_xlna_rx_gain_table,
685 ARRAY_SIZE(ar9580_1p0_wo_xlna_rx_gain_table),
688 INIT_INI_ARRAY(&ah->iniModesRxGain,
689 ar9300Common_wo_xlna_rx_gain_table_2p2,
690 ARRAY_SIZE(ar9300Common_wo_xlna_rx_gain_table_2p2),
694 static void ar9003_rx_gain_table_mode2(struct ath_hw *ah)
696 if (AR_SREV_9462_20(ah))
697 INIT_INI_ARRAY(&ah->iniModesRxGain,
698 ar9462_common_mixed_rx_gain_table_2p0,
699 ARRAY_SIZE(ar9462_common_mixed_rx_gain_table_2p0), 2);
702 static void ar9003_rx_gain_table_apply(struct ath_hw *ah)
704 switch (ar9003_hw_get_rx_gain_idx(ah)) {
707 ar9003_rx_gain_table_mode0(ah);
710 ar9003_rx_gain_table_mode1(ah);
713 ar9003_rx_gain_table_mode2(ah);
718 /* set gain table pointers according to values read from the eeprom */
719 static void ar9003_hw_init_mode_gain_regs(struct ath_hw *ah)
721 ar9003_tx_gain_table_apply(ah);
722 ar9003_rx_gain_table_apply(ah);
726 * Helper for ASPM support.
728 * Disable PLL when in L0s as well as receiver clock when in L1.
729 * This power saving option must be enabled through the SerDes.
731 * Programming the SerDes must go through the same 288 bit serial shift
732 * register as the other analog registers. Hence the 9 writes.
734 static void ar9003_hw_configpcipowersave(struct ath_hw *ah,
737 /* Nothing to do on restore for 11N */
738 if (!power_off /* !restore */) {
739 /* set bit 19 to allow forcing of pcie core into L1 state */
740 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
742 /* Several PCIe massages to ensure proper behaviour */
743 if (ah->config.pcie_waen)
744 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
746 REG_WRITE(ah, AR_WA, ah->WARegVal);
750 * Configire PCIE after Ini init. SERDES values now come from ini file
751 * This enables PCIe low power mode.
753 if (ah->config.pcieSerDesWrite) {
755 struct ar5416IniArray *array;
757 array = power_off ? &ah->iniPcieSerdes :
758 &ah->iniPcieSerdesLowPower;
760 for (i = 0; i < array->ia_rows; i++) {
763 INI_RA(array, i, 1));
768 /* Sets up the AR9003 hardware familiy callbacks */
769 void ar9003_hw_attach_ops(struct ath_hw *ah)
771 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
772 struct ath_hw_ops *ops = ath9k_hw_ops(ah);
774 priv_ops->init_mode_regs = ar9003_hw_init_mode_regs;
775 priv_ops->init_mode_gain_regs = ar9003_hw_init_mode_gain_regs;
777 ops->config_pci_powersave = ar9003_hw_configpcipowersave;
779 ar9003_hw_attach_phy_ops(ah);
780 ar9003_hw_attach_calib_ops(ah);
781 ar9003_hw_attach_mac_ops(ah);