1 #ifndef AR9003_EEPROM_H
2 #define AR9003_EEPROM_H
4 #include <linux/types.h>
6 #define AR9300_EEP_VER 0xD000
7 #define AR9300_EEP_VER_MINOR_MASK 0xFFF
8 #define AR9300_EEP_MINOR_VER_1 0x1
9 #define AR9300_EEP_MINOR_VER AR9300_EEP_MINOR_VER_1
11 /* 16-bit offset location start of calibration struct */
12 #define AR9300_EEP_START_LOC 256
13 #define AR9300_NUM_5G_CAL_PIERS 8
14 #define AR9300_NUM_2G_CAL_PIERS 3
15 #define AR9300_NUM_5G_20_TARGET_POWERS 8
16 #define AR9300_NUM_5G_40_TARGET_POWERS 8
17 #define AR9300_NUM_2G_CCK_TARGET_POWERS 2
18 #define AR9300_NUM_2G_20_TARGET_POWERS 3
19 #define AR9300_NUM_2G_40_TARGET_POWERS 3
20 /* #define AR9300_NUM_CTLS 21 */
21 #define AR9300_NUM_CTLS_5G 9
22 #define AR9300_NUM_CTLS_2G 12
23 #define AR9300_CTL_MODE_M 0xF
24 #define AR9300_NUM_BAND_EDGES_5G 8
25 #define AR9300_NUM_BAND_EDGES_2G 4
26 #define AR9300_NUM_PD_GAINS 4
27 #define AR9300_PD_GAINS_IN_MASK 4
28 #define AR9300_PD_GAIN_ICEPTS 5
29 #define AR9300_EEPROM_MODAL_SPURS 5
30 #define AR9300_MAX_RATE_POWER 63
31 #define AR9300_NUM_PDADC_VALUES 128
32 #define AR9300_NUM_RATES 16
33 #define AR9300_BCHAN_UNUSED 0xFF
34 #define AR9300_MAX_PWR_RANGE_IN_HALF_DB 64
35 #define AR9300_OPFLAGS_11A 0x01
36 #define AR9300_OPFLAGS_11G 0x02
37 #define AR9300_OPFLAGS_5G_HT40 0x04
38 #define AR9300_OPFLAGS_2G_HT40 0x08
39 #define AR9300_OPFLAGS_5G_HT20 0x10
40 #define AR9300_OPFLAGS_2G_HT20 0x20
41 #define AR9300_EEPMISC_BIG_ENDIAN 0x01
42 #define AR9300_EEPMISC_WOW 0x02
43 #define AR9300_CUSTOMER_DATA_SIZE 20
45 #define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
46 #define FBIN2FREQ(x, y) ((y) ? (2300 + x) : (4800 + 5 * x))
47 #define AR9300_MAX_CHAINS 3
48 #define AR9300_ANT_16S 25
49 #define AR9300_FUTURE_MODAL_SZ 6
51 #define AR9300_NUM_ANT_CHAIN_FIELDS 7
52 #define AR9300_NUM_ANT_COMMON_FIELDS 4
53 #define AR9300_SIZE_ANT_CHAIN_FIELD 3
54 #define AR9300_SIZE_ANT_COMMON_FIELD 4
55 #define AR9300_ANT_CHAIN_MASK 0x7
56 #define AR9300_ANT_COMMON_MASK 0xf
57 #define AR9300_CHAIN_0_IDX 0
58 #define AR9300_CHAIN_1_IDX 1
59 #define AR9300_CHAIN_2_IDX 2
61 #define AR928X_NUM_ANT_CHAIN_FIELDS 6
62 #define AR928X_SIZE_ANT_CHAIN_FIELD 2
63 #define AR928X_ANT_CHAIN_MASK 0x3
65 /* Delta from which to start power to pdadc table */
66 /* This offset is used in both open loop and closed loop power control
67 * schemes. In open loop power control, it is not really needed, but for
68 * the "sake of consistency" it was kept. For certain AP designs, this
69 * value is overwritten by the value in the flag "pwrTableOffset" just
70 * before writing the pdadc vs pwr into the chip registers.
72 #define AR9300_PWR_TABLE_OFFSET 0
74 /* enable flags for voltage and temp compensation */
75 #define ENABLE_TEMP_COMPENSATION 0x01
76 #define ENABLE_VOLT_COMPENSATION 0x02
77 /* byte addressable */
78 #define AR9300_EEPROM_SIZE (16*1024)
79 #define FIXED_CCA_THRESHOLD 15
81 #define AR9300_BASE_ADDR 0x3ff
83 enum targetPowerHTRates {
84 HT_TARGET_RATE_0_8_16,
85 HT_TARGET_RATE_1_3_9_11_17_19,
100 enum targetPowerLegacyRates {
101 LEGACY_TARGET_RATE_6_24,
102 LEGACY_TARGET_RATE_36,
103 LEGACY_TARGET_RATE_48,
104 LEGACY_TARGET_RATE_54
107 enum targetPowerCckRates {
108 LEGACY_TARGET_RATE_1L_5L,
109 LEGACY_TARGET_RATE_5S,
110 LEGACY_TARGET_RATE_11L,
111 LEGACY_TARGET_RATE_11S
115 ALL_TARGET_LEGACY_6_24,
116 ALL_TARGET_LEGACY_36,
117 ALL_TARGET_LEGACY_48,
118 ALL_TARGET_LEGACY_54,
119 ALL_TARGET_LEGACY_1L_5L,
120 ALL_TARGET_LEGACY_5S,
121 ALL_TARGET_LEGACY_11L,
122 ALL_TARGET_LEGACY_11S,
123 ALL_TARGET_HT20_0_8_16,
124 ALL_TARGET_HT20_1_3_9_11_17_19,
137 ALL_TARGET_HT40_0_8_16,
138 ALL_TARGET_HT40_1_3_9_11_17_19,
160 enum CompressAlgorithm {
171 struct ar9300_base_eep_hdr {
173 /* 4 bits tx and 4 bits rx */
175 struct eepFlags opCapFlags;
179 /* takes lower byte in eeprom location */
181 /* offset in dB to be added to beginning
182 * of pdadc table in calibration
184 int8_t pwrTableOffset;
185 u8 params_for_tuning_caps[2];
187 * bit0 - enable tx temp comp
188 * bit1 - enable tx volt comp
189 * bit2 - enable fastClock - default to 1
190 * bit3 - enable doubling - default to 1
191 * bit4 - enable internal regulator - default to 1
194 /* misc flags: bit0 - turn down drivestrength */
195 u8 miscConfiguration;
196 u8 eepromWriteEnableGpio;
201 /* SW controlled internal regulator fields */
205 struct ar9300_modal_eep_header {
206 /* 4 idle, t1, t2, b (4 bits per setting) */
207 __le32 antCtrlCommon;
208 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
209 __le32 antCtrlCommon2;
210 /* 6 idle, t, r, rx1, rx12, b (2 bits each) */
211 __le16 antCtrlChain[AR9300_MAX_CHAINS];
212 /* 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
213 u8 xatten1DB[AR9300_MAX_CHAINS];
214 /* 3 xatten1_margin for merlin (0xa20c/b20c 16:12 */
215 u8 xatten1Margin[AR9300_MAX_CHAINS];
218 /* spur channels in usual fbin coding format */
219 u8 spurChans[AR9300_EEPROM_MODAL_SPURS];
220 /* 3 Check if the register is per chain */
221 int8_t noiseFloorThreshCh[AR9300_MAX_CHAINS];
222 u8 ob[AR9300_MAX_CHAINS];
223 u8 db_stage2[AR9300_MAX_CHAINS];
224 u8 db_stage3[AR9300_MAX_CHAINS];
225 u8 db_stage4[AR9300_MAX_CHAINS];
227 u8 txFrameToDataStart;
232 int8_t adcDesiredSize;
240 struct ar9300_cal_data_per_freq_op_loop {
242 /* pdadc voltage at power measurement */
244 /* pcdac used for power measurement */
246 /* range is -60 to -127 create a mapping equation 1db resolution */
247 int8_t rxNoisefloorCal;
248 /*range is same as noisefloor */
249 int8_t rxNoisefloorPower;
250 /* temp measured when noisefloor cal was performed */
254 struct cal_tgt_pow_legacy {
258 struct cal_tgt_pow_ht {
262 struct cal_ctl_edge_pwr {
267 struct cal_ctl_data_2g {
268 struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_2G];
271 struct cal_ctl_data_5g {
272 struct cal_ctl_edge_pwr ctlEdges[AR9300_NUM_BAND_EDGES_5G];
275 struct ar9300_eeprom {
279 u8 custData[AR9300_CUSTOMER_DATA_SIZE];
281 struct ar9300_base_eep_hdr baseEepHeader;
283 struct ar9300_modal_eep_header modalHeader2G;
284 u8 calFreqPier2G[AR9300_NUM_2G_CAL_PIERS];
285 struct ar9300_cal_data_per_freq_op_loop
286 calPierData2G[AR9300_MAX_CHAINS][AR9300_NUM_2G_CAL_PIERS];
287 u8 calTarget_freqbin_Cck[AR9300_NUM_2G_CCK_TARGET_POWERS];
288 u8 calTarget_freqbin_2G[AR9300_NUM_2G_20_TARGET_POWERS];
289 u8 calTarget_freqbin_2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
290 u8 calTarget_freqbin_2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
291 struct cal_tgt_pow_legacy
292 calTargetPowerCck[AR9300_NUM_2G_CCK_TARGET_POWERS];
293 struct cal_tgt_pow_legacy
294 calTargetPower2G[AR9300_NUM_2G_20_TARGET_POWERS];
295 struct cal_tgt_pow_ht
296 calTargetPower2GHT20[AR9300_NUM_2G_20_TARGET_POWERS];
297 struct cal_tgt_pow_ht
298 calTargetPower2GHT40[AR9300_NUM_2G_40_TARGET_POWERS];
299 u8 ctlIndex_2G[AR9300_NUM_CTLS_2G];
300 u8 ctl_freqbin_2G[AR9300_NUM_CTLS_2G][AR9300_NUM_BAND_EDGES_2G];
301 struct cal_ctl_data_2g ctlPowerData_2G[AR9300_NUM_CTLS_2G];
302 struct ar9300_modal_eep_header modalHeader5G;
303 u8 calFreqPier5G[AR9300_NUM_5G_CAL_PIERS];
304 struct ar9300_cal_data_per_freq_op_loop
305 calPierData5G[AR9300_MAX_CHAINS][AR9300_NUM_5G_CAL_PIERS];
306 u8 calTarget_freqbin_5G[AR9300_NUM_5G_20_TARGET_POWERS];
307 u8 calTarget_freqbin_5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
308 u8 calTarget_freqbin_5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
309 struct cal_tgt_pow_legacy
310 calTargetPower5G[AR9300_NUM_5G_20_TARGET_POWERS];
311 struct cal_tgt_pow_ht
312 calTargetPower5GHT20[AR9300_NUM_5G_20_TARGET_POWERS];
313 struct cal_tgt_pow_ht
314 calTargetPower5GHT40[AR9300_NUM_5G_40_TARGET_POWERS];
315 u8 ctlIndex_5G[AR9300_NUM_CTLS_5G];
316 u8 ctl_freqbin_5G[AR9300_NUM_CTLS_5G][AR9300_NUM_BAND_EDGES_5G];
317 struct cal_ctl_data_5g ctlPowerData_5G[AR9300_NUM_CTLS_5G];
320 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah);
321 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah);