drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

   1 /*
   2  * Copyright (c) 2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "ar9003_phy.h"
  19 #include "ar9003_eeprom.h"
  20
  21 #define COMP_HDR_LEN 4
  22 #define COMP_CKSUM_LEN 2
  23
  24 #define AR_CH0_TOP (0x00016288)
  25 #define AR_CH0_TOP_XPABIASLVL (0x300)
  26 #define AR_CH0_TOP_XPABIASLVL_S (8)
  27
  28 #define AR_CH0_THERM (0x00016290)
  29 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
  30 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
  31 #define AR_CH0_THERM_XPASHORT2GND 0x4
  32 #define AR_CH0_THERM_XPASHORT2GND_S 2
  33
  34 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
  35 #define AR_SWITCH_TABLE_COM_ALL_S (0)
  36
  37 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
  38 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
  39
  40 #define AR_SWITCH_TABLE_ALL (0xfff)
  41 #define AR_SWITCH_TABLE_ALL_S (0)
  42
  43 #define LE16(x) __constant_cpu_to_le16(x)
  44 #define LE32(x) __constant_cpu_to_le32(x)
  45
  46 /* Local defines to distinguish between extension and control CTL's */
  47 #define EXT_ADDITIVE (0x8000)
  48 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  49 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  50 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  51 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  52 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9  /* 10*log10(3)*2 */
  53 #define PWRINCR_3_TO_1_CHAIN      9             /* 10*log(3)*2 */
  54 #define PWRINCR_3_TO_2_CHAIN      3             /* floor(10*log(3/2)*2) */
  55 #define PWRINCR_2_TO_1_CHAIN      6             /* 10*log(2)*2 */
  56
  57 #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
  58 #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
  59
  60 static int ar9003_hw_power_interpolate(int32_t x,
  61                                        int32_t *px, int32_t *py, u_int16_t np);
  62 static const struct ar9300_eeprom ar9300_default = {
  63         .eepromVersion = 2,
  64         .templateVersion = 2,
  65         .macAddr = {1, 2, 3, 4, 5, 6},
  66         .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  67                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
  68         .baseEepHeader = {
  69                 .regDmn = { LE16(0), LE16(0x1f) },
  70                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
  71                 .opCapFlags = {
  72                         .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
  73                         .eepMisc = 0,
  74                 },
  75                 .rfSilent = 0,
  76                 .blueToothOptions = 0,
  77                 .deviceCap = 0,
  78                 .deviceType = 5, /* takes lower byte in eeprom location */
  79                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  80                 .params_for_tuning_caps = {0, 0},
  81                 .featureEnable = 0x0c,
  82                  /*
  83                   * bit0 - enable tx temp comp - disabled
  84                   * bit1 - enable tx volt comp - disabled
  85                   * bit2 - enable fastClock - enabled
  86                   * bit3 - enable doubling - enabled
  87                   * bit4 - enable internal regulator - disabled
  88                   * bit5 - enable pa predistortion - disabled
  89                   */
  90                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
  91                 .eepromWriteEnableGpio = 3,
  92                 .wlanDisableGpio = 0,
  93                 .wlanLedGpio = 8,
  94                 .rxBandSelectGpio = 0xff,
  95                 .txrxgain = 0,
  96                 .swreg = 0,
  97          },
  98         .modalHeader2G = {
  99         /* ar9300_modal_eep_header  2g */
 100                 /* 4 idle,t1,t2,b(4 bits per setting) */
 101                 .antCtrlCommon = LE32(0x110),
 102                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 103                 .antCtrlCommon2 = LE32(0x22222),
 104
 105                 /*
 106                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 107                  * rx1, rx12, b (2 bits each)
 108                  */
 109                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 110
 111                 /*
 112                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 113                  * for ar9280 (0xa20c/b20c 5:0)
 114                  */
 115                 .xatten1DB = {0, 0, 0},
 116
 117                 /*
 118                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 119                  * for ar9280 (0xa20c/b20c 16:12
 120                  */
 121                 .xatten1Margin = {0, 0, 0},
 122                 .tempSlope = 36,
 123                 .voltSlope = 0,
 124
 125                 /*
 126                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 127                  * channels in usual fbin coding format
 128                  */
 129                 .spurChans = {0, 0, 0, 0, 0},
 130
 131                 /*
 132                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 133                  * if the register is per chain
 134                  */
 135                 .noiseFloorThreshCh = {-1, 0, 0},
 136                 .ob = {1, 1, 1},/* 3 chain */
 137                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
 138                 .db_stage3 = {0, 0, 0},
 139                 .db_stage4 = {0, 0, 0},
 140                 .xpaBiasLvl = 0,
 141                 .txFrameToDataStart = 0x0e,
 142                 .txFrameToPaOn = 0x0e,
 143                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 144                 .antennaGain = 0,
 145                 .switchSettling = 0x2c,
 146                 .adcDesiredSize = -30,
 147                 .txEndToXpaOff = 0,
 148                 .txEndToRxOn = 0x2,
 149                 .txFrameToXpaOn = 0xe,
 150                 .thresh62 = 28,
 151                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 152                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 153                 .futureModal = {
 154                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 155                 },
 156          },
 157         .base_ext1 = {
 158                 .ant_div_control = 0,
 159                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 160         },
 161         .calFreqPier2G = {
 162                 FREQ2FBIN(2412, 1),
 163                 FREQ2FBIN(2437, 1),
 164                 FREQ2FBIN(2472, 1),
 165          },
 166         /* ar9300_cal_data_per_freq_op_loop 2g */
 167         .calPierData2G = {
 168                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 169                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 170                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 171          },
 172         .calTarget_freqbin_Cck = {
 173                 FREQ2FBIN(2412, 1),
 174                 FREQ2FBIN(2484, 1),
 175          },
 176         .calTarget_freqbin_2G = {
 177                 FREQ2FBIN(2412, 1),
 178                 FREQ2FBIN(2437, 1),
 179                 FREQ2FBIN(2472, 1)
 180          },
 181         .calTarget_freqbin_2GHT20 = {
 182                 FREQ2FBIN(2412, 1),
 183                 FREQ2FBIN(2437, 1),
 184                 FREQ2FBIN(2472, 1)
 185          },
 186         .calTarget_freqbin_2GHT40 = {
 187                 FREQ2FBIN(2412, 1),
 188                 FREQ2FBIN(2437, 1),
 189                 FREQ2FBIN(2472, 1)
 190          },
 191         .calTargetPowerCck = {
 192                  /* 1L-5L,5S,11L,11S */
 193                  { {36, 36, 36, 36} },
 194                  { {36, 36, 36, 36} },
 195         },
 196         .calTargetPower2G = {
 197                  /* 6-24,36,48,54 */
 198                  { {32, 32, 28, 24} },
 199                  { {32, 32, 28, 24} },
 200                  { {32, 32, 28, 24} },
 201         },
 202         .calTargetPower2GHT20 = {
 203                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 204                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 205                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 206         },
 207         .calTargetPower2GHT40 = {
 208                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 209                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 210                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 211         },
 212         .ctlIndex_2G =  {
 213                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 214                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 215         },
 216         .ctl_freqbin_2G = {
 217                 {
 218                         FREQ2FBIN(2412, 1),
 219                         FREQ2FBIN(2417, 1),
 220                         FREQ2FBIN(2457, 1),
 221                         FREQ2FBIN(2462, 1)
 222                 },
 223                 {
 224                         FREQ2FBIN(2412, 1),
 225                         FREQ2FBIN(2417, 1),
 226                         FREQ2FBIN(2462, 1),
 227                         0xFF,
 228                 },
 229
 230                 {
 231                         FREQ2FBIN(2412, 1),
 232                         FREQ2FBIN(2417, 1),
 233                         FREQ2FBIN(2462, 1),
 234                         0xFF,
 235                 },
 236                 {
 237                         FREQ2FBIN(2422, 1),
 238                         FREQ2FBIN(2427, 1),
 239                         FREQ2FBIN(2447, 1),
 240                         FREQ2FBIN(2452, 1)
 241                 },
 242
 243                 {
 244                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 245                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 246                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 247                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 248                 },
 249
 250                 {
 251                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 252                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 253                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 254                         0,
 255                 },
 256
 257                 {
 258                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 259                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 260                         FREQ2FBIN(2472, 1),
 261                         0,
 262                 },
 263
 264                 {
 265                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 266                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 267                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 268                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 269                 },
 270
 271                 {
 272                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 273                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 274                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 275                 },
 276
 277                 {
 278                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 279                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 280                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 281                         0
 282                 },
 283
 284                 {
 285                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 286                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 287                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 288                         0
 289                 },
 290
 291                 {
 292                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 293                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 294                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 295                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 296                 }
 297          },
 298         .ctlPowerData_2G = {
 299                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 300                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 301                  { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
 302
 303                  { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
 304                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 305                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 306
 307                  { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
 308                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 309                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 310
 311                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 312                  { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
 313                  { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
 314          },
 315         .modalHeader5G = {
 316                 /* 4 idle,t1,t2,b (4 bits per setting) */
 317                 .antCtrlCommon = LE32(0x110),
 318                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 319                 .antCtrlCommon2 = LE32(0x22222),
 320                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 321                 .antCtrlChain = {
 322                         LE16(0x000), LE16(0x000), LE16(0x000),
 323                 },
 324                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 325                 .xatten1DB = {0, 0, 0},
 326
 327                 /*
 328                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 329                  * for merlin (0xa20c/b20c 16:12
 330                  */
 331                 .xatten1Margin = {0, 0, 0},
 332                 .tempSlope = 68,
 333                 .voltSlope = 0,
 334                 /* spurChans spur channels in usual fbin coding format */
 335                 .spurChans = {0, 0, 0, 0, 0},
 336                 /* noiseFloorThreshCh Check if the register is per chain */
 337                 .noiseFloorThreshCh = {-1, 0, 0},
 338                 .ob = {3, 3, 3}, /* 3 chain */
 339                 .db_stage2 = {3, 3, 3}, /* 3 chain */
 340                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 341                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 342                 .xpaBiasLvl = 0,
 343                 .txFrameToDataStart = 0x0e,
 344                 .txFrameToPaOn = 0x0e,
 345                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 346                 .antennaGain = 0,
 347                 .switchSettling = 0x2d,
 348                 .adcDesiredSize = -30,
 349                 .txEndToXpaOff = 0,
 350                 .txEndToRxOn = 0x2,
 351                 .txFrameToXpaOn = 0xe,
 352                 .thresh62 = 28,
 353                 .papdRateMaskHt20 = LE32(0x0c80c080),
 354                 .papdRateMaskHt40 = LE32(0x0080c080),
 355                 .futureModal = {
 356                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 357                 },
 358          },
 359         .base_ext2 = {
 360                 .tempSlopeLow = 0,
 361                 .tempSlopeHigh = 0,
 362                 .xatten1DBLow = {0, 0, 0},
 363                 .xatten1MarginLow = {0, 0, 0},
 364                 .xatten1DBHigh = {0, 0, 0},
 365                 .xatten1MarginHigh = {0, 0, 0}
 366         },
 367         .calFreqPier5G = {
 368                 FREQ2FBIN(5180, 0),
 369                 FREQ2FBIN(5220, 0),
 370                 FREQ2FBIN(5320, 0),
 371                 FREQ2FBIN(5400, 0),
 372                 FREQ2FBIN(5500, 0),
 373                 FREQ2FBIN(5600, 0),
 374                 FREQ2FBIN(5725, 0),
 375                 FREQ2FBIN(5825, 0)
 376         },
 377         .calPierData5G = {
 378                         {
 379                                 {0, 0, 0, 0, 0},
 380                                 {0, 0, 0, 0, 0},
 381                                 {0, 0, 0, 0, 0},
 382                                 {0, 0, 0, 0, 0},
 383                                 {0, 0, 0, 0, 0},
 384                                 {0, 0, 0, 0, 0},
 385                                 {0, 0, 0, 0, 0},
 386                                 {0, 0, 0, 0, 0},
 387                         },
 388                         {
 389                                 {0, 0, 0, 0, 0},
 390                                 {0, 0, 0, 0, 0},
 391                                 {0, 0, 0, 0, 0},
 392                                 {0, 0, 0, 0, 0},
 393                                 {0, 0, 0, 0, 0},
 394                                 {0, 0, 0, 0, 0},
 395                                 {0, 0, 0, 0, 0},
 396                                 {0, 0, 0, 0, 0},
 397                         },
 398                         {
 399                                 {0, 0, 0, 0, 0},
 400                                 {0, 0, 0, 0, 0},
 401                                 {0, 0, 0, 0, 0},
 402                                 {0, 0, 0, 0, 0},
 403                                 {0, 0, 0, 0, 0},
 404                                 {0, 0, 0, 0, 0},
 405                                 {0, 0, 0, 0, 0},
 406                                 {0, 0, 0, 0, 0},
 407                         },
 408
 409         },
 410         .calTarget_freqbin_5G = {
 411                 FREQ2FBIN(5180, 0),
 412                 FREQ2FBIN(5220, 0),
 413                 FREQ2FBIN(5320, 0),
 414                 FREQ2FBIN(5400, 0),
 415                 FREQ2FBIN(5500, 0),
 416                 FREQ2FBIN(5600, 0),
 417                 FREQ2FBIN(5725, 0),
 418                 FREQ2FBIN(5825, 0)
 419         },
 420         .calTarget_freqbin_5GHT20 = {
 421                 FREQ2FBIN(5180, 0),
 422                 FREQ2FBIN(5240, 0),
 423                 FREQ2FBIN(5320, 0),
 424                 FREQ2FBIN(5500, 0),
 425                 FREQ2FBIN(5700, 0),
 426                 FREQ2FBIN(5745, 0),
 427                 FREQ2FBIN(5725, 0),
 428                 FREQ2FBIN(5825, 0)
 429         },
 430         .calTarget_freqbin_5GHT40 = {
 431                 FREQ2FBIN(5180, 0),
 432                 FREQ2FBIN(5240, 0),
 433                 FREQ2FBIN(5320, 0),
 434                 FREQ2FBIN(5500, 0),
 435                 FREQ2FBIN(5700, 0),
 436                 FREQ2FBIN(5745, 0),
 437                 FREQ2FBIN(5725, 0),
 438                 FREQ2FBIN(5825, 0)
 439          },
 440         .calTargetPower5G = {
 441                 /* 6-24,36,48,54 */
 442                 { {20, 20, 20, 10} },
 443                 { {20, 20, 20, 10} },
 444                 { {20, 20, 20, 10} },
 445                 { {20, 20, 20, 10} },
 446                 { {20, 20, 20, 10} },
 447                 { {20, 20, 20, 10} },
 448                 { {20, 20, 20, 10} },
 449                 { {20, 20, 20, 10} },
 450          },
 451         .calTargetPower5GHT20 = {
 452                 /*
 453                  * 0_8_16,1-3_9-11_17-19,
 454                  * 4,5,6,7,12,13,14,15,20,21,22,23
 455                  */
 456                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 457                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 458                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 459                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 460                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 461                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 462                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 463                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 464          },
 465         .calTargetPower5GHT40 =  {
 466                 /*
 467                  * 0_8_16,1-3_9-11_17-19,
 468                  * 4,5,6,7,12,13,14,15,20,21,22,23
 469                  */
 470                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 471                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 472                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 473                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 474                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 475                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 476                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 477                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 478          },
 479         .ctlIndex_5G =  {
 480                 0x10, 0x16, 0x18, 0x40, 0x46,
 481                 0x48, 0x30, 0x36, 0x38
 482         },
 483         .ctl_freqbin_5G =  {
 484                 {
 485                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 486                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 487                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 488                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 489                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 490                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 491                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 492                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 493                 },
 494                 {
 495                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 496                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 497                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 498                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 499                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 500                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 501                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 502                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 503                 },
 504
 505                 {
 506                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 507                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 508                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 509                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 510                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 511                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 512                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 513                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 514                 },
 515
 516                 {
 517                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 518                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 519                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 520                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 521                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 522                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 523                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
 524                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
 525                 },
 526
 527                 {
 528                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 529                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 530                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 531                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 532                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
 533                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
 534                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
 535                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
 536                 },
 537
 538                 {
 539                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 540                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 541                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 542                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 543                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 544                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 545                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
 546                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
 547                 },
 548
 549                 {
 550                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 551                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 552                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 553                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 554                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 555                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 556                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 557                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 558                 },
 559
 560                 {
 561                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 562                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 563                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 564                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 565                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 566                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 567                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 568                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 569                 },
 570
 571                 {
 572                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 573                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 574                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 575                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 576                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 577                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 578                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 579                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 580                 }
 581          },
 582         .ctlPowerData_5G = {
 583                 {
 584                         {
 585                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
 586                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
 587                         }
 588                 },
 589                 {
 590                         {
 591                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
 592                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
 593                         }
 594                 },
 595                 {
 596                         {
 597                                 {60, 0}, {60, 1}, {60, 0}, {60, 1},
 598                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
 599                         }
 600                 },
 601                 {
 602                         {
 603                                 {60, 0}, {60, 1}, {60, 1}, {60, 0},
 604                                 {60, 1}, {60, 0}, {60, 0}, {60, 0},
 605                         }
 606                 },
 607                 {
 608                         {
 609                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
 610                                 {60, 0}, {60, 0}, {60, 0}, {60, 0},
 611                         }
 612                 },
 613                 {
 614                         {
 615                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
 616                                 {60, 1}, {60, 0}, {60, 0}, {60, 0},
 617                         }
 618                 },
 619                 {
 620                         {
 621                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
 622                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
 623                         }
 624                 },
 625                 {
 626                         {
 627                                 {60, 1}, {60, 1}, {60, 0}, {60, 1},
 628                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
 629                         }
 630                 },
 631                 {
 632                         {
 633                                 {60, 1}, {60, 0}, {60, 1}, {60, 1},
 634                                 {60, 1}, {60, 1}, {60, 0}, {60, 1},
 635                         }
 636                 },
 637          }
 638 };
 639
 640 static const struct ar9300_eeprom ar9300_x113 = {
 641         .eepromVersion = 2,
 642         .templateVersion = 6,
 643         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 644         .custData = {"x113-023-f0000"},
 645         .baseEepHeader = {
 646                 .regDmn = { LE16(0), LE16(0x1f) },
 647                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 648                 .opCapFlags = {
 649                         .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
 650                         .eepMisc = 0,
 651                 },
 652                 .rfSilent = 0,
 653                 .blueToothOptions = 0,
 654                 .deviceCap = 0,
 655                 .deviceType = 5, /* takes lower byte in eeprom location */
 656                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 657                 .params_for_tuning_caps = {0, 0},
 658                 .featureEnable = 0x0d,
 659                  /*
 660                   * bit0 - enable tx temp comp - disabled
 661                   * bit1 - enable tx volt comp - disabled
 662                   * bit2 - enable fastClock - enabled
 663                   * bit3 - enable doubling - enabled
 664                   * bit4 - enable internal regulator - disabled
 665                   * bit5 - enable pa predistortion - disabled
 666                   */
 667                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 668                 .eepromWriteEnableGpio = 6,
 669                 .wlanDisableGpio = 0,
 670                 .wlanLedGpio = 8,
 671                 .rxBandSelectGpio = 0xff,
 672                 .txrxgain = 0x21,
 673                 .swreg = 0,
 674          },
 675         .modalHeader2G = {
 676         /* ar9300_modal_eep_header  2g */
 677                 /* 4 idle,t1,t2,b(4 bits per setting) */
 678                 .antCtrlCommon = LE32(0x110),
 679                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 680                 .antCtrlCommon2 = LE32(0x44444),
 681
 682                 /*
 683                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 684                  * rx1, rx12, b (2 bits each)
 685                  */
 686                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 687
 688                 /*
 689                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 690                  * for ar9280 (0xa20c/b20c 5:0)
 691                  */
 692                 .xatten1DB = {0, 0, 0},
 693
 694                 /*
 695                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 696                  * for ar9280 (0xa20c/b20c 16:12
 697                  */
 698                 .xatten1Margin = {0, 0, 0},
 699                 .tempSlope = 25,
 700                 .voltSlope = 0,
 701
 702                 /*
 703                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 704                  * channels in usual fbin coding format
 705                  */
 706                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 707
 708                 /*
 709                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 710                  * if the register is per chain
 711                  */
 712                 .noiseFloorThreshCh = {-1, 0, 0},
 713                 .ob = {1, 1, 1},/* 3 chain */
 714                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
 715                 .db_stage3 = {0, 0, 0},
 716                 .db_stage4 = {0, 0, 0},
 717                 .xpaBiasLvl = 0,
 718                 .txFrameToDataStart = 0x0e,
 719                 .txFrameToPaOn = 0x0e,
 720                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 721                 .antennaGain = 0,
 722                 .switchSettling = 0x2c,
 723                 .adcDesiredSize = -30,
 724                 .txEndToXpaOff = 0,
 725                 .txEndToRxOn = 0x2,
 726                 .txFrameToXpaOn = 0xe,
 727                 .thresh62 = 28,
 728                 .papdRateMaskHt20 = LE32(0x0c80c080),
 729                 .papdRateMaskHt40 = LE32(0x0080c080),
 730                 .futureModal = {
 731                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 732                 },
 733          },
 734          .base_ext1 = {
 735                 .ant_div_control = 0,
 736                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 737          },
 738         .calFreqPier2G = {
 739                 FREQ2FBIN(2412, 1),
 740                 FREQ2FBIN(2437, 1),
 741                 FREQ2FBIN(2472, 1),
 742          },
 743         /* ar9300_cal_data_per_freq_op_loop 2g */
 744         .calPierData2G = {
 745                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 746                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 747                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 748          },
 749         .calTarget_freqbin_Cck = {
 750                 FREQ2FBIN(2412, 1),
 751                 FREQ2FBIN(2472, 1),
 752          },
 753         .calTarget_freqbin_2G = {
 754                 FREQ2FBIN(2412, 1),
 755                 FREQ2FBIN(2437, 1),
 756                 FREQ2FBIN(2472, 1)
 757          },
 758         .calTarget_freqbin_2GHT20 = {
 759                 FREQ2FBIN(2412, 1),
 760                 FREQ2FBIN(2437, 1),
 761                 FREQ2FBIN(2472, 1)
 762          },
 763         .calTarget_freqbin_2GHT40 = {
 764                 FREQ2FBIN(2412, 1),
 765                 FREQ2FBIN(2437, 1),
 766                 FREQ2FBIN(2472, 1)
 767          },
 768         .calTargetPowerCck = {
 769                  /* 1L-5L,5S,11L,11S */
 770                  { {34, 34, 34, 34} },
 771                  { {34, 34, 34, 34} },
 772         },
 773         .calTargetPower2G = {
 774                  /* 6-24,36,48,54 */
 775                  { {34, 34, 32, 32} },
 776                  { {34, 34, 32, 32} },
 777                  { {34, 34, 32, 32} },
 778         },
 779         .calTargetPower2GHT20 = {
 780                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 781                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 782                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 783         },
 784         .calTargetPower2GHT40 = {
 785                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 786                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 787                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 788         },
 789         .ctlIndex_2G =  {
 790                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 791                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 792         },
 793         .ctl_freqbin_2G = {
 794                 {
 795                         FREQ2FBIN(2412, 1),
 796                         FREQ2FBIN(2417, 1),
 797                         FREQ2FBIN(2457, 1),
 798                         FREQ2FBIN(2462, 1)
 799                 },
 800                 {
 801                         FREQ2FBIN(2412, 1),
 802                         FREQ2FBIN(2417, 1),
 803                         FREQ2FBIN(2462, 1),
 804                         0xFF,
 805                 },
 806
 807                 {
 808                         FREQ2FBIN(2412, 1),
 809                         FREQ2FBIN(2417, 1),
 810                         FREQ2FBIN(2462, 1),
 811                         0xFF,
 812                 },
 813                 {
 814                         FREQ2FBIN(2422, 1),
 815                         FREQ2FBIN(2427, 1),
 816                         FREQ2FBIN(2447, 1),
 817                         FREQ2FBIN(2452, 1)
 818                 },
 819
 820                 {
 821                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 822                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 823                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 824                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 825                 },
 826
 827                 {
 828                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 829                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 830                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 831                         0,
 832                 },
 833
 834                 {
 835                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 836                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 837                         FREQ2FBIN(2472, 1),
 838                         0,
 839                 },
 840
 841                 {
 842                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 843                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 844                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 845                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 846                 },
 847
 848                 {
 849                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 850                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 851                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 852                 },
 853
 854                 {
 855                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 856                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 857                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 858                         0
 859                 },
 860
 861                 {
 862                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 863                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 864                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 865                         0
 866                 },
 867
 868                 {
 869                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 870                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 871                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 872                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 873                 }
 874          },
 875         .ctlPowerData_2G = {
 876                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 877                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 878                  { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
 879
 880                  { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
 881                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 882                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 883
 884                  { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
 885                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 886                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 887
 888                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
 889                  { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
 890                  { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
 891          },
 892         .modalHeader5G = {
 893                 /* 4 idle,t1,t2,b (4 bits per setting) */
 894                 .antCtrlCommon = LE32(0x220),
 895                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 896                 .antCtrlCommon2 = LE32(0x11111),
 897                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 898                 .antCtrlChain = {
 899                         LE16(0x150), LE16(0x150), LE16(0x150),
 900                 },
 901                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 902                 .xatten1DB = {0, 0, 0},
 903
 904                 /*
 905                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 906                  * for merlin (0xa20c/b20c 16:12
 907                  */
 908                 .xatten1Margin = {0, 0, 0},
 909                 .tempSlope = 68,
 910                 .voltSlope = 0,
 911                 /* spurChans spur channels in usual fbin coding format */
 912                 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
 913                 /* noiseFloorThreshCh Check if the register is per chain */
 914                 .noiseFloorThreshCh = {-1, 0, 0},
 915                 .ob = {3, 3, 3}, /* 3 chain */
 916                 .db_stage2 = {3, 3, 3}, /* 3 chain */
 917                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 918                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 919                 .xpaBiasLvl = 0,
 920                 .txFrameToDataStart = 0x0e,
 921                 .txFrameToPaOn = 0x0e,
 922                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 923                 .antennaGain = 0,
 924                 .switchSettling = 0x2d,
 925                 .adcDesiredSize = -30,
 926                 .txEndToXpaOff = 0,
 927                 .txEndToRxOn = 0x2,
 928                 .txFrameToXpaOn = 0xe,
 929                 .thresh62 = 28,
 930                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 931                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 932                 .futureModal = {
 933                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 934                 },
 935          },
 936         .base_ext2 = {
 937                 .tempSlopeLow = 72,
 938                 .tempSlopeHigh = 105,
 939                 .xatten1DBLow = {0, 0, 0},
 940                 .xatten1MarginLow = {0, 0, 0},
 941                 .xatten1DBHigh = {0, 0, 0},
 942                 .xatten1MarginHigh = {0, 0, 0}
 943          },
 944         .calFreqPier5G = {
 945                 FREQ2FBIN(5180, 0),
 946                 FREQ2FBIN(5240, 0),
 947                 FREQ2FBIN(5320, 0),
 948                 FREQ2FBIN(5400, 0),
 949                 FREQ2FBIN(5500, 0),
 950                 FREQ2FBIN(5600, 0),
 951                 FREQ2FBIN(5745, 0),
 952                 FREQ2FBIN(5785, 0)
 953         },
 954         .calPierData5G = {
 955                         {
 956                                 {0, 0, 0, 0, 0},
 957                                 {0, 0, 0, 0, 0},
 958                                 {0, 0, 0, 0, 0},
 959                                 {0, 0, 0, 0, 0},
 960                                 {0, 0, 0, 0, 0},
 961                                 {0, 0, 0, 0, 0},
 962                                 {0, 0, 0, 0, 0},
 963                                 {0, 0, 0, 0, 0},
 964                         },
 965                         {
 966                                 {0, 0, 0, 0, 0},
 967                                 {0, 0, 0, 0, 0},
 968                                 {0, 0, 0, 0, 0},
 969                                 {0, 0, 0, 0, 0},
 970                                 {0, 0, 0, 0, 0},
 971                                 {0, 0, 0, 0, 0},
 972                                 {0, 0, 0, 0, 0},
 973                                 {0, 0, 0, 0, 0},
 974                         },
 975                         {
 976                                 {0, 0, 0, 0, 0},
 977                                 {0, 0, 0, 0, 0},
 978                                 {0, 0, 0, 0, 0},
 979                                 {0, 0, 0, 0, 0},
 980                                 {0, 0, 0, 0, 0},
 981                                 {0, 0, 0, 0, 0},
 982                                 {0, 0, 0, 0, 0},
 983                                 {0, 0, 0, 0, 0},
 984                         },
 985
 986         },
 987         .calTarget_freqbin_5G = {
 988                 FREQ2FBIN(5180, 0),
 989                 FREQ2FBIN(5220, 0),
 990                 FREQ2FBIN(5320, 0),
 991                 FREQ2FBIN(5400, 0),
 992                 FREQ2FBIN(5500, 0),
 993                 FREQ2FBIN(5600, 0),
 994                 FREQ2FBIN(5745, 0),
 995                 FREQ2FBIN(5785, 0)
 996         },
 997         .calTarget_freqbin_5GHT20 = {
 998                 FREQ2FBIN(5180, 0),
 999                 FREQ2FBIN(5240, 0),
1000                 FREQ2FBIN(5320, 0),
1001                 FREQ2FBIN(5400, 0),
1002                 FREQ2FBIN(5500, 0),
1003                 FREQ2FBIN(5700, 0),
1004                 FREQ2FBIN(5745, 0),
1005                 FREQ2FBIN(5825, 0)
1006         },
1007         .calTarget_freqbin_5GHT40 = {
1008                 FREQ2FBIN(5190, 0),
1009                 FREQ2FBIN(5230, 0),
1010                 FREQ2FBIN(5320, 0),
1011                 FREQ2FBIN(5410, 0),
1012                 FREQ2FBIN(5510, 0),
1013                 FREQ2FBIN(5670, 0),
1014                 FREQ2FBIN(5755, 0),
1015                 FREQ2FBIN(5825, 0)
1016          },
1017         .calTargetPower5G = {
1018                 /* 6-24,36,48,54 */
1019                 { {42, 40, 40, 34} },
1020                 { {42, 40, 40, 34} },
1021                 { {42, 40, 40, 34} },
1022                 { {42, 40, 40, 34} },
1023                 { {42, 40, 40, 34} },
1024                 { {42, 40, 40, 34} },
1025                 { {42, 40, 40, 34} },
1026                 { {42, 40, 40, 34} },
1027          },
1028         .calTargetPower5GHT20 = {
1029                 /*
1030                  * 0_8_16,1-3_9-11_17-19,
1031                  * 4,5,6,7,12,13,14,15,20,21,22,23
1032                  */
1033                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1034                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1035                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1036                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1037                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1038                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1039                 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1040                 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1041          },
1042         .calTargetPower5GHT40 =  {
1043                 /*
1044                  * 0_8_16,1-3_9-11_17-19,
1045                  * 4,5,6,7,12,13,14,15,20,21,22,23
1046                  */
1047                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1048                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1049                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1050                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1051                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1052                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1053                 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1054                 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1055          },
1056         .ctlIndex_5G =  {
1057                 0x10, 0x16, 0x18, 0x40, 0x46,
1058                 0x48, 0x30, 0x36, 0x38
1059         },
1060         .ctl_freqbin_5G =  {
1061                 {
1062                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1063                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1064                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1065                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1066                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1067                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1068                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1069                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1070                 },
1071                 {
1072                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1073                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1074                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1075                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1076                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1077                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1078                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1079                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1080                 },
1081
1082                 {
1083                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1084                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1085                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1086                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1087                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1088                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1089                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1090                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1091                 },
1092
1093                 {
1094                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1095                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1096                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1097                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1098                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1099                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1100                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1101                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1102                 },
1103
1104                 {
1105                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1106                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1107                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1108                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1109                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1110                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1111                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1112                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1113                 },
1114
1115                 {
1116                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1117                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1118                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1119                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1120                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1121                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1122                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1123                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1124                 },
1125
1126                 {
1127                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1128                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1129                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1130                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1131                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1132                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1133                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1134                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1135                 },
1136
1137                 {
1138                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1139                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1140                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1141                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1142                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1143                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1144                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1145                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1146                 },
1147
1148                 {
1149                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1150                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1151                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1152                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1153                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1154                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1155                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1156                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1157                 }
1158          },
1159         .ctlPowerData_5G = {
1160                 {
1161                         {
1162                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1163                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1164                         }
1165                 },
1166                 {
1167                         {
1168                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1169                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1170                         }
1171                 },
1172                 {
1173                         {
1174                                 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1175                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1176                         }
1177                 },
1178                 {
1179                         {
1180                                 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1181                                 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1182                         }
1183                 },
1184                 {
1185                         {
1186                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1187                                 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1188                         }
1189                 },
1190                 {
1191                         {
1192                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1193                                 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1194                         }
1195                 },
1196                 {
1197                         {
1198                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1199                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1200                         }
1201                 },
1202                 {
1203                         {
1204                                 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1205                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1206                         }
1207                 },
1208                 {
1209                         {
1210                                 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1211                                 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1212                         }
1213                 },
1214          }
1215 };
1216
1217
1218 static const struct ar9300_eeprom ar9300_h112 = {
1219         .eepromVersion = 2,
1220         .templateVersion = 3,
1221         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1222         .custData = {"h112-241-f0000"},
1223         .baseEepHeader = {
1224                 .regDmn = { LE16(0), LE16(0x1f) },
1225                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1226                 .opCapFlags = {
1227                         .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1228                         .eepMisc = 0,
1229                 },
1230                 .rfSilent = 0,
1231                 .blueToothOptions = 0,
1232                 .deviceCap = 0,
1233                 .deviceType = 5, /* takes lower byte in eeprom location */
1234                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1235                 .params_for_tuning_caps = {0, 0},
1236                 .featureEnable = 0x0d,
1237                 /*
1238                  * bit0 - enable tx temp comp - disabled
1239                  * bit1 - enable tx volt comp - disabled
1240                  * bit2 - enable fastClock - enabled
1241                  * bit3 - enable doubling - enabled
1242                  * bit4 - enable internal regulator - disabled
1243                  * bit5 - enable pa predistortion - disabled
1244                  */
1245                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1246                 .eepromWriteEnableGpio = 6,
1247                 .wlanDisableGpio = 0,
1248                 .wlanLedGpio = 8,
1249                 .rxBandSelectGpio = 0xff,
1250                 .txrxgain = 0x10,
1251                 .swreg = 0,
1252         },
1253         .modalHeader2G = {
1254                 /* ar9300_modal_eep_header  2g */
1255                 /* 4 idle,t1,t2,b(4 bits per setting) */
1256                 .antCtrlCommon = LE32(0x110),
1257                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1258                 .antCtrlCommon2 = LE32(0x44444),
1259
1260                 /*
1261                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1262                  * rx1, rx12, b (2 bits each)
1263                  */
1264                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1265
1266                 /*
1267                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
1268                  * for ar9280 (0xa20c/b20c 5:0)
1269                  */
1270                 .xatten1DB = {0, 0, 0},
1271
1272                 /*
1273                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1274                  * for ar9280 (0xa20c/b20c 16:12
1275                  */
1276                 .xatten1Margin = {0, 0, 0},
1277                 .tempSlope = 25,
1278                 .voltSlope = 0,
1279
1280                 /*
1281                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1282                  * channels in usual fbin coding format
1283                  */
1284                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1285
1286                 /*
1287                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1288                  * if the register is per chain
1289                  */
1290                 .noiseFloorThreshCh = {-1, 0, 0},
1291                 .ob = {1, 1, 1},/* 3 chain */
1292                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
1293                 .db_stage3 = {0, 0, 0},
1294                 .db_stage4 = {0, 0, 0},
1295                 .xpaBiasLvl = 0,
1296                 .txFrameToDataStart = 0x0e,
1297                 .txFrameToPaOn = 0x0e,
1298                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1299                 .antennaGain = 0,
1300                 .switchSettling = 0x2c,
1301                 .adcDesiredSize = -30,
1302                 .txEndToXpaOff = 0,
1303                 .txEndToRxOn = 0x2,
1304                 .txFrameToXpaOn = 0xe,
1305                 .thresh62 = 28,
1306                 .papdRateMaskHt20 = LE32(0x80c080),
1307                 .papdRateMaskHt40 = LE32(0x80c080),
1308                 .futureModal = {
1309                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1310                 },
1311         },
1312         .base_ext1 = {
1313                 .ant_div_control = 0,
1314                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1315         },
1316         .calFreqPier2G = {
1317                 FREQ2FBIN(2412, 1),
1318                 FREQ2FBIN(2437, 1),
1319                 FREQ2FBIN(2472, 1),
1320         },
1321         /* ar9300_cal_data_per_freq_op_loop 2g */
1322         .calPierData2G = {
1323                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1324                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1325                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1326         },
1327         .calTarget_freqbin_Cck = {
1328                 FREQ2FBIN(2412, 1),
1329                 FREQ2FBIN(2484, 1),
1330         },
1331         .calTarget_freqbin_2G = {
1332                 FREQ2FBIN(2412, 1),
1333                 FREQ2FBIN(2437, 1),
1334                 FREQ2FBIN(2472, 1)
1335         },
1336         .calTarget_freqbin_2GHT20 = {
1337                 FREQ2FBIN(2412, 1),
1338                 FREQ2FBIN(2437, 1),
1339                 FREQ2FBIN(2472, 1)
1340         },
1341         .calTarget_freqbin_2GHT40 = {
1342                 FREQ2FBIN(2412, 1),
1343                 FREQ2FBIN(2437, 1),
1344                 FREQ2FBIN(2472, 1)
1345         },
1346         .calTargetPowerCck = {
1347                 /* 1L-5L,5S,11L,11S */
1348                 { {34, 34, 34, 34} },
1349                 { {34, 34, 34, 34} },
1350         },
1351         .calTargetPower2G = {
1352                 /* 6-24,36,48,54 */
1353                 { {34, 34, 32, 32} },
1354                 { {34, 34, 32, 32} },
1355                 { {34, 34, 32, 32} },
1356         },
1357         .calTargetPower2GHT20 = {
1358                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1359                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1360                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1361         },
1362         .calTargetPower2GHT40 = {
1363                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1364                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1365                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1366         },
1367         .ctlIndex_2G =  {
1368                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1369                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1370         },
1371         .ctl_freqbin_2G = {
1372                 {
1373                         FREQ2FBIN(2412, 1),
1374                         FREQ2FBIN(2417, 1),
1375                         FREQ2FBIN(2457, 1),
1376                         FREQ2FBIN(2462, 1)
1377                 },
1378                 {
1379                         FREQ2FBIN(2412, 1),
1380                         FREQ2FBIN(2417, 1),
1381                         FREQ2FBIN(2462, 1),
1382                         0xFF,
1383                 },
1384
1385                 {
1386                         FREQ2FBIN(2412, 1),
1387                         FREQ2FBIN(2417, 1),
1388                         FREQ2FBIN(2462, 1),
1389                         0xFF,
1390                 },
1391                 {
1392                         FREQ2FBIN(2422, 1),
1393                         FREQ2FBIN(2427, 1),
1394                         FREQ2FBIN(2447, 1),
1395                         FREQ2FBIN(2452, 1)
1396                 },
1397
1398                 {
1399                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1400                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1401                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1402                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1403                 },
1404
1405                 {
1406                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1409                         0,
1410                 },
1411
1412                 {
1413                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415                         FREQ2FBIN(2472, 1),
1416                         0,
1417                 },
1418
1419                 {
1420                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1421                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1422                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1423                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1424                 },
1425
1426                 {
1427                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1428                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1429                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1430                 },
1431
1432                 {
1433                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1434                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1435                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1436                         0
1437                 },
1438
1439                 {
1440                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1441                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1442                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1443                         0
1444                 },
1445
1446                 {
1447                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1448                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1449                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1450                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1451                 }
1452         },
1453         .ctlPowerData_2G = {
1454                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1455                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1456                 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
1457
1458                 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
1459                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1460                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1461
1462                 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
1463                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1464                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1465
1466                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
1467                 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1468                 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
1469         },
1470         .modalHeader5G = {
1471                 /* 4 idle,t1,t2,b (4 bits per setting) */
1472                 .antCtrlCommon = LE32(0x220),
1473                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1474                 .antCtrlCommon2 = LE32(0x44444),
1475                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1476                 .antCtrlChain = {
1477                         LE16(0x150), LE16(0x150), LE16(0x150),
1478                 },
1479                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1480                 .xatten1DB = {0, 0, 0},
1481
1482                 /*
1483                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1484                  * for merlin (0xa20c/b20c 16:12
1485                  */
1486                 .xatten1Margin = {0, 0, 0},
1487                 .tempSlope = 45,
1488                 .voltSlope = 0,
1489                 /* spurChans spur channels in usual fbin coding format */
1490                 .spurChans = {0, 0, 0, 0, 0},
1491                 /* noiseFloorThreshCh Check if the register is per chain */
1492                 .noiseFloorThreshCh = {-1, 0, 0},
1493                 .ob = {3, 3, 3}, /* 3 chain */
1494                 .db_stage2 = {3, 3, 3}, /* 3 chain */
1495                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1496                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
1497                 .xpaBiasLvl = 0,
1498                 .txFrameToDataStart = 0x0e,
1499                 .txFrameToPaOn = 0x0e,
1500                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1501                 .antennaGain = 0,
1502                 .switchSettling = 0x2d,
1503                 .adcDesiredSize = -30,
1504                 .txEndToXpaOff = 0,
1505                 .txEndToRxOn = 0x2,
1506                 .txFrameToXpaOn = 0xe,
1507                 .thresh62 = 28,
1508                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1509                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1510                 .futureModal = {
1511                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1512                 },
1513         },
1514         .base_ext2 = {
1515                 .tempSlopeLow = 40,
1516                 .tempSlopeHigh = 50,
1517                 .xatten1DBLow = {0, 0, 0},
1518                 .xatten1MarginLow = {0, 0, 0},
1519                 .xatten1DBHigh = {0, 0, 0},
1520                 .xatten1MarginHigh = {0, 0, 0}
1521         },
1522         .calFreqPier5G = {
1523                 FREQ2FBIN(5180, 0),
1524                 FREQ2FBIN(5220, 0),
1525                 FREQ2FBIN(5320, 0),
1526                 FREQ2FBIN(5400, 0),
1527                 FREQ2FBIN(5500, 0),
1528                 FREQ2FBIN(5600, 0),
1529                 FREQ2FBIN(5700, 0),
1530                 FREQ2FBIN(5825, 0)
1531         },
1532         .calPierData5G = {
1533                 {
1534                         {0, 0, 0, 0, 0},
1535                         {0, 0, 0, 0, 0},
1536                         {0, 0, 0, 0, 0},
1537                         {0, 0, 0, 0, 0},
1538                         {0, 0, 0, 0, 0},
1539                         {0, 0, 0, 0, 0},
1540                         {0, 0, 0, 0, 0},
1541                         {0, 0, 0, 0, 0},
1542                 },
1543                 {
1544                         {0, 0, 0, 0, 0},
1545                         {0, 0, 0, 0, 0},
1546                         {0, 0, 0, 0, 0},
1547                         {0, 0, 0, 0, 0},
1548                         {0, 0, 0, 0, 0},
1549                         {0, 0, 0, 0, 0},
1550                         {0, 0, 0, 0, 0},
1551                         {0, 0, 0, 0, 0},
1552                 },
1553                 {
1554                         {0, 0, 0, 0, 0},
1555                         {0, 0, 0, 0, 0},
1556                         {0, 0, 0, 0, 0},
1557                         {0, 0, 0, 0, 0},
1558                         {0, 0, 0, 0, 0},
1559                         {0, 0, 0, 0, 0},
1560                         {0, 0, 0, 0, 0},
1561                         {0, 0, 0, 0, 0},
1562                 },
1563
1564         },
1565         .calTarget_freqbin_5G = {
1566                 FREQ2FBIN(5180, 0),
1567                 FREQ2FBIN(5240, 0),
1568                 FREQ2FBIN(5320, 0),
1569                 FREQ2FBIN(5400, 0),
1570                 FREQ2FBIN(5500, 0),
1571                 FREQ2FBIN(5600, 0),
1572                 FREQ2FBIN(5700, 0),
1573                 FREQ2FBIN(5825, 0)
1574         },
1575         .calTarget_freqbin_5GHT20 = {
1576                 FREQ2FBIN(5180, 0),
1577                 FREQ2FBIN(5240, 0),
1578                 FREQ2FBIN(5320, 0),
1579                 FREQ2FBIN(5400, 0),
1580                 FREQ2FBIN(5500, 0),
1581                 FREQ2FBIN(5700, 0),
1582                 FREQ2FBIN(5745, 0),
1583                 FREQ2FBIN(5825, 0)
1584         },
1585         .calTarget_freqbin_5GHT40 = {
1586                 FREQ2FBIN(5180, 0),
1587                 FREQ2FBIN(5240, 0),
1588                 FREQ2FBIN(5320, 0),
1589                 FREQ2FBIN(5400, 0),
1590                 FREQ2FBIN(5500, 0),
1591                 FREQ2FBIN(5700, 0),
1592                 FREQ2FBIN(5745, 0),
1593                 FREQ2FBIN(5825, 0)
1594         },
1595         .calTargetPower5G = {
1596                 /* 6-24,36,48,54 */
1597                 { {30, 30, 28, 24} },
1598                 { {30, 30, 28, 24} },
1599                 { {30, 30, 28, 24} },
1600                 { {30, 30, 28, 24} },
1601                 { {30, 30, 28, 24} },
1602                 { {30, 30, 28, 24} },
1603                 { {30, 30, 28, 24} },
1604                 { {30, 30, 28, 24} },
1605         },
1606         .calTargetPower5GHT20 = {
1607                 /*
1608                  * 0_8_16,1-3_9-11_17-19,
1609                  * 4,5,6,7,12,13,14,15,20,21,22,23
1610                  */
1611                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1612                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1613                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1614                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1615                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1616                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1617                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1618                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1619         },
1620         .calTargetPower5GHT40 =  {
1621                 /*
1622                  * 0_8_16,1-3_9-11_17-19,
1623                  * 4,5,6,7,12,13,14,15,20,21,22,23
1624                  */
1625                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1626                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1627                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1628                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1629                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1630                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1631                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1632                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1633         },
1634         .ctlIndex_5G =  {
1635                 0x10, 0x16, 0x18, 0x40, 0x46,
1636                 0x48, 0x30, 0x36, 0x38
1637         },
1638         .ctl_freqbin_5G =  {
1639                 {
1640                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1641                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1642                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1643                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1644                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1645                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1646                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1647                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1648                 },
1649                 {
1650                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1651                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1652                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1653                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1654                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1655                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1656                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1657                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1658                 },
1659
1660                 {
1661                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1662                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1663                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1664                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1665                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1666                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1667                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1668                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1669                 },
1670
1671                 {
1672                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1673                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1674                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1675                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1676                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1677                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1678                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1679                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1680                 },
1681
1682                 {
1683                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1684                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1685                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1686                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1687                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1688                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1689                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1690                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1691                 },
1692
1693                 {
1694                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1695                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1696                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1697                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1698                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1699                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1700                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1701                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1702                 },
1703
1704                 {
1705                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1706                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1707                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1708                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1709                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1710                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1711                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1712                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1713                 },
1714
1715                 {
1716                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1717                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1718                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1719                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1720                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1721                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1722                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1723                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1724                 },
1725
1726                 {
1727                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1728                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1729                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1730                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1731                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1732                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1733                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1734                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1735                 }
1736         },
1737         .ctlPowerData_5G = {
1738                 {
1739                         {
1740                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1741                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1742                         }
1743                 },
1744                 {
1745                         {
1746                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1747                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1748                         }
1749                 },
1750                 {
1751                         {
1752                                 {60, 0}, {60, 1}, {60, 0}, {60, 1},
1753                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1754                         }
1755                 },
1756                 {
1757                         {
1758                                 {60, 0}, {60, 1}, {60, 1}, {60, 0},
1759                                 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1760                         }
1761                 },
1762                 {
1763                         {
1764                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1765                                 {60, 0}, {60, 0}, {60, 0}, {60, 0},
1766                         }
1767                 },
1768                 {
1769                         {
1770                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1771                                 {60, 1}, {60, 0}, {60, 0}, {60, 0},
1772                         }
1773                 },
1774                 {
1775                         {
1776                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1777                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
1778                         }
1779                 },
1780                 {
1781                         {
1782                                 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1783                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
1784                         }
1785                 },
1786                 {
1787                         {
1788                                 {60, 1}, {60, 0}, {60, 1}, {60, 1},
1789                                 {60, 1}, {60, 1}, {60, 0}, {60, 1},
1790                         }
1791                 },
1792         }
1793 };
1794
1795
1796 static const struct ar9300_eeprom ar9300_x112 = {
1797         .eepromVersion = 2,
1798         .templateVersion = 5,
1799         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1800         .custData = {"x112-041-f0000"},
1801         .baseEepHeader = {
1802                 .regDmn = { LE16(0), LE16(0x1f) },
1803                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1804                 .opCapFlags = {
1805                         .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
1806                         .eepMisc = 0,
1807                 },
1808                 .rfSilent = 0,
1809                 .blueToothOptions = 0,
1810                 .deviceCap = 0,
1811                 .deviceType = 5, /* takes lower byte in eeprom location */
1812                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1813                 .params_for_tuning_caps = {0, 0},
1814                 .featureEnable = 0x0d,
1815                 /*
1816                  * bit0 - enable tx temp comp - disabled
1817                  * bit1 - enable tx volt comp - disabled
1818                  * bit2 - enable fastclock - enabled
1819                  * bit3 - enable doubling - enabled
1820                  * bit4 - enable internal regulator - disabled
1821                  * bit5 - enable pa predistortion - disabled
1822                  */
1823                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1824                 .eepromWriteEnableGpio = 6,
1825                 .wlanDisableGpio = 0,
1826                 .wlanLedGpio = 8,
1827                 .rxBandSelectGpio = 0xff,
1828                 .txrxgain = 0x0,
1829                 .swreg = 0,
1830         },
1831         .modalHeader2G = {
1832                 /* ar9300_modal_eep_header  2g */
1833                 /* 4 idle,t1,t2,b(4 bits per setting) */
1834                 .antCtrlCommon = LE32(0x110),
1835                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1836                 .antCtrlCommon2 = LE32(0x22222),
1837
1838                 /*
1839                  * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1840                  * rx1, rx12, b (2 bits each)
1841                  */
1842                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1843
1844                 /*
1845                  * xatten1DB[AR9300_max_chains];  3 xatten1_db
1846                  * for ar9280 (0xa20c/b20c 5:0)
1847                  */
1848                 .xatten1DB = {0x1b, 0x1b, 0x1b},
1849
1850                 /*
1851                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1852                  * for ar9280 (0xa20c/b20c 16:12
1853                  */
1854                 .xatten1Margin = {0x15, 0x15, 0x15},
1855                 .tempSlope = 50,
1856                 .voltSlope = 0,
1857
1858                 /*
1859                  * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1860                  * channels in usual fbin coding format
1861                  */
1862                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1863
1864                 /*
1865                  * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1866                  * if the register is per chain
1867                  */
1868                 .noiseFloorThreshCh = {-1, 0, 0},
1869                 .ob = {1, 1, 1},/* 3 chain */
1870                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
1871                 .db_stage3 = {0, 0, 0},
1872                 .db_stage4 = {0, 0, 0},
1873                 .xpaBiasLvl = 0,
1874                 .txFrameToDataStart = 0x0e,
1875                 .txFrameToPaOn = 0x0e,
1876                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1877                 .antennaGain = 0,
1878                 .switchSettling = 0x2c,
1879                 .adcDesiredSize = -30,
1880                 .txEndToXpaOff = 0,
1881                 .txEndToRxOn = 0x2,
1882                 .txFrameToXpaOn = 0xe,
1883                 .thresh62 = 28,
1884                 .papdRateMaskHt20 = LE32(0x0c80c080),
1885                 .papdRateMaskHt40 = LE32(0x0080c080),
1886                 .futureModal = {
1887                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
1888                 },
1889         },
1890         .base_ext1 = {
1891                 .ant_div_control = 0,
1892                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1893         },
1894         .calFreqPier2G = {
1895                 FREQ2FBIN(2412, 1),
1896                 FREQ2FBIN(2437, 1),
1897                 FREQ2FBIN(2472, 1),
1898         },
1899         /* ar9300_cal_data_per_freq_op_loop 2g */
1900         .calPierData2G = {
1901                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1902                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1903                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1904         },
1905         .calTarget_freqbin_Cck = {
1906                 FREQ2FBIN(2412, 1),
1907                 FREQ2FBIN(2472, 1),
1908         },
1909         .calTarget_freqbin_2G = {
1910                 FREQ2FBIN(2412, 1),
1911                 FREQ2FBIN(2437, 1),
1912                 FREQ2FBIN(2472, 1)
1913         },
1914         .calTarget_freqbin_2GHT20 = {
1915                 FREQ2FBIN(2412, 1),
1916                 FREQ2FBIN(2437, 1),
1917                 FREQ2FBIN(2472, 1)
1918         },
1919         .calTarget_freqbin_2GHT40 = {
1920                 FREQ2FBIN(2412, 1),
1921                 FREQ2FBIN(2437, 1),
1922                 FREQ2FBIN(2472, 1)
1923         },
1924         .calTargetPowerCck = {
1925                 /* 1L-5L,5S,11L,11s */
1926                 { {38, 38, 38, 38} },
1927                 { {38, 38, 38, 38} },
1928         },
1929         .calTargetPower2G = {
1930                 /* 6-24,36,48,54 */
1931                 { {38, 38, 36, 34} },
1932                 { {38, 38, 36, 34} },
1933                 { {38, 38, 34, 32} },
1934         },
1935         .calTargetPower2GHT20 = {
1936                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1937                 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1938                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1939         },
1940         .calTargetPower2GHT40 = {
1941                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1942                 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1943                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1944         },
1945         .ctlIndex_2G =  {
1946                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1947                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1948         },
1949         .ctl_freqbin_2G = {
1950                 {
1951                         FREQ2FBIN(2412, 1),
1952                         FREQ2FBIN(2417, 1),
1953                         FREQ2FBIN(2457, 1),
1954                         FREQ2FBIN(2462, 1)
1955                 },
1956                 {
1957                         FREQ2FBIN(2412, 1),
1958                         FREQ2FBIN(2417, 1),
1959                         FREQ2FBIN(2462, 1),
1960                         0xFF,
1961                 },
1962
1963                 {
1964                         FREQ2FBIN(2412, 1),
1965                         FREQ2FBIN(2417, 1),
1966                         FREQ2FBIN(2462, 1),
1967                         0xFF,
1968                 },
1969                 {
1970                         FREQ2FBIN(2422, 1),
1971                         FREQ2FBIN(2427, 1),
1972                         FREQ2FBIN(2447, 1),
1973                         FREQ2FBIN(2452, 1)
1974                 },
1975
1976                 {
1977                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1978                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1979                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1980                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1981                 },
1982
1983                 {
1984                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1985                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1986                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1987                         0,
1988                 },
1989
1990                 {
1991                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1992                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1993                         FREQ2FBIN(2472, 1),
1994                         0,
1995                 },
1996
1997                 {
1998                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1999                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2000                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2001                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2002                 },
2003
2004                 {
2005                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2006                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2007                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2008                 },
2009
2010                 {
2011                         /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2012                         /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2013                         /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2014                         0
2015                 },
2016
2017                 {
2018                         /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2019                         /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2020                         /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2021                         0
2022                 },
2023
2024                 {
2025                         /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2026                         /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2027                         /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2028                         /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2029                 }
2030         },
2031         .ctlPowerData_2G = {
2032                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2033                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2034                 { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2035
2036                 { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2037                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2038                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2039
2040                 { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2041                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2042                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2043
2044                 { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2045                 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2046                 { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2047         },
2048         .modalHeader5G = {
2049                 /* 4 idle,t1,t2,b (4 bits per setting) */
2050                 .antCtrlCommon = LE32(0x110),
2051                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2052                 .antCtrlCommon2 = LE32(0x22222),
2053                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2054                 .antCtrlChain = {
2055                         LE16(0x0), LE16(0x0), LE16(0x0),
2056                 },
2057                 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2058                 .xatten1DB = {0x13, 0x19, 0x17},
2059
2060                 /*
2061                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2062                  * for merlin (0xa20c/b20c 16:12
2063                  */
2064                 .xatten1Margin = {0x19, 0x19, 0x19},
2065                 .tempSlope = 70,
2066                 .voltSlope = 15,
2067                 /* spurChans spur channels in usual fbin coding format */
2068                 .spurChans = {0, 0, 0, 0, 0},
2069                 /* noiseFloorThreshch check if the register is per chain */
2070                 .noiseFloorThreshCh = {-1, 0, 0},
2071                 .ob = {3, 3, 3}, /* 3 chain */
2072                 .db_stage2 = {3, 3, 3}, /* 3 chain */
2073                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2074                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
2075                 .xpaBiasLvl = 0,
2076                 .txFrameToDataStart = 0x0e,
2077                 .txFrameToPaOn = 0x0e,
2078                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2079                 .antennaGain = 0,
2080                 .switchSettling = 0x2d,
2081                 .adcDesiredSize = -30,
2082                 .txEndToXpaOff = 0,
2083                 .txEndToRxOn = 0x2,
2084                 .txFrameToXpaOn = 0xe,
2085                 .thresh62 = 28,
2086                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2087                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2088                 .futureModal = {
2089                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2090                 },
2091         },
2092         .base_ext2 = {
2093                 .tempSlopeLow = 72,
2094                 .tempSlopeHigh = 105,
2095                 .xatten1DBLow = {0x10, 0x14, 0x10},
2096                 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2097                 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2098                 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2099         },
2100         .calFreqPier5G = {
2101                 FREQ2FBIN(5180, 0),
2102                 FREQ2FBIN(5220, 0),
2103                 FREQ2FBIN(5320, 0),
2104                 FREQ2FBIN(5400, 0),
2105                 FREQ2FBIN(5500, 0),
2106                 FREQ2FBIN(5600, 0),
2107                 FREQ2FBIN(5700, 0),
2108                 FREQ2FBIN(5785, 0)
2109         },
2110         .calPierData5G = {
2111                 {
2112                         {0, 0, 0, 0, 0},
2113                         {0, 0, 0, 0, 0},
2114                         {0, 0, 0, 0, 0},
2115                         {0, 0, 0, 0, 0},
2116                         {0, 0, 0, 0, 0},
2117                         {0, 0, 0, 0, 0},
2118                         {0, 0, 0, 0, 0},
2119                         {0, 0, 0, 0, 0},
2120                 },
2121                 {
2122                         {0, 0, 0, 0, 0},
2123                         {0, 0, 0, 0, 0},
2124                         {0, 0, 0, 0, 0},
2125                         {0, 0, 0, 0, 0},
2126                         {0, 0, 0, 0, 0},
2127                         {0, 0, 0, 0, 0},
2128                         {0, 0, 0, 0, 0},
2129                         {0, 0, 0, 0, 0},
2130                 },
2131                 {
2132                         {0, 0, 0, 0, 0},
2133                         {0, 0, 0, 0, 0},
2134                         {0, 0, 0, 0, 0},
2135                         {0, 0, 0, 0, 0},
2136                         {0, 0, 0, 0, 0},
2137                         {0, 0, 0, 0, 0},
2138                         {0, 0, 0, 0, 0},
2139                         {0, 0, 0, 0, 0},
2140                 },
2141
2142         },
2143         .calTarget_freqbin_5G = {
2144                 FREQ2FBIN(5180, 0),
2145                 FREQ2FBIN(5220, 0),
2146                 FREQ2FBIN(5320, 0),
2147                 FREQ2FBIN(5400, 0),
2148                 FREQ2FBIN(5500, 0),
2149                 FREQ2FBIN(5600, 0),
2150                 FREQ2FBIN(5725, 0),
2151                 FREQ2FBIN(5825, 0)
2152         },
2153         .calTarget_freqbin_5GHT20 = {
2154                 FREQ2FBIN(5180, 0),
2155                 FREQ2FBIN(5220, 0),
2156                 FREQ2FBIN(5320, 0),
2157                 FREQ2FBIN(5400, 0),
2158                 FREQ2FBIN(5500, 0),
2159                 FREQ2FBIN(5600, 0),
2160                 FREQ2FBIN(5725, 0),
2161                 FREQ2FBIN(5825, 0)
2162         },
2163         .calTarget_freqbin_5GHT40 = {
2164                 FREQ2FBIN(5180, 0),
2165                 FREQ2FBIN(5220, 0),
2166                 FREQ2FBIN(5320, 0),
2167                 FREQ2FBIN(5400, 0),
2168                 FREQ2FBIN(5500, 0),
2169                 FREQ2FBIN(5600, 0),
2170                 FREQ2FBIN(5725, 0),
2171                 FREQ2FBIN(5825, 0)
2172         },
2173         .calTargetPower5G = {
2174                 /* 6-24,36,48,54 */
2175                 { {32, 32, 28, 26} },
2176                 { {32, 32, 28, 26} },
2177                 { {32, 32, 28, 26} },
2178                 { {32, 32, 26, 24} },
2179                 { {32, 32, 26, 24} },
2180                 { {32, 32, 24, 22} },
2181                 { {30, 30, 24, 22} },
2182                 { {30, 30, 24, 22} },
2183         },
2184         .calTargetPower5GHT20 = {
2185                 /*
2186                  * 0_8_16,1-3_9-11_17-19,
2187                  * 4,5,6,7,12,13,14,15,20,21,22,23
2188                  */
2189                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2190                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2191                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2192                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2193                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2194                 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2195                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2196                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2197         },
2198         .calTargetPower5GHT40 =  {
2199                 /*
2200                  * 0_8_16,1-3_9-11_17-19,
2201                  * 4,5,6,7,12,13,14,15,20,21,22,23
2202                  */
2203                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2204                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2205                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2206                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2207                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2208                 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2209                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2210                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2211         },
2212         .ctlIndex_5G =  {
2213                 0x10, 0x16, 0x18, 0x40, 0x46,
2214                 0x48, 0x30, 0x36, 0x38
2215         },
2216         .ctl_freqbin_5G =  {
2217                 {
2218                         /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2219                         /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2220                         /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2221                         /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2222                         /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2223                         /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2224                         /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2225                         /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2226                 },
2227                 {
2228                         /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2229                         /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2230                         /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2231                         /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2232                         /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2233                         /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2234                         /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2235                         /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2236                 },
2237
2238                 {
2239                         /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2240                         /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2241                         /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2242                         /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2243                         /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2244                         /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2245                         /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2246                         /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2247                 },
2248
2249                 {
2250                         /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2251                         /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2252                         /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2253                         /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2254                         /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2255                         /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2256                         /* Data[3].ctledges[6].bchannel */ 0xFF,
2257                         /* Data[3].ctledges[7].bchannel */ 0xFF,
2258                 },
2259
2260                 {
2261                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2262                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2263                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2264                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2265                         /* Data[4].ctledges[4].bchannel */ 0xFF,
2266                         /* Data[4].ctledges[5].bchannel */ 0xFF,
2267                         /* Data[4].ctledges[6].bchannel */ 0xFF,
2268                         /* Data[4].ctledges[7].bchannel */ 0xFF,
2269                 },
2270
2271                 {
2272                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2273                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2274                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2275                         /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2276                         /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2277                         /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2278                         /* Data[5].ctledges[6].bchannel */ 0xFF,
2279                         /* Data[5].ctledges[7].bchannel */ 0xFF
2280                 },
2281
2282                 {
2283                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2284                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2285                         /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2286                         /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2287                         /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2288                         /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2289                         /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2290                         /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2291                 },
2292
2293                 {
2294                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2295                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2296                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2297                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2298                         /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2299                         /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2300                         /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2301                         /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2302                 },
2303
2304                 {
2305                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2306                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2307                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2308                         /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2309                         /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2310                         /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2311                         /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2312                         /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2313                 }
2314         },
2315         .ctlPowerData_5G = {
2316                 {
2317                         {
2318                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2319                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2320                         }
2321                 },
2322                 {
2323                         {
2324                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2325                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2326                         }
2327                 },
2328                 {
2329                         {
2330                                 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2331                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2332                         }
2333                 },
2334                 {
2335                         {
2336                                 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2337                                 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2338                         }
2339                 },
2340                 {
2341                         {
2342                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2343                                 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2344                         }
2345                 },
2346                 {
2347                         {
2348                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2349                                 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2350                         }
2351                 },
2352                 {
2353                         {
2354                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2355                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2356                         }
2357                 },
2358                 {
2359                         {
2360                                 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2361                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2362                         }
2363                 },
2364                 {
2365                         {
2366                                 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2367                                 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2368                         }
2369                 },
2370         }
2371 };
2372
2373 static const struct ar9300_eeprom ar9300_h116 = {
2374         .eepromVersion = 2,
2375         .templateVersion = 4,
2376         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2377         .custData = {"h116-041-f0000"},
2378         .baseEepHeader = {
2379                 .regDmn = { LE16(0), LE16(0x1f) },
2380                 .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
2381                 .opCapFlags = {
2382                         .opFlags = AR9300_OPFLAGS_11G | AR9300_OPFLAGS_11A,
2383                         .eepMisc = 0,
2384                 },
2385                 .rfSilent = 0,
2386                 .blueToothOptions = 0,
2387                 .deviceCap = 0,
2388                 .deviceType = 5, /* takes lower byte in eeprom location */
2389                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2390                 .params_for_tuning_caps = {0, 0},
2391                 .featureEnable = 0x0d,
2392                  /*
2393                   * bit0 - enable tx temp comp - disabled
2394                   * bit1 - enable tx volt comp - disabled
2395                   * bit2 - enable fastClock - enabled
2396                   * bit3 - enable doubling - enabled
2397                   * bit4 - enable internal regulator - disabled
2398                   * bit5 - enable pa predistortion - disabled
2399                   */
2400                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2401                 .eepromWriteEnableGpio = 6,
2402                 .wlanDisableGpio = 0,
2403                 .wlanLedGpio = 8,
2404                 .rxBandSelectGpio = 0xff,
2405                 .txrxgain = 0x10,
2406                 .swreg = 0,
2407          },
2408         .modalHeader2G = {
2409         /* ar9300_modal_eep_header  2g */
2410                 /* 4 idle,t1,t2,b(4 bits per setting) */
2411                 .antCtrlCommon = LE32(0x110),
2412                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2413                 .antCtrlCommon2 = LE32(0x44444),
2414
2415                 /*
2416                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2417                  * rx1, rx12, b (2 bits each)
2418                  */
2419                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2420
2421                 /*
2422                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
2423                  * for ar9280 (0xa20c/b20c 5:0)
2424                  */
2425                 .xatten1DB = {0x1f, 0x1f, 0x1f},
2426
2427                 /*
2428                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2429                  * for ar9280 (0xa20c/b20c 16:12
2430                  */
2431                 .xatten1Margin = {0x12, 0x12, 0x12},
2432                 .tempSlope = 25,
2433                 .voltSlope = 0,
2434
2435                 /*
2436                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2437                  * channels in usual fbin coding format
2438                  */
2439                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2440
2441                 /*
2442                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2443                  * if the register is per chain
2444                  */
2445                 .noiseFloorThreshCh = {-1, 0, 0},
2446                 .ob = {1, 1, 1},/* 3 chain */
2447                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
2448                 .db_stage3 = {0, 0, 0},
2449                 .db_stage4 = {0, 0, 0},
2450                 .xpaBiasLvl = 0,
2451                 .txFrameToDataStart = 0x0e,
2452                 .txFrameToPaOn = 0x0e,
2453                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2454                 .antennaGain = 0,
2455                 .switchSettling = 0x2c,
2456                 .adcDesiredSize = -30,
2457                 .txEndToXpaOff = 0,
2458                 .txEndToRxOn = 0x2,
2459                 .txFrameToXpaOn = 0xe,
2460                 .thresh62 = 28,
2461                 .papdRateMaskHt20 = LE32(0x0c80C080),
2462                 .papdRateMaskHt40 = LE32(0x0080C080),
2463                 .futureModal = {
2464                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2465                 },
2466          },
2467          .base_ext1 = {
2468                 .ant_div_control = 0,
2469                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2470          },
2471         .calFreqPier2G = {
2472                 FREQ2FBIN(2412, 1),
2473                 FREQ2FBIN(2437, 1),
2474                 FREQ2FBIN(2472, 1),
2475          },
2476         /* ar9300_cal_data_per_freq_op_loop 2g */
2477         .calPierData2G = {
2478                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2479                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2480                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2481          },
2482         .calTarget_freqbin_Cck = {
2483                 FREQ2FBIN(2412, 1),
2484                 FREQ2FBIN(2472, 1),
2485          },
2486         .calTarget_freqbin_2G = {
2487                 FREQ2FBIN(2412, 1),
2488                 FREQ2FBIN(2437, 1),
2489                 FREQ2FBIN(2472, 1)
2490          },
2491         .calTarget_freqbin_2GHT20 = {
2492                 FREQ2FBIN(2412, 1),
2493                 FREQ2FBIN(2437, 1),
2494                 FREQ2FBIN(2472, 1)
2495          },
2496         .calTarget_freqbin_2GHT40 = {
2497                 FREQ2FBIN(2412, 1),
2498                 FREQ2FBIN(2437, 1),
2499                 FREQ2FBIN(2472, 1)
2500          },
2501         .calTargetPowerCck = {
2502                  /* 1L-5L,5S,11L,11S */
2503                  { {34, 34, 34, 34} },
2504                  { {34, 34, 34, 34} },
2505         },
2506         .calTargetPower2G = {
2507                  /* 6-24,36,48,54 */
2508                  { {34, 34, 32, 32} },
2509                  { {34, 34, 32, 32} },
2510                  { {34, 34, 32, 32} },
2511         },
2512         .calTargetPower2GHT20 = {
2513                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2514                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2515                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2516         },
2517         .calTargetPower2GHT40 = {
2518                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2519                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2520                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2521         },
2522         .ctlIndex_2G =  {
2523                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2524                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2525         },
2526         .ctl_freqbin_2G = {
2527                 {
2528                         FREQ2FBIN(2412, 1),
2529                         FREQ2FBIN(2417, 1),
2530                         FREQ2FBIN(2457, 1),
2531                         FREQ2FBIN(2462, 1)
2532                 },
2533                 {
2534                         FREQ2FBIN(2412, 1),
2535                         FREQ2FBIN(2417, 1),
2536                         FREQ2FBIN(2462, 1),
2537                         0xFF,
2538                 },
2539
2540                 {
2541                         FREQ2FBIN(2412, 1),
2542                         FREQ2FBIN(2417, 1),
2543                         FREQ2FBIN(2462, 1),
2544                         0xFF,
2545                 },
2546                 {
2547                         FREQ2FBIN(2422, 1),
2548                         FREQ2FBIN(2427, 1),
2549                         FREQ2FBIN(2447, 1),
2550                         FREQ2FBIN(2452, 1)
2551                 },
2552
2553                 {
2554                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2555                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2556                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2557                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2558                 },
2559
2560                 {
2561                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2562                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2563                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2564                         0,
2565                 },
2566
2567                 {
2568                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2569                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2570                         FREQ2FBIN(2472, 1),
2571                         0,
2572                 },
2573
2574                 {
2575                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2576                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2577                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2578                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2579                 },
2580
2581                 {
2582                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2583                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2584                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2585                 },
2586
2587                 {
2588                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2589                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2590                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2591                         0
2592                 },
2593
2594                 {
2595                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2596                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2597                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2598                         0
2599                 },
2600
2601                 {
2602                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2603                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2604                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2605                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2606                 }
2607          },
2608         .ctlPowerData_2G = {
2609                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2610                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2611                  { { {60, 1}, {60, 0}, {60, 0}, {60, 1} } },
2612
2613                  { { {60, 1}, {60, 0}, {0, 0}, {0, 0} } },
2614                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2615                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2616
2617                  { { {60, 0}, {60, 1}, {60, 1}, {60, 0} } },
2618                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2619                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2620
2621                  { { {60, 0}, {60, 1}, {60, 0}, {60, 0} } },
2622                  { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2623                  { { {60, 0}, {60, 1}, {60, 1}, {60, 1} } },
2624          },
2625         .modalHeader5G = {
2626                 /* 4 idle,t1,t2,b (4 bits per setting) */
2627                 .antCtrlCommon = LE32(0x220),
2628                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2629                 .antCtrlCommon2 = LE32(0x44444),
2630                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2631                 .antCtrlChain = {
2632                         LE16(0x150), LE16(0x150), LE16(0x150),
2633                 },
2634                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2635                 .xatten1DB = {0x19, 0x19, 0x19},
2636
2637                 /*
2638                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2639                  * for merlin (0xa20c/b20c 16:12
2640                  */
2641                 .xatten1Margin = {0x14, 0x14, 0x14},
2642                 .tempSlope = 70,
2643                 .voltSlope = 0,
2644                 /* spurChans spur channels in usual fbin coding format */
2645                 .spurChans = {0, 0, 0, 0, 0},
2646                 /* noiseFloorThreshCh Check if the register is per chain */
2647                 .noiseFloorThreshCh = {-1, 0, 0},
2648                 .ob = {3, 3, 3}, /* 3 chain */
2649                 .db_stage2 = {3, 3, 3}, /* 3 chain */
2650                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2651                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
2652                 .xpaBiasLvl = 0,
2653                 .txFrameToDataStart = 0x0e,
2654                 .txFrameToPaOn = 0x0e,
2655                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2656                 .antennaGain = 0,
2657                 .switchSettling = 0x2d,
2658                 .adcDesiredSize = -30,
2659                 .txEndToXpaOff = 0,
2660                 .txEndToRxOn = 0x2,
2661                 .txFrameToXpaOn = 0xe,
2662                 .thresh62 = 28,
2663                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2664                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2665                 .futureModal = {
2666                         0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
2667                 },
2668          },
2669         .base_ext2 = {
2670                 .tempSlopeLow = 35,
2671                 .tempSlopeHigh = 50,
2672                 .xatten1DBLow = {0, 0, 0},
2673                 .xatten1MarginLow = {0, 0, 0},
2674                 .xatten1DBHigh = {0, 0, 0},
2675                 .xatten1MarginHigh = {0, 0, 0}
2676          },
2677         .calFreqPier5G = {
2678                 FREQ2FBIN(5180, 0),
2679                 FREQ2FBIN(5220, 0),
2680                 FREQ2FBIN(5320, 0),
2681                 FREQ2FBIN(5400, 0),
2682                 FREQ2FBIN(5500, 0),
2683                 FREQ2FBIN(5600, 0),
2684                 FREQ2FBIN(5700, 0),
2685                 FREQ2FBIN(5785, 0)
2686         },
2687         .calPierData5G = {
2688                         {
2689                                 {0, 0, 0, 0, 0},
2690                                 {0, 0, 0, 0, 0},
2691                                 {0, 0, 0, 0, 0},
2692                                 {0, 0, 0, 0, 0},
2693                                 {0, 0, 0, 0, 0},
2694                                 {0, 0, 0, 0, 0},
2695                                 {0, 0, 0, 0, 0},
2696                                 {0, 0, 0, 0, 0},
2697                         },
2698                         {
2699                                 {0, 0, 0, 0, 0},
2700                                 {0, 0, 0, 0, 0},
2701                                 {0, 0, 0, 0, 0},
2702                                 {0, 0, 0, 0, 0},
2703                                 {0, 0, 0, 0, 0},
2704                                 {0, 0, 0, 0, 0},
2705                                 {0, 0, 0, 0, 0},
2706                                 {0, 0, 0, 0, 0},
2707                         },
2708                         {
2709                                 {0, 0, 0, 0, 0},
2710                                 {0, 0, 0, 0, 0},
2711                                 {0, 0, 0, 0, 0},
2712                                 {0, 0, 0, 0, 0},
2713                                 {0, 0, 0, 0, 0},
2714                                 {0, 0, 0, 0, 0},
2715                                 {0, 0, 0, 0, 0},
2716                                 {0, 0, 0, 0, 0},
2717                         },
2718
2719         },
2720         .calTarget_freqbin_5G = {
2721                 FREQ2FBIN(5180, 0),
2722                 FREQ2FBIN(5240, 0),
2723                 FREQ2FBIN(5320, 0),
2724                 FREQ2FBIN(5400, 0),
2725                 FREQ2FBIN(5500, 0),
2726                 FREQ2FBIN(5600, 0),
2727                 FREQ2FBIN(5700, 0),
2728                 FREQ2FBIN(5825, 0)
2729         },
2730         .calTarget_freqbin_5GHT20 = {
2731                 FREQ2FBIN(5180, 0),
2732                 FREQ2FBIN(5240, 0),
2733                 FREQ2FBIN(5320, 0),
2734                 FREQ2FBIN(5400, 0),
2735                 FREQ2FBIN(5500, 0),
2736                 FREQ2FBIN(5700, 0),
2737                 FREQ2FBIN(5745, 0),
2738                 FREQ2FBIN(5825, 0)
2739         },
2740         .calTarget_freqbin_5GHT40 = {
2741                 FREQ2FBIN(5180, 0),
2742                 FREQ2FBIN(5240, 0),
2743                 FREQ2FBIN(5320, 0),
2744                 FREQ2FBIN(5400, 0),
2745                 FREQ2FBIN(5500, 0),
2746                 FREQ2FBIN(5700, 0),
2747                 FREQ2FBIN(5745, 0),
2748                 FREQ2FBIN(5825, 0)
2749          },
2750         .calTargetPower5G = {
2751                 /* 6-24,36,48,54 */
2752                 { {30, 30, 28, 24} },
2753                 { {30, 30, 28, 24} },
2754                 { {30, 30, 28, 24} },
2755                 { {30, 30, 28, 24} },
2756                 { {30, 30, 28, 24} },
2757                 { {30, 30, 28, 24} },
2758                 { {30, 30, 28, 24} },
2759                 { {30, 30, 28, 24} },
2760          },
2761         .calTargetPower5GHT20 = {
2762                 /*
2763                  * 0_8_16,1-3_9-11_17-19,
2764                  * 4,5,6,7,12,13,14,15,20,21,22,23
2765                  */
2766                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2767                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2768                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2769                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2770                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2771                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2772                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2773                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2774          },
2775         .calTargetPower5GHT40 =  {
2776                 /*
2777                  * 0_8_16,1-3_9-11_17-19,
2778                  * 4,5,6,7,12,13,14,15,20,21,22,23
2779                  */
2780                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2781                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2782                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2783                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2784                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2785                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2786                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2787                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2788          },
2789         .ctlIndex_5G =  {
2790                 0x10, 0x16, 0x18, 0x40, 0x46,
2791                 0x48, 0x30, 0x36, 0x38
2792         },
2793         .ctl_freqbin_5G =  {
2794                 {
2795                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2796                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2797                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2798                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2799                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2800                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2801                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2802                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2803                 },
2804                 {
2805                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2806                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2807                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2808                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2809                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2810                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2811                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2812                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2813                 },
2814
2815                 {
2816                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2817                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2818                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2819                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2820                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2821                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2822                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2823                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2824                 },
2825
2826                 {
2827                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2828                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2829                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2830                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2831                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2832                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2833                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2834                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2835                 },
2836
2837                 {
2838                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2839                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2840                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2841                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2842                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2843                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2844                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2845                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2846                 },
2847
2848                 {
2849                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2850                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2851                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2852                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2853                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2854                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2855                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2856                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
2857                 },
2858
2859                 {
2860                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2861                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2862                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2863                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2864                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2865                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2866                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2867                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2868                 },
2869
2870                 {
2871                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2872                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2873                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2874                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2875                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2876                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2877                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2878                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2879                 },
2880
2881                 {
2882                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2883                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2884                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2885                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2886                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2887                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2888                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2889                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2890                 }
2891          },
2892         .ctlPowerData_5G = {
2893                 {
2894                         {
2895                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2896                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2897                         }
2898                 },
2899                 {
2900                         {
2901                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2902                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2903                         }
2904                 },
2905                 {
2906                         {
2907                                 {60, 0}, {60, 1}, {60, 0}, {60, 1},
2908                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2909                         }
2910                 },
2911                 {
2912                         {
2913                                 {60, 0}, {60, 1}, {60, 1}, {60, 0},
2914                                 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2915                         }
2916                 },
2917                 {
2918                         {
2919                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2920                                 {60, 0}, {60, 0}, {60, 0}, {60, 0},
2921                         }
2922                 },
2923                 {
2924                         {
2925                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2926                                 {60, 1}, {60, 0}, {60, 0}, {60, 0},
2927                         }
2928                 },
2929                 {
2930                         {
2931                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2932                                 {60, 1}, {60, 1}, {60, 1}, {60, 1},
2933                         }
2934                 },
2935                 {
2936                         {
2937                                 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2938                                 {60, 1}, {60, 1}, {60, 1}, {60, 0},
2939                         }
2940                 },
2941                 {
2942                         {
2943                                 {60, 1}, {60, 0}, {60, 1}, {60, 1},
2944                                 {60, 1}, {60, 1}, {60, 0}, {60, 1},
2945                         }
2946                 },
2947          }
2948 };
2949
2950
2951 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2952         &ar9300_default,
2953         &ar9300_x112,
2954         &ar9300_h116,
2955         &ar9300_h112,
2956         &ar9300_x113,
2957 };
2958
2959 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2960 {
2961 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2962         int it;
2963
2964         for (it = 0; it < N_LOOP; it++)
2965                 if (ar9300_eep_templates[it]->templateVersion == id)
2966                         return ar9300_eep_templates[it];
2967         return NULL;
2968 #undef N_LOOP
2969 }
2970
2971
2972 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2973 {
2974         if (fbin == AR9300_BCHAN_UNUSED)
2975                 return fbin;
2976
2977         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2978 }
2979
2980 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2981 {
2982         return 0;
2983 }
2984
2985 static int interpolate(int x, int xa, int xb, int ya, int yb)
2986 {
2987         int bf, factor, plus;
2988
2989         bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2990         factor = bf / 2;
2991         plus = bf % 2;
2992         return ya + factor + plus;
2993 }
2994
2995 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2996                                       enum eeprom_param param)
2997 {
2998         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2999         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3000
3001         switch (param) {
3002         case EEP_MAC_LSW:
3003                 return eep->macAddr[0] << 8 | eep->macAddr[1];
3004         case EEP_MAC_MID:
3005                 return eep->macAddr[2] << 8 | eep->macAddr[3];
3006         case EEP_MAC_MSW:
3007                 return eep->macAddr[4] << 8 | eep->macAddr[5];
3008         case EEP_REG_0:
3009                 return le16_to_cpu(pBase->regDmn[0]);
3010         case EEP_REG_1:
3011                 return le16_to_cpu(pBase->regDmn[1]);
3012         case EEP_OP_CAP:
3013                 return pBase->deviceCap;
3014         case EEP_OP_MODE:
3015                 return pBase->opCapFlags.opFlags;
3016         case EEP_RF_SILENT:
3017                 return pBase->rfSilent;
3018         case EEP_TX_MASK:
3019                 return (pBase->txrxMask >> 4) & 0xf;
3020         case EEP_RX_MASK:
3021                 return pBase->txrxMask & 0xf;
3022         case EEP_DRIVE_STRENGTH:
3023 #define AR9300_EEP_BASE_DRIV_STRENGTH   0x1
3024                 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3025         case EEP_INTERNAL_REGULATOR:
3026                 /* Bit 4 is internal regulator flag */
3027                 return (pBase->featureEnable & 0x10) >> 4;
3028         case EEP_SWREG:
3029                 return le32_to_cpu(pBase->swreg);
3030         case EEP_PAPRD:
3031                 return !!(pBase->featureEnable & BIT(5));
3032         default:
3033                 return 0;
3034         }
3035 }
3036
3037 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3038                                     u8 *buffer)
3039 {
3040         u16 val;
3041
3042         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3043                 return false;
3044
3045         *buffer = (val >> (8 * (address % 2))) & 0xff;
3046         return true;
3047 }
3048
3049 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3050                                     u8 *buffer)
3051 {
3052         u16 val;
3053
3054         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3055                 return false;
3056
3057         buffer[0] = val >> 8;
3058         buffer[1] = val & 0xff;
3059
3060         return true;
3061 }
3062
3063 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3064                                int count)
3065 {
3066         struct ath_common *common = ath9k_hw_common(ah);
3067         int i;
3068
3069         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3070                 ath_print(common, ATH_DBG_EEPROM,
3071                           "eeprom address not in range\n");
3072                 return false;
3073         }
3074
3075         /*
3076          * Since we're reading the bytes in reverse order from a little-endian
3077          * word stream, an even address means we only use the lower half of
3078          * the 16-bit word at that address
3079          */
3080         if (address % 2 == 0) {
3081                 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3082                         goto error;
3083
3084                 count--;
3085         }
3086
3087         for (i = 0; i < count / 2; i++) {
3088                 if (!ar9300_eeprom_read_word(common, address, buffer))
3089                         goto error;
3090
3091                 address -= 2;
3092                 buffer += 2;
3093         }
3094
3095         if (count % 2)
3096                 if (!ar9300_eeprom_read_byte(common, address, buffer))
3097                         goto error;
3098
3099         return true;
3100
3101 error:
3102         ath_print(common, ATH_DBG_EEPROM,
3103                   "unable to read eeprom region at offset %d\n", address);
3104         return false;
3105 }
3106
3107 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3108 {
3109         REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3110
3111         if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3112                            AR9300_OTP_STATUS_VALID, 1000))
3113                 return false;
3114
3115         *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3116         return true;
3117 }
3118
3119 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3120                             int count)
3121 {
3122         u32 data;
3123         int i;
3124
3125         for (i = 0; i < count; i++) {
3126                 int offset = 8 * ((address - i) % 4);
3127                 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3128                         return false;
3129
3130                 buffer[i] = (data >> offset) & 0xff;
3131         }
3132
3133         return true;
3134 }
3135
3136
3137 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3138                                    int *length, int *major, int *minor)
3139 {
3140         unsigned long value[4];
3141
3142         value[0] = best[0];
3143         value[1] = best[1];
3144         value[2] = best[2];
3145         value[3] = best[3];
3146         *code = ((value[0] >> 5) & 0x0007);
3147         *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3148         *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3149         *major = (value[2] & 0x000f);
3150         *minor = (value[3] & 0x00ff);
3151 }
3152
3153 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3154 {
3155         int it, checksum = 0;
3156
3157         for (it = 0; it < dsize; it++) {
3158                 checksum += data[it];
3159                 checksum &= 0xffff;
3160         }
3161
3162         return checksum;
3163 }
3164
3165 static bool ar9300_uncompress_block(struct ath_hw *ah,
3166                                     u8 *mptr,
3167                                     int mdataSize,
3168                                     u8 *block,
3169                                     int size)
3170 {
3171         int it;
3172         int spot;
3173         int offset;
3174         int length;
3175         struct ath_common *common = ath9k_hw_common(ah);
3176
3177         spot = 0;
3178
3179         for (it = 0; it < size; it += (length+2)) {
3180                 offset = block[it];
3181                 offset &= 0xff;
3182                 spot += offset;
3183                 length = block[it+1];
3184                 length &= 0xff;
3185
3186                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3187                         ath_print(common, ATH_DBG_EEPROM,
3188                                   "Restore at %d: spot=%d "
3189                                   "offset=%d length=%d\n",
3190                                    it, spot, offset, length);
3191                         memcpy(&mptr[spot], &block[it+2], length);
3192                         spot += length;
3193                 } else if (length > 0) {
3194                         ath_print(common, ATH_DBG_EEPROM,
3195                                   "Bad restore at %d: spot=%d "
3196                                   "offset=%d length=%d\n",
3197                                   it, spot, offset, length);
3198                         return false;
3199                 }
3200         }
3201         return true;
3202 }
3203
3204 static int ar9300_compress_decision(struct ath_hw *ah,
3205                                     int it,
3206                                     int code,
3207                                     int reference,
3208                                     u8 *mptr,
3209                                     u8 *word, int length, int mdata_size)
3210 {
3211         struct ath_common *common = ath9k_hw_common(ah);
3212         u8 *dptr;
3213         const struct ar9300_eeprom *eep = NULL;
3214
3215         switch (code) {
3216         case _CompressNone:
3217                 if (length != mdata_size) {
3218                         ath_print(common, ATH_DBG_EEPROM,
3219                                   "EEPROM structure size mismatch"
3220                                   "memory=%d eeprom=%d\n", mdata_size, length);
3221                         return -1;
3222                 }
3223                 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3224                 ath_print(common, ATH_DBG_EEPROM, "restored eeprom %d:"
3225                           " uncompressed, length %d\n", it, length);
3226                 break;
3227         case _CompressBlock:
3228                 if (reference == 0) {
3229                         dptr = mptr;
3230                 } else {
3231                         eep = ar9003_eeprom_struct_find_by_id(reference);
3232                         if (eep == NULL) {
3233                                 ath_print(common, ATH_DBG_EEPROM,
3234                                           "cant find reference eeprom"
3235                                           "struct %d\n", reference);
3236                                 return -1;
3237                         }
3238                         memcpy(mptr, eep, mdata_size);
3239                 }
3240                 ath_print(common, ATH_DBG_EEPROM,
3241                           "restore eeprom %d: block, reference %d,"
3242                           " length %d\n", it, reference, length);
3243                 ar9300_uncompress_block(ah, mptr, mdata_size,
3244                                         (u8 *) (word + COMP_HDR_LEN), length);
3245                 break;
3246         default:
3247                 ath_print(common, ATH_DBG_EEPROM, "unknown compression"
3248                           " code %d\n", code);
3249                 return -1;
3250         }
3251         return 0;
3252 }
3253
3254 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3255                                int count);
3256
3257 static bool ar9300_check_header(void *data)
3258 {
3259         u32 *word = data;
3260         return !(*word == 0 || *word == ~0);
3261 }
3262
3263 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3264                                        int base_addr)
3265 {
3266         u8 header[4];
3267
3268         if (!read(ah, base_addr, header, 4))
3269                 return false;
3270
3271         return ar9300_check_header(header);
3272 }
3273
3274 /*
3275  * Read the configuration data from the eeprom.
3276  * The data can be put in any specified memory buffer.
3277  *
3278  * Returns -1 on error.
3279  * Returns address of next memory location on success.
3280  */
3281 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3282                                           u8 *mptr, int mdata_size)
3283 {
3284 #define MDEFAULT 15
3285 #define MSTATE 100
3286         int cptr;
3287         u8 *word;
3288         int code;
3289         int reference, length, major, minor;
3290         int osize;
3291         int it;
3292         u16 checksum, mchecksum;
3293         struct ath_common *common = ath9k_hw_common(ah);
3294         eeprom_read_op read;
3295
3296         word = kzalloc(2048, GFP_KERNEL);
3297         if (!word)
3298                 return -1;
3299
3300         memcpy(mptr, &ar9300_default, mdata_size);
3301
3302         read = ar9300_read_eeprom;
3303         cptr = AR9300_BASE_ADDR;
3304         ath_print(common, ATH_DBG_EEPROM,
3305                 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3306         if (ar9300_check_eeprom_header(ah, read, cptr))
3307                 goto found;
3308
3309         cptr = AR9300_BASE_ADDR_512;
3310         ath_print(common, ATH_DBG_EEPROM,
3311                 "Trying EEPROM accesss at Address 0x%04x\n", cptr);
3312         if (ar9300_check_eeprom_header(ah, read, cptr))
3313                 goto found;
3314
3315         read = ar9300_read_otp;
3316         cptr = AR9300_BASE_ADDR;
3317         ath_print(common, ATH_DBG_EEPROM,
3318                 "Trying OTP accesss at Address 0x%04x\n", cptr);
3319         if (ar9300_check_eeprom_header(ah, read, cptr))
3320                 goto found;
3321
3322         cptr = AR9300_BASE_ADDR_512;
3323         ath_print(common, ATH_DBG_EEPROM,
3324                 "Trying OTP accesss at Address 0x%04x\n", cptr);
3325         if (ar9300_check_eeprom_header(ah, read, cptr))
3326                 goto found;
3327
3328         goto fail;
3329
3330 found:
3331         ath_print(common, ATH_DBG_EEPROM, "Found valid EEPROM data");
3332
3333         for (it = 0; it < MSTATE; it++) {
3334                 if (!read(ah, cptr, word, COMP_HDR_LEN))
3335                         goto fail;
3336
3337                 if (!ar9300_check_header(word))
3338                         break;
3339
3340                 ar9300_comp_hdr_unpack(word, &code, &reference,
3341                                        &length, &major, &minor);
3342                 ath_print(common, ATH_DBG_EEPROM,
3343                           "Found block at %x: code=%d ref=%d"
3344                           "length=%d major=%d minor=%d\n", cptr, code,
3345                           reference, length, major, minor);
3346                 if (length >= 1024) {
3347                         ath_print(common, ATH_DBG_EEPROM,
3348                                   "Skipping bad header\n");
3349                         cptr -= COMP_HDR_LEN;
3350                         continue;
3351                 }
3352
3353                 osize = length;
3354                 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3355                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3356                 mchecksum = word[COMP_HDR_LEN + osize] |
3357                     (word[COMP_HDR_LEN + osize + 1] << 8);
3358                 ath_print(common, ATH_DBG_EEPROM,
3359                           "checksum %x %x\n", checksum, mchecksum);
3360                 if (checksum == mchecksum) {
3361                         ar9300_compress_decision(ah, it, code, reference, mptr,
3362                                                  word, length, mdata_size);
3363                 } else {
3364                         ath_print(common, ATH_DBG_EEPROM,
3365                                   "skipping block with bad checksum\n");
3366                 }
3367                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3368         }
3369
3370         kfree(word);
3371         return cptr;
3372
3373 fail:
3374         kfree(word);
3375         return -1;
3376 }
3377
3378 /*
3379  * Restore the configuration structure by reading the eeprom.
3380  * This function destroys any existing in-memory structure
3381  * content.
3382  */
3383 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3384 {
3385         u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3386
3387         if (ar9300_eeprom_restore_internal(ah, mptr,
3388                         sizeof(struct ar9300_eeprom)) < 0)
3389                 return false;
3390
3391         return true;
3392 }
3393
3394 /* XXX: review hardware docs */
3395 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3396 {
3397         return ah->eeprom.ar9300_eep.eepromVersion;
3398 }
3399
3400 /* XXX: could be read from the eepromVersion, not sure yet */
3401 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3402 {
3403         return 0;
3404 }
3405
3406 static u8 ath9k_hw_ar9300_get_num_ant_config(struct ath_hw *ah,
3407                                              enum ath9k_hal_freq_band freq_band)
3408 {
3409         return 1;
3410 }
3411
3412 static u32 ath9k_hw_ar9300_get_eeprom_antenna_cfg(struct ath_hw *ah,
3413                                                   struct ath9k_channel *chan)
3414 {
3415         return -EINVAL;
3416 }
3417
3418 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3419 {
3420         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3421
3422         if (is2ghz)
3423                 return eep->modalHeader2G.xpaBiasLvl;
3424         else
3425                 return eep->modalHeader5G.xpaBiasLvl;
3426 }
3427
3428 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3429 {
3430         int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3431         REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3432         REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPABIASLVL_MSB, bias >> 2);
3433         REG_RMW_FIELD(ah, AR_CH0_THERM, AR_CH0_THERM_XPASHORT2GND, 1);
3434 }
3435
3436 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3437 {
3438         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3439         __le32 val;
3440
3441         if (is2ghz)
3442                 val = eep->modalHeader2G.antCtrlCommon;
3443         else
3444                 val = eep->modalHeader5G.antCtrlCommon;
3445         return le32_to_cpu(val);
3446 }
3447
3448 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3449 {
3450         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3451         __le32 val;
3452
3453         if (is2ghz)
3454                 val = eep->modalHeader2G.antCtrlCommon2;
3455         else
3456                 val = eep->modalHeader5G.antCtrlCommon2;
3457         return le32_to_cpu(val);
3458 }
3459
3460 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3461                                         int chain,
3462                                         bool is2ghz)
3463 {
3464         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3465         __le16 val = 0;
3466
3467         if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3468                 if (is2ghz)
3469                         val = eep->modalHeader2G.antCtrlChain[chain];
3470                 else
3471                         val = eep->modalHeader5G.antCtrlChain[chain];
3472         }
3473
3474         return le16_to_cpu(val);
3475 }
3476
3477 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3478 {
3479         u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3480         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM, AR_SWITCH_TABLE_COM_ALL, value);
3481
3482         value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3483         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3484
3485         value = ar9003_hw_ant_ctrl_chain_get(ah, 0, is2ghz);
3486         REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_0, AR_SWITCH_TABLE_ALL, value);
3487
3488         value = ar9003_hw_ant_ctrl_chain_get(ah, 1, is2ghz);
3489         REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_1, AR_SWITCH_TABLE_ALL, value);
3490
3491         value = ar9003_hw_ant_ctrl_chain_get(ah, 2, is2ghz);
3492         REG_RMW_FIELD(ah, AR_PHY_SWITCH_CHAIN_2, AR_SWITCH_TABLE_ALL, value);
3493 }
3494
3495 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3496 {
3497         int drive_strength;
3498         unsigned long reg;
3499
3500         drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3501
3502         if (!drive_strength)
3503                 return;
3504
3505         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3506         reg &= ~0x00ffffc0;
3507         reg |= 0x5 << 21;
3508         reg |= 0x5 << 18;
3509         reg |= 0x5 << 15;
3510         reg |= 0x5 << 12;
3511         reg |= 0x5 << 9;
3512         reg |= 0x5 << 6;
3513         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3514
3515         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3516         reg &= ~0xffffffe0;
3517         reg |= 0x5 << 29;
3518         reg |= 0x5 << 26;
3519         reg |= 0x5 << 23;
3520         reg |= 0x5 << 20;
3521         reg |= 0x5 << 17;
3522         reg |= 0x5 << 14;
3523         reg |= 0x5 << 11;
3524         reg |= 0x5 << 8;
3525         reg |= 0x5 << 5;
3526         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3527
3528         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3529         reg &= ~0xff800000;
3530         reg |= 0x5 << 29;
3531         reg |= 0x5 << 26;
3532         reg |= 0x5 << 23;
3533         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3534 }
3535
3536 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3537                                      struct ath9k_channel *chan)
3538 {
3539         int f[3], t[3];
3540         u16 value;
3541         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3542
3543         if (chain >= 0 && chain < 3) {
3544                 if (IS_CHAN_2GHZ(chan))
3545                         return eep->modalHeader2G.xatten1DB[chain];
3546                 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3547                         t[0] = eep->base_ext2.xatten1DBLow[chain];
3548                         f[0] = 5180;
3549                         t[1] = eep->modalHeader5G.xatten1DB[chain];
3550                         f[1] = 5500;
3551                         t[2] = eep->base_ext2.xatten1DBHigh[chain];
3552                         f[2] = 5785;
3553                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3554                                                             f, t, 3);
3555                         return value;
3556                 } else
3557                         return eep->modalHeader5G.xatten1DB[chain];
3558         }
3559
3560         return 0;
3561 }
3562
3563
3564 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3565                                             struct ath9k_channel *chan)
3566 {
3567         int f[3], t[3];
3568         u16 value;
3569         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3570
3571         if (chain >= 0 && chain < 3) {
3572                 if (IS_CHAN_2GHZ(chan))
3573                         return eep->modalHeader2G.xatten1Margin[chain];
3574                 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3575                         t[0] = eep->base_ext2.xatten1MarginLow[chain];
3576                         f[0] = 5180;
3577                         t[1] = eep->modalHeader5G.xatten1Margin[chain];
3578                         f[1] = 5500;
3579                         t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3580                         f[2] = 5785;
3581                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3582                                                             f, t, 3);
3583                         return value;
3584                 } else
3585                         return eep->modalHeader5G.xatten1Margin[chain];
3586         }
3587
3588         return 0;
3589 }
3590
3591 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3592 {
3593         int i;
3594         u16 value;
3595         unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3596                                           AR_PHY_EXT_ATTEN_CTL_1,
3597                                           AR_PHY_EXT_ATTEN_CTL_2,
3598                                          };
3599
3600         /* Test value. if 0 then attenuation is unused. Don't load anything. */
3601         for (i = 0; i < 3; i++) {
3602                 value = ar9003_hw_atten_chain_get(ah, i, chan);
3603                 REG_RMW_FIELD(ah, ext_atten_reg[i],
3604                               AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3605
3606                 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3607                 REG_RMW_FIELD(ah, ext_atten_reg[i],
3608                               AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN, value);
3609         }
3610 }
3611
3612 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3613 {
3614         int internal_regulator =
3615                 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3616
3617         if (internal_regulator) {
3618                 /* Internal regulator is ON. Write swreg register. */
3619                 int swreg = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3620                 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3621                 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3622                          (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3623                 REG_WRITE(ah, AR_RTC_REG_CONTROL0, swreg);
3624                 /* Set REG_CONTROL1.SWREG_PROGRAM */
3625                 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3626                           REG_READ(ah,
3627                                    AR_RTC_REG_CONTROL1) |
3628                                    AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3629         } else {
3630                 REG_WRITE(ah, AR_RTC_SLEEP_CLK,
3631                           (REG_READ(ah,
3632                                     AR_RTC_SLEEP_CLK) |
3633                                     AR_RTC_FORCE_SWREG_PRD));
3634         }
3635 }
3636
3637 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3638                                              struct ath9k_channel *chan)
3639 {
3640         ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3641         ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3642         ar9003_hw_drive_strength_apply(ah);
3643         ar9003_hw_atten_apply(ah, chan);
3644         ar9003_hw_internal_regulator_apply(ah);
3645 }
3646
3647 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3648                                       struct ath9k_channel *chan)
3649 {
3650 }
3651
3652 /*
3653  * Returns the interpolated y value corresponding to the specified x value
3654  * from the np ordered pairs of data (px,py).
3655  * The pairs do not have to be in any order.
3656  * If the specified x value is less than any of the px,
3657  * the returned y value is equal to the py for the lowest px.
3658  * If the specified x value is greater than any of the px,
3659  * the returned y value is equal to the py for the highest px.
3660  */
3661 static int ar9003_hw_power_interpolate(int32_t x,
3662                                        int32_t *px, int32_t *py, u_int16_t np)
3663 {
3664         int ip = 0;
3665         int lx = 0, ly = 0, lhave = 0;
3666         int hx = 0, hy = 0, hhave = 0;
3667         int dx = 0;
3668         int y = 0;
3669
3670         lhave = 0;
3671         hhave = 0;
3672
3673         /* identify best lower and higher x calibration measurement */
3674         for (ip = 0; ip < np; ip++) {
3675                 dx = x - px[ip];
3676
3677                 /* this measurement is higher than our desired x */
3678                 if (dx <= 0) {
3679                         if (!hhave || dx > (x - hx)) {
3680                                 /* new best higher x measurement */
3681                                 hx = px[ip];
3682                                 hy = py[ip];
3683                                 hhave = 1;
3684                         }
3685                 }
3686                 /* this measurement is lower than our desired x */
3687                 if (dx >= 0) {
3688                         if (!lhave || dx < (x - lx)) {
3689                                 /* new best lower x measurement */
3690                                 lx = px[ip];
3691                                 ly = py[ip];
3692                                 lhave = 1;
3693                         }
3694                 }
3695         }
3696
3697         /* the low x is good */
3698         if (lhave) {
3699                 /* so is the high x */
3700                 if (hhave) {
3701                         /* they're the same, so just pick one */
3702                         if (hx == lx)
3703                                 y = ly;
3704                         else    /* interpolate  */
3705                                 y = interpolate(x, lx, hx, ly, hy);
3706                 } else          /* only low is good, use it */
3707                         y = ly;
3708         } else if (hhave)       /* only high is good, use it */
3709                 y = hy;
3710         else /* nothing is good,this should never happen unless np=0, ???? */
3711                 y = -(1 << 30);
3712         return y;
3713 }
3714
3715 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
3716                                        u16 rateIndex, u16 freq, bool is2GHz)
3717 {
3718         u16 numPiers, i;
3719         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3720         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3721         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3722         struct cal_tgt_pow_legacy *pEepromTargetPwr;
3723         u8 *pFreqBin;
3724
3725         if (is2GHz) {
3726                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3727                 pEepromTargetPwr = eep->calTargetPower2G;
3728                 pFreqBin = eep->calTarget_freqbin_2G;
3729         } else {
3730                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3731                 pEepromTargetPwr = eep->calTargetPower5G;
3732                 pFreqBin = eep->calTarget_freqbin_5G;
3733         }
3734
3735         /*
3736          * create array of channels and targetpower from
3737          * targetpower piers stored on eeprom
3738          */
3739         for (i = 0; i < numPiers; i++) {
3740                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3741                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3742         }
3743
3744         /* interpolate to get target power for given frequency */
3745         return (u8) ar9003_hw_power_interpolate((s32) freq,
3746                                                  freqArray,
3747                                                  targetPowerArray, numPiers);
3748 }
3749
3750 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
3751                                             u16 rateIndex,
3752                                             u16 freq, bool is2GHz)
3753 {
3754         u16 numPiers, i;
3755         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
3756         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
3757         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3758         struct cal_tgt_pow_ht *pEepromTargetPwr;
3759         u8 *pFreqBin;
3760
3761         if (is2GHz) {
3762                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
3763                 pEepromTargetPwr = eep->calTargetPower2GHT20;
3764                 pFreqBin = eep->calTarget_freqbin_2GHT20;
3765         } else {
3766                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
3767                 pEepromTargetPwr = eep->calTargetPower5GHT20;
3768                 pFreqBin = eep->calTarget_freqbin_5GHT20;
3769         }
3770
3771         /*
3772          * create array of channels and targetpower
3773          * from targetpower piers stored on eeprom
3774          */
3775         for (i = 0; i < numPiers; i++) {
3776                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3777                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3778         }
3779
3780         /* interpolate to get target power for given frequency */
3781         return (u8) ar9003_hw_power_interpolate((s32) freq,
3782                                                  freqArray,
3783                                                  targetPowerArray, numPiers);
3784 }
3785
3786 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
3787                                             u16 rateIndex,
3788                                             u16 freq, bool is2GHz)
3789 {
3790         u16 numPiers, i;
3791         s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
3792         s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
3793         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3794         struct cal_tgt_pow_ht *pEepromTargetPwr;
3795         u8 *pFreqBin;
3796
3797         if (is2GHz) {
3798                 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
3799                 pEepromTargetPwr = eep->calTargetPower2GHT40;
3800                 pFreqBin = eep->calTarget_freqbin_2GHT40;
3801         } else {
3802                 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
3803                 pEepromTargetPwr = eep->calTargetPower5GHT40;
3804                 pFreqBin = eep->calTarget_freqbin_5GHT40;
3805         }
3806
3807         /*
3808          * create array of channels and targetpower from
3809          * targetpower piers stored on eeprom
3810          */
3811         for (i = 0; i < numPiers; i++) {
3812                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
3813                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3814         }
3815
3816         /* interpolate to get target power for given frequency */
3817         return (u8) ar9003_hw_power_interpolate((s32) freq,
3818                                                  freqArray,
3819                                                  targetPowerArray, numPiers);
3820 }
3821
3822 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
3823                                            u16 rateIndex, u16 freq)
3824 {
3825         u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
3826         s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3827         s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
3828         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3829         struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
3830         u8 *pFreqBin = eep->calTarget_freqbin_Cck;
3831
3832         /*
3833          * create array of channels and targetpower from
3834          * targetpower piers stored on eeprom
3835          */
3836         for (i = 0; i < numPiers; i++) {
3837                 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
3838                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
3839         }
3840
3841         /* interpolate to get target power for given frequency */
3842         return (u8) ar9003_hw_power_interpolate((s32) freq,
3843                                                  freqArray,
3844                                                  targetPowerArray, numPiers);
3845 }
3846
3847 /* Set tx power registers to array of values passed in */
3848 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
3849 {
3850 #define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
3851         /* make sure forced gain is not set */
3852         REG_WRITE(ah, 0xa458, 0);
3853
3854         /* Write the OFDM power per rate set */
3855
3856         /* 6 (LSB), 9, 12, 18 (MSB) */
3857         REG_WRITE(ah, 0xa3c0,
3858                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
3859                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
3860                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
3861                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3862
3863         /* 24 (LSB), 36, 48, 54 (MSB) */
3864         REG_WRITE(ah, 0xa3c4,
3865                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
3866                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
3867                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
3868                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
3869
3870         /* Write the CCK power per rate set */
3871
3872         /* 1L (LSB), reserved, 2L, 2S (MSB) */
3873         REG_WRITE(ah, 0xa3c8,
3874                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
3875                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
3876                   /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
3877                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
3878
3879         /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
3880         REG_WRITE(ah, 0xa3cc,
3881                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
3882                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
3883                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
3884                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
3885             );
3886
3887         /* Write the HT20 power per rate set */
3888
3889         /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
3890         REG_WRITE(ah, 0xa3d0,
3891                   POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
3892                   POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
3893                   POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
3894                   POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
3895             );
3896
3897         /* 6 (LSB), 7, 12, 13 (MSB) */
3898         REG_WRITE(ah, 0xa3d4,
3899                   POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
3900                   POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
3901                   POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
3902                   POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
3903             );
3904
3905         /* 14 (LSB), 15, 20, 21 */
3906         REG_WRITE(ah, 0xa3e4,
3907                   POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
3908                   POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
3909                   POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
3910                   POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
3911             );
3912
3913         /* Mixed HT20 and HT40 rates */
3914
3915         /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
3916         REG_WRITE(ah, 0xa3e8,
3917                   POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
3918                   POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
3919                   POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
3920                   POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
3921             );
3922
3923         /*
3924          * Write the HT40 power per rate set
3925          * correct PAR difference between HT40 and HT20/LEGACY
3926          * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
3927          */
3928         REG_WRITE(ah, 0xa3d8,
3929                   POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
3930                   POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
3931                   POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
3932                   POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
3933             );
3934
3935         /* 6 (LSB), 7, 12, 13 (MSB) */
3936         REG_WRITE(ah, 0xa3dc,
3937                   POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
3938                   POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
3939                   POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
3940                   POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
3941             );
3942
3943         /* 14 (LSB), 15, 20, 21 */
3944         REG_WRITE(ah, 0xa3ec,
3945                   POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
3946                   POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
3947                   POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
3948                   POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
3949             );
3950
3951         return 0;
3952 #undef POW_SM
3953 }
3954
3955 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
3956                                               u8 *targetPowerValT2)
3957 {
3958         /* XXX: hard code for now, need to get from eeprom struct */
3959         u8 ht40PowerIncForPdadc = 0;
3960         bool is2GHz = false;
3961         unsigned int i = 0;
3962         struct ath_common *common = ath9k_hw_common(ah);
3963
3964         if (freq < 4000)
3965                 is2GHz = true;
3966
3967         targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
3968             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
3969                                          is2GHz);
3970         targetPowerValT2[ALL_TARGET_LEGACY_36] =
3971             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
3972                                          is2GHz);
3973         targetPowerValT2[ALL_TARGET_LEGACY_48] =
3974             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
3975                                          is2GHz);
3976         targetPowerValT2[ALL_TARGET_LEGACY_54] =
3977             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
3978                                          is2GHz);
3979         targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
3980             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
3981                                              freq);
3982         targetPowerValT2[ALL_TARGET_LEGACY_5S] =
3983             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
3984         targetPowerValT2[ALL_TARGET_LEGACY_11L] =
3985             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
3986         targetPowerValT2[ALL_TARGET_LEGACY_11S] =
3987             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
3988         targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
3989             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
3990                                               is2GHz);
3991         targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
3992             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
3993                                               freq, is2GHz);
3994         targetPowerValT2[ALL_TARGET_HT20_4] =
3995             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
3996                                               is2GHz);
3997         targetPowerValT2[ALL_TARGET_HT20_5] =
3998             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
3999                                               is2GHz);
4000         targetPowerValT2[ALL_TARGET_HT20_6] =
4001             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4002                                               is2GHz);
4003         targetPowerValT2[ALL_TARGET_HT20_7] =
4004             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4005                                               is2GHz);
4006         targetPowerValT2[ALL_TARGET_HT20_12] =
4007             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4008                                               is2GHz);
4009         targetPowerValT2[ALL_TARGET_HT20_13] =
4010             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4011                                               is2GHz);
4012         targetPowerValT2[ALL_TARGET_HT20_14] =
4013             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4014                                               is2GHz);
4015         targetPowerValT2[ALL_TARGET_HT20_15] =
4016             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4017                                               is2GHz);
4018         targetPowerValT2[ALL_TARGET_HT20_20] =
4019             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4020                                               is2GHz);
4021         targetPowerValT2[ALL_TARGET_HT20_21] =
4022             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4023                                               is2GHz);
4024         targetPowerValT2[ALL_TARGET_HT20_22] =
4025             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4026                                               is2GHz);
4027         targetPowerValT2[ALL_TARGET_HT20_23] =
4028             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4029                                               is2GHz);
4030         targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4031             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4032                                               is2GHz) + ht40PowerIncForPdadc;
4033         targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4034             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4035                                               freq,
4036                                               is2GHz) + ht40PowerIncForPdadc;
4037         targetPowerValT2[ALL_TARGET_HT40_4] =
4038             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4039                                               is2GHz) + ht40PowerIncForPdadc;
4040         targetPowerValT2[ALL_TARGET_HT40_5] =
4041             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4042                                               is2GHz) + ht40PowerIncForPdadc;
4043         targetPowerValT2[ALL_TARGET_HT40_6] =
4044             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4045                                               is2GHz) + ht40PowerIncForPdadc;
4046         targetPowerValT2[ALL_TARGET_HT40_7] =
4047             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4048                                               is2GHz) + ht40PowerIncForPdadc;
4049         targetPowerValT2[ALL_TARGET_HT40_12] =
4050             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4051                                               is2GHz) + ht40PowerIncForPdadc;
4052         targetPowerValT2[ALL_TARGET_HT40_13] =
4053             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4054                                               is2GHz) + ht40PowerIncForPdadc;
4055         targetPowerValT2[ALL_TARGET_HT40_14] =
4056             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4057                                               is2GHz) + ht40PowerIncForPdadc;
4058         targetPowerValT2[ALL_TARGET_HT40_15] =
4059             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4060                                               is2GHz) + ht40PowerIncForPdadc;
4061         targetPowerValT2[ALL_TARGET_HT40_20] =
4062             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4063                                               is2GHz) + ht40PowerIncForPdadc;
4064         targetPowerValT2[ALL_TARGET_HT40_21] =
4065             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4066                                               is2GHz) + ht40PowerIncForPdadc;
4067         targetPowerValT2[ALL_TARGET_HT40_22] =
4068             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4069                                               is2GHz) + ht40PowerIncForPdadc;
4070         targetPowerValT2[ALL_TARGET_HT40_23] =
4071             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4072                                               is2GHz) + ht40PowerIncForPdadc;
4073
4074         while (i < ar9300RateSize) {
4075                 ath_print(common, ATH_DBG_EEPROM,
4076                           "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4077                 i++;
4078
4079                 ath_print(common, ATH_DBG_EEPROM,
4080                           "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4081                 i++;
4082
4083                 ath_print(common, ATH_DBG_EEPROM,
4084                           "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4085                 i++;
4086
4087                 ath_print(common, ATH_DBG_EEPROM,
4088                           "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4089                 i++;
4090         }
4091 }
4092
4093 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4094                                   int mode,
4095                                   int ipier,
4096                                   int ichain,
4097                                   int *pfrequency,
4098                                   int *pcorrection,
4099                                   int *ptemperature, int *pvoltage)
4100 {
4101         u8 *pCalPier;
4102         struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4103         int is2GHz;
4104         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4105         struct ath_common *common = ath9k_hw_common(ah);
4106
4107         if (ichain >= AR9300_MAX_CHAINS) {
4108                 ath_print(common, ATH_DBG_EEPROM,
4109                           "Invalid chain index, must be less than %d\n",
4110                           AR9300_MAX_CHAINS);
4111                 return -1;
4112         }
4113
4114         if (mode) {             /* 5GHz */
4115                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4116                         ath_print(common, ATH_DBG_EEPROM,
4117                                   "Invalid 5GHz cal pier index, must "
4118                                   "be less than %d\n",
4119                                   AR9300_NUM_5G_CAL_PIERS);
4120                         return -1;
4121                 }
4122                 pCalPier = &(eep->calFreqPier5G[ipier]);
4123                 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4124                 is2GHz = 0;
4125         } else {
4126                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4127                         ath_print(common, ATH_DBG_EEPROM,
4128                                   "Invalid 2GHz cal pier index, must "
4129                                   "be less than %d\n", AR9300_NUM_2G_CAL_PIERS);
4130                         return -1;
4131                 }
4132
4133                 pCalPier = &(eep->calFreqPier2G[ipier]);
4134                 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4135                 is2GHz = 1;
4136         }
4137
4138         *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4139         *pcorrection = pCalPierStruct->refPower;
4140         *ptemperature = pCalPierStruct->tempMeas;
4141         *pvoltage = pCalPierStruct->voltMeas;
4142
4143         return 0;
4144 }
4145
4146 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4147                                             int frequency,
4148                                             int *correction,
4149                                             int *voltage, int *temperature)
4150 {
4151         int tempSlope = 0;
4152         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4153         int f[3], t[3];
4154
4155         REG_RMW(ah, AR_PHY_TPC_11_B0,
4156                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4157                 AR_PHY_TPC_OLPC_GAIN_DELTA);
4158         REG_RMW(ah, AR_PHY_TPC_11_B1,
4159                 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4160                 AR_PHY_TPC_OLPC_GAIN_DELTA);
4161         REG_RMW(ah, AR_PHY_TPC_11_B2,
4162                 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4163                 AR_PHY_TPC_OLPC_GAIN_DELTA);
4164
4165         /* enable open loop power control on chip */
4166         REG_RMW(ah, AR_PHY_TPC_6_B0,
4167                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4168                 AR_PHY_TPC_6_ERROR_EST_MODE);
4169         REG_RMW(ah, AR_PHY_TPC_6_B1,
4170                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4171                 AR_PHY_TPC_6_ERROR_EST_MODE);
4172         REG_RMW(ah, AR_PHY_TPC_6_B2,
4173                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4174                 AR_PHY_TPC_6_ERROR_EST_MODE);
4175
4176         /*
4177          * enable temperature compensation
4178          * Need to use register names
4179          */
4180         if (frequency < 4000)
4181                 tempSlope = eep->modalHeader2G.tempSlope;
4182         else if (eep->base_ext2.tempSlopeLow != 0) {
4183                 t[0] = eep->base_ext2.tempSlopeLow;
4184                 f[0] = 5180;
4185                 t[1] = eep->modalHeader5G.tempSlope;
4186                 f[1] = 5500;
4187                 t[2] = eep->base_ext2.tempSlopeHigh;
4188                 f[2] = 5785;
4189                 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4190                                                         f, t, 3);
4191         } else
4192                 tempSlope = eep->modalHeader5G.tempSlope;
4193
4194         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4195         REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4196                       temperature[0]);
4197
4198         return 0;
4199 }
4200
4201 /* Apply the recorded correction values. */
4202 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4203 {
4204         int ichain, ipier, npier;
4205         int mode;
4206         int lfrequency[AR9300_MAX_CHAINS],
4207             lcorrection[AR9300_MAX_CHAINS],
4208             ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4209         int hfrequency[AR9300_MAX_CHAINS],
4210             hcorrection[AR9300_MAX_CHAINS],
4211             htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4212         int fdiff;
4213         int correction[AR9300_MAX_CHAINS],
4214             voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4215         int pfrequency, pcorrection, ptemperature, pvoltage;
4216         struct ath_common *common = ath9k_hw_common(ah);
4217
4218         mode = (frequency >= 4000);
4219         if (mode)
4220                 npier = AR9300_NUM_5G_CAL_PIERS;
4221         else
4222                 npier = AR9300_NUM_2G_CAL_PIERS;
4223
4224         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4225                 lfrequency[ichain] = 0;
4226                 hfrequency[ichain] = 100000;
4227         }
4228         /* identify best lower and higher frequency calibration measurement */
4229         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4230                 for (ipier = 0; ipier < npier; ipier++) {
4231                         if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4232                                                     &pfrequency, &pcorrection,
4233                                                     &ptemperature, &pvoltage)) {
4234                                 fdiff = frequency - pfrequency;
4235
4236                                 /*
4237                                  * this measurement is higher than
4238                                  * our desired frequency
4239                                  */
4240                                 if (fdiff <= 0) {
4241                                         if (hfrequency[ichain] <= 0 ||
4242                                             hfrequency[ichain] >= 100000 ||
4243                                             fdiff >
4244                                             (frequency - hfrequency[ichain])) {
4245                                                 /*
4246                                                  * new best higher
4247                                                  * frequency measurement
4248                                                  */
4249                                                 hfrequency[ichain] = pfrequency;
4250                                                 hcorrection[ichain] =
4251                                                     pcorrection;
4252                                                 htemperature[ichain] =
4253                                                     ptemperature;
4254                                                 hvoltage[ichain] = pvoltage;
4255                                         }
4256                                 }
4257                                 if (fdiff >= 0) {
4258                                         if (lfrequency[ichain] <= 0
4259                                             || fdiff <
4260                                             (frequency - lfrequency[ichain])) {
4261                                                 /*
4262                                                  * new best lower
4263                                                  * frequency measurement
4264                                                  */
4265                                                 lfrequency[ichain] = pfrequency;
4266                                                 lcorrection[ichain] =
4267                                                     pcorrection;
4268                                                 ltemperature[ichain] =
4269                                                     ptemperature;
4270                                                 lvoltage[ichain] = pvoltage;
4271                                         }
4272                                 }
4273                         }
4274                 }
4275         }
4276
4277         /* interpolate  */
4278         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4279                 ath_print(common, ATH_DBG_EEPROM,
4280                           "ch=%d f=%d low=%d %d h=%d %d\n",
4281                           ichain, frequency, lfrequency[ichain],
4282                           lcorrection[ichain], hfrequency[ichain],
4283                           hcorrection[ichain]);
4284                 /* they're the same, so just pick one */
4285                 if (hfrequency[ichain] == lfrequency[ichain]) {
4286                         correction[ichain] = lcorrection[ichain];
4287                         voltage[ichain] = lvoltage[ichain];
4288                         temperature[ichain] = ltemperature[ichain];
4289                 }
4290                 /* the low frequency is good */
4291                 else if (frequency - lfrequency[ichain] < 1000) {
4292                         /* so is the high frequency, interpolate */
4293                         if (hfrequency[ichain] - frequency < 1000) {
4294
4295                                 correction[ichain] = interpolate(frequency,
4296                                                 lfrequency[ichain],
4297                                                 hfrequency[ichain],
4298                                                 lcorrection[ichain],
4299                                                 hcorrection[ichain]);
4300
4301                                 temperature[ichain] = interpolate(frequency,
4302                                                 lfrequency[ichain],
4303                                                 hfrequency[ichain],
4304                                                 ltemperature[ichain],
4305                                                 htemperature[ichain]);
4306
4307                                 voltage[ichain] = interpolate(frequency,
4308                                                 lfrequency[ichain],
4309                                                 hfrequency[ichain],
4310                                                 lvoltage[ichain],
4311                                                 hvoltage[ichain]);
4312                         }
4313                         /* only low is good, use it */
4314                         else {
4315                                 correction[ichain] = lcorrection[ichain];
4316                                 temperature[ichain] = ltemperature[ichain];
4317                                 voltage[ichain] = lvoltage[ichain];
4318                         }
4319                 }
4320                 /* only high is good, use it */
4321                 else if (hfrequency[ichain] - frequency < 1000) {
4322                         correction[ichain] = hcorrection[ichain];
4323                         temperature[ichain] = htemperature[ichain];
4324                         voltage[ichain] = hvoltage[ichain];
4325                 } else {        /* nothing is good, presume 0???? */
4326                         correction[ichain] = 0;
4327                         temperature[ichain] = 0;
4328                         voltage[ichain] = 0;
4329                 }
4330         }
4331
4332         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4333                                          temperature);
4334
4335         ath_print(common, ATH_DBG_EEPROM,
4336                   "for frequency=%d, calibration correction = %d %d %d\n",
4337                   frequency, correction[0], correction[1], correction[2]);
4338
4339         return 0;
4340 }
4341
4342 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4343                                            int idx,
4344                                            int edge,
4345                                            bool is2GHz)
4346 {
4347         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4348         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4349
4350         if (is2GHz)
4351                 return ctl_2g[idx].ctlEdges[edge].tPower;
4352         else
4353                 return ctl_5g[idx].ctlEdges[edge].tPower;
4354 }
4355
4356 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4357                                              int idx,
4358                                              unsigned int edge,
4359                                              u16 freq,
4360                                              bool is2GHz)
4361 {
4362         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4363         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4364
4365         u8 *ctl_freqbin = is2GHz ?
4366                 &eep->ctl_freqbin_2G[idx][0] :
4367                 &eep->ctl_freqbin_5G[idx][0];
4368
4369         if (is2GHz) {
4370                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4371                     ctl_2g[idx].ctlEdges[edge - 1].flag)
4372                         return ctl_2g[idx].ctlEdges[edge - 1].tPower;
4373         } else {
4374                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4375                     ctl_5g[idx].ctlEdges[edge - 1].flag)
4376                         return ctl_5g[idx].ctlEdges[edge - 1].tPower;
4377         }
4378
4379         return AR9300_MAX_RATE_POWER;
4380 }
4381
4382 /*
4383  * Find the maximum conformance test limit for the given channel and CTL info
4384  */
4385 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4386                                         u16 freq, int idx, bool is2GHz)
4387 {
4388         u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4389         u8 *ctl_freqbin = is2GHz ?
4390                 &eep->ctl_freqbin_2G[idx][0] :
4391                 &eep->ctl_freqbin_5G[idx][0];
4392         u16 num_edges = is2GHz ?
4393                 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4394         unsigned int edge;
4395
4396         /* Get the edge power */
4397         for (edge = 0;
4398              (edge < num_edges) && (ctl_freqbin[edge] != AR9300_BCHAN_UNUSED);
4399              edge++) {
4400                 /*
4401                  * If there's an exact channel match or an inband flag set
4402                  * on the lower channel use the given rdEdgePower
4403                  */
4404                 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4405                         twiceMaxEdgePower =
4406                                 ar9003_hw_get_direct_edge_power(eep, idx,
4407                                                                 edge, is2GHz);
4408                         break;
4409                 } else if ((edge > 0) &&
4410                            (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4411                                                       is2GHz))) {
4412                         twiceMaxEdgePower =
4413                                 ar9003_hw_get_indirect_edge_power(eep, idx,
4414                                                                   edge, freq,
4415                                                                   is2GHz);
4416                         /*
4417                          * Leave loop - no more affecting edges possible in
4418                          * this monotonic increasing list
4419                          */
4420                         break;
4421                 }
4422         }
4423         return twiceMaxEdgePower;
4424 }
4425
4426 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4427                                                struct ath9k_channel *chan,
4428                                                u8 *pPwrArray, u16 cfgCtl,
4429                                                u8 twiceAntennaReduction,
4430                                                u8 twiceMaxRegulatoryPower,
4431                                                u16 powerLimit)
4432 {
4433         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4434         struct ath_common *common = ath9k_hw_common(ah);
4435         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4436         u16 twiceMaxEdgePower = AR9300_MAX_RATE_POWER;
4437         static const u16 tpScaleReductionTable[5] = {
4438                 0, 3, 6, 9, AR9300_MAX_RATE_POWER
4439         };
4440         int i;
4441         int16_t  twiceLargestAntenna;
4442         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4443         u16 ctlModesFor11a[] = {
4444                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4445         };
4446         u16 ctlModesFor11g[] = {
4447                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4448                 CTL_11G_EXT, CTL_2GHT40
4449         };
4450         u16 numCtlModes, *pCtlMode, ctlMode, freq;
4451         struct chan_centers centers;
4452         u8 *ctlIndex;
4453         u8 ctlNum;
4454         u16 twiceMinEdgePower;
4455         bool is2ghz = IS_CHAN_2GHZ(chan);
4456
4457         ath9k_hw_get_channel_centers(ah, chan, &centers);
4458
4459         /* Compute TxPower reduction due to Antenna Gain */
4460         if (is2ghz)
4461                 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4462         else
4463                 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4464
4465         twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4466                                 twiceLargestAntenna, 0);
4467
4468         /*
4469          * scaledPower is the minimum of the user input power level
4470          * and the regulatory allowed power level
4471          */
4472         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4473
4474         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4475                 maxRegAllowedPower -=
4476                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4477         }
4478
4479         scaledPower = min(powerLimit, maxRegAllowedPower);
4480
4481         /*
4482          * Reduce scaled Power by number of chains active to get
4483          * to per chain tx power level
4484          */
4485         switch (ar5416_get_ntxchains(ah->txchainmask)) {
4486         case 1:
4487                 break;
4488         case 2:
4489                 scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4490                 break;
4491         case 3:
4492                 scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4493                 break;
4494         }
4495
4496         scaledPower = max((u16)0, scaledPower);
4497
4498         /*
4499          * Get target powers from EEPROM - our baseline for TX Power
4500          */
4501         if (is2ghz) {
4502                 /* Setup for CTL modes */
4503                 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4504                 numCtlModes =
4505                         ARRAY_SIZE(ctlModesFor11g) -
4506                                    SUB_NUM_CTL_MODES_AT_2G_40;
4507                 pCtlMode = ctlModesFor11g;
4508                 if (IS_CHAN_HT40(chan))
4509                         /* All 2G CTL's */
4510                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4511         } else {
4512                 /* Setup for CTL modes */
4513                 /* CTL_11A, CTL_5GHT20 */
4514                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4515                                          SUB_NUM_CTL_MODES_AT_5G_40;
4516                 pCtlMode = ctlModesFor11a;
4517                 if (IS_CHAN_HT40(chan))
4518                         /* All 5G CTL's */
4519                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4520         }
4521
4522         /*
4523          * For MIMO, need to apply regulatory caps individually across
4524          * dynamically running modes: CCK, OFDM, HT20, HT40
4525          *
4526          * The outer loop walks through each possible applicable runtime mode.
4527          * The inner loop walks through each ctlIndex entry in EEPROM.
4528          * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4529          */
4530         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4531                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4532                         (pCtlMode[ctlMode] == CTL_2GHT40);
4533                 if (isHt40CtlMode)
4534                         freq = centers.synth_center;
4535                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4536                         freq = centers.ext_center;
4537                 else
4538                         freq = centers.ctl_center;
4539
4540                 ath_print(common, ATH_DBG_REGULATORY,
4541                           "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4542                           "EXT_ADDITIVE %d\n",
4543                           ctlMode, numCtlModes, isHt40CtlMode,
4544                           (pCtlMode[ctlMode] & EXT_ADDITIVE));
4545
4546                 /* walk through each CTL index stored in EEPROM */
4547                 if (is2ghz) {
4548                         ctlIndex = pEepData->ctlIndex_2G;
4549                         ctlNum = AR9300_NUM_CTLS_2G;
4550                 } else {
4551                         ctlIndex = pEepData->ctlIndex_5G;
4552                         ctlNum = AR9300_NUM_CTLS_5G;
4553                 }
4554
4555                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4556                         ath_print(common, ATH_DBG_REGULATORY,
4557                                   "LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4558                                   "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4559                                   "chan %dn",
4560                                   i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4561                                   chan->channel);
4562
4563                                 /*
4564                                  * compare test group from regulatory
4565                                  * channel list with test mode from pCtlMode
4566                                  * list
4567                                  */
4568                                 if ((((cfgCtl & ~CTL_MODE_M) |
4569                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4570                                         ctlIndex[i]) ||
4571                                     (((cfgCtl & ~CTL_MODE_M) |
4572                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4573                                      ((ctlIndex[i] & CTL_MODE_M) |
4574                                        SD_NO_CTL))) {
4575                                         twiceMinEdgePower =
4576                                           ar9003_hw_get_max_edge_power(pEepData,
4577                                                                        freq, i,
4578                                                                        is2ghz);
4579
4580                                         if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4581                                                 /*
4582                                                  * Find the minimum of all CTL
4583                                                  * edge powers that apply to
4584                                                  * this channel
4585                                                  */
4586                                                 twiceMaxEdgePower =
4587                                                         min(twiceMaxEdgePower,
4588                                                             twiceMinEdgePower);
4589                                                 else {
4590                                                         /* specific */
4591                                                         twiceMaxEdgePower =
4592                                                           twiceMinEdgePower;
4593                                                         break;
4594                                                 }
4595                                 }
4596                         }
4597
4598                         minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4599
4600                         ath_print(common, ATH_DBG_REGULATORY,
4601                                   "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d "
4602                                   "sP %d minCtlPwr %d\n",
4603                                   ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4604                                   scaledPower, minCtlPower);
4605
4606                         /* Apply ctl mode to correct target power set */
4607                         switch (pCtlMode[ctlMode]) {
4608                         case CTL_11B:
4609                                 for (i = ALL_TARGET_LEGACY_1L_5L;
4610                                      i <= ALL_TARGET_LEGACY_11S; i++)
4611                                         pPwrArray[i] =
4612                                           (u8)min((u16)pPwrArray[i],
4613                                                   minCtlPower);
4614                                 break;
4615                         case CTL_11A:
4616                         case CTL_11G:
4617                                 for (i = ALL_TARGET_LEGACY_6_24;
4618                                      i <= ALL_TARGET_LEGACY_54; i++)
4619                                         pPwrArray[i] =
4620                                           (u8)min((u16)pPwrArray[i],
4621                                                   minCtlPower);
4622                                 break;
4623                         case CTL_5GHT20:
4624                         case CTL_2GHT20:
4625                                 for (i = ALL_TARGET_HT20_0_8_16;
4626                                      i <= ALL_TARGET_HT20_21; i++)
4627                                         pPwrArray[i] =
4628                                           (u8)min((u16)pPwrArray[i],
4629                                                   minCtlPower);
4630                                 pPwrArray[ALL_TARGET_HT20_22] =
4631                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4632                                           minCtlPower);
4633                                 pPwrArray[ALL_TARGET_HT20_23] =
4634                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4635                                            minCtlPower);
4636                                 break;
4637                         case CTL_5GHT40:
4638                         case CTL_2GHT40:
4639                                 for (i = ALL_TARGET_HT40_0_8_16;
4640                                      i <= ALL_TARGET_HT40_23; i++)
4641                                         pPwrArray[i] =
4642                                           (u8)min((u16)pPwrArray[i],
4643                                                   minCtlPower);
4644                                 break;
4645                         default:
4646                             break;
4647                         }
4648         } /* end ctl mode checking */
4649 }
4650
4651 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4652                                         struct ath9k_channel *chan, u16 cfgCtl,
4653                                         u8 twiceAntennaReduction,
4654                                         u8 twiceMaxRegulatoryPower,
4655                                         u8 powerLimit, bool test)
4656 {
4657         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4658         struct ath_common *common = ath9k_hw_common(ah);
4659         u8 targetPowerValT2[ar9300RateSize];
4660         unsigned int i = 0;
4661
4662         ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
4663         ar9003_hw_set_power_per_rate_table(ah, chan,
4664                                            targetPowerValT2, cfgCtl,
4665                                            twiceAntennaReduction,
4666                                            twiceMaxRegulatoryPower,
4667                                            powerLimit);
4668
4669         regulatory->max_power_level = 0;
4670         for (i = 0; i < ar9300RateSize; i++) {
4671                 if (targetPowerValT2[i] > regulatory->max_power_level)
4672                         regulatory->max_power_level = targetPowerValT2[i];
4673         }
4674
4675         if (test)
4676                 return;
4677
4678         for (i = 0; i < ar9300RateSize; i++) {
4679                 ath_print(common, ATH_DBG_EEPROM,
4680                           "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4681                 i++;
4682                 ath_print(common, ATH_DBG_EEPROM,
4683                           "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4684                 i++;
4685                 ath_print(common, ATH_DBG_EEPROM,
4686                           "TPC[%02d] 0x%08x ", i, targetPowerValT2[i]);
4687                 i++;
4688                 ath_print(common, ATH_DBG_EEPROM,
4689                           "TPC[%02d] 0x%08x\n\n", i, targetPowerValT2[i]);
4690                 i++;
4691         }
4692
4693         /*
4694          * This is the TX power we send back to driver core,
4695          * and it can use to pass to userspace to display our
4696          * currently configured TX power setting.
4697          *
4698          * Since power is rate dependent, use one of the indices
4699          * from the AR9300_Rates enum to select an entry from
4700          * targetPowerValT2[] to report. Currently returns the
4701          * power for HT40 MCS 0, HT20 MCS 0, or OFDM 6 Mbps
4702          * as CCK power is less interesting (?).
4703          */
4704         i = ALL_TARGET_LEGACY_6_24; /* legacy */
4705         if (IS_CHAN_HT40(chan))
4706                 i = ALL_TARGET_HT40_0_8_16; /* ht40 */
4707         else if (IS_CHAN_HT20(chan))
4708                 i = ALL_TARGET_HT20_0_8_16; /* ht20 */
4709
4710         ah->txpower_limit = targetPowerValT2[i];
4711         regulatory->max_power_level = targetPowerValT2[i];
4712
4713         /* Write target power array to registers */
4714         ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
4715         ar9003_hw_calibration_apply(ah, chan->channel);
4716 }
4717
4718 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
4719                                             u16 i, bool is2GHz)
4720 {
4721         return AR_NO_SPUR;
4722 }
4723
4724 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
4725 {
4726         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4727
4728         return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
4729 }
4730
4731 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
4732 {
4733         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4734
4735         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
4736 }
4737
4738 const struct eeprom_ops eep_ar9300_ops = {
4739         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
4740         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
4741         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
4742         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
4743         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
4744         .get_num_ant_config = ath9k_hw_ar9300_get_num_ant_config,
4745         .get_eeprom_antenna_cfg = ath9k_hw_ar9300_get_eeprom_antenna_cfg,
4746         .set_board_values = ath9k_hw_ar9300_set_board_values,
4747         .set_addac = ath9k_hw_ar9300_set_addac,
4748         .set_txpower = ath9k_hw_ar9300_set_txpower,
4749         .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
4750 };