drivers/net/wireless/ath/ath9k/ar9003_eeprom.c

   1 /*
   2  * Copyright (c) 2010-2011 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include <asm/unaligned.h>
  18 #include "hw.h"
  19 #include "ar9003_phy.h"
  20 #include "ar9003_eeprom.h"
  21
  22 #define COMP_HDR_LEN 4
  23 #define COMP_CKSUM_LEN 2
  24
  25 #define AR_CH0_TOP      (AR_SREV_9300(ah) ? 0x16288 : \
  26                                 ((AR_SREV_9480(ah) ? 0x1628c : 0x16280)))
  27 #define AR_CH0_TOP_XPABIASLVL (0x300)
  28 #define AR_CH0_TOP_XPABIASLVL_S (8)
  29
  30 #define AR_CH0_THERM    (AR_SREV_9300(ah) ? 0x16290 : \
  31                                 ((AR_SREV_9485(ah) ? 0x1628c : 0x16294)))
  32 #define AR_CH0_THERM_XPABIASLVL_MSB 0x3
  33 #define AR_CH0_THERM_XPABIASLVL_MSB_S 0
  34 #define AR_CH0_THERM_XPASHORT2GND 0x4
  35 #define AR_CH0_THERM_XPASHORT2GND_S 2
  36
  37 #define AR_SWITCH_TABLE_COM_ALL (0xffff)
  38 #define AR_SWITCH_TABLE_COM_ALL_S (0)
  39 #define AR_SWITCH_TABLE_COM_AR9480_ALL (0xffffff)
  40 #define AR_SWITCH_TABLE_COM_AR9480_ALL_S (0)
  41 #define AR_SWITCH_TABLE_COM_SPDT (0x00f00000)
  42 #define AR_SWITCH_TABLE_COM_SPDT_ALL (0x0000fff0)
  43 #define AR_SWITCH_TABLE_COM_SPDT_ALL_S (4)
  44
  45 #define AR_SWITCH_TABLE_COM2_ALL (0xffffff)
  46 #define AR_SWITCH_TABLE_COM2_ALL_S (0)
  47
  48 #define AR_SWITCH_TABLE_ALL (0xfff)
  49 #define AR_SWITCH_TABLE_ALL_S (0)
  50
  51 #define LE16(x) __constant_cpu_to_le16(x)
  52 #define LE32(x) __constant_cpu_to_le32(x)
  53
  54 /* Local defines to distinguish between extension and control CTL's */
  55 #define EXT_ADDITIVE (0x8000)
  56 #define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
  57 #define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
  58 #define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
  59 #define REDUCE_SCALED_POWER_BY_TWO_CHAIN     6  /* 10*log10(2)*2 */
  60 #define REDUCE_SCALED_POWER_BY_THREE_CHAIN   9  /* 10*log10(3)*2 */
  61 #define PWRINCR_3_TO_1_CHAIN      9             /* 10*log(3)*2 */
  62 #define PWRINCR_3_TO_2_CHAIN      3             /* floor(10*log(3/2)*2) */
  63 #define PWRINCR_2_TO_1_CHAIN      6             /* 10*log(2)*2 */
  64
  65 #define SUB_NUM_CTL_MODES_AT_5G_40 2    /* excluding HT40, EXT-OFDM */
  66 #define SUB_NUM_CTL_MODES_AT_2G_40 3    /* excluding HT40, EXT-OFDM, EXT-CCK */
  67
  68 #define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
  69
  70 #define EEPROM_DATA_LEN_9485    1088
  71
  72 static int ar9003_hw_power_interpolate(int32_t x,
  73                                        int32_t *px, int32_t *py, u_int16_t np);
  74
  75
  76 static const struct ar9300_eeprom ar9300_default = {
  77         .eepromVersion = 2,
  78         .templateVersion = 2,
  79         .macAddr = {1, 2, 3, 4, 5, 6},
  80         .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
  81                      0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
  82         .baseEepHeader = {
  83                 .regDmn = { LE16(0), LE16(0x1f) },
  84                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
  85                 .opCapFlags = {
  86                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
  87                         .eepMisc = 0,
  88                 },
  89                 .rfSilent = 0,
  90                 .blueToothOptions = 0,
  91                 .deviceCap = 0,
  92                 .deviceType = 5, /* takes lower byte in eeprom location */
  93                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
  94                 .params_for_tuning_caps = {0, 0},
  95                 .featureEnable = 0x0c,
  96                  /*
  97                   * bit0 - enable tx temp comp - disabled
  98                   * bit1 - enable tx volt comp - disabled
  99                   * bit2 - enable fastClock - enabled
 100                   * bit3 - enable doubling - enabled
 101                   * bit4 - enable internal regulator - disabled
 102                   * bit5 - enable pa predistortion - disabled
 103                   */
 104                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 105                 .eepromWriteEnableGpio = 3,
 106                 .wlanDisableGpio = 0,
 107                 .wlanLedGpio = 8,
 108                 .rxBandSelectGpio = 0xff,
 109                 .txrxgain = 0,
 110                 .swreg = 0,
 111          },
 112         .modalHeader2G = {
 113         /* ar9300_modal_eep_header  2g */
 114                 /* 4 idle,t1,t2,b(4 bits per setting) */
 115                 .antCtrlCommon = LE32(0x110),
 116                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 117                 .antCtrlCommon2 = LE32(0x22222),
 118
 119                 /*
 120                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 121                  * rx1, rx12, b (2 bits each)
 122                  */
 123                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 124
 125                 /*
 126                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 127                  * for ar9280 (0xa20c/b20c 5:0)
 128                  */
 129                 .xatten1DB = {0, 0, 0},
 130
 131                 /*
 132                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 133                  * for ar9280 (0xa20c/b20c 16:12
 134                  */
 135                 .xatten1Margin = {0, 0, 0},
 136                 .tempSlope = 36,
 137                 .voltSlope = 0,
 138
 139                 /*
 140                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 141                  * channels in usual fbin coding format
 142                  */
 143                 .spurChans = {0, 0, 0, 0, 0},
 144
 145                 /*
 146                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 147                  * if the register is per chain
 148                  */
 149                 .noiseFloorThreshCh = {-1, 0, 0},
 150                 .ob = {1, 1, 1},/* 3 chain */
 151                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
 152                 .db_stage3 = {0, 0, 0},
 153                 .db_stage4 = {0, 0, 0},
 154                 .xpaBiasLvl = 0,
 155                 .txFrameToDataStart = 0x0e,
 156                 .txFrameToPaOn = 0x0e,
 157                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 158                 .antennaGain = 0,
 159                 .switchSettling = 0x2c,
 160                 .adcDesiredSize = -30,
 161                 .txEndToXpaOff = 0,
 162                 .txEndToRxOn = 0x2,
 163                 .txFrameToXpaOn = 0xe,
 164                 .thresh62 = 28,
 165                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 166                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 167                 .futureModal = {
 168                         0, 0, 0, 0, 0, 0, 0, 0,
 169                 },
 170          },
 171         .base_ext1 = {
 172                 .ant_div_control = 0,
 173                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 174         },
 175         .calFreqPier2G = {
 176                 FREQ2FBIN(2412, 1),
 177                 FREQ2FBIN(2437, 1),
 178                 FREQ2FBIN(2472, 1),
 179          },
 180         /* ar9300_cal_data_per_freq_op_loop 2g */
 181         .calPierData2G = {
 182                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 183                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 184                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 185          },
 186         .calTarget_freqbin_Cck = {
 187                 FREQ2FBIN(2412, 1),
 188                 FREQ2FBIN(2484, 1),
 189          },
 190         .calTarget_freqbin_2G = {
 191                 FREQ2FBIN(2412, 1),
 192                 FREQ2FBIN(2437, 1),
 193                 FREQ2FBIN(2472, 1)
 194          },
 195         .calTarget_freqbin_2GHT20 = {
 196                 FREQ2FBIN(2412, 1),
 197                 FREQ2FBIN(2437, 1),
 198                 FREQ2FBIN(2472, 1)
 199          },
 200         .calTarget_freqbin_2GHT40 = {
 201                 FREQ2FBIN(2412, 1),
 202                 FREQ2FBIN(2437, 1),
 203                 FREQ2FBIN(2472, 1)
 204          },
 205         .calTargetPowerCck = {
 206                  /* 1L-5L,5S,11L,11S */
 207                  { {36, 36, 36, 36} },
 208                  { {36, 36, 36, 36} },
 209         },
 210         .calTargetPower2G = {
 211                  /* 6-24,36,48,54 */
 212                  { {32, 32, 28, 24} },
 213                  { {32, 32, 28, 24} },
 214                  { {32, 32, 28, 24} },
 215         },
 216         .calTargetPower2GHT20 = {
 217                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 218                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 219                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 220         },
 221         .calTargetPower2GHT40 = {
 222                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 223                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 224                 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
 225         },
 226         .ctlIndex_2G =  {
 227                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 228                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 229         },
 230         .ctl_freqbin_2G = {
 231                 {
 232                         FREQ2FBIN(2412, 1),
 233                         FREQ2FBIN(2417, 1),
 234                         FREQ2FBIN(2457, 1),
 235                         FREQ2FBIN(2462, 1)
 236                 },
 237                 {
 238                         FREQ2FBIN(2412, 1),
 239                         FREQ2FBIN(2417, 1),
 240                         FREQ2FBIN(2462, 1),
 241                         0xFF,
 242                 },
 243
 244                 {
 245                         FREQ2FBIN(2412, 1),
 246                         FREQ2FBIN(2417, 1),
 247                         FREQ2FBIN(2462, 1),
 248                         0xFF,
 249                 },
 250                 {
 251                         FREQ2FBIN(2422, 1),
 252                         FREQ2FBIN(2427, 1),
 253                         FREQ2FBIN(2447, 1),
 254                         FREQ2FBIN(2452, 1)
 255                 },
 256
 257                 {
 258                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 259                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 260                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 261                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 262                 },
 263
 264                 {
 265                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 266                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 267                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 268                         0,
 269                 },
 270
 271                 {
 272                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 273                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 274                         FREQ2FBIN(2472, 1),
 275                         0,
 276                 },
 277
 278                 {
 279                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 280                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 281                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 282                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 283                 },
 284
 285                 {
 286                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 287                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 288                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 289                 },
 290
 291                 {
 292                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 293                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 294                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 295                         0
 296                 },
 297
 298                 {
 299                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 300                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 301                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 302                         0
 303                 },
 304
 305                 {
 306                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 307                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 308                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 309                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 310                 }
 311          },
 312         .ctlPowerData_2G = {
 313                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 314                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 315                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 316
 317                  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
 318                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 319                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 320
 321                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 322                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 323                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 324
 325                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 326                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 327                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 328          },
 329         .modalHeader5G = {
 330                 /* 4 idle,t1,t2,b (4 bits per setting) */
 331                 .antCtrlCommon = LE32(0x110),
 332                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 333                 .antCtrlCommon2 = LE32(0x22222),
 334                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 335                 .antCtrlChain = {
 336                         LE16(0x000), LE16(0x000), LE16(0x000),
 337                 },
 338                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 339                 .xatten1DB = {0, 0, 0},
 340
 341                 /*
 342                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 343                  * for merlin (0xa20c/b20c 16:12
 344                  */
 345                 .xatten1Margin = {0, 0, 0},
 346                 .tempSlope = 68,
 347                 .voltSlope = 0,
 348                 /* spurChans spur channels in usual fbin coding format */
 349                 .spurChans = {0, 0, 0, 0, 0},
 350                 /* noiseFloorThreshCh Check if the register is per chain */
 351                 .noiseFloorThreshCh = {-1, 0, 0},
 352                 .ob = {3, 3, 3}, /* 3 chain */
 353                 .db_stage2 = {3, 3, 3}, /* 3 chain */
 354                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 355                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 356                 .xpaBiasLvl = 0,
 357                 .txFrameToDataStart = 0x0e,
 358                 .txFrameToPaOn = 0x0e,
 359                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 360                 .antennaGain = 0,
 361                 .switchSettling = 0x2d,
 362                 .adcDesiredSize = -30,
 363                 .txEndToXpaOff = 0,
 364                 .txEndToRxOn = 0x2,
 365                 .txFrameToXpaOn = 0xe,
 366                 .thresh62 = 28,
 367                 .papdRateMaskHt20 = LE32(0x0c80c080),
 368                 .papdRateMaskHt40 = LE32(0x0080c080),
 369                 .futureModal = {
 370                         0, 0, 0, 0, 0, 0, 0, 0,
 371                 },
 372          },
 373         .base_ext2 = {
 374                 .tempSlopeLow = 0,
 375                 .tempSlopeHigh = 0,
 376                 .xatten1DBLow = {0, 0, 0},
 377                 .xatten1MarginLow = {0, 0, 0},
 378                 .xatten1DBHigh = {0, 0, 0},
 379                 .xatten1MarginHigh = {0, 0, 0}
 380         },
 381         .calFreqPier5G = {
 382                 FREQ2FBIN(5180, 0),
 383                 FREQ2FBIN(5220, 0),
 384                 FREQ2FBIN(5320, 0),
 385                 FREQ2FBIN(5400, 0),
 386                 FREQ2FBIN(5500, 0),
 387                 FREQ2FBIN(5600, 0),
 388                 FREQ2FBIN(5725, 0),
 389                 FREQ2FBIN(5825, 0)
 390         },
 391         .calPierData5G = {
 392                         {
 393                                 {0, 0, 0, 0, 0},
 394                                 {0, 0, 0, 0, 0},
 395                                 {0, 0, 0, 0, 0},
 396                                 {0, 0, 0, 0, 0},
 397                                 {0, 0, 0, 0, 0},
 398                                 {0, 0, 0, 0, 0},
 399                                 {0, 0, 0, 0, 0},
 400                                 {0, 0, 0, 0, 0},
 401                         },
 402                         {
 403                                 {0, 0, 0, 0, 0},
 404                                 {0, 0, 0, 0, 0},
 405                                 {0, 0, 0, 0, 0},
 406                                 {0, 0, 0, 0, 0},
 407                                 {0, 0, 0, 0, 0},
 408                                 {0, 0, 0, 0, 0},
 409                                 {0, 0, 0, 0, 0},
 410                                 {0, 0, 0, 0, 0},
 411                         },
 412                         {
 413                                 {0, 0, 0, 0, 0},
 414                                 {0, 0, 0, 0, 0},
 415                                 {0, 0, 0, 0, 0},
 416                                 {0, 0, 0, 0, 0},
 417                                 {0, 0, 0, 0, 0},
 418                                 {0, 0, 0, 0, 0},
 419                                 {0, 0, 0, 0, 0},
 420                                 {0, 0, 0, 0, 0},
 421                         },
 422
 423         },
 424         .calTarget_freqbin_5G = {
 425                 FREQ2FBIN(5180, 0),
 426                 FREQ2FBIN(5220, 0),
 427                 FREQ2FBIN(5320, 0),
 428                 FREQ2FBIN(5400, 0),
 429                 FREQ2FBIN(5500, 0),
 430                 FREQ2FBIN(5600, 0),
 431                 FREQ2FBIN(5725, 0),
 432                 FREQ2FBIN(5825, 0)
 433         },
 434         .calTarget_freqbin_5GHT20 = {
 435                 FREQ2FBIN(5180, 0),
 436                 FREQ2FBIN(5240, 0),
 437                 FREQ2FBIN(5320, 0),
 438                 FREQ2FBIN(5500, 0),
 439                 FREQ2FBIN(5700, 0),
 440                 FREQ2FBIN(5745, 0),
 441                 FREQ2FBIN(5725, 0),
 442                 FREQ2FBIN(5825, 0)
 443         },
 444         .calTarget_freqbin_5GHT40 = {
 445                 FREQ2FBIN(5180, 0),
 446                 FREQ2FBIN(5240, 0),
 447                 FREQ2FBIN(5320, 0),
 448                 FREQ2FBIN(5500, 0),
 449                 FREQ2FBIN(5700, 0),
 450                 FREQ2FBIN(5745, 0),
 451                 FREQ2FBIN(5725, 0),
 452                 FREQ2FBIN(5825, 0)
 453          },
 454         .calTargetPower5G = {
 455                 /* 6-24,36,48,54 */
 456                 { {20, 20, 20, 10} },
 457                 { {20, 20, 20, 10} },
 458                 { {20, 20, 20, 10} },
 459                 { {20, 20, 20, 10} },
 460                 { {20, 20, 20, 10} },
 461                 { {20, 20, 20, 10} },
 462                 { {20, 20, 20, 10} },
 463                 { {20, 20, 20, 10} },
 464          },
 465         .calTargetPower5GHT20 = {
 466                 /*
 467                  * 0_8_16,1-3_9-11_17-19,
 468                  * 4,5,6,7,12,13,14,15,20,21,22,23
 469                  */
 470                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 471                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 472                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 473                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 474                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 475                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 476                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 477                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 478          },
 479         .calTargetPower5GHT40 =  {
 480                 /*
 481                  * 0_8_16,1-3_9-11_17-19,
 482                  * 4,5,6,7,12,13,14,15,20,21,22,23
 483                  */
 484                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 485                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 486                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 487                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 488                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 489                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 490                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 491                 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
 492          },
 493         .ctlIndex_5G =  {
 494                 0x10, 0x16, 0x18, 0x40, 0x46,
 495                 0x48, 0x30, 0x36, 0x38
 496         },
 497         .ctl_freqbin_5G =  {
 498                 {
 499                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 500                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 501                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 502                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 503                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
 504                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 505                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 506                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 507                 },
 508                 {
 509                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 510                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 511                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
 512                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 513                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
 514                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 515                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 516                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 517                 },
 518
 519                 {
 520                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 521                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 522                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 523                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
 524                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
 525                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
 526                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
 527                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
 528                 },
 529
 530                 {
 531                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 532                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 533                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
 534                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
 535                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 536                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 537                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
 538                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
 539                 },
 540
 541                 {
 542                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 543                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 544                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
 545                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
 546                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
 547                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
 548                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
 549                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
 550                 },
 551
 552                 {
 553                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 554                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
 555                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
 556                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 557                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
 558                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 559                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
 560                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
 561                 },
 562
 563                 {
 564                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 565                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
 566                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
 567                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
 568                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
 569                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
 570                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
 571                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
 572                 },
 573
 574                 {
 575                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
 576                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
 577                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
 578                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
 579                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
 580                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
 581                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
 582                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
 583                 },
 584
 585                 {
 586                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
 587                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
 588                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
 589                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
 590                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
 591                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
 592                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
 593                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
 594                 }
 595          },
 596         .ctlPowerData_5G = {
 597                 {
 598                         {
 599                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 600                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 601                         }
 602                 },
 603                 {
 604                         {
 605                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 606                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 607                         }
 608                 },
 609                 {
 610                         {
 611                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 612                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 613                         }
 614                 },
 615                 {
 616                         {
 617                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 618                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 619                         }
 620                 },
 621                 {
 622                         {
 623                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 624                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 625                         }
 626                 },
 627                 {
 628                         {
 629                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 630                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
 631                         }
 632                 },
 633                 {
 634                         {
 635                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 636                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
 637                         }
 638                 },
 639                 {
 640                         {
 641                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 642                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
 643                         }
 644                 },
 645                 {
 646                         {
 647                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
 648                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
 649                         }
 650                 },
 651          }
 652 };
 653
 654 static const struct ar9300_eeprom ar9300_x113 = {
 655         .eepromVersion = 2,
 656         .templateVersion = 6,
 657         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
 658         .custData = {"x113-023-f0000"},
 659         .baseEepHeader = {
 660                 .regDmn = { LE16(0), LE16(0x1f) },
 661                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
 662                 .opCapFlags = {
 663                         .opFlags = AR5416_OPFLAGS_11A,
 664                         .eepMisc = 0,
 665                 },
 666                 .rfSilent = 0,
 667                 .blueToothOptions = 0,
 668                 .deviceCap = 0,
 669                 .deviceType = 5, /* takes lower byte in eeprom location */
 670                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
 671                 .params_for_tuning_caps = {0, 0},
 672                 .featureEnable = 0x0d,
 673                  /*
 674                   * bit0 - enable tx temp comp - disabled
 675                   * bit1 - enable tx volt comp - disabled
 676                   * bit2 - enable fastClock - enabled
 677                   * bit3 - enable doubling - enabled
 678                   * bit4 - enable internal regulator - disabled
 679                   * bit5 - enable pa predistortion - disabled
 680                   */
 681                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
 682                 .eepromWriteEnableGpio = 6,
 683                 .wlanDisableGpio = 0,
 684                 .wlanLedGpio = 8,
 685                 .rxBandSelectGpio = 0xff,
 686                 .txrxgain = 0x21,
 687                 .swreg = 0,
 688          },
 689         .modalHeader2G = {
 690         /* ar9300_modal_eep_header  2g */
 691                 /* 4 idle,t1,t2,b(4 bits per setting) */
 692                 .antCtrlCommon = LE32(0x110),
 693                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
 694                 .antCtrlCommon2 = LE32(0x44444),
 695
 696                 /*
 697                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
 698                  * rx1, rx12, b (2 bits each)
 699                  */
 700                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
 701
 702                 /*
 703                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
 704                  * for ar9280 (0xa20c/b20c 5:0)
 705                  */
 706                 .xatten1DB = {0, 0, 0},
 707
 708                 /*
 709                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 710                  * for ar9280 (0xa20c/b20c 16:12
 711                  */
 712                 .xatten1Margin = {0, 0, 0},
 713                 .tempSlope = 25,
 714                 .voltSlope = 0,
 715
 716                 /*
 717                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
 718                  * channels in usual fbin coding format
 719                  */
 720                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
 721
 722                 /*
 723                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
 724                  * if the register is per chain
 725                  */
 726                 .noiseFloorThreshCh = {-1, 0, 0},
 727                 .ob = {1, 1, 1},/* 3 chain */
 728                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
 729                 .db_stage3 = {0, 0, 0},
 730                 .db_stage4 = {0, 0, 0},
 731                 .xpaBiasLvl = 0,
 732                 .txFrameToDataStart = 0x0e,
 733                 .txFrameToPaOn = 0x0e,
 734                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 735                 .antennaGain = 0,
 736                 .switchSettling = 0x2c,
 737                 .adcDesiredSize = -30,
 738                 .txEndToXpaOff = 0,
 739                 .txEndToRxOn = 0x2,
 740                 .txFrameToXpaOn = 0xe,
 741                 .thresh62 = 28,
 742                 .papdRateMaskHt20 = LE32(0x0c80c080),
 743                 .papdRateMaskHt40 = LE32(0x0080c080),
 744                 .futureModal = {
 745                         0, 0, 0, 0, 0, 0, 0, 0,
 746                 },
 747          },
 748          .base_ext1 = {
 749                 .ant_div_control = 0,
 750                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
 751          },
 752         .calFreqPier2G = {
 753                 FREQ2FBIN(2412, 1),
 754                 FREQ2FBIN(2437, 1),
 755                 FREQ2FBIN(2472, 1),
 756          },
 757         /* ar9300_cal_data_per_freq_op_loop 2g */
 758         .calPierData2G = {
 759                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 760                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 761                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
 762          },
 763         .calTarget_freqbin_Cck = {
 764                 FREQ2FBIN(2412, 1),
 765                 FREQ2FBIN(2472, 1),
 766          },
 767         .calTarget_freqbin_2G = {
 768                 FREQ2FBIN(2412, 1),
 769                 FREQ2FBIN(2437, 1),
 770                 FREQ2FBIN(2472, 1)
 771          },
 772         .calTarget_freqbin_2GHT20 = {
 773                 FREQ2FBIN(2412, 1),
 774                 FREQ2FBIN(2437, 1),
 775                 FREQ2FBIN(2472, 1)
 776          },
 777         .calTarget_freqbin_2GHT40 = {
 778                 FREQ2FBIN(2412, 1),
 779                 FREQ2FBIN(2437, 1),
 780                 FREQ2FBIN(2472, 1)
 781          },
 782         .calTargetPowerCck = {
 783                  /* 1L-5L,5S,11L,11S */
 784                  { {34, 34, 34, 34} },
 785                  { {34, 34, 34, 34} },
 786         },
 787         .calTargetPower2G = {
 788                  /* 6-24,36,48,54 */
 789                  { {34, 34, 32, 32} },
 790                  { {34, 34, 32, 32} },
 791                  { {34, 34, 32, 32} },
 792         },
 793         .calTargetPower2GHT20 = {
 794                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 795                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 796                 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
 797         },
 798         .calTargetPower2GHT40 = {
 799                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 800                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 801                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
 802         },
 803         .ctlIndex_2G =  {
 804                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
 805                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
 806         },
 807         .ctl_freqbin_2G = {
 808                 {
 809                         FREQ2FBIN(2412, 1),
 810                         FREQ2FBIN(2417, 1),
 811                         FREQ2FBIN(2457, 1),
 812                         FREQ2FBIN(2462, 1)
 813                 },
 814                 {
 815                         FREQ2FBIN(2412, 1),
 816                         FREQ2FBIN(2417, 1),
 817                         FREQ2FBIN(2462, 1),
 818                         0xFF,
 819                 },
 820
 821                 {
 822                         FREQ2FBIN(2412, 1),
 823                         FREQ2FBIN(2417, 1),
 824                         FREQ2FBIN(2462, 1),
 825                         0xFF,
 826                 },
 827                 {
 828                         FREQ2FBIN(2422, 1),
 829                         FREQ2FBIN(2427, 1),
 830                         FREQ2FBIN(2447, 1),
 831                         FREQ2FBIN(2452, 1)
 832                 },
 833
 834                 {
 835                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 836                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 837                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 838                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
 839                 },
 840
 841                 {
 842                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 843                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 844                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 845                         0,
 846                 },
 847
 848                 {
 849                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 850                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 851                         FREQ2FBIN(2472, 1),
 852                         0,
 853                 },
 854
 855                 {
 856                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 857                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 858                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 859                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 860                 },
 861
 862                 {
 863                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 864                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 865                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 866                 },
 867
 868                 {
 869                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 870                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 871                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 872                         0
 873                 },
 874
 875                 {
 876                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
 877                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
 878                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
 879                         0
 880                 },
 881
 882                 {
 883                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
 884                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
 885                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
 886                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
 887                 }
 888          },
 889         .ctlPowerData_2G = {
 890                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 891                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 892                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
 893
 894                  { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
 895                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 896                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 897
 898                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
 899                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 900                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 901
 902                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
 903                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 904                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
 905          },
 906         .modalHeader5G = {
 907                 /* 4 idle,t1,t2,b (4 bits per setting) */
 908                 .antCtrlCommon = LE32(0x220),
 909                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
 910                 .antCtrlCommon2 = LE32(0x11111),
 911                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
 912                 .antCtrlChain = {
 913                         LE16(0x150), LE16(0x150), LE16(0x150),
 914                 },
 915                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
 916                 .xatten1DB = {0, 0, 0},
 917
 918                 /*
 919                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
 920                  * for merlin (0xa20c/b20c 16:12
 921                  */
 922                 .xatten1Margin = {0, 0, 0},
 923                 .tempSlope = 68,
 924                 .voltSlope = 0,
 925                 /* spurChans spur channels in usual fbin coding format */
 926                 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
 927                 /* noiseFloorThreshCh Check if the register is per chain */
 928                 .noiseFloorThreshCh = {-1, 0, 0},
 929                 .ob = {3, 3, 3}, /* 3 chain */
 930                 .db_stage2 = {3, 3, 3}, /* 3 chain */
 931                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
 932                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
 933                 .xpaBiasLvl = 0xf,
 934                 .txFrameToDataStart = 0x0e,
 935                 .txFrameToPaOn = 0x0e,
 936                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
 937                 .antennaGain = 0,
 938                 .switchSettling = 0x2d,
 939                 .adcDesiredSize = -30,
 940                 .txEndToXpaOff = 0,
 941                 .txEndToRxOn = 0x2,
 942                 .txFrameToXpaOn = 0xe,
 943                 .thresh62 = 28,
 944                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
 945                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
 946                 .futureModal = {
 947                         0, 0, 0, 0, 0, 0, 0, 0,
 948                 },
 949          },
 950         .base_ext2 = {
 951                 .tempSlopeLow = 72,
 952                 .tempSlopeHigh = 105,
 953                 .xatten1DBLow = {0, 0, 0},
 954                 .xatten1MarginLow = {0, 0, 0},
 955                 .xatten1DBHigh = {0, 0, 0},
 956                 .xatten1MarginHigh = {0, 0, 0}
 957          },
 958         .calFreqPier5G = {
 959                 FREQ2FBIN(5180, 0),
 960                 FREQ2FBIN(5240, 0),
 961                 FREQ2FBIN(5320, 0),
 962                 FREQ2FBIN(5400, 0),
 963                 FREQ2FBIN(5500, 0),
 964                 FREQ2FBIN(5600, 0),
 965                 FREQ2FBIN(5745, 0),
 966                 FREQ2FBIN(5785, 0)
 967         },
 968         .calPierData5G = {
 969                         {
 970                                 {0, 0, 0, 0, 0},
 971                                 {0, 0, 0, 0, 0},
 972                                 {0, 0, 0, 0, 0},
 973                                 {0, 0, 0, 0, 0},
 974                                 {0, 0, 0, 0, 0},
 975                                 {0, 0, 0, 0, 0},
 976                                 {0, 0, 0, 0, 0},
 977                                 {0, 0, 0, 0, 0},
 978                         },
 979                         {
 980                                 {0, 0, 0, 0, 0},
 981                                 {0, 0, 0, 0, 0},
 982                                 {0, 0, 0, 0, 0},
 983                                 {0, 0, 0, 0, 0},
 984                                 {0, 0, 0, 0, 0},
 985                                 {0, 0, 0, 0, 0},
 986                                 {0, 0, 0, 0, 0},
 987                                 {0, 0, 0, 0, 0},
 988                         },
 989                         {
 990                                 {0, 0, 0, 0, 0},
 991                                 {0, 0, 0, 0, 0},
 992                                 {0, 0, 0, 0, 0},
 993                                 {0, 0, 0, 0, 0},
 994                                 {0, 0, 0, 0, 0},
 995                                 {0, 0, 0, 0, 0},
 996                                 {0, 0, 0, 0, 0},
 997                                 {0, 0, 0, 0, 0},
 998                         },
 999
1000         },
1001         .calTarget_freqbin_5G = {
1002                 FREQ2FBIN(5180, 0),
1003                 FREQ2FBIN(5220, 0),
1004                 FREQ2FBIN(5320, 0),
1005                 FREQ2FBIN(5400, 0),
1006                 FREQ2FBIN(5500, 0),
1007                 FREQ2FBIN(5600, 0),
1008                 FREQ2FBIN(5745, 0),
1009                 FREQ2FBIN(5785, 0)
1010         },
1011         .calTarget_freqbin_5GHT20 = {
1012                 FREQ2FBIN(5180, 0),
1013                 FREQ2FBIN(5240, 0),
1014                 FREQ2FBIN(5320, 0),
1015                 FREQ2FBIN(5400, 0),
1016                 FREQ2FBIN(5500, 0),
1017                 FREQ2FBIN(5700, 0),
1018                 FREQ2FBIN(5745, 0),
1019                 FREQ2FBIN(5825, 0)
1020         },
1021         .calTarget_freqbin_5GHT40 = {
1022                 FREQ2FBIN(5190, 0),
1023                 FREQ2FBIN(5230, 0),
1024                 FREQ2FBIN(5320, 0),
1025                 FREQ2FBIN(5410, 0),
1026                 FREQ2FBIN(5510, 0),
1027                 FREQ2FBIN(5670, 0),
1028                 FREQ2FBIN(5755, 0),
1029                 FREQ2FBIN(5825, 0)
1030          },
1031         .calTargetPower5G = {
1032                 /* 6-24,36,48,54 */
1033                 { {42, 40, 40, 34} },
1034                 { {42, 40, 40, 34} },
1035                 { {42, 40, 40, 34} },
1036                 { {42, 40, 40, 34} },
1037                 { {42, 40, 40, 34} },
1038                 { {42, 40, 40, 34} },
1039                 { {42, 40, 40, 34} },
1040                 { {42, 40, 40, 34} },
1041          },
1042         .calTargetPower5GHT20 = {
1043                 /*
1044                  * 0_8_16,1-3_9-11_17-19,
1045                  * 4,5,6,7,12,13,14,15,20,21,22,23
1046                  */
1047                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1048                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1049                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1050                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1051                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1052                 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1053                 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1054                 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1055          },
1056         .calTargetPower5GHT40 =  {
1057                 /*
1058                  * 0_8_16,1-3_9-11_17-19,
1059                  * 4,5,6,7,12,13,14,15,20,21,22,23
1060                  */
1061                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1062                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1063                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1064                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1065                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1066                 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1067                 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1068                 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1069          },
1070         .ctlIndex_5G =  {
1071                 0x10, 0x16, 0x18, 0x40, 0x46,
1072                 0x48, 0x30, 0x36, 0x38
1073         },
1074         .ctl_freqbin_5G =  {
1075                 {
1076                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1077                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1078                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1079                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1080                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1081                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1082                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1083                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1084                 },
1085                 {
1086                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1087                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1088                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1089                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1090                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1091                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1092                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1093                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1094                 },
1095
1096                 {
1097                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1098                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1099                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1100                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1101                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1102                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1103                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1104                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1105                 },
1106
1107                 {
1108                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1109                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1110                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1111                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1112                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1113                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1114                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1115                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1116                 },
1117
1118                 {
1119                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1120                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1121                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1122                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1123                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1124                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1125                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1126                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1127                 },
1128
1129                 {
1130                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1131                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1132                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1133                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1134                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1135                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1136                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1137                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1138                 },
1139
1140                 {
1141                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1142                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1143                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1144                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1145                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1146                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1147                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1148                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1149                 },
1150
1151                 {
1152                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1153                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1154                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1155                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1156                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1157                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1158                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1159                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1160                 },
1161
1162                 {
1163                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1164                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1165                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1166                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1167                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1168                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1169                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1170                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1171                 }
1172          },
1173         .ctlPowerData_5G = {
1174                 {
1175                         {
1176                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1177                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1178                         }
1179                 },
1180                 {
1181                         {
1182                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1183                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1184                         }
1185                 },
1186                 {
1187                         {
1188                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1189                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1190                         }
1191                 },
1192                 {
1193                         {
1194                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1195                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1196                         }
1197                 },
1198                 {
1199                         {
1200                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1201                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1202                         }
1203                 },
1204                 {
1205                         {
1206                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1207                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1208                         }
1209                 },
1210                 {
1211                         {
1212                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1213                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1214                         }
1215                 },
1216                 {
1217                         {
1218                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1219                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1220                         }
1221                 },
1222                 {
1223                         {
1224                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1225                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1226                         }
1227                 },
1228          }
1229 };
1230
1231
1232 static const struct ar9300_eeprom ar9300_h112 = {
1233         .eepromVersion = 2,
1234         .templateVersion = 3,
1235         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1236         .custData = {"h112-241-f0000"},
1237         .baseEepHeader = {
1238                 .regDmn = { LE16(0), LE16(0x1f) },
1239                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1240                 .opCapFlags = {
1241                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1242                         .eepMisc = 0,
1243                 },
1244                 .rfSilent = 0,
1245                 .blueToothOptions = 0,
1246                 .deviceCap = 0,
1247                 .deviceType = 5, /* takes lower byte in eeprom location */
1248                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1249                 .params_for_tuning_caps = {0, 0},
1250                 .featureEnable = 0x0d,
1251                 /*
1252                  * bit0 - enable tx temp comp - disabled
1253                  * bit1 - enable tx volt comp - disabled
1254                  * bit2 - enable fastClock - enabled
1255                  * bit3 - enable doubling - enabled
1256                  * bit4 - enable internal regulator - disabled
1257                  * bit5 - enable pa predistortion - disabled
1258                  */
1259                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1260                 .eepromWriteEnableGpio = 6,
1261                 .wlanDisableGpio = 0,
1262                 .wlanLedGpio = 8,
1263                 .rxBandSelectGpio = 0xff,
1264                 .txrxgain = 0x10,
1265                 .swreg = 0,
1266         },
1267         .modalHeader2G = {
1268                 /* ar9300_modal_eep_header  2g */
1269                 /* 4 idle,t1,t2,b(4 bits per setting) */
1270                 .antCtrlCommon = LE32(0x110),
1271                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1272                 .antCtrlCommon2 = LE32(0x44444),
1273
1274                 /*
1275                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1276                  * rx1, rx12, b (2 bits each)
1277                  */
1278                 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1279
1280                 /*
1281                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
1282                  * for ar9280 (0xa20c/b20c 5:0)
1283                  */
1284                 .xatten1DB = {0, 0, 0},
1285
1286                 /*
1287                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1288                  * for ar9280 (0xa20c/b20c 16:12
1289                  */
1290                 .xatten1Margin = {0, 0, 0},
1291                 .tempSlope = 25,
1292                 .voltSlope = 0,
1293
1294                 /*
1295                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1296                  * channels in usual fbin coding format
1297                  */
1298                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1299
1300                 /*
1301                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1302                  * if the register is per chain
1303                  */
1304                 .noiseFloorThreshCh = {-1, 0, 0},
1305                 .ob = {1, 1, 1},/* 3 chain */
1306                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
1307                 .db_stage3 = {0, 0, 0},
1308                 .db_stage4 = {0, 0, 0},
1309                 .xpaBiasLvl = 0,
1310                 .txFrameToDataStart = 0x0e,
1311                 .txFrameToPaOn = 0x0e,
1312                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1313                 .antennaGain = 0,
1314                 .switchSettling = 0x2c,
1315                 .adcDesiredSize = -30,
1316                 .txEndToXpaOff = 0,
1317                 .txEndToRxOn = 0x2,
1318                 .txFrameToXpaOn = 0xe,
1319                 .thresh62 = 28,
1320                 .papdRateMaskHt20 = LE32(0x80c080),
1321                 .papdRateMaskHt40 = LE32(0x80c080),
1322                 .futureModal = {
1323                         0, 0, 0, 0, 0, 0, 0, 0,
1324                 },
1325         },
1326         .base_ext1 = {
1327                 .ant_div_control = 0,
1328                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1329         },
1330         .calFreqPier2G = {
1331                 FREQ2FBIN(2412, 1),
1332                 FREQ2FBIN(2437, 1),
1333                 FREQ2FBIN(2472, 1),
1334         },
1335         /* ar9300_cal_data_per_freq_op_loop 2g */
1336         .calPierData2G = {
1337                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1338                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1339                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1340         },
1341         .calTarget_freqbin_Cck = {
1342                 FREQ2FBIN(2412, 1),
1343                 FREQ2FBIN(2484, 1),
1344         },
1345         .calTarget_freqbin_2G = {
1346                 FREQ2FBIN(2412, 1),
1347                 FREQ2FBIN(2437, 1),
1348                 FREQ2FBIN(2472, 1)
1349         },
1350         .calTarget_freqbin_2GHT20 = {
1351                 FREQ2FBIN(2412, 1),
1352                 FREQ2FBIN(2437, 1),
1353                 FREQ2FBIN(2472, 1)
1354         },
1355         .calTarget_freqbin_2GHT40 = {
1356                 FREQ2FBIN(2412, 1),
1357                 FREQ2FBIN(2437, 1),
1358                 FREQ2FBIN(2472, 1)
1359         },
1360         .calTargetPowerCck = {
1361                 /* 1L-5L,5S,11L,11S */
1362                 { {34, 34, 34, 34} },
1363                 { {34, 34, 34, 34} },
1364         },
1365         .calTargetPower2G = {
1366                 /* 6-24,36,48,54 */
1367                 { {34, 34, 32, 32} },
1368                 { {34, 34, 32, 32} },
1369                 { {34, 34, 32, 32} },
1370         },
1371         .calTargetPower2GHT20 = {
1372                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1373                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1374                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1375         },
1376         .calTargetPower2GHT40 = {
1377                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1378                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1379                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1380         },
1381         .ctlIndex_2G =  {
1382                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1383                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1384         },
1385         .ctl_freqbin_2G = {
1386                 {
1387                         FREQ2FBIN(2412, 1),
1388                         FREQ2FBIN(2417, 1),
1389                         FREQ2FBIN(2457, 1),
1390                         FREQ2FBIN(2462, 1)
1391                 },
1392                 {
1393                         FREQ2FBIN(2412, 1),
1394                         FREQ2FBIN(2417, 1),
1395                         FREQ2FBIN(2462, 1),
1396                         0xFF,
1397                 },
1398
1399                 {
1400                         FREQ2FBIN(2412, 1),
1401                         FREQ2FBIN(2417, 1),
1402                         FREQ2FBIN(2462, 1),
1403                         0xFF,
1404                 },
1405                 {
1406                         FREQ2FBIN(2422, 1),
1407                         FREQ2FBIN(2427, 1),
1408                         FREQ2FBIN(2447, 1),
1409                         FREQ2FBIN(2452, 1)
1410                 },
1411
1412                 {
1413                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1416                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1417                 },
1418
1419                 {
1420                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1421                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1422                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1423                         0,
1424                 },
1425
1426                 {
1427                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1428                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1429                         FREQ2FBIN(2472, 1),
1430                         0,
1431                 },
1432
1433                 {
1434                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1435                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1436                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1437                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1438                 },
1439
1440                 {
1441                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1442                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1443                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1444                 },
1445
1446                 {
1447                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1448                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1449                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1450                         0
1451                 },
1452
1453                 {
1454                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1455                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1456                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1457                         0
1458                 },
1459
1460                 {
1461                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1462                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1463                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1464                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1465                 }
1466         },
1467         .ctlPowerData_2G = {
1468                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1469                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1470                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
1471
1472                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
1473                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1474                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1475
1476                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1477                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1478                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1479
1480                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1481                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1482                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1483         },
1484         .modalHeader5G = {
1485                 /* 4 idle,t1,t2,b (4 bits per setting) */
1486                 .antCtrlCommon = LE32(0x220),
1487                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1488                 .antCtrlCommon2 = LE32(0x44444),
1489                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1490                 .antCtrlChain = {
1491                         LE16(0x150), LE16(0x150), LE16(0x150),
1492                 },
1493                 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1494                 .xatten1DB = {0, 0, 0},
1495
1496                 /*
1497                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1498                  * for merlin (0xa20c/b20c 16:12
1499                  */
1500                 .xatten1Margin = {0, 0, 0},
1501                 .tempSlope = 45,
1502                 .voltSlope = 0,
1503                 /* spurChans spur channels in usual fbin coding format */
1504                 .spurChans = {0, 0, 0, 0, 0},
1505                 /* noiseFloorThreshCh Check if the register is per chain */
1506                 .noiseFloorThreshCh = {-1, 0, 0},
1507                 .ob = {3, 3, 3}, /* 3 chain */
1508                 .db_stage2 = {3, 3, 3}, /* 3 chain */
1509                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
1510                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
1511                 .xpaBiasLvl = 0,
1512                 .txFrameToDataStart = 0x0e,
1513                 .txFrameToPaOn = 0x0e,
1514                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1515                 .antennaGain = 0,
1516                 .switchSettling = 0x2d,
1517                 .adcDesiredSize = -30,
1518                 .txEndToXpaOff = 0,
1519                 .txEndToRxOn = 0x2,
1520                 .txFrameToXpaOn = 0xe,
1521                 .thresh62 = 28,
1522                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1523                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1524                 .futureModal = {
1525                         0, 0, 0, 0, 0, 0, 0, 0,
1526                 },
1527         },
1528         .base_ext2 = {
1529                 .tempSlopeLow = 40,
1530                 .tempSlopeHigh = 50,
1531                 .xatten1DBLow = {0, 0, 0},
1532                 .xatten1MarginLow = {0, 0, 0},
1533                 .xatten1DBHigh = {0, 0, 0},
1534                 .xatten1MarginHigh = {0, 0, 0}
1535         },
1536         .calFreqPier5G = {
1537                 FREQ2FBIN(5180, 0),
1538                 FREQ2FBIN(5220, 0),
1539                 FREQ2FBIN(5320, 0),
1540                 FREQ2FBIN(5400, 0),
1541                 FREQ2FBIN(5500, 0),
1542                 FREQ2FBIN(5600, 0),
1543                 FREQ2FBIN(5700, 0),
1544                 FREQ2FBIN(5825, 0)
1545         },
1546         .calPierData5G = {
1547                 {
1548                         {0, 0, 0, 0, 0},
1549                         {0, 0, 0, 0, 0},
1550                         {0, 0, 0, 0, 0},
1551                         {0, 0, 0, 0, 0},
1552                         {0, 0, 0, 0, 0},
1553                         {0, 0, 0, 0, 0},
1554                         {0, 0, 0, 0, 0},
1555                         {0, 0, 0, 0, 0},
1556                 },
1557                 {
1558                         {0, 0, 0, 0, 0},
1559                         {0, 0, 0, 0, 0},
1560                         {0, 0, 0, 0, 0},
1561                         {0, 0, 0, 0, 0},
1562                         {0, 0, 0, 0, 0},
1563                         {0, 0, 0, 0, 0},
1564                         {0, 0, 0, 0, 0},
1565                         {0, 0, 0, 0, 0},
1566                 },
1567                 {
1568                         {0, 0, 0, 0, 0},
1569                         {0, 0, 0, 0, 0},
1570                         {0, 0, 0, 0, 0},
1571                         {0, 0, 0, 0, 0},
1572                         {0, 0, 0, 0, 0},
1573                         {0, 0, 0, 0, 0},
1574                         {0, 0, 0, 0, 0},
1575                         {0, 0, 0, 0, 0},
1576                 },
1577
1578         },
1579         .calTarget_freqbin_5G = {
1580                 FREQ2FBIN(5180, 0),
1581                 FREQ2FBIN(5240, 0),
1582                 FREQ2FBIN(5320, 0),
1583                 FREQ2FBIN(5400, 0),
1584                 FREQ2FBIN(5500, 0),
1585                 FREQ2FBIN(5600, 0),
1586                 FREQ2FBIN(5700, 0),
1587                 FREQ2FBIN(5825, 0)
1588         },
1589         .calTarget_freqbin_5GHT20 = {
1590                 FREQ2FBIN(5180, 0),
1591                 FREQ2FBIN(5240, 0),
1592                 FREQ2FBIN(5320, 0),
1593                 FREQ2FBIN(5400, 0),
1594                 FREQ2FBIN(5500, 0),
1595                 FREQ2FBIN(5700, 0),
1596                 FREQ2FBIN(5745, 0),
1597                 FREQ2FBIN(5825, 0)
1598         },
1599         .calTarget_freqbin_5GHT40 = {
1600                 FREQ2FBIN(5180, 0),
1601                 FREQ2FBIN(5240, 0),
1602                 FREQ2FBIN(5320, 0),
1603                 FREQ2FBIN(5400, 0),
1604                 FREQ2FBIN(5500, 0),
1605                 FREQ2FBIN(5700, 0),
1606                 FREQ2FBIN(5745, 0),
1607                 FREQ2FBIN(5825, 0)
1608         },
1609         .calTargetPower5G = {
1610                 /* 6-24,36,48,54 */
1611                 { {30, 30, 28, 24} },
1612                 { {30, 30, 28, 24} },
1613                 { {30, 30, 28, 24} },
1614                 { {30, 30, 28, 24} },
1615                 { {30, 30, 28, 24} },
1616                 { {30, 30, 28, 24} },
1617                 { {30, 30, 28, 24} },
1618                 { {30, 30, 28, 24} },
1619         },
1620         .calTargetPower5GHT20 = {
1621                 /*
1622                  * 0_8_16,1-3_9-11_17-19,
1623                  * 4,5,6,7,12,13,14,15,20,21,22,23
1624                  */
1625                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1626                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1627                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1628                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1629                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1630                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1631                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1632                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1633         },
1634         .calTargetPower5GHT40 =  {
1635                 /*
1636                  * 0_8_16,1-3_9-11_17-19,
1637                  * 4,5,6,7,12,13,14,15,20,21,22,23
1638                  */
1639                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1640                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1641                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1642                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1643                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1644                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1645                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1646                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1647         },
1648         .ctlIndex_5G =  {
1649                 0x10, 0x16, 0x18, 0x40, 0x46,
1650                 0x48, 0x30, 0x36, 0x38
1651         },
1652         .ctl_freqbin_5G =  {
1653                 {
1654                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1655                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1656                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1657                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1658                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1659                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1660                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1661                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1662                 },
1663                 {
1664                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1665                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1666                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1667                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1668                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1669                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1670                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1671                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1672                 },
1673
1674                 {
1675                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1676                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1677                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1678                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1679                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1680                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1681                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1682                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1683                 },
1684
1685                 {
1686                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1687                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1688                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1689                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1690                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1691                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1692                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1693                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1694                 },
1695
1696                 {
1697                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1698                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1699                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1700                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1701                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1702                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1703                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1704                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1705                 },
1706
1707                 {
1708                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1709                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1710                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1711                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1712                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1713                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1714                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1715                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
1716                 },
1717
1718                 {
1719                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1720                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1721                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1722                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1723                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1724                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1725                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1726                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1727                 },
1728
1729                 {
1730                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1731                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1732                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1733                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1734                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1735                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1736                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1737                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1738                 },
1739
1740                 {
1741                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1742                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1743                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1744                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1745                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1746                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1747                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1748                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1749                 }
1750         },
1751         .ctlPowerData_5G = {
1752                 {
1753                         {
1754                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1755                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1756                         }
1757                 },
1758                 {
1759                         {
1760                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1761                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1762                         }
1763                 },
1764                 {
1765                         {
1766                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1767                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1768                         }
1769                 },
1770                 {
1771                         {
1772                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1773                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1774                         }
1775                 },
1776                 {
1777                         {
1778                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1779                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1780                         }
1781                 },
1782                 {
1783                         {
1784                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1785                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
1786                         }
1787                 },
1788                 {
1789                         {
1790                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1791                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1792                         }
1793                 },
1794                 {
1795                         {
1796                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1797                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1798                         }
1799                 },
1800                 {
1801                         {
1802                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1803                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1804                         }
1805                 },
1806         }
1807 };
1808
1809
1810 static const struct ar9300_eeprom ar9300_x112 = {
1811         .eepromVersion = 2,
1812         .templateVersion = 5,
1813         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1814         .custData = {"x112-041-f0000"},
1815         .baseEepHeader = {
1816                 .regDmn = { LE16(0), LE16(0x1f) },
1817                 .txrxMask =  0x77, /* 4 bits tx and 4 bits rx */
1818                 .opCapFlags = {
1819                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
1820                         .eepMisc = 0,
1821                 },
1822                 .rfSilent = 0,
1823                 .blueToothOptions = 0,
1824                 .deviceCap = 0,
1825                 .deviceType = 5, /* takes lower byte in eeprom location */
1826                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1827                 .params_for_tuning_caps = {0, 0},
1828                 .featureEnable = 0x0d,
1829                 /*
1830                  * bit0 - enable tx temp comp - disabled
1831                  * bit1 - enable tx volt comp - disabled
1832                  * bit2 - enable fastclock - enabled
1833                  * bit3 - enable doubling - enabled
1834                  * bit4 - enable internal regulator - disabled
1835                  * bit5 - enable pa predistortion - disabled
1836                  */
1837                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1838                 .eepromWriteEnableGpio = 6,
1839                 .wlanDisableGpio = 0,
1840                 .wlanLedGpio = 8,
1841                 .rxBandSelectGpio = 0xff,
1842                 .txrxgain = 0x0,
1843                 .swreg = 0,
1844         },
1845         .modalHeader2G = {
1846                 /* ar9300_modal_eep_header  2g */
1847                 /* 4 idle,t1,t2,b(4 bits per setting) */
1848                 .antCtrlCommon = LE32(0x110),
1849                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1850                 .antCtrlCommon2 = LE32(0x22222),
1851
1852                 /*
1853                  * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1854                  * rx1, rx12, b (2 bits each)
1855                  */
1856                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1857
1858                 /*
1859                  * xatten1DB[AR9300_max_chains];  3 xatten1_db
1860                  * for ar9280 (0xa20c/b20c 5:0)
1861                  */
1862                 .xatten1DB = {0x1b, 0x1b, 0x1b},
1863
1864                 /*
1865                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1866                  * for ar9280 (0xa20c/b20c 16:12
1867                  */
1868                 .xatten1Margin = {0x15, 0x15, 0x15},
1869                 .tempSlope = 50,
1870                 .voltSlope = 0,
1871
1872                 /*
1873                  * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1874                  * channels in usual fbin coding format
1875                  */
1876                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1877
1878                 /*
1879                  * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1880                  * if the register is per chain
1881                  */
1882                 .noiseFloorThreshCh = {-1, 0, 0},
1883                 .ob = {1, 1, 1},/* 3 chain */
1884                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
1885                 .db_stage3 = {0, 0, 0},
1886                 .db_stage4 = {0, 0, 0},
1887                 .xpaBiasLvl = 0,
1888                 .txFrameToDataStart = 0x0e,
1889                 .txFrameToPaOn = 0x0e,
1890                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1891                 .antennaGain = 0,
1892                 .switchSettling = 0x2c,
1893                 .adcDesiredSize = -30,
1894                 .txEndToXpaOff = 0,
1895                 .txEndToRxOn = 0x2,
1896                 .txFrameToXpaOn = 0xe,
1897                 .thresh62 = 28,
1898                 .papdRateMaskHt20 = LE32(0x0c80c080),
1899                 .papdRateMaskHt40 = LE32(0x0080c080),
1900                 .futureModal = {
1901                         0, 0, 0, 0, 0, 0, 0, 0,
1902                 },
1903         },
1904         .base_ext1 = {
1905                 .ant_div_control = 0,
1906                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
1907         },
1908         .calFreqPier2G = {
1909                 FREQ2FBIN(2412, 1),
1910                 FREQ2FBIN(2437, 1),
1911                 FREQ2FBIN(2472, 1),
1912         },
1913         /* ar9300_cal_data_per_freq_op_loop 2g */
1914         .calPierData2G = {
1915                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1916                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1917                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1918         },
1919         .calTarget_freqbin_Cck = {
1920                 FREQ2FBIN(2412, 1),
1921                 FREQ2FBIN(2472, 1),
1922         },
1923         .calTarget_freqbin_2G = {
1924                 FREQ2FBIN(2412, 1),
1925                 FREQ2FBIN(2437, 1),
1926                 FREQ2FBIN(2472, 1)
1927         },
1928         .calTarget_freqbin_2GHT20 = {
1929                 FREQ2FBIN(2412, 1),
1930                 FREQ2FBIN(2437, 1),
1931                 FREQ2FBIN(2472, 1)
1932         },
1933         .calTarget_freqbin_2GHT40 = {
1934                 FREQ2FBIN(2412, 1),
1935                 FREQ2FBIN(2437, 1),
1936                 FREQ2FBIN(2472, 1)
1937         },
1938         .calTargetPowerCck = {
1939                 /* 1L-5L,5S,11L,11s */
1940                 { {38, 38, 38, 38} },
1941                 { {38, 38, 38, 38} },
1942         },
1943         .calTargetPower2G = {
1944                 /* 6-24,36,48,54 */
1945                 { {38, 38, 36, 34} },
1946                 { {38, 38, 36, 34} },
1947                 { {38, 38, 34, 32} },
1948         },
1949         .calTargetPower2GHT20 = {
1950                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1951                 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1952                 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1953         },
1954         .calTargetPower2GHT40 = {
1955                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1956                 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1957                 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1958         },
1959         .ctlIndex_2G =  {
1960                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1961                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1962         },
1963         .ctl_freqbin_2G = {
1964                 {
1965                         FREQ2FBIN(2412, 1),
1966                         FREQ2FBIN(2417, 1),
1967                         FREQ2FBIN(2457, 1),
1968                         FREQ2FBIN(2462, 1)
1969                 },
1970                 {
1971                         FREQ2FBIN(2412, 1),
1972                         FREQ2FBIN(2417, 1),
1973                         FREQ2FBIN(2462, 1),
1974                         0xFF,
1975                 },
1976
1977                 {
1978                         FREQ2FBIN(2412, 1),
1979                         FREQ2FBIN(2417, 1),
1980                         FREQ2FBIN(2462, 1),
1981                         0xFF,
1982                 },
1983                 {
1984                         FREQ2FBIN(2422, 1),
1985                         FREQ2FBIN(2427, 1),
1986                         FREQ2FBIN(2447, 1),
1987                         FREQ2FBIN(2452, 1)
1988                 },
1989
1990                 {
1991                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1992                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1993                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1994                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1995                 },
1996
1997                 {
1998                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1999                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2000                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2001                         0,
2002                 },
2003
2004                 {
2005                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2006                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2007                         FREQ2FBIN(2472, 1),
2008                         0,
2009                 },
2010
2011                 {
2012                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2013                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2014                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2015                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2016                 },
2017
2018                 {
2019                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2020                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2021                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2022                 },
2023
2024                 {
2025                         /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2026                         /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2027                         /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2028                         0
2029                 },
2030
2031                 {
2032                         /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
2033                         /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
2034                         /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
2035                         0
2036                 },
2037
2038                 {
2039                         /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
2040                         /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
2041                         /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
2042                         /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
2043                 }
2044         },
2045         .ctlPowerData_2G = {
2046                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2047                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2048                 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2049
2050                 { { CTL(60, 1), CTL(60, 0), CTL(0, 0), CTL(0, 0) } },
2051                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2052                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2053
2054                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2055                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2056                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2057
2058                 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2059                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2060                 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2061         },
2062         .modalHeader5G = {
2063                 /* 4 idle,t1,t2,b (4 bits per setting) */
2064                 .antCtrlCommon = LE32(0x110),
2065                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2066                 .antCtrlCommon2 = LE32(0x22222),
2067                 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2068                 .antCtrlChain = {
2069                         LE16(0x0), LE16(0x0), LE16(0x0),
2070                 },
2071                 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2072                 .xatten1DB = {0x13, 0x19, 0x17},
2073
2074                 /*
2075                  * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2076                  * for merlin (0xa20c/b20c 16:12
2077                  */
2078                 .xatten1Margin = {0x19, 0x19, 0x19},
2079                 .tempSlope = 70,
2080                 .voltSlope = 15,
2081                 /* spurChans spur channels in usual fbin coding format */
2082                 .spurChans = {0, 0, 0, 0, 0},
2083                 /* noiseFloorThreshch check if the register is per chain */
2084                 .noiseFloorThreshCh = {-1, 0, 0},
2085                 .ob = {3, 3, 3}, /* 3 chain */
2086                 .db_stage2 = {3, 3, 3}, /* 3 chain */
2087                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2088                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
2089                 .xpaBiasLvl = 0,
2090                 .txFrameToDataStart = 0x0e,
2091                 .txFrameToPaOn = 0x0e,
2092                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2093                 .antennaGain = 0,
2094                 .switchSettling = 0x2d,
2095                 .adcDesiredSize = -30,
2096                 .txEndToXpaOff = 0,
2097                 .txEndToRxOn = 0x2,
2098                 .txFrameToXpaOn = 0xe,
2099                 .thresh62 = 28,
2100                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2101                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2102                 .futureModal = {
2103                         0, 0, 0, 0, 0, 0, 0, 0,
2104                 },
2105         },
2106         .base_ext2 = {
2107                 .tempSlopeLow = 72,
2108                 .tempSlopeHigh = 105,
2109                 .xatten1DBLow = {0x10, 0x14, 0x10},
2110                 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2111                 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2112                 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2113         },
2114         .calFreqPier5G = {
2115                 FREQ2FBIN(5180, 0),
2116                 FREQ2FBIN(5220, 0),
2117                 FREQ2FBIN(5320, 0),
2118                 FREQ2FBIN(5400, 0),
2119                 FREQ2FBIN(5500, 0),
2120                 FREQ2FBIN(5600, 0),
2121                 FREQ2FBIN(5700, 0),
2122                 FREQ2FBIN(5785, 0)
2123         },
2124         .calPierData5G = {
2125                 {
2126                         {0, 0, 0, 0, 0},
2127                         {0, 0, 0, 0, 0},
2128                         {0, 0, 0, 0, 0},
2129                         {0, 0, 0, 0, 0},
2130                         {0, 0, 0, 0, 0},
2131                         {0, 0, 0, 0, 0},
2132                         {0, 0, 0, 0, 0},
2133                         {0, 0, 0, 0, 0},
2134                 },
2135                 {
2136                         {0, 0, 0, 0, 0},
2137                         {0, 0, 0, 0, 0},
2138                         {0, 0, 0, 0, 0},
2139                         {0, 0, 0, 0, 0},
2140                         {0, 0, 0, 0, 0},
2141                         {0, 0, 0, 0, 0},
2142                         {0, 0, 0, 0, 0},
2143                         {0, 0, 0, 0, 0},
2144                 },
2145                 {
2146                         {0, 0, 0, 0, 0},
2147                         {0, 0, 0, 0, 0},
2148                         {0, 0, 0, 0, 0},
2149                         {0, 0, 0, 0, 0},
2150                         {0, 0, 0, 0, 0},
2151                         {0, 0, 0, 0, 0},
2152                         {0, 0, 0, 0, 0},
2153                         {0, 0, 0, 0, 0},
2154                 },
2155
2156         },
2157         .calTarget_freqbin_5G = {
2158                 FREQ2FBIN(5180, 0),
2159                 FREQ2FBIN(5220, 0),
2160                 FREQ2FBIN(5320, 0),
2161                 FREQ2FBIN(5400, 0),
2162                 FREQ2FBIN(5500, 0),
2163                 FREQ2FBIN(5600, 0),
2164                 FREQ2FBIN(5725, 0),
2165                 FREQ2FBIN(5825, 0)
2166         },
2167         .calTarget_freqbin_5GHT20 = {
2168                 FREQ2FBIN(5180, 0),
2169                 FREQ2FBIN(5220, 0),
2170                 FREQ2FBIN(5320, 0),
2171                 FREQ2FBIN(5400, 0),
2172                 FREQ2FBIN(5500, 0),
2173                 FREQ2FBIN(5600, 0),
2174                 FREQ2FBIN(5725, 0),
2175                 FREQ2FBIN(5825, 0)
2176         },
2177         .calTarget_freqbin_5GHT40 = {
2178                 FREQ2FBIN(5180, 0),
2179                 FREQ2FBIN(5220, 0),
2180                 FREQ2FBIN(5320, 0),
2181                 FREQ2FBIN(5400, 0),
2182                 FREQ2FBIN(5500, 0),
2183                 FREQ2FBIN(5600, 0),
2184                 FREQ2FBIN(5725, 0),
2185                 FREQ2FBIN(5825, 0)
2186         },
2187         .calTargetPower5G = {
2188                 /* 6-24,36,48,54 */
2189                 { {32, 32, 28, 26} },
2190                 { {32, 32, 28, 26} },
2191                 { {32, 32, 28, 26} },
2192                 { {32, 32, 26, 24} },
2193                 { {32, 32, 26, 24} },
2194                 { {32, 32, 24, 22} },
2195                 { {30, 30, 24, 22} },
2196                 { {30, 30, 24, 22} },
2197         },
2198         .calTargetPower5GHT20 = {
2199                 /*
2200                  * 0_8_16,1-3_9-11_17-19,
2201                  * 4,5,6,7,12,13,14,15,20,21,22,23
2202                  */
2203                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2204                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2205                 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2206                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2207                 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2208                 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2209                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2210                 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2211         },
2212         .calTargetPower5GHT40 =  {
2213                 /*
2214                  * 0_8_16,1-3_9-11_17-19,
2215                  * 4,5,6,7,12,13,14,15,20,21,22,23
2216                  */
2217                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2218                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2219                 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2220                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2221                 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2222                 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2223                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2224                 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2225         },
2226         .ctlIndex_5G =  {
2227                 0x10, 0x16, 0x18, 0x40, 0x46,
2228                 0x48, 0x30, 0x36, 0x38
2229         },
2230         .ctl_freqbin_5G =  {
2231                 {
2232                         /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2233                         /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2234                         /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2235                         /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2236                         /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2237                         /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2238                         /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2239                         /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2240                 },
2241                 {
2242                         /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2243                         /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2244                         /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2245                         /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2246                         /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2247                         /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2248                         /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2249                         /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2250                 },
2251
2252                 {
2253                         /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2254                         /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2255                         /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2256                         /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2257                         /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2258                         /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2259                         /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2260                         /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2261                 },
2262
2263                 {
2264                         /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2265                         /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2266                         /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2267                         /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2268                         /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2269                         /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2270                         /* Data[3].ctledges[6].bchannel */ 0xFF,
2271                         /* Data[3].ctledges[7].bchannel */ 0xFF,
2272                 },
2273
2274                 {
2275                         /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2276                         /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2277                         /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2278                         /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2279                         /* Data[4].ctledges[4].bchannel */ 0xFF,
2280                         /* Data[4].ctledges[5].bchannel */ 0xFF,
2281                         /* Data[4].ctledges[6].bchannel */ 0xFF,
2282                         /* Data[4].ctledges[7].bchannel */ 0xFF,
2283                 },
2284
2285                 {
2286                         /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2287                         /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2288                         /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2289                         /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2290                         /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2291                         /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2292                         /* Data[5].ctledges[6].bchannel */ 0xFF,
2293                         /* Data[5].ctledges[7].bchannel */ 0xFF
2294                 },
2295
2296                 {
2297                         /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2298                         /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2299                         /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2300                         /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2301                         /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2302                         /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2303                         /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2304                         /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2305                 },
2306
2307                 {
2308                         /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2309                         /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2310                         /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2311                         /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2312                         /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2313                         /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2314                         /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2315                         /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2316                 },
2317
2318                 {
2319                         /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2320                         /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2321                         /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2322                         /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2323                         /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2324                         /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2325                         /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2326                         /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2327                 }
2328         },
2329         .ctlPowerData_5G = {
2330                 {
2331                         {
2332                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2333                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2334                         }
2335                 },
2336                 {
2337                         {
2338                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2339                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2340                         }
2341                 },
2342                 {
2343                         {
2344                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2345                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2346                         }
2347                 },
2348                 {
2349                         {
2350                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2351                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2352                         }
2353                 },
2354                 {
2355                         {
2356                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2357                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2358                         }
2359                 },
2360                 {
2361                         {
2362                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2363                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2364                         }
2365                 },
2366                 {
2367                         {
2368                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2369                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2370                         }
2371                 },
2372                 {
2373                         {
2374                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2375                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2376                         }
2377                 },
2378                 {
2379                         {
2380                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2381                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2382                         }
2383                 },
2384         }
2385 };
2386
2387 static const struct ar9300_eeprom ar9300_h116 = {
2388         .eepromVersion = 2,
2389         .templateVersion = 4,
2390         .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2391         .custData = {"h116-041-f0000"},
2392         .baseEepHeader = {
2393                 .regDmn = { LE16(0), LE16(0x1f) },
2394                 .txrxMask =  0x33, /* 4 bits tx and 4 bits rx */
2395                 .opCapFlags = {
2396                         .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
2397                         .eepMisc = 0,
2398                 },
2399                 .rfSilent = 0,
2400                 .blueToothOptions = 0,
2401                 .deviceCap = 0,
2402                 .deviceType = 5, /* takes lower byte in eeprom location */
2403                 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2404                 .params_for_tuning_caps = {0, 0},
2405                 .featureEnable = 0x0d,
2406                  /*
2407                   * bit0 - enable tx temp comp - disabled
2408                   * bit1 - enable tx volt comp - disabled
2409                   * bit2 - enable fastClock - enabled
2410                   * bit3 - enable doubling - enabled
2411                   * bit4 - enable internal regulator - disabled
2412                   * bit5 - enable pa predistortion - disabled
2413                   */
2414                 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2415                 .eepromWriteEnableGpio = 6,
2416                 .wlanDisableGpio = 0,
2417                 .wlanLedGpio = 8,
2418                 .rxBandSelectGpio = 0xff,
2419                 .txrxgain = 0x10,
2420                 .swreg = 0,
2421          },
2422         .modalHeader2G = {
2423         /* ar9300_modal_eep_header  2g */
2424                 /* 4 idle,t1,t2,b(4 bits per setting) */
2425                 .antCtrlCommon = LE32(0x110),
2426                 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2427                 .antCtrlCommon2 = LE32(0x44444),
2428
2429                 /*
2430                  * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2431                  * rx1, rx12, b (2 bits each)
2432                  */
2433                 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2434
2435                 /*
2436                  * xatten1DB[AR9300_MAX_CHAINS];  3 xatten1_db
2437                  * for ar9280 (0xa20c/b20c 5:0)
2438                  */
2439                 .xatten1DB = {0x1f, 0x1f, 0x1f},
2440
2441                 /*
2442                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2443                  * for ar9280 (0xa20c/b20c 16:12
2444                  */
2445                 .xatten1Margin = {0x12, 0x12, 0x12},
2446                 .tempSlope = 25,
2447                 .voltSlope = 0,
2448
2449                 /*
2450                  * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2451                  * channels in usual fbin coding format
2452                  */
2453                 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2454
2455                 /*
2456                  * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2457                  * if the register is per chain
2458                  */
2459                 .noiseFloorThreshCh = {-1, 0, 0},
2460                 .ob = {1, 1, 1},/* 3 chain */
2461                 .db_stage2 = {1, 1, 1}, /* 3 chain  */
2462                 .db_stage3 = {0, 0, 0},
2463                 .db_stage4 = {0, 0, 0},
2464                 .xpaBiasLvl = 0,
2465                 .txFrameToDataStart = 0x0e,
2466                 .txFrameToPaOn = 0x0e,
2467                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2468                 .antennaGain = 0,
2469                 .switchSettling = 0x2c,
2470                 .adcDesiredSize = -30,
2471                 .txEndToXpaOff = 0,
2472                 .txEndToRxOn = 0x2,
2473                 .txFrameToXpaOn = 0xe,
2474                 .thresh62 = 28,
2475                 .papdRateMaskHt20 = LE32(0x0c80C080),
2476                 .papdRateMaskHt40 = LE32(0x0080C080),
2477                 .futureModal = {
2478                         0, 0, 0, 0, 0, 0, 0, 0,
2479                 },
2480          },
2481          .base_ext1 = {
2482                 .ant_div_control = 0,
2483                 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
2484          },
2485         .calFreqPier2G = {
2486                 FREQ2FBIN(2412, 1),
2487                 FREQ2FBIN(2437, 1),
2488                 FREQ2FBIN(2472, 1),
2489          },
2490         /* ar9300_cal_data_per_freq_op_loop 2g */
2491         .calPierData2G = {
2492                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2493                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2494                 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2495          },
2496         .calTarget_freqbin_Cck = {
2497                 FREQ2FBIN(2412, 1),
2498                 FREQ2FBIN(2472, 1),
2499          },
2500         .calTarget_freqbin_2G = {
2501                 FREQ2FBIN(2412, 1),
2502                 FREQ2FBIN(2437, 1),
2503                 FREQ2FBIN(2472, 1)
2504          },
2505         .calTarget_freqbin_2GHT20 = {
2506                 FREQ2FBIN(2412, 1),
2507                 FREQ2FBIN(2437, 1),
2508                 FREQ2FBIN(2472, 1)
2509          },
2510         .calTarget_freqbin_2GHT40 = {
2511                 FREQ2FBIN(2412, 1),
2512                 FREQ2FBIN(2437, 1),
2513                 FREQ2FBIN(2472, 1)
2514          },
2515         .calTargetPowerCck = {
2516                  /* 1L-5L,5S,11L,11S */
2517                  { {34, 34, 34, 34} },
2518                  { {34, 34, 34, 34} },
2519         },
2520         .calTargetPower2G = {
2521                  /* 6-24,36,48,54 */
2522                  { {34, 34, 32, 32} },
2523                  { {34, 34, 32, 32} },
2524                  { {34, 34, 32, 32} },
2525         },
2526         .calTargetPower2GHT20 = {
2527                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2528                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2529                 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2530         },
2531         .calTargetPower2GHT40 = {
2532                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2533                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2534                 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2535         },
2536         .ctlIndex_2G =  {
2537                 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2538                 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2539         },
2540         .ctl_freqbin_2G = {
2541                 {
2542                         FREQ2FBIN(2412, 1),
2543                         FREQ2FBIN(2417, 1),
2544                         FREQ2FBIN(2457, 1),
2545                         FREQ2FBIN(2462, 1)
2546                 },
2547                 {
2548                         FREQ2FBIN(2412, 1),
2549                         FREQ2FBIN(2417, 1),
2550                         FREQ2FBIN(2462, 1),
2551                         0xFF,
2552                 },
2553
2554                 {
2555                         FREQ2FBIN(2412, 1),
2556                         FREQ2FBIN(2417, 1),
2557                         FREQ2FBIN(2462, 1),
2558                         0xFF,
2559                 },
2560                 {
2561                         FREQ2FBIN(2422, 1),
2562                         FREQ2FBIN(2427, 1),
2563                         FREQ2FBIN(2447, 1),
2564                         FREQ2FBIN(2452, 1)
2565                 },
2566
2567                 {
2568                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2569                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2570                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2571                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2572                 },
2573
2574                 {
2575                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2576                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2577                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2578                         0,
2579                 },
2580
2581                 {
2582                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2583                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2584                         FREQ2FBIN(2472, 1),
2585                         0,
2586                 },
2587
2588                 {
2589                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2590                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2591                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2592                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2593                 },
2594
2595                 {
2596                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2597                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2598                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2599                 },
2600
2601                 {
2602                         /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2603                         /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2604                         /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2605                         0
2606                 },
2607
2608                 {
2609                         /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2610                         /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2611                         /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2612                         0
2613                 },
2614
2615                 {
2616                         /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2617                         /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2618                         /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2619                         /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2620                 }
2621          },
2622         .ctlPowerData_2G = {
2623                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2624                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2625                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
2626
2627                  { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
2628                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2629                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2630
2631                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2632                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2633                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2634
2635                  { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2636                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2637                  { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2638          },
2639         .modalHeader5G = {
2640                 /* 4 idle,t1,t2,b (4 bits per setting) */
2641                 .antCtrlCommon = LE32(0x220),
2642                 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2643                 .antCtrlCommon2 = LE32(0x44444),
2644                  /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2645                 .antCtrlChain = {
2646                         LE16(0x150), LE16(0x150), LE16(0x150),
2647                 },
2648                  /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2649                 .xatten1DB = {0x19, 0x19, 0x19},
2650
2651                 /*
2652                  * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2653                  * for merlin (0xa20c/b20c 16:12
2654                  */
2655                 .xatten1Margin = {0x14, 0x14, 0x14},
2656                 .tempSlope = 70,
2657                 .voltSlope = 0,
2658                 /* spurChans spur channels in usual fbin coding format */
2659                 .spurChans = {0, 0, 0, 0, 0},
2660                 /* noiseFloorThreshCh Check if the register is per chain */
2661                 .noiseFloorThreshCh = {-1, 0, 0},
2662                 .ob = {3, 3, 3}, /* 3 chain */
2663                 .db_stage2 = {3, 3, 3}, /* 3 chain */
2664                 .db_stage3 = {3, 3, 3}, /* doesn't exist for 2G */
2665                 .db_stage4 = {3, 3, 3},  /* don't exist for 2G */
2666                 .xpaBiasLvl = 0,
2667                 .txFrameToDataStart = 0x0e,
2668                 .txFrameToPaOn = 0x0e,
2669                 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2670                 .antennaGain = 0,
2671                 .switchSettling = 0x2d,
2672                 .adcDesiredSize = -30,
2673                 .txEndToXpaOff = 0,
2674                 .txEndToRxOn = 0x2,
2675                 .txFrameToXpaOn = 0xe,
2676                 .thresh62 = 28,
2677                 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2678                 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2679                 .futureModal = {
2680                         0, 0, 0, 0, 0, 0, 0, 0,
2681                 },
2682          },
2683         .base_ext2 = {
2684                 .tempSlopeLow = 35,
2685                 .tempSlopeHigh = 50,
2686                 .xatten1DBLow = {0, 0, 0},
2687                 .xatten1MarginLow = {0, 0, 0},
2688                 .xatten1DBHigh = {0, 0, 0},
2689                 .xatten1MarginHigh = {0, 0, 0}
2690          },
2691         .calFreqPier5G = {
2692                 FREQ2FBIN(5180, 0),
2693                 FREQ2FBIN(5220, 0),
2694                 FREQ2FBIN(5320, 0),
2695                 FREQ2FBIN(5400, 0),
2696                 FREQ2FBIN(5500, 0),
2697                 FREQ2FBIN(5600, 0),
2698                 FREQ2FBIN(5700, 0),
2699                 FREQ2FBIN(5785, 0)
2700         },
2701         .calPierData5G = {
2702                         {
2703                                 {0, 0, 0, 0, 0},
2704                                 {0, 0, 0, 0, 0},
2705                                 {0, 0, 0, 0, 0},
2706                                 {0, 0, 0, 0, 0},
2707                                 {0, 0, 0, 0, 0},
2708                                 {0, 0, 0, 0, 0},
2709                                 {0, 0, 0, 0, 0},
2710                                 {0, 0, 0, 0, 0},
2711                         },
2712                         {
2713                                 {0, 0, 0, 0, 0},
2714                                 {0, 0, 0, 0, 0},
2715                                 {0, 0, 0, 0, 0},
2716                                 {0, 0, 0, 0, 0},
2717                                 {0, 0, 0, 0, 0},
2718                                 {0, 0, 0, 0, 0},
2719                                 {0, 0, 0, 0, 0},
2720                                 {0, 0, 0, 0, 0},
2721                         },
2722                         {
2723                                 {0, 0, 0, 0, 0},
2724                                 {0, 0, 0, 0, 0},
2725                                 {0, 0, 0, 0, 0},
2726                                 {0, 0, 0, 0, 0},
2727                                 {0, 0, 0, 0, 0},
2728                                 {0, 0, 0, 0, 0},
2729                                 {0, 0, 0, 0, 0},
2730                                 {0, 0, 0, 0, 0},
2731                         },
2732
2733         },
2734         .calTarget_freqbin_5G = {
2735                 FREQ2FBIN(5180, 0),
2736                 FREQ2FBIN(5240, 0),
2737                 FREQ2FBIN(5320, 0),
2738                 FREQ2FBIN(5400, 0),
2739                 FREQ2FBIN(5500, 0),
2740                 FREQ2FBIN(5600, 0),
2741                 FREQ2FBIN(5700, 0),
2742                 FREQ2FBIN(5825, 0)
2743         },
2744         .calTarget_freqbin_5GHT20 = {
2745                 FREQ2FBIN(5180, 0),
2746                 FREQ2FBIN(5240, 0),
2747                 FREQ2FBIN(5320, 0),
2748                 FREQ2FBIN(5400, 0),
2749                 FREQ2FBIN(5500, 0),
2750                 FREQ2FBIN(5700, 0),
2751                 FREQ2FBIN(5745, 0),
2752                 FREQ2FBIN(5825, 0)
2753         },
2754         .calTarget_freqbin_5GHT40 = {
2755                 FREQ2FBIN(5180, 0),
2756                 FREQ2FBIN(5240, 0),
2757                 FREQ2FBIN(5320, 0),
2758                 FREQ2FBIN(5400, 0),
2759                 FREQ2FBIN(5500, 0),
2760                 FREQ2FBIN(5700, 0),
2761                 FREQ2FBIN(5745, 0),
2762                 FREQ2FBIN(5825, 0)
2763          },
2764         .calTargetPower5G = {
2765                 /* 6-24,36,48,54 */
2766                 { {30, 30, 28, 24} },
2767                 { {30, 30, 28, 24} },
2768                 { {30, 30, 28, 24} },
2769                 { {30, 30, 28, 24} },
2770                 { {30, 30, 28, 24} },
2771                 { {30, 30, 28, 24} },
2772                 { {30, 30, 28, 24} },
2773                 { {30, 30, 28, 24} },
2774          },
2775         .calTargetPower5GHT20 = {
2776                 /*
2777                  * 0_8_16,1-3_9-11_17-19,
2778                  * 4,5,6,7,12,13,14,15,20,21,22,23
2779                  */
2780                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2781                 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2782                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2783                 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2784                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2785                 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2786                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2787                 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2788          },
2789         .calTargetPower5GHT40 =  {
2790                 /*
2791                  * 0_8_16,1-3_9-11_17-19,
2792                  * 4,5,6,7,12,13,14,15,20,21,22,23
2793                  */
2794                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2795                 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2796                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2797                 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2798                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2799                 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2800                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2801                 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2802          },
2803         .ctlIndex_5G =  {
2804                 0x10, 0x16, 0x18, 0x40, 0x46,
2805                 0x48, 0x30, 0x36, 0x38
2806         },
2807         .ctl_freqbin_5G =  {
2808                 {
2809                         /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2810                         /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2811                         /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2812                         /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2813                         /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2814                         /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2815                         /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2816                         /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2817                 },
2818                 {
2819                         /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2820                         /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2821                         /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2822                         /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2823                         /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2824                         /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2825                         /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2826                         /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2827                 },
2828
2829                 {
2830                         /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2831                         /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2832                         /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2833                         /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2834                         /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2835                         /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2836                         /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2837                         /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2838                 },
2839
2840                 {
2841                         /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2842                         /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2843                         /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2844                         /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2845                         /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2846                         /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2847                         /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2848                         /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2849                 },
2850
2851                 {
2852                         /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2853                         /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2854                         /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2855                         /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2856                         /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2857                         /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2858                         /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2859                         /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2860                 },
2861
2862                 {
2863                         /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2864                         /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2865                         /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2866                         /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2867                         /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2868                         /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2869                         /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2870                         /* Data[5].ctlEdges[7].bChannel */ 0xFF
2871                 },
2872
2873                 {
2874                         /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2875                         /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2876                         /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2877                         /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2878                         /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2879                         /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2880                         /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2881                         /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2882                 },
2883
2884                 {
2885                         /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2886                         /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2887                         /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2888                         /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2889                         /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2890                         /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2891                         /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2892                         /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2893                 },
2894
2895                 {
2896                         /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2897                         /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2898                         /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2899                         /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2900                         /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2901                         /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2902                         /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2903                         /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2904                 }
2905          },
2906         .ctlPowerData_5G = {
2907                 {
2908                         {
2909                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2910                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2911                         }
2912                 },
2913                 {
2914                         {
2915                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2916                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2917                         }
2918                 },
2919                 {
2920                         {
2921                                 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2922                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2923                         }
2924                 },
2925                 {
2926                         {
2927                                 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2928                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2929                         }
2930                 },
2931                 {
2932                         {
2933                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2934                                 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2935                         }
2936                 },
2937                 {
2938                         {
2939                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2940                                 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
2941                         }
2942                 },
2943                 {
2944                         {
2945                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2946                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2947                         }
2948                 },
2949                 {
2950                         {
2951                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2952                                 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2953                         }
2954                 },
2955                 {
2956                         {
2957                                 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2958                                 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2959                         }
2960                 },
2961          }
2962 };
2963
2964
2965 static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2966         &ar9300_default,
2967         &ar9300_x112,
2968         &ar9300_h116,
2969         &ar9300_h112,
2970         &ar9300_x113,
2971 };
2972
2973 static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2974 {
2975 #define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2976         int it;
2977
2978         for (it = 0; it < N_LOOP; it++)
2979                 if (ar9300_eep_templates[it]->templateVersion == id)
2980                         return ar9300_eep_templates[it];
2981         return NULL;
2982 #undef N_LOOP
2983 }
2984
2985
2986 static u16 ath9k_hw_fbin2freq(u8 fbin, bool is2GHz)
2987 {
2988         if (fbin == AR5416_BCHAN_UNUSED)
2989                 return fbin;
2990
2991         return (u16) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
2992 }
2993
2994 static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2995 {
2996         return 0;
2997 }
2998
2999 static int interpolate(int x, int xa, int xb, int ya, int yb)
3000 {
3001         int bf, factor, plus;
3002
3003         bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
3004         factor = bf / 2;
3005         plus = bf % 2;
3006         return ya + factor + plus;
3007 }
3008
3009 static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
3010                                       enum eeprom_param param)
3011 {
3012         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3013         struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
3014
3015         switch (param) {
3016         case EEP_MAC_LSW:
3017                 return get_unaligned_be16(eep->macAddr);
3018         case EEP_MAC_MID:
3019                 return get_unaligned_be16(eep->macAddr + 2);
3020         case EEP_MAC_MSW:
3021                 return get_unaligned_be16(eep->macAddr + 4);
3022         case EEP_REG_0:
3023                 return le16_to_cpu(pBase->regDmn[0]);
3024         case EEP_REG_1:
3025                 return le16_to_cpu(pBase->regDmn[1]);
3026         case EEP_OP_CAP:
3027                 return pBase->deviceCap;
3028         case EEP_OP_MODE:
3029                 return pBase->opCapFlags.opFlags;
3030         case EEP_RF_SILENT:
3031                 return pBase->rfSilent;
3032         case EEP_TX_MASK:
3033                 return (pBase->txrxMask >> 4) & 0xf;
3034         case EEP_RX_MASK:
3035                 return pBase->txrxMask & 0xf;
3036         case EEP_DRIVE_STRENGTH:
3037 #define AR9300_EEP_BASE_DRIV_STRENGTH   0x1
3038                 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
3039         case EEP_INTERNAL_REGULATOR:
3040                 /* Bit 4 is internal regulator flag */
3041                 return (pBase->featureEnable & 0x10) >> 4;
3042         case EEP_SWREG:
3043                 return le32_to_cpu(pBase->swreg);
3044         case EEP_PAPRD:
3045                 return !!(pBase->featureEnable & BIT(5));
3046         case EEP_CHAIN_MASK_REDUCE:
3047                 return (pBase->miscConfiguration >> 0x3) & 0x1;
3048         case EEP_ANT_DIV_CTL1:
3049                 return eep->base_ext1.ant_div_control;
3050         default:
3051                 return 0;
3052         }
3053 }
3054
3055 static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3056                                     u8 *buffer)
3057 {
3058         u16 val;
3059
3060         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3061                 return false;
3062
3063         *buffer = (val >> (8 * (address % 2))) & 0xff;
3064         return true;
3065 }
3066
3067 static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3068                                     u8 *buffer)
3069 {
3070         u16 val;
3071
3072         if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3073                 return false;
3074
3075         buffer[0] = val >> 8;
3076         buffer[1] = val & 0xff;
3077
3078         return true;
3079 }
3080
3081 static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3082                                int count)
3083 {
3084         struct ath_common *common = ath9k_hw_common(ah);
3085         int i;
3086
3087         if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
3088                 ath_dbg(common, ATH_DBG_EEPROM,
3089                         "eeprom address not in range\n");
3090                 return false;
3091         }
3092
3093         /*
3094          * Since we're reading the bytes in reverse order from a little-endian
3095          * word stream, an even address means we only use the lower half of
3096          * the 16-bit word at that address
3097          */
3098         if (address % 2 == 0) {
3099                 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3100                         goto error;
3101
3102                 count--;
3103         }
3104
3105         for (i = 0; i < count / 2; i++) {
3106                 if (!ar9300_eeprom_read_word(common, address, buffer))
3107                         goto error;
3108
3109                 address -= 2;
3110                 buffer += 2;
3111         }
3112
3113         if (count % 2)
3114                 if (!ar9300_eeprom_read_byte(common, address, buffer))
3115                         goto error;
3116
3117         return true;
3118
3119 error:
3120         ath_dbg(common, ATH_DBG_EEPROM,
3121                 "unable to read eeprom region at offset %d\n", address);
3122         return false;
3123 }
3124
3125 static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3126 {
3127         REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3128
3129         if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3130                            AR9300_OTP_STATUS_VALID, 1000))
3131                 return false;
3132
3133         *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3134         return true;
3135 }
3136
3137 static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3138                             int count)
3139 {
3140         u32 data;
3141         int i;
3142
3143         for (i = 0; i < count; i++) {
3144                 int offset = 8 * ((address - i) % 4);
3145                 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3146                         return false;
3147
3148                 buffer[i] = (data >> offset) & 0xff;
3149         }
3150
3151         return true;
3152 }
3153
3154
3155 static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3156                                    int *length, int *major, int *minor)
3157 {
3158         unsigned long value[4];
3159
3160         value[0] = best[0];
3161         value[1] = best[1];
3162         value[2] = best[2];
3163         value[3] = best[3];
3164         *code = ((value[0] >> 5) & 0x0007);
3165         *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3166         *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3167         *major = (value[2] & 0x000f);
3168         *minor = (value[3] & 0x00ff);
3169 }
3170
3171 static u16 ar9300_comp_cksum(u8 *data, int dsize)
3172 {
3173         int it, checksum = 0;
3174
3175         for (it = 0; it < dsize; it++) {
3176                 checksum += data[it];
3177                 checksum &= 0xffff;
3178         }
3179
3180         return checksum;
3181 }
3182
3183 static bool ar9300_uncompress_block(struct ath_hw *ah,
3184                                     u8 *mptr,
3185                                     int mdataSize,
3186                                     u8 *block,
3187                                     int size)
3188 {
3189         int it;
3190         int spot;
3191         int offset;
3192         int length;
3193         struct ath_common *common = ath9k_hw_common(ah);
3194
3195         spot = 0;
3196
3197         for (it = 0; it < size; it += (length+2)) {
3198                 offset = block[it];
3199                 offset &= 0xff;
3200                 spot += offset;
3201                 length = block[it+1];
3202                 length &= 0xff;
3203
3204                 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
3205                         ath_dbg(common, ATH_DBG_EEPROM,
3206                                 "Restore at %d: spot=%d offset=%d length=%d\n",
3207                                 it, spot, offset, length);
3208                         memcpy(&mptr[spot], &block[it+2], length);
3209                         spot += length;
3210                 } else if (length > 0) {
3211                         ath_dbg(common, ATH_DBG_EEPROM,
3212                                 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3213                                 it, spot, offset, length);
3214                         return false;
3215                 }
3216         }
3217         return true;
3218 }
3219
3220 static int ar9300_compress_decision(struct ath_hw *ah,
3221                                     int it,
3222                                     int code,
3223                                     int reference,
3224                                     u8 *mptr,
3225                                     u8 *word, int length, int mdata_size)
3226 {
3227         struct ath_common *common = ath9k_hw_common(ah);
3228         const struct ar9300_eeprom *eep = NULL;
3229
3230         switch (code) {
3231         case _CompressNone:
3232                 if (length != mdata_size) {
3233                         ath_dbg(common, ATH_DBG_EEPROM,
3234                                 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3235                                 mdata_size, length);
3236                         return -1;
3237                 }
3238                 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
3239                 ath_dbg(common, ATH_DBG_EEPROM,
3240                         "restored eeprom %d: uncompressed, length %d\n",
3241                         it, length);
3242                 break;
3243         case _CompressBlock:
3244                 if (reference == 0) {
3245                 } else {
3246                         eep = ar9003_eeprom_struct_find_by_id(reference);
3247                         if (eep == NULL) {
3248                                 ath_dbg(common, ATH_DBG_EEPROM,
3249                                         "can't find reference eeprom struct %d\n",
3250                                         reference);
3251                                 return -1;
3252                         }
3253                         memcpy(mptr, eep, mdata_size);
3254                 }
3255                 ath_dbg(common, ATH_DBG_EEPROM,
3256                         "restore eeprom %d: block, reference %d, length %d\n",
3257                         it, reference, length);
3258                 ar9300_uncompress_block(ah, mptr, mdata_size,
3259                                         (u8 *) (word + COMP_HDR_LEN), length);
3260                 break;
3261         default:
3262                 ath_dbg(common, ATH_DBG_EEPROM,
3263                         "unknown compression code %d\n", code);
3264                 return -1;
3265         }
3266         return 0;
3267 }
3268
3269 typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3270                                int count);
3271
3272 static bool ar9300_check_header(void *data)
3273 {
3274         u32 *word = data;
3275         return !(*word == 0 || *word == ~0);
3276 }
3277
3278 static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3279                                        int base_addr)
3280 {
3281         u8 header[4];
3282
3283         if (!read(ah, base_addr, header, 4))
3284                 return false;
3285
3286         return ar9300_check_header(header);
3287 }
3288
3289 static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3290                                        int mdata_size)
3291 {
3292         struct ath_common *common = ath9k_hw_common(ah);
3293         u16 *data = (u16 *) mptr;
3294         int i;
3295
3296         for (i = 0; i < mdata_size / 2; i++, data++)
3297                 ath9k_hw_nvram_read(common, i, data);
3298
3299         return 0;
3300 }
3301 /*
3302  * Read the configuration data from the eeprom.
3303  * The data can be put in any specified memory buffer.
3304  *
3305  * Returns -1 on error.
3306  * Returns address of next memory location on success.
3307  */
3308 static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3309                                           u8 *mptr, int mdata_size)
3310 {
3311 #define MDEFAULT 15
3312 #define MSTATE 100
3313         int cptr;
3314         u8 *word;
3315         int code;
3316         int reference, length, major, minor;
3317         int osize;
3318         int it;
3319         u16 checksum, mchecksum;
3320         struct ath_common *common = ath9k_hw_common(ah);
3321         eeprom_read_op read;
3322
3323         if (ath9k_hw_use_flash(ah))
3324                 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3325
3326         word = kzalloc(2048, GFP_KERNEL);
3327         if (!word)
3328                 return -ENOMEM;
3329
3330         memcpy(mptr, &ar9300_default, mdata_size);
3331
3332         read = ar9300_read_eeprom;
3333         if (AR_SREV_9485(ah))
3334                 cptr = AR9300_BASE_ADDR_4K;
3335         else if (AR_SREV_9330(ah))
3336                 cptr = AR9300_BASE_ADDR_512;
3337         else
3338                 cptr = AR9300_BASE_ADDR;
3339         ath_dbg(common, ATH_DBG_EEPROM,
3340                 "Trying EEPROM access at Address 0x%04x\n", cptr);
3341         if (ar9300_check_eeprom_header(ah, read, cptr))
3342                 goto found;
3343
3344         cptr = AR9300_BASE_ADDR_512;
3345         ath_dbg(common, ATH_DBG_EEPROM,
3346                 "Trying EEPROM access at Address 0x%04x\n", cptr);
3347         if (ar9300_check_eeprom_header(ah, read, cptr))
3348                 goto found;
3349
3350         read = ar9300_read_otp;
3351         cptr = AR9300_BASE_ADDR;
3352         ath_dbg(common, ATH_DBG_EEPROM,
3353                 "Trying OTP access at Address 0x%04x\n", cptr);
3354         if (ar9300_check_eeprom_header(ah, read, cptr))
3355                 goto found;
3356
3357         cptr = AR9300_BASE_ADDR_512;
3358         ath_dbg(common, ATH_DBG_EEPROM,
3359                 "Trying OTP access at Address 0x%04x\n", cptr);
3360         if (ar9300_check_eeprom_header(ah, read, cptr))
3361                 goto found;
3362
3363         goto fail;
3364
3365 found:
3366         ath_dbg(common, ATH_DBG_EEPROM, "Found valid EEPROM data\n");
3367
3368         for (it = 0; it < MSTATE; it++) {
3369                 if (!read(ah, cptr, word, COMP_HDR_LEN))
3370                         goto fail;
3371
3372                 if (!ar9300_check_header(word))
3373                         break;
3374
3375                 ar9300_comp_hdr_unpack(word, &code, &reference,
3376                                        &length, &major, &minor);
3377                 ath_dbg(common, ATH_DBG_EEPROM,
3378                         "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3379                         cptr, code, reference, length, major, minor);
3380                 if ((!AR_SREV_9485(ah) && length >= 1024) ||
3381                     (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
3382                         ath_dbg(common, ATH_DBG_EEPROM,
3383                                 "Skipping bad header\n");
3384                         cptr -= COMP_HDR_LEN;
3385                         continue;
3386                 }
3387
3388                 osize = length;
3389                 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3390                 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
3391                 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
3392                 ath_dbg(common, ATH_DBG_EEPROM,
3393                         "checksum %x %x\n", checksum, mchecksum);
3394                 if (checksum == mchecksum) {
3395                         ar9300_compress_decision(ah, it, code, reference, mptr,
3396                                                  word, length, mdata_size);
3397                 } else {
3398                         ath_dbg(common, ATH_DBG_EEPROM,
3399                                 "skipping block with bad checksum\n");
3400                 }
3401                 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3402         }
3403
3404         kfree(word);
3405         return cptr;
3406
3407 fail:
3408         kfree(word);
3409         return -1;
3410 }
3411
3412 /*
3413  * Restore the configuration structure by reading the eeprom.
3414  * This function destroys any existing in-memory structure
3415  * content.
3416  */
3417 static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3418 {
3419         u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
3420
3421         if (ar9300_eeprom_restore_internal(ah, mptr,
3422                         sizeof(struct ar9300_eeprom)) < 0)
3423                 return false;
3424
3425         return true;
3426 }
3427
3428 #if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3429 static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3430                                     struct ar9300_modal_eep_header *modal_hdr)
3431 {
3432         PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3433         PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3434         PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3435         PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3436         PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3437         PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3438         PR_EEP("Switch Settle", modal_hdr->switchSettling);
3439         PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3440         PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3441         PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3442         PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3443         PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3444         PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3445         PR_EEP("Temp Slope", modal_hdr->tempSlope);
3446         PR_EEP("Volt Slope", modal_hdr->voltSlope);
3447         PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3448         PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3449         PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3450         PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3451         PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3452         PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3453         PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3454         PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
3455         PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3456         PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3457         PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3458         PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3459         PR_EEP("txClip", modal_hdr->txClip);
3460         PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
3461         PR_EEP("Chain0 ob", modal_hdr->ob[0]);
3462         PR_EEP("Chain1 ob", modal_hdr->ob[1]);
3463         PR_EEP("Chain2 ob", modal_hdr->ob[2]);
3464
3465         PR_EEP("Chain0 db_stage2", modal_hdr->db_stage2[0]);
3466         PR_EEP("Chain1 db_stage2", modal_hdr->db_stage2[1]);
3467         PR_EEP("Chain2 db_stage2", modal_hdr->db_stage2[2]);
3468         PR_EEP("Chain0 db_stage3", modal_hdr->db_stage3[0]);
3469         PR_EEP("Chain1 db_stage3", modal_hdr->db_stage3[1]);
3470         PR_EEP("Chain2 db_stage3", modal_hdr->db_stage3[2]);
3471         PR_EEP("Chain0 db_stage4", modal_hdr->db_stage4[0]);
3472         PR_EEP("Chain1 db_stage4", modal_hdr->db_stage4[1]);
3473         PR_EEP("Chain2 db_stage4", modal_hdr->db_stage4[2]);
3474
3475         return len;
3476 }
3477
3478 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3479                                        u8 *buf, u32 len, u32 size)
3480 {
3481         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3482         struct ar9300_base_eep_hdr *pBase;
3483
3484         if (!dump_base_hdr) {
3485                 len += snprintf(buf + len, size - len,
3486                                 "%20s :\n", "2GHz modal Header");
3487                 len += ar9003_dump_modal_eeprom(buf, len, size,
3488                                                 &eep->modalHeader2G);
3489                 len += snprintf(buf + len, size - len,
3490                                 "%20s :\n", "5GHz modal Header");
3491                 len += ar9003_dump_modal_eeprom(buf, len, size,
3492                                                 &eep->modalHeader5G);
3493                 goto out;
3494         }
3495
3496         pBase = &eep->baseEepHeader;
3497
3498         PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3499         PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3500         PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3501         PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3502         PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3503         PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3504                                 AR5416_OPFLAGS_11A));
3505         PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3506                                 AR5416_OPFLAGS_11G));
3507         PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3508                                         AR5416_OPFLAGS_N_2G_HT20));
3509         PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3510                                         AR5416_OPFLAGS_N_2G_HT40));
3511         PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3512                                         AR5416_OPFLAGS_N_5G_HT20));
3513         PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3514                                         AR5416_OPFLAGS_N_5G_HT40));
3515         PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3516         PR_EEP("RF Silent", pBase->rfSilent);
3517         PR_EEP("BT option", pBase->blueToothOptions);
3518         PR_EEP("Device Cap", pBase->deviceCap);
3519         PR_EEP("Device Type", pBase->deviceType);
3520         PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3521         PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3522         PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3523         PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3524         PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3525         PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3526         PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3527         PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3528         PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3529         PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
3530         PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3531         PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3532         PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3533         PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3534         PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3535         PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3536         PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3537         PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3538
3539         len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3540                         ah->eeprom.ar9300_eep.macAddr);
3541 out:
3542         if (len > size)
3543                 len = size;
3544
3545         return len;
3546 }
3547 #else
3548 static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3549                                        u8 *buf, u32 len, u32 size)
3550 {
3551         return 0;
3552 }
3553 #endif
3554
3555 /* XXX: review hardware docs */
3556 static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3557 {
3558         return ah->eeprom.ar9300_eep.eepromVersion;
3559 }
3560
3561 /* XXX: could be read from the eepromVersion, not sure yet */
3562 static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3563 {
3564         return 0;
3565 }
3566
3567 static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3568 {
3569         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3570
3571         if (is2ghz)
3572                 return eep->modalHeader2G.xpaBiasLvl;
3573         else
3574                 return eep->modalHeader5G.xpaBiasLvl;
3575 }
3576
3577 static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3578 {
3579         int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
3580
3581         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
3582                 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
3583         else if (AR_SREV_9480(ah))
3584                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3585         else {
3586                 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
3587                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3588                                 AR_CH0_THERM_XPABIASLVL_MSB,
3589                                 bias >> 2);
3590                 REG_RMW_FIELD(ah, AR_CH0_THERM,
3591                                 AR_CH0_THERM_XPASHORT2GND, 1);
3592         }
3593 }
3594
3595 static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
3596 {
3597         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3598         __le32 val;
3599
3600         if (is_2ghz)
3601                 val = eep->modalHeader2G.switchcomspdt;
3602         else
3603                 val = eep->modalHeader5G.switchcomspdt;
3604         return le32_to_cpu(val);
3605 }
3606
3607
3608 static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3609 {
3610         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3611         __le32 val;
3612
3613         if (is2ghz)
3614                 val = eep->modalHeader2G.antCtrlCommon;
3615         else
3616                 val = eep->modalHeader5G.antCtrlCommon;
3617         return le32_to_cpu(val);
3618 }
3619
3620 static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3621 {
3622         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3623         __le32 val;
3624
3625         if (is2ghz)
3626                 val = eep->modalHeader2G.antCtrlCommon2;
3627         else
3628                 val = eep->modalHeader5G.antCtrlCommon2;
3629         return le32_to_cpu(val);
3630 }
3631
3632 static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3633                                         int chain,
3634                                         bool is2ghz)
3635 {
3636         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3637         __le16 val = 0;
3638
3639         if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3640                 if (is2ghz)
3641                         val = eep->modalHeader2G.antCtrlChain[chain];
3642                 else
3643                         val = eep->modalHeader5G.antCtrlChain[chain];
3644         }
3645
3646         return le16_to_cpu(val);
3647 }
3648
3649 static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3650 {
3651         int chain;
3652         u32 regval;
3653         u32 ant_div_ctl1;
3654         static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3655                         AR_PHY_SWITCH_CHAIN_0,
3656                         AR_PHY_SWITCH_CHAIN_1,
3657                         AR_PHY_SWITCH_CHAIN_2,
3658         };
3659
3660         u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
3661
3662         if (AR_SREV_9480(ah)) {
3663                 if (AR_SREV_9480_10(ah)) {
3664                         value &= ~AR_SWITCH_TABLE_COM_SPDT;
3665                         value |= 0x00100000;
3666                 }
3667                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3668                                 AR_SWITCH_TABLE_COM_AR9480_ALL, value);
3669         } else
3670                 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3671                               AR_SWITCH_TABLE_COM_ALL, value);
3672
3673
3674         /*
3675          *   AR9480 defines new switch table for BT/WLAN,
3676          *       here's new field name in XXX.ref for both 2G and 5G.
3677          *   Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3678          *   15:12   R/W     SWITCH_TABLE_COM_SPDT_WLAN_RX
3679          * SWITCH_TABLE_COM_SPDT_WLAN_RX
3680          *
3681          *   11:8     R/W     SWITCH_TABLE_COM_SPDT_WLAN_TX
3682          * SWITCH_TABLE_COM_SPDT_WLAN_TX
3683          *
3684          *   7:4 R/W  SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3685          * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3686          */
3687         if (AR_SREV_9480_20_OR_LATER(ah)) {
3688                 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3689                 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3690                                 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3691         }
3692
3693         value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3694         REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3695
3696         for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3697                 if ((ah->rxchainmask & BIT(chain)) ||
3698                     (ah->txchainmask & BIT(chain))) {
3699                         value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3700                                                              is2ghz);
3701                         REG_RMW_FIELD(ah, switch_chain_reg[chain],
3702                                       AR_SWITCH_TABLE_ALL, value);
3703                 }
3704         }
3705
3706         if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3707                 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
3708                 /*
3709                  * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3710                  * are the fields present
3711                  */
3712                 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3713                 regval &= (~AR_ANT_DIV_CTRL_ALL);
3714                 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3715                 /* enable_lnadiv */
3716                 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3717                 regval |= ((value >> 6) & 0x1) <<
3718                                 AR_PHY_9485_ANT_DIV_LNADIV_S;
3719                 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3720
3721                 /*enable fast_div */
3722                 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3723                 regval &= (~AR_FAST_DIV_ENABLE);
3724                 regval |= ((value >> 7) & 0x1) <<
3725                                 AR_FAST_DIV_ENABLE_S;
3726                 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3727                 ant_div_ctl1 =
3728                         ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3729                 /* check whether antenna diversity is enabled */
3730                 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3731                         regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3732                         /*
3733                          * clear bits 25-30 main_lnaconf, alt_lnaconf,
3734                          * main_tb, alt_tb
3735                          */
3736                         regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3737                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3738                                         AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3739                                         AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3740                         /* by default use LNA1 for the main antenna */
3741                         regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3742                                         AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3743                         regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3744                                         AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3745                         REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3746                 }
3747
3748
3749         }
3750
3751 }
3752
3753 static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3754 {
3755         int drive_strength;
3756         unsigned long reg;
3757
3758         drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3759
3760         if (!drive_strength)
3761                 return;
3762
3763         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3764         reg &= ~0x00ffffc0;
3765         reg |= 0x5 << 21;
3766         reg |= 0x5 << 18;
3767         reg |= 0x5 << 15;
3768         reg |= 0x5 << 12;
3769         reg |= 0x5 << 9;
3770         reg |= 0x5 << 6;
3771         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3772
3773         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3774         reg &= ~0xffffffe0;
3775         reg |= 0x5 << 29;
3776         reg |= 0x5 << 26;
3777         reg |= 0x5 << 23;
3778         reg |= 0x5 << 20;
3779         reg |= 0x5 << 17;
3780         reg |= 0x5 << 14;
3781         reg |= 0x5 << 11;
3782         reg |= 0x5 << 8;
3783         reg |= 0x5 << 5;
3784         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3785
3786         reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3787         reg &= ~0xff800000;
3788         reg |= 0x5 << 29;
3789         reg |= 0x5 << 26;
3790         reg |= 0x5 << 23;
3791         REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3792 }
3793
3794 static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3795                                      struct ath9k_channel *chan)
3796 {
3797         int f[3], t[3];
3798         u16 value;
3799         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3800
3801         if (chain >= 0 && chain < 3) {
3802                 if (IS_CHAN_2GHZ(chan))
3803                         return eep->modalHeader2G.xatten1DB[chain];
3804                 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3805                         t[0] = eep->base_ext2.xatten1DBLow[chain];
3806                         f[0] = 5180;
3807                         t[1] = eep->modalHeader5G.xatten1DB[chain];
3808                         f[1] = 5500;
3809                         t[2] = eep->base_ext2.xatten1DBHigh[chain];
3810                         f[2] = 5785;
3811                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3812                                                             f, t, 3);
3813                         return value;
3814                 } else
3815                         return eep->modalHeader5G.xatten1DB[chain];
3816         }
3817
3818         return 0;
3819 }
3820
3821
3822 static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3823                                             struct ath9k_channel *chan)
3824 {
3825         int f[3], t[3];
3826         u16 value;
3827         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3828
3829         if (chain >= 0 && chain < 3) {
3830                 if (IS_CHAN_2GHZ(chan))
3831                         return eep->modalHeader2G.xatten1Margin[chain];
3832                 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3833                         t[0] = eep->base_ext2.xatten1MarginLow[chain];
3834                         f[0] = 5180;
3835                         t[1] = eep->modalHeader5G.xatten1Margin[chain];
3836                         f[1] = 5500;
3837                         t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3838                         f[2] = 5785;
3839                         value = ar9003_hw_power_interpolate((s32) chan->channel,
3840                                                             f, t, 3);
3841                         return value;
3842                 } else
3843                         return eep->modalHeader5G.xatten1Margin[chain];
3844         }
3845
3846         return 0;
3847 }
3848
3849 static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3850 {
3851         int i;
3852         u16 value;
3853         unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3854                                           AR_PHY_EXT_ATTEN_CTL_1,
3855                                           AR_PHY_EXT_ATTEN_CTL_2,
3856                                          };
3857
3858         /* Test value. if 0 then attenuation is unused. Don't load anything. */
3859         for (i = 0; i < 3; i++) {
3860                 if (ah->txchainmask & BIT(i)) {
3861                         value = ar9003_hw_atten_chain_get(ah, i, chan);
3862                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3863                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
3864
3865                         value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3866                         REG_RMW_FIELD(ah, ext_atten_reg[i],
3867                                       AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3868                                       value);
3869                 }
3870         }
3871 }
3872
3873 static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3874 {
3875         int timeout = 100;
3876
3877         while (pmu_set != REG_READ(ah, pmu_reg)) {
3878                 if (timeout-- == 0)
3879                         return false;
3880                 REG_WRITE(ah, pmu_reg, pmu_set);
3881                 udelay(10);
3882         }
3883
3884         return true;
3885 }
3886
3887 static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3888 {
3889         int internal_regulator =
3890                 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
3891         u32 reg_val;
3892
3893         if (internal_regulator) {
3894                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3895                         int reg_pmu_set;
3896
3897                         reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3898                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3899                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3900                                 return;
3901
3902                         if (AR_SREV_9330(ah)) {
3903                                 if (ah->is_clk_25mhz) {
3904                                         reg_pmu_set = (3 << 1) | (8 << 4) |
3905                                                       (3 << 8) | (1 << 14) |
3906                                                       (6 << 17) | (1 << 20) |
3907                                                       (3 << 24);
3908                                 } else {
3909                                         reg_pmu_set = (4 << 1)  | (7 << 4) |
3910                                                       (3 << 8)  | (1 << 14) |
3911                                                       (6 << 17) | (1 << 20) |
3912                                                       (3 << 24);
3913                                 }
3914                         } else {
3915                                 reg_pmu_set = (5 << 1) | (7 << 4) |
3916                                               (1 << 8) | (2 << 14) |
3917                                               (6 << 17) | (1 << 20) |
3918                                               (3 << 24) | (1 << 28);
3919                         }
3920
3921                         REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3922                         if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3923                                 return;
3924
3925                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3926                                         | (4 << 26);
3927                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3928                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3929                                 return;
3930
3931                         reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3932                                         | (1 << 21);
3933                         REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3934                         if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3935                                 return;
3936                 } else if (AR_SREV_9480(ah)) {
3937                         reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3938                         REG_WRITE(ah, AR_PHY_PMU1, reg_val);
3939                 } else {
3940                         /* Internal regulator is ON. Write swreg register. */
3941                         reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3942                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3943                                   REG_READ(ah, AR_RTC_REG_CONTROL1) &
3944                                   (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
3945                         REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
3946                         /* Set REG_CONTROL1.SWREG_PROGRAM */
3947                         REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3948                                   REG_READ(ah,
3949                                            AR_RTC_REG_CONTROL1) |
3950                                            AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3951                 }
3952         } else {
3953                 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
3954                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3955                         while (REG_READ_FIELD(ah, AR_PHY_PMU2,
3956                                                 AR_PHY_PMU2_PGM))
3957                                 udelay(10);
3958
3959                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3960                         while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
3961                                                 AR_PHY_PMU1_PWD))
3962                                 udelay(10);
3963                         REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3964                         while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
3965                                                 AR_PHY_PMU2_PGM))
3966                                 udelay(10);
3967                 } else if (AR_SREV_9480(ah))
3968                         REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3969                 else {
3970                         reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3971                                 AR_RTC_FORCE_SWREG_PRD;
3972                         REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3973                 }
3974         }
3975
3976 }
3977
3978 static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3979 {
3980         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3981         u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3982
3983         if (eep->baseEepHeader.featureEnable & 0x40) {
3984                 tuning_caps_param &= 0x7f;
3985                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3986                               tuning_caps_param);
3987                 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3988                               tuning_caps_param);
3989         }
3990 }
3991
3992 static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3993                                              struct ath9k_channel *chan)
3994 {
3995         ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3996         ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3997         ar9003_hw_drive_strength_apply(ah);
3998         ar9003_hw_atten_apply(ah, chan);
3999         if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
4000                 ar9003_hw_internal_regulator_apply(ah);
4001         if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
4002                 ar9003_hw_apply_tuning_caps(ah);
4003 }
4004
4005 static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
4006                                       struct ath9k_channel *chan)
4007 {
4008 }
4009
4010 /*
4011  * Returns the interpolated y value corresponding to the specified x value
4012  * from the np ordered pairs of data (px,py).
4013  * The pairs do not have to be in any order.
4014  * If the specified x value is less than any of the px,
4015  * the returned y value is equal to the py for the lowest px.
4016  * If the specified x value is greater than any of the px,
4017  * the returned y value is equal to the py for the highest px.
4018  */
4019 static int ar9003_hw_power_interpolate(int32_t x,
4020                                        int32_t *px, int32_t *py, u_int16_t np)
4021 {
4022         int ip = 0;
4023         int lx = 0, ly = 0, lhave = 0;
4024         int hx = 0, hy = 0, hhave = 0;
4025         int dx = 0;
4026         int y = 0;
4027
4028         lhave = 0;
4029         hhave = 0;
4030
4031         /* identify best lower and higher x calibration measurement */
4032         for (ip = 0; ip < np; ip++) {
4033                 dx = x - px[ip];
4034
4035                 /* this measurement is higher than our desired x */
4036                 if (dx <= 0) {
4037                         if (!hhave || dx > (x - hx)) {
4038                                 /* new best higher x measurement */
4039                                 hx = px[ip];
4040                                 hy = py[ip];
4041                                 hhave = 1;
4042                         }
4043                 }
4044                 /* this measurement is lower than our desired x */
4045                 if (dx >= 0) {
4046                         if (!lhave || dx < (x - lx)) {
4047                                 /* new best lower x measurement */
4048                                 lx = px[ip];
4049                                 ly = py[ip];
4050                                 lhave = 1;
4051                         }
4052                 }
4053         }
4054
4055         /* the low x is good */
4056         if (lhave) {
4057                 /* so is the high x */
4058                 if (hhave) {
4059                         /* they're the same, so just pick one */
4060                         if (hx == lx)
4061                                 y = ly;
4062                         else    /* interpolate  */
4063                                 y = interpolate(x, lx, hx, ly, hy);
4064                 } else          /* only low is good, use it */
4065                         y = ly;
4066         } else if (hhave)       /* only high is good, use it */
4067                 y = hy;
4068         else /* nothing is good,this should never happen unless np=0, ???? */
4069                 y = -(1 << 30);
4070         return y;
4071 }
4072
4073 static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4074                                        u16 rateIndex, u16 freq, bool is2GHz)
4075 {
4076         u16 numPiers, i;
4077         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4078         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4079         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4080         struct cal_tgt_pow_legacy *pEepromTargetPwr;
4081         u8 *pFreqBin;
4082
4083         if (is2GHz) {
4084                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4085                 pEepromTargetPwr = eep->calTargetPower2G;
4086                 pFreqBin = eep->calTarget_freqbin_2G;
4087         } else {
4088                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4089                 pEepromTargetPwr = eep->calTargetPower5G;
4090                 pFreqBin = eep->calTarget_freqbin_5G;
4091         }
4092
4093         /*
4094          * create array of channels and targetpower from
4095          * targetpower piers stored on eeprom
4096          */
4097         for (i = 0; i < numPiers; i++) {
4098                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4099                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4100         }
4101
4102         /* interpolate to get target power for given frequency */
4103         return (u8) ar9003_hw_power_interpolate((s32) freq,
4104                                                  freqArray,
4105                                                  targetPowerArray, numPiers);
4106 }
4107
4108 static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4109                                             u16 rateIndex,
4110                                             u16 freq, bool is2GHz)
4111 {
4112         u16 numPiers, i;
4113         s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4114         s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4115         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4116         struct cal_tgt_pow_ht *pEepromTargetPwr;
4117         u8 *pFreqBin;
4118
4119         if (is2GHz) {
4120                 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
4121                 pEepromTargetPwr = eep->calTargetPower2GHT20;
4122                 pFreqBin = eep->calTarget_freqbin_2GHT20;
4123         } else {
4124                 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4125                 pEepromTargetPwr = eep->calTargetPower5GHT20;
4126                 pFreqBin = eep->calTarget_freqbin_5GHT20;
4127         }
4128
4129         /*
4130          * create array of channels and targetpower
4131          * from targetpower piers stored on eeprom
4132          */
4133         for (i = 0; i < numPiers; i++) {
4134                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4135                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4136         }
4137
4138         /* interpolate to get target power for given frequency */
4139         return (u8) ar9003_hw_power_interpolate((s32) freq,
4140                                                  freqArray,
4141                                                  targetPowerArray, numPiers);
4142 }
4143
4144 static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4145                                             u16 rateIndex,
4146                                             u16 freq, bool is2GHz)
4147 {
4148         u16 numPiers, i;
4149         s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4150         s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4151         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4152         struct cal_tgt_pow_ht *pEepromTargetPwr;
4153         u8 *pFreqBin;
4154
4155         if (is2GHz) {
4156                 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4157                 pEepromTargetPwr = eep->calTargetPower2GHT40;
4158                 pFreqBin = eep->calTarget_freqbin_2GHT40;
4159         } else {
4160                 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4161                 pEepromTargetPwr = eep->calTargetPower5GHT40;
4162                 pFreqBin = eep->calTarget_freqbin_5GHT40;
4163         }
4164
4165         /*
4166          * create array of channels and targetpower from
4167          * targetpower piers stored on eeprom
4168          */
4169         for (i = 0; i < numPiers; i++) {
4170                 freqArray[i] = FBIN2FREQ(pFreqBin[i], is2GHz);
4171                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4172         }
4173
4174         /* interpolate to get target power for given frequency */
4175         return (u8) ar9003_hw_power_interpolate((s32) freq,
4176                                                  freqArray,
4177                                                  targetPowerArray, numPiers);
4178 }
4179
4180 static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4181                                            u16 rateIndex, u16 freq)
4182 {
4183         u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4184         s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4185         s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4186         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4187         struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4188         u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4189
4190         /*
4191          * create array of channels and targetpower from
4192          * targetpower piers stored on eeprom
4193          */
4194         for (i = 0; i < numPiers; i++) {
4195                 freqArray[i] = FBIN2FREQ(pFreqBin[i], 1);
4196                 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4197         }
4198
4199         /* interpolate to get target power for given frequency */
4200         return (u8) ar9003_hw_power_interpolate((s32) freq,
4201                                                  freqArray,
4202                                                  targetPowerArray, numPiers);
4203 }
4204
4205 /* Set tx power registers to array of values passed in */
4206 static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4207 {
4208 #define POW_SM(_r, _s)     (((_r) & 0x3f) << (_s))
4209         /* make sure forced gain is not set */
4210         REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
4211
4212         /* Write the OFDM power per rate set */
4213
4214         /* 6 (LSB), 9, 12, 18 (MSB) */
4215         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
4216                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4217                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4218                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4219                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4220
4221         /* 24 (LSB), 36, 48, 54 (MSB) */
4222         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
4223                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4224                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4225                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4226                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4227
4228         /* Write the CCK power per rate set */
4229
4230         /* 1L (LSB), reserved, 2L, 2S (MSB) */
4231         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
4232                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4233                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4234                   /* POW_SM(txPowerTimes2,  8) | this is reserved for AR9003 */
4235                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4236
4237         /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
4238         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
4239                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4240                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4241                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4242                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4243             );
4244
4245         /* Write the power for duplicated frames - HT40 */
4246
4247         /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
4248         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
4249                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4250                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4251                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24],  8) |
4252                   POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L],  0)
4253             );
4254
4255         /* Write the HT20 power per rate set */
4256
4257         /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
4258         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
4259                   POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4260                   POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4261                   POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4262                   POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4263             );
4264
4265         /* 6 (LSB), 7, 12, 13 (MSB) */
4266         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
4267                   POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4268                   POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4269                   POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4270                   POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4271             );
4272
4273         /* 14 (LSB), 15, 20, 21 */
4274         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
4275                   POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4276                   POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4277                   POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4278                   POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4279             );
4280
4281         /* Mixed HT20 and HT40 rates */
4282
4283         /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
4284         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
4285                   POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4286                   POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4287                   POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4288                   POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4289             );
4290
4291         /*
4292          * Write the HT40 power per rate set
4293          * correct PAR difference between HT40 and HT20/LEGACY
4294          * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4295          */
4296         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
4297                   POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4298                   POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4299                   POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4300                   POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4301             );
4302
4303         /* 6 (LSB), 7, 12, 13 (MSB) */
4304         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
4305                   POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4306                   POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4307                   POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4308                   POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4309             );
4310
4311         /* 14 (LSB), 15, 20, 21 */
4312         REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
4313                   POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4314                   POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4315                   POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4316                   POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4317             );
4318
4319         return 0;
4320 #undef POW_SM
4321 }
4322
4323 static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4324                                               u8 *targetPowerValT2)
4325 {
4326         /* XXX: hard code for now, need to get from eeprom struct */
4327         u8 ht40PowerIncForPdadc = 0;
4328         bool is2GHz = false;
4329         unsigned int i = 0;
4330         struct ath_common *common = ath9k_hw_common(ah);
4331
4332         if (freq < 4000)
4333                 is2GHz = true;
4334
4335         targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4336             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4337                                          is2GHz);
4338         targetPowerValT2[ALL_TARGET_LEGACY_36] =
4339             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4340                                          is2GHz);
4341         targetPowerValT2[ALL_TARGET_LEGACY_48] =
4342             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4343                                          is2GHz);
4344         targetPowerValT2[ALL_TARGET_LEGACY_54] =
4345             ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4346                                          is2GHz);
4347         targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4348             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4349                                              freq);
4350         targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4351             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4352         targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4353             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4354         targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4355             ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4356         targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4357             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4358                                               is2GHz);
4359         targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4360             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4361                                               freq, is2GHz);
4362         targetPowerValT2[ALL_TARGET_HT20_4] =
4363             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4364                                               is2GHz);
4365         targetPowerValT2[ALL_TARGET_HT20_5] =
4366             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4367                                               is2GHz);
4368         targetPowerValT2[ALL_TARGET_HT20_6] =
4369             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4370                                               is2GHz);
4371         targetPowerValT2[ALL_TARGET_HT20_7] =
4372             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4373                                               is2GHz);
4374         targetPowerValT2[ALL_TARGET_HT20_12] =
4375             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4376                                               is2GHz);
4377         targetPowerValT2[ALL_TARGET_HT20_13] =
4378             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4379                                               is2GHz);
4380         targetPowerValT2[ALL_TARGET_HT20_14] =
4381             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4382                                               is2GHz);
4383         targetPowerValT2[ALL_TARGET_HT20_15] =
4384             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4385                                               is2GHz);
4386         targetPowerValT2[ALL_TARGET_HT20_20] =
4387             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4388                                               is2GHz);
4389         targetPowerValT2[ALL_TARGET_HT20_21] =
4390             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4391                                               is2GHz);
4392         targetPowerValT2[ALL_TARGET_HT20_22] =
4393             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4394                                               is2GHz);
4395         targetPowerValT2[ALL_TARGET_HT20_23] =
4396             ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4397                                               is2GHz);
4398         targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4399             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4400                                               is2GHz) + ht40PowerIncForPdadc;
4401         targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4402             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4403                                               freq,
4404                                               is2GHz) + ht40PowerIncForPdadc;
4405         targetPowerValT2[ALL_TARGET_HT40_4] =
4406             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4407                                               is2GHz) + ht40PowerIncForPdadc;
4408         targetPowerValT2[ALL_TARGET_HT40_5] =
4409             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4410                                               is2GHz) + ht40PowerIncForPdadc;
4411         targetPowerValT2[ALL_TARGET_HT40_6] =
4412             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4413                                               is2GHz) + ht40PowerIncForPdadc;
4414         targetPowerValT2[ALL_TARGET_HT40_7] =
4415             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4416                                               is2GHz) + ht40PowerIncForPdadc;
4417         targetPowerValT2[ALL_TARGET_HT40_12] =
4418             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4419                                               is2GHz) + ht40PowerIncForPdadc;
4420         targetPowerValT2[ALL_TARGET_HT40_13] =
4421             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4422                                               is2GHz) + ht40PowerIncForPdadc;
4423         targetPowerValT2[ALL_TARGET_HT40_14] =
4424             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4425                                               is2GHz) + ht40PowerIncForPdadc;
4426         targetPowerValT2[ALL_TARGET_HT40_15] =
4427             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4428                                               is2GHz) + ht40PowerIncForPdadc;
4429         targetPowerValT2[ALL_TARGET_HT40_20] =
4430             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4431                                               is2GHz) + ht40PowerIncForPdadc;
4432         targetPowerValT2[ALL_TARGET_HT40_21] =
4433             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4434                                               is2GHz) + ht40PowerIncForPdadc;
4435         targetPowerValT2[ALL_TARGET_HT40_22] =
4436             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4437                                               is2GHz) + ht40PowerIncForPdadc;
4438         targetPowerValT2[ALL_TARGET_HT40_23] =
4439             ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4440                                               is2GHz) + ht40PowerIncForPdadc;
4441
4442         for (i = 0; i < ar9300RateSize; i++) {
4443                 ath_dbg(common, ATH_DBG_EEPROM,
4444                         "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
4445         }
4446 }
4447
4448 static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4449                                   int mode,
4450                                   int ipier,
4451                                   int ichain,
4452                                   int *pfrequency,
4453                                   int *pcorrection,
4454                                   int *ptemperature, int *pvoltage)
4455 {
4456         u8 *pCalPier;
4457         struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4458         int is2GHz;
4459         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4460         struct ath_common *common = ath9k_hw_common(ah);
4461
4462         if (ichain >= AR9300_MAX_CHAINS) {
4463                 ath_dbg(common, ATH_DBG_EEPROM,
4464                         "Invalid chain index, must be less than %d\n",
4465                         AR9300_MAX_CHAINS);
4466                 return -1;
4467         }
4468
4469         if (mode) {             /* 5GHz */
4470                 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
4471                         ath_dbg(common, ATH_DBG_EEPROM,
4472                                 "Invalid 5GHz cal pier index, must be less than %d\n",
4473                                 AR9300_NUM_5G_CAL_PIERS);
4474                         return -1;
4475                 }
4476                 pCalPier = &(eep->calFreqPier5G[ipier]);
4477                 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4478                 is2GHz = 0;
4479         } else {
4480                 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
4481                         ath_dbg(common, ATH_DBG_EEPROM,
4482                                 "Invalid 2GHz cal pier index, must be less than %d\n",
4483                                 AR9300_NUM_2G_CAL_PIERS);
4484                         return -1;
4485                 }
4486
4487                 pCalPier = &(eep->calFreqPier2G[ipier]);
4488                 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4489                 is2GHz = 1;
4490         }
4491
4492         *pfrequency = FBIN2FREQ(*pCalPier, is2GHz);
4493         *pcorrection = pCalPierStruct->refPower;
4494         *ptemperature = pCalPierStruct->tempMeas;
4495         *pvoltage = pCalPierStruct->voltMeas;
4496
4497         return 0;
4498 }
4499
4500 static int ar9003_hw_power_control_override(struct ath_hw *ah,
4501                                             int frequency,
4502                                             int *correction,
4503                                             int *voltage, int *temperature)
4504 {
4505         int tempSlope = 0;
4506         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4507         int f[3], t[3];
4508
4509         REG_RMW(ah, AR_PHY_TPC_11_B0,
4510                 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4511                 AR_PHY_TPC_OLPC_GAIN_DELTA);
4512         if (ah->caps.tx_chainmask & BIT(1))
4513                 REG_RMW(ah, AR_PHY_TPC_11_B1,
4514                         (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4515                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4516         if (ah->caps.tx_chainmask & BIT(2))
4517                 REG_RMW(ah, AR_PHY_TPC_11_B2,
4518                         (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4519                         AR_PHY_TPC_OLPC_GAIN_DELTA);
4520
4521         /* enable open loop power control on chip */
4522         REG_RMW(ah, AR_PHY_TPC_6_B0,
4523                 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4524                 AR_PHY_TPC_6_ERROR_EST_MODE);
4525         if (ah->caps.tx_chainmask & BIT(1))
4526                 REG_RMW(ah, AR_PHY_TPC_6_B1,
4527                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4528                         AR_PHY_TPC_6_ERROR_EST_MODE);
4529         if (ah->caps.tx_chainmask & BIT(2))
4530                 REG_RMW(ah, AR_PHY_TPC_6_B2,
4531                         (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4532                         AR_PHY_TPC_6_ERROR_EST_MODE);
4533
4534         /*
4535          * enable temperature compensation
4536          * Need to use register names
4537          */
4538         if (frequency < 4000)
4539                 tempSlope = eep->modalHeader2G.tempSlope;
4540         else if (eep->base_ext2.tempSlopeLow != 0) {
4541                 t[0] = eep->base_ext2.tempSlopeLow;
4542                 f[0] = 5180;
4543                 t[1] = eep->modalHeader5G.tempSlope;
4544                 f[1] = 5500;
4545                 t[2] = eep->base_ext2.tempSlopeHigh;
4546                 f[2] = 5785;
4547                 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4548                                                         f, t, 3);
4549         } else
4550                 tempSlope = eep->modalHeader5G.tempSlope;
4551
4552         REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
4553
4554         if (AR_SREV_9480_20(ah))
4555                 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4556                               AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4557
4558
4559         REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4560                       temperature[0]);
4561
4562         return 0;
4563 }
4564
4565 /* Apply the recorded correction values. */
4566 static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4567 {
4568         int ichain, ipier, npier;
4569         int mode;
4570         int lfrequency[AR9300_MAX_CHAINS],
4571             lcorrection[AR9300_MAX_CHAINS],
4572             ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4573         int hfrequency[AR9300_MAX_CHAINS],
4574             hcorrection[AR9300_MAX_CHAINS],
4575             htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4576         int fdiff;
4577         int correction[AR9300_MAX_CHAINS],
4578             voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4579         int pfrequency, pcorrection, ptemperature, pvoltage;
4580         struct ath_common *common = ath9k_hw_common(ah);
4581
4582         mode = (frequency >= 4000);
4583         if (mode)
4584                 npier = AR9300_NUM_5G_CAL_PIERS;
4585         else
4586                 npier = AR9300_NUM_2G_CAL_PIERS;
4587
4588         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4589                 lfrequency[ichain] = 0;
4590                 hfrequency[ichain] = 100000;
4591         }
4592         /* identify best lower and higher frequency calibration measurement */
4593         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4594                 for (ipier = 0; ipier < npier; ipier++) {
4595                         if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4596                                                     &pfrequency, &pcorrection,
4597                                                     &ptemperature, &pvoltage)) {
4598                                 fdiff = frequency - pfrequency;
4599
4600                                 /*
4601                                  * this measurement is higher than
4602                                  * our desired frequency
4603                                  */
4604                                 if (fdiff <= 0) {
4605                                         if (hfrequency[ichain] <= 0 ||
4606                                             hfrequency[ichain] >= 100000 ||
4607                                             fdiff >
4608                                             (frequency - hfrequency[ichain])) {
4609                                                 /*
4610                                                  * new best higher
4611                                                  * frequency measurement
4612                                                  */
4613                                                 hfrequency[ichain] = pfrequency;
4614                                                 hcorrection[ichain] =
4615                                                     pcorrection;
4616                                                 htemperature[ichain] =
4617                                                     ptemperature;
4618                                                 hvoltage[ichain] = pvoltage;
4619                                         }
4620                                 }
4621                                 if (fdiff >= 0) {
4622                                         if (lfrequency[ichain] <= 0
4623                                             || fdiff <
4624                                             (frequency - lfrequency[ichain])) {
4625                                                 /*
4626                                                  * new best lower
4627                                                  * frequency measurement
4628                                                  */
4629                                                 lfrequency[ichain] = pfrequency;
4630                                                 lcorrection[ichain] =
4631                                                     pcorrection;
4632                                                 ltemperature[ichain] =
4633                                                     ptemperature;
4634                                                 lvoltage[ichain] = pvoltage;
4635                                         }
4636                                 }
4637                         }
4638                 }
4639         }
4640
4641         /* interpolate  */
4642         for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4643                 ath_dbg(common, ATH_DBG_EEPROM,
4644                         "ch=%d f=%d low=%d %d h=%d %d\n",
4645                         ichain, frequency, lfrequency[ichain],
4646                         lcorrection[ichain], hfrequency[ichain],
4647                         hcorrection[ichain]);
4648                 /* they're the same, so just pick one */
4649                 if (hfrequency[ichain] == lfrequency[ichain]) {
4650                         correction[ichain] = lcorrection[ichain];
4651                         voltage[ichain] = lvoltage[ichain];
4652                         temperature[ichain] = ltemperature[ichain];
4653                 }
4654                 /* the low frequency is good */
4655                 else if (frequency - lfrequency[ichain] < 1000) {
4656                         /* so is the high frequency, interpolate */
4657                         if (hfrequency[ichain] - frequency < 1000) {
4658
4659                                 correction[ichain] = interpolate(frequency,
4660                                                 lfrequency[ichain],
4661                                                 hfrequency[ichain],
4662                                                 lcorrection[ichain],
4663                                                 hcorrection[ichain]);
4664
4665                                 temperature[ichain] = interpolate(frequency,
4666                                                 lfrequency[ichain],
4667                                                 hfrequency[ichain],
4668                                                 ltemperature[ichain],
4669                                                 htemperature[ichain]);
4670
4671                                 voltage[ichain] = interpolate(frequency,
4672                                                 lfrequency[ichain],
4673                                                 hfrequency[ichain],
4674                                                 lvoltage[ichain],
4675                                                 hvoltage[ichain]);
4676                         }
4677                         /* only low is good, use it */
4678                         else {
4679                                 correction[ichain] = lcorrection[ichain];
4680                                 temperature[ichain] = ltemperature[ichain];
4681                                 voltage[ichain] = lvoltage[ichain];
4682                         }
4683                 }
4684                 /* only high is good, use it */
4685                 else if (hfrequency[ichain] - frequency < 1000) {
4686                         correction[ichain] = hcorrection[ichain];
4687                         temperature[ichain] = htemperature[ichain];
4688                         voltage[ichain] = hvoltage[ichain];
4689                 } else {        /* nothing is good, presume 0???? */
4690                         correction[ichain] = 0;
4691                         temperature[ichain] = 0;
4692                         voltage[ichain] = 0;
4693                 }
4694         }
4695
4696         ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4697                                          temperature);
4698
4699         ath_dbg(common, ATH_DBG_EEPROM,
4700                 "for frequency=%d, calibration correction = %d %d %d\n",
4701                 frequency, correction[0], correction[1], correction[2]);
4702
4703         return 0;
4704 }
4705
4706 static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4707                                            int idx,
4708                                            int edge,
4709                                            bool is2GHz)
4710 {
4711         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4712         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4713
4714         if (is2GHz)
4715                 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
4716         else
4717                 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
4718 }
4719
4720 static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4721                                              int idx,
4722                                              unsigned int edge,
4723                                              u16 freq,
4724                                              bool is2GHz)
4725 {
4726         struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4727         struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4728
4729         u8 *ctl_freqbin = is2GHz ?
4730                 &eep->ctl_freqbin_2G[idx][0] :
4731                 &eep->ctl_freqbin_5G[idx][0];
4732
4733         if (is2GHz) {
4734                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
4735                     CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4736                         return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
4737         } else {
4738                 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
4739                     CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4740                         return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
4741         }
4742
4743         return MAX_RATE_POWER;
4744 }
4745
4746 /*
4747  * Find the maximum conformance test limit for the given channel and CTL info
4748  */
4749 static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4750                                         u16 freq, int idx, bool is2GHz)
4751 {
4752         u16 twiceMaxEdgePower = MAX_RATE_POWER;
4753         u8 *ctl_freqbin = is2GHz ?
4754                 &eep->ctl_freqbin_2G[idx][0] :
4755                 &eep->ctl_freqbin_5G[idx][0];
4756         u16 num_edges = is2GHz ?
4757                 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4758         unsigned int edge;
4759
4760         /* Get the edge power */
4761         for (edge = 0;
4762              (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
4763              edge++) {
4764                 /*
4765                  * If there's an exact channel match or an inband flag set
4766                  * on the lower channel use the given rdEdgePower
4767                  */
4768                 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4769                         twiceMaxEdgePower =
4770                                 ar9003_hw_get_direct_edge_power(eep, idx,
4771                                                                 edge, is2GHz);
4772                         break;
4773                 } else if ((edge > 0) &&
4774                            (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4775                                                       is2GHz))) {
4776                         twiceMaxEdgePower =
4777                                 ar9003_hw_get_indirect_edge_power(eep, idx,
4778                                                                   edge, freq,
4779                                                                   is2GHz);
4780                         /*
4781                          * Leave loop - no more affecting edges possible in
4782                          * this monotonic increasing list
4783                          */
4784                         break;
4785                 }
4786         }
4787         return twiceMaxEdgePower;
4788 }
4789
4790 static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4791                                                struct ath9k_channel *chan,
4792                                                u8 *pPwrArray, u16 cfgCtl,
4793                                                u8 twiceAntennaReduction,
4794                                                u8 twiceMaxRegulatoryPower,
4795                                                u16 powerLimit)
4796 {
4797         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
4798         struct ath_common *common = ath9k_hw_common(ah);
4799         struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
4800         u16 twiceMaxEdgePower = MAX_RATE_POWER;
4801         static const u16 tpScaleReductionTable[5] = {
4802                 0, 3, 6, 9, MAX_RATE_POWER
4803         };
4804         int i;
4805         int16_t  twiceLargestAntenna;
4806         u16 scaledPower = 0, minCtlPower, maxRegAllowedPower;
4807         static const u16 ctlModesFor11a[] = {
4808                 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4809         };
4810         static const u16 ctlModesFor11g[] = {
4811                 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4812                 CTL_11G_EXT, CTL_2GHT40
4813         };
4814         u16 numCtlModes;
4815         const u16 *pCtlMode;
4816         u16 ctlMode, freq;
4817         struct chan_centers centers;
4818         u8 *ctlIndex;
4819         u8 ctlNum;
4820         u16 twiceMinEdgePower;
4821         bool is2ghz = IS_CHAN_2GHZ(chan);
4822
4823         ath9k_hw_get_channel_centers(ah, chan, &centers);
4824
4825         /* Compute TxPower reduction due to Antenna Gain */
4826         if (is2ghz)
4827                 twiceLargestAntenna = pEepData->modalHeader2G.antennaGain;
4828         else
4829                 twiceLargestAntenna = pEepData->modalHeader5G.antennaGain;
4830
4831         twiceLargestAntenna = (int16_t)min((twiceAntennaReduction) -
4832                                 twiceLargestAntenna, 0);
4833
4834         /*
4835          * scaledPower is the minimum of the user input power level
4836          * and the regulatory allowed power level
4837          */
4838         maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4839
4840         if (regulatory->tp_scale != ATH9K_TP_SCALE_MAX) {
4841                 maxRegAllowedPower -=
4842                         (tpScaleReductionTable[(regulatory->tp_scale)] * 2);
4843         }
4844
4845         scaledPower = min(powerLimit, maxRegAllowedPower);
4846
4847         /*
4848          * Reduce scaled Power by number of chains active to get
4849          * to per chain tx power level
4850          */
4851         switch (ar5416_get_ntxchains(ah->txchainmask)) {
4852         case 1:
4853                 break;
4854         case 2:
4855                 if (scaledPower > REDUCE_SCALED_POWER_BY_TWO_CHAIN)
4856                         scaledPower -= REDUCE_SCALED_POWER_BY_TWO_CHAIN;
4857                 else
4858                         scaledPower = 0;
4859                 break;
4860         case 3:
4861                 if (scaledPower > REDUCE_SCALED_POWER_BY_THREE_CHAIN)
4862                         scaledPower -= REDUCE_SCALED_POWER_BY_THREE_CHAIN;
4863                 else
4864                         scaledPower = 0;
4865                 break;
4866         }
4867
4868         scaledPower = max((u16)0, scaledPower);
4869
4870         /*
4871          * Get target powers from EEPROM - our baseline for TX Power
4872          */
4873         if (is2ghz) {
4874                 /* Setup for CTL modes */
4875                 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4876                 numCtlModes =
4877                         ARRAY_SIZE(ctlModesFor11g) -
4878                                    SUB_NUM_CTL_MODES_AT_2G_40;
4879                 pCtlMode = ctlModesFor11g;
4880                 if (IS_CHAN_HT40(chan))
4881                         /* All 2G CTL's */
4882                         numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4883         } else {
4884                 /* Setup for CTL modes */
4885                 /* CTL_11A, CTL_5GHT20 */
4886                 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4887                                          SUB_NUM_CTL_MODES_AT_5G_40;
4888                 pCtlMode = ctlModesFor11a;
4889                 if (IS_CHAN_HT40(chan))
4890                         /* All 5G CTL's */
4891                         numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4892         }
4893
4894         /*
4895          * For MIMO, need to apply regulatory caps individually across
4896          * dynamically running modes: CCK, OFDM, HT20, HT40
4897          *
4898          * The outer loop walks through each possible applicable runtime mode.
4899          * The inner loop walks through each ctlIndex entry in EEPROM.
4900          * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4901          */
4902         for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4903                 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4904                         (pCtlMode[ctlMode] == CTL_2GHT40);
4905                 if (isHt40CtlMode)
4906                         freq = centers.synth_center;
4907                 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4908                         freq = centers.ext_center;
4909                 else
4910                         freq = centers.ctl_center;
4911
4912                 ath_dbg(common, ATH_DBG_REGULATORY,
4913                         "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4914                         ctlMode, numCtlModes, isHt40CtlMode,
4915                         (pCtlMode[ctlMode] & EXT_ADDITIVE));
4916
4917                 /* walk through each CTL index stored in EEPROM */
4918                 if (is2ghz) {
4919                         ctlIndex = pEepData->ctlIndex_2G;
4920                         ctlNum = AR9300_NUM_CTLS_2G;
4921                 } else {
4922                         ctlIndex = pEepData->ctlIndex_5G;
4923                         ctlNum = AR9300_NUM_CTLS_5G;
4924                 }
4925
4926                 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
4927                         ath_dbg(common, ATH_DBG_REGULATORY,
4928                                 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4929                                 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4930                                 chan->channel);
4931
4932                                 /*
4933                                  * compare test group from regulatory
4934                                  * channel list with test mode from pCtlMode
4935                                  * list
4936                                  */
4937                                 if ((((cfgCtl & ~CTL_MODE_M) |
4938                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4939                                         ctlIndex[i]) ||
4940                                     (((cfgCtl & ~CTL_MODE_M) |
4941                                        (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4942                                      ((ctlIndex[i] & CTL_MODE_M) |
4943                                        SD_NO_CTL))) {
4944                                         twiceMinEdgePower =
4945                                           ar9003_hw_get_max_edge_power(pEepData,
4946                                                                        freq, i,
4947                                                                        is2ghz);
4948
4949                                         if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4950                                                 /*
4951                                                  * Find the minimum of all CTL
4952                                                  * edge powers that apply to
4953                                                  * this channel
4954                                                  */
4955                                                 twiceMaxEdgePower =
4956                                                         min(twiceMaxEdgePower,
4957                                                             twiceMinEdgePower);
4958                                                 else {
4959                                                         /* specific */
4960                                                         twiceMaxEdgePower =
4961                                                           twiceMinEdgePower;
4962                                                         break;
4963                                                 }
4964                                 }
4965                         }
4966
4967                         minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4968
4969                         ath_dbg(common, ATH_DBG_REGULATORY,
4970                                 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4971                                 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4972                                 scaledPower, minCtlPower);
4973
4974                         /* Apply ctl mode to correct target power set */
4975                         switch (pCtlMode[ctlMode]) {
4976                         case CTL_11B:
4977                                 for (i = ALL_TARGET_LEGACY_1L_5L;
4978                                      i <= ALL_TARGET_LEGACY_11S; i++)
4979                                         pPwrArray[i] =
4980                                           (u8)min((u16)pPwrArray[i],
4981                                                   minCtlPower);
4982                                 break;
4983                         case CTL_11A:
4984                         case CTL_11G:
4985                                 for (i = ALL_TARGET_LEGACY_6_24;
4986                                      i <= ALL_TARGET_LEGACY_54; i++)
4987                                         pPwrArray[i] =
4988                                           (u8)min((u16)pPwrArray[i],
4989                                                   minCtlPower);
4990                                 break;
4991                         case CTL_5GHT20:
4992                         case CTL_2GHT20:
4993                                 for (i = ALL_TARGET_HT20_0_8_16;
4994                                      i <= ALL_TARGET_HT20_21; i++)
4995                                         pPwrArray[i] =
4996                                           (u8)min((u16)pPwrArray[i],
4997                                                   minCtlPower);
4998                                 pPwrArray[ALL_TARGET_HT20_22] =
4999                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
5000                                           minCtlPower);
5001                                 pPwrArray[ALL_TARGET_HT20_23] =
5002                                   (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
5003                                            minCtlPower);
5004                                 break;
5005                         case CTL_5GHT40:
5006                         case CTL_2GHT40:
5007                                 for (i = ALL_TARGET_HT40_0_8_16;
5008                                      i <= ALL_TARGET_HT40_23; i++)
5009                                         pPwrArray[i] =
5010                                           (u8)min((u16)pPwrArray[i],
5011                                                   minCtlPower);
5012                                 break;
5013                         default:
5014                             break;
5015                         }
5016         } /* end ctl mode checking */
5017 }
5018
5019 static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
5020 {
5021         u8 mod_idx = mcs_idx % 8;
5022
5023         if (mod_idx <= 3)
5024                 return mod_idx ? (base_pwridx + 1) : base_pwridx;
5025         else
5026                 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
5027 }
5028
5029 static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
5030                                         struct ath9k_channel *chan, u16 cfgCtl,
5031                                         u8 twiceAntennaReduction,
5032                                         u8 twiceMaxRegulatoryPower,
5033                                         u8 powerLimit, bool test)
5034 {
5035         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
5036         struct ath_common *common = ath9k_hw_common(ah);
5037         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5038         struct ar9300_modal_eep_header *modal_hdr;
5039         u8 targetPowerValT2[ar9300RateSize];
5040         u8 target_power_val_t2_eep[ar9300RateSize];
5041         unsigned int i = 0, paprd_scale_factor = 0;
5042         u8 pwr_idx, min_pwridx = 0;
5043
5044         ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
5045
5046         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5047                 if (IS_CHAN_2GHZ(chan))
5048                         modal_hdr = &eep->modalHeader2G;
5049                 else
5050                         modal_hdr = &eep->modalHeader5G;
5051
5052                 ah->paprd_ratemask =
5053                         le32_to_cpu(modal_hdr->papdRateMaskHt20) &
5054                         AR9300_PAPRD_RATE_MASK;
5055
5056                 ah->paprd_ratemask_ht40 =
5057                         le32_to_cpu(modal_hdr->papdRateMaskHt40) &
5058                         AR9300_PAPRD_RATE_MASK;
5059
5060                 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
5061                 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
5062                                                   ALL_TARGET_HT20_0_8_16;
5063
5064                 if (!ah->paprd_table_write_done) {
5065                         memcpy(target_power_val_t2_eep, targetPowerValT2,
5066                                sizeof(targetPowerValT2));
5067                         for (i = 0; i < 24; i++) {
5068                                 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
5069                                 if (ah->paprd_ratemask & (1 << i)) {
5070                                         if (targetPowerValT2[pwr_idx] &&
5071                                             targetPowerValT2[pwr_idx] ==
5072                                             target_power_val_t2_eep[pwr_idx])
5073                                                 targetPowerValT2[pwr_idx] -=
5074                                                         paprd_scale_factor;
5075                                 }
5076                         }
5077                 }
5078                 memcpy(target_power_val_t2_eep, targetPowerValT2,
5079                        sizeof(targetPowerValT2));
5080         }
5081
5082         ar9003_hw_set_power_per_rate_table(ah, chan,
5083                                            targetPowerValT2, cfgCtl,
5084                                            twiceAntennaReduction,
5085                                            twiceMaxRegulatoryPower,
5086                                            powerLimit);
5087
5088         if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
5089                 for (i = 0; i < ar9300RateSize; i++) {
5090                         if ((ah->paprd_ratemask & (1 << i)) &&
5091                             (abs(targetPowerValT2[i] -
5092                                 target_power_val_t2_eep[i]) >
5093                             paprd_scale_factor)) {
5094                                 ah->paprd_ratemask &= ~(1 << i);
5095                                 ath_dbg(common, ATH_DBG_EEPROM,
5096                                         "paprd disabled for mcs %d\n", i);
5097                         }
5098                 }
5099         }
5100
5101         regulatory->max_power_level = 0;
5102         for (i = 0; i < ar9300RateSize; i++) {
5103                 if (targetPowerValT2[i] > regulatory->max_power_level)
5104                         regulatory->max_power_level = targetPowerValT2[i];
5105         }
5106
5107         if (test)
5108                 return;
5109
5110         for (i = 0; i < ar9300RateSize; i++) {
5111                 ath_dbg(common, ATH_DBG_EEPROM,
5112                         "TPC[%02d] 0x%08x\n", i, targetPowerValT2[i]);
5113         }
5114
5115         ah->txpower_limit = regulatory->max_power_level;
5116
5117         /* Write target power array to registers */
5118         ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
5119         ar9003_hw_calibration_apply(ah, chan->channel);
5120
5121         if (IS_CHAN_2GHZ(chan)) {
5122                 if (IS_CHAN_HT40(chan))
5123                         i = ALL_TARGET_HT40_0_8_16;
5124                 else
5125                         i = ALL_TARGET_HT20_0_8_16;
5126         } else {
5127                 if (IS_CHAN_HT40(chan))
5128                         i = ALL_TARGET_HT40_7;
5129                 else
5130                         i = ALL_TARGET_HT20_7;
5131         }
5132         ah->paprd_target_power = targetPowerValT2[i];
5133 }
5134
5135 static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5136                                             u16 i, bool is2GHz)
5137 {
5138         return AR_NO_SPUR;
5139 }
5140
5141 s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5142 {
5143         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5144
5145         return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5146 }
5147
5148 s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5149 {
5150         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5151
5152         return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5153 }
5154
5155 u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
5156 {
5157         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5158
5159         if (is_2ghz)
5160                 return eep->modalHeader2G.spurChans;
5161         else
5162                 return eep->modalHeader5G.spurChans;
5163 }
5164
5165 unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5166                                            struct ath9k_channel *chan)
5167 {
5168         struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5169
5170         if (IS_CHAN_2GHZ(chan))
5171                 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5172                           AR9300_PAPRD_SCALE_1);
5173         else {
5174                 if (chan->channel >= 5700)
5175                 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5176                           AR9300_PAPRD_SCALE_1);
5177                 else if (chan->channel >= 5400)
5178                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5179                                    AR9300_PAPRD_SCALE_2);
5180                 else
5181                         return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5182                                   AR9300_PAPRD_SCALE_1);
5183         }
5184 }
5185
5186 const struct eeprom_ops eep_ar9300_ops = {
5187         .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5188         .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5189         .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
5190         .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
5191         .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5192         .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
5193         .set_board_values = ath9k_hw_ar9300_set_board_values,
5194         .set_addac = ath9k_hw_ar9300_set_addac,
5195         .set_txpower = ath9k_hw_ar9300_set_txpower,
5196         .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5197 };