2 * Copyright (c) 2008-2010 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * DOC: Programming Atheros 802.11n analog front end radios
20 * AR5416 MAC based PCI devices and AR518 MAC based PCI-Express
21 * devices have either an external AR2133 analog front end radio for single
22 * band 2.4 GHz communication or an AR5133 analog front end radio for dual
23 * band 2.4 GHz / 5 GHz communication.
25 * All devices after the AR5416 and AR5418 family starting with the AR9280
26 * have their analog front radios, MAC/BB and host PCIe/USB interface embedded
27 * into a single-chip and require less programming.
29 * The following single-chips exist with a respective embedded radio:
31 * AR9280 - 11n dual-band 2x2 MIMO for PCIe
32 * AR9281 - 11n single-band 1x2 MIMO for PCIe
33 * AR9285 - 11n single-band 1x1 for PCIe
34 * AR9287 - 11n single-band 2x2 MIMO for PCIe
36 * AR9220 - 11n dual-band 2x2 MIMO for PCI
37 * AR9223 - 11n single-band 2x2 MIMO for PCI
39 * AR9287 - 11n single-band 1x1 MIMO for USB
43 #include "ar9002_phy.h"
46 * ar9002_hw_set_channel - set channel on single-chip device
47 * @ah: atheros hardware structure
50 * This is the function to change channel on single-chip devices, that is
51 * all devices after ar9280.
53 * This function takes the channel value in MHz and sets
54 * hardware channel value. Assumes writes have been enabled to analog bus.
59 * Channel Frequency = (3/4) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^17)
63 * Channel Frequency = (3/2) * freq_ref * (chansel[8:0] + chanfrac[16:0]/2^10)
64 * (freq_ref = 40MHz/(24>>amodeRefSel))
66 static int ar9002_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
68 u16 bMode, fracMode, aModeRefSel = 0;
69 u32 freq, ndiv, channelSel = 0, channelFrac = 0, reg32 = 0;
70 struct chan_centers centers;
73 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
74 freq = centers.synth_center;
76 reg32 = REG_READ(ah, AR_PHY_SYNTH_CONTROL);
79 if (freq < 4800) { /* 2 GHz, fractional mode */
86 channelSel = CHANSEL_2G(freq);
88 if (AR_SREV_9287_11_OR_LATER(ah)) {
90 /* Enable channel spreading for channel 14 */
91 REG_WRITE_ARRAY(&ah->iniCckfirJapan2484,
94 REG_WRITE_ARRAY(&ah->iniCckfirNormal,
98 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
100 /* Enable channel spreading for channel 14 */
101 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
102 txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
104 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
105 txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
112 switch (ah->eep_ops->get_eeprom(ah, EEP_FRAC_N_5G)) {
114 if ((freq % 20) == 0)
116 else if ((freq % 10) == 0)
124 * Enable 2G (fractional) mode for channels
125 * which are 5MHz spaced.
129 channelSel = CHANSEL_5G(freq);
131 /* RefDivA setting */
132 REG_RMW_FIELD(ah, AR_AN_SYNTH9,
133 AR_AN_SYNTH9_REFDIVA, refDivA);
138 ndiv = (freq * (refDivA >> aModeRefSel)) / 60;
139 channelSel = ndiv & 0x1ff;
140 channelFrac = (ndiv & 0xfffffe00) * 2;
141 channelSel = (channelSel << 17) | channelFrac;
147 (fracMode << 28) | (aModeRefSel << 26) | (channelSel);
149 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32);
152 ah->curchan_rad_index = -1;
158 * ar9002_hw_spur_mitigate - convert baseband spur frequency
159 * @ah: atheros hardware structure
162 * For single-chip solutions. Converts to baseband spur frequency given the
163 * input channel frequency and compute register settings below.
165 static void ar9002_hw_spur_mitigate(struct ath_hw *ah,
166 struct ath9k_channel *chan)
168 int bb_spur = AR_NO_SPUR;
171 int bb_spur_off, spur_subchannel_sd;
173 int spur_delta_phase;
175 int upper, lower, cur_vit_mask;
178 static const int pilot_mask_reg[4] = {
179 AR_PHY_TIMING7, AR_PHY_TIMING8,
180 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
182 static const int chan_mask_reg[4] = {
183 AR_PHY_TIMING9, AR_PHY_TIMING10,
184 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
186 static const int inc[4] = { 0, 100, 0, 0 };
187 struct chan_centers centers;
194 bool is2GHz = IS_CHAN_2GHZ(chan);
196 memset(&mask_m, 0, sizeof(int8_t) * 123);
197 memset(&mask_p, 0, sizeof(int8_t) * 123);
199 ath9k_hw_get_channel_centers(ah, chan, ¢ers);
200 freq = centers.synth_center;
202 ah->config.spurmode = SPUR_ENABLE_EEPROM;
203 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
204 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
207 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
209 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
211 if (AR_NO_SPUR == cur_bb_spur)
213 cur_bb_spur = cur_bb_spur - freq;
215 if (IS_CHAN_HT40(chan)) {
216 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
217 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
218 bb_spur = cur_bb_spur;
221 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
222 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
223 bb_spur = cur_bb_spur;
228 if (AR_NO_SPUR == bb_spur) {
229 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
230 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
233 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
234 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
239 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
241 ENABLE_REGWRITE_BUFFER(ah);
243 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
244 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
245 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
246 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
247 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
249 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
250 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
251 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
252 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
253 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
254 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
256 if (IS_CHAN_HT40(chan)) {
258 spur_subchannel_sd = 1;
259 bb_spur_off = bb_spur + 10;
261 spur_subchannel_sd = 0;
262 bb_spur_off = bb_spur - 10;
265 spur_subchannel_sd = 0;
266 bb_spur_off = bb_spur;
269 if (IS_CHAN_HT40(chan))
271 ((bb_spur * 262144) /
272 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
275 ((bb_spur * 524288) /
276 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
278 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
279 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
281 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
282 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
283 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
284 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
286 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
287 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
293 for (i = 0; i < 4; i++) {
297 for (bp = 0; bp < 30; bp++) {
298 if ((cur_bin > lower) && (cur_bin < upper)) {
299 pilot_mask = pilot_mask | 0x1 << bp;
300 chan_mask = chan_mask | 0x1 << bp;
305 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
306 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
313 for (i = 0; i < 123; i++) {
314 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
316 /* workaround for gcc bug #37014 */
317 volatile int tmp_v = abs(cur_vit_mask - bin);
323 if (cur_vit_mask < 0)
324 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
326 mask_p[cur_vit_mask / 100] = mask_amt;
331 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
332 | (mask_m[48] << 26) | (mask_m[49] << 24)
333 | (mask_m[50] << 22) | (mask_m[51] << 20)
334 | (mask_m[52] << 18) | (mask_m[53] << 16)
335 | (mask_m[54] << 14) | (mask_m[55] << 12)
336 | (mask_m[56] << 10) | (mask_m[57] << 8)
337 | (mask_m[58] << 6) | (mask_m[59] << 4)
338 | (mask_m[60] << 2) | (mask_m[61] << 0);
339 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
340 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
342 tmp_mask = (mask_m[31] << 28)
343 | (mask_m[32] << 26) | (mask_m[33] << 24)
344 | (mask_m[34] << 22) | (mask_m[35] << 20)
345 | (mask_m[36] << 18) | (mask_m[37] << 16)
346 | (mask_m[48] << 14) | (mask_m[39] << 12)
347 | (mask_m[40] << 10) | (mask_m[41] << 8)
348 | (mask_m[42] << 6) | (mask_m[43] << 4)
349 | (mask_m[44] << 2) | (mask_m[45] << 0);
350 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
351 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
353 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
354 | (mask_m[18] << 26) | (mask_m[18] << 24)
355 | (mask_m[20] << 22) | (mask_m[20] << 20)
356 | (mask_m[22] << 18) | (mask_m[22] << 16)
357 | (mask_m[24] << 14) | (mask_m[24] << 12)
358 | (mask_m[25] << 10) | (mask_m[26] << 8)
359 | (mask_m[27] << 6) | (mask_m[28] << 4)
360 | (mask_m[29] << 2) | (mask_m[30] << 0);
361 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
362 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
364 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
365 | (mask_m[2] << 26) | (mask_m[3] << 24)
366 | (mask_m[4] << 22) | (mask_m[5] << 20)
367 | (mask_m[6] << 18) | (mask_m[7] << 16)
368 | (mask_m[8] << 14) | (mask_m[9] << 12)
369 | (mask_m[10] << 10) | (mask_m[11] << 8)
370 | (mask_m[12] << 6) | (mask_m[13] << 4)
371 | (mask_m[14] << 2) | (mask_m[15] << 0);
372 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
373 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
375 tmp_mask = (mask_p[15] << 28)
376 | (mask_p[14] << 26) | (mask_p[13] << 24)
377 | (mask_p[12] << 22) | (mask_p[11] << 20)
378 | (mask_p[10] << 18) | (mask_p[9] << 16)
379 | (mask_p[8] << 14) | (mask_p[7] << 12)
380 | (mask_p[6] << 10) | (mask_p[5] << 8)
381 | (mask_p[4] << 6) | (mask_p[3] << 4)
382 | (mask_p[2] << 2) | (mask_p[1] << 0);
383 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
384 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
386 tmp_mask = (mask_p[30] << 28)
387 | (mask_p[29] << 26) | (mask_p[28] << 24)
388 | (mask_p[27] << 22) | (mask_p[26] << 20)
389 | (mask_p[25] << 18) | (mask_p[24] << 16)
390 | (mask_p[23] << 14) | (mask_p[22] << 12)
391 | (mask_p[21] << 10) | (mask_p[20] << 8)
392 | (mask_p[19] << 6) | (mask_p[18] << 4)
393 | (mask_p[17] << 2) | (mask_p[16] << 0);
394 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
395 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
397 tmp_mask = (mask_p[45] << 28)
398 | (mask_p[44] << 26) | (mask_p[43] << 24)
399 | (mask_p[42] << 22) | (mask_p[41] << 20)
400 | (mask_p[40] << 18) | (mask_p[39] << 16)
401 | (mask_p[38] << 14) | (mask_p[37] << 12)
402 | (mask_p[36] << 10) | (mask_p[35] << 8)
403 | (mask_p[34] << 6) | (mask_p[33] << 4)
404 | (mask_p[32] << 2) | (mask_p[31] << 0);
405 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
406 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
408 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
409 | (mask_p[59] << 26) | (mask_p[58] << 24)
410 | (mask_p[57] << 22) | (mask_p[56] << 20)
411 | (mask_p[55] << 18) | (mask_p[54] << 16)
412 | (mask_p[53] << 14) | (mask_p[52] << 12)
413 | (mask_p[51] << 10) | (mask_p[50] << 8)
414 | (mask_p[49] << 6) | (mask_p[48] << 4)
415 | (mask_p[47] << 2) | (mask_p[46] << 0);
416 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
417 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
419 REGWRITE_BUFFER_FLUSH(ah);
422 static void ar9002_olc_init(struct ath_hw *ah)
426 if (!OLC_FOR_AR9280_20_LATER)
429 if (OLC_FOR_AR9287_10_LATER) {
430 REG_SET_BIT(ah, AR_PHY_TX_PWRCTRL9,
431 AR_PHY_TX_PWRCTRL9_RES_DC_REMOVAL);
432 ath9k_hw_analog_shift_rmw(ah, AR9287_AN_TXPC0,
433 AR9287_AN_TXPC0_TXPCMODE,
434 AR9287_AN_TXPC0_TXPCMODE_S,
435 AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE);
438 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
439 ah->originalGain[i] =
440 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
446 static u32 ar9002_hw_compute_pll_control(struct ath_hw *ah,
447 struct ath9k_channel *chan)
451 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
453 if (chan && IS_CHAN_HALF_RATE(chan))
454 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
455 else if (chan && IS_CHAN_QUARTER_RATE(chan))
456 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
458 if (chan && IS_CHAN_5GHZ(chan)) {
459 if (IS_CHAN_A_FAST_CLOCK(ah, chan))
461 else if (AR_SREV_9280_20(ah))
464 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
466 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
472 static void ar9002_hw_do_getnf(struct ath_hw *ah,
473 int16_t nfarray[NUM_NF_READINGS])
477 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
478 nfarray[0] = sign_extend32(nf, 8);
480 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR);
481 if (IS_CHAN_HT40(ah->curchan))
482 nfarray[3] = sign_extend32(nf, 8);
484 if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
487 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR);
488 nfarray[1] = sign_extend32(nf, 8);
490 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR);
491 if (IS_CHAN_HT40(ah->curchan))
492 nfarray[4] = sign_extend32(nf, 8);
495 static void ar9002_hw_set_nf_limits(struct ath_hw *ah)
497 if (AR_SREV_9285(ah)) {
498 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9285_2GHZ;
499 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9285_2GHZ;
500 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9285_2GHZ;
501 } else if (AR_SREV_9287(ah)) {
502 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9287_2GHZ;
503 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9287_2GHZ;
504 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9287_2GHZ;
505 } else if (AR_SREV_9271(ah)) {
506 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9271_2GHZ;
507 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9271_2GHZ;
508 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9271_2GHZ;
510 ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_2GHZ;
511 ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_2GHZ;
512 ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_9280_2GHZ;
513 ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9280_5GHZ;
514 ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_9280_5GHZ;
515 ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_9280_5GHZ;
519 void ar9002_hw_attach_phy_ops(struct ath_hw *ah)
521 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
523 priv_ops->set_rf_regs = NULL;
524 priv_ops->rf_alloc_ext_banks = NULL;
525 priv_ops->rf_free_ext_banks = NULL;
526 priv_ops->rf_set_freq = ar9002_hw_set_channel;
527 priv_ops->spur_mitigate_freq = ar9002_hw_spur_mitigate;
528 priv_ops->olc_init = ar9002_olc_init;
529 priv_ops->compute_pll_control = ar9002_hw_compute_pll_control;
530 priv_ops->do_getnf = ar9002_hw_do_getnf;
532 ar9002_hw_set_nf_limits(ah);
535 void ath9k_hw_antdiv_comb_conf_get(struct ath_hw *ah,
536 struct ath_hw_antcomb_conf *antconf)
540 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
541 antconf->main_lna_conf = (regval & AR_PHY_9285_ANT_DIV_MAIN_LNACONF) >>
542 AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S;
543 antconf->alt_lna_conf = (regval & AR_PHY_9285_ANT_DIV_ALT_LNACONF) >>
544 AR_PHY_9285_ANT_DIV_ALT_LNACONF_S;
545 antconf->fast_div_bias = (regval & AR_PHY_9285_FAST_DIV_BIAS) >>
546 AR_PHY_9285_FAST_DIV_BIAS_S;
548 EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_get);
550 void ath9k_hw_antdiv_comb_conf_set(struct ath_hw *ah,
551 struct ath_hw_antcomb_conf *antconf)
555 regval = REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL);
556 regval &= ~(AR_PHY_9285_ANT_DIV_MAIN_LNACONF |
557 AR_PHY_9285_ANT_DIV_ALT_LNACONF |
558 AR_PHY_9285_FAST_DIV_BIAS);
559 regval |= ((antconf->main_lna_conf << AR_PHY_9285_ANT_DIV_MAIN_LNACONF_S)
560 & AR_PHY_9285_ANT_DIV_MAIN_LNACONF);
561 regval |= ((antconf->alt_lna_conf << AR_PHY_9285_ANT_DIV_ALT_LNACONF_S)
562 & AR_PHY_9285_ANT_DIV_ALT_LNACONF);
563 regval |= ((antconf->fast_div_bias << AR_PHY_9285_FAST_DIV_BIAS_S)
564 & AR_PHY_9285_FAST_DIV_BIAS);
566 REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regval);
568 EXPORT_SYMBOL(ath9k_hw_antdiv_comb_conf_set);