drivers/net/wireless/ath/ath9k/ar5008_phy.c

   1 /*
   2  * Copyright (c) 2008-2010 Atheros Communications Inc.
   3  *
   4  * Permission to use, copy, modify, and/or distribute this software for any
   5  * purpose with or without fee is hereby granted, provided that the above
   6  * copyright notice and this permission notice appear in all copies.
   7  *
   8  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15  */
  16
  17 #include "hw.h"
  18 #include "hw-ops.h"
  19 #include "../regd.h"
  20 #include "ar9002_phy.h"
  21
  22 /* All code below is for AR5008, AR9001, AR9002 */
  23
  24 static const int firstep_table[] =
  25 /* level:  0   1   2   3   4   5   6   7   8  */
  26         { -4, -2,  0,  2,  4,  6,  8, 10, 12 }; /* lvl 0-8, default 2 */
  27
  28 static const int cycpwrThr1_table[] =
  29 /* level:  0   1   2   3   4   5   6   7   8  */
  30         { -6, -4, -2,  0,  2,  4,  6,  8 };     /* lvl 0-7, default 3 */
  31
  32 /*
  33  * register values to turn OFDM weak signal detection OFF
  34  */
  35 static const int m1ThreshLow_off = 127;
  36 static const int m2ThreshLow_off = 127;
  37 static const int m1Thresh_off = 127;
  38 static const int m2Thresh_off = 127;
  39 static const int m2CountThr_off =  31;
  40 static const int m2CountThrLow_off =  63;
  41 static const int m1ThreshLowExt_off = 127;
  42 static const int m2ThreshLowExt_off = 127;
  43 static const int m1ThreshExt_off = 127;
  44 static const int m2ThreshExt_off = 127;
  45
  46
  47 /**
  48  * ar5008_hw_phy_modify_rx_buffer() - perform analog swizzling of parameters
  49  * @rfbuf:
  50  * @reg32:
  51  * @numBits:
  52  * @firstBit:
  53  * @column:
  54  *
  55  * Performs analog "swizzling" of parameters into their location.
  56  * Used on external AR2133/AR5133 radios.
  57  */
  58 static void ar5008_hw_phy_modify_rx_buffer(u32 *rfBuf, u32 reg32,
  59                                            u32 numBits, u32 firstBit,
  60                                            u32 column)
  61 {
  62         u32 tmp32, mask, arrayEntry, lastBit;
  63         int32_t bitPosition, bitsLeft;
  64
  65         tmp32 = ath9k_hw_reverse_bits(reg32, numBits);
  66         arrayEntry = (firstBit - 1) / 8;
  67         bitPosition = (firstBit - 1) % 8;
  68         bitsLeft = numBits;
  69         while (bitsLeft > 0) {
  70                 lastBit = (bitPosition + bitsLeft > 8) ?
  71                     8 : bitPosition + bitsLeft;
  72                 mask = (((1 << lastBit) - 1) ^ ((1 << bitPosition) - 1)) <<
  73                     (column * 8);
  74                 rfBuf[arrayEntry] &= ~mask;
  75                 rfBuf[arrayEntry] |= ((tmp32 << bitPosition) <<
  76                                       (column * 8)) & mask;
  77                 bitsLeft -= 8 - bitPosition;
  78                 tmp32 = tmp32 >> (8 - bitPosition);
  79                 bitPosition = 0;
  80                 arrayEntry++;
  81         }
  82 }
  83
  84 /*
  85  * Fix on 2.4 GHz band for orientation sensitivity issue by increasing
  86  * rf_pwd_icsyndiv.
  87  *
  88  * Theoretical Rules:
  89  *   if 2 GHz band
  90  *      if forceBiasAuto
  91  *         if synth_freq < 2412
  92  *            bias = 0
  93  *         else if 2412 <= synth_freq <= 2422
  94  *            bias = 1
  95  *         else // synth_freq > 2422
  96  *            bias = 2
  97  *      else if forceBias > 0
  98  *         bias = forceBias & 7
  99  *      else
 100  *         no change, use value from ini file
 101  *   else
 102  *      no change, invalid band
 103  *
 104  *  1st Mod:
 105  *    2422 also uses value of 2
 106  *    <approved>
 107  *
 108  *  2nd Mod:
 109  *    Less than 2412 uses value of 0, 2412 and above uses value of 2
 110  */
 111 static void ar5008_hw_force_bias(struct ath_hw *ah, u16 synth_freq)
 112 {
 113         struct ath_common *common = ath9k_hw_common(ah);
 114         u32 tmp_reg;
 115         int reg_writes = 0;
 116         u32 new_bias = 0;
 117
 118         if (!AR_SREV_5416(ah) || synth_freq >= 3000)
 119                 return;
 120
 121         BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 122
 123         if (synth_freq < 2412)
 124                 new_bias = 0;
 125         else if (synth_freq < 2422)
 126                 new_bias = 1;
 127         else
 128                 new_bias = 2;
 129
 130         /* pre-reverse this field */
 131         tmp_reg = ath9k_hw_reverse_bits(new_bias, 3);
 132
 133         ath_print(common, ATH_DBG_CONFIG,
 134                   "Force rf_pwd_icsyndiv to %1d on %4d\n",
 135                   new_bias, synth_freq);
 136
 137         /* swizzle rf_pwd_icsyndiv */
 138         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data, tmp_reg, 3, 181, 3);
 139
 140         /* write Bank 6 with new params */
 141         REG_WRITE_RF_ARRAY(&ah->iniBank6, ah->analogBank6Data, reg_writes);
 142 }
 143
 144 /**
 145  * ar5008_hw_set_channel - tune to a channel on the external AR2133/AR5133 radios
 146  * @ah: atheros hardware stucture
 147  * @chan:
 148  *
 149  * For the external AR2133/AR5133 radios, takes the MHz channel value and set
 150  * the channel value. Assumes writes enabled to analog bus and bank6 register
 151  * cache in ah->analogBank6Data.
 152  */
 153 static int ar5008_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
 154 {
 155         struct ath_common *common = ath9k_hw_common(ah);
 156         u32 channelSel = 0;
 157         u32 bModeSynth = 0;
 158         u32 aModeRefSel = 0;
 159         u32 reg32 = 0;
 160         u16 freq;
 161         struct chan_centers centers;
 162
 163         ath9k_hw_get_channel_centers(ah, chan, &centers);
 164         freq = centers.synth_center;
 165
 166         if (freq < 4800) {
 167                 u32 txctl;
 168
 169                 if (((freq - 2192) % 5) == 0) {
 170                         channelSel = ((freq - 672) * 2 - 3040) / 10;
 171                         bModeSynth = 0;
 172                 } else if (((freq - 2224) % 5) == 0) {
 173                         channelSel = ((freq - 704) * 2 - 3040) / 10;
 174                         bModeSynth = 1;
 175                 } else {
 176                         ath_print(common, ATH_DBG_FATAL,
 177                                   "Invalid channel %u MHz\n", freq);
 178                         return -EINVAL;
 179                 }
 180
 181                 channelSel = (channelSel << 2) & 0xff;
 182                 channelSel = ath9k_hw_reverse_bits(channelSel, 8);
 183
 184                 txctl = REG_READ(ah, AR_PHY_CCK_TX_CTRL);
 185                 if (freq == 2484) {
 186
 187                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 188                                   txctl | AR_PHY_CCK_TX_CTRL_JAPAN);
 189                 } else {
 190                         REG_WRITE(ah, AR_PHY_CCK_TX_CTRL,
 191                                   txctl & ~AR_PHY_CCK_TX_CTRL_JAPAN);
 192                 }
 193
 194         } else if ((freq % 20) == 0 && freq >= 5120) {
 195                 channelSel =
 196                     ath9k_hw_reverse_bits(((freq - 4800) / 20 << 2), 8);
 197                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
 198         } else if ((freq % 10) == 0) {
 199                 channelSel =
 200                     ath9k_hw_reverse_bits(((freq - 4800) / 10 << 1), 8);
 201                 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah))
 202                         aModeRefSel = ath9k_hw_reverse_bits(2, 2);
 203                 else
 204                         aModeRefSel = ath9k_hw_reverse_bits(1, 2);
 205         } else if ((freq % 5) == 0) {
 206                 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
 207                 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
 208         } else {
 209                 ath_print(common, ATH_DBG_FATAL,
 210                           "Invalid channel %u MHz\n", freq);
 211                 return -EINVAL;
 212         }
 213
 214         ar5008_hw_force_bias(ah, freq);
 215
 216         reg32 =
 217             (channelSel << 8) | (aModeRefSel << 2) | (bModeSynth << 1) |
 218             (1 << 5) | 0x1;
 219
 220         REG_WRITE(ah, AR_PHY(0x37), reg32);
 221
 222         ah->curchan = chan;
 223         ah->curchan_rad_index = -1;
 224
 225         return 0;
 226 }
 227
 228 /**
 229  * ar5008_hw_spur_mitigate - convert baseband spur frequency for external radios
 230  * @ah: atheros hardware structure
 231  * @chan:
 232  *
 233  * For non single-chip solutions. Converts to baseband spur frequency given the
 234  * input channel frequency and compute register settings below.
 235  */
 236 static void ar5008_hw_spur_mitigate(struct ath_hw *ah,
 237                                     struct ath9k_channel *chan)
 238 {
 239         int bb_spur = AR_NO_SPUR;
 240         int bin, cur_bin;
 241         int spur_freq_sd;
 242         int spur_delta_phase;
 243         int denominator;
 244         int upper, lower, cur_vit_mask;
 245         int tmp, new;
 246         int i;
 247         int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
 248                           AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
 249         };
 250         int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
 251                          AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
 252         };
 253         int inc[4] = { 0, 100, 0, 0 };
 254
 255         int8_t mask_m[123];
 256         int8_t mask_p[123];
 257         int8_t mask_amt;
 258         int tmp_mask;
 259         int cur_bb_spur;
 260         bool is2GHz = IS_CHAN_2GHZ(chan);
 261
 262         memset(&mask_m, 0, sizeof(int8_t) * 123);
 263         memset(&mask_p, 0, sizeof(int8_t) * 123);
 264
 265         for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
 266                 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
 267                 if (AR_NO_SPUR == cur_bb_spur)
 268                         break;
 269                 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
 270                 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
 271                         bb_spur = cur_bb_spur;
 272                         break;
 273                 }
 274         }
 275
 276         if (AR_NO_SPUR == bb_spur)
 277                 return;
 278
 279         bin = bb_spur * 32;
 280
 281         tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
 282         new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
 283                      AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
 284                      AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
 285                      AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
 286
 287         REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
 288
 289         new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
 290                AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
 291                AR_PHY_SPUR_REG_MASK_RATE_SELECT |
 292                AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
 293                SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
 294         REG_WRITE(ah, AR_PHY_SPUR_REG, new);
 295
 296         spur_delta_phase = ((bb_spur * 524288) / 100) &
 297                 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
 298
 299         denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
 300         spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
 301
 302         new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
 303                SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
 304                SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
 305         REG_WRITE(ah, AR_PHY_TIMING11, new);
 306
 307         cur_bin = -6000;
 308         upper = bin + 100;
 309         lower = bin - 100;
 310
 311         for (i = 0; i < 4; i++) {
 312                 int pilot_mask = 0;
 313                 int chan_mask = 0;
 314                 int bp = 0;
 315                 for (bp = 0; bp < 30; bp++) {
 316                         if ((cur_bin > lower) && (cur_bin < upper)) {
 317                                 pilot_mask = pilot_mask | 0x1 << bp;
 318                                 chan_mask = chan_mask | 0x1 << bp;
 319                         }
 320                         cur_bin += 100;
 321                 }
 322                 cur_bin += inc[i];
 323                 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
 324                 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
 325         }
 326
 327         cur_vit_mask = 6100;
 328         upper = bin + 120;
 329         lower = bin - 120;
 330
 331         for (i = 0; i < 123; i++) {
 332                 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
 333
 334                         /* workaround for gcc bug #37014 */
 335                         volatile int tmp_v = abs(cur_vit_mask - bin);
 336
 337                         if (tmp_v < 75)
 338                                 mask_amt = 1;
 339                         else
 340                                 mask_amt = 0;
 341                         if (cur_vit_mask < 0)
 342                                 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
 343                         else
 344                                 mask_p[cur_vit_mask / 100] = mask_amt;
 345                 }
 346                 cur_vit_mask -= 100;
 347         }
 348
 349         tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
 350                 | (mask_m[48] << 26) | (mask_m[49] << 24)
 351                 | (mask_m[50] << 22) | (mask_m[51] << 20)
 352                 | (mask_m[52] << 18) | (mask_m[53] << 16)
 353                 | (mask_m[54] << 14) | (mask_m[55] << 12)
 354                 | (mask_m[56] << 10) | (mask_m[57] << 8)
 355                 | (mask_m[58] << 6) | (mask_m[59] << 4)
 356                 | (mask_m[60] << 2) | (mask_m[61] << 0);
 357         REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
 358         REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
 359
 360         tmp_mask = (mask_m[31] << 28)
 361                 | (mask_m[32] << 26) | (mask_m[33] << 24)
 362                 | (mask_m[34] << 22) | (mask_m[35] << 20)
 363                 | (mask_m[36] << 18) | (mask_m[37] << 16)
 364                 | (mask_m[48] << 14) | (mask_m[39] << 12)
 365                 | (mask_m[40] << 10) | (mask_m[41] << 8)
 366                 | (mask_m[42] << 6) | (mask_m[43] << 4)
 367                 | (mask_m[44] << 2) | (mask_m[45] << 0);
 368         REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
 369         REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
 370
 371         tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
 372                 | (mask_m[18] << 26) | (mask_m[18] << 24)
 373                 | (mask_m[20] << 22) | (mask_m[20] << 20)
 374                 | (mask_m[22] << 18) | (mask_m[22] << 16)
 375                 | (mask_m[24] << 14) | (mask_m[24] << 12)
 376                 | (mask_m[25] << 10) | (mask_m[26] << 8)
 377                 | (mask_m[27] << 6) | (mask_m[28] << 4)
 378                 | (mask_m[29] << 2) | (mask_m[30] << 0);
 379         REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
 380         REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
 381
 382         tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
 383                 | (mask_m[2] << 26) | (mask_m[3] << 24)
 384                 | (mask_m[4] << 22) | (mask_m[5] << 20)
 385                 | (mask_m[6] << 18) | (mask_m[7] << 16)
 386                 | (mask_m[8] << 14) | (mask_m[9] << 12)
 387                 | (mask_m[10] << 10) | (mask_m[11] << 8)
 388                 | (mask_m[12] << 6) | (mask_m[13] << 4)
 389                 | (mask_m[14] << 2) | (mask_m[15] << 0);
 390         REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
 391         REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
 392
 393         tmp_mask = (mask_p[15] << 28)
 394                 | (mask_p[14] << 26) | (mask_p[13] << 24)
 395                 | (mask_p[12] << 22) | (mask_p[11] << 20)
 396                 | (mask_p[10] << 18) | (mask_p[9] << 16)
 397                 | (mask_p[8] << 14) | (mask_p[7] << 12)
 398                 | (mask_p[6] << 10) | (mask_p[5] << 8)
 399                 | (mask_p[4] << 6) | (mask_p[3] << 4)
 400                 | (mask_p[2] << 2) | (mask_p[1] << 0);
 401         REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
 402         REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
 403
 404         tmp_mask = (mask_p[30] << 28)
 405                 | (mask_p[29] << 26) | (mask_p[28] << 24)
 406                 | (mask_p[27] << 22) | (mask_p[26] << 20)
 407                 | (mask_p[25] << 18) | (mask_p[24] << 16)
 408                 | (mask_p[23] << 14) | (mask_p[22] << 12)
 409                 | (mask_p[21] << 10) | (mask_p[20] << 8)
 410                 | (mask_p[19] << 6) | (mask_p[18] << 4)
 411                 | (mask_p[17] << 2) | (mask_p[16] << 0);
 412         REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
 413         REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
 414
 415         tmp_mask = (mask_p[45] << 28)
 416                 | (mask_p[44] << 26) | (mask_p[43] << 24)
 417                 | (mask_p[42] << 22) | (mask_p[41] << 20)
 418                 | (mask_p[40] << 18) | (mask_p[39] << 16)
 419                 | (mask_p[38] << 14) | (mask_p[37] << 12)
 420                 | (mask_p[36] << 10) | (mask_p[35] << 8)
 421                 | (mask_p[34] << 6) | (mask_p[33] << 4)
 422                 | (mask_p[32] << 2) | (mask_p[31] << 0);
 423         REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
 424         REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
 425
 426         tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
 427                 | (mask_p[59] << 26) | (mask_p[58] << 24)
 428                 | (mask_p[57] << 22) | (mask_p[56] << 20)
 429                 | (mask_p[55] << 18) | (mask_p[54] << 16)
 430                 | (mask_p[53] << 14) | (mask_p[52] << 12)
 431                 | (mask_p[51] << 10) | (mask_p[50] << 8)
 432                 | (mask_p[49] << 6) | (mask_p[48] << 4)
 433                 | (mask_p[47] << 2) | (mask_p[46] << 0);
 434         REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
 435         REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
 436 }
 437
 438 /**
 439  * ar5008_hw_rf_alloc_ext_banks - allocates banks for external radio programming
 440  * @ah: atheros hardware structure
 441  *
 442  * Only required for older devices with external AR2133/AR5133 radios.
 443  */
 444 static int ar5008_hw_rf_alloc_ext_banks(struct ath_hw *ah)
 445 {
 446 #define ATH_ALLOC_BANK(bank, size) do { \
 447                 bank = kzalloc((sizeof(u32) * size), GFP_KERNEL); \
 448                 if (!bank) { \
 449                         ath_print(common, ATH_DBG_FATAL, \
 450                                   "Cannot allocate RF banks\n"); \
 451                         return -ENOMEM; \
 452                 } \
 453         } while (0);
 454
 455         struct ath_common *common = ath9k_hw_common(ah);
 456
 457         BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 458
 459         ATH_ALLOC_BANK(ah->analogBank0Data, ah->iniBank0.ia_rows);
 460         ATH_ALLOC_BANK(ah->analogBank1Data, ah->iniBank1.ia_rows);
 461         ATH_ALLOC_BANK(ah->analogBank2Data, ah->iniBank2.ia_rows);
 462         ATH_ALLOC_BANK(ah->analogBank3Data, ah->iniBank3.ia_rows);
 463         ATH_ALLOC_BANK(ah->analogBank6Data, ah->iniBank6.ia_rows);
 464         ATH_ALLOC_BANK(ah->analogBank6TPCData, ah->iniBank6TPC.ia_rows);
 465         ATH_ALLOC_BANK(ah->analogBank7Data, ah->iniBank7.ia_rows);
 466         ATH_ALLOC_BANK(ah->addac5416_21,
 467                        ah->iniAddac.ia_rows * ah->iniAddac.ia_columns);
 468         ATH_ALLOC_BANK(ah->bank6Temp, ah->iniBank6.ia_rows);
 469
 470         return 0;
 471 #undef ATH_ALLOC_BANK
 472 }
 473
 474
 475 /**
 476  * ar5008_hw_rf_free_ext_banks - Free memory for analog bank scratch buffers
 477  * @ah: atheros hardware struture
 478  * For the external AR2133/AR5133 radios banks.
 479  */
 480 static void ar5008_hw_rf_free_ext_banks(struct ath_hw *ah)
 481 {
 482 #define ATH_FREE_BANK(bank) do { \
 483                 kfree(bank); \
 484                 bank = NULL; \
 485         } while (0);
 486
 487         BUG_ON(AR_SREV_9280_20_OR_LATER(ah));
 488
 489         ATH_FREE_BANK(ah->analogBank0Data);
 490         ATH_FREE_BANK(ah->analogBank1Data);
 491         ATH_FREE_BANK(ah->analogBank2Data);
 492         ATH_FREE_BANK(ah->analogBank3Data);
 493         ATH_FREE_BANK(ah->analogBank6Data);
 494         ATH_FREE_BANK(ah->analogBank6TPCData);
 495         ATH_FREE_BANK(ah->analogBank7Data);
 496         ATH_FREE_BANK(ah->addac5416_21);
 497         ATH_FREE_BANK(ah->bank6Temp);
 498
 499 #undef ATH_FREE_BANK
 500 }
 501
 502 /* *
 503  * ar5008_hw_set_rf_regs - programs rf registers based on EEPROM
 504  * @ah: atheros hardware structure
 505  * @chan:
 506  * @modesIndex:
 507  *
 508  * Used for the external AR2133/AR5133 radios.
 509  *
 510  * Reads the EEPROM header info from the device structure and programs
 511  * all rf registers. This routine requires access to the analog
 512  * rf device. This is not required for single-chip devices.
 513  */
 514 static bool ar5008_hw_set_rf_regs(struct ath_hw *ah,
 515                                   struct ath9k_channel *chan,
 516                                   u16 modesIndex)
 517 {
 518         u32 eepMinorRev;
 519         u32 ob5GHz = 0, db5GHz = 0;
 520         u32 ob2GHz = 0, db2GHz = 0;
 521         int regWrites = 0;
 522
 523         /*
 524          * Software does not need to program bank data
 525          * for single chip devices, that is AR9280 or anything
 526          * after that.
 527          */
 528         if (AR_SREV_9280_20_OR_LATER(ah))
 529                 return true;
 530
 531         /* Setup rf parameters */
 532         eepMinorRev = ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV);
 533
 534         /* Setup Bank 0 Write */
 535         RF_BANK_SETUP(ah->analogBank0Data, &ah->iniBank0, 1);
 536
 537         /* Setup Bank 1 Write */
 538         RF_BANK_SETUP(ah->analogBank1Data, &ah->iniBank1, 1);
 539
 540         /* Setup Bank 2 Write */
 541         RF_BANK_SETUP(ah->analogBank2Data, &ah->iniBank2, 1);
 542
 543         /* Setup Bank 6 Write */
 544         RF_BANK_SETUP(ah->analogBank3Data, &ah->iniBank3,
 545                       modesIndex);
 546         {
 547                 int i;
 548                 for (i = 0; i < ah->iniBank6TPC.ia_rows; i++) {
 549                         ah->analogBank6Data[i] =
 550                             INI_RA(&ah->iniBank6TPC, i, modesIndex);
 551                 }
 552         }
 553
 554         /* Only the 5 or 2 GHz OB/DB need to be set for a mode */
 555         if (eepMinorRev >= 2) {
 556                 if (IS_CHAN_2GHZ(chan)) {
 557                         ob2GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_2);
 558                         db2GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_2);
 559                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
 560                                                        ob2GHz, 3, 197, 0);
 561                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
 562                                                        db2GHz, 3, 194, 0);
 563                 } else {
 564                         ob5GHz = ah->eep_ops->get_eeprom(ah, EEP_OB_5);
 565                         db5GHz = ah->eep_ops->get_eeprom(ah, EEP_DB_5);
 566                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
 567                                                        ob5GHz, 3, 203, 0);
 568                         ar5008_hw_phy_modify_rx_buffer(ah->analogBank6Data,
 569                                                        db5GHz, 3, 200, 0);
 570                 }
 571         }
 572
 573         /* Setup Bank 7 Setup */
 574         RF_BANK_SETUP(ah->analogBank7Data, &ah->iniBank7, 1);
 575
 576         /* Write Analog registers */
 577         REG_WRITE_RF_ARRAY(&ah->iniBank0, ah->analogBank0Data,
 578                            regWrites);
 579         REG_WRITE_RF_ARRAY(&ah->iniBank1, ah->analogBank1Data,
 580                            regWrites);
 581         REG_WRITE_RF_ARRAY(&ah->iniBank2, ah->analogBank2Data,
 582                            regWrites);
 583         REG_WRITE_RF_ARRAY(&ah->iniBank3, ah->analogBank3Data,
 584                            regWrites);
 585         REG_WRITE_RF_ARRAY(&ah->iniBank6TPC, ah->analogBank6Data,
 586                            regWrites);
 587         REG_WRITE_RF_ARRAY(&ah->iniBank7, ah->analogBank7Data,
 588                            regWrites);
 589
 590         return true;
 591 }
 592
 593 static void ar5008_hw_init_bb(struct ath_hw *ah,
 594                               struct ath9k_channel *chan)
 595 {
 596         u32 synthDelay;
 597
 598         synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 599         if (IS_CHAN_B(chan))
 600                 synthDelay = (4 * synthDelay) / 22;
 601         else
 602                 synthDelay /= 10;
 603
 604         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
 605
 606         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 607 }
 608
 609 static void ar5008_hw_init_chain_masks(struct ath_hw *ah)
 610 {
 611         int rx_chainmask, tx_chainmask;
 612
 613         rx_chainmask = ah->rxchainmask;
 614         tx_chainmask = ah->txchainmask;
 615
 616
 617         switch (rx_chainmask) {
 618         case 0x5:
 619                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 620                             AR_PHY_SWAP_ALT_CHAIN);
 621         case 0x3:
 622                 if (ah->hw_version.macVersion == AR_SREV_REVISION_5416_10) {
 623                         REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
 624                         REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
 625                         break;
 626                 }
 627         case 0x1:
 628         case 0x2:
 629         case 0x7:
 630                 ENABLE_REGWRITE_BUFFER(ah);
 631                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
 632                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
 633                 break;
 634         default:
 635                 ENABLE_REGWRITE_BUFFER(ah);
 636                 break;
 637         }
 638
 639         REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
 640
 641         REGWRITE_BUFFER_FLUSH(ah);
 642
 643         if (tx_chainmask == 0x5) {
 644                 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
 645                             AR_PHY_SWAP_ALT_CHAIN);
 646         }
 647         if (AR_SREV_9100(ah))
 648                 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
 649                           REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
 650 }
 651
 652 static void ar5008_hw_override_ini(struct ath_hw *ah,
 653                                    struct ath9k_channel *chan)
 654 {
 655         u32 val;
 656
 657         /*
 658          * Set the RX_ABORT and RX_DIS and clear if off only after
 659          * RXE is set for MAC. This prevents frames with corrupted
 660          * descriptor status.
 661          */
 662         REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
 663
 664         if (AR_SREV_9280_20_OR_LATER(ah)) {
 665                 val = REG_READ(ah, AR_PCU_MISC_MODE2);
 666
 667                 if (!AR_SREV_9271(ah))
 668                         val &= ~AR_PCU_MISC_MODE2_HWWAR1;
 669
 670                 if (AR_SREV_9287_11_OR_LATER(ah))
 671                         val = val & (~AR_PCU_MISC_MODE2_HWWAR2);
 672
 673                 REG_WRITE(ah, AR_PCU_MISC_MODE2, val);
 674         }
 675
 676         if (!AR_SREV_5416_20_OR_LATER(ah) ||
 677             AR_SREV_9280_20_OR_LATER(ah))
 678                 return;
 679         /*
 680          * Disable BB clock gating
 681          * Necessary to avoid issues on AR5416 2.0
 682          */
 683         REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
 684
 685         /*
 686          * Disable RIFS search on some chips to avoid baseband
 687          * hang issues.
 688          */
 689         if (AR_SREV_9100(ah) || AR_SREV_9160(ah)) {
 690                 val = REG_READ(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS);
 691                 val &= ~AR_PHY_RIFS_INIT_DELAY;
 692                 REG_WRITE(ah, AR_PHY_HEAVY_CLIP_FACTOR_RIFS, val);
 693         }
 694 }
 695
 696 static void ar5008_hw_set_channel_regs(struct ath_hw *ah,
 697                                        struct ath9k_channel *chan)
 698 {
 699         u32 phymode;
 700         u32 enableDacFifo = 0;
 701
 702         if (AR_SREV_9285_12_OR_LATER(ah))
 703                 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
 704                                          AR_PHY_FC_ENABLE_DAC_FIFO);
 705
 706         phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
 707                 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
 708
 709         if (IS_CHAN_HT40(chan)) {
 710                 phymode |= AR_PHY_FC_DYN2040_EN;
 711
 712                 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
 713                     (chan->chanmode == CHANNEL_G_HT40PLUS))
 714                         phymode |= AR_PHY_FC_DYN2040_PRI_CH;
 715
 716         }
 717         REG_WRITE(ah, AR_PHY_TURBO, phymode);
 718
 719         ath9k_hw_set11nmac2040(ah);
 720
 721         ENABLE_REGWRITE_BUFFER(ah);
 722
 723         REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
 724         REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
 725
 726         REGWRITE_BUFFER_FLUSH(ah);
 727 }
 728
 729
 730 static int ar5008_hw_process_ini(struct ath_hw *ah,
 731                                  struct ath9k_channel *chan)
 732 {
 733         struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 734         int i, regWrites = 0;
 735         struct ieee80211_channel *channel = chan->chan;
 736         u32 modesIndex, freqIndex;
 737
 738         switch (chan->chanmode) {
 739         case CHANNEL_A:
 740         case CHANNEL_A_HT20:
 741                 modesIndex = 1;
 742                 freqIndex = 1;
 743                 break;
 744         case CHANNEL_A_HT40PLUS:
 745         case CHANNEL_A_HT40MINUS:
 746                 modesIndex = 2;
 747                 freqIndex = 1;
 748                 break;
 749         case CHANNEL_G:
 750         case CHANNEL_G_HT20:
 751         case CHANNEL_B:
 752                 modesIndex = 4;
 753                 freqIndex = 2;
 754                 break;
 755         case CHANNEL_G_HT40PLUS:
 756         case CHANNEL_G_HT40MINUS:
 757                 modesIndex = 3;
 758                 freqIndex = 2;
 759                 break;
 760
 761         default:
 762                 return -EINVAL;
 763         }
 764
 765         /*
 766          * Set correct baseband to analog shift setting to
 767          * access analog chips.
 768          */
 769         REG_WRITE(ah, AR_PHY(0), 0x00000007);
 770
 771         /* Write ADDAC shifts */
 772         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
 773         ah->eep_ops->set_addac(ah, chan);
 774
 775         if (AR_SREV_5416_22_OR_LATER(ah)) {
 776                 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
 777         } else {
 778                 struct ar5416IniArray temp;
 779                 u32 addacSize =
 780                         sizeof(u32) * ah->iniAddac.ia_rows *
 781                         ah->iniAddac.ia_columns;
 782
 783                 /* For AR5416 2.0/2.1 */
 784                 memcpy(ah->addac5416_21,
 785                        ah->iniAddac.ia_array, addacSize);
 786
 787                 /* override CLKDRV value at [row, column] = [31, 1] */
 788                 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
 789
 790                 temp.ia_array = ah->addac5416_21;
 791                 temp.ia_columns = ah->iniAddac.ia_columns;
 792                 temp.ia_rows = ah->iniAddac.ia_rows;
 793                 REG_WRITE_ARRAY(&temp, 1, regWrites);
 794         }
 795
 796         REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
 797
 798         ENABLE_REGWRITE_BUFFER(ah);
 799
 800         for (i = 0; i < ah->iniModes.ia_rows; i++) {
 801                 u32 reg = INI_RA(&ah->iniModes, i, 0);
 802                 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
 803
 804                 if (reg == AR_AN_TOP2 && ah->need_an_top2_fixup)
 805                         val &= ~AR_AN_TOP2_PWDCLKIND;
 806
 807                 REG_WRITE(ah, reg, val);
 808
 809                 if (reg >= 0x7800 && reg < 0x78a0
 810                     && ah->config.analog_shiftreg) {
 811                         udelay(100);
 812                 }
 813
 814                 DO_DELAY(regWrites);
 815         }
 816
 817         REGWRITE_BUFFER_FLUSH(ah);
 818
 819         if (AR_SREV_9280(ah) || AR_SREV_9287_11_OR_LATER(ah))
 820                 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
 821
 822         if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah) ||
 823             AR_SREV_9287_11_OR_LATER(ah))
 824                 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
 825
 826         if (AR_SREV_9271_10(ah))
 827                 REG_WRITE_ARRAY(&ah->iniModes_9271_1_0_only,
 828                                 modesIndex, regWrites);
 829
 830         ENABLE_REGWRITE_BUFFER(ah);
 831
 832         /* Write common array parameters */
 833         for (i = 0; i < ah->iniCommon.ia_rows; i++) {
 834                 u32 reg = INI_RA(&ah->iniCommon, i, 0);
 835                 u32 val = INI_RA(&ah->iniCommon, i, 1);
 836
 837                 REG_WRITE(ah, reg, val);
 838
 839                 if (reg >= 0x7800 && reg < 0x78a0
 840                     && ah->config.analog_shiftreg) {
 841                         udelay(100);
 842                 }
 843
 844                 DO_DELAY(regWrites);
 845         }
 846
 847         REGWRITE_BUFFER_FLUSH(ah);
 848
 849         if (AR_SREV_9271(ah)) {
 850                 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 1)
 851                         REG_WRITE_ARRAY(&ah->iniModes_high_power_tx_gain_9271,
 852                                         modesIndex, regWrites);
 853                 else
 854                         REG_WRITE_ARRAY(&ah->iniModes_normal_power_tx_gain_9271,
 855                                         modesIndex, regWrites);
 856         }
 857
 858         REG_WRITE_ARRAY(&ah->iniBB_RfGain, freqIndex, regWrites);
 859
 860         if (IS_CHAN_A_FAST_CLOCK(ah, chan)) {
 861                 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
 862                                 regWrites);
 863         }
 864
 865         ar5008_hw_override_ini(ah, chan);
 866         ar5008_hw_set_channel_regs(ah, chan);
 867         ar5008_hw_init_chain_masks(ah);
 868         ath9k_olc_init(ah);
 869
 870         /* Set TX power */
 871         ah->eep_ops->set_txpower(ah, chan,
 872                                  ath9k_regd_get_ctl(regulatory, chan),
 873                                  channel->max_antenna_gain * 2,
 874                                  channel->max_power * 2,
 875                                  min((u32) MAX_RATE_POWER,
 876                                  (u32) regulatory->power_limit));
 877
 878         /* Write analog registers */
 879         if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
 880                 ath_print(ath9k_hw_common(ah), ATH_DBG_FATAL,
 881                           "ar5416SetRfRegs failed\n");
 882                 return -EIO;
 883         }
 884
 885         return 0;
 886 }
 887
 888 static void ar5008_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
 889 {
 890         u32 rfMode = 0;
 891
 892         if (chan == NULL)
 893                 return;
 894
 895         rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
 896                 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
 897
 898         if (!AR_SREV_9280_20_OR_LATER(ah))
 899                 rfMode |= (IS_CHAN_5GHZ(chan)) ?
 900                         AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
 901
 902         if (IS_CHAN_A_FAST_CLOCK(ah, chan))
 903                 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
 904
 905         REG_WRITE(ah, AR_PHY_MODE, rfMode);
 906 }
 907
 908 static void ar5008_hw_mark_phy_inactive(struct ath_hw *ah)
 909 {
 910         REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
 911 }
 912
 913 static void ar5008_hw_set_delta_slope(struct ath_hw *ah,
 914                                       struct ath9k_channel *chan)
 915 {
 916         u32 coef_scaled, ds_coef_exp, ds_coef_man;
 917         u32 clockMhzScaled = 0x64000000;
 918         struct chan_centers centers;
 919
 920         if (IS_CHAN_HALF_RATE(chan))
 921                 clockMhzScaled = clockMhzScaled >> 1;
 922         else if (IS_CHAN_QUARTER_RATE(chan))
 923                 clockMhzScaled = clockMhzScaled >> 2;
 924
 925         ath9k_hw_get_channel_centers(ah, chan, &centers);
 926         coef_scaled = clockMhzScaled / centers.synth_center;
 927
 928         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 929                                       &ds_coef_exp);
 930
 931         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 932                       AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
 933         REG_RMW_FIELD(ah, AR_PHY_TIMING3,
 934                       AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
 935
 936         coef_scaled = (9 * coef_scaled) / 10;
 937
 938         ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
 939                                       &ds_coef_exp);
 940
 941         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
 942                       AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
 943         REG_RMW_FIELD(ah, AR_PHY_HALFGI,
 944                       AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
 945 }
 946
 947 static bool ar5008_hw_rfbus_req(struct ath_hw *ah)
 948 {
 949         REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
 950         return ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
 951                            AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT);
 952 }
 953
 954 static void ar5008_hw_rfbus_done(struct ath_hw *ah)
 955 {
 956         u32 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
 957         if (IS_CHAN_B(ah->curchan))
 958                 synthDelay = (4 * synthDelay) / 22;
 959         else
 960                 synthDelay /= 10;
 961
 962         udelay(synthDelay + BASE_ACTIVATE_DELAY);
 963
 964         REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
 965 }
 966
 967 static void ar5008_hw_enable_rfkill(struct ath_hw *ah)
 968 {
 969         REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
 970                     AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
 971
 972         REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
 973                     AR_GPIO_INPUT_MUX2_RFSILENT);
 974
 975         ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
 976         REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
 977 }
 978
 979 static void ar5008_restore_chainmask(struct ath_hw *ah)
 980 {
 981         int rx_chainmask = ah->rxchainmask;
 982
 983         if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
 984                 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
 985                 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
 986         }
 987 }
 988
 989 static void ar5008_set_diversity(struct ath_hw *ah, bool value)
 990 {
 991         u32 v = REG_READ(ah, AR_PHY_CCK_DETECT);
 992         if (value)
 993                 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 994         else
 995                 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
 996         REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
 997 }
 998
 999 static u32 ar9100_hw_compute_pll_control(struct ath_hw *ah,
1000                                          struct ath9k_channel *chan)
1001 {
1002         if (chan && IS_CHAN_5GHZ(chan))
1003                 return 0x1450;
1004         return 0x1458;
1005 }
1006
1007 static u32 ar9160_hw_compute_pll_control(struct ath_hw *ah,
1008                                          struct ath9k_channel *chan)
1009 {
1010         u32 pll;
1011
1012         pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1013
1014         if (chan && IS_CHAN_HALF_RATE(chan))
1015                 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1016         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1017                 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1018
1019         if (chan && IS_CHAN_5GHZ(chan))
1020                 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1021         else
1022                 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1023
1024         return pll;
1025 }
1026
1027 static u32 ar5008_hw_compute_pll_control(struct ath_hw *ah,
1028                                          struct ath9k_channel *chan)
1029 {
1030         u32 pll;
1031
1032         pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1033
1034         if (chan && IS_CHAN_HALF_RATE(chan))
1035                 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1036         else if (chan && IS_CHAN_QUARTER_RATE(chan))
1037                 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1038
1039         if (chan && IS_CHAN_5GHZ(chan))
1040                 pll |= SM(0xa, AR_RTC_PLL_DIV);
1041         else
1042                 pll |= SM(0xb, AR_RTC_PLL_DIV);
1043
1044         return pll;
1045 }
1046
1047 static bool ar5008_hw_ani_control_old(struct ath_hw *ah,
1048                                       enum ath9k_ani_cmd cmd,
1049                                       int param)
1050 {
1051         struct ar5416AniState *aniState = &ah->curchan->ani;
1052         struct ath_common *common = ath9k_hw_common(ah);
1053
1054         switch (cmd & ah->ani_function) {
1055         case ATH9K_ANI_NOISE_IMMUNITY_LEVEL:{
1056                 u32 level = param;
1057
1058                 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
1059                         ath_print(common, ATH_DBG_ANI,
1060                                   "level out of range (%u > %u)\n",
1061                                   level,
1062                                   (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
1063                         return false;
1064                 }
1065
1066                 REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
1067                               AR_PHY_DESIRED_SZ_TOT_DES,
1068                               ah->totalSizeDesired[level]);
1069                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1070                               AR_PHY_AGC_CTL1_COARSE_LOW,
1071                               ah->coarse_low[level]);
1072                 REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
1073                               AR_PHY_AGC_CTL1_COARSE_HIGH,
1074                               ah->coarse_high[level]);
1075                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1076                               AR_PHY_FIND_SIG_FIRPWR,
1077                               ah->firpwr[level]);
1078
1079                 if (level > aniState->noiseImmunityLevel)
1080                         ah->stats.ast_ani_niup++;
1081                 else if (level < aniState->noiseImmunityLevel)
1082                         ah->stats.ast_ani_nidown++;
1083                 aniState->noiseImmunityLevel = level;
1084                 break;
1085         }
1086         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1087                 const int m1ThreshLow[] = { 127, 50 };
1088                 const int m2ThreshLow[] = { 127, 40 };
1089                 const int m1Thresh[] = { 127, 0x4d };
1090                 const int m2Thresh[] = { 127, 0x40 };
1091                 const int m2CountThr[] = { 31, 16 };
1092                 const int m2CountThrLow[] = { 63, 48 };
1093                 u32 on = param ? 1 : 0;
1094
1095                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1096                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1097                               m1ThreshLow[on]);
1098                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1099                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1100                               m2ThreshLow[on]);
1101                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1102                               AR_PHY_SFCORR_M1_THRESH,
1103                               m1Thresh[on]);
1104                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1105                               AR_PHY_SFCORR_M2_THRESH,
1106                               m2Thresh[on]);
1107                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1108                               AR_PHY_SFCORR_M2COUNT_THR,
1109                               m2CountThr[on]);
1110                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1111                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1112                               m2CountThrLow[on]);
1113
1114                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1115                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
1116                               m1ThreshLow[on]);
1117                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1118                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
1119                               m2ThreshLow[on]);
1120                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1121                               AR_PHY_SFCORR_EXT_M1_THRESH,
1122                               m1Thresh[on]);
1123                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1124                               AR_PHY_SFCORR_EXT_M2_THRESH,
1125                               m2Thresh[on]);
1126
1127                 if (on)
1128                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1129                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1130                 else
1131                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1132                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1133
1134                 if (!on != aniState->ofdmWeakSigDetectOff) {
1135                         if (on)
1136                                 ah->stats.ast_ani_ofdmon++;
1137                         else
1138                                 ah->stats.ast_ani_ofdmoff++;
1139                         aniState->ofdmWeakSigDetectOff = !on;
1140                 }
1141                 break;
1142         }
1143         case ATH9K_ANI_CCK_WEAK_SIGNAL_THR:{
1144                 const int weakSigThrCck[] = { 8, 6 };
1145                 u32 high = param ? 1 : 0;
1146
1147                 REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
1148                               AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
1149                               weakSigThrCck[high]);
1150                 if (high != aniState->cckWeakSigThreshold) {
1151                         if (high)
1152                                 ah->stats.ast_ani_cckhigh++;
1153                         else
1154                                 ah->stats.ast_ani_ccklow++;
1155                         aniState->cckWeakSigThreshold = high;
1156                 }
1157                 break;
1158         }
1159         case ATH9K_ANI_FIRSTEP_LEVEL:{
1160                 const int firstep[] = { 0, 4, 8 };
1161                 u32 level = param;
1162
1163                 if (level >= ARRAY_SIZE(firstep)) {
1164                         ath_print(common, ATH_DBG_ANI,
1165                                   "level out of range (%u > %u)\n",
1166                                   level,
1167                                   (unsigned) ARRAY_SIZE(firstep));
1168                         return false;
1169                 }
1170                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1171                               AR_PHY_FIND_SIG_FIRSTEP,
1172                               firstep[level]);
1173                 if (level > aniState->firstepLevel)
1174                         ah->stats.ast_ani_stepup++;
1175                 else if (level < aniState->firstepLevel)
1176                         ah->stats.ast_ani_stepdown++;
1177                 aniState->firstepLevel = level;
1178                 break;
1179         }
1180         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1181                 const int cycpwrThr1[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
1182                 u32 level = param;
1183
1184                 if (level >= ARRAY_SIZE(cycpwrThr1)) {
1185                         ath_print(common, ATH_DBG_ANI,
1186                                   "level out of range (%u > %u)\n",
1187                                   level,
1188                                   (unsigned) ARRAY_SIZE(cycpwrThr1));
1189                         return false;
1190                 }
1191                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1192                               AR_PHY_TIMING5_CYCPWR_THR1,
1193                               cycpwrThr1[level]);
1194                 if (level > aniState->spurImmunityLevel)
1195                         ah->stats.ast_ani_spurup++;
1196                 else if (level < aniState->spurImmunityLevel)
1197                         ah->stats.ast_ani_spurdown++;
1198                 aniState->spurImmunityLevel = level;
1199                 break;
1200         }
1201         case ATH9K_ANI_PRESENT:
1202                 break;
1203         default:
1204                 ath_print(common, ATH_DBG_ANI,
1205                           "invalid cmd %u\n", cmd);
1206                 return false;
1207         }
1208
1209         ath_print(common, ATH_DBG_ANI, "ANI parameters:\n");
1210         ath_print(common, ATH_DBG_ANI,
1211                   "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
1212                   "ofdmWeakSigDetectOff=%d\n",
1213                   aniState->noiseImmunityLevel,
1214                   aniState->spurImmunityLevel,
1215                   !aniState->ofdmWeakSigDetectOff);
1216         ath_print(common, ATH_DBG_ANI,
1217                   "cckWeakSigThreshold=%d, "
1218                   "firstepLevel=%d, listenTime=%d\n",
1219                   aniState->cckWeakSigThreshold,
1220                   aniState->firstepLevel,
1221                   aniState->listenTime);
1222         ath_print(common, ATH_DBG_ANI,
1223                 "ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
1224                 aniState->ofdmPhyErrCount,
1225                 aniState->cckPhyErrCount);
1226
1227         return true;
1228 }
1229
1230 static bool ar5008_hw_ani_control_new(struct ath_hw *ah,
1231                                       enum ath9k_ani_cmd cmd,
1232                                       int param)
1233 {
1234         struct ath_common *common = ath9k_hw_common(ah);
1235         struct ath9k_channel *chan = ah->curchan;
1236         struct ar5416AniState *aniState = &chan->ani;
1237         s32 value, value2;
1238
1239         switch (cmd & ah->ani_function) {
1240         case ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
1241                 /*
1242                  * on == 1 means ofdm weak signal detection is ON
1243                  * on == 1 is the default, for less noise immunity
1244                  *
1245                  * on == 0 means ofdm weak signal detection is OFF
1246                  * on == 0 means more noise imm
1247                  */
1248                 u32 on = param ? 1 : 0;
1249                 /*
1250                  * make register setting for default
1251                  * (weak sig detect ON) come from INI file
1252                  */
1253                 int m1ThreshLow = on ?
1254                         aniState->iniDef.m1ThreshLow : m1ThreshLow_off;
1255                 int m2ThreshLow = on ?
1256                         aniState->iniDef.m2ThreshLow : m2ThreshLow_off;
1257                 int m1Thresh = on ?
1258                         aniState->iniDef.m1Thresh : m1Thresh_off;
1259                 int m2Thresh = on ?
1260                         aniState->iniDef.m2Thresh : m2Thresh_off;
1261                 int m2CountThr = on ?
1262                         aniState->iniDef.m2CountThr : m2CountThr_off;
1263                 int m2CountThrLow = on ?
1264                         aniState->iniDef.m2CountThrLow : m2CountThrLow_off;
1265                 int m1ThreshLowExt = on ?
1266                         aniState->iniDef.m1ThreshLowExt : m1ThreshLowExt_off;
1267                 int m2ThreshLowExt = on ?
1268                         aniState->iniDef.m2ThreshLowExt : m2ThreshLowExt_off;
1269                 int m1ThreshExt = on ?
1270                         aniState->iniDef.m1ThreshExt : m1ThreshExt_off;
1271                 int m2ThreshExt = on ?
1272                         aniState->iniDef.m2ThreshExt : m2ThreshExt_off;
1273
1274                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1275                               AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
1276                               m1ThreshLow);
1277                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1278                               AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
1279                               m2ThreshLow);
1280                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1281                               AR_PHY_SFCORR_M1_THRESH, m1Thresh);
1282                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1283                               AR_PHY_SFCORR_M2_THRESH, m2Thresh);
1284                 REG_RMW_FIELD(ah, AR_PHY_SFCORR,
1285                               AR_PHY_SFCORR_M2COUNT_THR, m2CountThr);
1286                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
1287                               AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
1288                               m2CountThrLow);
1289
1290                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1291                               AR_PHY_SFCORR_EXT_M1_THRESH_LOW, m1ThreshLowExt);
1292                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1293                               AR_PHY_SFCORR_EXT_M2_THRESH_LOW, m2ThreshLowExt);
1294                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1295                               AR_PHY_SFCORR_EXT_M1_THRESH, m1ThreshExt);
1296                 REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
1297                               AR_PHY_SFCORR_EXT_M2_THRESH, m2ThreshExt);
1298
1299                 if (on)
1300                         REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
1301                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1302                 else
1303                         REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
1304                                     AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
1305
1306                 if (!on != aniState->ofdmWeakSigDetectOff) {
1307                         ath_print(common, ATH_DBG_ANI,
1308                                   "** ch %d: ofdm weak signal: %s=>%s\n",
1309                                   chan->channel,
1310                                   !aniState->ofdmWeakSigDetectOff ?
1311                                         "on" : "off",
1312                                   on ? "on" : "off");
1313                         if (on)
1314                                 ah->stats.ast_ani_ofdmon++;
1315                         else
1316                                 ah->stats.ast_ani_ofdmoff++;
1317                         aniState->ofdmWeakSigDetectOff = !on;
1318                 }
1319                 break;
1320         }
1321         case ATH9K_ANI_FIRSTEP_LEVEL:{
1322                 u32 level = param;
1323
1324                 if (level >= ARRAY_SIZE(firstep_table)) {
1325                         ath_print(common, ATH_DBG_ANI,
1326                                   "ATH9K_ANI_FIRSTEP_LEVEL: level "
1327                                   "out of range (%u > %u)\n",
1328                                   level,
1329                                   (unsigned) ARRAY_SIZE(firstep_table));
1330                         return false;
1331                 }
1332
1333                 /*
1334                  * make register setting relative to default
1335                  * from INI file & cap value
1336                  */
1337                 value = firstep_table[level] -
1338                         firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1339                         aniState->iniDef.firstep;
1340                 if (value < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1341                         value = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1342                 if (value > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1343                         value = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1344                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
1345                               AR_PHY_FIND_SIG_FIRSTEP,
1346                               value);
1347                 /*
1348                  * we need to set first step low register too
1349                  * make register setting relative to default
1350                  * from INI file & cap value
1351                  */
1352                 value2 = firstep_table[level] -
1353                          firstep_table[ATH9K_ANI_FIRSTEP_LVL_NEW] +
1354                          aniState->iniDef.firstepLow;
1355                 if (value2 < ATH9K_SIG_FIRSTEP_SETTING_MIN)
1356                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MIN;
1357                 if (value2 > ATH9K_SIG_FIRSTEP_SETTING_MAX)
1358                         value2 = ATH9K_SIG_FIRSTEP_SETTING_MAX;
1359
1360                 REG_RMW_FIELD(ah, AR_PHY_FIND_SIG_LOW,
1361                               AR_PHY_FIND_SIG_FIRSTEP_LOW, value2);
1362
1363                 if (level != aniState->firstepLevel) {
1364                         ath_print(common, ATH_DBG_ANI,
1365                                   "** ch %d: level %d=>%d[def:%d] "
1366                                   "firstep[level]=%d ini=%d\n",
1367                                   chan->channel,
1368                                   aniState->firstepLevel,
1369                                   level,
1370                                   ATH9K_ANI_FIRSTEP_LVL_NEW,
1371                                   value,
1372                                   aniState->iniDef.firstep);
1373                         ath_print(common, ATH_DBG_ANI,
1374                                   "** ch %d: level %d=>%d[def:%d] "
1375                                   "firstep_low[level]=%d ini=%d\n",
1376                                   chan->channel,
1377                                   aniState->firstepLevel,
1378                                   level,
1379                                   ATH9K_ANI_FIRSTEP_LVL_NEW,
1380                                   value2,
1381                                   aniState->iniDef.firstepLow);
1382                         if (level > aniState->firstepLevel)
1383                                 ah->stats.ast_ani_stepup++;
1384                         else if (level < aniState->firstepLevel)
1385                                 ah->stats.ast_ani_stepdown++;
1386                         aniState->firstepLevel = level;
1387                 }
1388                 break;
1389         }
1390         case ATH9K_ANI_SPUR_IMMUNITY_LEVEL:{
1391                 u32 level = param;
1392
1393                 if (level >= ARRAY_SIZE(cycpwrThr1_table)) {
1394                         ath_print(common, ATH_DBG_ANI,
1395                                   "ATH9K_ANI_SPUR_IMMUNITY_LEVEL: level "
1396                                   "out of range (%u > %u)\n",
1397                                   level,
1398                                   (unsigned) ARRAY_SIZE(cycpwrThr1_table));
1399                         return false;
1400                 }
1401                 /*
1402                  * make register setting relative to default
1403                  * from INI file & cap value
1404                  */
1405                 value = cycpwrThr1_table[level] -
1406                         cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1407                         aniState->iniDef.cycpwrThr1;
1408                 if (value < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1409                         value = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1410                 if (value > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1411                         value = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1412                 REG_RMW_FIELD(ah, AR_PHY_TIMING5,
1413                               AR_PHY_TIMING5_CYCPWR_THR1,
1414                               value);
1415
1416                 /*
1417                  * set AR_PHY_EXT_CCA for extension channel
1418                  * make register setting relative to default
1419                  * from INI file & cap value
1420                  */
1421                 value2 = cycpwrThr1_table[level] -
1422                          cycpwrThr1_table[ATH9K_ANI_SPUR_IMMUNE_LVL_NEW] +
1423                          aniState->iniDef.cycpwrThr1Ext;
1424                 if (value2 < ATH9K_SIG_SPUR_IMM_SETTING_MIN)
1425                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MIN;
1426                 if (value2 > ATH9K_SIG_SPUR_IMM_SETTING_MAX)
1427                         value2 = ATH9K_SIG_SPUR_IMM_SETTING_MAX;
1428                 REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
1429                               AR_PHY_EXT_TIMING5_CYCPWR_THR1, value2);
1430
1431                 if (level != aniState->spurImmunityLevel) {
1432                         ath_print(common, ATH_DBG_ANI,
1433                                   "** ch %d: level %d=>%d[def:%d] "
1434                                   "cycpwrThr1[level]=%d ini=%d\n",
1435                                   chan->channel,
1436                                   aniState->spurImmunityLevel,
1437                                   level,
1438                                   ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1439                                   value,
1440                                   aniState->iniDef.cycpwrThr1);
1441                         ath_print(common, ATH_DBG_ANI,
1442                                   "** ch %d: level %d=>%d[def:%d] "
1443                                   "cycpwrThr1Ext[level]=%d ini=%d\n",
1444                                   chan->channel,
1445                                   aniState->spurImmunityLevel,
1446                                   level,
1447                                   ATH9K_ANI_SPUR_IMMUNE_LVL_NEW,
1448                                   value2,
1449                                   aniState->iniDef.cycpwrThr1Ext);
1450                         if (level > aniState->spurImmunityLevel)
1451                                 ah->stats.ast_ani_spurup++;
1452                         else if (level < aniState->spurImmunityLevel)
1453                                 ah->stats.ast_ani_spurdown++;
1454                         aniState->spurImmunityLevel = level;
1455                 }
1456                 break;
1457         }
1458         case ATH9K_ANI_MRC_CCK:
1459                 /*
1460                  * You should not see this as AR5008, AR9001, AR9002
1461                  * does not have hardware support for MRC CCK.
1462                  */
1463                 WARN_ON(1);
1464                 break;
1465         case ATH9K_ANI_PRESENT:
1466                 break;
1467         default:
1468                 ath_print(common, ATH_DBG_ANI,
1469                           "invalid cmd %u\n", cmd);
1470                 return false;
1471         }
1472
1473         ath_print(common, ATH_DBG_ANI,
1474                   "ANI parameters: SI=%d, ofdmWS=%s FS=%d "
1475                   "MRCcck=%s listenTime=%d "
1476                   "ofdmErrs=%d cckErrs=%d\n",
1477                   aniState->spurImmunityLevel,
1478                   !aniState->ofdmWeakSigDetectOff ? "on" : "off",
1479                   aniState->firstepLevel,
1480                   !aniState->mrcCCKOff ? "on" : "off",
1481                   aniState->listenTime,
1482                   aniState->ofdmPhyErrCount,
1483                   aniState->cckPhyErrCount);
1484         return true;
1485 }
1486
1487 static void ar5008_hw_do_getnf(struct ath_hw *ah,
1488                               int16_t nfarray[NUM_NF_READINGS])
1489 {
1490         int16_t nf;
1491
1492         nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1493         nfarray[0] = sign_extend(nf, 9);
1494
1495         nf = MS(REG_READ(ah, AR_PHY_CH1_CCA), AR_PHY_CH1_MINCCA_PWR);
1496         nfarray[1] = sign_extend(nf, 9);
1497
1498         nf = MS(REG_READ(ah, AR_PHY_CH2_CCA), AR_PHY_CH2_MINCCA_PWR);
1499         nfarray[2] = sign_extend(nf, 9);
1500
1501         if (!IS_CHAN_HT40(ah->curchan))
1502                 return;
1503
1504         nf = MS(REG_READ(ah, AR_PHY_EXT_CCA), AR_PHY_EXT_MINCCA_PWR);
1505         nfarray[3] = sign_extend(nf, 9);
1506
1507         nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR_PHY_CH1_EXT_MINCCA_PWR);
1508         nfarray[4] = sign_extend(nf, 9);
1509
1510         nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA), AR_PHY_CH2_EXT_MINCCA_PWR);
1511         nfarray[5] = sign_extend(nf, 9);
1512 }
1513
1514 /*
1515  * Initialize the ANI register values with default (ini) values.
1516  * This routine is called during a (full) hardware reset after
1517  * all the registers are initialised from the INI.
1518  */
1519 static void ar5008_hw_ani_cache_ini_regs(struct ath_hw *ah)
1520 {
1521         struct ath_common *common = ath9k_hw_common(ah);
1522         struct ath9k_channel *chan = ah->curchan;
1523         struct ar5416AniState *aniState = &chan->ani;
1524         struct ath9k_ani_default *iniDef;
1525         u32 val;
1526
1527         iniDef = &aniState->iniDef;
1528
1529         ath_print(common, ATH_DBG_ANI,
1530                   "ver %d.%d opmode %u chan %d Mhz/0x%x\n",
1531                   ah->hw_version.macVersion,
1532                   ah->hw_version.macRev,
1533                   ah->opmode,
1534                   chan->channel,
1535                   chan->channelFlags);
1536
1537         val = REG_READ(ah, AR_PHY_SFCORR);
1538         iniDef->m1Thresh = MS(val, AR_PHY_SFCORR_M1_THRESH);
1539         iniDef->m2Thresh = MS(val, AR_PHY_SFCORR_M2_THRESH);
1540         iniDef->m2CountThr = MS(val, AR_PHY_SFCORR_M2COUNT_THR);
1541
1542         val = REG_READ(ah, AR_PHY_SFCORR_LOW);
1543         iniDef->m1ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M1_THRESH_LOW);
1544         iniDef->m2ThreshLow = MS(val, AR_PHY_SFCORR_LOW_M2_THRESH_LOW);
1545         iniDef->m2CountThrLow = MS(val, AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW);
1546
1547         val = REG_READ(ah, AR_PHY_SFCORR_EXT);
1548         iniDef->m1ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH);
1549         iniDef->m2ThreshExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH);
1550         iniDef->m1ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M1_THRESH_LOW);
1551         iniDef->m2ThreshLowExt = MS(val, AR_PHY_SFCORR_EXT_M2_THRESH_LOW);
1552         iniDef->firstep = REG_READ_FIELD(ah,
1553                                          AR_PHY_FIND_SIG,
1554                                          AR_PHY_FIND_SIG_FIRSTEP);
1555         iniDef->firstepLow = REG_READ_FIELD(ah,
1556                                             AR_PHY_FIND_SIG_LOW,
1557                                             AR_PHY_FIND_SIG_FIRSTEP_LOW);
1558         iniDef->cycpwrThr1 = REG_READ_FIELD(ah,
1559                                             AR_PHY_TIMING5,
1560                                             AR_PHY_TIMING5_CYCPWR_THR1);
1561         iniDef->cycpwrThr1Ext = REG_READ_FIELD(ah,
1562                                                AR_PHY_EXT_CCA,
1563                                                AR_PHY_EXT_TIMING5_CYCPWR_THR1);
1564
1565         /* these levels just got reset to defaults by the INI */
1566         aniState->spurImmunityLevel = ATH9K_ANI_SPUR_IMMUNE_LVL_NEW;
1567         aniState->firstepLevel = ATH9K_ANI_FIRSTEP_LVL_NEW;
1568         aniState->ofdmWeakSigDetectOff = !ATH9K_ANI_USE_OFDM_WEAK_SIG;
1569         aniState->mrcCCKOff = true; /* not available on pre AR9003 */
1570 }
1571
1572 static void ar5008_hw_set_nf_limits(struct ath_hw *ah)
1573 {
1574         ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_2GHZ;
1575         ah->nf_2g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_2GHZ;
1576         ah->nf_2g.nominal = AR_PHY_CCA_NOM_VAL_5416_2GHZ;
1577         ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_5416_5GHZ;
1578         ah->nf_5g.min = AR_PHY_CCA_MIN_GOOD_VAL_5416_5GHZ;
1579         ah->nf_5g.nominal = AR_PHY_CCA_NOM_VAL_5416_5GHZ;
1580 }
1581
1582 void ar5008_hw_attach_phy_ops(struct ath_hw *ah)
1583 {
1584         struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah);
1585         const u32 ar5416_cca_regs[6] = {
1586                 AR_PHY_CCA,
1587                 AR_PHY_CH1_CCA,
1588                 AR_PHY_CH2_CCA,
1589                 AR_PHY_EXT_CCA,
1590                 AR_PHY_CH1_EXT_CCA,
1591                 AR_PHY_CH2_EXT_CCA
1592         };
1593
1594         priv_ops->rf_set_freq = ar5008_hw_set_channel;
1595         priv_ops->spur_mitigate_freq = ar5008_hw_spur_mitigate;
1596
1597         priv_ops->rf_alloc_ext_banks = ar5008_hw_rf_alloc_ext_banks;
1598         priv_ops->rf_free_ext_banks = ar5008_hw_rf_free_ext_banks;
1599         priv_ops->set_rf_regs = ar5008_hw_set_rf_regs;
1600         priv_ops->set_channel_regs = ar5008_hw_set_channel_regs;
1601         priv_ops->init_bb = ar5008_hw_init_bb;
1602         priv_ops->process_ini = ar5008_hw_process_ini;
1603         priv_ops->set_rfmode = ar5008_hw_set_rfmode;
1604         priv_ops->mark_phy_inactive = ar5008_hw_mark_phy_inactive;
1605         priv_ops->set_delta_slope = ar5008_hw_set_delta_slope;
1606         priv_ops->rfbus_req = ar5008_hw_rfbus_req;
1607         priv_ops->rfbus_done = ar5008_hw_rfbus_done;
1608         priv_ops->enable_rfkill = ar5008_hw_enable_rfkill;
1609         priv_ops->restore_chainmask = ar5008_restore_chainmask;
1610         priv_ops->set_diversity = ar5008_set_diversity;
1611         priv_ops->do_getnf = ar5008_hw_do_getnf;
1612
1613         if (modparam_force_new_ani) {
1614                 priv_ops->ani_control = ar5008_hw_ani_control_new;
1615                 priv_ops->ani_cache_ini_regs = ar5008_hw_ani_cache_ini_regs;
1616         } else
1617                 priv_ops->ani_control = ar5008_hw_ani_control_old;
1618
1619         if (AR_SREV_9100(ah))
1620                 priv_ops->compute_pll_control = ar9100_hw_compute_pll_control;
1621         else if (AR_SREV_9160_10_OR_LATER(ah))
1622                 priv_ops->compute_pll_control = ar9160_hw_compute_pll_control;
1623         else
1624                 priv_ops->compute_pll_control = ar5008_hw_compute_pll_control;
1625
1626         ar5008_hw_set_nf_limits(ah);
1627         memcpy(ah->nf_regs, ar5416_cca_regs, sizeof(ah->nf_regs));
1628 }