4 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
5 * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
6 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
7 * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 #include <linux/delay.h>
24 #include <linux/slab.h>
38 * Get the PHY Chip revision
40 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan)
47 * Set the radio chip access register
51 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
54 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
62 /* ...wait until PHY is ready and read the selected radio revision */
63 ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
65 for (i = 0; i < 8; i++)
66 ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
68 if (ah->ah_version == AR5K_AR5210) {
69 srev = ath5k_hw_reg_read(ah, AR5K_PHY(256) >> 28) & 0xf;
70 ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
72 srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
73 ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
74 ((srev & 0x0f) << 4), 8);
77 /* Reset to the 5GHz mode */
78 ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
84 * Check if a channel is supported
86 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags)
88 /* Check if the channel is in our supported range */
89 if (flags & CHANNEL_2GHZ) {
90 if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
91 (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
93 } else if (flags & CHANNEL_5GHZ)
94 if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
95 (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
101 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
102 struct ieee80211_channel *channel)
106 if ((ah->ah_radio == AR5K_RF5112) ||
107 (ah->ah_radio == AR5K_RF5413) ||
108 (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
113 if ((channel->center_freq % refclk_freq != 0) &&
114 ((channel->center_freq % refclk_freq < 10) ||
115 (channel->center_freq % refclk_freq > 22)))
122 * Used to modify RF Banks before writing them to AR5K_RF_BUFFER
124 static unsigned int ath5k_hw_rfb_op(struct ath5k_hw *ah,
125 const struct ath5k_rf_reg *rf_regs,
126 u32 val, u8 reg_id, bool set)
128 const struct ath5k_rf_reg *rfreg = NULL;
129 u8 offset, bank, num_bits, col, position;
131 u32 mask, data, last_bit, bits_shifted, first_bit;
137 rfb = ah->ah_rf_banks;
139 for (i = 0; i < ah->ah_rf_regs_count; i++) {
140 if (rf_regs[i].index == reg_id) {
146 if (rfb == NULL || rfreg == NULL) {
147 ATH5K_PRINTF("Rf register not found!\n");
148 /* should not happen */
153 num_bits = rfreg->field.len;
154 first_bit = rfreg->field.pos;
155 col = rfreg->field.col;
157 /* first_bit is an offset from bank's
158 * start. Since we have all banks on
159 * the same array, we use this offset
160 * to mark each bank's start */
161 offset = ah->ah_offset[bank];
164 if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
165 ATH5K_PRINTF("invalid values at offset %u\n", offset);
169 entry = ((first_bit - 1) / 8) + offset;
170 position = (first_bit - 1) % 8;
173 data = ath5k_hw_bitswap(val, num_bits);
175 for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
176 position = 0, entry++) {
178 last_bit = (position + bits_left > 8) ? 8 :
179 position + bits_left;
181 mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
186 rfb[entry] |= ((data << position) << (col * 8)) & mask;
187 data >>= (8 - position);
189 data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
191 bits_shifted += last_bit - position;
194 bits_left -= 8 - position;
197 data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
203 * ath5k_hw_write_ofdm_timings - set OFDM timings on AR5212
205 * @ah: the &struct ath5k_hw
206 * @channel: the currently set channel upon reset
208 * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
209 * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
211 * Since delta slope is floating point we split it on its exponent and
212 * mantissa and provide these values on hw.
214 * For more infos i think this patent is related
215 * http://www.freepatentsonline.com/7184495.html
217 static inline int ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
218 struct ieee80211_channel *channel)
220 /* Get exponent and mantissa and set it */
221 u32 coef_scaled, coef_exp, coef_man,
222 ds_coef_exp, ds_coef_man, clock;
224 BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
225 !(channel->hw_value & CHANNEL_OFDM));
228 * ALGO: coef = (5 * clock / carrier_freq) / 2
229 * we scale coef by shifting clock value by 24 for
230 * better precision since we use integers */
231 switch (ah->ah_bwmode) {
232 case AR5K_BWMODE_40MHZ:
235 case AR5K_BWMODE_10MHZ:
238 case AR5K_BWMODE_5MHZ:
245 coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
248 * ALGO: coef_exp = 14 - highest set bit position */
249 coef_exp = ilog2(coef_scaled);
251 /* Doesn't make sense if it's zero*/
252 if (!coef_scaled || !coef_exp)
255 /* Note: we've shifted coef_scaled by 24 */
256 coef_exp = 14 - (coef_exp - 24);
259 /* Get mantissa (significant digits)
260 * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
261 coef_man = coef_scaled +
262 (1 << (24 - coef_exp - 1));
264 /* Calculate delta slope coefficient exponent
265 * and mantissa (remove scaling) and set them on hw */
266 ds_coef_man = coef_man >> (24 - coef_exp);
267 ds_coef_exp = coef_exp - 16;
269 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
270 AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
271 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
272 AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
277 int ath5k_hw_phy_disable(struct ath5k_hw *ah)
280 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
286 /**********************\
287 * RF Gain optimization *
288 \**********************/
291 * This code is used to optimize RF gain on different environments
292 * (temperature mostly) based on feedback from a power detector.
294 * It's only used on RF5111 and RF5112, later RF chips seem to have
295 * auto adjustment on hw -notice they have a much smaller BANK 7 and
296 * no gain optimization ladder-.
298 * For more infos check out this patent doc
299 * http://www.freepatentsonline.com/7400691.html
301 * This paper describes power drops as seen on the receiver due to
303 * http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
304 * %20of%20Power%20Control.pdf
306 * And this is the MadWiFi bug entry related to the above
307 * http://madwifi-project.org/ticket/1659
308 * with various measurements and diagrams
310 * TODO: Deal with power drops due to probes by setting an apropriate
311 * tx power on the probe packets ! Make this part of the calibration process.
314 /* Initialize ah_gain durring attach */
315 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
317 /* Initialize the gain optimization values */
318 switch (ah->ah_radio) {
320 ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
321 ah->ah_gain.g_low = 20;
322 ah->ah_gain.g_high = 35;
323 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
326 ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
327 ah->ah_gain.g_low = 20;
328 ah->ah_gain.g_high = 85;
329 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
338 /* Schedule a gain probe check on the next transmited packet.
339 * That means our next packet is going to be sent with lower
340 * tx power and a Peak to Average Power Detector (PAPD) will try
341 * to measure the gain.
343 * XXX: How about forcing a tx packet (bypassing PCU arbitrator etc)
344 * just after we enable the probe so that we don't mess with
345 * standard traffic ? Maybe it's time to use sw interrupts and
346 * a probe tasklet !!!
348 static void ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
351 /* Skip if gain calibration is inactive or
352 * we already handle a probe request */
353 if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
356 /* Send the packet with 2dB below max power as
357 * patent doc suggest */
358 ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
359 AR5K_PHY_PAPD_PROBE_TXPOWER) |
360 AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
362 ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
366 /* Calculate gain_F measurement correction
367 * based on the current step for RF5112 rev. 2 */
368 static u32 ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
372 const struct ath5k_gain_opt *go;
373 const struct ath5k_gain_opt_step *g_step;
374 const struct ath5k_rf_reg *rf_regs;
376 /* Only RF5112 Rev. 2 supports it */
377 if ((ah->ah_radio != AR5K_RF5112) ||
378 (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
381 go = &rfgain_opt_5112;
382 rf_regs = rf_regs_5112a;
383 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
385 g_step = &go->go_step[ah->ah_gain.g_step_idx];
387 if (ah->ah_rf_banks == NULL)
390 rf = ah->ah_rf_banks;
391 ah->ah_gain.g_f_corr = 0;
393 /* No VGA (Variable Gain Amplifier) override, skip */
394 if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
397 /* Mix gain stepping */
398 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
400 /* Mix gain override */
401 mix = g_step->gos_param[0];
405 ah->ah_gain.g_f_corr = step * 2;
408 ah->ah_gain.g_f_corr = (step - 5) * 2;
411 ah->ah_gain.g_f_corr = step;
414 ah->ah_gain.g_f_corr = 0;
418 return ah->ah_gain.g_f_corr;
421 /* Check if current gain_F measurement is in the range of our
422 * power detector windows. If we get a measurement outside range
423 * we know it's not accurate (detectors can't measure anything outside
424 * their detection window) so we must ignore it */
425 static bool ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
427 const struct ath5k_rf_reg *rf_regs;
428 u32 step, mix_ovr, level[4];
431 if (ah->ah_rf_banks == NULL)
434 rf = ah->ah_rf_banks;
436 if (ah->ah_radio == AR5K_RF5111) {
438 rf_regs = rf_regs_5111;
439 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
441 step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
445 level[1] = (step == 63) ? 50 : step + 4;
446 level[2] = (step != 63) ? 64 : level[0];
447 level[3] = level[2] + 50 ;
449 ah->ah_gain.g_high = level[3] -
450 (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
451 ah->ah_gain.g_low = level[0] +
452 (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
455 rf_regs = rf_regs_5112;
456 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
458 mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
461 level[0] = level[2] = 0;
464 level[1] = level[3] = 83;
466 level[1] = level[3] = 107;
467 ah->ah_gain.g_high = 55;
471 return (ah->ah_gain.g_current >= level[0] &&
472 ah->ah_gain.g_current <= level[1]) ||
473 (ah->ah_gain.g_current >= level[2] &&
474 ah->ah_gain.g_current <= level[3]);
477 /* Perform gain_F adjustment by choosing the right set
478 * of parameters from RF gain optimization ladder */
479 static s8 ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
481 const struct ath5k_gain_opt *go;
482 const struct ath5k_gain_opt_step *g_step;
485 switch (ah->ah_radio) {
487 go = &rfgain_opt_5111;
490 go = &rfgain_opt_5112;
496 g_step = &go->go_step[ah->ah_gain.g_step_idx];
498 if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
500 /* Reached maximum */
501 if (ah->ah_gain.g_step_idx == 0)
504 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
505 ah->ah_gain.g_target >= ah->ah_gain.g_high &&
506 ah->ah_gain.g_step_idx > 0;
507 g_step = &go->go_step[ah->ah_gain.g_step_idx])
508 ah->ah_gain.g_target -= 2 *
509 (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
516 if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
518 /* Reached minimum */
519 if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
522 for (ah->ah_gain.g_target = ah->ah_gain.g_current;
523 ah->ah_gain.g_target <= ah->ah_gain.g_low &&
524 ah->ah_gain.g_step_idx < go->go_steps_count-1;
525 g_step = &go->go_step[ah->ah_gain.g_step_idx])
526 ah->ah_gain.g_target -= 2 *
527 (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
535 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
536 "ret %d, gain step %u, current gain %u, target gain %u\n",
537 ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
538 ah->ah_gain.g_target);
543 /* Main callback for thermal RF gain calibration engine
544 * Check for a new gain reading and schedule an adjustment
547 * TODO: Use sw interrupt to schedule reset if gain_F needs
549 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
552 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
554 if (ah->ah_rf_banks == NULL ||
555 ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
556 return AR5K_RFGAIN_INACTIVE;
558 /* No check requested, either engine is inactive
559 * or an adjustment is already requested */
560 if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
563 /* Read the PAPD (Peak to Average Power Detector)
565 data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
567 /* No probe is scheduled, read gain_F measurement */
568 if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
569 ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
570 type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
572 /* If tx packet is CCK correct the gain_F measurement
573 * by cck ofdm gain delta */
574 if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
575 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
576 ah->ah_gain.g_current +=
577 ee->ee_cck_ofdm_gain_delta;
579 ah->ah_gain.g_current +=
580 AR5K_GAIN_CCK_PROBE_CORR;
583 /* Further correct gain_F measurement for
585 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
586 ath5k_hw_rf_gainf_corr(ah);
587 ah->ah_gain.g_current =
588 ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
589 (ah->ah_gain.g_current-ah->ah_gain.g_f_corr) :
593 /* Check if measurement is ok and if we need
594 * to adjust gain, schedule a gain adjustment,
595 * else switch back to the acive state */
596 if (ath5k_hw_rf_check_gainf_readback(ah) &&
597 AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
598 ath5k_hw_rf_gainf_adjust(ah)) {
599 ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
601 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
606 return ah->ah_gain.g_state;
609 /* Write initial RF gain table to set the RF sensitivity
610 * this one works on all RF chips and has nothing to do
611 * with gain_F calibration */
612 static int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq)
614 const struct ath5k_ini_rfgain *ath5k_rfg;
615 unsigned int i, size;
617 switch (ah->ah_radio) {
619 ath5k_rfg = rfgain_5111;
620 size = ARRAY_SIZE(rfgain_5111);
623 ath5k_rfg = rfgain_5112;
624 size = ARRAY_SIZE(rfgain_5112);
627 ath5k_rfg = rfgain_2413;
628 size = ARRAY_SIZE(rfgain_2413);
631 ath5k_rfg = rfgain_2316;
632 size = ARRAY_SIZE(rfgain_2316);
635 ath5k_rfg = rfgain_5413;
636 size = ARRAY_SIZE(rfgain_5413);
640 ath5k_rfg = rfgain_2425;
641 size = ARRAY_SIZE(rfgain_2425);
648 case AR5K_INI_RFGAIN_2GHZ:
649 case AR5K_INI_RFGAIN_5GHZ:
655 for (i = 0; i < size; i++) {
657 ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[freq],
658 (u32)ath5k_rfg[i].rfg_register);
666 /********************\
667 * RF Registers setup *
668 \********************/
671 * Setup RF registers by writing RF buffer on hw
673 static int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
674 struct ieee80211_channel *channel, unsigned int mode)
676 const struct ath5k_rf_reg *rf_regs;
677 const struct ath5k_ini_rfbuffer *ini_rfb;
678 const struct ath5k_gain_opt *go = NULL;
679 const struct ath5k_gain_opt_step *g_step;
680 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
683 int i, obdb = -1, bank = -1;
685 switch (ah->ah_radio) {
687 rf_regs = rf_regs_5111;
688 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
690 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
691 go = &rfgain_opt_5111;
694 if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
695 rf_regs = rf_regs_5112a;
696 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
698 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
700 rf_regs = rf_regs_5112;
701 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
703 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
705 go = &rfgain_opt_5112;
708 rf_regs = rf_regs_2413;
709 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
711 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
714 rf_regs = rf_regs_2316;
715 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
717 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
720 rf_regs = rf_regs_5413;
721 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
723 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
726 rf_regs = rf_regs_2425;
727 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
729 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
732 rf_regs = rf_regs_2425;
733 ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
734 if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
736 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
739 ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
746 /* If it's the first time we set RF buffer, allocate
747 * ah->ah_rf_banks based on ah->ah_rf_banks_size
749 if (ah->ah_rf_banks == NULL) {
750 ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
752 if (ah->ah_rf_banks == NULL) {
753 ATH5K_ERR(ah->ah_sc, "out of memory\n");
758 /* Copy values to modify them */
759 rfb = ah->ah_rf_banks;
761 for (i = 0; i < ah->ah_rf_banks_size; i++) {
762 if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
763 ATH5K_ERR(ah->ah_sc, "invalid bank\n");
767 /* Bank changed, write down the offset */
768 if (bank != ini_rfb[i].rfb_bank) {
769 bank = ini_rfb[i].rfb_bank;
770 ah->ah_offset[bank] = i;
773 rfb[i] = ini_rfb[i].rfb_mode_data[mode];
776 /* Set Output and Driver bias current (OB/DB) */
777 if (channel->hw_value & CHANNEL_2GHZ) {
779 if (channel->hw_value & CHANNEL_CCK)
780 ee_mode = AR5K_EEPROM_MODE_11B;
782 ee_mode = AR5K_EEPROM_MODE_11G;
784 /* For RF511X/RF211X combination we
785 * use b_OB and b_DB parameters stored
786 * in eeprom on ee->ee_ob[ee_mode][0]
788 * For all other chips we use OB/DB for 2Ghz
789 * stored in the b/g modal section just like
790 * 802.11a on ee->ee_ob[ee_mode][1] */
791 if ((ah->ah_radio == AR5K_RF5111) ||
792 (ah->ah_radio == AR5K_RF5112))
797 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
798 AR5K_RF_OB_2GHZ, true);
800 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
801 AR5K_RF_DB_2GHZ, true);
803 /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
804 } else if ((channel->hw_value & CHANNEL_5GHZ) ||
805 (ah->ah_radio == AR5K_RF5111)) {
807 /* For 11a, Turbo and XR we need to choose
808 * OB/DB based on frequency range */
809 ee_mode = AR5K_EEPROM_MODE_11A;
810 obdb = channel->center_freq >= 5725 ? 3 :
811 (channel->center_freq >= 5500 ? 2 :
812 (channel->center_freq >= 5260 ? 1 :
813 (channel->center_freq > 4000 ? 0 : -1)));
818 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
819 AR5K_RF_OB_5GHZ, true);
821 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
822 AR5K_RF_DB_5GHZ, true);
825 g_step = &go->go_step[ah->ah_gain.g_step_idx];
827 /* Bank Modifications (chip-specific) */
828 if (ah->ah_radio == AR5K_RF5111) {
830 /* Set gain_F settings according to current step */
831 if (channel->hw_value & CHANNEL_OFDM) {
833 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
834 AR5K_PHY_FRAME_CTL_TX_CLIP,
835 g_step->gos_param[0]);
837 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
838 AR5K_RF_PWD_90, true);
840 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
841 AR5K_RF_PWD_84, true);
843 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
844 AR5K_RF_RFGAIN_SEL, true);
846 /* We programmed gain_F parameters, switch back
848 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
854 ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
855 AR5K_RF_PWD_XPD, true);
857 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
858 AR5K_RF_XPD_GAIN, true);
860 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
861 AR5K_RF_GAIN_I, true);
863 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
864 AR5K_RF_PLO_SEL, true);
866 /* Tweak power detectors for half/quarter rate support */
867 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
868 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
871 ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
872 AR5K_RF_WAIT_S, true);
874 wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
877 ath5k_hw_rfb_op(ah, rf_regs, wait_i,
878 AR5K_RF_WAIT_I, true);
879 ath5k_hw_rfb_op(ah, rf_regs, 3,
880 AR5K_RF_MAX_TIME, true);
885 if (ah->ah_radio == AR5K_RF5112) {
887 /* Set gain_F settings according to current step */
888 if (channel->hw_value & CHANNEL_OFDM) {
890 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
891 AR5K_RF_MIXGAIN_OVR, true);
893 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
894 AR5K_RF_PWD_138, true);
896 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
897 AR5K_RF_PWD_137, true);
899 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
900 AR5K_RF_PWD_136, true);
902 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
903 AR5K_RF_PWD_132, true);
905 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
906 AR5K_RF_PWD_131, true);
908 ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
909 AR5K_RF_PWD_130, true);
911 /* We programmed gain_F parameters, switch back
913 ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
918 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
919 AR5K_RF_XPD_SEL, true);
921 if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
922 /* Rev. 1 supports only one xpd */
923 ath5k_hw_rfb_op(ah, rf_regs,
924 ee->ee_x_gain[ee_mode],
925 AR5K_RF_XPD_GAIN, true);
928 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
929 if (ee->ee_pd_gains[ee_mode] > 1) {
930 ath5k_hw_rfb_op(ah, rf_regs,
932 AR5K_RF_PD_GAIN_LO, true);
933 ath5k_hw_rfb_op(ah, rf_regs,
935 AR5K_RF_PD_GAIN_HI, true);
937 ath5k_hw_rfb_op(ah, rf_regs,
939 AR5K_RF_PD_GAIN_LO, true);
940 ath5k_hw_rfb_op(ah, rf_regs,
942 AR5K_RF_PD_GAIN_HI, true);
945 /* Lower synth voltage on Rev 2 */
946 ath5k_hw_rfb_op(ah, rf_regs, 2,
947 AR5K_RF_HIGH_VC_CP, true);
949 ath5k_hw_rfb_op(ah, rf_regs, 2,
950 AR5K_RF_MID_VC_CP, true);
952 ath5k_hw_rfb_op(ah, rf_regs, 2,
953 AR5K_RF_LOW_VC_CP, true);
955 ath5k_hw_rfb_op(ah, rf_regs, 2,
956 AR5K_RF_PUSH_UP, true);
958 /* Decrease power consumption on 5213+ BaseBand */
959 if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
960 ath5k_hw_rfb_op(ah, rf_regs, 1,
961 AR5K_RF_PAD2GND, true);
963 ath5k_hw_rfb_op(ah, rf_regs, 1,
964 AR5K_RF_XB2_LVL, true);
966 ath5k_hw_rfb_op(ah, rf_regs, 1,
967 AR5K_RF_XB5_LVL, true);
969 ath5k_hw_rfb_op(ah, rf_regs, 1,
970 AR5K_RF_PWD_167, true);
972 ath5k_hw_rfb_op(ah, rf_regs, 1,
973 AR5K_RF_PWD_166, true);
977 ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
978 AR5K_RF_GAIN_I, true);
980 /* Tweak power detector for half/quarter rates */
981 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
982 ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
985 pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
988 ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
989 AR5K_RF_PD_PERIOD_A, true);
990 ath5k_hw_rfb_op(ah, rf_regs, 0xf,
991 AR5K_RF_PD_DELAY_A, true);
996 if (ah->ah_radio == AR5K_RF5413 &&
997 channel->hw_value & CHANNEL_2GHZ) {
999 ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
1002 /* Set optimum value for early revisions (on pci-e chips) */
1003 if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
1004 ah->ah_mac_srev < AR5K_SREV_AR5413)
1005 ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
1006 AR5K_RF_PWD_ICLOBUF_2G, true);
1010 /* Write RF banks on hw */
1011 for (i = 0; i < ah->ah_rf_banks_size; i++) {
1013 ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
1020 /**************************\
1021 PHY/RF channel functions
1022 \**************************/
1025 * Convertion needed for RF5110
1027 static u32 ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
1032 * Convert IEEE channel/MHz to an internal channel value used
1033 * by the AR5210 chipset. This has not been verified with
1034 * newer chipsets like the AR5212A who have a completely
1035 * different RF/PHY part.
1037 athchan = (ath5k_hw_bitswap(
1038 (ieee80211_frequency_to_channel(
1039 channel->center_freq) - 24) / 2, 5)
1040 << 1) | (1 << 6) | 0x1;
1045 * Set channel on RF5110
1047 static int ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
1048 struct ieee80211_channel *channel)
1053 * Set the channel and wait
1055 data = ath5k_hw_rf5110_chan2athchan(channel);
1056 ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
1057 ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
1064 * Convertion needed for 5111
1066 static int ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
1067 struct ath5k_athchan_2ghz *athchan)
1071 /* Cast this value to catch negative channel numbers (>= -19) */
1072 channel = (int)ieee;
1075 * Map 2GHz IEEE channel to 5GHz Atheros channel
1077 if (channel <= 13) {
1078 athchan->a2_athchan = 115 + channel;
1079 athchan->a2_flags = 0x46;
1080 } else if (channel == 14) {
1081 athchan->a2_athchan = 124;
1082 athchan->a2_flags = 0x44;
1083 } else if (channel >= 15 && channel <= 26) {
1084 athchan->a2_athchan = ((channel - 14) * 4) + 132;
1085 athchan->a2_flags = 0x46;
1093 * Set channel on 5111
1095 static int ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
1096 struct ieee80211_channel *channel)
1098 struct ath5k_athchan_2ghz ath5k_channel_2ghz;
1099 unsigned int ath5k_channel =
1100 ieee80211_frequency_to_channel(channel->center_freq);
1101 u32 data0, data1, clock;
1105 * Set the channel on the RF5111 radio
1109 if (channel->hw_value & CHANNEL_2GHZ) {
1110 /* Map 2GHz channel to 5GHz Atheros channel ID */
1111 ret = ath5k_hw_rf5111_chan2athchan(
1112 ieee80211_frequency_to_channel(channel->center_freq),
1113 &ath5k_channel_2ghz);
1117 ath5k_channel = ath5k_channel_2ghz.a2_athchan;
1118 data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
1122 if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
1124 data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
1125 (clock << 1) | (1 << 10) | 1;
1128 data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
1129 << 2) | (clock << 1) | (1 << 10) | 1;
1132 ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
1134 ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
1135 AR5K_RF_BUFFER_CONTROL_3);
1141 * Set channel on 5112 and newer
1143 static int ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
1144 struct ieee80211_channel *channel)
1146 u32 data, data0, data1, data2;
1149 data = data0 = data1 = data2 = 0;
1150 c = channel->center_freq;
1153 if (!((c - 2224) % 5)) {
1154 data0 = ((2 * (c - 704)) - 3040) / 10;
1156 } else if (!((c - 2192) % 5)) {
1157 data0 = ((2 * (c - 672)) - 3040) / 10;
1162 data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
1163 } else if ((c % 5) != 2 || c > 5435) {
1164 if (!(c % 20) && c >= 5120) {
1165 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1166 data2 = ath5k_hw_bitswap(3, 2);
1167 } else if (!(c % 10)) {
1168 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1169 data2 = ath5k_hw_bitswap(2, 2);
1170 } else if (!(c % 5)) {
1171 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1172 data2 = ath5k_hw_bitswap(1, 2);
1176 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1177 data2 = ath5k_hw_bitswap(0, 2);
1180 data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
1182 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1183 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1189 * Set the channel on the RF2425
1191 static int ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
1192 struct ieee80211_channel *channel)
1194 u32 data, data0, data2;
1197 data = data0 = data2 = 0;
1198 c = channel->center_freq;
1201 data0 = ath5k_hw_bitswap((c - 2272), 8);
1204 } else if ((c % 5) != 2 || c > 5435) {
1205 if (!(c % 20) && c < 5120)
1206 data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
1208 data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
1210 data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
1213 data2 = ath5k_hw_bitswap(1, 2);
1215 data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
1216 data2 = ath5k_hw_bitswap(0, 2);
1219 data = (data0 << 4) | data2 << 2 | 0x1001;
1221 ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
1222 ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
1228 * Set a channel on the radio chip
1230 static int ath5k_hw_channel(struct ath5k_hw *ah,
1231 struct ieee80211_channel *channel)
1235 * Check bounds supported by the PHY (we don't care about regultory
1236 * restrictions at this point). Note: hw_value already has the band
1237 * (CHANNEL_2GHZ, or CHANNEL_5GHZ) so we inform ath5k_channel_ok()
1238 * of the band by that */
1239 if (!ath5k_channel_ok(ah, channel->center_freq, channel->hw_value)) {
1240 ATH5K_ERR(ah->ah_sc,
1241 "channel frequency (%u MHz) out of supported "
1243 channel->center_freq);
1248 * Set the channel and wait
1250 switch (ah->ah_radio) {
1252 ret = ath5k_hw_rf5110_channel(ah, channel);
1255 ret = ath5k_hw_rf5111_channel(ah, channel);
1258 ret = ath5k_hw_rf2425_channel(ah, channel);
1261 ret = ath5k_hw_rf5112_channel(ah, channel);
1268 /* Set JAPAN setting for channel 14 */
1269 if (channel->center_freq == 2484) {
1270 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1271 AR5K_PHY_CCKTXCTL_JAPAN);
1273 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
1274 AR5K_PHY_CCKTXCTL_WORLD);
1277 ah->ah_current_channel = channel;
1286 static s32 ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
1290 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
1291 return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
1294 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
1298 ah->ah_nfcal_hist.index = 0;
1299 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
1300 ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1303 static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
1305 struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
1306 hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX-1);
1307 hist->nfval[hist->index] = noise_floor;
1310 static s16 ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
1312 s16 sort[ATH5K_NF_CAL_HIST_MAX];
1316 memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
1317 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
1318 for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
1319 if (sort[j] > sort[j-1]) {
1321 sort[j] = sort[j-1];
1326 for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
1327 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1328 "cal %d:%d\n", i, sort[i]);
1330 return sort[(ATH5K_NF_CAL_HIST_MAX-1) / 2];
1334 * When we tell the hardware to perform a noise floor calibration
1335 * by setting the AR5K_PHY_AGCCTL_NF bit, it will periodically
1336 * sample-and-hold the minimum noise level seen at the antennas.
1337 * This value is then stored in a ring buffer of recently measured
1338 * noise floor values so we have a moving window of the last few
1341 * The median of the values in the history is then loaded into the
1342 * hardware for its own use for RSSI and CCA measurements.
1344 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
1346 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1351 /* keep last value if calibration hasn't completed */
1352 if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
1353 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1354 "NF did not complete in calibration window\n");
1359 switch (ah->ah_current_channel->hw_value & CHANNEL_MODES) {
1362 ee_mode = AR5K_EEPROM_MODE_11A;
1365 ee_mode = AR5K_EEPROM_MODE_11G;
1369 ee_mode = AR5K_EEPROM_MODE_11B;
1374 /* completed NF calibration, test threshold */
1375 nf = ath5k_hw_read_measured_noise_floor(ah);
1376 threshold = ee->ee_noise_floor_thr[ee_mode];
1378 if (nf > threshold) {
1379 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1380 "noise floor failure detected; "
1381 "read %d, threshold %d\n",
1384 nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
1387 ath5k_hw_update_nfcal_hist(ah, nf);
1388 nf = ath5k_hw_get_median_noise_floor(ah);
1390 /* load noise floor (in .5 dBm) so the hardware will use it */
1391 val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
1392 val |= (nf * 2) & AR5K_PHY_NF_M;
1393 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1395 AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1396 ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
1398 ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
1402 * Load a high max CCA Power value (-50 dBm in .5 dBm units)
1403 * so that we're not capped by the median we just loaded.
1404 * This will be used as the initial value for the next noise
1405 * floor calibration.
1407 val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
1408 ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
1409 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1410 AR5K_PHY_AGCCTL_NF_EN |
1411 AR5K_PHY_AGCCTL_NF_NOUPDATE |
1412 AR5K_PHY_AGCCTL_NF);
1414 ah->ah_noise_floor = nf;
1416 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1417 "noise floor calibrated: %d\n", nf);
1421 * Perform a PHY calibration on RF5110
1422 * -Fix BPSK/QAM Constellation (I/Q correction)
1424 static int ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
1425 struct ieee80211_channel *channel)
1427 u32 phy_sig, phy_agc, phy_sat, beacon;
1431 * Disable beacons and RX/TX queues, wait
1433 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
1434 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1435 beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
1436 ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
1441 * Set the channel (with AGC turned off)
1443 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1445 ret = ath5k_hw_channel(ah, channel);
1448 * Activate PHY and wait
1450 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
1453 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1459 * Calibrate the radio chip
1462 /* Remember normal state */
1463 phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
1464 phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
1465 phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
1467 /* Update radio registers */
1468 ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
1469 AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
1471 ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
1472 AR5K_PHY_AGCCOARSE_LO)) |
1473 AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
1474 AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
1476 ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
1477 AR5K_PHY_ADCSAT_THR)) |
1478 AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
1479 AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
1483 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1485 ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
1486 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
1491 * Enable calibration and wait until completion
1493 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
1495 ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
1496 AR5K_PHY_AGCCTL_CAL, 0, false);
1498 /* Reset to normal state */
1499 ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
1500 ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
1501 ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
1504 ATH5K_ERR(ah->ah_sc, "calibration timeout (%uMHz)\n",
1505 channel->center_freq);
1510 * Re-enable RX/TX and beacons
1512 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
1513 AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
1514 ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
1520 * Perform I/Q calibration on RF5111/5112 and newer chips
1523 ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
1526 s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
1529 if (!ah->ah_calibration ||
1530 ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN)
1533 /* Calibration has finished, get the results and re-run */
1534 /* work around empty results which can apparently happen on 5212 */
1535 for (i = 0; i <= 10; i++) {
1536 iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
1537 i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
1538 q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
1539 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1540 "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
1545 i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
1547 if (ah->ah_version == AR5K_AR5211)
1548 q_coffd = q_pwr >> 6;
1550 q_coffd = q_pwr >> 7;
1552 /* protect against divide by 0 and loss of sign bits */
1553 if (i_coffd == 0 || q_coffd < 2)
1556 i_coff = (-iq_corr) / i_coffd;
1557 i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
1559 if (ah->ah_version == AR5K_AR5211)
1560 q_coff = (i_pwr / q_coffd) - 64;
1562 q_coff = (i_pwr / q_coffd) - 128;
1563 q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
1565 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_CALIBRATE,
1566 "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
1567 i_coff, q_coff, i_coffd, q_coffd);
1569 /* Commit new I/Q values (set enable bit last to match HAL sources) */
1570 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
1571 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
1572 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
1574 /* Re-enable calibration -if we don't we'll commit
1575 * the same values again and again */
1576 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
1577 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
1578 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
1584 * Perform a PHY calibration
1586 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
1587 struct ieee80211_channel *channel)
1591 if (ah->ah_radio == AR5K_RF5110)
1592 ret = ath5k_hw_rf5110_calibrate(ah, channel);
1594 ret = ath5k_hw_rf511x_iq_calibrate(ah);
1595 ath5k_hw_request_rfgain_probe(ah);
1602 /***************************\
1603 * Spur mitigation functions *
1604 \***************************/
1607 ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
1608 struct ieee80211_channel *channel)
1610 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
1611 u32 mag_mask[4] = {0, 0, 0, 0};
1612 u32 pilot_mask[2] = {0, 0};
1613 /* Note: fbin values are scaled up by 2 */
1614 u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
1615 s32 spur_delta_phase, spur_freq_sigma_delta;
1616 s32 spur_offset, num_symbols_x16;
1617 u8 num_symbol_offsets, i, freq_band;
1619 /* Convert current frequency to fbin value (the same way channels
1620 * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
1621 * up by 2 so we can compare it later */
1622 if (channel->hw_value & CHANNEL_2GHZ) {
1623 chan_fbin = (channel->center_freq - 2300) * 10;
1624 freq_band = AR5K_EEPROM_BAND_2GHZ;
1626 chan_fbin = (channel->center_freq - 4900) * 10;
1627 freq_band = AR5K_EEPROM_BAND_5GHZ;
1630 /* Check if any spur_chan_fbin from EEPROM is
1631 * within our current channel's spur detection range */
1632 spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
1633 spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
1634 /* XXX: Half/Quarter channels ?*/
1635 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
1636 spur_detection_window *= 2;
1638 for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
1639 spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
1641 /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
1642 * so it's zero if we got nothing from EEPROM */
1643 if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
1644 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1648 if ((chan_fbin - spur_detection_window <=
1649 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
1650 (chan_fbin + spur_detection_window >=
1651 (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
1652 spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
1657 /* We need to enable spur filter for this channel */
1658 if (spur_chan_fbin) {
1659 spur_offset = spur_chan_fbin - chan_fbin;
1662 * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
1663 * spur_delta_phase -> spur_offset / chip_freq << 11
1664 * Note: Both values have 100Hz resolution
1666 switch (ah->ah_bwmode) {
1667 case AR5K_BWMODE_40MHZ:
1668 /* Both sample_freq and chip_freq are 80MHz */
1669 spur_delta_phase = (spur_offset << 16) / 25;
1670 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1671 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
1673 case AR5K_BWMODE_10MHZ:
1674 /* Both sample_freq and chip_freq are 20MHz (?) */
1675 spur_delta_phase = (spur_offset << 18) / 25;
1676 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1677 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
1678 case AR5K_BWMODE_5MHZ:
1679 /* Both sample_freq and chip_freq are 10MHz (?) */
1680 spur_delta_phase = (spur_offset << 19) / 25;
1681 spur_freq_sigma_delta = (spur_delta_phase >> 10);
1682 symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
1684 if (channel->hw_value == CHANNEL_A) {
1685 /* Both sample_freq and chip_freq are 40MHz */
1686 spur_delta_phase = (spur_offset << 17) / 25;
1687 spur_freq_sigma_delta =
1688 (spur_delta_phase >> 10);
1690 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1692 /* sample_freq -> 40MHz chip_freq -> 44MHz
1693 * (for b compatibility) */
1694 spur_delta_phase = (spur_offset << 17) / 25;
1695 spur_freq_sigma_delta =
1696 (spur_offset << 8) / 55;
1698 AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
1703 /* Calculate pilot and magnitude masks */
1705 /* Scale up spur_offset by 1000 to switch to 100HZ resolution
1706 * and divide by symbol_width to find how many symbols we have
1707 * Note: number of symbols is scaled up by 16 */
1708 num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
1710 /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
1711 if (!(num_symbols_x16 & 0xF))
1713 num_symbol_offsets = 3;
1716 num_symbol_offsets = 4;
1718 for (i = 0; i < num_symbol_offsets; i++) {
1720 /* Calculate pilot mask */
1722 (num_symbols_x16 / 16) + i + 25;
1724 /* Pilot magnitude mask seems to be a way to
1725 * declare the boundaries for our detection
1726 * window or something, it's 2 for the middle
1727 * value(s) where the symbol is expected to be
1728 * and 1 on the boundary values */
1730 (i == 0 || i == (num_symbol_offsets - 1))
1733 if (curr_sym_off >= 0 && curr_sym_off <= 32) {
1734 if (curr_sym_off <= 25)
1735 pilot_mask[0] |= 1 << curr_sym_off;
1736 else if (curr_sym_off >= 27)
1737 pilot_mask[0] |= 1 << (curr_sym_off - 1);
1738 } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
1739 pilot_mask[1] |= 1 << (curr_sym_off - 33);
1741 /* Calculate magnitude mask (for viterbi decoder) */
1742 if (curr_sym_off >= -1 && curr_sym_off <= 14)
1744 plt_mag_map << (curr_sym_off + 1) * 2;
1745 else if (curr_sym_off >= 15 && curr_sym_off <= 30)
1747 plt_mag_map << (curr_sym_off - 15) * 2;
1748 else if (curr_sym_off >= 31 && curr_sym_off <= 46)
1750 plt_mag_map << (curr_sym_off - 31) * 2;
1751 else if (curr_sym_off >= 47 && curr_sym_off <= 53)
1753 plt_mag_map << (curr_sym_off - 47) * 2;
1757 /* Write settings on hw to enable spur filter */
1758 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1759 AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
1760 /* XXX: Self correlator also ? */
1761 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
1762 AR5K_PHY_IQ_PILOT_MASK_EN |
1763 AR5K_PHY_IQ_CHAN_MASK_EN |
1764 AR5K_PHY_IQ_SPUR_FILT_EN);
1766 /* Set delta phase and freq sigma delta */
1767 ath5k_hw_reg_write(ah,
1768 AR5K_REG_SM(spur_delta_phase,
1769 AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
1770 AR5K_REG_SM(spur_freq_sigma_delta,
1771 AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
1772 AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
1773 AR5K_PHY_TIMING_11);
1775 /* Write pilot masks */
1776 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
1777 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1778 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1781 ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
1782 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1783 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1786 /* Write magnitude masks */
1787 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
1788 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
1789 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
1790 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1791 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1794 ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
1795 ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
1796 ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
1797 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1798 AR5K_PHY_BIN_MASK2_4_MASK_4,
1801 } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
1802 AR5K_PHY_IQ_SPUR_FILT_EN) {
1803 /* Clean up spur mitigation settings and disable fliter */
1804 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1805 AR5K_PHY_BIN_MASK_CTL_RATE, 0);
1806 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
1807 AR5K_PHY_IQ_PILOT_MASK_EN |
1808 AR5K_PHY_IQ_CHAN_MASK_EN |
1809 AR5K_PHY_IQ_SPUR_FILT_EN);
1810 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
1812 /* Clear pilot masks */
1813 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
1814 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
1815 AR5K_PHY_TIMING_8_PILOT_MASK_2,
1818 ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
1819 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
1820 AR5K_PHY_TIMING_10_PILOT_MASK_2,
1823 /* Clear magnitude masks */
1824 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
1825 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
1826 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
1827 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
1828 AR5K_PHY_BIN_MASK_CTL_MASK_4,
1831 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
1832 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
1833 ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
1834 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
1835 AR5K_PHY_BIN_MASK2_4_MASK_4,
1845 static void /*TODO:Boundary check*/
1846 ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
1848 if (ah->ah_version != AR5K_AR5210)
1849 ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
1853 * Enable/disable fast rx antenna diversity
1856 ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
1859 case AR5K_EEPROM_MODE_11G:
1860 /* XXX: This is set to
1861 * disabled on initvals !!! */
1862 case AR5K_EEPROM_MODE_11A:
1864 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
1865 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1867 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1868 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1870 case AR5K_EEPROM_MODE_11B:
1871 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
1872 AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
1879 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1880 AR5K_PHY_RESTART_DIV_GC, 4);
1882 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1883 AR5K_PHY_FAST_ANT_DIV_EN);
1885 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
1886 AR5K_PHY_RESTART_DIV_GC, 0);
1888 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
1889 AR5K_PHY_FAST_ANT_DIV_EN);
1894 ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
1899 * In case a fixed antenna was set as default
1900 * use the same switch table twice.
1902 if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
1903 ant0 = ant1 = AR5K_ANT_SWTABLE_A;
1904 else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
1905 ant0 = ant1 = AR5K_ANT_SWTABLE_B;
1907 ant0 = AR5K_ANT_SWTABLE_A;
1908 ant1 = AR5K_ANT_SWTABLE_B;
1911 /* Set antenna idle switch table */
1912 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
1913 AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
1914 (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
1915 AR5K_PHY_ANT_CTL_TXRX_EN));
1917 /* Set antenna switch tables */
1918 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
1919 AR5K_PHY_ANT_SWITCH_TABLE_0);
1920 ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
1921 AR5K_PHY_ANT_SWITCH_TABLE_1);
1925 * Set antenna operating mode
1928 ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
1930 struct ieee80211_channel *channel = ah->ah_current_channel;
1931 bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
1932 bool use_def_for_sg;
1933 u8 def_ant, tx_ant, ee_mode;
1936 /* if channel is not initialized yet we can't set the antennas
1937 * so just store the mode. it will be set on the next reset */
1938 if (channel == NULL) {
1939 ah->ah_ant_mode = ant_mode;
1943 def_ant = ah->ah_def_ant;
1945 switch (channel->hw_value & CHANNEL_MODES) {
1948 ee_mode = AR5K_EEPROM_MODE_11A;
1951 ee_mode = AR5K_EEPROM_MODE_11G;
1954 ee_mode = AR5K_EEPROM_MODE_11B;
1957 ATH5K_ERR(ah->ah_sc,
1958 "invalid channel: %d\n", channel->center_freq);
1963 case AR5K_ANTMODE_DEFAULT:
1965 use_def_for_tx = false;
1966 update_def_on_tx = false;
1967 use_def_for_rts = false;
1968 use_def_for_sg = false;
1971 case AR5K_ANTMODE_FIXED_A:
1974 use_def_for_tx = true;
1975 update_def_on_tx = false;
1976 use_def_for_rts = true;
1977 use_def_for_sg = true;
1980 case AR5K_ANTMODE_FIXED_B:
1983 use_def_for_tx = true;
1984 update_def_on_tx = false;
1985 use_def_for_rts = true;
1986 use_def_for_sg = true;
1989 case AR5K_ANTMODE_SINGLE_AP:
1990 def_ant = 1; /* updated on tx */
1992 use_def_for_tx = true;
1993 update_def_on_tx = true;
1994 use_def_for_rts = true;
1995 use_def_for_sg = true;
1998 case AR5K_ANTMODE_SECTOR_AP:
1999 tx_ant = 1; /* variable */
2000 use_def_for_tx = false;
2001 update_def_on_tx = false;
2002 use_def_for_rts = true;
2003 use_def_for_sg = false;
2006 case AR5K_ANTMODE_SECTOR_STA:
2007 tx_ant = 1; /* variable */
2008 use_def_for_tx = true;
2009 update_def_on_tx = false;
2010 use_def_for_rts = true;
2011 use_def_for_sg = false;
2014 case AR5K_ANTMODE_DEBUG:
2017 use_def_for_tx = false;
2018 update_def_on_tx = false;
2019 use_def_for_rts = false;
2020 use_def_for_sg = false;
2027 ah->ah_tx_ant = tx_ant;
2028 ah->ah_ant_mode = ant_mode;
2029 ah->ah_def_ant = def_ant;
2031 sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
2032 sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
2033 sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
2034 sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
2036 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
2039 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
2041 ath5k_hw_set_antenna_switch(ah, ee_mode);
2042 /* Note: set diversity before default antenna
2043 * because it won't work correctly */
2044 ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
2045 ath5k_hw_set_def_antenna(ah, def_ant);
2058 * Do linear interpolation between two given (x, y) points
2061 ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
2062 s16 y_left, s16 y_right)
2066 /* Avoid divide by zero and skip interpolation
2067 * if we have the same point */
2068 if ((x_left == x_right) || (y_left == y_right))
2072 * Since we use ints and not fps, we need to scale up in
2073 * order to get a sane ratio value (or else we 'll eg. get
2074 * always 1 instead of 1.25, 1.75 etc). We scale up by 100
2075 * to have some accuracy both for 0.5 and 0.25 steps.
2077 ratio = ((100 * y_right - 100 * y_left)/(x_right - x_left));
2079 /* Now scale down to be in range */
2080 result = y_left + (ratio * (target - x_left) / 100);
2086 * Find vertical boundary (min pwr) for the linear PCDAC curve.
2088 * Since we have the top of the curve and we draw the line below
2089 * until we reach 1 (1 pcdac step) we need to know which point
2090 * (x value) that is so that we don't go below y axis and have negative
2091 * pcdac values when creating the curve, or fill the table with zeroes.
2094 ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
2095 const s16 *pwrL, const s16 *pwrR)
2098 s16 min_pwrL, min_pwrR;
2101 /* Some vendors write the same pcdac value twice !!! */
2102 if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
2103 return max(pwrL[0], pwrR[0]);
2105 if (pwrL[0] == pwrL[1])
2111 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2113 stepL[0], stepL[1]);
2119 if (pwrR[0] == pwrR[1])
2125 tmp = (s8) ath5k_get_interpolated_value(pwr_i,
2127 stepR[0], stepR[1]);
2133 /* Keep the right boundary so that it works for both curves */
2134 return max(min_pwrL, min_pwrR);
2138 * Interpolate (pwr,vpd) points to create a Power to PDADC or a
2139 * Power to PCDAC curve.
2141 * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
2142 * steps (offsets) on y axis. Power can go up to 31.5dB and max
2143 * PCDAC/PDADC step for each curve is 64 but we can write more than
2144 * one curves on hw so we can go up to 128 (which is the max step we
2145 * can write on the final table).
2147 * We write y values (PCDAC/PDADC steps) on hw.
2150 ath5k_create_power_curve(s16 pmin, s16 pmax,
2151 const s16 *pwr, const u8 *vpd,
2153 u8 *vpd_table, u8 type)
2155 u8 idx[2] = { 0, 1 };
2162 /* We want the whole line, so adjust boundaries
2163 * to cover the entire power range. Note that
2164 * power values are already 0.25dB so no need
2165 * to multiply pwr_i by 2 */
2166 if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
2172 /* Find surrounding turning points (TPs)
2173 * and interpolate between them */
2174 for (i = 0; (i <= (u16) (pmax - pmin)) &&
2175 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2177 /* We passed the right TP, move to the next set of TPs
2178 * if we pass the last TP, extrapolate above using the last
2179 * two TPs for ratio */
2180 if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
2185 vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
2186 pwr[idx[0]], pwr[idx[1]],
2187 vpd[idx[0]], vpd[idx[1]]);
2189 /* Increase by 0.5dB
2190 * (0.25 dB units) */
2196 * Get the surrounding per-channel power calibration piers
2197 * for a given frequency so that we can interpolate between
2198 * them and come up with an apropriate dataset for our current
2202 ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
2203 struct ieee80211_channel *channel,
2204 struct ath5k_chan_pcal_info **pcinfo_l,
2205 struct ath5k_chan_pcal_info **pcinfo_r)
2207 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2208 struct ath5k_chan_pcal_info *pcinfo;
2211 u32 target = channel->center_freq;
2216 if (!(channel->hw_value & CHANNEL_OFDM)) {
2217 pcinfo = ee->ee_pwr_cal_b;
2218 mode = AR5K_EEPROM_MODE_11B;
2219 } else if (channel->hw_value & CHANNEL_2GHZ) {
2220 pcinfo = ee->ee_pwr_cal_g;
2221 mode = AR5K_EEPROM_MODE_11G;
2223 pcinfo = ee->ee_pwr_cal_a;
2224 mode = AR5K_EEPROM_MODE_11A;
2226 max = ee->ee_n_piers[mode] - 1;
2228 /* Frequency is below our calibrated
2229 * range. Use the lowest power curve
2231 if (target < pcinfo[0].freq) {
2236 /* Frequency is above our calibrated
2237 * range. Use the highest power curve
2239 if (target > pcinfo[max].freq) {
2240 idx_l = idx_r = max;
2244 /* Frequency is inside our calibrated
2245 * channel range. Pick the surrounding
2246 * calibration piers so that we can
2248 for (i = 0; i <= max; i++) {
2250 /* Frequency matches one of our calibration
2251 * piers, no need to interpolate, just use
2252 * that calibration pier */
2253 if (pcinfo[i].freq == target) {
2258 /* We found a calibration pier that's above
2259 * frequency, use this pier and the previous
2260 * one to interpolate */
2261 if (target < pcinfo[i].freq) {
2269 *pcinfo_l = &pcinfo[idx_l];
2270 *pcinfo_r = &pcinfo[idx_r];
2274 * Get the surrounding per-rate power calibration data
2275 * for a given frequency and interpolate between power
2276 * values to set max target power supported by hw for
2280 ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
2281 struct ieee80211_channel *channel,
2282 struct ath5k_rate_pcal_info *rates)
2284 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2285 struct ath5k_rate_pcal_info *rpinfo;
2288 u32 target = channel->center_freq;
2293 if (!(channel->hw_value & CHANNEL_OFDM)) {
2294 rpinfo = ee->ee_rate_tpwr_b;
2295 mode = AR5K_EEPROM_MODE_11B;
2296 } else if (channel->hw_value & CHANNEL_2GHZ) {
2297 rpinfo = ee->ee_rate_tpwr_g;
2298 mode = AR5K_EEPROM_MODE_11G;
2300 rpinfo = ee->ee_rate_tpwr_a;
2301 mode = AR5K_EEPROM_MODE_11A;
2303 max = ee->ee_rate_target_pwr_num[mode] - 1;
2305 /* Get the surrounding calibration
2306 * piers - same as above */
2307 if (target < rpinfo[0].freq) {
2312 if (target > rpinfo[max].freq) {
2313 idx_l = idx_r = max;
2317 for (i = 0; i <= max; i++) {
2319 if (rpinfo[i].freq == target) {
2324 if (target < rpinfo[i].freq) {
2332 /* Now interpolate power value, based on the frequency */
2333 rates->freq = target;
2335 rates->target_power_6to24 =
2336 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2338 rpinfo[idx_l].target_power_6to24,
2339 rpinfo[idx_r].target_power_6to24);
2341 rates->target_power_36 =
2342 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2344 rpinfo[idx_l].target_power_36,
2345 rpinfo[idx_r].target_power_36);
2347 rates->target_power_48 =
2348 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2350 rpinfo[idx_l].target_power_48,
2351 rpinfo[idx_r].target_power_48);
2353 rates->target_power_54 =
2354 ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
2356 rpinfo[idx_l].target_power_54,
2357 rpinfo[idx_r].target_power_54);
2361 * Get the max edge power for this channel if
2362 * we have such data from EEPROM's Conformance Test
2363 * Limits (CTL), and limit max power if needed.
2366 ath5k_get_max_ctl_power(struct ath5k_hw *ah,
2367 struct ieee80211_channel *channel)
2369 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
2370 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2371 struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
2372 u8 *ctl_val = ee->ee_ctl;
2373 s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
2378 u32 target = channel->center_freq;
2380 ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
2382 switch (channel->hw_value & CHANNEL_MODES) {
2384 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2385 ctl_mode |= AR5K_CTL_TURBO;
2387 ctl_mode |= AR5K_CTL_11A;
2390 if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
2391 ctl_mode |= AR5K_CTL_TURBOG;
2393 ctl_mode |= AR5K_CTL_11G;
2396 ctl_mode |= AR5K_CTL_11B;
2404 for (i = 0; i < ee->ee_ctls; i++) {
2405 if (ctl_val[i] == ctl_mode) {
2411 /* If we have a CTL dataset available grab it and find the
2412 * edge power for our frequency */
2413 if (ctl_idx == 0xFF)
2416 /* Edge powers are sorted by frequency from lower
2417 * to higher. Each CTL corresponds to 8 edge power
2419 rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
2421 /* Don't do boundaries check because we
2422 * might have more that one bands defined
2425 /* Get the edge power that's closer to our
2427 for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
2429 if (target <= rep[rep_idx].freq)
2430 edge_pwr = (s16) rep[rep_idx].edge;
2434 ah->ah_txpower.txp_max_pwr = 4*min(edge_pwr, max_chan_pwr);
2439 * Power to PCDAC table functions
2443 * Fill Power to PCDAC table on RF5111
2445 * No further processing is needed for RF5111, the only thing we have to
2446 * do is fill the values below and above calibration range since eeprom data
2447 * may not cover the entire PCDAC table.
2450 ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
2453 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2454 u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
2455 u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
2456 s16 min_pwr, max_pwr;
2458 /* Get table boundaries */
2459 min_pwr = table_min[0];
2460 pcdac_0 = pcdac_tmp[0];
2462 max_pwr = table_max[0];
2463 pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
2465 /* Extrapolate below minimum using pcdac_0 */
2467 for (i = 0; i < min_pwr; i++)
2468 pcdac_out[pcdac_i++] = pcdac_0;
2470 /* Copy values from pcdac_tmp */
2472 for (i = 0 ; pwr_idx <= max_pwr &&
2473 pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
2474 pcdac_out[pcdac_i++] = pcdac_tmp[i];
2478 /* Extrapolate above maximum */
2479 while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
2480 pcdac_out[pcdac_i++] = pcdac_n;
2485 * Combine available XPD Curves and fill Linear Power to PCDAC table
2488 * RFX112 can have up to 2 curves (one for low txpower range and one for
2489 * higher txpower range). We need to put them both on pcdac_out and place
2490 * them in the correct location. In case we only have one curve available
2491 * just fit it on pcdac_out (it's supposed to cover the entire range of
2492 * available pwr levels since it's always the higher power curve). Extrapolate
2493 * below and above final table if needed.
2496 ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
2497 s16 *table_max, u8 pdcurves)
2499 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2506 s16 mid_pwr_idx = 0;
2507 /* Edge flag turs on the 7nth bit on the PCDAC
2508 * to delcare the higher power curve (force values
2509 * to be greater than 64). If we only have one curve
2510 * we don't need to set this, if we have 2 curves and
2511 * fill the table backwards this can also be used to
2512 * switch from higher power curve to lower power curve */
2516 /* When we have only one curve available
2517 * that's the higher power curve. If we have
2518 * two curves the first is the high power curve
2519 * and the next is the low power curve. */
2521 pcdac_low_pwr = ah->ah_txpower.tmpL[1];
2522 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2523 mid_pwr_idx = table_max[1] - table_min[1] - 1;
2524 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2526 /* If table size goes beyond 31.5dB, keep the
2527 * upper 31.5dB range when setting tx power.
2528 * Note: 126 = 31.5 dB in quarter dB steps */
2529 if (table_max[0] - table_min[1] > 126)
2530 min_pwr_idx = table_max[0] - 126;
2532 min_pwr_idx = table_min[1];
2534 /* Since we fill table backwards
2535 * start from high power curve */
2536 pcdac_tmp = pcdac_high_pwr;
2540 pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
2541 pcdac_high_pwr = ah->ah_txpower.tmpL[0];
2542 min_pwr_idx = table_min[0];
2543 max_pwr_idx = (table_max[0] - table_min[0]) / 2;
2544 pcdac_tmp = pcdac_high_pwr;
2548 /* This is used when setting tx power*/
2549 ah->ah_txpower.txp_min_idx = min_pwr_idx/2;
2551 /* Fill Power to PCDAC table backwards */
2553 for (i = 63; i >= 0; i--) {
2554 /* Entering lower power range, reset
2555 * edge flag and set pcdac_tmp to lower
2557 if (edge_flag == 0x40 &&
2558 (2*pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
2560 pcdac_tmp = pcdac_low_pwr;
2561 pwr = mid_pwr_idx/2;
2564 /* Don't go below 1, extrapolate below if we have
2565 * already swithced to the lower power curve -or
2566 * we only have one curve and edge_flag is zero
2568 if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
2570 pcdac_out[i] = pcdac_out[i + 1];
2576 pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
2578 /* Extrapolate above if pcdac is greater than
2579 * 126 -this can happen because we OR pcdac_out
2580 * value with edge_flag on high power curve */
2581 if (pcdac_out[i] > 126)
2584 /* Decrease by a 0.5dB step */
2589 /* Write PCDAC values on hw */
2591 ath5k_setup_pcdac_table(struct ath5k_hw *ah)
2593 u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
2597 * Write TX power values
2599 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2600 ath5k_hw_reg_write(ah,
2601 (((pcdac_out[2*i + 0] << 8 | 0xff) & 0xffff) << 0) |
2602 (((pcdac_out[2*i + 1] << 8 | 0xff) & 0xffff) << 16),
2603 AR5K_PHY_PCDAC_TXPOWER(i));
2609 * Power to PDADC table functions
2613 * Set the gain boundaries and create final Power to PDADC table
2615 * We can have up to 4 pd curves, we need to do a simmilar process
2616 * as we do for RF5112. This time we don't have an edge_flag but we
2617 * set the gain boundaries on a separate register.
2620 ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
2621 s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
2623 u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
2624 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2627 u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
2630 /* Note: Register value is initialized on initvals
2631 * there is no feedback from hw.
2632 * XXX: What about pd_gain_overlap from EEPROM ? */
2633 pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
2634 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
2636 /* Create final PDADC table */
2637 for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
2638 pdadc_tmp = ah->ah_txpower.tmpL[pdg];
2640 if (pdg == pdcurves - 1)
2641 /* 2 dB boundary stretch for last
2642 * (higher power) curve */
2643 gain_boundaries[pdg] = pwr_max[pdg] + 4;
2645 /* Set gain boundary in the middle
2646 * between this curve and the next one */
2647 gain_boundaries[pdg] =
2648 (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
2650 /* Sanity check in case our 2 db stretch got out of
2652 if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
2653 gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
2655 /* For the first curve (lower power)
2656 * start from 0 dB */
2660 /* For the other curves use the gain overlap */
2661 pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
2664 /* Force each power step to be at least 0.5 dB */
2665 if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
2666 pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
2670 /* If pdadc_0 is negative, we need to extrapolate
2671 * below this pdgain by a number of pwr_steps */
2672 while ((pdadc_0 < 0) && (pdadc_i < 128)) {
2673 s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
2674 pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
2678 /* Set last pwr level, using gain boundaries */
2679 pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
2680 /* Limit it to be inside pwr range */
2681 table_size = pwr_max[pdg] - pwr_min[pdg];
2682 max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
2684 /* Fill pdadc_out table */
2685 while (pdadc_0 < max_idx && pdadc_i < 128)
2686 pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
2688 /* Need to extrapolate above this pdgain? */
2689 if (pdadc_n <= max_idx)
2692 /* Force each power step to be at least 0.5 dB */
2693 if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
2694 pwr_step = pdadc_tmp[table_size - 1] -
2695 pdadc_tmp[table_size - 2];
2699 /* Extrapolate above */
2700 while ((pdadc_0 < (s16) pdadc_n) &&
2701 (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
2702 s16 tmp = pdadc_tmp[table_size - 1] +
2703 (pdadc_0 - max_idx) * pwr_step;
2704 pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
2709 while (pdg < AR5K_EEPROM_N_PD_GAINS) {
2710 gain_boundaries[pdg] = gain_boundaries[pdg - 1];
2714 while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
2715 pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
2719 /* Set gain boundaries */
2720 ath5k_hw_reg_write(ah,
2721 AR5K_REG_SM(pd_gain_overlap,
2722 AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
2723 AR5K_REG_SM(gain_boundaries[0],
2724 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
2725 AR5K_REG_SM(gain_boundaries[1],
2726 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
2727 AR5K_REG_SM(gain_boundaries[2],
2728 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
2729 AR5K_REG_SM(gain_boundaries[3],
2730 AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
2733 /* Used for setting rate power table */
2734 ah->ah_txpower.txp_min_idx = pwr_min[0];
2738 /* Write PDADC values on hw */
2740 ath5k_setup_pwr_to_pdadc_table(struct ath5k_hw *ah,
2741 u8 pdcurves, u8 *pdg_to_idx)
2743 u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
2747 /* Select the right pdgain curves */
2749 /* Clear current settings */
2750 reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
2751 reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
2752 AR5K_PHY_TPC_RG1_PDGAIN_2 |
2753 AR5K_PHY_TPC_RG1_PDGAIN_3 |
2754 AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2757 * Use pd_gains curve from eeprom
2759 * This overrides the default setting from initvals
2760 * in case some vendors (e.g. Zcomax) don't use the default
2761 * curves. If we don't honor their settings we 'll get a
2762 * 5dB (1 * gain overlap ?) drop.
2764 reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
2768 reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
2771 reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
2774 reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
2777 ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
2780 * Write TX power values
2782 for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
2783 ath5k_hw_reg_write(ah,
2784 ((pdadc_out[4*i + 0] & 0xff) << 0) |
2785 ((pdadc_out[4*i + 1] & 0xff) << 8) |
2786 ((pdadc_out[4*i + 2] & 0xff) << 16) |
2787 ((pdadc_out[4*i + 3] & 0xff) << 24),
2788 AR5K_PHY_PDADC_TXPOWER(i));
2794 * Common code for PCDAC/PDADC tables
2798 * This is the main function that uses all of the above
2799 * to set PCDAC/PDADC table on hw for the current channel.
2800 * This table is used for tx power calibration on the basband,
2801 * without it we get weird tx power levels and in some cases
2802 * distorted spectral mask
2805 ath5k_setup_channel_powertable(struct ath5k_hw *ah,
2806 struct ieee80211_channel *channel,
2807 u8 ee_mode, u8 type)
2809 struct ath5k_pdgain_info *pdg_L, *pdg_R;
2810 struct ath5k_chan_pcal_info *pcinfo_L;
2811 struct ath5k_chan_pcal_info *pcinfo_R;
2812 struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
2813 u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
2814 s16 table_min[AR5K_EEPROM_N_PD_GAINS];
2815 s16 table_max[AR5K_EEPROM_N_PD_GAINS];
2818 u32 target = channel->center_freq;
2821 /* Get surounding freq piers for this channel */
2822 ath5k_get_chan_pcal_surrounding_piers(ah, channel,
2826 /* Loop over pd gain curves on
2827 * surounding freq piers by index */
2828 for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
2830 /* Fill curves in reverse order
2831 * from lower power (max gain)
2832 * to higher power. Use curve -> idx
2833 * backmapping we did on eeprom init */
2834 u8 idx = pdg_curve_to_idx[pdg];
2836 /* Grab the needed curves by index */
2837 pdg_L = &pcinfo_L->pd_curves[idx];
2838 pdg_R = &pcinfo_R->pd_curves[idx];
2840 /* Initialize the temp tables */
2841 tmpL = ah->ah_txpower.tmpL[pdg];
2842 tmpR = ah->ah_txpower.tmpR[pdg];
2844 /* Set curve's x boundaries and create
2845 * curves so that they cover the same
2846 * range (if we don't do that one table
2847 * will have values on some range and the
2848 * other one won't have any so interpolation
2850 table_min[pdg] = min(pdg_L->pd_pwr[0],
2851 pdg_R->pd_pwr[0]) / 2;
2853 table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2854 pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
2856 /* Now create the curves on surrounding channels
2857 * and interpolate if needed to get the final
2858 * curve for this gain on this channel */
2860 case AR5K_PWRTABLE_LINEAR_PCDAC:
2861 /* Override min/max so that we don't loose
2862 * accuracy (don't divide by 2) */
2863 table_min[pdg] = min(pdg_L->pd_pwr[0],
2867 max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
2868 pdg_R->pd_pwr[pdg_R->pd_points - 1]);
2870 /* Override minimum so that we don't get
2871 * out of bounds while extrapolating
2872 * below. Don't do this when we have 2
2873 * curves and we are on the high power curve
2874 * because table_min is ok in this case */
2875 if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
2878 ath5k_get_linear_pcdac_min(pdg_L->pd_step,
2883 /* Don't go too low because we will
2884 * miss the upper part of the curve.
2885 * Note: 126 = 31.5dB (max power supported)
2886 * in 0.25dB units */
2887 if (table_max[pdg] - table_min[pdg] > 126)
2888 table_min[pdg] = table_max[pdg] - 126;
2892 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2893 case AR5K_PWRTABLE_PWR_TO_PDADC:
2895 ath5k_create_power_curve(table_min[pdg],
2899 pdg_L->pd_points, tmpL, type);
2901 /* We are in a calibration
2902 * pier, no need to interpolate
2903 * between freq piers */
2904 if (pcinfo_L == pcinfo_R)
2907 ath5k_create_power_curve(table_min[pdg],
2911 pdg_R->pd_points, tmpR, type);
2917 /* Interpolate between curves
2918 * of surounding freq piers to
2919 * get the final curve for this
2920 * pd gain. Re-use tmpL for interpolation
2922 for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
2923 (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
2924 tmpL[i] = (u8) ath5k_get_interpolated_value(target,
2925 (s16) pcinfo_L->freq,
2926 (s16) pcinfo_R->freq,
2932 /* Now we have a set of curves for this
2933 * channel on tmpL (x range is table_max - table_min
2934 * and y values are tmpL[pdg][]) sorted in the same
2935 * order as EEPROM (because we've used the backmapping).
2936 * So for RF5112 it's from higher power to lower power
2937 * and for RF2413 it's from lower power to higher power.
2938 * For RF5111 we only have one curve. */
2940 /* Fill min and max power levels for this
2941 * channel by interpolating the values on
2942 * surounding channels to complete the dataset */
2943 ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
2944 (s16) pcinfo_L->freq,
2945 (s16) pcinfo_R->freq,
2946 pcinfo_L->min_pwr, pcinfo_R->min_pwr);
2948 ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
2949 (s16) pcinfo_L->freq,
2950 (s16) pcinfo_R->freq,
2951 pcinfo_L->max_pwr, pcinfo_R->max_pwr);
2953 /* We are ready to go, fill PCDAC/PDADC
2954 * table and write settings on hardware */
2956 case AR5K_PWRTABLE_LINEAR_PCDAC:
2957 /* For RF5112 we can have one or two curves
2958 * and each curve covers a certain power lvl
2959 * range so we need to do some more processing */
2960 ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
2961 ee->ee_pd_gains[ee_mode]);
2963 /* Set txp.offset so that we can
2964 * match max power value with max
2966 ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
2968 /* Write settings on hw */
2969 ath5k_setup_pcdac_table(ah);
2971 case AR5K_PWRTABLE_PWR_TO_PCDAC:
2972 /* We are done for RF5111 since it has only
2973 * one curve, just fit the curve on the table */
2974 ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
2976 /* No rate powertable adjustment for RF5111 */
2977 ah->ah_txpower.txp_min_idx = 0;
2978 ah->ah_txpower.txp_offset = 0;
2980 /* Write settings on hw */
2981 ath5k_setup_pcdac_table(ah);
2983 case AR5K_PWRTABLE_PWR_TO_PDADC:
2984 /* Set PDADC boundaries and fill
2985 * final PDADC table */
2986 ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
2987 ee->ee_pd_gains[ee_mode]);
2989 /* Write settings on hw */
2990 ath5k_setup_pwr_to_pdadc_table(ah, pdg, pdg_curve_to_idx);
2992 /* Set txp.offset, note that table_min
2993 * can be negative */
2994 ah->ah_txpower.txp_offset = table_min[0];
3005 * Per-rate tx power setting
3007 * This is the code that sets the desired tx power (below
3008 * maximum) on hw for each rate (we also have TPC that sets
3009 * power per packet). We do that by providing an index on the
3010 * PCDAC/PDADC table we set up.
3014 * Set rate power table
3016 * For now we only limit txpower based on maximum tx power
3017 * supported by hw (what's inside rate_info). We need to limit
3018 * this even more, based on regulatory domain etc.
3020 * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps)
3021 * and is indexed as follows:
3022 * rates[0] - rates[7] -> OFDM rates
3023 * rates[8] - rates[14] -> CCK rates
3024 * rates[15] -> XR rates (they all have the same power)
3027 ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
3028 struct ath5k_rate_pcal_info *rate_info,
3034 /* max_pwr is power level we got from driver/user in 0.5dB
3035 * units, switch to 0.25dB units so we can compare */
3037 max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
3039 /* apply rate limits */
3040 rates = ah->ah_txpower.txp_rates_power_table;
3042 /* OFDM rates 6 to 24Mb/s */
3043 for (i = 0; i < 5; i++)
3044 rates[i] = min(max_pwr, rate_info->target_power_6to24);
3046 /* Rest OFDM rates */
3047 rates[5] = min(rates[0], rate_info->target_power_36);
3048 rates[6] = min(rates[0], rate_info->target_power_48);
3049 rates[7] = min(rates[0], rate_info->target_power_54);
3053 rates[8] = min(rates[0], rate_info->target_power_6to24);
3055 rates[9] = min(rates[0], rate_info->target_power_36);
3057 rates[10] = min(rates[0], rate_info->target_power_36);
3059 rates[11] = min(rates[0], rate_info->target_power_48);
3061 rates[12] = min(rates[0], rate_info->target_power_48);
3063 rates[13] = min(rates[0], rate_info->target_power_54);
3065 rates[14] = min(rates[0], rate_info->target_power_54);
3068 rates[15] = min(rates[0], rate_info->target_power_6to24);
3070 /* CCK rates have different peak to average ratio
3071 * so we have to tweak their power so that gainf
3072 * correction works ok. For this we use OFDM to
3073 * CCK delta from eeprom */
3074 if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
3075 (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
3076 for (i = 8; i <= 15; i++)
3077 rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
3079 /* Now that we have all rates setup use table offset to
3080 * match the power range set by user with the power indices
3081 * on PCDAC/PDADC table */
3082 for (i = 0; i < 16; i++) {
3083 rates[i] += ah->ah_txpower.txp_offset;
3084 /* Don't get out of bounds */
3089 /* Min/max in 0.25dB units */
3090 ah->ah_txpower.txp_min_pwr = 2 * rates[7];
3091 ah->ah_txpower.txp_max_pwr = 2 * rates[0];
3092 ah->ah_txpower.txp_ofdm = rates[7];
3097 * Set transmission power
3100 ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3101 u8 ee_mode, u8 txpower, bool fast)
3103 struct ath5k_rate_pcal_info rate_info;
3107 if (txpower > AR5K_TUNE_MAX_TXPOWER) {
3108 ATH5K_ERR(ah->ah_sc, "invalid tx power: %u\n", txpower);
3112 /* Reset TX power values */
3113 memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
3114 ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
3115 ah->ah_txpower.txp_min_pwr = 0;
3116 ah->ah_txpower.txp_max_pwr = AR5K_TUNE_MAX_TXPOWER;
3118 /* Initialize TX power table */
3119 switch (ah->ah_radio) {
3124 type = AR5K_PWRTABLE_PWR_TO_PCDAC;
3127 type = AR5K_PWRTABLE_LINEAR_PCDAC;
3134 type = AR5K_PWRTABLE_PWR_TO_PDADC;
3140 /* If fast is set it means we are on the same channel/mode
3141 * so there is no need to recalculate the powertable, we 'll
3142 * just use the cached one */
3144 ret = ath5k_setup_channel_powertable(ah, channel,
3150 /* Limit max power if we have a CTL available */
3151 ath5k_get_max_ctl_power(ah, channel);
3153 /* FIXME: Antenna reduction stuff */
3155 /* FIXME: Limit power on turbo modes */
3157 /* FIXME: TPC scale reduction */
3159 /* Get surounding channels for per-rate power table
3161 ath5k_get_rate_pcal_data(ah, channel, &rate_info);
3163 /* Setup rate power table */
3164 ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
3166 /* Write rate power table on hw */
3167 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
3168 AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
3169 AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
3171 ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
3172 AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
3173 AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
3175 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
3176 AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
3177 AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
3179 ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
3180 AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
3181 AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
3183 /* FIXME: TPC support */
3184 if (ah->ah_txpower.txp_tpc) {
3185 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
3186 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3188 ath5k_hw_reg_write(ah,
3189 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
3190 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
3191 AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
3194 ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX |
3195 AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
3201 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
3204 struct ieee80211_channel *channel = ah->ah_current_channel;
3207 switch (channel->hw_value & CHANNEL_MODES) {
3210 ee_mode = AR5K_EEPROM_MODE_11A;
3213 ee_mode = AR5K_EEPROM_MODE_11G;
3216 ee_mode = AR5K_EEPROM_MODE_11B;
3219 ATH5K_ERR(ah->ah_sc,
3220 "invalid channel: %d\n", channel->center_freq);
3224 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_TXPOWER,
3225 "changing txpower to %d\n", txpower);
3227 return ath5k_hw_txpower(ah, channel, ee_mode, txpower, true);
3234 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
3235 u8 mode, u8 ee_mode, u8 freq, bool fast)
3237 struct ieee80211_channel *curr_channel;
3244 * Sanity check for fast flag
3245 * Don't try fast channel change when changing modulation
3246 * mode/band. We check for chip compatibility on
3249 curr_channel = ah->ah_current_channel;
3250 if (fast && (channel->hw_value != curr_channel->hw_value))
3254 * On fast channel change we only set the synth parameters
3255 * while PHY is running, enable calibration and skip the rest.
3258 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3259 AR5K_PHY_RFBUS_REQ_REQUEST);
3260 for (i = 0; i < 100; i++) {
3261 if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
3271 * If we don't change channel/mode skip
3272 * tx powertable calculation and use the
3275 if ((channel->hw_value == curr_channel->hw_value) &&
3276 (channel->center_freq == curr_channel->center_freq))
3284 * Note: We need to do that before we set
3285 * RF buffer settings on 5211/5212+ so that we
3286 * properly set curve indices.
3288 ret = ath5k_hw_txpower(ah, channel, ee_mode,
3289 ah->ah_txpower.txp_max_pwr / 2,
3295 * For 5210 we do all initialization using
3296 * initvals, so we don't have to modify
3297 * any settings (5210 also only supports
3300 if ((ah->ah_version != AR5K_AR5210) && !fast) {
3303 * Write initial RF gain settings
3304 * This should work for both 5111/5112
3306 ret = ath5k_hw_rfgain_init(ah, freq);
3315 ret = ath5k_hw_rfregs_init(ah, channel, mode);
3319 /* Write OFDM timings on 5212*/
3320 if (ah->ah_version == AR5K_AR5212 &&
3321 channel->hw_value & CHANNEL_OFDM) {
3323 ret = ath5k_hw_write_ofdm_timings(ah, channel);
3327 /* Spur info is available only from EEPROM versions
3328 * greater than 5.3, but the EEPROM routines will use
3329 * static values for older versions */
3330 if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
3331 ath5k_hw_set_spur_mitigation_filter(ah,
3335 /*Enable/disable 802.11b mode on 5111
3336 (enable 2111 frequency converter + CCK)*/
3337 if (ah->ah_radio == AR5K_RF5111) {
3338 if (mode == AR5K_MODE_11B)
3339 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
3342 AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
3346 } else if (ah->ah_version == AR5K_AR5210) {
3348 /* Disable phy and wait */
3349 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
3353 /* Set channel on PHY */
3354 ret = ath5k_hw_channel(ah, channel);
3359 * Enable the PHY and wait until completion
3360 * This includes BaseBand and Synthesizer
3363 ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
3366 * On 5211+ read activation -> rx delay
3369 if (ah->ah_version != AR5K_AR5210) {
3371 delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
3372 AR5K_PHY_RX_DELAY_M;
3373 delay = (channel->hw_value & CHANNEL_CCK) ?
3374 ((delay << 2) / 22) : (delay / 10);
3375 if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
3377 if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
3379 /* XXX: /2 on turbo ? Let's be safe
3381 udelay(100 + delay);
3388 * Release RF Bus grant
3390 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
3391 AR5K_PHY_RFBUS_REQ_REQUEST);
3394 * Perform ADC test to see if baseband is ready
3395 * Set tx hold and check adc test register
3397 phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
3398 ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
3399 for (i = 0; i <= 20; i++) {
3400 if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
3404 ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
3408 * Start automatic gain control calibration
3410 * During AGC calibration RX path is re-routed to
3411 * a power detector so we don't receive anything.
3413 * This method is used to calibrate some static offsets
3414 * used together with on-the fly I/Q calibration (the
3415 * one performed via ath5k_hw_phy_calibrate), which doesn't
3416 * interrupt rx path.
3418 * While rx path is re-routed to the power detector we also
3419 * start a noise floor calibration to measure the
3420 * card's noise floor (the noise we measure when we are not
3421 * transmitting or receiving anything).
3423 * If we are in a noisy environment, AGC calibration may time
3424 * out and/or noise floor calibration might timeout.
3426 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
3427 AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
3429 /* At the same time start I/Q calibration for QAM constellation
3430 * -no need for CCK- */
3431 ah->ah_calibration = false;
3432 if (!(mode == AR5K_MODE_11B)) {
3433 ah->ah_calibration = true;
3434 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
3435 AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
3436 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
3440 /* Wait for gain calibration to finish (we check for I/Q calibration
3441 * during ath5k_phy_calibrate) */
3442 if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
3443 AR5K_PHY_AGCCTL_CAL, 0, false)) {
3444 ATH5K_ERR(ah->ah_sc, "gain calibration timeout (%uMHz)\n",
3445 channel->center_freq);
3448 /* Restore antenna mode */
3449 ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);