2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 /*********************************\
24 * Protocol Control Unit Functions *
25 \*********************************/
27 #include <asm/unaligned.h>
39 * ath5k_hw_set_opmode - Set PCU operating mode
41 * @ah: The &struct ath5k_hw
42 * @op_mode: &enum nl80211_iftype operating mode
44 * Initialize PCU for the various operating modes (AP/STA etc)
46 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
48 struct ath_common *common = ath5k_hw_common(ah);
49 u32 pcu_reg, beacon_reg, low_id, high_id;
51 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
53 /* Preserve rest settings */
54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
55 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
56 | AR5K_STA_ID1_KEYSRCH_MODE
57 | (ah->ah_version == AR5K_AR5210 ?
58 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
63 case NL80211_IFTYPE_ADHOC:
64 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
65 beacon_reg |= AR5K_BCR_ADHOC;
66 if (ah->ah_version == AR5K_AR5210)
67 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
69 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
72 case NL80211_IFTYPE_AP:
73 case NL80211_IFTYPE_MESH_POINT:
74 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
75 beacon_reg |= AR5K_BCR_AP;
76 if (ah->ah_version == AR5K_AR5210)
77 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
79 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
82 case NL80211_IFTYPE_STATION:
83 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
84 | (ah->ah_version == AR5K_AR5210 ?
85 AR5K_STA_ID1_PWR_SV : 0);
86 case NL80211_IFTYPE_MONITOR:
87 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
88 | (ah->ah_version == AR5K_AR5210 ?
89 AR5K_STA_ID1_NO_PSPOLL : 0);
99 low_id = get_unaligned_le32(common->macaddr);
100 high_id = get_unaligned_le16(common->macaddr + 4);
101 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
102 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
105 * Set Beacon Control Register on 5210
107 if (ah->ah_version == AR5K_AR5210)
108 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
114 * ath5k_hw_update - Update MIB counters (mac layer statistics)
116 * @ah: The &struct ath5k_hw
118 * Reads MIB counters from PCU and updates sw statistics. Is called after a
119 * MIB interrupt, because one of these counters might have reached their maximum
120 * and triggered the MIB interrupt, to let us read and clear the counter.
122 * Is called in interrupt context!
124 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
126 struct ath5k_statistics *stats = &ah->ah_sc->stats;
129 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
130 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
131 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
132 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
133 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
137 * ath5k_hw_set_ack_bitrate - set bitrate for ACKs
139 * @ah: The &struct ath5k_hw
140 * @high: Flag to determine if we want to use high transmition rate
143 * If high flag is set, we tell hw to use a set of control rates based on
144 * the current transmition rate (check out control_rates array inside reset.c).
145 * If not hw just uses the lowest rate available for the current modulation
146 * scheme being used (1Mbit for CCK and 6Mbits for OFDM).
148 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
150 if (ah->ah_version != AR5K_AR5212)
153 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
155 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
157 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
167 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
169 * @ah: The &struct ath5k_hw
170 * @timeout: Timeout in usec
172 static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
174 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
178 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
179 ath5k_hw_htoclock(ah, timeout));
185 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
187 * @ah: The &struct ath5k_hw
188 * @timeout: Timeout in usec
190 static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
192 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
196 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
197 ath5k_hw_htoclock(ah, timeout));
203 * ath5k_hw_htoclock - Translate usec to hw clock units
205 * @ah: The &struct ath5k_hw
206 * @usec: value in microseconds
208 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
210 return usec * ath5k_hw_get_clockrate(ah);
214 * ath5k_hw_clocktoh - Translate hw clock units to usec
215 * @clock: value in hw clock units
217 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
219 return clock / ath5k_hw_get_clockrate(ah);
223 * ath5k_hw_get_clockrate - Get the clock rate for current mode
225 * @ah: The &struct ath5k_hw
227 unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah)
229 struct ieee80211_channel *channel = ah->ah_current_channel;
232 if (channel->hw_value & CHANNEL_5GHZ)
233 clock = 40; /* 802.11a */
234 else if (channel->hw_value & CHANNEL_CCK)
235 clock = 22; /* 802.11b */
237 clock = 44; /* 802.11g */
239 /* Clock rate in turbo modes is twice the normal rate */
240 if (channel->hw_value & CHANNEL_TURBO)
247 * ath5k_hw_get_default_slottime - Get the default slot time for current mode
249 * @ah: The &struct ath5k_hw
251 static unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
253 struct ieee80211_channel *channel = ah->ah_current_channel;
255 if (channel->hw_value & CHANNEL_TURBO)
256 return 6; /* both turbo modes */
258 if (channel->hw_value & CHANNEL_CCK)
259 return 20; /* 802.11b */
261 return 9; /* 802.11 a/g */
265 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
267 * @ah: The &struct ath5k_hw
269 static unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
271 struct ieee80211_channel *channel = ah->ah_current_channel;
273 if (channel->hw_value & CHANNEL_TURBO)
274 return 8; /* both turbo modes */
276 if (channel->hw_value & CHANNEL_5GHZ)
277 return 16; /* 802.11a */
279 return 10; /* 802.11 b/g */
283 * ath5k_hw_set_lladdr - Set station id
285 * @ah: The &struct ath5k_hw
286 * @mac: The card's mac address
288 * Set station id on hw using the provided mac address
290 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
292 struct ath_common *common = ath5k_hw_common(ah);
296 /* Set new station ID */
297 memcpy(common->macaddr, mac, ETH_ALEN);
299 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
301 low_id = get_unaligned_le32(mac);
302 high_id = get_unaligned_le16(mac + 4);
304 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
305 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
311 * ath5k_hw_set_associd - Set BSSID for association
313 * @ah: The &struct ath5k_hw
315 * @assoc_id: Assoc id
317 * Sets the BSSID which trigers the "SME Join" operation
319 void ath5k_hw_set_associd(struct ath5k_hw *ah)
321 struct ath_common *common = ath5k_hw_common(ah);
325 * Set simple BSSID mask on 5212
327 if (ah->ah_version == AR5K_AR5212)
328 ath_hw_setbssidmask(common);
331 * Set BSSID which triggers the "SME Join" operation
333 ath5k_hw_reg_write(ah,
334 get_unaligned_le32(common->curbssid),
336 ath5k_hw_reg_write(ah,
337 get_unaligned_le16(common->curbssid + 4) |
338 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S),
341 if (common->curaid == 0) {
342 ath5k_hw_disable_pspoll(ah);
346 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
347 tim_offset ? tim_offset + 4 : 0);
349 ath5k_hw_enable_pspoll(ah, NULL, 0);
352 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
354 struct ath_common *common = ath5k_hw_common(ah);
356 /* Cache bssid mask so that we can restore it
358 memcpy(common->bssidmask, mask, ETH_ALEN);
359 if (ah->ah_version == AR5K_AR5212)
360 ath_hw_setbssidmask(common);
368 * ath5k_hw_start_rx_pcu - Start RX engine
370 * @ah: The &struct ath5k_hw
372 * Starts RX engine on PCU so that hw can process RXed frames
375 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
377 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
379 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
383 * at5k_hw_stop_rx_pcu - Stop RX engine
385 * @ah: The &struct ath5k_hw
387 * Stops RX engine on PCU
389 * TODO: Detach ANI here
391 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
393 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
397 * Set multicast filter
399 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
401 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
402 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
406 * ath5k_hw_get_rx_filter - Get current rx filter
408 * @ah: The &struct ath5k_hw
410 * Returns the RX filter by reading rx filter and
411 * phy error filter registers. RX filter is used
412 * to set the allowed frame types that PCU will accept
413 * and pass to the driver. For a list of frame types
416 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
418 u32 data, filter = 0;
420 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
422 /*Radar detection for 5212*/
423 if (ah->ah_version == AR5K_AR5212) {
424 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
426 if (data & AR5K_PHY_ERR_FIL_RADAR)
427 filter |= AR5K_RX_FILTER_RADARERR;
428 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
429 filter |= AR5K_RX_FILTER_PHYERR;
436 * ath5k_hw_set_rx_filter - Set rx filter
438 * @ah: The &struct ath5k_hw
439 * @filter: RX filter mask (see reg.h)
441 * Sets RX filter register and also handles PHY error filter
442 * register on 5212 and newer chips so that we have proper PHY
445 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
449 /* Set PHY error filter register on 5212*/
450 if (ah->ah_version == AR5K_AR5212) {
451 if (filter & AR5K_RX_FILTER_RADARERR)
452 data |= AR5K_PHY_ERR_FIL_RADAR;
453 if (filter & AR5K_RX_FILTER_PHYERR)
454 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
458 * The AR5210 uses promiscous mode to detect radar activity
460 if (ah->ah_version == AR5K_AR5210 &&
461 (filter & AR5K_RX_FILTER_RADARERR)) {
462 filter &= ~AR5K_RX_FILTER_RADARERR;
463 filter |= AR5K_RX_FILTER_PROM;
466 /*Zero length DMA (phy error reporting) */
468 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
470 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
472 /*Write RX Filter register*/
473 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
475 /*Write PHY error filter register on 5212*/
476 if (ah->ah_version == AR5K_AR5212)
477 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
486 #define ATH5K_MAX_TSF_READ 10
489 * ath5k_hw_get_tsf64 - Get the full 64bit TSF
491 * @ah: The &struct ath5k_hw
493 * Returns the current TSF
495 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
497 u32 tsf_lower, tsf_upper1, tsf_upper2;
501 * While reading TSF upper and then lower part, the clock is still
502 * counting (or jumping in case of IBSS merge) so we might get
503 * inconsistent values. To avoid this, we read the upper part again
504 * and check it has not been changed. We make the hypothesis that a
505 * maximum of 3 changes can happens in a row (we use 10 as a safe
508 * Impact on performance is pretty small, since in most cases, only
509 * 3 register reads are needed.
512 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
513 for (i = 0; i < ATH5K_MAX_TSF_READ; i++) {
514 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
515 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
516 if (tsf_upper2 == tsf_upper1)
518 tsf_upper1 = tsf_upper2;
521 WARN_ON( i == ATH5K_MAX_TSF_READ );
523 return (((u64)tsf_upper1 << 32) | tsf_lower);
527 * ath5k_hw_set_tsf64 - Set a new 64bit TSF
529 * @ah: The &struct ath5k_hw
530 * @tsf64: The new 64bit TSF
534 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
536 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
537 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
541 * ath5k_hw_reset_tsf - Force a TSF reset
543 * @ah: The &struct ath5k_hw
545 * Forces a TSF reset on PCU
547 void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
551 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
554 * Each write to the RESET_TSF bit toggles a hardware internal
555 * signal to reset TSF, but if left high it will cause a TSF reset
556 * on the next chip reset as well. Thus we always write the value
557 * twice to clear the signal.
559 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
560 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
564 * Initialize beacon timers
566 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
568 u32 timer1, timer2, timer3;
571 * Set the additional timers by mode
573 switch (ah->ah_sc->opmode) {
574 case NL80211_IFTYPE_MONITOR:
575 case NL80211_IFTYPE_STATION:
576 /* In STA mode timer1 is used as next wakeup
577 * timer and timer2 as next CFP duration start
578 * timer. Both in 1/8TUs. */
579 /* TODO: PCF handling */
580 if (ah->ah_version == AR5K_AR5210) {
587 /* Mark associated AP as PCF incapable for now */
588 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF);
590 case NL80211_IFTYPE_ADHOC:
591 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
593 /* On non-STA modes timer1 is used as next DMA
594 * beacon alert (DBA) timer and timer2 as next
595 * software beacon alert. Both in 1/8TUs. */
596 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
597 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
601 /* Timer3 marks the end of our ATIM window
602 * a zero length window is not allowed because
603 * we 'll get no beacons */
604 timer3 = next_beacon + (ah->ah_atim_window ? ah->ah_atim_window : 1);
607 * Set the beacon register and enable all timers.
609 /* When in AP or Mesh Point mode zero timer0 to start TSF */
610 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP ||
611 ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT)
612 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
614 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
615 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
616 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
617 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
619 /* Force a TSF reset if requested and enable beacons */
620 if (interval & AR5K_BEACON_RESET_TSF)
621 ath5k_hw_reset_tsf(ah);
623 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
627 /* Flush any pending BMISS interrupts on ISR by
628 * performing a clear-on-write operation on PISR
629 * register for the BMISS bit (writing a bit on
630 * ISR togles a reset for that bit and leaves
631 * the rest bits intact) */
632 if (ah->ah_version == AR5K_AR5210)
633 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);
635 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);
637 /* TODO: Set enchanced sleep registers on AR5212
638 * based on vif->bss_conf params, until then
639 * disable power save reporting.*/
640 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
645 /*********************\
646 * Key table functions *
647 \*********************/
650 * Reset a key entry on the table
652 int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry)
654 unsigned int i, type;
655 u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
657 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
659 type = ath5k_hw_reg_read(ah, AR5K_KEYTABLE_TYPE(entry));
661 for (i = 0; i < AR5K_KEYCACHE_SIZE; i++)
662 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_OFF(entry, i));
664 /* Reset associated MIC entry if TKIP
665 * is enabled located at offset (entry + 64) */
666 if (type == AR5K_KEYTABLE_TYPE_TKIP) {
667 AR5K_ASSERT_ENTRY(micentry, AR5K_KEYTABLE_SIZE);
668 for (i = 0; i < AR5K_KEYCACHE_SIZE / 2 ; i++)
669 ath5k_hw_reg_write(ah, 0,
670 AR5K_KEYTABLE_OFF(micentry, i));
674 * Set NULL encryption on AR5212+
676 * Note: AR5K_KEYTABLE_TYPE -> AR5K_KEYTABLE_OFF(entry, 5)
677 * AR5K_KEYTABLE_TYPE_NULL -> 0x00000007
679 * Note2: Windows driver (ndiswrapper) sets this to
680 * 0x00000714 instead of 0x00000007
682 if (ah->ah_version >= AR5K_AR5211) {
683 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
684 AR5K_KEYTABLE_TYPE(entry));
686 if (type == AR5K_KEYTABLE_TYPE_TKIP) {
687 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
688 AR5K_KEYTABLE_TYPE(micentry));
696 int ath5k_keycache_type(const struct ieee80211_key_conf *key)
700 return AR5K_KEYTABLE_TYPE_TKIP;
702 return AR5K_KEYTABLE_TYPE_CCM;
704 if (key->keylen == WLAN_KEY_LEN_WEP40)
705 return AR5K_KEYTABLE_TYPE_40;
706 else if (key->keylen == WLAN_KEY_LEN_WEP104)
707 return AR5K_KEYTABLE_TYPE_104;
716 * Set a key entry on the table
718 int ath5k_hw_set_key(struct ath5k_hw *ah, u16 entry,
719 const struct ieee80211_key_conf *key, const u8 *mac)
723 __le32 key_v[5] = {};
724 __le32 key0 = 0, key1 = 0;
725 __le32 *rxmic, *txmic;
727 u16 micentry = entry + AR5K_KEYTABLE_MIC_OFFSET;
731 is_tkip = (key->alg == ALG_TKIP);
734 * key->keylen comes in from mac80211 in bytes.
735 * TKIP is 128 bit + 128 bit mic
737 keylen = (is_tkip) ? (128 / 8) : key->keylen;
739 if (entry > AR5K_KEYTABLE_SIZE ||
740 (is_tkip && micentry > AR5K_KEYTABLE_SIZE))
743 if (unlikely(keylen > 16))
746 keytype = ath5k_keycache_type(key);
751 * each key block is 6 bytes wide, written as pairs of
752 * alternating 32 and 16 bit le values.
755 for (i = 0; keylen >= 6; keylen -= 6) {
756 memcpy(&key_v[i], key_ptr, 6);
761 memcpy(&key_v[i], key_ptr, keylen);
763 /* intentionally corrupt key until mic is installed */
765 key0 = key_v[0] = ~key_v[0];
766 key1 = key_v[1] = ~key_v[1];
769 for (i = 0; i < ARRAY_SIZE(key_v); i++)
770 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
771 AR5K_KEYTABLE_OFF(entry, i));
773 ath5k_hw_reg_write(ah, keytype, AR5K_KEYTABLE_TYPE(entry));
776 /* Install rx/tx MIC */
777 rxmic = (__le32 *) &key->key[16];
778 txmic = (__le32 *) &key->key[24];
780 if (ah->ah_combined_mic) {
782 key_v[1] = cpu_to_le32(le32_to_cpu(txmic[0]) >> 16);
784 key_v[3] = cpu_to_le32(le32_to_cpu(txmic[0]) & 0xffff);
793 for (i = 0; i < ARRAY_SIZE(key_v); i++)
794 ath5k_hw_reg_write(ah, le32_to_cpu(key_v[i]),
795 AR5K_KEYTABLE_OFF(micentry, i));
797 ath5k_hw_reg_write(ah, AR5K_KEYTABLE_TYPE_NULL,
798 AR5K_KEYTABLE_TYPE(micentry));
799 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC0(micentry));
800 ath5k_hw_reg_write(ah, 0, AR5K_KEYTABLE_MAC1(micentry));
802 /* restore first 2 words of key */
803 ath5k_hw_reg_write(ah, le32_to_cpu(~key0),
804 AR5K_KEYTABLE_OFF(entry, 0));
805 ath5k_hw_reg_write(ah, le32_to_cpu(~key1),
806 AR5K_KEYTABLE_OFF(entry, 1));
809 return ath5k_hw_set_key_lladdr(ah, entry, mac);
812 int ath5k_hw_set_key_lladdr(struct ath5k_hw *ah, u16 entry, const u8 *mac)
816 /* Invalid entry (key table overflow) */
817 AR5K_ASSERT_ENTRY(entry, AR5K_KEYTABLE_SIZE);
820 * MAC may be NULL if it's a broadcast key. In this case no need to
821 * to compute get_unaligned_le32 and get_unaligned_le16 as we
826 high_id = 0xffff | AR5K_KEYTABLE_VALID;
828 low_id = get_unaligned_le32(mac);
829 high_id = get_unaligned_le16(mac + 4) | AR5K_KEYTABLE_VALID;
832 ath5k_hw_reg_write(ah, low_id, AR5K_KEYTABLE_MAC0(entry));
833 ath5k_hw_reg_write(ah, high_id, AR5K_KEYTABLE_MAC1(entry));
839 * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class
841 * @ah: The &struct ath5k_hw
842 * @coverage_class: IEEE 802.11 coverage class number
844 * Sets slot time, ACK timeout and CTS timeout for given coverage class.
846 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
848 /* As defined by IEEE 802.11-2007 17.3.8.6 */
849 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
850 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
851 int cts_timeout = ack_timeout;
853 ath5k_hw_set_slot_time(ah, slot_time);
854 ath5k_hw_set_ack_timeout(ah, ack_timeout);
855 ath5k_hw_set_cts_timeout(ah, cts_timeout);
857 ah->ah_coverage_class = coverage_class;