2 * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
4 * Copyright (c) 2007-2008 Matthew W. S. Bell <mentor@madwifi.org>
5 * Copyright (c) 2007-2008 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
6 * Copyright (c) 2007-2008 Pavel Roskin <proski@gnu.org>
7 * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
9 * Permission to use, copy, modify, and distribute this software for any
10 * purpose with or without fee is hereby granted, provided that the above
11 * copyright notice and this permission notice appear in all copies.
13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
14 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
15 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
16 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
17 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
18 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
19 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
23 /*********************************\
24 * Protocol Control Unit Functions *
25 \*********************************/
27 #include <asm/unaligned.h>
39 * ath5k_hw_set_opmode - Set PCU operating mode
41 * @ah: The &struct ath5k_hw
42 * @op_mode: &enum nl80211_iftype operating mode
44 * Initialize PCU for the various operating modes (AP/STA etc)
46 int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype op_mode)
48 struct ath_common *common = ath5k_hw_common(ah);
49 u32 pcu_reg, beacon_reg, low_id, high_id;
51 ATH5K_DBG(ah->ah_sc, ATH5K_DEBUG_MODE, "mode %d\n", op_mode);
53 /* Preserve rest settings */
54 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
55 pcu_reg &= ~(AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_AP
56 | AR5K_STA_ID1_KEYSRCH_MODE
57 | (ah->ah_version == AR5K_AR5210 ?
58 (AR5K_STA_ID1_PWR_SV | AR5K_STA_ID1_NO_PSPOLL) : 0));
63 case NL80211_IFTYPE_ADHOC:
64 pcu_reg |= AR5K_STA_ID1_ADHOC | AR5K_STA_ID1_KEYSRCH_MODE;
65 beacon_reg |= AR5K_BCR_ADHOC;
66 if (ah->ah_version == AR5K_AR5210)
67 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
69 AR5K_REG_ENABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
72 case NL80211_IFTYPE_AP:
73 case NL80211_IFTYPE_MESH_POINT:
74 pcu_reg |= AR5K_STA_ID1_AP | AR5K_STA_ID1_KEYSRCH_MODE;
75 beacon_reg |= AR5K_BCR_AP;
76 if (ah->ah_version == AR5K_AR5210)
77 pcu_reg |= AR5K_STA_ID1_NO_PSPOLL;
79 AR5K_REG_DISABLE_BITS(ah, AR5K_CFG, AR5K_CFG_IBSS);
82 case NL80211_IFTYPE_STATION:
83 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
84 | (ah->ah_version == AR5K_AR5210 ?
85 AR5K_STA_ID1_PWR_SV : 0);
86 case NL80211_IFTYPE_MONITOR:
87 pcu_reg |= AR5K_STA_ID1_KEYSRCH_MODE
88 | (ah->ah_version == AR5K_AR5210 ?
89 AR5K_STA_ID1_NO_PSPOLL : 0);
99 low_id = get_unaligned_le32(common->macaddr);
100 high_id = get_unaligned_le16(common->macaddr + 4);
101 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
102 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
105 * Set Beacon Control Register on 5210
107 if (ah->ah_version == AR5K_AR5210)
108 ath5k_hw_reg_write(ah, beacon_reg, AR5K_BCR);
114 * ath5k_hw_update - Update MIB counters (mac layer statistics)
116 * @ah: The &struct ath5k_hw
118 * Reads MIB counters from PCU and updates sw statistics. Is called after a
119 * MIB interrupt, because one of these counters might have reached their maximum
120 * and triggered the MIB interrupt, to let us read and clear the counter.
122 * Is called in interrupt context!
124 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah)
126 struct ath5k_statistics *stats = &ah->ah_sc->stats;
129 stats->ack_fail += ath5k_hw_reg_read(ah, AR5K_ACK_FAIL);
130 stats->rts_fail += ath5k_hw_reg_read(ah, AR5K_RTS_FAIL);
131 stats->rts_ok += ath5k_hw_reg_read(ah, AR5K_RTS_OK);
132 stats->fcs_error += ath5k_hw_reg_read(ah, AR5K_FCS_FAIL);
133 stats->beacons += ath5k_hw_reg_read(ah, AR5K_BEACON_CNT);
137 * ath5k_hw_set_ack_bitrate - set bitrate for ACKs
139 * @ah: The &struct ath5k_hw
140 * @high: Flag to determine if we want to use high transmission rate
143 * If high flag is set, we tell hw to use a set of control rates based on
144 * the current transmission rate (check out control_rates array inside reset.c).
145 * If not hw just uses the lowest rate available for the current modulation
146 * scheme being used (1Mbit for CCK and 6Mbits for OFDM).
148 void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, bool high)
150 if (ah->ah_version != AR5K_AR5212)
153 u32 val = AR5K_STA_ID1_BASE_RATE_11B | AR5K_STA_ID1_ACKCTS_6MB;
155 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, val);
157 AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, val);
167 * ath5k_hw_set_ack_timeout - Set ACK timeout on PCU
169 * @ah: The &struct ath5k_hw
170 * @timeout: Timeout in usec
172 static int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout)
174 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_ACK))
178 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_ACK,
179 ath5k_hw_htoclock(ah, timeout));
185 * ath5k_hw_set_cts_timeout - Set CTS timeout on PCU
187 * @ah: The &struct ath5k_hw
188 * @timeout: Timeout in usec
190 static int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout)
192 if (ath5k_hw_clocktoh(ah, AR5K_REG_MS(0xffffffff, AR5K_TIME_OUT_CTS))
196 AR5K_REG_WRITE_BITS(ah, AR5K_TIME_OUT, AR5K_TIME_OUT_CTS,
197 ath5k_hw_htoclock(ah, timeout));
203 * ath5k_hw_htoclock - Translate usec to hw clock units
205 * @ah: The &struct ath5k_hw
206 * @usec: value in microseconds
208 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec)
210 return usec * ath5k_hw_get_clockrate(ah);
214 * ath5k_hw_clocktoh - Translate hw clock units to usec
215 * @clock: value in hw clock units
217 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock)
219 return clock / ath5k_hw_get_clockrate(ah);
223 * ath5k_hw_get_clockrate - Get the clock rate for current mode
225 * @ah: The &struct ath5k_hw
227 unsigned int ath5k_hw_get_clockrate(struct ath5k_hw *ah)
229 struct ieee80211_channel *channel = ah->ah_current_channel;
232 if (channel->hw_value & CHANNEL_5GHZ)
233 clock = 40; /* 802.11a */
234 else if (channel->hw_value & CHANNEL_CCK)
235 clock = 22; /* 802.11b */
237 clock = 44; /* 802.11g */
239 /* Clock rate in turbo modes is twice the normal rate */
240 if (channel->hw_value & CHANNEL_TURBO)
247 * ath5k_hw_get_default_slottime - Get the default slot time for current mode
249 * @ah: The &struct ath5k_hw
251 static unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah)
253 struct ieee80211_channel *channel = ah->ah_current_channel;
255 if (channel->hw_value & CHANNEL_TURBO)
256 return 6; /* both turbo modes */
258 if (channel->hw_value & CHANNEL_CCK)
259 return 20; /* 802.11b */
261 return 9; /* 802.11 a/g */
265 * ath5k_hw_get_default_sifs - Get the default SIFS for current mode
267 * @ah: The &struct ath5k_hw
269 static unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah)
271 struct ieee80211_channel *channel = ah->ah_current_channel;
273 if (channel->hw_value & CHANNEL_TURBO)
274 return 8; /* both turbo modes */
276 if (channel->hw_value & CHANNEL_5GHZ)
277 return 16; /* 802.11a */
279 return 10; /* 802.11 b/g */
283 * ath5k_hw_set_lladdr - Set station id
285 * @ah: The &struct ath5k_hw
286 * @mac: The card's mac address
288 * Set station id on hw using the provided mac address
290 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac)
292 struct ath_common *common = ath5k_hw_common(ah);
296 /* Set new station ID */
297 memcpy(common->macaddr, mac, ETH_ALEN);
299 pcu_reg = ath5k_hw_reg_read(ah, AR5K_STA_ID1) & 0xffff0000;
301 low_id = get_unaligned_le32(mac);
302 high_id = get_unaligned_le16(mac + 4);
304 ath5k_hw_reg_write(ah, low_id, AR5K_STA_ID0);
305 ath5k_hw_reg_write(ah, pcu_reg | high_id, AR5K_STA_ID1);
311 * ath5k_hw_set_bssid - Set current BSSID on hw
313 * @ah: The &struct ath5k_hw
315 * Sets the current BSSID and BSSID mask we have from the
316 * common struct into the hardware
318 void ath5k_hw_set_bssid(struct ath5k_hw *ah)
320 struct ath_common *common = ath5k_hw_common(ah);
324 * Set BSSID mask on 5212
326 if (ah->ah_version == AR5K_AR5212)
327 ath_hw_setbssidmask(common);
332 ath5k_hw_reg_write(ah,
333 get_unaligned_le32(common->curbssid),
335 ath5k_hw_reg_write(ah,
336 get_unaligned_le16(common->curbssid + 4) |
337 ((common->curaid & 0x3fff) << AR5K_BSS_ID1_AID_S),
340 if (common->curaid == 0) {
341 ath5k_hw_disable_pspoll(ah);
345 AR5K_REG_WRITE_BITS(ah, AR5K_BEACON, AR5K_BEACON_TIM,
346 tim_offset ? tim_offset + 4 : 0);
348 ath5k_hw_enable_pspoll(ah, NULL, 0);
351 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask)
353 struct ath_common *common = ath5k_hw_common(ah);
355 /* Cache bssid mask so that we can restore it
357 memcpy(common->bssidmask, mask, ETH_ALEN);
358 if (ah->ah_version == AR5K_AR5212)
359 ath_hw_setbssidmask(common);
367 * ath5k_hw_start_rx_pcu - Start RX engine
369 * @ah: The &struct ath5k_hw
371 * Starts RX engine on PCU so that hw can process RXed frames
374 * NOTE: RX DMA should be already enabled using ath5k_hw_start_rx_dma
376 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah)
378 AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
382 * at5k_hw_stop_rx_pcu - Stop RX engine
384 * @ah: The &struct ath5k_hw
386 * Stops RX engine on PCU
388 * TODO: Detach ANI here
390 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah)
392 AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW, AR5K_DIAG_SW_DIS_RX);
396 * Set multicast filter
398 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1)
400 ath5k_hw_reg_write(ah, filter0, AR5K_MCAST_FILTER0);
401 ath5k_hw_reg_write(ah, filter1, AR5K_MCAST_FILTER1);
405 * ath5k_hw_get_rx_filter - Get current rx filter
407 * @ah: The &struct ath5k_hw
409 * Returns the RX filter by reading rx filter and
410 * phy error filter registers. RX filter is used
411 * to set the allowed frame types that PCU will accept
412 * and pass to the driver. For a list of frame types
415 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah)
417 u32 data, filter = 0;
419 filter = ath5k_hw_reg_read(ah, AR5K_RX_FILTER);
421 /*Radar detection for 5212*/
422 if (ah->ah_version == AR5K_AR5212) {
423 data = ath5k_hw_reg_read(ah, AR5K_PHY_ERR_FIL);
425 if (data & AR5K_PHY_ERR_FIL_RADAR)
426 filter |= AR5K_RX_FILTER_RADARERR;
427 if (data & (AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK))
428 filter |= AR5K_RX_FILTER_PHYERR;
435 * ath5k_hw_set_rx_filter - Set rx filter
437 * @ah: The &struct ath5k_hw
438 * @filter: RX filter mask (see reg.h)
440 * Sets RX filter register and also handles PHY error filter
441 * register on 5212 and newer chips so that we have proper PHY
444 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter)
448 /* Set PHY error filter register on 5212*/
449 if (ah->ah_version == AR5K_AR5212) {
450 if (filter & AR5K_RX_FILTER_RADARERR)
451 data |= AR5K_PHY_ERR_FIL_RADAR;
452 if (filter & AR5K_RX_FILTER_PHYERR)
453 data |= AR5K_PHY_ERR_FIL_OFDM | AR5K_PHY_ERR_FIL_CCK;
457 * The AR5210 uses promiscous mode to detect radar activity
459 if (ah->ah_version == AR5K_AR5210 &&
460 (filter & AR5K_RX_FILTER_RADARERR)) {
461 filter &= ~AR5K_RX_FILTER_RADARERR;
462 filter |= AR5K_RX_FILTER_PROM;
465 /*Zero length DMA (phy error reporting) */
467 AR5K_REG_ENABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
469 AR5K_REG_DISABLE_BITS(ah, AR5K_RXCFG, AR5K_RXCFG_ZLFDMA);
471 /*Write RX Filter register*/
472 ath5k_hw_reg_write(ah, filter & 0xff, AR5K_RX_FILTER);
474 /*Write PHY error filter register on 5212*/
475 if (ah->ah_version == AR5K_AR5212)
476 ath5k_hw_reg_write(ah, data, AR5K_PHY_ERR_FIL);
485 #define ATH5K_MAX_TSF_READ 10
488 * ath5k_hw_get_tsf64 - Get the full 64bit TSF
490 * @ah: The &struct ath5k_hw
492 * Returns the current TSF
494 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah)
496 u32 tsf_lower, tsf_upper1, tsf_upper2;
500 /* This code is time critical - we don't want to be interrupted here */
501 local_irq_save(flags);
504 * While reading TSF upper and then lower part, the clock is still
505 * counting (or jumping in case of IBSS merge) so we might get
506 * inconsistent values. To avoid this, we read the upper part again
507 * and check it has not been changed. We make the hypothesis that a
508 * maximum of 3 changes can happens in a row (we use 10 as a safe
511 * Impact on performance is pretty small, since in most cases, only
512 * 3 register reads are needed.
515 tsf_upper1 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
516 for (i = 0; i < ATH5K_MAX_TSF_READ; i++) {
517 tsf_lower = ath5k_hw_reg_read(ah, AR5K_TSF_L32);
518 tsf_upper2 = ath5k_hw_reg_read(ah, AR5K_TSF_U32);
519 if (tsf_upper2 == tsf_upper1)
521 tsf_upper1 = tsf_upper2;
524 local_irq_restore(flags);
526 WARN_ON( i == ATH5K_MAX_TSF_READ );
528 return (((u64)tsf_upper1 << 32) | tsf_lower);
532 * ath5k_hw_set_tsf64 - Set a new 64bit TSF
534 * @ah: The &struct ath5k_hw
535 * @tsf64: The new 64bit TSF
539 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64)
541 ath5k_hw_reg_write(ah, tsf64 & 0xffffffff, AR5K_TSF_L32);
542 ath5k_hw_reg_write(ah, (tsf64 >> 32) & 0xffffffff, AR5K_TSF_U32);
546 * ath5k_hw_reset_tsf - Force a TSF reset
548 * @ah: The &struct ath5k_hw
550 * Forces a TSF reset on PCU
552 void ath5k_hw_reset_tsf(struct ath5k_hw *ah)
556 val = ath5k_hw_reg_read(ah, AR5K_BEACON) | AR5K_BEACON_RESET_TSF;
559 * Each write to the RESET_TSF bit toggles a hardware internal
560 * signal to reset TSF, but if left high it will cause a TSF reset
561 * on the next chip reset as well. Thus we always write the value
562 * twice to clear the signal.
564 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
565 ath5k_hw_reg_write(ah, val, AR5K_BEACON);
569 * Initialize beacon timers
571 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval)
573 u32 timer1, timer2, timer3;
576 * Set the additional timers by mode
578 switch (ah->ah_sc->opmode) {
579 case NL80211_IFTYPE_MONITOR:
580 case NL80211_IFTYPE_STATION:
581 /* In STA mode timer1 is used as next wakeup
582 * timer and timer2 as next CFP duration start
583 * timer. Both in 1/8TUs. */
584 /* TODO: PCF handling */
585 if (ah->ah_version == AR5K_AR5210) {
592 /* Mark associated AP as PCF incapable for now */
593 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PCF);
595 case NL80211_IFTYPE_ADHOC:
596 AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG, AR5K_TXCFG_ADHOC_BCN_ATIM);
598 /* On non-STA modes timer1 is used as next DMA
599 * beacon alert (DBA) timer and timer2 as next
600 * software beacon alert. Both in 1/8TUs. */
601 timer1 = (next_beacon - AR5K_TUNE_DMA_BEACON_RESP) << 3;
602 timer2 = (next_beacon - AR5K_TUNE_SW_BEACON_RESP) << 3;
606 /* Timer3 marks the end of our ATIM window
607 * a zero length window is not allowed because
608 * we 'll get no beacons */
609 timer3 = next_beacon + 1;
612 * Set the beacon register and enable all timers.
614 /* When in AP or Mesh Point mode zero timer0 to start TSF */
615 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP ||
616 ah->ah_sc->opmode == NL80211_IFTYPE_MESH_POINT)
617 ath5k_hw_reg_write(ah, 0, AR5K_TIMER0);
619 ath5k_hw_reg_write(ah, next_beacon, AR5K_TIMER0);
620 ath5k_hw_reg_write(ah, timer1, AR5K_TIMER1);
621 ath5k_hw_reg_write(ah, timer2, AR5K_TIMER2);
622 ath5k_hw_reg_write(ah, timer3, AR5K_TIMER3);
624 /* Force a TSF reset if requested and enable beacons */
625 if (interval & AR5K_BEACON_RESET_TSF)
626 ath5k_hw_reset_tsf(ah);
628 ath5k_hw_reg_write(ah, interval & (AR5K_BEACON_PERIOD |
632 /* Flush any pending BMISS interrupts on ISR by
633 * performing a clear-on-write operation on PISR
634 * register for the BMISS bit (writing a bit on
635 * ISR togles a reset for that bit and leaves
636 * the rest bits intact) */
637 if (ah->ah_version == AR5K_AR5210)
638 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_ISR);
640 ath5k_hw_reg_write(ah, AR5K_ISR_BMISS, AR5K_PISR);
642 /* TODO: Set enchanced sleep registers on AR5212
643 * based on vif->bss_conf params, until then
644 * disable power save reporting.*/
645 AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_PWR_SV);
650 * ath5k_check_timer_win - Check if timer B is timer A + window
652 * @a: timer a (before b)
653 * @b: timer b (after a)
654 * @window: difference between a and b
655 * @intval: timers are increased by this interval
657 * This helper function checks if timer B is timer A + window and covers
658 * cases where timer A or B might have already been updated or wrapped
659 * around (Timers are 16 bit).
661 * Returns true if O.K.
664 ath5k_check_timer_win(int a, int b, int window, int intval)
667 * 1.) usually B should be A + window
668 * 2.) A already updated, B not updated yet
669 * 3.) A already updated and has wrapped around
670 * 4.) B has wrapped around
672 if ((b - a == window) || /* 1.) */
673 (a - b == intval - window) || /* 2.) */
674 ((a | 0x10000) - b == intval - window) || /* 3.) */
675 ((b | 0x10000) - a == window)) /* 4.) */
676 return true; /* O.K. */
681 * ath5k_hw_check_beacon_timers - Check if the beacon timers are correct
683 * @ah: The &struct ath5k_hw
684 * @intval: beacon interval
686 * This is a workaround for IBSS mode:
688 * The need for this function arises from the fact that we have 4 separate
689 * HW timer registers (TIMER0 - TIMER3), which are closely related to the
690 * next beacon target time (NBTT), and that the HW updates these timers
691 * seperately based on the current TSF value. The hardware increments each
692 * timer by the beacon interval, when the local TSF coverted to TU is equal
693 * to the value stored in the timer.
695 * The reception of a beacon with the same BSSID can update the local HW TSF
696 * at any time - this is something we can't avoid. If the TSF jumps to a
697 * time which is later than the time stored in a timer, this timer will not
698 * be updated until the TSF in TU wraps around at 16 bit (the size of the
699 * timers) and reaches the time which is stored in the timer.
701 * The problem is that these timers are closely related to TIMER0 (NBTT) and
702 * that they define a time "window". When the TSF jumps between two timers
703 * (e.g. ATIM and NBTT), the one in the past will be left behind (not
704 * updated), while the one in the future will be updated every beacon
705 * interval. This causes the window to get larger, until the TSF wraps
706 * around as described above and the timer which was left behind gets
707 * updated again. But - because the beacon interval is usually not an exact
708 * divisor of the size of the timers (16 bit), an unwanted "window" between
709 * these timers has developed!
711 * This is especially important with the ATIM window, because during
712 * the ATIM window only ATIM frames and no data frames are allowed to be
713 * sent, which creates transmission pauses after each beacon. This symptom
714 * has been described as "ramping ping" because ping times increase linearly
715 * for some time and then drop down again. A wrong window on the DMA beacon
716 * timer has the same effect, so we check for these two conditions.
718 * Returns true if O.K.
721 ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval)
723 unsigned int nbtt, atim, dma;
725 nbtt = ath5k_hw_reg_read(ah, AR5K_TIMER0);
726 atim = ath5k_hw_reg_read(ah, AR5K_TIMER3);
727 dma = ath5k_hw_reg_read(ah, AR5K_TIMER1) >> 3;
729 /* NOTE: SWBA is different. Having a wrong window there does not
730 * stop us from sending data and this condition is catched thru
731 * other means (SWBA interrupt) */
733 if (ath5k_check_timer_win(nbtt, atim, 1, intval) &&
734 ath5k_check_timer_win(dma, nbtt, AR5K_TUNE_DMA_BEACON_RESP,
736 return true; /* O.K. */
741 * ath5k_hw_set_coverage_class - Set IEEE 802.11 coverage class
743 * @ah: The &struct ath5k_hw
744 * @coverage_class: IEEE 802.11 coverage class number
746 * Sets slot time, ACK timeout and CTS timeout for given coverage class.
748 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class)
750 /* As defined by IEEE 802.11-2007 17.3.8.6 */
751 int slot_time = ath5k_hw_get_default_slottime(ah) + 3 * coverage_class;
752 int ack_timeout = ath5k_hw_get_default_sifs(ah) + slot_time;
753 int cts_timeout = ack_timeout;
755 ath5k_hw_set_slot_time(ah, slot_time);
756 ath5k_hw_set_ack_timeout(ah, ack_timeout);
757 ath5k_hw_set_cts_timeout(ah, cts_timeout);
759 ah->ah_coverage_class = coverage_class;