2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
3 * Copyright (c) 2004-2005 Atheros Communications, Inc.
4 * Copyright (c) 2006 Devicescape Software, Inc.
5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer,
15 * without modification.
16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
18 * redistribution must be conditioned upon including a substantially
19 * similar Disclaimer requirement for further binary redistribution.
20 * 3. Neither the names of the above-listed copyright holders nor the names
21 * of any contributors may be used to endorse or promote products derived
22 * from this software without specific prior written permission.
24 * Alternatively, this software may be distributed under the terms of the
25 * GNU General Public License ("GPL") version 2 as published by the Free
26 * Software Foundation.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
39 * THE POSSIBILITY OF SUCH DAMAGES.
43 #include <linux/module.h>
44 #include <linux/delay.h>
45 #include <linux/hardirq.h>
48 #include <linux/netdevice.h>
49 #include <linux/cache.h>
50 #include <linux/pci.h>
51 #include <linux/ethtool.h>
52 #include <linux/uaccess.h>
54 #include <net/ieee80211_radiotap.h>
56 #include <asm/unaligned.h>
62 static u8 ath5k_calinterval = 10; /* Calibrate PHY every 10 secs (TODO: Fixme) */
63 static int modparam_nohwcrypt;
64 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
65 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
67 static int modparam_all_channels;
68 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO);
69 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use.");
77 MODULE_AUTHOR("Jiri Slaby");
78 MODULE_AUTHOR("Nick Kossifidis");
79 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards.");
80 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards");
81 MODULE_LICENSE("Dual BSD/GPL");
82 MODULE_VERSION("0.6.0 (EXPERIMENTAL)");
86 static const struct pci_device_id ath5k_pci_id_table[] = {
87 { PCI_VDEVICE(ATHEROS, 0x0207) }, /* 5210 early */
88 { PCI_VDEVICE(ATHEROS, 0x0007) }, /* 5210 */
89 { PCI_VDEVICE(ATHEROS, 0x0011) }, /* 5311 - this is on AHB bus !*/
90 { PCI_VDEVICE(ATHEROS, 0x0012) }, /* 5211 */
91 { PCI_VDEVICE(ATHEROS, 0x0013) }, /* 5212 */
92 { PCI_VDEVICE(3COM_2, 0x0013) }, /* 3com 5212 */
93 { PCI_VDEVICE(3COM, 0x0013) }, /* 3com 3CRDAG675 5212 */
94 { PCI_VDEVICE(ATHEROS, 0x1014) }, /* IBM minipci 5212 */
95 { PCI_VDEVICE(ATHEROS, 0x0014) }, /* 5212 combatible */
96 { PCI_VDEVICE(ATHEROS, 0x0015) }, /* 5212 combatible */
97 { PCI_VDEVICE(ATHEROS, 0x0016) }, /* 5212 combatible */
98 { PCI_VDEVICE(ATHEROS, 0x0017) }, /* 5212 combatible */
99 { PCI_VDEVICE(ATHEROS, 0x0018) }, /* 5212 combatible */
100 { PCI_VDEVICE(ATHEROS, 0x0019) }, /* 5212 combatible */
101 { PCI_VDEVICE(ATHEROS, 0x001a) }, /* 2413 Griffin-lite */
102 { PCI_VDEVICE(ATHEROS, 0x001b) }, /* 5413 Eagle */
103 { PCI_VDEVICE(ATHEROS, 0x001c) }, /* PCI-E cards */
104 { PCI_VDEVICE(ATHEROS, 0x001d) }, /* 2417 Nala */
107 MODULE_DEVICE_TABLE(pci, ath5k_pci_id_table);
110 static const struct ath5k_srev_name srev_names[] = {
111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 },
112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 },
113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A },
114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B },
115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 },
116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 },
117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 },
118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A },
119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 },
120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 },
121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 },
122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 },
123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 },
124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 },
125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 },
126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 },
127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 },
128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 },
129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN },
130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 },
131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 },
132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A },
133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 },
134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 },
135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A },
136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B },
137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 },
138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A },
139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B },
140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 },
141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 },
142 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 },
143 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 },
144 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 },
145 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 },
146 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN },
149 static const struct ieee80211_rate ath5k_rates[] = {
151 .hw_value = ATH5K_RATE_CODE_1M, },
153 .hw_value = ATH5K_RATE_CODE_2M,
154 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE,
155 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
157 .hw_value = ATH5K_RATE_CODE_5_5M,
158 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE,
159 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
161 .hw_value = ATH5K_RATE_CODE_11M,
162 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE,
163 .flags = IEEE80211_RATE_SHORT_PREAMBLE },
165 .hw_value = ATH5K_RATE_CODE_6M,
168 .hw_value = ATH5K_RATE_CODE_9M,
171 .hw_value = ATH5K_RATE_CODE_12M,
174 .hw_value = ATH5K_RATE_CODE_18M,
177 .hw_value = ATH5K_RATE_CODE_24M,
180 .hw_value = ATH5K_RATE_CODE_36M,
183 .hw_value = ATH5K_RATE_CODE_48M,
186 .hw_value = ATH5K_RATE_CODE_54M,
192 * Prototypes - PCI stack related functions
194 static int __devinit ath5k_pci_probe(struct pci_dev *pdev,
195 const struct pci_device_id *id);
196 static void __devexit ath5k_pci_remove(struct pci_dev *pdev);
198 static int ath5k_pci_suspend(struct device *dev);
199 static int ath5k_pci_resume(struct device *dev);
201 SIMPLE_DEV_PM_OPS(ath5k_pm_ops, ath5k_pci_suspend, ath5k_pci_resume);
202 #define ATH5K_PM_OPS (&ath5k_pm_ops)
204 #define ATH5K_PM_OPS NULL
205 #endif /* CONFIG_PM */
207 static struct pci_driver ath5k_pci_driver = {
208 .name = KBUILD_MODNAME,
209 .id_table = ath5k_pci_id_table,
210 .probe = ath5k_pci_probe,
211 .remove = __devexit_p(ath5k_pci_remove),
212 .driver.pm = ATH5K_PM_OPS,
218 * Prototypes - MAC 802.11 stack related functions
220 static int ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb);
221 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
222 struct ath5k_txq *txq);
223 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan);
224 static int ath5k_reset_wake(struct ath5k_softc *sc);
225 static int ath5k_start(struct ieee80211_hw *hw);
226 static void ath5k_stop(struct ieee80211_hw *hw);
227 static int ath5k_add_interface(struct ieee80211_hw *hw,
228 struct ieee80211_if_init_conf *conf);
229 static void ath5k_remove_interface(struct ieee80211_hw *hw,
230 struct ieee80211_if_init_conf *conf);
231 static int ath5k_config(struct ieee80211_hw *hw, u32 changed);
232 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
233 int mc_count, struct dev_addr_list *mc_list);
234 static void ath5k_configure_filter(struct ieee80211_hw *hw,
235 unsigned int changed_flags,
236 unsigned int *new_flags,
238 static int ath5k_set_key(struct ieee80211_hw *hw,
239 enum set_key_cmd cmd,
240 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
241 struct ieee80211_key_conf *key);
242 static int ath5k_get_stats(struct ieee80211_hw *hw,
243 struct ieee80211_low_level_stats *stats);
244 static int ath5k_get_tx_stats(struct ieee80211_hw *hw,
245 struct ieee80211_tx_queue_stats *stats);
246 static u64 ath5k_get_tsf(struct ieee80211_hw *hw);
247 static void ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf);
248 static void ath5k_reset_tsf(struct ieee80211_hw *hw);
249 static int ath5k_beacon_update(struct ieee80211_hw *hw,
250 struct ieee80211_vif *vif);
251 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
252 struct ieee80211_vif *vif,
253 struct ieee80211_bss_conf *bss_conf,
255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw);
256 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw);
258 static const struct ieee80211_ops ath5k_hw_ops = {
260 .start = ath5k_start,
262 .add_interface = ath5k_add_interface,
263 .remove_interface = ath5k_remove_interface,
264 .config = ath5k_config,
265 .prepare_multicast = ath5k_prepare_multicast,
266 .configure_filter = ath5k_configure_filter,
267 .set_key = ath5k_set_key,
268 .get_stats = ath5k_get_stats,
270 .get_tx_stats = ath5k_get_tx_stats,
271 .get_tsf = ath5k_get_tsf,
272 .set_tsf = ath5k_set_tsf,
273 .reset_tsf = ath5k_reset_tsf,
274 .bss_info_changed = ath5k_bss_info_changed,
275 .sw_scan_start = ath5k_sw_scan_start,
276 .sw_scan_complete = ath5k_sw_scan_complete,
280 * Prototypes - Internal functions
283 static int ath5k_attach(struct pci_dev *pdev,
284 struct ieee80211_hw *hw);
285 static void ath5k_detach(struct pci_dev *pdev,
286 struct ieee80211_hw *hw);
287 /* Channel/mode setup */
288 static inline short ath5k_ieee2mhz(short chan);
289 static unsigned int ath5k_copy_channels(struct ath5k_hw *ah,
290 struct ieee80211_channel *channels,
293 static int ath5k_setup_bands(struct ieee80211_hw *hw);
294 static int ath5k_chan_set(struct ath5k_softc *sc,
295 struct ieee80211_channel *chan);
296 static void ath5k_setcurmode(struct ath5k_softc *sc,
298 static void ath5k_mode_setup(struct ath5k_softc *sc);
300 /* Descriptor setup */
301 static int ath5k_desc_alloc(struct ath5k_softc *sc,
302 struct pci_dev *pdev);
303 static void ath5k_desc_free(struct ath5k_softc *sc,
304 struct pci_dev *pdev);
306 static int ath5k_rxbuf_setup(struct ath5k_softc *sc,
307 struct ath5k_buf *bf);
308 static int ath5k_txbuf_setup(struct ath5k_softc *sc,
309 struct ath5k_buf *bf,
310 struct ath5k_txq *txq);
311 static inline void ath5k_txbuf_free(struct ath5k_softc *sc,
312 struct ath5k_buf *bf)
317 pci_unmap_single(sc->pdev, bf->skbaddr, bf->skb->len,
319 dev_kfree_skb_any(bf->skb);
323 static inline void ath5k_rxbuf_free(struct ath5k_softc *sc,
324 struct ath5k_buf *bf)
329 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
331 dev_kfree_skb_any(bf->skb);
337 static struct ath5k_txq *ath5k_txq_setup(struct ath5k_softc *sc,
338 int qtype, int subtype);
339 static int ath5k_beaconq_setup(struct ath5k_hw *ah);
340 static int ath5k_beaconq_config(struct ath5k_softc *sc);
341 static void ath5k_txq_drainq(struct ath5k_softc *sc,
342 struct ath5k_txq *txq);
343 static void ath5k_txq_cleanup(struct ath5k_softc *sc);
344 static void ath5k_txq_release(struct ath5k_softc *sc);
346 static int ath5k_rx_start(struct ath5k_softc *sc);
347 static void ath5k_rx_stop(struct ath5k_softc *sc);
348 static unsigned int ath5k_rx_decrypted(struct ath5k_softc *sc,
349 struct ath5k_desc *ds,
351 struct ath5k_rx_status *rs);
352 static void ath5k_tasklet_rx(unsigned long data);
354 static void ath5k_tx_processq(struct ath5k_softc *sc,
355 struct ath5k_txq *txq);
356 static void ath5k_tasklet_tx(unsigned long data);
357 /* Beacon handling */
358 static int ath5k_beacon_setup(struct ath5k_softc *sc,
359 struct ath5k_buf *bf);
360 static void ath5k_beacon_send(struct ath5k_softc *sc);
361 static void ath5k_beacon_config(struct ath5k_softc *sc);
362 static void ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf);
363 static void ath5k_tasklet_beacon(unsigned long data);
365 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp)
367 u64 tsf = ath5k_hw_get_tsf64(ah);
369 if ((tsf & 0x7fff) < rstamp)
372 return (tsf & ~0x7fff) | rstamp;
375 /* Interrupt handling */
376 static int ath5k_init(struct ath5k_softc *sc);
377 static int ath5k_stop_locked(struct ath5k_softc *sc);
378 static int ath5k_stop_hw(struct ath5k_softc *sc);
379 static irqreturn_t ath5k_intr(int irq, void *dev_id);
380 static void ath5k_tasklet_reset(unsigned long data);
382 static void ath5k_tasklet_calibrate(unsigned long data);
385 * Module init/exit functions
394 ret = pci_register_driver(&ath5k_pci_driver);
396 printk(KERN_ERR "ath5k_pci: can't register pci driver\n");
406 pci_unregister_driver(&ath5k_pci_driver);
408 ath5k_debug_finish();
411 module_init(init_ath5k_pci);
412 module_exit(exit_ath5k_pci);
415 /********************\
416 * PCI Initialization *
417 \********************/
420 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val)
422 const char *name = "xxxxx";
425 for (i = 0; i < ARRAY_SIZE(srev_names); i++) {
426 if (srev_names[i].sr_type != type)
429 if ((val & 0xf0) == srev_names[i].sr_val)
430 name = srev_names[i].sr_name;
432 if ((val & 0xff) == srev_names[i].sr_val) {
433 name = srev_names[i].sr_name;
440 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset)
442 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
443 return ath5k_hw_reg_read(ah, reg_offset);
446 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
448 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv;
449 ath5k_hw_reg_write(ah, val, reg_offset);
452 static const struct ath_ops ath5k_common_ops = {
453 .read = ath5k_ioread32,
454 .write = ath5k_iowrite32,
458 ath5k_pci_probe(struct pci_dev *pdev,
459 const struct pci_device_id *id)
462 struct ath5k_softc *sc;
463 struct ath_common *common;
464 struct ieee80211_hw *hw;
468 ret = pci_enable_device(pdev);
470 dev_err(&pdev->dev, "can't enable device\n");
474 /* XXX 32-bit addressing only */
475 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
477 dev_err(&pdev->dev, "32-bit DMA not available\n");
482 * Cache line size is used to size and align various
483 * structures used to communicate with the hardware.
485 pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &csz);
488 * Linux 2.4.18 (at least) writes the cache line size
489 * register as a 16-bit wide register which is wrong.
490 * We must have this setup properly for rx buffer
491 * DMA to work so force a reasonable value here if it
494 csz = L1_CACHE_BYTES >> 2;
495 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, csz);
498 * The default setting of latency timer yields poor results,
499 * set it to the value used by other systems. It may be worth
500 * tweaking this setting more.
502 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0xa8);
504 /* Enable bus mastering */
505 pci_set_master(pdev);
508 * Disable the RETRY_TIMEOUT register (0x41) to keep
509 * PCI Tx retries from interfering with C3 CPU state.
511 pci_write_config_byte(pdev, 0x41, 0);
513 ret = pci_request_region(pdev, 0, "ath5k");
515 dev_err(&pdev->dev, "cannot reserve PCI memory region\n");
519 mem = pci_iomap(pdev, 0, 0);
521 dev_err(&pdev->dev, "cannot remap PCI memory region\n") ;
527 * Allocate hw (mac80211 main struct)
528 * and hw->priv (driver private data)
530 hw = ieee80211_alloc_hw(sizeof(*sc), &ath5k_hw_ops);
532 dev_err(&pdev->dev, "cannot allocate ieee80211_hw\n");
537 dev_info(&pdev->dev, "registered as '%s'\n", wiphy_name(hw->wiphy));
539 /* Initialize driver private data */
540 SET_IEEE80211_DEV(hw, &pdev->dev);
541 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS |
542 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
543 IEEE80211_HW_SIGNAL_DBM |
544 IEEE80211_HW_NOISE_DBM;
546 hw->wiphy->interface_modes =
547 BIT(NL80211_IFTYPE_AP) |
548 BIT(NL80211_IFTYPE_STATION) |
549 BIT(NL80211_IFTYPE_ADHOC) |
550 BIT(NL80211_IFTYPE_MESH_POINT);
552 hw->extra_tx_headroom = 2;
553 hw->channel_change_time = 5000;
558 ath5k_debug_init_device(sc);
561 * Mark the device as detached to avoid processing
562 * interrupts until setup is complete.
564 __set_bit(ATH_STAT_INVALID, sc->status);
566 sc->iobase = mem; /* So we can unmap it on detach */
567 sc->opmode = NL80211_IFTYPE_STATION;
569 mutex_init(&sc->lock);
570 spin_lock_init(&sc->rxbuflock);
571 spin_lock_init(&sc->txbuflock);
572 spin_lock_init(&sc->block);
574 /* Set private data */
575 pci_set_drvdata(pdev, hw);
577 /* Setup interrupt handler */
578 ret = request_irq(pdev->irq, ath5k_intr, IRQF_SHARED, "ath", sc);
580 ATH5K_ERR(sc, "request_irq failed\n");
584 /*If we passed the test malloc a ath5k_hw struct*/
585 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL);
588 ATH5K_ERR(sc, "out of memory\n");
593 sc->ah->ah_iobase = sc->iobase;
594 common = ath5k_hw_common(sc->ah);
595 common->ops = &ath5k_common_ops;
598 common->cachelsz = csz << 2; /* convert to bytes */
600 /* Initialize device */
601 ret = ath5k_hw_attach(sc);
606 /* set up multi-rate retry capabilities */
607 if (sc->ah->ah_version == AR5K_AR5212) {
609 hw->max_rate_tries = 11;
612 /* Finish private driver data initialization */
613 ret = ath5k_attach(pdev, hw);
617 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n",
618 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev),
620 sc->ah->ah_phy_revision);
622 if (!sc->ah->ah_single_chip) {
623 /* Single chip radio (!RF5111) */
624 if (sc->ah->ah_radio_5ghz_revision &&
625 !sc->ah->ah_radio_2ghz_revision) {
626 /* No 5GHz support -> report 2GHz radio */
627 if (!test_bit(AR5K_MODE_11A,
628 sc->ah->ah_capabilities.cap_mode)) {
629 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
630 ath5k_chip_name(AR5K_VERSION_RAD,
631 sc->ah->ah_radio_5ghz_revision),
632 sc->ah->ah_radio_5ghz_revision);
633 /* No 2GHz support (5110 and some
634 * 5Ghz only cards) -> report 5Ghz radio */
635 } else if (!test_bit(AR5K_MODE_11B,
636 sc->ah->ah_capabilities.cap_mode)) {
637 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
638 ath5k_chip_name(AR5K_VERSION_RAD,
639 sc->ah->ah_radio_5ghz_revision),
640 sc->ah->ah_radio_5ghz_revision);
641 /* Multiband radio */
643 ATH5K_INFO(sc, "RF%s multiband radio found"
645 ath5k_chip_name(AR5K_VERSION_RAD,
646 sc->ah->ah_radio_5ghz_revision),
647 sc->ah->ah_radio_5ghz_revision);
650 /* Multi chip radio (RF5111 - RF2111) ->
651 * report both 2GHz/5GHz radios */
652 else if (sc->ah->ah_radio_5ghz_revision &&
653 sc->ah->ah_radio_2ghz_revision){
654 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n",
655 ath5k_chip_name(AR5K_VERSION_RAD,
656 sc->ah->ah_radio_5ghz_revision),
657 sc->ah->ah_radio_5ghz_revision);
658 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n",
659 ath5k_chip_name(AR5K_VERSION_RAD,
660 sc->ah->ah_radio_2ghz_revision),
661 sc->ah->ah_radio_2ghz_revision);
666 /* ready to process interrupts */
667 __clear_bit(ATH_STAT_INVALID, sc->status);
671 ath5k_hw_detach(sc->ah);
673 free_irq(pdev->irq, sc);
677 ieee80211_free_hw(hw);
679 pci_iounmap(pdev, mem);
681 pci_release_region(pdev, 0);
683 pci_disable_device(pdev);
688 static void __devexit
689 ath5k_pci_remove(struct pci_dev *pdev)
691 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
692 struct ath5k_softc *sc = hw->priv;
694 ath5k_debug_finish_device(sc);
695 ath5k_detach(pdev, hw);
696 ath5k_hw_detach(sc->ah);
698 free_irq(pdev->irq, sc);
699 pci_iounmap(pdev, sc->iobase);
700 pci_release_region(pdev, 0);
701 pci_disable_device(pdev);
702 ieee80211_free_hw(hw);
706 static int ath5k_pci_suspend(struct device *dev)
708 struct ieee80211_hw *hw = pci_get_drvdata(to_pci_dev(dev));
709 struct ath5k_softc *sc = hw->priv;
715 static int ath5k_pci_resume(struct device *dev)
717 struct pci_dev *pdev = to_pci_dev(dev);
718 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
719 struct ath5k_softc *sc = hw->priv;
722 * Suspend/Resume resets the PCI configuration space, so we have to
723 * re-disable the RETRY_TIMEOUT register (0x41) to keep
724 * PCI Tx retries from interfering with C3 CPU state
726 pci_write_config_byte(pdev, 0x41, 0);
728 ath5k_led_enable(sc);
731 #endif /* CONFIG_PM */
734 /***********************\
735 * Driver Initialization *
736 \***********************/
738 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request)
740 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
741 struct ath5k_softc *sc = hw->priv;
742 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah);
744 return ath_reg_notifier_apply(wiphy, request, regulatory);
748 ath5k_attach(struct pci_dev *pdev, struct ieee80211_hw *hw)
750 struct ath5k_softc *sc = hw->priv;
751 struct ath5k_hw *ah = sc->ah;
752 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
753 u8 mac[ETH_ALEN] = {};
756 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "devid 0x%x\n", pdev->device);
759 * Check if the MAC has multi-rate retry support.
760 * We do this by trying to setup a fake extended
761 * descriptor. MAC's that don't have support will
762 * return false w/o doing anything. MAC's that do
763 * support it will return true w/o doing anything.
765 ret = ah->ah_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0);
769 __set_bit(ATH_STAT_MRRETRY, sc->status);
772 * Collect the channel list. The 802.11 layer
773 * is resposible for filtering this list based
774 * on settings like the phy mode and regulatory
775 * domain restrictions.
777 ret = ath5k_setup_bands(hw);
779 ATH5K_ERR(sc, "can't get channels\n");
783 /* NB: setup here so ath5k_rate_update is happy */
784 if (test_bit(AR5K_MODE_11A, ah->ah_modes))
785 ath5k_setcurmode(sc, AR5K_MODE_11A);
787 ath5k_setcurmode(sc, AR5K_MODE_11B);
790 * Allocate tx+rx descriptors and populate the lists.
792 ret = ath5k_desc_alloc(sc, pdev);
794 ATH5K_ERR(sc, "can't allocate descriptors\n");
799 * Allocate hardware transmit queues: one queue for
800 * beacon frames and one data queue for each QoS
801 * priority. Note that hw functions handle reseting
802 * these queues at the needed time.
804 ret = ath5k_beaconq_setup(ah);
806 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n");
810 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0);
811 if (IS_ERR(sc->cabq)) {
812 ATH5K_ERR(sc, "can't setup cab queue\n");
813 ret = PTR_ERR(sc->cabq);
817 sc->txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK);
818 if (IS_ERR(sc->txq)) {
819 ATH5K_ERR(sc, "can't setup xmit queue\n");
820 ret = PTR_ERR(sc->txq);
824 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc);
825 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc);
826 tasklet_init(&sc->restq, ath5k_tasklet_reset, (unsigned long)sc);
827 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc);
828 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc);
830 ret = ath5k_eeprom_read_mac(ah, mac);
832 ATH5K_ERR(sc, "unable to read address from EEPROM: 0x%04x\n",
837 SET_IEEE80211_PERM_ADDR(hw, mac);
838 /* All MAC address bits matter for ACKs */
839 memcpy(sc->bssidmask, ath_bcast_mac, ETH_ALEN);
840 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask);
842 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain;
843 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier);
845 ATH5K_ERR(sc, "can't initialize regulatory system\n");
849 ret = ieee80211_register_hw(hw);
851 ATH5K_ERR(sc, "can't register ieee80211 hw\n");
855 if (!ath_is_world_regd(regulatory))
856 regulatory_hint(hw->wiphy, regulatory->alpha2);
862 ath5k_txq_release(sc);
864 ath5k_hw_release_tx_queue(ah, sc->bhalq);
866 ath5k_desc_free(sc, pdev);
872 ath5k_detach(struct pci_dev *pdev, struct ieee80211_hw *hw)
874 struct ath5k_softc *sc = hw->priv;
877 * NB: the order of these is important:
878 * o call the 802.11 layer before detaching ath5k_hw to
879 * insure callbacks into the driver to delete global
880 * key cache entries can be handled
881 * o reclaim the tx queue data structures after calling
882 * the 802.11 layer as we'll get called back to reclaim
883 * node state and potentially want to use them
884 * o to cleanup the tx queues the hal is called, so detach
886 * XXX: ??? detach ath5k_hw ???
887 * Other than that, it's straightforward...
889 ieee80211_unregister_hw(hw);
890 ath5k_desc_free(sc, pdev);
891 ath5k_txq_release(sc);
892 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq);
893 ath5k_unregister_leds(sc);
896 * NB: can't reclaim these until after ieee80211_ifdetach
897 * returns because we'll get called back to reclaim node
898 * state and potentially want to use them.
905 /********************\
906 * Channel/mode setup *
907 \********************/
910 * Convert IEEE channel number to MHz frequency.
913 ath5k_ieee2mhz(short chan)
915 if (chan <= 14 || chan >= 27)
916 return ieee80211chan2mhz(chan);
918 return 2212 + chan * 20;
922 * Returns true for the channel numbers used without all_channels modparam.
924 static bool ath5k_is_standard_channel(short chan)
926 return ((chan <= 14) ||
928 ((chan & 3) == 0 && chan >= 36 && chan <= 64) ||
930 ((chan & 3) == 0 && chan >= 100 && chan <= 140) ||
932 ((chan & 3) == 1 && chan >= 149 && chan <= 165));
936 ath5k_copy_channels(struct ath5k_hw *ah,
937 struct ieee80211_channel *channels,
941 unsigned int i, count, size, chfreq, freq, ch;
943 if (!test_bit(mode, ah->ah_modes))
948 case AR5K_MODE_11A_TURBO:
949 /* 1..220, but 2GHz frequencies are filtered by check_channel */
951 chfreq = CHANNEL_5GHZ;
955 case AR5K_MODE_11G_TURBO:
957 chfreq = CHANNEL_2GHZ;
960 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n");
964 for (i = 0, count = 0; i < size && max > 0; i++) {
966 freq = ath5k_ieee2mhz(ch);
968 /* Check if channel is supported by the chipset */
969 if (!ath5k_channel_ok(ah, freq, chfreq))
972 if (!modparam_all_channels && !ath5k_is_standard_channel(ch))
975 /* Write channel info and increment counter */
976 channels[count].center_freq = freq;
977 channels[count].band = (chfreq == CHANNEL_2GHZ) ?
978 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
982 channels[count].hw_value = chfreq | CHANNEL_OFDM;
984 case AR5K_MODE_11A_TURBO:
985 case AR5K_MODE_11G_TURBO:
986 channels[count].hw_value = chfreq |
987 CHANNEL_OFDM | CHANNEL_TURBO;
990 channels[count].hw_value = CHANNEL_B;
1001 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b)
1005 for (i = 0; i < AR5K_MAX_RATES; i++)
1006 sc->rate_idx[b->band][i] = -1;
1008 for (i = 0; i < b->n_bitrates; i++) {
1009 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i;
1010 if (b->bitrates[i].hw_value_short)
1011 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i;
1016 ath5k_setup_bands(struct ieee80211_hw *hw)
1018 struct ath5k_softc *sc = hw->priv;
1019 struct ath5k_hw *ah = sc->ah;
1020 struct ieee80211_supported_band *sband;
1021 int max_c, count_c = 0;
1024 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS);
1025 max_c = ARRAY_SIZE(sc->channels);
1028 sband = &sc->sbands[IEEE80211_BAND_2GHZ];
1029 sband->band = IEEE80211_BAND_2GHZ;
1030 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0];
1032 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) {
1034 memcpy(sband->bitrates, &ath5k_rates[0],
1035 sizeof(struct ieee80211_rate) * 12);
1036 sband->n_bitrates = 12;
1038 sband->channels = sc->channels;
1039 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1040 AR5K_MODE_11G, max_c);
1042 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1043 count_c = sband->n_channels;
1045 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) {
1047 memcpy(sband->bitrates, &ath5k_rates[0],
1048 sizeof(struct ieee80211_rate) * 4);
1049 sband->n_bitrates = 4;
1051 /* 5211 only supports B rates and uses 4bit rate codes
1052 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B)
1055 if (ah->ah_version == AR5K_AR5211) {
1056 for (i = 0; i < 4; i++) {
1057 sband->bitrates[i].hw_value =
1058 sband->bitrates[i].hw_value & 0xF;
1059 sband->bitrates[i].hw_value_short =
1060 sband->bitrates[i].hw_value_short & 0xF;
1064 sband->channels = sc->channels;
1065 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1066 AR5K_MODE_11B, max_c);
1068 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
1069 count_c = sband->n_channels;
1072 ath5k_setup_rate_idx(sc, sband);
1074 /* 5GHz band, A mode */
1075 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) {
1076 sband = &sc->sbands[IEEE80211_BAND_5GHZ];
1077 sband->band = IEEE80211_BAND_5GHZ;
1078 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0];
1080 memcpy(sband->bitrates, &ath5k_rates[4],
1081 sizeof(struct ieee80211_rate) * 8);
1082 sband->n_bitrates = 8;
1084 sband->channels = &sc->channels[count_c];
1085 sband->n_channels = ath5k_copy_channels(ah, sband->channels,
1086 AR5K_MODE_11A, max_c);
1088 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband;
1090 ath5k_setup_rate_idx(sc, sband);
1092 ath5k_debug_dump_bands(sc);
1098 * Set/change channels. We always reset the chip.
1099 * To accomplish this we must first cleanup any pending DMA,
1100 * then restart stuff after a la ath5k_init.
1102 * Called with sc->lock.
1105 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan)
1107 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "(%u MHz) -> (%u MHz)\n",
1108 sc->curchan->center_freq, chan->center_freq);
1111 * To switch channels clear any pending DMA operations;
1112 * wait long enough for the RX fifo to drain, reset the
1113 * hardware at the new frequency, and then re-enable
1114 * the relevant bits of the h/w.
1116 return ath5k_reset(sc, chan);
1120 ath5k_setcurmode(struct ath5k_softc *sc, unsigned int mode)
1124 if (mode == AR5K_MODE_11A) {
1125 sc->curband = &sc->sbands[IEEE80211_BAND_5GHZ];
1127 sc->curband = &sc->sbands[IEEE80211_BAND_2GHZ];
1132 ath5k_mode_setup(struct ath5k_softc *sc)
1134 struct ath5k_hw *ah = sc->ah;
1137 ah->ah_op_mode = sc->opmode;
1139 /* configure rx filter */
1140 rfilt = sc->filter_flags;
1141 ath5k_hw_set_rx_filter(ah, rfilt);
1143 if (ath5k_hw_hasbssidmask(ah))
1144 ath5k_hw_set_bssid_mask(ah, sc->bssidmask);
1146 /* configure operational mode */
1147 ath5k_hw_set_opmode(ah);
1149 ath5k_hw_set_mcast_filter(ah, 0, 0);
1150 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt);
1154 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix)
1158 /* return base rate on errors */
1159 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES,
1160 "hw_rix out of bounds: %x\n", hw_rix))
1163 rix = sc->rate_idx[sc->curband->band][hw_rix];
1164 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix))
1175 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr)
1177 struct ath_common *common = ath5k_hw_common(sc->ah);
1178 struct sk_buff *skb;
1181 * Allocate buffer with headroom_needed space for the
1182 * fake physical layer header at the start.
1184 skb = ath_rxbuf_alloc(common,
1185 sc->rxbufsize + common->cachelsz - 1,
1189 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n",
1190 sc->rxbufsize + common->cachelsz - 1);
1194 *skb_addr = pci_map_single(sc->pdev,
1195 skb->data, sc->rxbufsize, PCI_DMA_FROMDEVICE);
1196 if (unlikely(pci_dma_mapping_error(sc->pdev, *skb_addr))) {
1197 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__);
1205 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
1207 struct ath5k_hw *ah = sc->ah;
1208 struct sk_buff *skb = bf->skb;
1209 struct ath5k_desc *ds;
1212 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr);
1219 * Setup descriptors. For receive we always terminate
1220 * the descriptor list with a self-linked entry so we'll
1221 * not get overrun under high load (as can happen with a
1222 * 5212 when ANI processing enables PHY error frames).
1224 * To insure the last descriptor is self-linked we create
1225 * each descriptor as self-linked and add it to the end. As
1226 * each additional descriptor is added the previous self-linked
1227 * entry is ``fixed'' naturally. This should be safe even
1228 * if DMA is happening. When processing RX interrupts we
1229 * never remove/process the last, self-linked, entry on the
1230 * descriptor list. This insures the hardware always has
1231 * someplace to write a new frame.
1234 ds->ds_link = bf->daddr; /* link to self */
1235 ds->ds_data = bf->skbaddr;
1236 ah->ah_setup_rx_desc(ah, ds,
1237 skb_tailroom(skb), /* buffer size */
1240 if (sc->rxlink != NULL)
1241 *sc->rxlink = bf->daddr;
1242 sc->rxlink = &ds->ds_link;
1247 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf,
1248 struct ath5k_txq *txq)
1250 struct ath5k_hw *ah = sc->ah;
1251 struct ath5k_desc *ds = bf->desc;
1252 struct sk_buff *skb = bf->skb;
1253 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1254 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID;
1255 struct ieee80211_rate *rate;
1256 unsigned int mrr_rate[3], mrr_tries[3];
1263 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK;
1265 /* XXX endianness */
1266 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
1269 rate = ieee80211_get_tx_rate(sc->hw, info);
1271 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1272 flags |= AR5K_TXDESC_NOACK;
1274 rc_flags = info->control.rates[0].flags;
1275 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ?
1276 rate->hw_value_short : rate->hw_value;
1280 /* FIXME: If we are in g mode and rate is a CCK rate
1281 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
1282 * from tx power (value is in dB units already) */
1283 if (info->control.hw_key) {
1284 keyidx = info->control.hw_key->hw_key_idx;
1285 pktlen += info->control.hw_key->icv_len;
1287 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
1288 flags |= AR5K_TXDESC_RTSENA;
1289 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1290 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw,
1291 sc->vif, pktlen, info));
1293 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
1294 flags |= AR5K_TXDESC_CTSENA;
1295 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value;
1296 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw,
1297 sc->vif, pktlen, info));
1299 ret = ah->ah_setup_tx_desc(ah, ds, pktlen,
1300 ieee80211_get_hdrlen_from_skb(skb), AR5K_PKT_TYPE_NORMAL,
1301 (sc->power_level * 2),
1303 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags,
1304 cts_rate, duration);
1308 memset(mrr_rate, 0, sizeof(mrr_rate));
1309 memset(mrr_tries, 0, sizeof(mrr_tries));
1310 for (i = 0; i < 3; i++) {
1311 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i);
1315 mrr_rate[i] = rate->hw_value;
1316 mrr_tries[i] = info->control.rates[i + 1].count;
1319 ah->ah_setup_mrr_tx_desc(ah, ds,
1320 mrr_rate[0], mrr_tries[0],
1321 mrr_rate[1], mrr_tries[1],
1322 mrr_rate[2], mrr_tries[2]);
1325 ds->ds_data = bf->skbaddr;
1327 spin_lock_bh(&txq->lock);
1328 list_add_tail(&bf->list, &txq->q);
1329 sc->tx_stats[txq->qnum].len++;
1330 if (txq->link == NULL) /* is this first packet? */
1331 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr);
1332 else /* no, so only link it */
1333 *txq->link = bf->daddr;
1335 txq->link = &ds->ds_link;
1336 ath5k_hw_start_tx_dma(ah, txq->qnum);
1338 spin_unlock_bh(&txq->lock);
1342 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
1346 /*******************\
1347 * Descriptors setup *
1348 \*******************/
1351 ath5k_desc_alloc(struct ath5k_softc *sc, struct pci_dev *pdev)
1353 struct ath5k_desc *ds;
1354 struct ath5k_buf *bf;
1359 /* allocate descriptors */
1360 sc->desc_len = sizeof(struct ath5k_desc) *
1361 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1);
1362 sc->desc = pci_alloc_consistent(pdev, sc->desc_len, &sc->desc_daddr);
1363 if (sc->desc == NULL) {
1364 ATH5K_ERR(sc, "can't allocate descriptors\n");
1369 da = sc->desc_daddr;
1370 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n",
1371 ds, sc->desc_len, (unsigned long long)sc->desc_daddr);
1373 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF,
1374 sizeof(struct ath5k_buf), GFP_KERNEL);
1376 ATH5K_ERR(sc, "can't allocate bufptr\n");
1382 INIT_LIST_HEAD(&sc->rxbuf);
1383 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) {
1386 list_add_tail(&bf->list, &sc->rxbuf);
1389 INIT_LIST_HEAD(&sc->txbuf);
1390 sc->txbuf_len = ATH_TXBUF;
1391 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++,
1392 da += sizeof(*ds)) {
1395 list_add_tail(&bf->list, &sc->txbuf);
1405 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1412 ath5k_desc_free(struct ath5k_softc *sc, struct pci_dev *pdev)
1414 struct ath5k_buf *bf;
1416 ath5k_txbuf_free(sc, sc->bbuf);
1417 list_for_each_entry(bf, &sc->txbuf, list)
1418 ath5k_txbuf_free(sc, bf);
1419 list_for_each_entry(bf, &sc->rxbuf, list)
1420 ath5k_rxbuf_free(sc, bf);
1422 /* Free memory associated with all descriptors */
1423 pci_free_consistent(pdev, sc->desc_len, sc->desc, sc->desc_daddr);
1437 static struct ath5k_txq *
1438 ath5k_txq_setup(struct ath5k_softc *sc,
1439 int qtype, int subtype)
1441 struct ath5k_hw *ah = sc->ah;
1442 struct ath5k_txq *txq;
1443 struct ath5k_txq_info qi = {
1444 .tqi_subtype = subtype,
1445 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1446 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1447 .tqi_cw_max = AR5K_TXQ_USEDEFAULT
1452 * Enable interrupts only for EOL and DESC conditions.
1453 * We mark tx descriptors to receive a DESC interrupt
1454 * when a tx queue gets deep; otherwise waiting for the
1455 * EOL to reap descriptors. Note that this is done to
1456 * reduce interrupt load and this only defers reaping
1457 * descriptors, never transmitting frames. Aside from
1458 * reducing interrupts this also permits more concurrency.
1459 * The only potential downside is if the tx queue backs
1460 * up in which case the top half of the kernel may backup
1461 * due to a lack of tx descriptors.
1463 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE |
1464 AR5K_TXQ_FLAG_TXDESCINT_ENABLE;
1465 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi);
1468 * NB: don't print a message, this happens
1469 * normally on parts with too few tx queues
1471 return ERR_PTR(qnum);
1473 if (qnum >= ARRAY_SIZE(sc->txqs)) {
1474 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n",
1475 qnum, ARRAY_SIZE(sc->txqs));
1476 ath5k_hw_release_tx_queue(ah, qnum);
1477 return ERR_PTR(-EINVAL);
1479 txq = &sc->txqs[qnum];
1483 INIT_LIST_HEAD(&txq->q);
1484 spin_lock_init(&txq->lock);
1487 return &sc->txqs[qnum];
1491 ath5k_beaconq_setup(struct ath5k_hw *ah)
1493 struct ath5k_txq_info qi = {
1494 .tqi_aifs = AR5K_TXQ_USEDEFAULT,
1495 .tqi_cw_min = AR5K_TXQ_USEDEFAULT,
1496 .tqi_cw_max = AR5K_TXQ_USEDEFAULT,
1497 /* NB: for dynamic turbo, don't enable any other interrupts */
1498 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE
1501 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi);
1505 ath5k_beaconq_config(struct ath5k_softc *sc)
1507 struct ath5k_hw *ah = sc->ah;
1508 struct ath5k_txq_info qi;
1511 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi);
1514 if (sc->opmode == NL80211_IFTYPE_AP ||
1515 sc->opmode == NL80211_IFTYPE_MESH_POINT) {
1517 * Always burst out beacon and CAB traffic
1518 * (aifs = cwmin = cwmax = 0)
1523 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) {
1525 * Adhoc mode; backoff between 0 and (2 * cw_min).
1529 qi.tqi_cw_max = 2 * ah->ah_cw_min;
1532 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
1533 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n",
1534 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max);
1536 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi);
1538 ATH5K_ERR(sc, "%s: unable to update parameters for beacon "
1539 "hardware queue!\n", __func__);
1543 return ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */;
1547 ath5k_txq_drainq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1549 struct ath5k_buf *bf, *bf0;
1552 * NB: this assumes output has been stopped and
1553 * we do not need to block ath5k_tx_tasklet
1555 spin_lock_bh(&txq->lock);
1556 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1557 ath5k_debug_printtxbuf(sc, bf);
1559 ath5k_txbuf_free(sc, bf);
1561 spin_lock_bh(&sc->txbuflock);
1562 sc->tx_stats[txq->qnum].len--;
1563 list_move_tail(&bf->list, &sc->txbuf);
1565 spin_unlock_bh(&sc->txbuflock);
1568 spin_unlock_bh(&txq->lock);
1572 * Drain the transmit queues and reclaim resources.
1575 ath5k_txq_cleanup(struct ath5k_softc *sc)
1577 struct ath5k_hw *ah = sc->ah;
1580 /* XXX return value */
1581 if (likely(!test_bit(ATH_STAT_INVALID, sc->status))) {
1582 /* don't touch the hardware if marked invalid */
1583 ath5k_hw_stop_tx_dma(ah, sc->bhalq);
1584 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "beacon queue %x\n",
1585 ath5k_hw_get_txdp(ah, sc->bhalq));
1586 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1587 if (sc->txqs[i].setup) {
1588 ath5k_hw_stop_tx_dma(ah, sc->txqs[i].qnum);
1589 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "txq [%u] %x, "
1592 ath5k_hw_get_txdp(ah,
1597 ieee80211_wake_queues(sc->hw); /* XXX move to callers */
1599 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++)
1600 if (sc->txqs[i].setup)
1601 ath5k_txq_drainq(sc, &sc->txqs[i]);
1605 ath5k_txq_release(struct ath5k_softc *sc)
1607 struct ath5k_txq *txq = sc->txqs;
1610 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++)
1612 ath5k_hw_release_tx_queue(sc->ah, txq->qnum);
1625 * Enable the receive h/w following a reset.
1628 ath5k_rx_start(struct ath5k_softc *sc)
1630 struct ath5k_hw *ah = sc->ah;
1631 struct ath_common *common = ath5k_hw_common(ah);
1632 struct ath5k_buf *bf;
1635 sc->rxbufsize = roundup(IEEE80211_MAX_LEN, common->cachelsz);
1637 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rxbufsize %u\n",
1638 common->cachelsz, sc->rxbufsize);
1640 spin_lock_bh(&sc->rxbuflock);
1642 list_for_each_entry(bf, &sc->rxbuf, list) {
1643 ret = ath5k_rxbuf_setup(sc, bf);
1645 spin_unlock_bh(&sc->rxbuflock);
1649 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1650 ath5k_hw_set_rxdp(ah, bf->daddr);
1651 spin_unlock_bh(&sc->rxbuflock);
1653 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */
1654 ath5k_mode_setup(sc); /* set filters, etc. */
1655 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */
1663 * Disable the receive h/w in preparation for a reset.
1666 ath5k_rx_stop(struct ath5k_softc *sc)
1668 struct ath5k_hw *ah = sc->ah;
1670 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */
1671 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */
1672 ath5k_hw_stop_rx_dma(ah); /* disable DMA engine */
1674 ath5k_debug_printrxbuffs(sc, ah);
1676 sc->rxlink = NULL; /* just in case */
1680 ath5k_rx_decrypted(struct ath5k_softc *sc, struct ath5k_desc *ds,
1681 struct sk_buff *skb, struct ath5k_rx_status *rs)
1683 struct ieee80211_hdr *hdr = (void *)skb->data;
1684 unsigned int keyix, hlen;
1686 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1687 rs->rs_keyix != AR5K_RXKEYIX_INVALID)
1688 return RX_FLAG_DECRYPTED;
1690 /* Apparently when a default key is used to decrypt the packet
1691 the hw does not set the index used to decrypt. In such cases
1692 get the index from the packet. */
1693 hlen = ieee80211_hdrlen(hdr->frame_control);
1694 if (ieee80211_has_protected(hdr->frame_control) &&
1695 !(rs->rs_status & AR5K_RXERR_DECRYPT) &&
1696 skb->len >= hlen + 4) {
1697 keyix = skb->data[hlen + 3] >> 6;
1699 if (test_bit(keyix, sc->keymap))
1700 return RX_FLAG_DECRYPTED;
1708 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb,
1709 struct ieee80211_rx_status *rxs)
1711 struct ath_common *common = ath5k_hw_common(sc->ah);
1714 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
1716 if (ieee80211_is_beacon(mgmt->frame_control) &&
1717 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS &&
1718 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) {
1720 * Received an IBSS beacon with the same BSSID. Hardware *must*
1721 * have updated the local TSF. We have to work around various
1722 * hardware bugs, though...
1724 tsf = ath5k_hw_get_tsf64(sc->ah);
1725 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp);
1726 hw_tu = TSF_TO_TU(tsf);
1728 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1729 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n",
1730 (unsigned long long)bc_tstamp,
1731 (unsigned long long)rxs->mactime,
1732 (unsigned long long)(rxs->mactime - bc_tstamp),
1733 (unsigned long long)tsf);
1736 * Sometimes the HW will give us a wrong tstamp in the rx
1737 * status, causing the timestamp extension to go wrong.
1738 * (This seems to happen especially with beacon frames bigger
1739 * than 78 byte (incl. FCS))
1740 * But we know that the receive timestamp must be later than the
1741 * timestamp of the beacon since HW must have synced to that.
1743 * NOTE: here we assume mactime to be after the frame was
1744 * received, not like mac80211 which defines it at the start.
1746 if (bc_tstamp > rxs->mactime) {
1747 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
1748 "fixing mactime from %llx to %llx\n",
1749 (unsigned long long)rxs->mactime,
1750 (unsigned long long)tsf);
1755 * Local TSF might have moved higher than our beacon timers,
1756 * in that case we have to update them to continue sending
1757 * beacons. This also takes care of synchronizing beacon sending
1758 * times with other stations.
1760 if (hw_tu >= sc->nexttbtt)
1761 ath5k_beacon_update_timers(sc, bc_tstamp);
1766 ath5k_tasklet_rx(unsigned long data)
1768 struct ieee80211_rx_status *rxs;
1769 struct ath5k_rx_status rs = {};
1770 struct sk_buff *skb, *next_skb;
1771 dma_addr_t next_skb_addr;
1772 struct ath5k_softc *sc = (void *)data;
1773 struct ath5k_buf *bf;
1774 struct ath5k_desc *ds;
1780 spin_lock(&sc->rxbuflock);
1781 if (list_empty(&sc->rxbuf)) {
1782 ATH5K_WARN(sc, "empty rx buf pool\n");
1788 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list);
1789 BUG_ON(bf->skb == NULL);
1793 /* bail if HW is still using self-linked descriptor */
1794 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr)
1797 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs);
1798 if (unlikely(ret == -EINPROGRESS))
1800 else if (unlikely(ret)) {
1801 ATH5K_ERR(sc, "error in processing rx descriptor\n");
1802 spin_unlock(&sc->rxbuflock);
1806 if (unlikely(rs.rs_more)) {
1807 ATH5K_WARN(sc, "unsupported jumbo\n");
1811 if (unlikely(rs.rs_status)) {
1812 if (rs.rs_status & AR5K_RXERR_PHY)
1814 if (rs.rs_status & AR5K_RXERR_DECRYPT) {
1816 * Decrypt error. If the error occurred
1817 * because there was no hardware key, then
1818 * let the frame through so the upper layers
1819 * can process it. This is necessary for 5210
1820 * parts which have no way to setup a ``clear''
1823 * XXX do key cache faulting
1825 if (rs.rs_keyix == AR5K_RXKEYIX_INVALID &&
1826 !(rs.rs_status & AR5K_RXERR_CRC))
1829 if (rs.rs_status & AR5K_RXERR_MIC) {
1830 rx_flag |= RX_FLAG_MMIC_ERROR;
1834 /* let crypto-error packets fall through in MNTR */
1836 ~(AR5K_RXERR_DECRYPT|AR5K_RXERR_MIC)) ||
1837 sc->opmode != NL80211_IFTYPE_MONITOR)
1841 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr);
1844 * If we can't replace bf->skb with a new skb under memory
1845 * pressure, just skip this packet
1850 pci_unmap_single(sc->pdev, bf->skbaddr, sc->rxbufsize,
1851 PCI_DMA_FROMDEVICE);
1852 skb_put(skb, rs.rs_datalen);
1854 /* The MAC header is padded to have 32-bit boundary if the
1855 * packet payload is non-zero. The general calculation for
1856 * padsize would take into account odd header lengths:
1857 * padsize = (4 - hdrlen % 4) % 4; However, since only
1858 * even-length headers are used, padding can only be 0 or 2
1859 * bytes and we can optimize this a bit. In addition, we must
1860 * not try to remove padding from short control frames that do
1861 * not have payload. */
1862 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
1863 padsize = ath5k_pad_size(hdrlen);
1865 memmove(skb->data + padsize, skb->data, hdrlen);
1866 skb_pull(skb, padsize);
1868 rxs = IEEE80211_SKB_RXCB(skb);
1871 * always extend the mac timestamp, since this information is
1872 * also needed for proper IBSS merging.
1874 * XXX: it might be too late to do it here, since rs_tstamp is
1875 * 15bit only. that means TSF extension has to be done within
1876 * 32768usec (about 32ms). it might be necessary to move this to
1877 * the interrupt handler, like it is done in madwifi.
1879 * Unfortunately we don't know when the hardware takes the rx
1880 * timestamp (beginning of phy frame, data frame, end of rx?).
1881 * The only thing we know is that it is hardware specific...
1882 * On AR5213 it seems the rx timestamp is at the end of the
1883 * frame, but i'm not sure.
1885 * NOTE: mac80211 defines mactime at the beginning of the first
1886 * data symbol. Since we don't have any time references it's
1887 * impossible to comply to that. This affects IBSS merge only
1888 * right now, so it's not too bad...
1890 rxs->mactime = ath5k_extend_tsf(sc->ah, rs.rs_tstamp);
1891 rxs->flag = rx_flag | RX_FLAG_TSFT;
1893 rxs->freq = sc->curchan->center_freq;
1894 rxs->band = sc->curband->band;
1896 rxs->noise = sc->ah->ah_noise_floor;
1897 rxs->signal = rxs->noise + rs.rs_rssi;
1899 /* An rssi of 35 indicates you should be able use
1900 * 54 Mbps reliably. A more elaborate scheme can be used
1901 * here but it requires a map of SNR/throughput for each
1902 * possible mode used */
1903 rxs->qual = rs.rs_rssi * 100 / 35;
1905 /* rssi can be more than 35 though, anything above that
1906 * should be considered at 100% */
1907 if (rxs->qual > 100)
1910 rxs->antenna = rs.rs_antenna;
1911 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs.rs_rate);
1912 rxs->flag |= ath5k_rx_decrypted(sc, ds, skb, &rs);
1914 if (rxs->rate_idx >= 0 && rs.rs_rate ==
1915 sc->curband->bitrates[rxs->rate_idx].hw_value_short)
1916 rxs->flag |= RX_FLAG_SHORTPRE;
1918 ath5k_debug_dump_skb(sc, skb, "RX ", 0);
1920 /* check beacons in IBSS mode */
1921 if (sc->opmode == NL80211_IFTYPE_ADHOC)
1922 ath5k_check_ibss_tsf(sc, skb, rxs);
1924 ieee80211_rx(sc->hw, skb);
1927 bf->skbaddr = next_skb_addr;
1929 list_move_tail(&bf->list, &sc->rxbuf);
1930 } while (ath5k_rxbuf_setup(sc, bf) == 0);
1932 spin_unlock(&sc->rxbuflock);
1943 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq)
1945 struct ath5k_tx_status ts = {};
1946 struct ath5k_buf *bf, *bf0;
1947 struct ath5k_desc *ds;
1948 struct sk_buff *skb;
1949 struct ieee80211_tx_info *info;
1952 spin_lock(&txq->lock);
1953 list_for_each_entry_safe(bf, bf0, &txq->q, list) {
1956 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts);
1957 if (unlikely(ret == -EINPROGRESS))
1959 else if (unlikely(ret)) {
1960 ATH5K_ERR(sc, "error %d while processing queue %u\n",
1966 info = IEEE80211_SKB_CB(skb);
1969 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len,
1972 ieee80211_tx_info_clear_status(info);
1973 for (i = 0; i < 4; i++) {
1974 struct ieee80211_tx_rate *r =
1975 &info->status.rates[i];
1977 if (ts.ts_rate[i]) {
1978 r->idx = ath5k_hw_to_driver_rix(sc, ts.ts_rate[i]);
1979 r->count = ts.ts_retry[i];
1986 /* count the successful attempt as well */
1987 info->status.rates[ts.ts_final_idx].count++;
1989 if (unlikely(ts.ts_status)) {
1990 sc->ll_stats.dot11ACKFailureCount++;
1991 if (ts.ts_status & AR5K_TXERR_FILT)
1992 info->flags |= IEEE80211_TX_STAT_TX_FILTERED;
1994 info->flags |= IEEE80211_TX_STAT_ACK;
1995 info->status.ack_signal = ts.ts_rssi;
1998 ieee80211_tx_status(sc->hw, skb);
1999 sc->tx_stats[txq->qnum].count++;
2001 spin_lock(&sc->txbuflock);
2002 sc->tx_stats[txq->qnum].len--;
2003 list_move_tail(&bf->list, &sc->txbuf);
2005 spin_unlock(&sc->txbuflock);
2007 if (likely(list_empty(&txq->q)))
2009 spin_unlock(&txq->lock);
2010 if (sc->txbuf_len > ATH_TXBUF / 5)
2011 ieee80211_wake_queues(sc->hw);
2015 ath5k_tasklet_tx(unsigned long data)
2018 struct ath5k_softc *sc = (void *)data;
2020 for (i=0; i < AR5K_NUM_TX_QUEUES; i++)
2021 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i)))
2022 ath5k_tx_processq(sc, &sc->txqs[i]);
2031 * Setup the beacon frame for transmit.
2034 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf)
2036 struct sk_buff *skb = bf->skb;
2037 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
2038 struct ath5k_hw *ah = sc->ah;
2039 struct ath5k_desc *ds;
2044 bf->skbaddr = pci_map_single(sc->pdev, skb->data, skb->len,
2046 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] "
2047 "skbaddr %llx\n", skb, skb->data, skb->len,
2048 (unsigned long long)bf->skbaddr);
2049 if (pci_dma_mapping_error(sc->pdev, bf->skbaddr)) {
2050 ATH5K_ERR(sc, "beacon DMA mapping failed\n");
2055 antenna = ah->ah_tx_ant;
2057 flags = AR5K_TXDESC_NOACK;
2058 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) {
2059 ds->ds_link = bf->daddr; /* self-linked */
2060 flags |= AR5K_TXDESC_VEOL;
2065 * If we use multiple antennas on AP and use
2066 * the Sectored AP scenario, switch antenna every
2067 * 4 beacons to make sure everybody hears our AP.
2068 * When a client tries to associate, hw will keep
2069 * track of the tx antenna to be used for this client
2070 * automaticaly, based on ACKed packets.
2072 * Note: AP still listens and transmits RTS on the
2073 * default antenna which is supposed to be an omni.
2075 * Note2: On sectored scenarios it's possible to have
2076 * multiple antennas (1omni -the default- and 14 sectors)
2077 * so if we choose to actually support this mode we need
2078 * to allow user to set how many antennas we have and tweak
2079 * the code below to send beacons on all of them.
2081 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP)
2082 antenna = sc->bsent & 4 ? 2 : 1;
2085 /* FIXME: If we are in g mode and rate is a CCK rate
2086 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta
2087 * from tx power (value is in dB units already) */
2088 ds->ds_data = bf->skbaddr;
2089 ret = ah->ah_setup_tx_desc(ah, ds, skb->len,
2090 ieee80211_get_hdrlen_from_skb(skb),
2091 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2),
2092 ieee80211_get_tx_rate(sc->hw, info)->hw_value,
2093 1, AR5K_TXKEYIX_INVALID,
2094 antenna, flags, 0, 0);
2100 pci_unmap_single(sc->pdev, bf->skbaddr, skb->len, PCI_DMA_TODEVICE);
2105 * Transmit a beacon frame at SWBA. Dynamic updates to the
2106 * frame contents are done as needed and the slot time is
2107 * also adjusted based on current state.
2109 * This is called from software irq context (beacontq or restq
2110 * tasklets) or user context from ath5k_beacon_config.
2113 ath5k_beacon_send(struct ath5k_softc *sc)
2115 struct ath5k_buf *bf = sc->bbuf;
2116 struct ath5k_hw *ah = sc->ah;
2117 struct sk_buff *skb;
2119 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n");
2121 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION ||
2122 sc->opmode == NL80211_IFTYPE_MONITOR)) {
2123 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL);
2127 * Check if the previous beacon has gone out. If
2128 * not don't don't try to post another, skip this
2129 * period and wait for the next. Missed beacons
2130 * indicate a problem and should not occur. If we
2131 * miss too many consecutive beacons reset the device.
2133 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) {
2135 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2136 "missed %u consecutive beacons\n", sc->bmisscount);
2137 if (sc->bmisscount > 10) { /* NB: 10 is a guess */
2138 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2139 "stuck beacon time (%u missed)\n",
2141 tasklet_schedule(&sc->restq);
2145 if (unlikely(sc->bmisscount != 0)) {
2146 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2147 "resume beacon xmit after %u misses\n",
2153 * Stop any current dma and put the new frame on the queue.
2154 * This should never fail since we check above that no frames
2155 * are still pending on the queue.
2157 if (unlikely(ath5k_hw_stop_tx_dma(ah, sc->bhalq))) {
2158 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq);
2159 /* NB: hw still stops DMA, so proceed */
2162 /* refresh the beacon for AP mode */
2163 if (sc->opmode == NL80211_IFTYPE_AP)
2164 ath5k_beacon_update(sc->hw, sc->vif);
2166 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr);
2167 ath5k_hw_start_tx_dma(ah, sc->bhalq);
2168 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n",
2169 sc->bhalq, (unsigned long long)bf->daddr, bf->desc);
2171 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2173 ath5k_tx_queue(sc->hw, skb, sc->cabq);
2174 skb = ieee80211_get_buffered_bc(sc->hw, sc->vif);
2182 * ath5k_beacon_update_timers - update beacon timers
2184 * @sc: struct ath5k_softc pointer we are operating on
2185 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a
2186 * beacon timer update based on the current HW TSF.
2188 * Calculate the next target beacon transmit time (TBTT) based on the timestamp
2189 * of a received beacon or the current local hardware TSF and write it to the
2190 * beacon timer registers.
2192 * This is called in a variety of situations, e.g. when a beacon is received,
2193 * when a TSF update has been detected, but also when an new IBSS is created or
2194 * when we otherwise know we have to update the timers, but we keep it in this
2195 * function to have it all together in one place.
2198 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf)
2200 struct ath5k_hw *ah = sc->ah;
2201 u32 nexttbtt, intval, hw_tu, bc_tu;
2204 intval = sc->bintval & AR5K_BEACON_PERIOD;
2205 if (WARN_ON(!intval))
2208 /* beacon TSF converted to TU */
2209 bc_tu = TSF_TO_TU(bc_tsf);
2211 /* current TSF converted to TU */
2212 hw_tsf = ath5k_hw_get_tsf64(ah);
2213 hw_tu = TSF_TO_TU(hw_tsf);
2216 /* we use FUDGE to make sure the next TBTT is ahead of the current TU */
2219 * no beacons received, called internally.
2220 * just need to refresh timers based on HW TSF.
2222 nexttbtt = roundup(hw_tu + FUDGE, intval);
2223 } else if (bc_tsf == 0) {
2225 * no beacon received, probably called by ath5k_reset_tsf().
2226 * reset TSF to start with 0.
2229 intval |= AR5K_BEACON_RESET_TSF;
2230 } else if (bc_tsf > hw_tsf) {
2232 * beacon received, SW merge happend but HW TSF not yet updated.
2233 * not possible to reconfigure timers yet, but next time we
2234 * receive a beacon with the same BSSID, the hardware will
2235 * automatically update the TSF and then we need to reconfigure
2238 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2239 "need to wait for HW TSF sync\n");
2243 * most important case for beacon synchronization between STA.
2245 * beacon received and HW TSF has been already updated by HW.
2246 * update next TBTT based on the TSF of the beacon, but make
2247 * sure it is ahead of our local TSF timer.
2249 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval);
2253 sc->nexttbtt = nexttbtt;
2255 intval |= AR5K_BEACON_ENA;
2256 ath5k_hw_init_beacon(ah, nexttbtt, intval);
2259 * debugging output last in order to preserve the time critical aspect
2263 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2264 "reconfigured timers based on HW TSF\n");
2265 else if (bc_tsf == 0)
2266 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2267 "reset HW TSF and timers\n");
2269 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2270 "updated timers based on beacon TSF\n");
2272 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON,
2273 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n",
2274 (unsigned long long) bc_tsf,
2275 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt);
2276 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n",
2277 intval & AR5K_BEACON_PERIOD,
2278 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "",
2279 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : "");
2284 * ath5k_beacon_config - Configure the beacon queues and interrupts
2286 * @sc: struct ath5k_softc pointer we are operating on
2288 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA
2289 * interrupts to detect TSF updates only.
2292 ath5k_beacon_config(struct ath5k_softc *sc)
2294 struct ath5k_hw *ah = sc->ah;
2295 unsigned long flags;
2297 spin_lock_irqsave(&sc->block, flags);
2299 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA);
2301 if (sc->enable_beacon) {
2303 * In IBSS mode we use a self-linked tx descriptor and let the
2304 * hardware send the beacons automatically. We have to load it
2306 * We use the SWBA interrupt only to keep track of the beacon
2307 * timers in order to detect automatic TSF updates.
2309 ath5k_beaconq_config(sc);
2311 sc->imask |= AR5K_INT_SWBA;
2313 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2314 if (ath5k_hw_hasveol(ah))
2315 ath5k_beacon_send(sc);
2317 ath5k_beacon_update_timers(sc, -1);
2319 ath5k_hw_stop_tx_dma(sc->ah, sc->bhalq);
2322 ath5k_hw_set_imr(ah, sc->imask);
2324 spin_unlock_irqrestore(&sc->block, flags);
2327 static void ath5k_tasklet_beacon(unsigned long data)
2329 struct ath5k_softc *sc = (struct ath5k_softc *) data;
2332 * Software beacon alert--time to send a beacon.
2334 * In IBSS mode we use this interrupt just to
2335 * keep track of the next TBTT (target beacon
2336 * transmission time) in order to detect wether
2337 * automatic TSF updates happened.
2339 if (sc->opmode == NL80211_IFTYPE_ADHOC) {
2340 /* XXX: only if VEOL suppported */
2341 u64 tsf = ath5k_hw_get_tsf64(sc->ah);
2342 sc->nexttbtt += sc->bintval;
2343 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON,
2344 "SWBA nexttbtt: %x hw_tu: %x "
2348 (unsigned long long) tsf);
2350 spin_lock(&sc->block);
2351 ath5k_beacon_send(sc);
2352 spin_unlock(&sc->block);
2357 /********************\
2358 * Interrupt handling *
2359 \********************/
2362 ath5k_init(struct ath5k_softc *sc)
2364 struct ath5k_hw *ah = sc->ah;
2367 mutex_lock(&sc->lock);
2369 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode);
2372 * Stop anything previously setup. This is safe
2373 * no matter this is the first time through or not.
2375 ath5k_stop_locked(sc);
2378 * The basic interface to setting the hardware in a good
2379 * state is ``reset''. On return the hardware is known to
2380 * be powered up and with interrupts disabled. This must
2381 * be followed by initialization of the appropriate bits
2382 * and then setup of the interrupt mask.
2384 sc->curchan = sc->hw->conf.channel;
2385 sc->curband = &sc->sbands[sc->curchan->band];
2386 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL |
2387 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL |
2388 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_SWI;
2389 ret = ath5k_reset(sc, NULL);
2393 ath5k_rfkill_hw_start(ah);
2396 * Reset the key cache since some parts do not reset the
2397 * contents on initial power up or resume from suspend.
2399 for (i = 0; i < AR5K_KEYTABLE_SIZE; i++)
2400 ath5k_hw_reset_key(ah, i);
2402 /* Set ack to be sent at low bit-rates */
2403 ath5k_hw_set_ack_bitrate_high(ah, false);
2405 /* Set PHY calibration inteval */
2406 ah->ah_cal_intval = ath5k_calinterval;
2411 mutex_unlock(&sc->lock);
2416 ath5k_stop_locked(struct ath5k_softc *sc)
2418 struct ath5k_hw *ah = sc->ah;
2420 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n",
2421 test_bit(ATH_STAT_INVALID, sc->status));
2424 * Shutdown the hardware and driver:
2425 * stop output from above
2426 * disable interrupts
2428 * turn off the radio
2429 * clear transmit machinery
2430 * clear receive machinery
2431 * drain and release tx queues
2432 * reclaim beacon resources
2433 * power down hardware
2435 * Note that some of this work is not possible if the
2436 * hardware is gone (invalid).
2438 ieee80211_stop_queues(sc->hw);
2440 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2442 ath5k_hw_set_imr(ah, 0);
2443 synchronize_irq(sc->pdev->irq);
2445 ath5k_txq_cleanup(sc);
2446 if (!test_bit(ATH_STAT_INVALID, sc->status)) {
2448 ath5k_hw_phy_disable(ah);
2456 * Stop the device, grabbing the top-level lock to protect
2457 * against concurrent entry through ath5k_init (which can happen
2458 * if another thread does a system call and the thread doing the
2459 * stop is preempted).
2462 ath5k_stop_hw(struct ath5k_softc *sc)
2466 mutex_lock(&sc->lock);
2467 ret = ath5k_stop_locked(sc);
2468 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) {
2470 * Don't set the card in full sleep mode!
2472 * a) When the device is in this state it must be carefully
2473 * woken up or references to registers in the PCI clock
2474 * domain may freeze the bus (and system). This varies
2475 * by chip and is mostly an issue with newer parts
2476 * (madwifi sources mentioned srev >= 0x78) that go to
2477 * sleep more quickly.
2479 * b) On older chips full sleep results a weird behaviour
2480 * during wakeup. I tested various cards with srev < 0x78
2481 * and they don't wake up after module reload, a second
2482 * module reload is needed to bring the card up again.
2484 * Until we figure out what's going on don't enable
2485 * full chip reset on any chip (this is what Legacy HAL
2486 * and Sam's HAL do anyway). Instead Perform a full reset
2487 * on the device (same as initial state after attach) and
2488 * leave it idle (keep MAC/BB on warm reset) */
2489 ret = ath5k_hw_on_hold(sc->ah);
2491 ATH5K_DBG(sc, ATH5K_DEBUG_RESET,
2492 "putting device to sleep\n");
2494 ath5k_txbuf_free(sc, sc->bbuf);
2497 mutex_unlock(&sc->lock);
2499 tasklet_kill(&sc->rxtq);
2500 tasklet_kill(&sc->txtq);
2501 tasklet_kill(&sc->restq);
2502 tasklet_kill(&sc->calib);
2503 tasklet_kill(&sc->beacontq);
2505 ath5k_rfkill_hw_stop(sc->ah);
2511 ath5k_intr(int irq, void *dev_id)
2513 struct ath5k_softc *sc = dev_id;
2514 struct ath5k_hw *ah = sc->ah;
2515 enum ath5k_int status;
2516 unsigned int counter = 1000;
2518 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) ||
2519 !ath5k_hw_is_intr_pending(ah)))
2523 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */
2524 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n",
2526 if (unlikely(status & AR5K_INT_FATAL)) {
2528 * Fatal errors are unrecoverable.
2529 * Typically these are caused by DMA errors.
2531 tasklet_schedule(&sc->restq);
2532 } else if (unlikely(status & AR5K_INT_RXORN)) {
2533 tasklet_schedule(&sc->restq);
2535 if (status & AR5K_INT_SWBA) {
2536 tasklet_hi_schedule(&sc->beacontq);
2538 if (status & AR5K_INT_RXEOL) {
2540 * NB: the hardware should re-read the link when
2541 * RXE bit is written, but it doesn't work at
2542 * least on older hardware revs.
2546 if (status & AR5K_INT_TXURN) {
2547 /* bump tx trigger level */
2548 ath5k_hw_update_tx_triglevel(ah, true);
2550 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR))
2551 tasklet_schedule(&sc->rxtq);
2552 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC
2553 | AR5K_INT_TXERR | AR5K_INT_TXEOL))
2554 tasklet_schedule(&sc->txtq);
2555 if (status & AR5K_INT_BMISS) {
2558 if (status & AR5K_INT_SWI) {
2559 tasklet_schedule(&sc->calib);
2561 if (status & AR5K_INT_MIB) {
2563 * These stats are also used for ANI i think
2564 * so how about updating them more often ?
2566 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
2568 if (status & AR5K_INT_GPIO)
2569 tasklet_schedule(&sc->rf_kill.toggleq);
2572 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0);
2574 if (unlikely(!counter))
2575 ATH5K_WARN(sc, "too many interrupts, giving up for now\n");
2577 ath5k_hw_calibration_poll(ah);
2583 ath5k_tasklet_reset(unsigned long data)
2585 struct ath5k_softc *sc = (void *)data;
2587 ath5k_reset_wake(sc);
2591 * Periodically recalibrate the PHY to account
2592 * for temperature/environment changes.
2595 ath5k_tasklet_calibrate(unsigned long data)
2597 struct ath5k_softc *sc = (void *)data;
2598 struct ath5k_hw *ah = sc->ah;
2600 /* Only full calibration for now */
2601 if (ah->ah_swi_mask != AR5K_SWI_FULL_CALIBRATION)
2604 /* Stop queues so that calibration
2605 * doesn't interfere with tx */
2606 ieee80211_stop_queues(sc->hw);
2608 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n",
2609 ieee80211_frequency_to_channel(sc->curchan->center_freq),
2610 sc->curchan->hw_value);
2612 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) {
2614 * Rfgain is out of bounds, reset the chip
2615 * to load new gain values.
2617 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n");
2618 ath5k_reset_wake(sc);
2620 if (ath5k_hw_phy_calibrate(ah, sc->curchan))
2621 ATH5K_ERR(sc, "calibration of channel %u failed\n",
2622 ieee80211_frequency_to_channel(
2623 sc->curchan->center_freq));
2625 ah->ah_swi_mask = 0;
2628 ieee80211_wake_queues(sc->hw);
2633 /********************\
2634 * Mac80211 functions *
2635 \********************/
2638 ath5k_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2640 struct ath5k_softc *sc = hw->priv;
2642 return ath5k_tx_queue(hw, skb, sc->txq);
2645 static int ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb,
2646 struct ath5k_txq *txq)
2648 struct ath5k_softc *sc = hw->priv;
2649 struct ath5k_buf *bf;
2650 unsigned long flags;
2654 ath5k_debug_dump_skb(sc, skb, "TX ", 1);
2656 if (sc->opmode == NL80211_IFTYPE_MONITOR)
2657 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, "tx in monitor (scan?)\n");
2660 * the hardware expects the header padded to 4 byte boundaries
2661 * if this is not the case we add the padding after the header
2663 hdrlen = ieee80211_get_hdrlen_from_skb(skb);
2664 padsize = ath5k_pad_size(hdrlen);
2667 if (skb_headroom(skb) < padsize) {
2668 ATH5K_ERR(sc, "tx hdrlen not %%4: %d not enough"
2669 " headroom to pad %d\n", hdrlen, padsize);
2672 skb_push(skb, padsize);
2673 memmove(skb->data, skb->data+padsize, hdrlen);
2676 spin_lock_irqsave(&sc->txbuflock, flags);
2677 if (list_empty(&sc->txbuf)) {
2678 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n");
2679 spin_unlock_irqrestore(&sc->txbuflock, flags);
2680 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
2683 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list);
2684 list_del(&bf->list);
2686 if (list_empty(&sc->txbuf))
2687 ieee80211_stop_queues(hw);
2688 spin_unlock_irqrestore(&sc->txbuflock, flags);
2692 if (ath5k_txbuf_setup(sc, bf, txq)) {
2694 spin_lock_irqsave(&sc->txbuflock, flags);
2695 list_add_tail(&bf->list, &sc->txbuf);
2697 spin_unlock_irqrestore(&sc->txbuflock, flags);
2700 return NETDEV_TX_OK;
2703 dev_kfree_skb_any(skb);
2704 return NETDEV_TX_OK;
2708 * Reset the hardware. If chan is not NULL, then also pause rx/tx
2709 * and change to the given channel.
2712 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan)
2714 struct ath5k_hw *ah = sc->ah;
2717 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n");
2720 ath5k_hw_set_imr(ah, 0);
2721 ath5k_txq_cleanup(sc);
2725 sc->curband = &sc->sbands[chan->band];
2727 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, chan != NULL);
2729 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret);
2733 ret = ath5k_rx_start(sc);
2735 ATH5K_ERR(sc, "can't start recv logic\n");
2740 * Change channels and update the h/w rate map if we're switching;
2741 * e.g. 11a to 11b/g.
2743 * We may be doing a reset in response to an ioctl that changes the
2744 * channel so update any state that might change as a result.
2748 /* ath5k_chan_change(sc, c); */
2750 ath5k_beacon_config(sc);
2751 /* intrs are enabled by ath5k_beacon_config */
2759 ath5k_reset_wake(struct ath5k_softc *sc)
2763 ret = ath5k_reset(sc, sc->curchan);
2765 ieee80211_wake_queues(sc->hw);
2770 static int ath5k_start(struct ieee80211_hw *hw)
2772 return ath5k_init(hw->priv);
2775 static void ath5k_stop(struct ieee80211_hw *hw)
2777 ath5k_stop_hw(hw->priv);
2780 static int ath5k_add_interface(struct ieee80211_hw *hw,
2781 struct ieee80211_if_init_conf *conf)
2783 struct ath5k_softc *sc = hw->priv;
2786 mutex_lock(&sc->lock);
2792 sc->vif = conf->vif;
2794 switch (conf->type) {
2795 case NL80211_IFTYPE_AP:
2796 case NL80211_IFTYPE_STATION:
2797 case NL80211_IFTYPE_ADHOC:
2798 case NL80211_IFTYPE_MESH_POINT:
2799 case NL80211_IFTYPE_MONITOR:
2800 sc->opmode = conf->type;
2807 ath5k_hw_set_lladdr(sc->ah, conf->mac_addr);
2808 ath5k_mode_setup(sc);
2812 mutex_unlock(&sc->lock);
2817 ath5k_remove_interface(struct ieee80211_hw *hw,
2818 struct ieee80211_if_init_conf *conf)
2820 struct ath5k_softc *sc = hw->priv;
2821 u8 mac[ETH_ALEN] = {};
2823 mutex_lock(&sc->lock);
2824 if (sc->vif != conf->vif)
2827 ath5k_hw_set_lladdr(sc->ah, mac);
2830 mutex_unlock(&sc->lock);
2834 * TODO: Phy disable/diversity etc
2837 ath5k_config(struct ieee80211_hw *hw, u32 changed)
2839 struct ath5k_softc *sc = hw->priv;
2840 struct ath5k_hw *ah = sc->ah;
2841 struct ieee80211_conf *conf = &hw->conf;
2844 mutex_lock(&sc->lock);
2846 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
2847 ret = ath5k_chan_set(sc, conf->channel);
2852 if ((changed & IEEE80211_CONF_CHANGE_POWER) &&
2853 (sc->power_level != conf->power_level)) {
2854 sc->power_level = conf->power_level;
2857 ath5k_hw_set_txpower_limit(ah, (conf->power_level * 2));
2861 * 1) Move this on config_interface and handle each case
2862 * separately eg. when we have only one STA vif, use
2863 * AR5K_ANTMODE_SINGLE_AP
2865 * 2) Allow the user to change antenna mode eg. when only
2866 * one antenna is present
2868 * 3) Allow the user to set default/tx antenna when possible
2870 * 4) Default mode should handle 90% of the cases, together
2871 * with fixed a/b and single AP modes we should be able to
2872 * handle 99%. Sectored modes are extreme cases and i still
2873 * haven't found a usage for them. If we decide to support them,
2874 * then we must allow the user to set how many tx antennas we
2877 ath5k_hw_set_antenna_mode(ah, AR5K_ANTMODE_DEFAULT);
2880 mutex_unlock(&sc->lock);
2884 static u64 ath5k_prepare_multicast(struct ieee80211_hw *hw,
2885 int mc_count, struct dev_addr_list *mclist)
2894 for (i = 0; i < mc_count; i++) {
2897 /* calculate XOR of eight 6-bit values */
2898 val = get_unaligned_le32(mclist->dmi_addr + 0);
2899 pos = (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2900 val = get_unaligned_le32(mclist->dmi_addr + 3);
2901 pos ^= (val >> 18) ^ (val >> 12) ^ (val >> 6) ^ val;
2903 mfilt[pos / 32] |= (1 << (pos % 32));
2904 /* XXX: we might be able to just do this instead,
2905 * but not sure, needs testing, if we do use this we'd
2906 * neet to inform below to not reset the mcast */
2907 /* ath5k_hw_set_mcast_filterindex(ah,
2908 * mclist->dmi_addr[5]); */
2909 mclist = mclist->next;
2912 return ((u64)(mfilt[1]) << 32) | mfilt[0];
2915 #define SUPPORTED_FIF_FLAGS \
2916 FIF_PROMISC_IN_BSS | FIF_ALLMULTI | FIF_FCSFAIL | \
2917 FIF_PLCPFAIL | FIF_CONTROL | FIF_OTHER_BSS | \
2918 FIF_BCN_PRBRESP_PROMISC
2920 * o always accept unicast, broadcast, and multicast traffic
2921 * o multicast traffic for all BSSIDs will be enabled if mac80211
2923 * o maintain current state of phy ofdm or phy cck error reception.
2924 * If the hardware detects any of these type of errors then
2925 * ath5k_hw_get_rx_filter() will pass to us the respective
2926 * hardware filters to be able to receive these type of frames.
2927 * o probe request frames are accepted only when operating in
2928 * hostap, adhoc, or monitor modes
2929 * o enable promiscuous mode according to the interface state
2931 * - when operating in adhoc mode so the 802.11 layer creates
2932 * node table entries for peers,
2933 * - when operating in station mode for collecting rssi data when
2934 * the station is otherwise quiet, or
2937 static void ath5k_configure_filter(struct ieee80211_hw *hw,
2938 unsigned int changed_flags,
2939 unsigned int *new_flags,
2942 struct ath5k_softc *sc = hw->priv;
2943 struct ath5k_hw *ah = sc->ah;
2944 u32 mfilt[2], rfilt;
2946 mutex_lock(&sc->lock);
2948 mfilt[0] = multicast;
2949 mfilt[1] = multicast >> 32;
2951 /* Only deal with supported flags */
2952 changed_flags &= SUPPORTED_FIF_FLAGS;
2953 *new_flags &= SUPPORTED_FIF_FLAGS;
2955 /* If HW detects any phy or radar errors, leave those filters on.
2956 * Also, always enable Unicast, Broadcasts and Multicast
2957 * XXX: move unicast, bssid broadcasts and multicast to mac80211 */
2958 rfilt = (ath5k_hw_get_rx_filter(ah) & (AR5K_RX_FILTER_PHYERR)) |
2959 (AR5K_RX_FILTER_UCAST | AR5K_RX_FILTER_BCAST |
2960 AR5K_RX_FILTER_MCAST);
2962 if (changed_flags & (FIF_PROMISC_IN_BSS | FIF_OTHER_BSS)) {
2963 if (*new_flags & FIF_PROMISC_IN_BSS) {
2964 rfilt |= AR5K_RX_FILTER_PROM;
2965 __set_bit(ATH_STAT_PROMISC, sc->status);
2967 __clear_bit(ATH_STAT_PROMISC, sc->status);
2971 /* Note, AR5K_RX_FILTER_MCAST is already enabled */
2972 if (*new_flags & FIF_ALLMULTI) {
2977 /* This is the best we can do */
2978 if (*new_flags & (FIF_FCSFAIL | FIF_PLCPFAIL))
2979 rfilt |= AR5K_RX_FILTER_PHYERR;
2981 /* FIF_BCN_PRBRESP_PROMISC really means to enable beacons
2982 * and probes for any BSSID, this needs testing */
2983 if (*new_flags & FIF_BCN_PRBRESP_PROMISC)
2984 rfilt |= AR5K_RX_FILTER_BEACON | AR5K_RX_FILTER_PROBEREQ;
2986 /* FIF_CONTROL doc says that if FIF_PROMISC_IN_BSS is not
2987 * set we should only pass on control frames for this
2988 * station. This needs testing. I believe right now this
2989 * enables *all* control frames, which is OK.. but
2990 * but we should see if we can improve on granularity */
2991 if (*new_flags & FIF_CONTROL)
2992 rfilt |= AR5K_RX_FILTER_CONTROL;
2994 /* Additional settings per mode -- this is per ath5k */
2996 /* XXX move these to mac80211, and add a beacon IFF flag to mac80211 */
2998 switch (sc->opmode) {
2999 case NL80211_IFTYPE_MESH_POINT:
3000 case NL80211_IFTYPE_MONITOR:
3001 rfilt |= AR5K_RX_FILTER_CONTROL |
3002 AR5K_RX_FILTER_BEACON |
3003 AR5K_RX_FILTER_PROBEREQ |
3004 AR5K_RX_FILTER_PROM;
3006 case NL80211_IFTYPE_AP:
3007 case NL80211_IFTYPE_ADHOC:
3008 rfilt |= AR5K_RX_FILTER_PROBEREQ |
3009 AR5K_RX_FILTER_BEACON;
3011 case NL80211_IFTYPE_STATION:
3013 rfilt |= AR5K_RX_FILTER_BEACON;
3019 ath5k_hw_set_rx_filter(ah, rfilt);
3021 /* Set multicast bits */
3022 ath5k_hw_set_mcast_filter(ah, mfilt[0], mfilt[1]);
3023 /* Set the cached hw filter flags, this will alter actually
3025 sc->filter_flags = rfilt;
3027 mutex_unlock(&sc->lock);
3031 ath5k_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
3032 struct ieee80211_vif *vif, struct ieee80211_sta *sta,
3033 struct ieee80211_key_conf *key)
3035 struct ath5k_softc *sc = hw->priv;
3038 if (modparam_nohwcrypt)
3041 if (sc->opmode == NL80211_IFTYPE_AP)
3049 if (sc->ah->ah_aes_support)
3058 mutex_lock(&sc->lock);
3062 ret = ath5k_hw_set_key(sc->ah, key->keyidx, key,
3063 sta ? sta->addr : NULL);
3065 ATH5K_ERR(sc, "can't set the key\n");
3068 __set_bit(key->keyidx, sc->keymap);
3069 key->hw_key_idx = key->keyidx;
3070 key->flags |= (IEEE80211_KEY_FLAG_GENERATE_IV |
3071 IEEE80211_KEY_FLAG_GENERATE_MMIC);
3074 ath5k_hw_reset_key(sc->ah, key->keyidx);
3075 __clear_bit(key->keyidx, sc->keymap);
3084 mutex_unlock(&sc->lock);
3089 ath5k_get_stats(struct ieee80211_hw *hw,
3090 struct ieee80211_low_level_stats *stats)
3092 struct ath5k_softc *sc = hw->priv;
3093 struct ath5k_hw *ah = sc->ah;
3096 ath5k_hw_update_mib_counters(ah, &sc->ll_stats);
3098 memcpy(stats, &sc->ll_stats, sizeof(sc->ll_stats));
3104 ath5k_get_tx_stats(struct ieee80211_hw *hw,
3105 struct ieee80211_tx_queue_stats *stats)
3107 struct ath5k_softc *sc = hw->priv;
3109 memcpy(stats, &sc->tx_stats, sizeof(sc->tx_stats));
3115 ath5k_get_tsf(struct ieee80211_hw *hw)
3117 struct ath5k_softc *sc = hw->priv;
3119 return ath5k_hw_get_tsf64(sc->ah);
3123 ath5k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
3125 struct ath5k_softc *sc = hw->priv;
3127 ath5k_hw_set_tsf64(sc->ah, tsf);
3131 ath5k_reset_tsf(struct ieee80211_hw *hw)
3133 struct ath5k_softc *sc = hw->priv;
3136 * in IBSS mode we need to update the beacon timers too.
3137 * this will also reset the TSF if we call it with 0
3139 if (sc->opmode == NL80211_IFTYPE_ADHOC)
3140 ath5k_beacon_update_timers(sc, 0);
3142 ath5k_hw_reset_tsf(sc->ah);
3146 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc,
3147 * this is called only once at config_bss time, for AP we do it every
3148 * SWBA interrupt so that the TIM will reflect buffered frames.
3150 * Called with the beacon lock.
3153 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
3156 struct ath5k_softc *sc = hw->priv;
3157 struct sk_buff *skb;
3159 if (WARN_ON(!vif)) {
3164 skb = ieee80211_beacon_get(hw, vif);
3171 ath5k_debug_dump_skb(sc, skb, "BC ", 1);
3173 ath5k_txbuf_free(sc, sc->bbuf);
3174 sc->bbuf->skb = skb;
3175 ret = ath5k_beacon_setup(sc, sc->bbuf);
3177 sc->bbuf->skb = NULL;
3183 set_beacon_filter(struct ieee80211_hw *hw, bool enable)
3185 struct ath5k_softc *sc = hw->priv;
3186 struct ath5k_hw *ah = sc->ah;
3188 rfilt = ath5k_hw_get_rx_filter(ah);
3190 rfilt |= AR5K_RX_FILTER_BEACON;
3192 rfilt &= ~AR5K_RX_FILTER_BEACON;
3193 ath5k_hw_set_rx_filter(ah, rfilt);
3194 sc->filter_flags = rfilt;
3197 static void ath5k_bss_info_changed(struct ieee80211_hw *hw,
3198 struct ieee80211_vif *vif,
3199 struct ieee80211_bss_conf *bss_conf,
3202 struct ath5k_softc *sc = hw->priv;
3203 struct ath5k_hw *ah = sc->ah;
3204 struct ath_common *common = ath5k_hw_common(ah);
3205 unsigned long flags;
3207 mutex_lock(&sc->lock);
3208 if (WARN_ON(sc->vif != vif))
3211 if (changes & BSS_CHANGED_BSSID) {
3212 /* Cache for later use during resets */
3213 memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
3215 ath5k_hw_set_associd(ah);
3219 if (changes & BSS_CHANGED_BEACON_INT)
3220 sc->bintval = bss_conf->beacon_int;
3222 if (changes & BSS_CHANGED_ASSOC) {
3223 sc->assoc = bss_conf->assoc;
3224 if (sc->opmode == NL80211_IFTYPE_STATION)
3225 set_beacon_filter(hw, sc->assoc);
3226 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3227 AR5K_LED_ASSOC : AR5K_LED_INIT);
3228 if (bss_conf->assoc) {
3229 ATH5K_DBG(sc, ATH5K_DEBUG_ANY,
3230 "Bss Info ASSOC %d, bssid: %pM\n",
3231 bss_conf->aid, common->curbssid);
3232 common->curaid = bss_conf->aid;
3233 ath5k_hw_set_associd(ah);
3234 /* Once ANI is available you would start it here */
3238 if (changes & BSS_CHANGED_BEACON) {
3239 spin_lock_irqsave(&sc->block, flags);
3240 ath5k_beacon_update(hw, vif);
3241 spin_unlock_irqrestore(&sc->block, flags);
3244 if (changes & BSS_CHANGED_BEACON_ENABLED)
3245 sc->enable_beacon = bss_conf->enable_beacon;
3247 if (changes & (BSS_CHANGED_BEACON | BSS_CHANGED_BEACON_ENABLED |
3248 BSS_CHANGED_BEACON_INT))
3249 ath5k_beacon_config(sc);
3252 mutex_unlock(&sc->lock);
3255 static void ath5k_sw_scan_start(struct ieee80211_hw *hw)
3257 struct ath5k_softc *sc = hw->priv;
3259 ath5k_hw_set_ledstate(sc->ah, AR5K_LED_SCAN);
3262 static void ath5k_sw_scan_complete(struct ieee80211_hw *hw)
3264 struct ath5k_softc *sc = hw->priv;
3265 ath5k_hw_set_ledstate(sc->ah, sc->assoc ?
3266 AR5K_LED_ASSOC : AR5K_LED_INIT);
git.openpandora.org / pandora-kernel.git / blob