2 * Copyright (c) 2008-2009 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #include <linux/skbuff.h>
21 #include <linux/if_ether.h>
22 #include <linux/spinlock.h>
23 #include <net/mac80211.h>
26 * The key cache is used for h/w cipher state and also for
27 * tracking station state such as the current tx antenna.
28 * We also setup a mapping table between key cache slot indices
29 * and station state to short-circuit node lookups on rx.
30 * Different parts have different size key caches. We handle
31 * up to ATH_KEYMAX entries (could dynamically allocate state).
33 #define ATH_KEYMAX 128 /* max key cache size we handle */
35 static const u8 ath_bcast_mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
39 unsigned int longcal_timer;
40 unsigned int shortcal_timer;
41 unsigned int resetcal_timer;
42 unsigned int checkani_timer;
43 struct timer_list timer;
46 struct ath_cycle_counters {
53 enum ath_device_state {
64 struct reg_dmn_pair_mapping {
70 struct ath_regulatory {
78 struct reg_dmn_pair_mapping *regpair;
82 ATH_CRYPT_CAP_CIPHER_AESCCM = BIT(0),
83 ATH_CRYPT_CAP_MIC_COMBINED = BIT(1),
90 u8 kv_val[16]; /* TK */
91 u8 kv_mic[8]; /* Michael MIC key */
92 u8 kv_txmic[8]; /* Michael MIC TX key (used only if the hardware
93 * supports both MIC keys in the same key cache entry;
94 * in that case, kv_mic is the RX key) */
99 ATH_CIPHER_AES_OCB = 1,
100 ATH_CIPHER_AES_CCM = 2,
108 * struct ath_ops - Register read/write operations
110 * @read: Register read
111 * @multi_read: Multiple register read
112 * @write: Register write
113 * @enable_write_buffer: Enable multiple register writes
114 * @write_flush: flush buffered register writes and disable buffering
117 unsigned int (*read)(void *, u32 reg_offset);
118 void (*multi_read)(void *, u32 *addr, u32 *val, u16 count);
119 void (*write)(void *, u32 val, u32 reg_offset);
120 void (*enable_write_buffer)(void *);
121 void (*write_flush) (void *);
122 u32 (*rmw)(void *, u32 reg_offset, u32 set, u32 clr);
131 struct ieee80211_hw *hw;
133 enum ath_device_state state;
139 u8 macaddr[ETH_ALEN];
140 u8 curbssid[ETH_ALEN];
141 u8 bssidmask[ETH_ALEN];
149 DECLARE_BITMAP(keymap, ATH_KEYMAX);
150 DECLARE_BITMAP(tkip_keymap, ATH_KEYMAX);
151 enum ath_crypt_caps crypt_caps;
153 unsigned int clockrate;
156 struct ath_cycle_counters cc_ani;
157 struct ath_cycle_counters cc_survey;
159 struct ath_regulatory regulatory;
160 const struct ath_ops *ops;
161 const struct ath_bus_ops *bus_ops;
166 struct sk_buff *ath_rxbuf_alloc(struct ath_common *common,
170 void ath_hw_setbssidmask(struct ath_common *common);
171 void ath_key_delete(struct ath_common *common, struct ieee80211_key_conf *key);
172 int ath_key_config(struct ath_common *common,
173 struct ieee80211_vif *vif,
174 struct ieee80211_sta *sta,
175 struct ieee80211_key_conf *key);
176 bool ath_hw_keyreset(struct ath_common *common, u16 entry);
177 void ath_hw_cycle_counters_update(struct ath_common *common);
178 int32_t ath_hw_get_listen_time(struct ath_common *common);
180 extern __attribute__ ((format (printf, 3, 4))) int
181 ath_printk(const char *level, struct ath_common *common, const char *fmt, ...);
183 #define ath_emerg(common, fmt, ...) \
184 ath_printk(KERN_EMERG, common, fmt, ##__VA_ARGS__)
185 #define ath_alert(common, fmt, ...) \
186 ath_printk(KERN_ALERT, common, fmt, ##__VA_ARGS__)
187 #define ath_crit(common, fmt, ...) \
188 ath_printk(KERN_CRIT, common, fmt, ##__VA_ARGS__)
189 #define ath_err(common, fmt, ...) \
190 ath_printk(KERN_ERR, common, fmt, ##__VA_ARGS__)
191 #define ath_warn(common, fmt, ...) \
192 ath_printk(KERN_WARNING, common, fmt, ##__VA_ARGS__)
193 #define ath_notice(common, fmt, ...) \
194 ath_printk(KERN_NOTICE, common, fmt, ##__VA_ARGS__)
195 #define ath_info(common, fmt, ...) \
196 ath_printk(KERN_INFO, common, fmt, ##__VA_ARGS__)
199 * enum ath_debug_level - atheros wireless debug level
201 * @ATH_DBG_RESET: reset processing
202 * @ATH_DBG_QUEUE: hardware queue management
203 * @ATH_DBG_EEPROM: eeprom processing
204 * @ATH_DBG_CALIBRATE: periodic calibration
205 * @ATH_DBG_INTERRUPT: interrupt processing
206 * @ATH_DBG_REGULATORY: regulatory processing
207 * @ATH_DBG_ANI: adaptive noise immunitive processing
208 * @ATH_DBG_XMIT: basic xmit operation
209 * @ATH_DBG_BEACON: beacon handling
210 * @ATH_DBG_CONFIG: configuration of the hardware
211 * @ATH_DBG_FATAL: fatal errors, this is the default, DBG_DEFAULT
212 * @ATH_DBG_PS: power save processing
213 * @ATH_DBG_HWTIMER: hardware timer handling
214 * @ATH_DBG_BTCOEX: bluetooth coexistance
215 * @ATH_DBG_BSTUCK: stuck beacons
216 * @ATH_DBG_ANY: enable all debugging
218 * The debug level is used to control the amount and type of debugging output
219 * we want to see. Each driver has its own method for enabling debugging and
220 * modifying debug level states -- but this is typically done through a
221 * module parameter 'debug' along with a respective 'debug' debugfs file
225 ATH_DBG_RESET = 0x00000001,
226 ATH_DBG_QUEUE = 0x00000002,
227 ATH_DBG_EEPROM = 0x00000004,
228 ATH_DBG_CALIBRATE = 0x00000008,
229 ATH_DBG_INTERRUPT = 0x00000010,
230 ATH_DBG_REGULATORY = 0x00000020,
231 ATH_DBG_ANI = 0x00000040,
232 ATH_DBG_XMIT = 0x00000080,
233 ATH_DBG_BEACON = 0x00000100,
234 ATH_DBG_CONFIG = 0x00000200,
235 ATH_DBG_FATAL = 0x00000400,
236 ATH_DBG_PS = 0x00000800,
237 ATH_DBG_HWTIMER = 0x00001000,
238 ATH_DBG_BTCOEX = 0x00002000,
239 ATH_DBG_WMI = 0x00004000,
240 ATH_DBG_BSTUCK = 0x00008000,
241 ATH_DBG_ANY = 0xffffffff
244 #define ATH_DBG_DEFAULT (ATH_DBG_FATAL)
246 #ifdef CONFIG_ATH_DEBUG
248 #define ath_dbg(common, dbg_mask, fmt, ...) \
251 if ((common)->debug_mask & dbg_mask) \
252 rtn = ath_printk(KERN_DEBUG, common, fmt, \
259 #define ATH_DBG_WARN(foo, arg...) WARN(foo, arg)
260 #define ATH_DBG_WARN_ON_ONCE(foo) WARN_ON_ONCE(foo)
264 static inline __attribute__ ((format (printf, 3, 4))) int
265 ath_dbg(struct ath_common *common, enum ATH_DEBUG dbg_mask,
266 const char *fmt, ...)
270 #define ATH_DBG_WARN(foo, arg...) do {} while (0)
271 #define ATH_DBG_WARN_ON_ONCE(foo) ({ \
272 int __ret_warn_once = !!(foo); \
273 unlikely(__ret_warn_once); \
276 #endif /* CONFIG_ATH_DEBUG */
278 /** Returns string describing opmode, or NULL if unknown mode. */
279 #ifdef CONFIG_ATH_DEBUG
280 const char *ath_opmode_to_string(enum nl80211_iftype opmode);
282 static inline const char *ath_opmode_to_string(enum nl80211_iftype opmode)