1 /* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */
3 Written 1998-2001 by Donald Becker.
5 Current Maintainer: Roger Luethi <rl@hellgate.ch>
7 This software may be used and distributed according to the terms of
8 the GNU General Public License (GPL), incorporated herein by reference.
9 Drivers based on or derived from this code fall under the GPL and must
10 retain the authorship, copyright and license notice. This file is not
11 a complete program and may only be used when the entire operating
12 system is licensed under the GPL.
14 This driver is designed for the VIA VT86C100A Rhine-I.
15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM
16 and management NIC 6105M).
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
24 This driver contains some changes from the original Donald Becker
25 version. He may or may not be interested in bug reports on this
26 code. You can find his versions at:
27 http://www.scyld.com/network/via-rhine.html
28 [link no longer provides useful info -jgarzik]
32 #define DRV_NAME "via-rhine"
33 #define DRV_VERSION "1.4.3"
34 #define DRV_RELDATE "2007-03-06"
37 /* A few user-configurable values.
38 These may be modified when a driver module is loaded. */
40 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
41 static int max_interrupt_work = 20;
43 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
44 Setting to > 1518 effectively disables this feature. */
45 #if defined(__alpha__) || defined(__arm__) || defined(__hppa__) \
46 || defined(CONFIG_SPARC) || defined(__ia64__) \
47 || defined(__sh__) || defined(__mips__)
48 static int rx_copybreak = 1518;
50 static int rx_copybreak;
53 /* Work-around for broken BIOSes: they are unable to get the chip back out of
54 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */
58 * In case you are looking for 'options[]' or 'full_duplex[]', they
59 * are gone. Use ethtool(8) instead.
62 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
63 The Rhine has a 64 element 8390-like hash table. */
64 static const int multicast_filter_limit = 32;
67 /* Operational parameters that are set at compile time. */
69 /* Keep the ring sizes a power of two for compile efficiency.
70 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
71 Making the Tx ring too large decreases the effectiveness of channel
72 bonding and packet priority.
73 There are no ill effects from too-large receive rings. */
74 #define TX_RING_SIZE 16
75 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
76 #define RX_RING_SIZE 64
78 /* Operational parameters that usually are not changed. */
80 /* Time in jiffies before concluding the transmitter is hung. */
81 #define TX_TIMEOUT (2*HZ)
83 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
85 #include <linux/module.h>
86 #include <linux/moduleparam.h>
87 #include <linux/kernel.h>
88 #include <linux/string.h>
89 #include <linux/timer.h>
90 #include <linux/errno.h>
91 #include <linux/ioport.h>
92 #include <linux/slab.h>
93 #include <linux/interrupt.h>
94 #include <linux/pci.h>
95 #include <linux/dma-mapping.h>
96 #include <linux/netdevice.h>
97 #include <linux/etherdevice.h>
98 #include <linux/skbuff.h>
99 #include <linux/init.h>
100 #include <linux/delay.h>
101 #include <linux/mii.h>
102 #include <linux/ethtool.h>
103 #include <linux/crc32.h>
104 #include <linux/bitops.h>
105 #include <asm/processor.h> /* Processor type for cache alignment. */
108 #include <asm/uaccess.h>
109 #include <linux/dmi.h>
111 /* These identify the driver base version and may not be removed. */
112 static char version[] __devinitdata =
113 KERN_INFO DRV_NAME ".c:v1.10-LK" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
115 /* This driver was written to use PCI memory space. Some early versions
116 of the Rhine may only work correctly with I/O space accesses. */
117 #ifdef CONFIG_VIA_RHINE_MMIO
122 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
123 MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver");
124 MODULE_LICENSE("GPL");
126 module_param(max_interrupt_work, int, 0);
127 module_param(debug, int, 0);
128 module_param(rx_copybreak, int, 0);
129 module_param(avoid_D3, bool, 0);
130 MODULE_PARM_DESC(max_interrupt_work, "VIA Rhine maximum events handled per interrupt");
131 MODULE_PARM_DESC(debug, "VIA Rhine debug level (0-7)");
132 MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames");
133 MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)");
138 I. Board Compatibility
140 This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet
143 II. Board-specific settings
145 Boards with this chip are functional only in a bus-master PCI slot.
147 Many operational settings are loaded from the EEPROM to the Config word at
148 offset 0x78. For most of these settings, this driver assumes that they are
150 If this driver is compiled to use PCI memory space operations the EEPROM
151 must be configured to enable memory ops.
153 III. Driver operation
157 This driver uses two statically allocated fixed-size descriptor lists
158 formed into rings by a branch from the final descriptor to the beginning of
159 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
161 IIIb/c. Transmit/Receive Structure
163 This driver attempts to use a zero-copy receive and transmit scheme.
165 Alas, all data buffers are required to start on a 32 bit boundary, so
166 the driver must often copy transmit packets into bounce buffers.
168 The driver allocates full frame size skbuffs for the Rx ring buffers at
169 open() time and passes the skb->data field to the chip as receive data
170 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
171 a fresh skbuff is allocated and the frame is copied to the new skbuff.
172 When the incoming frame is larger, the skbuff is passed directly up the
173 protocol stack. Buffers consumed this way are replaced by newly allocated
174 skbuffs in the last phase of rhine_rx().
176 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
177 using a full-sized skbuff for small frames vs. the copying costs of larger
178 frames. New boards are typically used in generously configured machines
179 and the underfilled buffers have negligible impact compared to the benefit of
180 a single allocation size, so the default value of zero results in never
181 copying packets. When copying is done, the cost is usually mitigated by using
182 a combined copy/checksum routine. Copying also preloads the cache, which is
183 most useful with small frames.
185 Since the VIA chips are only able to transfer data to buffers on 32 bit
186 boundaries, the IP header at offset 14 in an ethernet frame isn't
187 longword aligned for further processing. Copying these unaligned buffers
188 has the beneficial effect of 16-byte aligning the IP header.
190 IIId. Synchronization
192 The driver runs as two independent, single-threaded flows of control. One
193 is the send-packet routine, which enforces single-threaded use by the
194 dev->priv->lock spinlock. The other thread is the interrupt handler, which
195 is single threaded by the hardware and interrupt handling software.
197 The send packet thread has partial control over the Tx ring. It locks the
198 dev->priv->lock whenever it's queuing a Tx packet. If the next slot in the ring
199 is not available it stops the transmit queue by calling netif_stop_queue.
201 The interrupt handler has exclusive control over the Rx ring and records stats
202 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
203 empty by incrementing the dirty_tx mark. If at least half of the entries in
204 the Rx ring are available the transmit queue is woken up if it was stopped.
210 Preliminary VT86C100A manual from http://www.via.com.tw/
211 http://www.scyld.com/expert/100mbps.html
212 http://www.scyld.com/expert/NWay.html
213 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf
214 ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF
219 The VT86C100A manual is not reliable information.
220 The 3043 chip does not handle unaligned transmit or receive buffers, resulting
221 in significant performance degradation for bounce buffer copies on transmit
222 and unaligned IP headers on receive.
223 The chip does not pad to minimum transmit length.
228 /* This table drives the PCI probe routines. It's mostly boilerplate in all
229 of the drivers, and will likely be provided by some future kernel.
230 Note the matching code -- the first table entry matchs all 56** cards but
231 second only the 1234 card.
238 VT8231 = 0x50, /* Integrated MAC */
239 VT8233 = 0x60, /* Integrated MAC */
240 VT8235 = 0x74, /* Integrated MAC */
241 VT8237 = 0x78, /* Integrated MAC */
248 VT6105M = 0x90, /* Management adapter */
252 rqWOL = 0x0001, /* Wake-On-LAN support */
253 rqForceReset = 0x0002,
254 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */
255 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */
256 rqRhineI = 0x0100, /* See comment below */
259 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable
260 * MMIO as well as for the collision counter and the Tx FIFO underflow
261 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned.
264 /* Beware of PCI posted writes */
265 #define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0)
267 static const struct pci_device_id rhine_pci_tbl[] = {
268 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */
269 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */
270 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */
271 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */
272 { } /* terminate list */
274 MODULE_DEVICE_TABLE(pci, rhine_pci_tbl);
277 /* Offsets to the device registers. */
278 enum register_offsets {
279 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08,
281 IntrStatus=0x0C, IntrEnable=0x0E,
282 MulticastFilter0=0x10, MulticastFilter1=0x14,
283 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54,
284 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E,
285 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74,
286 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B,
287 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81,
288 StickyHW=0x83, IntrStatus2=0x84,
289 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4,
290 WOLcrClr1=0xA6, WOLcgClr=0xA7,
291 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD,
294 /* Bits in ConfigD */
296 BackOptional=0x01, BackModify=0x02,
297 BackCaptureEffect=0x04, BackRandom=0x08
301 /* Registers we check that mmio and reg are the same. */
302 static const int mmio_verify_registers[] = {
303 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD,
308 /* Bits in the interrupt status/mask registers. */
309 enum intr_status_bits {
310 IntrRxDone=0x0001, IntrRxErr=0x0004, IntrRxEmpty=0x0020,
311 IntrTxDone=0x0002, IntrTxError=0x0008, IntrTxUnderrun=0x0210,
313 IntrStatsMax=0x0080, IntrRxEarly=0x0100,
314 IntrRxOverflow=0x0400, IntrRxDropped=0x0800, IntrRxNoBuf=0x1000,
315 IntrTxAborted=0x2000, IntrLinkChange=0x4000,
317 IntrNormalSummary=0x0003, IntrAbnormalSummary=0xC260,
318 IntrTxDescRace=0x080000, /* mapped from IntrStatus2 */
319 IntrTxErrSummary=0x082218,
322 /* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */
331 /* The Rx and Tx buffer descriptors. */
334 __le32 desc_length; /* Chain flag, Buffer/frame length */
340 __le32 desc_length; /* Chain flag, Tx Config, Frame length */
345 /* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */
346 #define TXDESC 0x00e08000
348 enum rx_status_bits {
349 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F
352 /* Bits in *_desc.*_status */
353 enum desc_status_bits {
357 /* Bits in ChipCmd. */
359 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08,
360 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40,
361 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04,
362 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80,
365 struct rhine_private {
366 /* Descriptor rings */
367 struct rx_desc *rx_ring;
368 struct tx_desc *tx_ring;
369 dma_addr_t rx_ring_dma;
370 dma_addr_t tx_ring_dma;
372 /* The addresses of receive-in-place skbuffs. */
373 struct sk_buff *rx_skbuff[RX_RING_SIZE];
374 dma_addr_t rx_skbuff_dma[RX_RING_SIZE];
376 /* The saved address of a sent-in-place packet/buffer, for later free(). */
377 struct sk_buff *tx_skbuff[TX_RING_SIZE];
378 dma_addr_t tx_skbuff_dma[TX_RING_SIZE];
380 /* Tx bounce buffers (Rhine-I only) */
381 unsigned char *tx_buf[TX_RING_SIZE];
382 unsigned char *tx_bufs;
383 dma_addr_t tx_bufs_dma;
385 struct pci_dev *pdev;
387 struct net_device *dev;
388 struct napi_struct napi;
389 struct net_device_stats stats;
392 /* Frequently used values: keep some adjacent for cache effect. */
394 struct rx_desc *rx_head_desc;
395 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
396 unsigned int cur_tx, dirty_tx;
397 unsigned int rx_buf_sz; /* Based on MTU+slack. */
400 u8 tx_thresh, rx_thresh;
402 struct mii_if_info mii_if;
406 static int mdio_read(struct net_device *dev, int phy_id, int location);
407 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
408 static int rhine_open(struct net_device *dev);
409 static void rhine_tx_timeout(struct net_device *dev);
410 static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev);
411 static irqreturn_t rhine_interrupt(int irq, void *dev_instance);
412 static void rhine_tx(struct net_device *dev);
413 static int rhine_rx(struct net_device *dev, int limit);
414 static void rhine_error(struct net_device *dev, int intr_status);
415 static void rhine_set_rx_mode(struct net_device *dev);
416 static struct net_device_stats *rhine_get_stats(struct net_device *dev);
417 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
418 static const struct ethtool_ops netdev_ethtool_ops;
419 static int rhine_close(struct net_device *dev);
420 static void rhine_shutdown (struct pci_dev *pdev);
422 #define RHINE_WAIT_FOR(condition) do { \
424 while (!(condition) && --i) \
426 if (debug > 1 && i < 512) \
427 printk(KERN_INFO "%s: %4d cycles used @ %s:%d\n", \
428 DRV_NAME, 1024-i, __func__, __LINE__); \
431 static inline u32 get_intr_status(struct net_device *dev)
433 struct rhine_private *rp = netdev_priv(dev);
434 void __iomem *ioaddr = rp->base;
437 intr_status = ioread16(ioaddr + IntrStatus);
438 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */
439 if (rp->quirks & rqStatusWBRace)
440 intr_status |= ioread8(ioaddr + IntrStatus2) << 16;
445 * Get power related registers into sane state.
446 * Notify user about past WOL event.
448 static void rhine_power_init(struct net_device *dev)
450 struct rhine_private *rp = netdev_priv(dev);
451 void __iomem *ioaddr = rp->base;
454 if (rp->quirks & rqWOL) {
455 /* Make sure chip is in power state D0 */
456 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW);
458 /* Disable "force PME-enable" */
459 iowrite8(0x80, ioaddr + WOLcgClr);
461 /* Clear power-event config bits (WOL) */
462 iowrite8(0xFF, ioaddr + WOLcrClr);
463 /* More recent cards can manage two additional patterns */
464 if (rp->quirks & rq6patterns)
465 iowrite8(0x03, ioaddr + WOLcrClr1);
467 /* Save power-event status bits */
468 wolstat = ioread8(ioaddr + PwrcsrSet);
469 if (rp->quirks & rq6patterns)
470 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8;
472 /* Clear power-event status bits */
473 iowrite8(0xFF, ioaddr + PwrcsrClr);
474 if (rp->quirks & rq6patterns)
475 iowrite8(0x03, ioaddr + PwrcsrClr1);
481 reason = "Magic packet";
484 reason = "Link went up";
487 reason = "Link went down";
490 reason = "Unicast packet";
493 reason = "Multicast/broadcast packet";
498 printk(KERN_INFO "%s: Woke system up. Reason: %s.\n",
504 static void rhine_chip_reset(struct net_device *dev)
506 struct rhine_private *rp = netdev_priv(dev);
507 void __iomem *ioaddr = rp->base;
509 iowrite8(Cmd1Reset, ioaddr + ChipCmd1);
512 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) {
513 printk(KERN_INFO "%s: Reset not complete yet. "
514 "Trying harder.\n", DRV_NAME);
517 if (rp->quirks & rqForceReset)
518 iowrite8(0x40, ioaddr + MiscCmd);
520 /* Reset can take somewhat longer (rare) */
521 RHINE_WAIT_FOR(!(ioread8(ioaddr + ChipCmd1) & Cmd1Reset));
525 printk(KERN_INFO "%s: Reset %s.\n", dev->name,
526 (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) ?
527 "failed" : "succeeded");
531 static void enable_mmio(long pioaddr, u32 quirks)
534 if (quirks & rqRhineI) {
535 /* More recent docs say that this bit is reserved ... */
536 n = inb(pioaddr + ConfigA) | 0x20;
537 outb(n, pioaddr + ConfigA);
539 n = inb(pioaddr + ConfigD) | 0x80;
540 outb(n, pioaddr + ConfigD);
546 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM
547 * (plus 0x6C for Rhine-I/II)
549 static void __devinit rhine_reload_eeprom(long pioaddr, struct net_device *dev)
551 struct rhine_private *rp = netdev_priv(dev);
552 void __iomem *ioaddr = rp->base;
554 outb(0x20, pioaddr + MACRegEEcsr);
555 RHINE_WAIT_FOR(!(inb(pioaddr + MACRegEEcsr) & 0x20));
559 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable
560 * MMIO. If reloading EEPROM was done first this could be avoided, but
561 * it is not known if that still works with the "win98-reboot" problem.
563 enable_mmio(pioaddr, rp->quirks);
566 /* Turn off EEPROM-controlled wake-up (magic packet) */
567 if (rp->quirks & rqWOL)
568 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA);
572 #ifdef CONFIG_NET_POLL_CONTROLLER
573 static void rhine_poll(struct net_device *dev)
575 disable_irq(dev->irq);
576 rhine_interrupt(dev->irq, (void *)dev);
577 enable_irq(dev->irq);
581 static int rhine_napipoll(struct napi_struct *napi, int budget)
583 struct rhine_private *rp = container_of(napi, struct rhine_private, napi);
584 struct net_device *dev = rp->dev;
585 void __iomem *ioaddr = rp->base;
588 work_done = rhine_rx(dev, budget);
590 if (work_done < budget) {
591 netif_rx_complete(dev, napi);
593 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
594 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
595 IntrTxDone | IntrTxError | IntrTxUnderrun |
596 IntrPCIErr | IntrStatsMax | IntrLinkChange,
597 ioaddr + IntrEnable);
602 static void __devinit rhine_hw_init(struct net_device *dev, long pioaddr)
604 struct rhine_private *rp = netdev_priv(dev);
606 /* Reset the chip to erase previous misconfiguration. */
607 rhine_chip_reset(dev);
609 /* Rhine-I needs extra time to recuperate before EEPROM reload */
610 if (rp->quirks & rqRhineI)
613 /* Reload EEPROM controlled bytes cleared by soft reset */
614 rhine_reload_eeprom(pioaddr, dev);
617 static int __devinit rhine_init_one(struct pci_dev *pdev,
618 const struct pci_device_id *ent)
620 struct net_device *dev;
621 struct rhine_private *rp;
626 void __iomem *ioaddr;
634 DECLARE_MAC_BUF(mac);
636 /* when built into the kernel, we only print version if device is found */
638 static int printed_version;
639 if (!printed_version++)
647 if (pdev->revision < VTunknown0) {
651 else if (pdev->revision >= VT6102) {
652 quirks = rqWOL | rqForceReset;
653 if (pdev->revision < VT6105) {
655 quirks |= rqStatusWBRace; /* Rhine-II exclusive */
658 phy_id = 1; /* Integrated PHY, phy_id fixed to 1 */
659 if (pdev->revision >= VT6105_B0)
660 quirks |= rq6patterns;
661 if (pdev->revision < VT6105M)
664 name = "Rhine III (Management Adapter)";
668 rc = pci_enable_device(pdev);
672 /* this should always be supported */
673 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
675 printk(KERN_ERR "32-bit PCI DMA addresses not supported by "
681 if ((pci_resource_len(pdev, 0) < io_size) ||
682 (pci_resource_len(pdev, 1) < io_size)) {
684 printk(KERN_ERR "Insufficient PCI resources, aborting\n");
688 pioaddr = pci_resource_start(pdev, 0);
689 memaddr = pci_resource_start(pdev, 1);
691 pci_set_master(pdev);
693 dev = alloc_etherdev(sizeof(struct rhine_private));
696 printk(KERN_ERR "alloc_etherdev failed\n");
699 SET_NETDEV_DEV(dev, &pdev->dev);
701 rp = netdev_priv(dev);
704 rp->pioaddr = pioaddr;
707 rc = pci_request_regions(pdev, DRV_NAME);
709 goto err_out_free_netdev;
711 ioaddr = pci_iomap(pdev, bar, io_size);
714 printk(KERN_ERR "ioremap failed for device %s, region 0x%X "
715 "@ 0x%lX\n", pci_name(pdev), io_size, memaddr);
716 goto err_out_free_res;
720 enable_mmio(pioaddr, quirks);
722 /* Check that selected MMIO registers match the PIO ones */
724 while (mmio_verify_registers[i]) {
725 int reg = mmio_verify_registers[i++];
726 unsigned char a = inb(pioaddr+reg);
727 unsigned char b = readb(ioaddr+reg);
730 printk(KERN_ERR "MMIO do not match PIO [%02x] "
731 "(%02x != %02x)\n", reg, a, b);
735 #endif /* USE_MMIO */
737 dev->base_addr = (unsigned long)ioaddr;
740 /* Get chip registers into a sane state */
741 rhine_power_init(dev);
742 rhine_hw_init(dev, pioaddr);
744 for (i = 0; i < 6; i++)
745 dev->dev_addr[i] = ioread8(ioaddr + StationAddr + i);
746 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
748 if (!is_valid_ether_addr(dev->perm_addr)) {
750 printk(KERN_ERR "Invalid MAC address\n");
754 /* For Rhine-I/II, phy_id is loaded from EEPROM */
756 phy_id = ioread8(ioaddr + 0x6C);
758 dev->irq = pdev->irq;
760 spin_lock_init(&rp->lock);
761 rp->mii_if.dev = dev;
762 rp->mii_if.mdio_read = mdio_read;
763 rp->mii_if.mdio_write = mdio_write;
764 rp->mii_if.phy_id_mask = 0x1f;
765 rp->mii_if.reg_num_mask = 0x1f;
767 /* The chip-specific entries in the device structure. */
768 dev->open = rhine_open;
769 dev->hard_start_xmit = rhine_start_tx;
770 dev->stop = rhine_close;
771 dev->get_stats = rhine_get_stats;
772 dev->set_multicast_list = rhine_set_rx_mode;
773 dev->do_ioctl = netdev_ioctl;
774 dev->ethtool_ops = &netdev_ethtool_ops;
775 dev->tx_timeout = rhine_tx_timeout;
776 dev->watchdog_timeo = TX_TIMEOUT;
777 #ifdef CONFIG_NET_POLL_CONTROLLER
778 dev->poll_controller = rhine_poll;
780 netif_napi_add(dev, &rp->napi, rhine_napipoll, 64);
782 if (rp->quirks & rqRhineI)
783 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM;
785 /* dev->name not defined before register_netdev()! */
786 rc = register_netdev(dev);
790 printk(KERN_INFO "%s: VIA %s at 0x%lx, %s, IRQ %d.\n",
797 print_mac(mac, dev->dev_addr), pdev->irq);
799 pci_set_drvdata(pdev, dev);
803 int mii_status = mdio_read(dev, phy_id, 1);
804 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE;
805 mdio_write(dev, phy_id, MII_BMCR, mii_cmd);
806 if (mii_status != 0xffff && mii_status != 0x0000) {
807 rp->mii_if.advertising = mdio_read(dev, phy_id, 4);
808 printk(KERN_INFO "%s: MII PHY found at address "
809 "%d, status 0x%4.4x advertising %4.4x "
810 "Link %4.4x.\n", dev->name, phy_id,
811 mii_status, rp->mii_if.advertising,
812 mdio_read(dev, phy_id, 5));
814 /* set IFF_RUNNING */
815 if (mii_status & BMSR_LSTATUS)
816 netif_carrier_on(dev);
818 netif_carrier_off(dev);
822 rp->mii_if.phy_id = phy_id;
823 if (debug > 1 && avoid_D3)
824 printk(KERN_INFO "%s: No D3 power state at shutdown.\n",
830 pci_iounmap(pdev, ioaddr);
832 pci_release_regions(pdev);
839 static int alloc_ring(struct net_device* dev)
841 struct rhine_private *rp = netdev_priv(dev);
845 ring = pci_alloc_consistent(rp->pdev,
846 RX_RING_SIZE * sizeof(struct rx_desc) +
847 TX_RING_SIZE * sizeof(struct tx_desc),
850 printk(KERN_ERR "Could not allocate DMA memory.\n");
853 if (rp->quirks & rqRhineI) {
854 rp->tx_bufs = pci_alloc_consistent(rp->pdev,
855 PKT_BUF_SZ * TX_RING_SIZE,
857 if (rp->tx_bufs == NULL) {
858 pci_free_consistent(rp->pdev,
859 RX_RING_SIZE * sizeof(struct rx_desc) +
860 TX_RING_SIZE * sizeof(struct tx_desc),
867 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc);
868 rp->rx_ring_dma = ring_dma;
869 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc);
874 static void free_ring(struct net_device* dev)
876 struct rhine_private *rp = netdev_priv(dev);
878 pci_free_consistent(rp->pdev,
879 RX_RING_SIZE * sizeof(struct rx_desc) +
880 TX_RING_SIZE * sizeof(struct tx_desc),
881 rp->rx_ring, rp->rx_ring_dma);
885 pci_free_consistent(rp->pdev, PKT_BUF_SZ * TX_RING_SIZE,
886 rp->tx_bufs, rp->tx_bufs_dma);
892 static void alloc_rbufs(struct net_device *dev)
894 struct rhine_private *rp = netdev_priv(dev);
898 rp->dirty_rx = rp->cur_rx = 0;
900 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
901 rp->rx_head_desc = &rp->rx_ring[0];
902 next = rp->rx_ring_dma;
904 /* Init the ring entries */
905 for (i = 0; i < RX_RING_SIZE; i++) {
906 rp->rx_ring[i].rx_status = 0;
907 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz);
908 next += sizeof(struct rx_desc);
909 rp->rx_ring[i].next_desc = cpu_to_le32(next);
910 rp->rx_skbuff[i] = NULL;
912 /* Mark the last entry as wrapping the ring. */
913 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma);
915 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
916 for (i = 0; i < RX_RING_SIZE; i++) {
917 struct sk_buff *skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
918 rp->rx_skbuff[i] = skb;
921 skb->dev = dev; /* Mark as being used by this device. */
923 rp->rx_skbuff_dma[i] =
924 pci_map_single(rp->pdev, skb->data, rp->rx_buf_sz,
927 rp->rx_ring[i].addr = cpu_to_le32(rp->rx_skbuff_dma[i]);
928 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn);
930 rp->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
933 static void free_rbufs(struct net_device* dev)
935 struct rhine_private *rp = netdev_priv(dev);
938 /* Free all the skbuffs in the Rx queue. */
939 for (i = 0; i < RX_RING_SIZE; i++) {
940 rp->rx_ring[i].rx_status = 0;
941 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
942 if (rp->rx_skbuff[i]) {
943 pci_unmap_single(rp->pdev,
944 rp->rx_skbuff_dma[i],
945 rp->rx_buf_sz, PCI_DMA_FROMDEVICE);
946 dev_kfree_skb(rp->rx_skbuff[i]);
948 rp->rx_skbuff[i] = NULL;
952 static void alloc_tbufs(struct net_device* dev)
954 struct rhine_private *rp = netdev_priv(dev);
958 rp->dirty_tx = rp->cur_tx = 0;
959 next = rp->tx_ring_dma;
960 for (i = 0; i < TX_RING_SIZE; i++) {
961 rp->tx_skbuff[i] = NULL;
962 rp->tx_ring[i].tx_status = 0;
963 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
964 next += sizeof(struct tx_desc);
965 rp->tx_ring[i].next_desc = cpu_to_le32(next);
966 if (rp->quirks & rqRhineI)
967 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ];
969 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma);
973 static void free_tbufs(struct net_device* dev)
975 struct rhine_private *rp = netdev_priv(dev);
978 for (i = 0; i < TX_RING_SIZE; i++) {
979 rp->tx_ring[i].tx_status = 0;
980 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC);
981 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */
982 if (rp->tx_skbuff[i]) {
983 if (rp->tx_skbuff_dma[i]) {
984 pci_unmap_single(rp->pdev,
985 rp->tx_skbuff_dma[i],
986 rp->tx_skbuff[i]->len,
989 dev_kfree_skb(rp->tx_skbuff[i]);
991 rp->tx_skbuff[i] = NULL;
992 rp->tx_buf[i] = NULL;
996 static void rhine_check_media(struct net_device *dev, unsigned int init_media)
998 struct rhine_private *rp = netdev_priv(dev);
999 void __iomem *ioaddr = rp->base;
1001 mii_check_media(&rp->mii_if, debug, init_media);
1003 if (rp->mii_if.full_duplex)
1004 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex,
1007 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex,
1010 printk(KERN_INFO "%s: force_media %d, carrier %d\n", dev->name,
1011 rp->mii_if.force_media, netif_carrier_ok(dev));
1014 /* Called after status of force_media possibly changed */
1015 static void rhine_set_carrier(struct mii_if_info *mii)
1017 if (mii->force_media) {
1018 /* autoneg is off: Link is always assumed to be up */
1019 if (!netif_carrier_ok(mii->dev))
1020 netif_carrier_on(mii->dev);
1022 else /* Let MMI library update carrier status */
1023 rhine_check_media(mii->dev, 0);
1025 printk(KERN_INFO "%s: force_media %d, carrier %d\n",
1026 mii->dev->name, mii->force_media,
1027 netif_carrier_ok(mii->dev));
1030 static void init_registers(struct net_device *dev)
1032 struct rhine_private *rp = netdev_priv(dev);
1033 void __iomem *ioaddr = rp->base;
1036 for (i = 0; i < 6; i++)
1037 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i);
1039 /* Initialize other registers. */
1040 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */
1041 /* Configure initial FIFO thresholds. */
1042 iowrite8(0x20, ioaddr + TxConfig);
1043 rp->tx_thresh = 0x20;
1044 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */
1046 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr);
1047 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr);
1049 rhine_set_rx_mode(dev);
1051 napi_enable(&rp->napi);
1053 /* Enable interrupts by setting the interrupt mask. */
1054 iowrite16(IntrRxDone | IntrRxErr | IntrRxEmpty| IntrRxOverflow |
1055 IntrRxDropped | IntrRxNoBuf | IntrTxAborted |
1056 IntrTxDone | IntrTxError | IntrTxUnderrun |
1057 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1058 ioaddr + IntrEnable);
1060 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8),
1062 rhine_check_media(dev, 1);
1065 /* Enable MII link status auto-polling (required for IntrLinkChange) */
1066 static void rhine_enable_linkmon(void __iomem *ioaddr)
1068 iowrite8(0, ioaddr + MIICmd);
1069 iowrite8(MII_BMSR, ioaddr + MIIRegAddr);
1070 iowrite8(0x80, ioaddr + MIICmd);
1072 RHINE_WAIT_FOR((ioread8(ioaddr + MIIRegAddr) & 0x20));
1074 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr);
1077 /* Disable MII link status auto-polling (required for MDIO access) */
1078 static void rhine_disable_linkmon(void __iomem *ioaddr, u32 quirks)
1080 iowrite8(0, ioaddr + MIICmd);
1082 if (quirks & rqRhineI) {
1083 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR
1085 /* Can be called from ISR. Evil. */
1088 /* 0x80 must be set immediately before turning it off */
1089 iowrite8(0x80, ioaddr + MIICmd);
1091 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x20);
1093 /* Heh. Now clear 0x80 again. */
1094 iowrite8(0, ioaddr + MIICmd);
1097 RHINE_WAIT_FOR(ioread8(ioaddr + MIIRegAddr) & 0x80);
1100 /* Read and write over the MII Management Data I/O (MDIO) interface. */
1102 static int mdio_read(struct net_device *dev, int phy_id, int regnum)
1104 struct rhine_private *rp = netdev_priv(dev);
1105 void __iomem *ioaddr = rp->base;
1108 rhine_disable_linkmon(ioaddr, rp->quirks);
1110 /* rhine_disable_linkmon already cleared MIICmd */
1111 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1112 iowrite8(regnum, ioaddr + MIIRegAddr);
1113 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */
1114 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x40));
1115 result = ioread16(ioaddr + MIIData);
1117 rhine_enable_linkmon(ioaddr);
1121 static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value)
1123 struct rhine_private *rp = netdev_priv(dev);
1124 void __iomem *ioaddr = rp->base;
1126 rhine_disable_linkmon(ioaddr, rp->quirks);
1128 /* rhine_disable_linkmon already cleared MIICmd */
1129 iowrite8(phy_id, ioaddr + MIIPhyAddr);
1130 iowrite8(regnum, ioaddr + MIIRegAddr);
1131 iowrite16(value, ioaddr + MIIData);
1132 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */
1133 RHINE_WAIT_FOR(!(ioread8(ioaddr + MIICmd) & 0x20));
1135 rhine_enable_linkmon(ioaddr);
1138 static int rhine_open(struct net_device *dev)
1140 struct rhine_private *rp = netdev_priv(dev);
1141 void __iomem *ioaddr = rp->base;
1144 rc = request_irq(rp->pdev->irq, &rhine_interrupt, IRQF_SHARED, dev->name,
1150 printk(KERN_DEBUG "%s: rhine_open() irq %d.\n",
1151 dev->name, rp->pdev->irq);
1153 rc = alloc_ring(dev);
1155 free_irq(rp->pdev->irq, dev);
1160 rhine_chip_reset(dev);
1161 init_registers(dev);
1163 printk(KERN_DEBUG "%s: Done rhine_open(), status %4.4x "
1164 "MII status: %4.4x.\n",
1165 dev->name, ioread16(ioaddr + ChipCmd),
1166 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1168 netif_start_queue(dev);
1173 static void rhine_tx_timeout(struct net_device *dev)
1175 struct rhine_private *rp = netdev_priv(dev);
1176 void __iomem *ioaddr = rp->base;
1178 printk(KERN_WARNING "%s: Transmit timed out, status %4.4x, PHY status "
1179 "%4.4x, resetting...\n",
1180 dev->name, ioread16(ioaddr + IntrStatus),
1181 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR));
1183 /* protect against concurrent rx interrupts */
1184 disable_irq(rp->pdev->irq);
1186 napi_disable(&rp->napi);
1188 spin_lock(&rp->lock);
1190 /* clear all descriptors */
1196 /* Reinitialize the hardware. */
1197 rhine_chip_reset(dev);
1198 init_registers(dev);
1200 spin_unlock(&rp->lock);
1201 enable_irq(rp->pdev->irq);
1203 dev->trans_start = jiffies;
1204 rp->stats.tx_errors++;
1205 netif_wake_queue(dev);
1208 static int rhine_start_tx(struct sk_buff *skb, struct net_device *dev)
1210 struct rhine_private *rp = netdev_priv(dev);
1211 void __iomem *ioaddr = rp->base;
1214 /* Caution: the write order is important here, set the field
1215 with the "ownership" bits last. */
1217 /* Calculate the next Tx descriptor entry. */
1218 entry = rp->cur_tx % TX_RING_SIZE;
1220 if (skb_padto(skb, ETH_ZLEN))
1223 rp->tx_skbuff[entry] = skb;
1225 if ((rp->quirks & rqRhineI) &&
1226 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) {
1227 /* Must use alignment buffer. */
1228 if (skb->len > PKT_BUF_SZ) {
1229 /* packet too long, drop it */
1231 rp->tx_skbuff[entry] = NULL;
1232 rp->stats.tx_dropped++;
1236 /* Padding is not copied and so must be redone. */
1237 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]);
1238 if (skb->len < ETH_ZLEN)
1239 memset(rp->tx_buf[entry] + skb->len, 0,
1240 ETH_ZLEN - skb->len);
1241 rp->tx_skbuff_dma[entry] = 0;
1242 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma +
1243 (rp->tx_buf[entry] -
1246 rp->tx_skbuff_dma[entry] =
1247 pci_map_single(rp->pdev, skb->data, skb->len,
1249 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]);
1252 rp->tx_ring[entry].desc_length =
1253 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN));
1256 spin_lock_irq(&rp->lock);
1258 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1263 /* Non-x86 Todo: explicitly flush cache lines here. */
1265 /* Wake the potentially-idle transmit channel */
1266 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1270 if (rp->cur_tx == rp->dirty_tx + TX_QUEUE_LEN)
1271 netif_stop_queue(dev);
1273 dev->trans_start = jiffies;
1275 spin_unlock_irq(&rp->lock);
1278 printk(KERN_DEBUG "%s: Transmit frame #%d queued in slot %d.\n",
1279 dev->name, rp->cur_tx-1, entry);
1284 /* The interrupt handler does all of the Rx thread work and cleans up
1285 after the Tx thread. */
1286 static irqreturn_t rhine_interrupt(int irq, void *dev_instance)
1288 struct net_device *dev = dev_instance;
1289 struct rhine_private *rp = netdev_priv(dev);
1290 void __iomem *ioaddr = rp->base;
1292 int boguscnt = max_interrupt_work;
1295 while ((intr_status = get_intr_status(dev))) {
1298 /* Acknowledge all of the current interrupt sources ASAP. */
1299 if (intr_status & IntrTxDescRace)
1300 iowrite8(0x08, ioaddr + IntrStatus2);
1301 iowrite16(intr_status & 0xffff, ioaddr + IntrStatus);
1305 printk(KERN_DEBUG "%s: Interrupt, status %8.8x.\n",
1306 dev->name, intr_status);
1308 if (intr_status & (IntrRxDone | IntrRxErr | IntrRxDropped |
1309 IntrRxWakeUp | IntrRxEmpty | IntrRxNoBuf)) {
1310 iowrite16(IntrTxAborted |
1311 IntrTxDone | IntrTxError | IntrTxUnderrun |
1312 IntrPCIErr | IntrStatsMax | IntrLinkChange,
1313 ioaddr + IntrEnable);
1315 netif_rx_schedule(dev, &rp->napi);
1318 if (intr_status & (IntrTxErrSummary | IntrTxDone)) {
1319 if (intr_status & IntrTxErrSummary) {
1320 /* Avoid scavenging before Tx engine turned off */
1321 RHINE_WAIT_FOR(!(ioread8(ioaddr+ChipCmd) & CmdTxOn));
1323 ioread8(ioaddr+ChipCmd) & CmdTxOn)
1324 printk(KERN_WARNING "%s: "
1325 "rhine_interrupt() Tx engine "
1326 "still on.\n", dev->name);
1331 /* Abnormal error summary/uncommon events handlers. */
1332 if (intr_status & (IntrPCIErr | IntrLinkChange |
1333 IntrStatsMax | IntrTxError | IntrTxAborted |
1334 IntrTxUnderrun | IntrTxDescRace))
1335 rhine_error(dev, intr_status);
1337 if (--boguscnt < 0) {
1338 printk(KERN_WARNING "%s: Too much work at interrupt, "
1340 dev->name, intr_status);
1346 printk(KERN_DEBUG "%s: exiting interrupt, status=%8.8x.\n",
1347 dev->name, ioread16(ioaddr + IntrStatus));
1348 return IRQ_RETVAL(handled);
1351 /* This routine is logically part of the interrupt handler, but isolated
1353 static void rhine_tx(struct net_device *dev)
1355 struct rhine_private *rp = netdev_priv(dev);
1356 int txstatus = 0, entry = rp->dirty_tx % TX_RING_SIZE;
1358 spin_lock(&rp->lock);
1360 /* find and cleanup dirty tx descriptors */
1361 while (rp->dirty_tx != rp->cur_tx) {
1362 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status);
1364 printk(KERN_DEBUG "Tx scavenge %d status %8.8x.\n",
1366 if (txstatus & DescOwn)
1368 if (txstatus & 0x8000) {
1370 printk(KERN_DEBUG "%s: Transmit error, "
1371 "Tx status %8.8x.\n",
1372 dev->name, txstatus);
1373 rp->stats.tx_errors++;
1374 if (txstatus & 0x0400) rp->stats.tx_carrier_errors++;
1375 if (txstatus & 0x0200) rp->stats.tx_window_errors++;
1376 if (txstatus & 0x0100) rp->stats.tx_aborted_errors++;
1377 if (txstatus & 0x0080) rp->stats.tx_heartbeat_errors++;
1378 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) ||
1379 (txstatus & 0x0800) || (txstatus & 0x1000)) {
1380 rp->stats.tx_fifo_errors++;
1381 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn);
1382 break; /* Keep the skb - we try again */
1384 /* Transmitter restarted in 'abnormal' handler. */
1386 if (rp->quirks & rqRhineI)
1387 rp->stats.collisions += (txstatus >> 3) & 0x0F;
1389 rp->stats.collisions += txstatus & 0x0F;
1391 printk(KERN_DEBUG "collisions: %1.1x:%1.1x\n",
1392 (txstatus >> 3) & 0xF,
1394 rp->stats.tx_bytes += rp->tx_skbuff[entry]->len;
1395 rp->stats.tx_packets++;
1397 /* Free the original skb. */
1398 if (rp->tx_skbuff_dma[entry]) {
1399 pci_unmap_single(rp->pdev,
1400 rp->tx_skbuff_dma[entry],
1401 rp->tx_skbuff[entry]->len,
1404 dev_kfree_skb_irq(rp->tx_skbuff[entry]);
1405 rp->tx_skbuff[entry] = NULL;
1406 entry = (++rp->dirty_tx) % TX_RING_SIZE;
1408 if ((rp->cur_tx - rp->dirty_tx) < TX_QUEUE_LEN - 4)
1409 netif_wake_queue(dev);
1411 spin_unlock(&rp->lock);
1414 /* Process up to limit frames from receive ring */
1415 static int rhine_rx(struct net_device *dev, int limit)
1417 struct rhine_private *rp = netdev_priv(dev);
1419 int entry = rp->cur_rx % RX_RING_SIZE;
1422 printk(KERN_DEBUG "%s: rhine_rx(), entry %d status %8.8x.\n",
1424 le32_to_cpu(rp->rx_head_desc->rx_status));
1427 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1428 for (count = 0; count < limit; ++count) {
1429 struct rx_desc *desc = rp->rx_head_desc;
1430 u32 desc_status = le32_to_cpu(desc->rx_status);
1431 int data_size = desc_status >> 16;
1433 if (desc_status & DescOwn)
1437 printk(KERN_DEBUG "rhine_rx() status is %8.8x.\n",
1440 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) {
1441 if ((desc_status & RxWholePkt) != RxWholePkt) {
1442 printk(KERN_WARNING "%s: Oversized Ethernet "
1443 "frame spanned multiple buffers, entry "
1444 "%#x length %d status %8.8x!\n",
1445 dev->name, entry, data_size,
1447 printk(KERN_WARNING "%s: Oversized Ethernet "
1448 "frame %p vs %p.\n", dev->name,
1449 rp->rx_head_desc, &rp->rx_ring[entry]);
1450 rp->stats.rx_length_errors++;
1451 } else if (desc_status & RxErr) {
1452 /* There was a error. */
1454 printk(KERN_DEBUG "rhine_rx() Rx "
1455 "error was %8.8x.\n",
1457 rp->stats.rx_errors++;
1458 if (desc_status & 0x0030) rp->stats.rx_length_errors++;
1459 if (desc_status & 0x0048) rp->stats.rx_fifo_errors++;
1460 if (desc_status & 0x0004) rp->stats.rx_frame_errors++;
1461 if (desc_status & 0x0002) {
1462 /* this can also be updated outside the interrupt handler */
1463 spin_lock(&rp->lock);
1464 rp->stats.rx_crc_errors++;
1465 spin_unlock(&rp->lock);
1469 struct sk_buff *skb;
1470 /* Length should omit the CRC */
1471 int pkt_len = data_size - 4;
1473 /* Check if the packet is long enough to accept without
1474 copying to a minimally-sized skbuff. */
1475 if (pkt_len < rx_copybreak &&
1476 (skb = netdev_alloc_skb(dev, pkt_len + NET_IP_ALIGN)) != NULL) {
1477 skb_reserve(skb, NET_IP_ALIGN); /* 16 byte align the IP header */
1478 pci_dma_sync_single_for_cpu(rp->pdev,
1479 rp->rx_skbuff_dma[entry],
1481 PCI_DMA_FROMDEVICE);
1483 skb_copy_to_linear_data(skb,
1484 rp->rx_skbuff[entry]->data,
1486 skb_put(skb, pkt_len);
1487 pci_dma_sync_single_for_device(rp->pdev,
1488 rp->rx_skbuff_dma[entry],
1490 PCI_DMA_FROMDEVICE);
1492 skb = rp->rx_skbuff[entry];
1494 printk(KERN_ERR "%s: Inconsistent Rx "
1495 "descriptor chain.\n",
1499 rp->rx_skbuff[entry] = NULL;
1500 skb_put(skb, pkt_len);
1501 pci_unmap_single(rp->pdev,
1502 rp->rx_skbuff_dma[entry],
1504 PCI_DMA_FROMDEVICE);
1506 skb->protocol = eth_type_trans(skb, dev);
1507 netif_receive_skb(skb);
1508 dev->last_rx = jiffies;
1509 rp->stats.rx_bytes += pkt_len;
1510 rp->stats.rx_packets++;
1512 entry = (++rp->cur_rx) % RX_RING_SIZE;
1513 rp->rx_head_desc = &rp->rx_ring[entry];
1516 /* Refill the Rx ring buffers. */
1517 for (; rp->cur_rx - rp->dirty_rx > 0; rp->dirty_rx++) {
1518 struct sk_buff *skb;
1519 entry = rp->dirty_rx % RX_RING_SIZE;
1520 if (rp->rx_skbuff[entry] == NULL) {
1521 skb = netdev_alloc_skb(dev, rp->rx_buf_sz);
1522 rp->rx_skbuff[entry] = skb;
1524 break; /* Better luck next round. */
1525 skb->dev = dev; /* Mark as being used by this device. */
1526 rp->rx_skbuff_dma[entry] =
1527 pci_map_single(rp->pdev, skb->data,
1529 PCI_DMA_FROMDEVICE);
1530 rp->rx_ring[entry].addr = cpu_to_le32(rp->rx_skbuff_dma[entry]);
1532 rp->rx_ring[entry].rx_status = cpu_to_le32(DescOwn);
1539 * Clears the "tally counters" for CRC errors and missed frames(?).
1540 * It has been reported that some chips need a write of 0 to clear
1541 * these, for others the counters are set to 1 when written to and
1542 * instead cleared when read. So we clear them both ways ...
1544 static inline void clear_tally_counters(void __iomem *ioaddr)
1546 iowrite32(0, ioaddr + RxMissed);
1547 ioread16(ioaddr + RxCRCErrs);
1548 ioread16(ioaddr + RxMissed);
1551 static void rhine_restart_tx(struct net_device *dev) {
1552 struct rhine_private *rp = netdev_priv(dev);
1553 void __iomem *ioaddr = rp->base;
1554 int entry = rp->dirty_tx % TX_RING_SIZE;
1558 * If new errors occured, we need to sort them out before doing Tx.
1559 * In that case the ISR will be back here RSN anyway.
1561 intr_status = get_intr_status(dev);
1563 if ((intr_status & IntrTxErrSummary) == 0) {
1565 /* We know better than the chip where it should continue. */
1566 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc),
1567 ioaddr + TxRingPtr);
1569 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn,
1571 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand,
1576 /* This should never happen */
1578 printk(KERN_WARNING "%s: rhine_restart_tx() "
1579 "Another error occured %8.8x.\n",
1580 dev->name, intr_status);
1585 static void rhine_error(struct net_device *dev, int intr_status)
1587 struct rhine_private *rp = netdev_priv(dev);
1588 void __iomem *ioaddr = rp->base;
1590 spin_lock(&rp->lock);
1592 if (intr_status & IntrLinkChange)
1593 rhine_check_media(dev, 0);
1594 if (intr_status & IntrStatsMax) {
1595 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1596 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1597 clear_tally_counters(ioaddr);
1599 if (intr_status & IntrTxAborted) {
1601 printk(KERN_INFO "%s: Abort %8.8x, frame dropped.\n",
1602 dev->name, intr_status);
1604 if (intr_status & IntrTxUnderrun) {
1605 if (rp->tx_thresh < 0xE0)
1606 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1608 printk(KERN_INFO "%s: Transmitter underrun, Tx "
1609 "threshold now %2.2x.\n",
1610 dev->name, rp->tx_thresh);
1612 if (intr_status & IntrTxDescRace) {
1614 printk(KERN_INFO "%s: Tx descriptor write-back race.\n",
1617 if ((intr_status & IntrTxError) &&
1618 (intr_status & (IntrTxAborted |
1619 IntrTxUnderrun | IntrTxDescRace)) == 0) {
1620 if (rp->tx_thresh < 0xE0) {
1621 iowrite8(rp->tx_thresh += 0x20, ioaddr + TxConfig);
1624 printk(KERN_INFO "%s: Unspecified error. Tx "
1625 "threshold now %2.2x.\n",
1626 dev->name, rp->tx_thresh);
1628 if (intr_status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace |
1630 rhine_restart_tx(dev);
1632 if (intr_status & ~(IntrLinkChange | IntrStatsMax | IntrTxUnderrun |
1633 IntrTxError | IntrTxAborted | IntrNormalSummary |
1636 printk(KERN_ERR "%s: Something Wicked happened! "
1637 "%8.8x.\n", dev->name, intr_status);
1640 spin_unlock(&rp->lock);
1643 static struct net_device_stats *rhine_get_stats(struct net_device *dev)
1645 struct rhine_private *rp = netdev_priv(dev);
1646 void __iomem *ioaddr = rp->base;
1647 unsigned long flags;
1649 spin_lock_irqsave(&rp->lock, flags);
1650 rp->stats.rx_crc_errors += ioread16(ioaddr + RxCRCErrs);
1651 rp->stats.rx_missed_errors += ioread16(ioaddr + RxMissed);
1652 clear_tally_counters(ioaddr);
1653 spin_unlock_irqrestore(&rp->lock, flags);
1658 static void rhine_set_rx_mode(struct net_device *dev)
1660 struct rhine_private *rp = netdev_priv(dev);
1661 void __iomem *ioaddr = rp->base;
1662 u32 mc_filter[2]; /* Multicast hash filter */
1663 u8 rx_mode; /* Note: 0x02=accept runt, 0x01=accept errs */
1665 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1667 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1668 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1669 } else if ((dev->mc_count > multicast_filter_limit)
1670 || (dev->flags & IFF_ALLMULTI)) {
1671 /* Too many to match, or accept all multicasts. */
1672 iowrite32(0xffffffff, ioaddr + MulticastFilter0);
1673 iowrite32(0xffffffff, ioaddr + MulticastFilter1);
1676 struct dev_mc_list *mclist;
1678 memset(mc_filter, 0, sizeof(mc_filter));
1679 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1680 i++, mclist = mclist->next) {
1681 int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
1683 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1685 iowrite32(mc_filter[0], ioaddr + MulticastFilter0);
1686 iowrite32(mc_filter[1], ioaddr + MulticastFilter1);
1689 iowrite8(rp->rx_thresh | rx_mode, ioaddr + RxConfig);
1692 static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1694 struct rhine_private *rp = netdev_priv(dev);
1696 strcpy(info->driver, DRV_NAME);
1697 strcpy(info->version, DRV_VERSION);
1698 strcpy(info->bus_info, pci_name(rp->pdev));
1701 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1703 struct rhine_private *rp = netdev_priv(dev);
1706 spin_lock_irq(&rp->lock);
1707 rc = mii_ethtool_gset(&rp->mii_if, cmd);
1708 spin_unlock_irq(&rp->lock);
1713 static int netdev_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1715 struct rhine_private *rp = netdev_priv(dev);
1718 spin_lock_irq(&rp->lock);
1719 rc = mii_ethtool_sset(&rp->mii_if, cmd);
1720 spin_unlock_irq(&rp->lock);
1721 rhine_set_carrier(&rp->mii_if);
1726 static int netdev_nway_reset(struct net_device *dev)
1728 struct rhine_private *rp = netdev_priv(dev);
1730 return mii_nway_restart(&rp->mii_if);
1733 static u32 netdev_get_link(struct net_device *dev)
1735 struct rhine_private *rp = netdev_priv(dev);
1737 return mii_link_ok(&rp->mii_if);
1740 static u32 netdev_get_msglevel(struct net_device *dev)
1745 static void netdev_set_msglevel(struct net_device *dev, u32 value)
1750 static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1752 struct rhine_private *rp = netdev_priv(dev);
1754 if (!(rp->quirks & rqWOL))
1757 spin_lock_irq(&rp->lock);
1758 wol->supported = WAKE_PHY | WAKE_MAGIC |
1759 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1760 wol->wolopts = rp->wolopts;
1761 spin_unlock_irq(&rp->lock);
1764 static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1766 struct rhine_private *rp = netdev_priv(dev);
1767 u32 support = WAKE_PHY | WAKE_MAGIC |
1768 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */
1770 if (!(rp->quirks & rqWOL))
1773 if (wol->wolopts & ~support)
1776 spin_lock_irq(&rp->lock);
1777 rp->wolopts = wol->wolopts;
1778 spin_unlock_irq(&rp->lock);
1783 static const struct ethtool_ops netdev_ethtool_ops = {
1784 .get_drvinfo = netdev_get_drvinfo,
1785 .get_settings = netdev_get_settings,
1786 .set_settings = netdev_set_settings,
1787 .nway_reset = netdev_nway_reset,
1788 .get_link = netdev_get_link,
1789 .get_msglevel = netdev_get_msglevel,
1790 .set_msglevel = netdev_set_msglevel,
1791 .get_wol = rhine_get_wol,
1792 .set_wol = rhine_set_wol,
1795 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1797 struct rhine_private *rp = netdev_priv(dev);
1800 if (!netif_running(dev))
1803 spin_lock_irq(&rp->lock);
1804 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL);
1805 spin_unlock_irq(&rp->lock);
1806 rhine_set_carrier(&rp->mii_if);
1811 static int rhine_close(struct net_device *dev)
1813 struct rhine_private *rp = netdev_priv(dev);
1814 void __iomem *ioaddr = rp->base;
1816 spin_lock_irq(&rp->lock);
1818 netif_stop_queue(dev);
1819 napi_disable(&rp->napi);
1822 printk(KERN_DEBUG "%s: Shutting down ethercard, "
1823 "status was %4.4x.\n",
1824 dev->name, ioread16(ioaddr + ChipCmd));
1826 /* Switch to loopback mode to avoid hardware races. */
1827 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig);
1829 /* Disable interrupts by clearing the interrupt mask. */
1830 iowrite16(0x0000, ioaddr + IntrEnable);
1832 /* Stop the chip's Tx and Rx processes. */
1833 iowrite16(CmdStop, ioaddr + ChipCmd);
1835 spin_unlock_irq(&rp->lock);
1837 free_irq(rp->pdev->irq, dev);
1846 static void __devexit rhine_remove_one(struct pci_dev *pdev)
1848 struct net_device *dev = pci_get_drvdata(pdev);
1849 struct rhine_private *rp = netdev_priv(dev);
1851 unregister_netdev(dev);
1853 pci_iounmap(pdev, rp->base);
1854 pci_release_regions(pdev);
1857 pci_disable_device(pdev);
1858 pci_set_drvdata(pdev, NULL);
1861 static void rhine_shutdown (struct pci_dev *pdev)
1863 struct net_device *dev = pci_get_drvdata(pdev);
1864 struct rhine_private *rp = netdev_priv(dev);
1865 void __iomem *ioaddr = rp->base;
1867 if (!(rp->quirks & rqWOL))
1868 return; /* Nothing to do for non-WOL adapters */
1870 rhine_power_init(dev);
1872 /* Make sure we use pattern 0, 1 and not 4, 5 */
1873 if (rp->quirks & rq6patterns)
1874 iowrite8(0x04, ioaddr + WOLcgClr);
1876 if (rp->wolopts & WAKE_MAGIC) {
1877 iowrite8(WOLmagic, ioaddr + WOLcrSet);
1879 * Turn EEPROM-controlled wake-up back on -- some hardware may
1880 * not cooperate otherwise.
1882 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA);
1885 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST))
1886 iowrite8(WOLbmcast, ioaddr + WOLcgSet);
1888 if (rp->wolopts & WAKE_PHY)
1889 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet);
1891 if (rp->wolopts & WAKE_UCAST)
1892 iowrite8(WOLucast, ioaddr + WOLcrSet);
1895 /* Enable legacy WOL (for old motherboards) */
1896 iowrite8(0x01, ioaddr + PwcfgSet);
1897 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW);
1900 /* Hit power state D3 (sleep) */
1902 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW);
1904 /* TODO: Check use of pci_enable_wake() */
1909 static int rhine_suspend(struct pci_dev *pdev, pm_message_t state)
1911 struct net_device *dev = pci_get_drvdata(pdev);
1912 struct rhine_private *rp = netdev_priv(dev);
1913 unsigned long flags;
1915 if (!netif_running(dev))
1918 napi_disable(&rp->napi);
1920 netif_device_detach(dev);
1921 pci_save_state(pdev);
1923 spin_lock_irqsave(&rp->lock, flags);
1924 rhine_shutdown(pdev);
1925 spin_unlock_irqrestore(&rp->lock, flags);
1927 free_irq(dev->irq, dev);
1931 static int rhine_resume(struct pci_dev *pdev)
1933 struct net_device *dev = pci_get_drvdata(pdev);
1934 struct rhine_private *rp = netdev_priv(dev);
1935 unsigned long flags;
1938 if (!netif_running(dev))
1941 if (request_irq(dev->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev))
1942 printk(KERN_ERR "via-rhine %s: request_irq failed\n", dev->name);
1944 ret = pci_set_power_state(pdev, PCI_D0);
1946 printk(KERN_INFO "%s: Entering power state D0 %s (%d).\n",
1947 dev->name, ret ? "failed" : "succeeded", ret);
1949 pci_restore_state(pdev);
1951 spin_lock_irqsave(&rp->lock, flags);
1953 enable_mmio(rp->pioaddr, rp->quirks);
1955 rhine_power_init(dev);
1960 init_registers(dev);
1961 spin_unlock_irqrestore(&rp->lock, flags);
1963 netif_device_attach(dev);
1967 #endif /* CONFIG_PM */
1969 static struct pci_driver rhine_driver = {
1971 .id_table = rhine_pci_tbl,
1972 .probe = rhine_init_one,
1973 .remove = __devexit_p(rhine_remove_one),
1975 .suspend = rhine_suspend,
1976 .resume = rhine_resume,
1977 #endif /* CONFIG_PM */
1978 .shutdown = rhine_shutdown,
1981 static struct dmi_system_id __initdata rhine_dmi_table[] = {
1985 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."),
1986 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
1992 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"),
1993 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"),
1999 static int __init rhine_init(void)
2001 /* when a module, this is printed whether or not devices are found in probe */
2005 if (dmi_check_system(rhine_dmi_table)) {
2006 /* these BIOSes fail at PXE boot if chip is in D3 */
2008 printk(KERN_WARNING "%s: Broken BIOS detected, avoid_D3 "
2013 printk(KERN_INFO "%s: avoid_D3 set.\n", DRV_NAME);
2015 return pci_register_driver(&rhine_driver);
2019 static void __exit rhine_cleanup(void)
2021 pci_unregister_driver(&rhine_driver);
2025 module_init(rhine_init);
2026 module_exit(rhine_cleanup);