2 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * version 2 as published by the Free Software Foundation.
10 #include <linux/signal.h>
11 #include <linux/slab.h>
12 #include <linux/module.h>
13 #include <linux/netdevice.h>
14 #include <linux/etherdevice.h>
15 #include <linux/mii.h>
16 #include <linux/ethtool.h>
17 #include <linux/usb.h>
18 #include <linux/crc32.h>
19 #include <linux/if_vlan.h>
20 #include <linux/uaccess.h>
21 #include <linux/list.h>
23 #include <linux/ipv6.h>
24 #include <net/ip6_checksum.h>
26 /* Version Information */
27 #define DRIVER_VERSION "v1.06.0 (2014/03/03)"
28 #define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
29 #define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
30 #define MODULENAME "r8152"
32 #define R8152_PHY_ID 32
34 #define PLA_IDR 0xc000
35 #define PLA_RCR 0xc010
36 #define PLA_RMS 0xc016
37 #define PLA_RXFIFO_CTRL0 0xc0a0
38 #define PLA_RXFIFO_CTRL1 0xc0a4
39 #define PLA_RXFIFO_CTRL2 0xc0a8
40 #define PLA_FMC 0xc0b4
41 #define PLA_CFG_WOL 0xc0b6
42 #define PLA_TEREDO_CFG 0xc0bc
43 #define PLA_MAR 0xcd00
44 #define PLA_BACKUP 0xd000
45 #define PAL_BDC_CR 0xd1a0
46 #define PLA_TEREDO_TIMER 0xd2cc
47 #define PLA_REALWOW_TIMER 0xd2e8
48 #define PLA_LEDSEL 0xdd90
49 #define PLA_LED_FEATURE 0xdd92
50 #define PLA_PHYAR 0xde00
51 #define PLA_BOOT_CTRL 0xe004
52 #define PLA_GPHY_INTR_IMR 0xe022
53 #define PLA_EEE_CR 0xe040
54 #define PLA_EEEP_CR 0xe080
55 #define PLA_MAC_PWR_CTRL 0xe0c0
56 #define PLA_MAC_PWR_CTRL2 0xe0ca
57 #define PLA_MAC_PWR_CTRL3 0xe0cc
58 #define PLA_MAC_PWR_CTRL4 0xe0ce
59 #define PLA_WDT6_CTRL 0xe428
60 #define PLA_TCR0 0xe610
61 #define PLA_TCR1 0xe612
62 #define PLA_MTPS 0xe615
63 #define PLA_TXFIFO_CTRL 0xe618
64 #define PLA_RSTTALLY 0xe800
66 #define PLA_CRWECR 0xe81c
67 #define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */
68 #define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */
69 #define PLA_CONFIG5 0xe822
70 #define PLA_PHY_PWR 0xe84c
71 #define PLA_OOB_CTRL 0xe84f
72 #define PLA_CPCR 0xe854
73 #define PLA_MISC_0 0xe858
74 #define PLA_MISC_1 0xe85a
75 #define PLA_OCP_GPHY_BASE 0xe86c
76 #define PLA_TALLYCNT 0xe890
77 #define PLA_SFF_STS_7 0xe8de
78 #define PLA_PHYSTATUS 0xe908
79 #define PLA_BP_BA 0xfc26
80 #define PLA_BP_0 0xfc28
81 #define PLA_BP_1 0xfc2a
82 #define PLA_BP_2 0xfc2c
83 #define PLA_BP_3 0xfc2e
84 #define PLA_BP_4 0xfc30
85 #define PLA_BP_5 0xfc32
86 #define PLA_BP_6 0xfc34
87 #define PLA_BP_7 0xfc36
88 #define PLA_BP_EN 0xfc38
90 #define USB_U2P3_CTRL 0xb460
91 #define USB_DEV_STAT 0xb808
92 #define USB_USB_CTRL 0xd406
93 #define USB_PHY_CTRL 0xd408
94 #define USB_TX_AGG 0xd40a
95 #define USB_RX_BUF_TH 0xd40c
96 #define USB_USB_TIMER 0xd428
97 #define USB_RX_EARLY_AGG 0xd42c
98 #define USB_PM_CTRL_STATUS 0xd432
99 #define USB_TX_DMA 0xd434
100 #define USB_TOLERANCE 0xd490
101 #define USB_LPM_CTRL 0xd41a
102 #define USB_UPS_CTRL 0xd800
103 #define USB_MISC_0 0xd81a
104 #define USB_POWER_CUT 0xd80a
105 #define USB_AFE_CTRL2 0xd824
106 #define USB_WDT11_CTRL 0xe43c
107 #define USB_BP_BA 0xfc26
108 #define USB_BP_0 0xfc28
109 #define USB_BP_1 0xfc2a
110 #define USB_BP_2 0xfc2c
111 #define USB_BP_3 0xfc2e
112 #define USB_BP_4 0xfc30
113 #define USB_BP_5 0xfc32
114 #define USB_BP_6 0xfc34
115 #define USB_BP_7 0xfc36
116 #define USB_BP_EN 0xfc38
119 #define OCP_ALDPS_CONFIG 0x2010
120 #define OCP_EEE_CONFIG1 0x2080
121 #define OCP_EEE_CONFIG2 0x2092
122 #define OCP_EEE_CONFIG3 0x2094
123 #define OCP_BASE_MII 0xa400
124 #define OCP_EEE_AR 0xa41a
125 #define OCP_EEE_DATA 0xa41c
126 #define OCP_PHY_STATUS 0xa420
127 #define OCP_POWER_CFG 0xa430
128 #define OCP_EEE_CFG 0xa432
129 #define OCP_SRAM_ADDR 0xa436
130 #define OCP_SRAM_DATA 0xa438
131 #define OCP_DOWN_SPEED 0xa442
132 #define OCP_EEE_CFG2 0xa5d0
133 #define OCP_ADC_CFG 0xbc06
136 #define SRAM_LPF_CFG 0x8012
137 #define SRAM_10M_AMP1 0x8080
138 #define SRAM_10M_AMP2 0x8082
139 #define SRAM_IMPEDANCE 0x8084
142 #define RCR_AAP 0x00000001
143 #define RCR_APM 0x00000002
144 #define RCR_AM 0x00000004
145 #define RCR_AB 0x00000008
146 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
148 /* PLA_RXFIFO_CTRL0 */
149 #define RXFIFO_THR1_NORMAL 0x00080002
150 #define RXFIFO_THR1_OOB 0x01800003
152 /* PLA_RXFIFO_CTRL1 */
153 #define RXFIFO_THR2_FULL 0x00000060
154 #define RXFIFO_THR2_HIGH 0x00000038
155 #define RXFIFO_THR2_OOB 0x0000004a
156 #define RXFIFO_THR2_NORMAL 0x00a0
158 /* PLA_RXFIFO_CTRL2 */
159 #define RXFIFO_THR3_FULL 0x00000078
160 #define RXFIFO_THR3_HIGH 0x00000048
161 #define RXFIFO_THR3_OOB 0x0000005a
162 #define RXFIFO_THR3_NORMAL 0x0110
164 /* PLA_TXFIFO_CTRL */
165 #define TXFIFO_THR_NORMAL 0x00400008
166 #define TXFIFO_THR_NORMAL2 0x01000008
169 #define FMC_FCR_MCU_EN 0x0001
172 #define EEEP_CR_EEEP_TX 0x0002
175 #define WDT6_SET_MODE 0x0010
178 #define TCR0_TX_EMPTY 0x0800
179 #define TCR0_AUTO_FIFO 0x0080
182 #define VERSION_MASK 0x7cf0
185 #define MTPS_JUMBO (12 * 1024 / 64)
186 #define MTPS_DEFAULT (6 * 1024 / 64)
189 #define TALLY_RESET 0x0001
197 #define CRWECR_NORAML 0x00
198 #define CRWECR_CONFIG 0xc0
201 #define NOW_IS_OOB 0x80
202 #define TXFIFO_EMPTY 0x20
203 #define RXFIFO_EMPTY 0x10
204 #define LINK_LIST_READY 0x02
205 #define DIS_MCU_CLROOB 0x01
206 #define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY)
209 #define RXDY_GATED_EN 0x0008
212 #define RE_INIT_LL 0x8000
213 #define MCU_BORW_EN 0x4000
216 #define CPCR_RX_VLAN 0x0040
219 #define MAGIC_EN 0x0001
222 #define TEREDO_SEL 0x8000
223 #define TEREDO_WAKE_MASK 0x7f00
224 #define TEREDO_RS_EVENT_MASK 0x00fe
225 #define OOB_TEREDO_EN 0x0001
228 #define ALDPS_PROXY_MODE 0x0001
231 #define LINK_ON_WAKE_EN 0x0010
232 #define LINK_OFF_WAKE_EN 0x0008
235 #define BWF_EN 0x0040
236 #define MWF_EN 0x0020
237 #define UWF_EN 0x0010
238 #define LAN_WAKE_EN 0x0002
240 /* PLA_LED_FEATURE */
241 #define LED_MODE_MASK 0x0700
244 #define TX_10M_IDLE_EN 0x0080
245 #define PFM_PWM_SWITCH 0x0040
247 /* PLA_MAC_PWR_CTRL */
248 #define D3_CLK_GATED_EN 0x00004000
249 #define MCU_CLK_RATIO 0x07010f07
250 #define MCU_CLK_RATIO_MASK 0x0f0f0f0f
251 #define ALDPS_SPDWN_RATIO 0x0f87
253 /* PLA_MAC_PWR_CTRL2 */
254 #define EEE_SPDWN_RATIO 0x8007
256 /* PLA_MAC_PWR_CTRL3 */
257 #define PKT_AVAIL_SPDWN_EN 0x0100
258 #define SUSPEND_SPDWN_EN 0x0004
259 #define U1U2_SPDWN_EN 0x0002
260 #define L1_SPDWN_EN 0x0001
262 /* PLA_MAC_PWR_CTRL4 */
263 #define PWRSAVE_SPDWN_EN 0x1000
264 #define RXDV_SPDWN_EN 0x0800
265 #define TX10MIDLE_EN 0x0100
266 #define TP100_SPDWN_EN 0x0020
267 #define TP500_SPDWN_EN 0x0010
268 #define TP1000_SPDWN_EN 0x0008
269 #define EEE_SPDWN_EN 0x0001
271 /* PLA_GPHY_INTR_IMR */
272 #define GPHY_STS_MSK 0x0001
273 #define SPEED_DOWN_MSK 0x0002
274 #define SPDWN_RXDV_MSK 0x0004
275 #define SPDWN_LINKCHG_MSK 0x0008
278 #define PHYAR_FLAG 0x80000000
281 #define EEE_RX_EN 0x0001
282 #define EEE_TX_EN 0x0002
285 #define AUTOLOAD_DONE 0x0002
288 #define STAT_SPEED_MASK 0x0006
289 #define STAT_SPEED_HIGH 0x0000
290 #define STAT_SPEED_FULL 0x0002
293 #define TX_AGG_MAX_THRESHOLD 0x03
296 #define RX_THR_SUPPER 0x0c350180
297 #define RX_THR_HIGH 0x7a120180
298 #define RX_THR_SLOW 0xffff0180
301 #define TEST_MODE_DISABLE 0x00000001
302 #define TX_SIZE_ADJUST1 0x00000100
305 #define POWER_CUT 0x0100
307 /* USB_PM_CTRL_STATUS */
308 #define RESUME_INDICATE 0x0001
311 #define RX_AGG_DISABLE 0x0010
314 #define U2P3_ENABLE 0x0001
317 #define PWR_EN 0x0001
318 #define PHASE2_EN 0x0008
321 #define PCUT_STATUS 0x0001
323 /* USB_RX_EARLY_AGG */
324 #define EARLY_AGG_SUPPER 0x0e832981
325 #define EARLY_AGG_HIGH 0x0e837a12
326 #define EARLY_AGG_SLOW 0x0e83ffff
329 #define TIMER11_EN 0x0001
332 #define LPM_TIMER_MASK 0x0c
333 #define LPM_TIMER_500MS 0x04 /* 500 ms */
334 #define LPM_TIMER_500US 0x0c /* 500 us */
337 #define SEN_VAL_MASK 0xf800
338 #define SEN_VAL_NORMAL 0xa000
339 #define SEL_RXIDLE 0x0100
341 /* OCP_ALDPS_CONFIG */
342 #define ENPWRSAVE 0x8000
343 #define ENPDNPS 0x0200
344 #define LINKENA 0x0100
345 #define DIS_SDSAVE 0x0010
348 #define PHY_STAT_MASK 0x0007
349 #define PHY_STAT_LAN_ON 3
350 #define PHY_STAT_PWRDN 5
353 #define EEE_CLKDIV_EN 0x8000
354 #define EN_ALDPS 0x0004
355 #define EN_10M_PLLOFF 0x0001
357 /* OCP_EEE_CONFIG1 */
358 #define RG_TXLPI_MSK_HFDUP 0x8000
359 #define RG_MATCLR_EN 0x4000
360 #define EEE_10_CAP 0x2000
361 #define EEE_NWAY_EN 0x1000
362 #define TX_QUIET_EN 0x0200
363 #define RX_QUIET_EN 0x0100
364 #define SDRISETIME 0x0010 /* bit 4 ~ 6 */
365 #define RG_RXLPI_MSK_HFDUP 0x0008
366 #define SDFALLTIME 0x0007 /* bit 0 ~ 2 */
368 /* OCP_EEE_CONFIG2 */
369 #define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */
370 #define RG_DACQUIET_EN 0x0400
371 #define RG_LDVQUIET_EN 0x0200
372 #define RG_CKRSEL 0x0020
373 #define RG_EEEPRG_EN 0x0010
375 /* OCP_EEE_CONFIG3 */
376 #define FST_SNR_EYE_R 0x1500 /* bit 7 ~ 15 */
377 #define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */
378 #define MSK_PH 0x0006 /* bit 0 ~ 3 */
381 /* bit[15:14] function */
382 #define FUN_ADDR 0x0000
383 #define FUN_DATA 0x4000
384 /* bit[4:0] device addr */
385 #define DEVICE_ADDR 0x0007
388 #define EEE_ADDR 0x003C
389 #define EEE_DATA 0x0002
392 #define CTAP_SHORT_EN 0x0040
393 #define EEE10_EN 0x0010
396 #define EN_10M_BGOFF 0x0080
399 #define MY1000_EEE 0x0004
400 #define MY100_EEE 0x0002
403 #define CKADSEL_L 0x0100
404 #define ADC_EN 0x0080
405 #define EN_EMI_L 0x0040
408 #define LPF_AUTO_TUNE 0x8000
411 #define GDAC_IB_UPALL 0x0008
414 #define AMP_DN 0x0200
417 #define RX_DRIVING_MASK 0x6000
419 enum rtl_register_content {
427 #define RTL8152_MAX_TX 10
428 #define RTL8152_MAX_RX 10
434 #define INTR_LINK 0x0004
436 #define RTL8152_REQT_READ 0xc0
437 #define RTL8152_REQT_WRITE 0x40
438 #define RTL8152_REQ_GET_REGS 0x05
439 #define RTL8152_REQ_SET_REGS 0x05
441 #define BYTE_EN_DWORD 0xff
442 #define BYTE_EN_WORD 0x33
443 #define BYTE_EN_BYTE 0x11
444 #define BYTE_EN_SIX_BYTES 0x3f
445 #define BYTE_EN_START_MASK 0x0f
446 #define BYTE_EN_END_MASK 0xf0
448 #define RTL8153_MAX_PACKET 9216 /* 9K */
449 #define RTL8153_MAX_MTU (RTL8153_MAX_PACKET - VLAN_ETH_HLEN - VLAN_HLEN)
450 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + VLAN_HLEN)
451 #define RTL8153_RMS RTL8153_MAX_PACKET
452 #define RTL8152_TX_TIMEOUT (5 * HZ)
465 /* Define these values to match your device */
466 #define VENDOR_ID_REALTEK 0x0bda
467 #define PRODUCT_ID_RTL8152 0x8152
468 #define PRODUCT_ID_RTL8153 0x8153
470 #define VENDOR_ID_SAMSUNG 0x04e8
471 #define PRODUCT_ID_SAMSUNG 0xa101
473 #define MCU_TYPE_PLA 0x0100
474 #define MCU_TYPE_USB 0x0000
476 #define REALTEK_USB_DEVICE(vend, prod) \
477 USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC)
479 struct tally_counter {
486 __le32 tx_one_collision;
487 __le32 tx_multi_collision;
497 #define RX_LEN_MASK 0x7fff
500 #define RD_UDP_CS (1 << 23)
501 #define RD_TCP_CS (1 << 22)
502 #define RD_IPV6_CS (1 << 20)
503 #define RD_IPV4_CS (1 << 19)
506 #define IPF (1 << 23) /* IP checksum fail */
507 #define UDPF (1 << 22) /* UDP checksum fail */
508 #define TCPF (1 << 21) /* TCP checksum fail */
517 #define TX_FS (1 << 31) /* First segment of a packet */
518 #define TX_LS (1 << 30) /* Final segment of a packet */
519 #define GTSENDV4 (1 << 28)
520 #define GTSENDV6 (1 << 27)
521 #define GTTCPHO_SHIFT 18
522 #define GTTCPHO_MAX 0x7fU
523 #define TX_LEN_MAX 0x3ffffU
526 #define UDP_CS (1 << 31) /* Calculate UDP/IP checksum */
527 #define TCP_CS (1 << 30) /* Calculate TCP/IP checksum */
528 #define IPV4_CS (1 << 29) /* Calculate IPv4 checksum */
529 #define IPV6_CS (1 << 28) /* Calculate IPv6 checksum */
531 #define MSS_MAX 0x7ffU
532 #define TCPHO_SHIFT 17
533 #define TCPHO_MAX 0x7ffU
539 struct list_head list;
541 struct r8152 *context;
547 struct list_head list;
549 struct r8152 *context;
558 struct usb_device *udev;
559 struct tasklet_struct tl;
560 struct usb_interface *intf;
561 struct net_device *netdev;
562 struct urb *intr_urb;
563 struct tx_agg tx_info[RTL8152_MAX_TX];
564 struct rx_agg rx_info[RTL8152_MAX_RX];
565 struct list_head rx_done, tx_free;
566 struct sk_buff_head tx_queue;
567 spinlock_t rx_lock, tx_lock;
568 struct delayed_work schedule;
569 struct mii_if_info mii;
572 void (*init)(struct r8152 *);
573 int (*enable)(struct r8152 *);
574 void (*disable)(struct r8152 *);
575 void (*up)(struct r8152 *);
576 void (*down)(struct r8152 *);
577 void (*unload)(struct r8152 *);
606 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
607 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
609 static const int multicast_filter_limit = 32;
610 static unsigned int rx_buf_sz = 16384;
612 #define RTL_LIMITED_TSO_SIZE (rx_buf_sz - sizeof(struct tx_desc) - \
613 VLAN_ETH_HLEN - VLAN_HLEN)
616 int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
621 tmp = kmalloc(size, GFP_KERNEL);
625 ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
626 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
627 value, index, tmp, size, 500);
629 memcpy(data, tmp, size);
636 int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
641 tmp = kmemdup(data, size, GFP_KERNEL);
645 ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
646 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
647 value, index, tmp, size, 500);
654 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
655 void *data, u16 type)
660 if (test_bit(RTL8152_UNPLUG, &tp->flags))
663 /* both size and indix must be 4 bytes align */
664 if ((size & 3) || !size || (index & 3) || !data)
667 if ((u32)index + (u32)size > 0xffff)
672 ret = get_registers(tp, index, type, limit, data);
680 ret = get_registers(tp, index, type, size, data);
694 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
695 u16 size, void *data, u16 type)
698 u16 byteen_start, byteen_end, byen;
701 if (test_bit(RTL8152_UNPLUG, &tp->flags))
704 /* both size and indix must be 4 bytes align */
705 if ((size & 3) || !size || (index & 3) || !data)
708 if ((u32)index + (u32)size > 0xffff)
711 byteen_start = byteen & BYTE_EN_START_MASK;
712 byteen_end = byteen & BYTE_EN_END_MASK;
714 byen = byteen_start | (byteen_start << 4);
715 ret = set_registers(tp, index, type | byen, 4, data);
728 ret = set_registers(tp, index,
729 type | BYTE_EN_DWORD,
738 ret = set_registers(tp, index,
739 type | BYTE_EN_DWORD,
751 byen = byteen_end | (byteen_end >> 4);
752 ret = set_registers(tp, index, type | byen, 4, data);
762 int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
764 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
768 int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
770 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
774 int usb_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
776 return generic_ocp_read(tp, index, size, data, MCU_TYPE_USB);
780 int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
782 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
785 static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
789 generic_ocp_read(tp, index, sizeof(data), &data, type);
791 return __le32_to_cpu(data);
794 static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
796 __le32 tmp = __cpu_to_le32(data);
798 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
801 static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
805 u8 shift = index & 2;
809 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
811 data = __le32_to_cpu(tmp);
812 data >>= (shift * 8);
818 static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
822 u16 byen = BYTE_EN_WORD;
823 u8 shift = index & 2;
829 mask <<= (shift * 8);
830 data <<= (shift * 8);
834 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
836 data |= __le32_to_cpu(tmp) & ~mask;
837 tmp = __cpu_to_le32(data);
839 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
842 static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
846 u8 shift = index & 3;
850 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
852 data = __le32_to_cpu(tmp);
853 data >>= (shift * 8);
859 static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
863 u16 byen = BYTE_EN_BYTE;
864 u8 shift = index & 3;
870 mask <<= (shift * 8);
871 data <<= (shift * 8);
875 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
877 data |= __le32_to_cpu(tmp) & ~mask;
878 tmp = __cpu_to_le32(data);
880 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
883 static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
885 u16 ocp_base, ocp_index;
887 ocp_base = addr & 0xf000;
888 if (ocp_base != tp->ocp_base) {
889 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
890 tp->ocp_base = ocp_base;
893 ocp_index = (addr & 0x0fff) | 0xb000;
894 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
897 static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
899 u16 ocp_base, ocp_index;
901 ocp_base = addr & 0xf000;
902 if (ocp_base != tp->ocp_base) {
903 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
904 tp->ocp_base = ocp_base;
907 ocp_index = (addr & 0x0fff) | 0xb000;
908 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
911 static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
913 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
916 static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
918 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
921 static void sram_write(struct r8152 *tp, u16 addr, u16 data)
923 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
924 ocp_reg_write(tp, OCP_SRAM_DATA, data);
927 static u16 sram_read(struct r8152 *tp, u16 addr)
929 ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
930 return ocp_reg_read(tp, OCP_SRAM_DATA);
933 static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
935 struct r8152 *tp = netdev_priv(netdev);
938 if (test_bit(RTL8152_UNPLUG, &tp->flags))
941 if (phy_id != R8152_PHY_ID)
944 ret = usb_autopm_get_interface(tp->intf);
948 ret = r8152_mdio_read(tp, reg);
950 usb_autopm_put_interface(tp->intf);
957 void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
959 struct r8152 *tp = netdev_priv(netdev);
961 if (test_bit(RTL8152_UNPLUG, &tp->flags))
964 if (phy_id != R8152_PHY_ID)
967 if (usb_autopm_get_interface(tp->intf) < 0)
970 r8152_mdio_write(tp, reg, val);
972 usb_autopm_put_interface(tp->intf);
976 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
978 static inline void set_ethernet_addr(struct r8152 *tp)
980 struct net_device *dev = tp->netdev;
984 if (tp->version == RTL_VER_01)
985 ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id);
987 ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id);
990 netif_notice(tp, probe, dev, "inet addr fail\n");
992 if (tp->version != RTL_VER_01) {
993 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
995 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES,
996 sizeof(node_id), node_id);
997 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
1001 memcpy(dev->dev_addr, node_id, dev->addr_len);
1002 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1006 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1008 struct r8152 *tp = netdev_priv(netdev);
1009 struct sockaddr *addr = p;
1011 if (!is_valid_ether_addr(addr->sa_data))
1012 return -EADDRNOTAVAIL;
1014 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1016 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1017 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1018 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1023 static void read_bulk_callback(struct urb *urb)
1025 struct net_device *netdev;
1026 int status = urb->status;
1039 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1042 if (!test_bit(WORK_ENABLE, &tp->flags))
1045 netdev = tp->netdev;
1047 /* When link down, the driver would cancel all bulks. */
1048 /* This avoid the re-submitting bulk */
1049 if (!netif_carrier_ok(netdev))
1052 usb_mark_last_busy(tp->udev);
1056 if (urb->actual_length < ETH_ZLEN)
1059 spin_lock(&tp->rx_lock);
1060 list_add_tail(&agg->list, &tp->rx_done);
1061 spin_unlock(&tp->rx_lock);
1062 tasklet_schedule(&tp->tl);
1065 set_bit(RTL8152_UNPLUG, &tp->flags);
1066 netif_device_detach(tp->netdev);
1069 return; /* the urb is in unlink state */
1071 if (net_ratelimit())
1072 netdev_warn(netdev, "maybe reset is needed?\n");
1075 if (net_ratelimit())
1076 netdev_warn(netdev, "Rx status %d\n", status);
1080 result = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1081 if (result == -ENODEV) {
1082 netif_device_detach(tp->netdev);
1083 } else if (result) {
1084 spin_lock(&tp->rx_lock);
1085 list_add_tail(&agg->list, &tp->rx_done);
1086 spin_unlock(&tp->rx_lock);
1087 tasklet_schedule(&tp->tl);
1091 static void write_bulk_callback(struct urb *urb)
1093 struct net_device_stats *stats;
1094 struct net_device *netdev;
1097 int status = urb->status;
1107 netdev = tp->netdev;
1108 stats = &netdev->stats;
1110 if (net_ratelimit())
1111 netdev_warn(netdev, "Tx status %d\n", status);
1112 stats->tx_errors += agg->skb_num;
1114 stats->tx_packets += agg->skb_num;
1115 stats->tx_bytes += agg->skb_len;
1118 spin_lock(&tp->tx_lock);
1119 list_add_tail(&agg->list, &tp->tx_free);
1120 spin_unlock(&tp->tx_lock);
1122 usb_autopm_put_interface_async(tp->intf);
1124 if (!netif_carrier_ok(netdev))
1127 if (!test_bit(WORK_ENABLE, &tp->flags))
1130 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1133 if (!skb_queue_empty(&tp->tx_queue))
1134 tasklet_schedule(&tp->tl);
1137 static void intr_callback(struct urb *urb)
1141 int status = urb->status;
1148 if (!test_bit(WORK_ENABLE, &tp->flags))
1151 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1155 case 0: /* success */
1157 case -ECONNRESET: /* unlink */
1159 netif_device_detach(tp->netdev);
1163 netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1165 /* -EPIPE: should clear the halt */
1167 netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1171 d = urb->transfer_buffer;
1172 if (INTR_LINK & __le16_to_cpu(d[0])) {
1173 if (!(tp->speed & LINK_STATUS)) {
1174 set_bit(RTL8152_LINK_CHG, &tp->flags);
1175 schedule_delayed_work(&tp->schedule, 0);
1178 if (tp->speed & LINK_STATUS) {
1179 set_bit(RTL8152_LINK_CHG, &tp->flags);
1180 schedule_delayed_work(&tp->schedule, 0);
1185 res = usb_submit_urb(urb, GFP_ATOMIC);
1187 netif_device_detach(tp->netdev);
1189 netif_err(tp, intr, tp->netdev,
1190 "can't resubmit intr, status %d\n", res);
1193 static inline void *rx_agg_align(void *data)
1195 return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1198 static inline void *tx_agg_align(void *data)
1200 return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1203 static void free_all_mem(struct r8152 *tp)
1207 for (i = 0; i < RTL8152_MAX_RX; i++) {
1208 usb_free_urb(tp->rx_info[i].urb);
1209 tp->rx_info[i].urb = NULL;
1211 kfree(tp->rx_info[i].buffer);
1212 tp->rx_info[i].buffer = NULL;
1213 tp->rx_info[i].head = NULL;
1216 for (i = 0; i < RTL8152_MAX_TX; i++) {
1217 usb_free_urb(tp->tx_info[i].urb);
1218 tp->tx_info[i].urb = NULL;
1220 kfree(tp->tx_info[i].buffer);
1221 tp->tx_info[i].buffer = NULL;
1222 tp->tx_info[i].head = NULL;
1225 usb_free_urb(tp->intr_urb);
1226 tp->intr_urb = NULL;
1228 kfree(tp->intr_buff);
1229 tp->intr_buff = NULL;
1232 static int alloc_all_mem(struct r8152 *tp)
1234 struct net_device *netdev = tp->netdev;
1235 struct usb_interface *intf = tp->intf;
1236 struct usb_host_interface *alt = intf->cur_altsetting;
1237 struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1242 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1244 spin_lock_init(&tp->rx_lock);
1245 spin_lock_init(&tp->tx_lock);
1246 INIT_LIST_HEAD(&tp->rx_done);
1247 INIT_LIST_HEAD(&tp->tx_free);
1248 skb_queue_head_init(&tp->tx_queue);
1250 for (i = 0; i < RTL8152_MAX_RX; i++) {
1251 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1255 if (buf != rx_agg_align(buf)) {
1257 buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL,
1263 urb = usb_alloc_urb(0, GFP_KERNEL);
1269 INIT_LIST_HEAD(&tp->rx_info[i].list);
1270 tp->rx_info[i].context = tp;
1271 tp->rx_info[i].urb = urb;
1272 tp->rx_info[i].buffer = buf;
1273 tp->rx_info[i].head = rx_agg_align(buf);
1276 for (i = 0; i < RTL8152_MAX_TX; i++) {
1277 buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
1281 if (buf != tx_agg_align(buf)) {
1283 buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL,
1289 urb = usb_alloc_urb(0, GFP_KERNEL);
1295 INIT_LIST_HEAD(&tp->tx_info[i].list);
1296 tp->tx_info[i].context = tp;
1297 tp->tx_info[i].urb = urb;
1298 tp->tx_info[i].buffer = buf;
1299 tp->tx_info[i].head = tx_agg_align(buf);
1301 list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1304 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1308 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1312 tp->intr_interval = (int)ep_intr->desc.bInterval;
1313 usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1314 tp->intr_buff, INTBUFSIZE, intr_callback,
1315 tp, tp->intr_interval);
1324 static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1326 struct tx_agg *agg = NULL;
1327 unsigned long flags;
1329 if (list_empty(&tp->tx_free))
1332 spin_lock_irqsave(&tp->tx_lock, flags);
1333 if (!list_empty(&tp->tx_free)) {
1334 struct list_head *cursor;
1336 cursor = tp->tx_free.next;
1337 list_del_init(cursor);
1338 agg = list_entry(cursor, struct tx_agg, list);
1340 spin_unlock_irqrestore(&tp->tx_lock, flags);
1345 static inline __be16 get_protocol(struct sk_buff *skb)
1349 if (skb->protocol == htons(ETH_P_8021Q))
1350 protocol = vlan_eth_hdr(skb)->h_vlan_encapsulated_proto;
1352 protocol = skb->protocol;
1358 * r8152_csum_workaround()
1359 * The hw limites the value the transport offset. When the offset is out of the
1360 * range, calculate the checksum by sw.
1362 static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1363 struct sk_buff_head *list)
1365 if (skb_shinfo(skb)->gso_size) {
1366 netdev_features_t features = tp->netdev->features;
1367 struct sk_buff_head seg_list;
1368 struct sk_buff *segs, *nskb;
1370 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1371 segs = skb_gso_segment(skb, features);
1372 if (IS_ERR(segs) || !segs)
1375 __skb_queue_head_init(&seg_list);
1381 __skb_queue_tail(&seg_list, nskb);
1384 skb_queue_splice(&seg_list, list);
1386 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1387 if (skb_checksum_help(skb) < 0)
1390 __skb_queue_head(list, skb);
1392 struct net_device_stats *stats;
1395 stats = &tp->netdev->stats;
1396 stats->tx_dropped++;
1402 * msdn_giant_send_check()
1403 * According to the document of microsoft, the TCP Pseudo Header excludes the
1404 * packet length for IPv6 TCP large packets.
1406 static int msdn_giant_send_check(struct sk_buff *skb)
1408 const struct ipv6hdr *ipv6h;
1412 ret = skb_cow_head(skb, 0);
1416 ipv6h = ipv6_hdr(skb);
1420 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1425 static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1426 struct sk_buff *skb, u32 len, u32 transport_offset)
1428 u32 mss = skb_shinfo(skb)->gso_size;
1429 u32 opts1, opts2 = 0;
1430 int ret = TX_CSUM_SUCCESS;
1432 WARN_ON_ONCE(len > TX_LEN_MAX);
1434 opts1 = len | TX_FS | TX_LS;
1437 if (transport_offset > GTTCPHO_MAX) {
1438 netif_warn(tp, tx_err, tp->netdev,
1439 "Invalid transport offset 0x%x for TSO\n",
1445 switch (get_protocol(skb)) {
1446 case htons(ETH_P_IP):
1450 case htons(ETH_P_IPV6):
1451 if (msdn_giant_send_check(skb)) {
1463 opts1 |= transport_offset << GTTCPHO_SHIFT;
1464 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1465 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1468 if (transport_offset > TCPHO_MAX) {
1469 netif_warn(tp, tx_err, tp->netdev,
1470 "Invalid transport offset 0x%x\n",
1476 switch (get_protocol(skb)) {
1477 case htons(ETH_P_IP):
1479 ip_protocol = ip_hdr(skb)->protocol;
1482 case htons(ETH_P_IPV6):
1484 ip_protocol = ipv6_hdr(skb)->nexthdr;
1488 ip_protocol = IPPROTO_RAW;
1492 if (ip_protocol == IPPROTO_TCP)
1494 else if (ip_protocol == IPPROTO_UDP)
1499 opts2 |= transport_offset << TCPHO_SHIFT;
1502 desc->opts2 = cpu_to_le32(opts2);
1503 desc->opts1 = cpu_to_le32(opts1);
1509 static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1511 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1515 __skb_queue_head_init(&skb_head);
1516 spin_lock(&tx_queue->lock);
1517 skb_queue_splice_init(tx_queue, &skb_head);
1518 spin_unlock(&tx_queue->lock);
1520 tx_data = agg->head;
1521 agg->skb_num = agg->skb_len = 0;
1524 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1525 struct tx_desc *tx_desc;
1526 struct sk_buff *skb;
1530 skb = __skb_dequeue(&skb_head);
1534 len = skb->len + sizeof(*tx_desc);
1537 __skb_queue_head(&skb_head, skb);
1541 tx_data = tx_agg_align(tx_data);
1542 tx_desc = (struct tx_desc *)tx_data;
1544 offset = (u32)skb_transport_offset(skb);
1546 if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1547 r8152_csum_workaround(tp, skb, &skb_head);
1551 tx_data += sizeof(*tx_desc);
1554 if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1555 struct net_device_stats *stats = &tp->netdev->stats;
1557 stats->tx_dropped++;
1558 dev_kfree_skb_any(skb);
1559 tx_data -= sizeof(*tx_desc);
1564 agg->skb_len += len;
1567 dev_kfree_skb_any(skb);
1569 remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1572 if (!skb_queue_empty(&skb_head)) {
1573 spin_lock(&tx_queue->lock);
1574 skb_queue_splice(&skb_head, tx_queue);
1575 spin_unlock(&tx_queue->lock);
1578 netif_tx_lock(tp->netdev);
1580 if (netif_queue_stopped(tp->netdev) &&
1581 skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1582 netif_wake_queue(tp->netdev);
1584 netif_tx_unlock(tp->netdev);
1586 ret = usb_autopm_get_interface_async(tp->intf);
1590 usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1591 agg->head, (int)(tx_data - (u8 *)agg->head),
1592 (usb_complete_t)write_bulk_callback, agg);
1594 ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1596 usb_autopm_put_interface_async(tp->intf);
1602 static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1604 u8 checksum = CHECKSUM_NONE;
1607 if (tp->version == RTL_VER_01)
1610 opts2 = le32_to_cpu(rx_desc->opts2);
1611 opts3 = le32_to_cpu(rx_desc->opts3);
1613 if (opts2 & RD_IPV4_CS) {
1615 checksum = CHECKSUM_NONE;
1616 else if ((opts2 & RD_UDP_CS) && (opts3 & UDPF))
1617 checksum = CHECKSUM_NONE;
1618 else if ((opts2 & RD_TCP_CS) && (opts3 & TCPF))
1619 checksum = CHECKSUM_NONE;
1621 checksum = CHECKSUM_UNNECESSARY;
1622 } else if (RD_IPV6_CS) {
1623 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1624 checksum = CHECKSUM_UNNECESSARY;
1625 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1626 checksum = CHECKSUM_UNNECESSARY;
1633 static void rx_bottom(struct r8152 *tp)
1635 unsigned long flags;
1636 struct list_head *cursor, *next, rx_queue;
1638 if (list_empty(&tp->rx_done))
1641 INIT_LIST_HEAD(&rx_queue);
1642 spin_lock_irqsave(&tp->rx_lock, flags);
1643 list_splice_init(&tp->rx_done, &rx_queue);
1644 spin_unlock_irqrestore(&tp->rx_lock, flags);
1646 list_for_each_safe(cursor, next, &rx_queue) {
1647 struct rx_desc *rx_desc;
1654 list_del_init(cursor);
1656 agg = list_entry(cursor, struct rx_agg, list);
1658 if (urb->actual_length < ETH_ZLEN)
1661 rx_desc = agg->head;
1662 rx_data = agg->head;
1663 len_used += sizeof(struct rx_desc);
1665 while (urb->actual_length > len_used) {
1666 struct net_device *netdev = tp->netdev;
1667 struct net_device_stats *stats = &netdev->stats;
1668 unsigned int pkt_len;
1669 struct sk_buff *skb;
1671 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1672 if (pkt_len < ETH_ZLEN)
1675 len_used += pkt_len;
1676 if (urb->actual_length < len_used)
1679 pkt_len -= CRC_SIZE;
1680 rx_data += sizeof(struct rx_desc);
1682 skb = netdev_alloc_skb_ip_align(netdev, pkt_len);
1684 stats->rx_dropped++;
1688 skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1689 memcpy(skb->data, rx_data, pkt_len);
1690 skb_put(skb, pkt_len);
1691 skb->protocol = eth_type_trans(skb, netdev);
1692 netif_receive_skb(skb);
1693 stats->rx_packets++;
1694 stats->rx_bytes += pkt_len;
1697 rx_data = rx_agg_align(rx_data + pkt_len + CRC_SIZE);
1698 rx_desc = (struct rx_desc *)rx_data;
1699 len_used = (int)(rx_data - (u8 *)agg->head);
1700 len_used += sizeof(struct rx_desc);
1704 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1705 if (ret && ret != -ENODEV) {
1706 spin_lock_irqsave(&tp->rx_lock, flags);
1707 list_add_tail(&agg->list, &tp->rx_done);
1708 spin_unlock_irqrestore(&tp->rx_lock, flags);
1709 tasklet_schedule(&tp->tl);
1714 static void tx_bottom(struct r8152 *tp)
1721 if (skb_queue_empty(&tp->tx_queue))
1724 agg = r8152_get_tx_agg(tp);
1728 res = r8152_tx_agg_fill(tp, agg);
1730 struct net_device *netdev = tp->netdev;
1732 if (res == -ENODEV) {
1733 netif_device_detach(netdev);
1735 struct net_device_stats *stats = &netdev->stats;
1736 unsigned long flags;
1738 netif_warn(tp, tx_err, netdev,
1739 "failed tx_urb %d\n", res);
1740 stats->tx_dropped += agg->skb_num;
1742 spin_lock_irqsave(&tp->tx_lock, flags);
1743 list_add_tail(&agg->list, &tp->tx_free);
1744 spin_unlock_irqrestore(&tp->tx_lock, flags);
1750 static void bottom_half(unsigned long data)
1754 tp = (struct r8152 *)data;
1756 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1759 if (!test_bit(WORK_ENABLE, &tp->flags))
1762 /* When link down, the driver would cancel all bulks. */
1763 /* This avoid the re-submitting bulk */
1764 if (!netif_carrier_ok(tp->netdev))
1772 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
1774 usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
1775 agg->head, rx_buf_sz,
1776 (usb_complete_t)read_bulk_callback, agg);
1778 return usb_submit_urb(agg->urb, mem_flags);
1781 static void rtl_drop_queued_tx(struct r8152 *tp)
1783 struct net_device_stats *stats = &tp->netdev->stats;
1784 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1785 struct sk_buff *skb;
1787 if (skb_queue_empty(tx_queue))
1790 __skb_queue_head_init(&skb_head);
1791 spin_lock_bh(&tx_queue->lock);
1792 skb_queue_splice_init(tx_queue, &skb_head);
1793 spin_unlock_bh(&tx_queue->lock);
1795 while ((skb = __skb_dequeue(&skb_head))) {
1797 stats->tx_dropped++;
1801 static void rtl8152_tx_timeout(struct net_device *netdev)
1803 struct r8152 *tp = netdev_priv(netdev);
1806 netif_warn(tp, tx_err, netdev, "Tx timeout\n");
1807 for (i = 0; i < RTL8152_MAX_TX; i++)
1808 usb_unlink_urb(tp->tx_info[i].urb);
1811 static void rtl8152_set_rx_mode(struct net_device *netdev)
1813 struct r8152 *tp = netdev_priv(netdev);
1815 if (tp->speed & LINK_STATUS) {
1816 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
1817 schedule_delayed_work(&tp->schedule, 0);
1821 static void _rtl8152_set_rx_mode(struct net_device *netdev)
1823 struct r8152 *tp = netdev_priv(netdev);
1824 u32 mc_filter[2]; /* Multicast hash filter */
1828 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1829 netif_stop_queue(netdev);
1830 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1831 ocp_data &= ~RCR_ACPT_ALL;
1832 ocp_data |= RCR_AB | RCR_APM;
1834 if (netdev->flags & IFF_PROMISC) {
1835 /* Unconditionally log net taps. */
1836 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
1837 ocp_data |= RCR_AM | RCR_AAP;
1838 mc_filter[1] = mc_filter[0] = 0xffffffff;
1839 } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
1840 (netdev->flags & IFF_ALLMULTI)) {
1841 /* Too many to filter perfectly -- accept all multicasts. */
1843 mc_filter[1] = mc_filter[0] = 0xffffffff;
1845 struct netdev_hw_addr *ha;
1847 mc_filter[1] = mc_filter[0] = 0;
1848 netdev_for_each_mc_addr(ha, netdev) {
1849 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
1850 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
1855 tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
1856 tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
1858 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
1859 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1860 netif_wake_queue(netdev);
1863 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
1864 struct net_device *netdev)
1866 struct r8152 *tp = netdev_priv(netdev);
1868 skb_tx_timestamp(skb);
1870 skb_queue_tail(&tp->tx_queue, skb);
1872 if (!list_empty(&tp->tx_free)) {
1873 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
1874 set_bit(SCHEDULE_TASKLET, &tp->flags);
1875 schedule_delayed_work(&tp->schedule, 0);
1877 usb_mark_last_busy(tp->udev);
1878 tasklet_schedule(&tp->tl);
1880 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
1881 netif_stop_queue(netdev);
1883 return NETDEV_TX_OK;
1886 static void r8152b_reset_packet_filter(struct r8152 *tp)
1890 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
1891 ocp_data &= ~FMC_FCR_MCU_EN;
1892 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1893 ocp_data |= FMC_FCR_MCU_EN;
1894 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
1897 static void rtl8152_nic_reset(struct r8152 *tp)
1901 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
1903 for (i = 0; i < 1000; i++) {
1904 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
1910 static void set_tx_qlen(struct r8152 *tp)
1912 struct net_device *netdev = tp->netdev;
1914 tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
1915 sizeof(struct tx_desc));
1918 static inline u8 rtl8152_get_speed(struct r8152 *tp)
1920 return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
1923 static void rtl_set_eee_plus(struct r8152 *tp)
1928 speed = rtl8152_get_speed(tp);
1929 if (speed & _10bps) {
1930 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1931 ocp_data |= EEEP_CR_EEEP_TX;
1932 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1934 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
1935 ocp_data &= ~EEEP_CR_EEEP_TX;
1936 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
1940 static void rxdy_gated_en(struct r8152 *tp, bool enable)
1944 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
1946 ocp_data |= RXDY_GATED_EN;
1948 ocp_data &= ~RXDY_GATED_EN;
1949 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
1952 static int rtl_start_rx(struct r8152 *tp)
1956 INIT_LIST_HEAD(&tp->rx_done);
1957 for (i = 0; i < RTL8152_MAX_RX; i++) {
1958 INIT_LIST_HEAD(&tp->rx_info[i].list);
1959 ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
1967 static int rtl_stop_rx(struct r8152 *tp)
1971 for (i = 0; i < RTL8152_MAX_RX; i++)
1972 usb_kill_urb(tp->rx_info[i].urb);
1977 static int rtl_enable(struct r8152 *tp)
1981 r8152b_reset_packet_filter(tp);
1983 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
1984 ocp_data |= CR_RE | CR_TE;
1985 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
1987 rxdy_gated_en(tp, false);
1989 return rtl_start_rx(tp);
1992 static int rtl8152_enable(struct r8152 *tp)
1994 if (test_bit(RTL8152_UNPLUG, &tp->flags))
1998 rtl_set_eee_plus(tp);
2000 return rtl_enable(tp);
2003 static void r8153_set_rx_agg(struct r8152 *tp)
2007 speed = rtl8152_get_speed(tp);
2008 if (speed & _1000bps) {
2009 if (tp->udev->speed == USB_SPEED_SUPER) {
2010 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2012 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2015 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH,
2017 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2021 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_SLOW);
2022 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_EARLY_AGG,
2027 static int rtl8153_enable(struct r8152 *tp)
2029 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2033 rtl_set_eee_plus(tp);
2034 r8153_set_rx_agg(tp);
2036 return rtl_enable(tp);
2039 static void rtl_disable(struct r8152 *tp)
2044 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2045 rtl_drop_queued_tx(tp);
2049 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2050 ocp_data &= ~RCR_ACPT_ALL;
2051 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2053 rtl_drop_queued_tx(tp);
2055 for (i = 0; i < RTL8152_MAX_TX; i++)
2056 usb_kill_urb(tp->tx_info[i].urb);
2058 rxdy_gated_en(tp, true);
2060 for (i = 0; i < 1000; i++) {
2061 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2062 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2067 for (i = 0; i < 1000; i++) {
2068 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2075 rtl8152_nic_reset(tp);
2078 static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2082 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2084 ocp_data |= POWER_CUT;
2086 ocp_data &= ~POWER_CUT;
2087 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2089 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2090 ocp_data &= ~RESUME_INDICATE;
2091 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2094 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2096 static u32 __rtl_get_wol(struct r8152 *tp)
2101 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2102 if (!(ocp_data & LAN_WAKE_EN))
2105 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2106 if (ocp_data & LINK_ON_WAKE_EN)
2107 wolopts |= WAKE_PHY;
2109 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2110 if (ocp_data & UWF_EN)
2111 wolopts |= WAKE_UCAST;
2112 if (ocp_data & BWF_EN)
2113 wolopts |= WAKE_BCAST;
2114 if (ocp_data & MWF_EN)
2115 wolopts |= WAKE_MCAST;
2117 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2118 if (ocp_data & MAGIC_EN)
2119 wolopts |= WAKE_MAGIC;
2124 static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2128 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2130 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2131 ocp_data &= ~LINK_ON_WAKE_EN;
2132 if (wolopts & WAKE_PHY)
2133 ocp_data |= LINK_ON_WAKE_EN;
2134 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2136 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2137 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN | LAN_WAKE_EN);
2138 if (wolopts & WAKE_UCAST)
2140 if (wolopts & WAKE_BCAST)
2142 if (wolopts & WAKE_MCAST)
2144 if (wolopts & WAKE_ANY)
2145 ocp_data |= LAN_WAKE_EN;
2146 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2148 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2150 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2151 ocp_data &= ~MAGIC_EN;
2152 if (wolopts & WAKE_MAGIC)
2153 ocp_data |= MAGIC_EN;
2154 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2156 if (wolopts & WAKE_ANY)
2157 device_set_wakeup_enable(&tp->udev->dev, true);
2159 device_set_wakeup_enable(&tp->udev->dev, false);
2162 static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2167 __rtl_set_wol(tp, WAKE_ANY);
2169 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2171 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2172 ocp_data |= LINK_OFF_WAKE_EN;
2173 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2175 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2177 __rtl_set_wol(tp, tp->saved_wolopts);
2181 static void rtl_phy_reset(struct r8152 *tp)
2186 clear_bit(PHY_RESET, &tp->flags);
2188 data = r8152_mdio_read(tp, MII_BMCR);
2190 /* don't reset again before the previous one complete */
2191 if (data & BMCR_RESET)
2195 r8152_mdio_write(tp, MII_BMCR, data);
2197 for (i = 0; i < 50; i++) {
2199 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2204 static void rtl_clear_bp(struct r8152 *tp)
2206 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_0, 0);
2207 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_2, 0);
2208 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_4, 0);
2209 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_BP_6, 0);
2210 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_0, 0);
2211 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_2, 0);
2212 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_4, 0);
2213 ocp_write_dword(tp, MCU_TYPE_USB, USB_BP_6, 0);
2215 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_BA, 0);
2216 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_BA, 0);
2219 static void r8153_clear_bp(struct r8152 *tp)
2221 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_BP_EN, 0);
2222 ocp_write_byte(tp, MCU_TYPE_USB, USB_BP_EN, 0);
2226 static void r8153_teredo_off(struct r8152 *tp)
2230 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2231 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | OOB_TEREDO_EN);
2232 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2234 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2235 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2236 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2239 static void r8152b_disable_aldps(struct r8152 *tp)
2241 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE);
2245 static inline void r8152b_enable_aldps(struct r8152 *tp)
2247 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2248 LINKENA | DIS_SDSAVE);
2251 static void rtl8152_disable(struct r8152 *tp)
2253 r8152b_disable_aldps(tp);
2255 r8152b_enable_aldps(tp);
2258 static void r8152b_hw_phy_cfg(struct r8152 *tp)
2262 data = r8152_mdio_read(tp, MII_BMCR);
2263 if (data & BMCR_PDOWN) {
2264 data &= ~BMCR_PDOWN;
2265 r8152_mdio_write(tp, MII_BMCR, data);
2270 set_bit(PHY_RESET, &tp->flags);
2273 static void r8152b_exit_oob(struct r8152 *tp)
2278 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2279 ocp_data &= ~RCR_ACPT_ALL;
2280 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2282 rxdy_gated_en(tp, true);
2283 r8153_teredo_off(tp);
2284 r8152b_hw_phy_cfg(tp);
2286 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2287 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
2289 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2290 ocp_data &= ~NOW_IS_OOB;
2291 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2293 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2294 ocp_data &= ~MCU_BORW_EN;
2295 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2297 for (i = 0; i < 1000; i++) {
2298 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2299 if (ocp_data & LINK_LIST_READY)
2304 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2305 ocp_data |= RE_INIT_LL;
2306 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2308 for (i = 0; i < 1000; i++) {
2309 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2310 if (ocp_data & LINK_LIST_READY)
2315 rtl8152_nic_reset(tp);
2317 /* rx share fifo credit full threshold */
2318 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2320 if (tp->udev->speed == USB_SPEED_FULL ||
2321 tp->udev->speed == USB_SPEED_LOW) {
2322 /* rx share fifo credit near full threshold */
2323 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2325 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2328 /* rx share fifo credit near full threshold */
2329 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
2331 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
2335 /* TX share fifo free credit full threshold */
2336 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
2338 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
2339 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
2340 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
2341 TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
2343 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2344 ocp_data &= ~CPCR_RX_VLAN;
2345 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2347 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2349 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2350 ocp_data |= TCR0_AUTO_FIFO;
2351 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2354 static void r8152b_enter_oob(struct r8152 *tp)
2359 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2360 ocp_data &= ~NOW_IS_OOB;
2361 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2363 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
2364 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
2365 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
2369 for (i = 0; i < 1000; i++) {
2370 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2371 if (ocp_data & LINK_LIST_READY)
2376 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2377 ocp_data |= RE_INIT_LL;
2378 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2380 for (i = 0; i < 1000; i++) {
2381 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2382 if (ocp_data & LINK_LIST_READY)
2387 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
2389 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2390 ocp_data |= CPCR_RX_VLAN;
2391 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2393 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2394 ocp_data |= ALDPS_PROXY_MODE;
2395 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2397 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2398 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2399 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2401 rxdy_gated_en(tp, false);
2403 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2404 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2405 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2408 static void r8153_hw_phy_cfg(struct r8152 *tp)
2413 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
2414 data = r8152_mdio_read(tp, MII_BMCR);
2415 if (data & BMCR_PDOWN) {
2416 data &= ~BMCR_PDOWN;
2417 r8152_mdio_write(tp, MII_BMCR, data);
2422 if (tp->version == RTL_VER_03) {
2423 data = ocp_reg_read(tp, OCP_EEE_CFG);
2424 data &= ~CTAP_SHORT_EN;
2425 ocp_reg_write(tp, OCP_EEE_CFG, data);
2428 data = ocp_reg_read(tp, OCP_POWER_CFG);
2429 data |= EEE_CLKDIV_EN;
2430 ocp_reg_write(tp, OCP_POWER_CFG, data);
2432 data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2433 data |= EN_10M_BGOFF;
2434 ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2435 data = ocp_reg_read(tp, OCP_POWER_CFG);
2436 data |= EN_10M_PLLOFF;
2437 ocp_reg_write(tp, OCP_POWER_CFG, data);
2438 data = sram_read(tp, SRAM_IMPEDANCE);
2439 data &= ~RX_DRIVING_MASK;
2440 sram_write(tp, SRAM_IMPEDANCE, data);
2442 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2443 ocp_data |= PFM_PWM_SWITCH;
2444 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2446 data = sram_read(tp, SRAM_LPF_CFG);
2447 data |= LPF_AUTO_TUNE;
2448 sram_write(tp, SRAM_LPF_CFG, data);
2450 data = sram_read(tp, SRAM_10M_AMP1);
2451 data |= GDAC_IB_UPALL;
2452 sram_write(tp, SRAM_10M_AMP1, data);
2453 data = sram_read(tp, SRAM_10M_AMP2);
2455 sram_write(tp, SRAM_10M_AMP2, data);
2457 set_bit(PHY_RESET, &tp->flags);
2460 static void r8153_u1u2en(struct r8152 *tp, bool enable)
2465 memset(u1u2, 0xff, sizeof(u1u2));
2467 memset(u1u2, 0x00, sizeof(u1u2));
2469 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2472 static void r8153_u2p3en(struct r8152 *tp, bool enable)
2476 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2478 ocp_data |= U2P3_ENABLE;
2480 ocp_data &= ~U2P3_ENABLE;
2481 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2484 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2488 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2490 ocp_data |= PWR_EN | PHASE2_EN;
2492 ocp_data &= ~(PWR_EN | PHASE2_EN);
2493 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2495 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2496 ocp_data &= ~PCUT_STATUS;
2497 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2500 static void r8153_first_init(struct r8152 *tp)
2505 rxdy_gated_en(tp, true);
2506 r8153_teredo_off(tp);
2508 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2509 ocp_data &= ~RCR_ACPT_ALL;
2510 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2512 r8153_hw_phy_cfg(tp);
2514 rtl8152_nic_reset(tp);
2516 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2517 ocp_data &= ~NOW_IS_OOB;
2518 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2520 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2521 ocp_data &= ~MCU_BORW_EN;
2522 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2524 for (i = 0; i < 1000; i++) {
2525 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2526 if (ocp_data & LINK_LIST_READY)
2531 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2532 ocp_data |= RE_INIT_LL;
2533 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2535 for (i = 0; i < 1000; i++) {
2536 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2537 if (ocp_data & LINK_LIST_READY)
2542 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2543 ocp_data &= ~CPCR_RX_VLAN;
2544 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2546 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2547 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
2549 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
2550 ocp_data |= TCR0_AUTO_FIFO;
2551 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
2553 rtl8152_nic_reset(tp);
2555 /* rx share fifo credit full threshold */
2556 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
2557 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
2558 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
2559 /* TX share fifo free credit full threshold */
2560 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
2562 /* rx aggregation */
2563 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2564 ocp_data &= ~RX_AGG_DISABLE;
2565 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2568 static void r8153_enter_oob(struct r8152 *tp)
2573 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2574 ocp_data &= ~NOW_IS_OOB;
2575 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2579 for (i = 0; i < 1000; i++) {
2580 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2581 if (ocp_data & LINK_LIST_READY)
2586 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
2587 ocp_data |= RE_INIT_LL;
2588 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
2590 for (i = 0; i < 1000; i++) {
2591 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2592 if (ocp_data & LINK_LIST_READY)
2597 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8153_RMS);
2599 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2600 ocp_data &= ~TEREDO_WAKE_MASK;
2601 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2603 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2604 ocp_data |= CPCR_RX_VLAN;
2605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2607 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
2608 ocp_data |= ALDPS_PROXY_MODE;
2609 ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
2611 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2612 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
2613 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
2615 rxdy_gated_en(tp, false);
2617 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2618 ocp_data |= RCR_APM | RCR_AM | RCR_AB;
2619 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2622 static void r8153_disable_aldps(struct r8152 *tp)
2626 data = ocp_reg_read(tp, OCP_POWER_CFG);
2628 ocp_reg_write(tp, OCP_POWER_CFG, data);
2632 static void r8153_enable_aldps(struct r8152 *tp)
2636 data = ocp_reg_read(tp, OCP_POWER_CFG);
2638 ocp_reg_write(tp, OCP_POWER_CFG, data);
2641 static void rtl8153_disable(struct r8152 *tp)
2643 r8153_disable_aldps(tp);
2645 r8153_enable_aldps(tp);
2648 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
2650 u16 bmcr, anar, gbcr;
2653 cancel_delayed_work_sync(&tp->schedule);
2654 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2655 anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
2656 ADVERTISE_100HALF | ADVERTISE_100FULL);
2657 if (tp->mii.supports_gmii) {
2658 gbcr = r8152_mdio_read(tp, MII_CTRL1000);
2659 gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
2664 if (autoneg == AUTONEG_DISABLE) {
2665 if (speed == SPEED_10) {
2667 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2668 } else if (speed == SPEED_100) {
2669 bmcr = BMCR_SPEED100;
2670 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2671 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2672 bmcr = BMCR_SPEED1000;
2673 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2679 if (duplex == DUPLEX_FULL)
2680 bmcr |= BMCR_FULLDPLX;
2682 if (speed == SPEED_10) {
2683 if (duplex == DUPLEX_FULL)
2684 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2686 anar |= ADVERTISE_10HALF;
2687 } else if (speed == SPEED_100) {
2688 if (duplex == DUPLEX_FULL) {
2689 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2690 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2692 anar |= ADVERTISE_10HALF;
2693 anar |= ADVERTISE_100HALF;
2695 } else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
2696 if (duplex == DUPLEX_FULL) {
2697 anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
2698 anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
2699 gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
2701 anar |= ADVERTISE_10HALF;
2702 anar |= ADVERTISE_100HALF;
2703 gbcr |= ADVERTISE_1000HALF;
2710 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
2713 if (test_bit(PHY_RESET, &tp->flags))
2716 if (tp->mii.supports_gmii)
2717 r8152_mdio_write(tp, MII_CTRL1000, gbcr);
2719 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2720 r8152_mdio_write(tp, MII_BMCR, bmcr);
2722 if (test_bit(PHY_RESET, &tp->flags)) {
2725 clear_bit(PHY_RESET, &tp->flags);
2726 for (i = 0; i < 50; i++) {
2728 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
2738 static void rtl8152_up(struct r8152 *tp)
2740 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2743 r8152b_disable_aldps(tp);
2744 r8152b_exit_oob(tp);
2745 r8152b_enable_aldps(tp);
2748 static void rtl8152_down(struct r8152 *tp)
2750 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2751 rtl_drop_queued_tx(tp);
2755 r8152_power_cut_en(tp, false);
2756 r8152b_disable_aldps(tp);
2757 r8152b_enter_oob(tp);
2758 r8152b_enable_aldps(tp);
2761 static void rtl8153_up(struct r8152 *tp)
2763 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2766 r8153_disable_aldps(tp);
2767 r8153_first_init(tp);
2768 r8153_enable_aldps(tp);
2771 static void rtl8153_down(struct r8152 *tp)
2773 if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2774 rtl_drop_queued_tx(tp);
2778 r8153_u1u2en(tp, false);
2779 r8153_power_cut_en(tp, false);
2780 r8153_disable_aldps(tp);
2781 r8153_enter_oob(tp);
2782 r8153_enable_aldps(tp);
2785 static void set_carrier(struct r8152 *tp)
2787 struct net_device *netdev = tp->netdev;
2790 clear_bit(RTL8152_LINK_CHG, &tp->flags);
2791 speed = rtl8152_get_speed(tp);
2793 if (speed & LINK_STATUS) {
2794 if (!(tp->speed & LINK_STATUS)) {
2795 tp->rtl_ops.enable(tp);
2796 set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2797 netif_carrier_on(netdev);
2800 if (tp->speed & LINK_STATUS) {
2801 netif_carrier_off(netdev);
2802 tasklet_disable(&tp->tl);
2803 tp->rtl_ops.disable(tp);
2804 tasklet_enable(&tp->tl);
2810 static void rtl_work_func_t(struct work_struct *work)
2812 struct r8152 *tp = container_of(work, struct r8152, schedule.work);
2814 if (usb_autopm_get_interface(tp->intf) < 0)
2817 if (!test_bit(WORK_ENABLE, &tp->flags))
2820 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2823 if (test_bit(RTL8152_LINK_CHG, &tp->flags))
2826 if (test_bit(RTL8152_SET_RX_MODE, &tp->flags))
2827 _rtl8152_set_rx_mode(tp->netdev);
2829 if (test_bit(SCHEDULE_TASKLET, &tp->flags) &&
2830 (tp->speed & LINK_STATUS)) {
2831 clear_bit(SCHEDULE_TASKLET, &tp->flags);
2832 tasklet_schedule(&tp->tl);
2835 if (test_bit(PHY_RESET, &tp->flags))
2839 usb_autopm_put_interface(tp->intf);
2842 static int rtl8152_open(struct net_device *netdev)
2844 struct r8152 *tp = netdev_priv(netdev);
2847 res = alloc_all_mem(tp);
2851 res = usb_autopm_get_interface(tp->intf);
2857 /* The WORK_ENABLE may be set when autoresume occurs */
2858 if (test_bit(WORK_ENABLE, &tp->flags)) {
2859 clear_bit(WORK_ENABLE, &tp->flags);
2860 usb_kill_urb(tp->intr_urb);
2861 cancel_delayed_work_sync(&tp->schedule);
2862 if (tp->speed & LINK_STATUS)
2863 tp->rtl_ops.disable(tp);
2868 rtl8152_set_speed(tp, AUTONEG_ENABLE,
2869 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
2872 netif_carrier_off(netdev);
2873 netif_start_queue(netdev);
2874 set_bit(WORK_ENABLE, &tp->flags);
2876 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
2879 netif_device_detach(tp->netdev);
2880 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
2885 usb_autopm_put_interface(tp->intf);
2891 static int rtl8152_close(struct net_device *netdev)
2893 struct r8152 *tp = netdev_priv(netdev);
2896 clear_bit(WORK_ENABLE, &tp->flags);
2897 usb_kill_urb(tp->intr_urb);
2898 cancel_delayed_work_sync(&tp->schedule);
2899 netif_stop_queue(netdev);
2901 res = usb_autopm_get_interface(tp->intf);
2903 rtl_drop_queued_tx(tp);
2906 * The autosuspend may have been enabled and wouldn't
2907 * be disable when autoresume occurs, because the
2908 * netif_running() would be false.
2910 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2911 rtl_runtime_suspend_enable(tp, false);
2912 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
2915 tasklet_disable(&tp->tl);
2916 tp->rtl_ops.down(tp);
2917 tasklet_enable(&tp->tl);
2918 usb_autopm_put_interface(tp->intf);
2926 static void r8152b_enable_eee(struct r8152 *tp)
2930 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2931 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2932 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2933 ocp_reg_write(tp, OCP_EEE_CONFIG1, RG_TXLPI_MSK_HFDUP | RG_MATCLR_EN |
2934 EEE_10_CAP | EEE_NWAY_EN |
2935 TX_QUIET_EN | RX_QUIET_EN |
2936 SDRISETIME | RG_RXLPI_MSK_HFDUP |
2938 ocp_reg_write(tp, OCP_EEE_CONFIG2, RG_LPIHYS_NUM | RG_DACQUIET_EN |
2939 RG_LDVQUIET_EN | RG_CKRSEL |
2941 ocp_reg_write(tp, OCP_EEE_CONFIG3, FST_SNR_EYE_R | RG_LFS_SEL | MSK_PH);
2942 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | DEVICE_ADDR);
2943 ocp_reg_write(tp, OCP_EEE_DATA, EEE_ADDR);
2944 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | DEVICE_ADDR);
2945 ocp_reg_write(tp, OCP_EEE_DATA, EEE_DATA);
2946 ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2949 static void r8153_enable_eee(struct r8152 *tp)
2954 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2955 ocp_data |= EEE_RX_EN | EEE_TX_EN;
2956 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2957 data = ocp_reg_read(tp, OCP_EEE_CFG);
2959 ocp_reg_write(tp, OCP_EEE_CFG, data);
2960 data = ocp_reg_read(tp, OCP_EEE_CFG2);
2961 data |= MY1000_EEE | MY100_EEE;
2962 ocp_reg_write(tp, OCP_EEE_CFG2, data);
2965 static void r8152b_enable_fc(struct r8152 *tp)
2969 anar = r8152_mdio_read(tp, MII_ADVERTISE);
2970 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
2971 r8152_mdio_write(tp, MII_ADVERTISE, anar);
2974 static void rtl_tally_reset(struct r8152 *tp)
2978 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
2979 ocp_data |= TALLY_RESET;
2980 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
2983 static void r8152b_init(struct r8152 *tp)
2987 if (test_bit(RTL8152_UNPLUG, &tp->flags))
2990 r8152b_disable_aldps(tp);
2992 if (tp->version == RTL_VER_01) {
2993 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
2994 ocp_data &= ~LED_MODE_MASK;
2995 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
2998 r8152_power_cut_en(tp, false);
3000 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3001 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
3002 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3003 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
3004 ocp_data &= ~MCU_CLK_RATIO_MASK;
3005 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
3006 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
3007 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
3008 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
3009 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
3011 r8152b_enable_eee(tp);
3012 r8152b_enable_aldps(tp);
3013 r8152b_enable_fc(tp);
3014 rtl_tally_reset(tp);
3016 /* enable rx aggregation */
3017 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
3018 ocp_data &= ~RX_AGG_DISABLE;
3019 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
3022 static void r8153_init(struct r8152 *tp)
3027 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3030 r8153_disable_aldps(tp);
3031 r8153_u1u2en(tp, false);
3033 for (i = 0; i < 500; i++) {
3034 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
3040 for (i = 0; i < 500; i++) {
3041 ocp_data = ocp_reg_read(tp, OCP_PHY_STATUS) & PHY_STAT_MASK;
3042 if (ocp_data == PHY_STAT_LAN_ON || ocp_data == PHY_STAT_PWRDN)
3047 r8153_u2p3en(tp, false);
3049 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
3050 ocp_data &= ~TIMER11_EN;
3051 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
3053 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
3054 ocp_data &= ~LED_MODE_MASK;
3055 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
3057 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL);
3058 ocp_data &= ~LPM_TIMER_MASK;
3059 if (tp->udev->speed == USB_SPEED_SUPER)
3060 ocp_data |= LPM_TIMER_500US;
3062 ocp_data |= LPM_TIMER_500MS;
3063 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
3065 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
3066 ocp_data &= ~SEN_VAL_MASK;
3067 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
3068 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
3070 r8153_power_cut_en(tp, false);
3071 r8153_u1u2en(tp, true);
3073 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ALDPS_SPDWN_RATIO);
3074 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, EEE_SPDWN_RATIO);
3075 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
3076 PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
3077 U1U2_SPDWN_EN | L1_SPDWN_EN);
3078 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
3079 PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
3080 TP100_SPDWN_EN | TP500_SPDWN_EN | TP1000_SPDWN_EN |
3083 r8153_enable_eee(tp);
3084 r8153_enable_aldps(tp);
3085 r8152b_enable_fc(tp);
3086 rtl_tally_reset(tp);
3089 static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
3091 struct r8152 *tp = usb_get_intfdata(intf);
3093 if (PMSG_IS_AUTO(message))
3094 set_bit(SELECTIVE_SUSPEND, &tp->flags);
3096 netif_device_detach(tp->netdev);
3098 if (netif_running(tp->netdev)) {
3099 clear_bit(WORK_ENABLE, &tp->flags);
3100 usb_kill_urb(tp->intr_urb);
3101 cancel_delayed_work_sync(&tp->schedule);
3102 tasklet_disable(&tp->tl);
3103 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3105 rtl_runtime_suspend_enable(tp, true);
3107 tp->rtl_ops.down(tp);
3109 tasklet_enable(&tp->tl);
3115 static int rtl8152_resume(struct usb_interface *intf)
3117 struct r8152 *tp = usb_get_intfdata(intf);
3119 if (!test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3120 tp->rtl_ops.init(tp);
3121 netif_device_attach(tp->netdev);
3124 if (netif_running(tp->netdev)) {
3125 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
3126 rtl_runtime_suspend_enable(tp, false);
3127 clear_bit(SELECTIVE_SUSPEND, &tp->flags);
3128 set_bit(WORK_ENABLE, &tp->flags);
3129 if (tp->speed & LINK_STATUS)
3133 rtl8152_set_speed(tp, AUTONEG_ENABLE,
3134 tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
3137 netif_carrier_off(tp->netdev);
3138 set_bit(WORK_ENABLE, &tp->flags);
3140 usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3146 static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3148 struct r8152 *tp = netdev_priv(dev);
3150 if (usb_autopm_get_interface(tp->intf) < 0)
3153 wol->supported = WAKE_ANY;
3154 wol->wolopts = __rtl_get_wol(tp);
3156 usb_autopm_put_interface(tp->intf);
3159 static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3161 struct r8152 *tp = netdev_priv(dev);
3164 ret = usb_autopm_get_interface(tp->intf);
3168 __rtl_set_wol(tp, wol->wolopts);
3169 tp->saved_wolopts = wol->wolopts & WAKE_ANY;
3171 usb_autopm_put_interface(tp->intf);
3177 static u32 rtl8152_get_msglevel(struct net_device *dev)
3179 struct r8152 *tp = netdev_priv(dev);
3181 return tp->msg_enable;
3184 static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
3186 struct r8152 *tp = netdev_priv(dev);
3188 tp->msg_enable = value;
3191 static void rtl8152_get_drvinfo(struct net_device *netdev,
3192 struct ethtool_drvinfo *info)
3194 struct r8152 *tp = netdev_priv(netdev);
3196 strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
3197 strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
3198 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
3202 int rtl8152_get_settings(struct net_device *netdev, struct ethtool_cmd *cmd)
3204 struct r8152 *tp = netdev_priv(netdev);
3206 if (!tp->mii.mdio_read)
3209 return mii_ethtool_gset(&tp->mii, cmd);
3212 static int rtl8152_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
3214 struct r8152 *tp = netdev_priv(dev);
3217 ret = usb_autopm_get_interface(tp->intf);
3221 ret = rtl8152_set_speed(tp, cmd->autoneg, cmd->speed, cmd->duplex);
3223 usb_autopm_put_interface(tp->intf);
3229 static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
3236 "tx_single_collisions",
3237 "tx_multi_collisions",
3245 static int rtl8152_get_sset_count(struct net_device *dev, int sset)
3249 return ARRAY_SIZE(rtl8152_gstrings);
3255 static void rtl8152_get_ethtool_stats(struct net_device *dev,
3256 struct ethtool_stats *stats, u64 *data)
3258 struct r8152 *tp = netdev_priv(dev);
3259 struct tally_counter tally;
3261 if (usb_autopm_get_interface(tp->intf) < 0)
3264 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
3266 usb_autopm_put_interface(tp->intf);
3268 data[0] = le64_to_cpu(tally.tx_packets);
3269 data[1] = le64_to_cpu(tally.rx_packets);
3270 data[2] = le64_to_cpu(tally.tx_errors);
3271 data[3] = le32_to_cpu(tally.rx_errors);
3272 data[4] = le16_to_cpu(tally.rx_missed);
3273 data[5] = le16_to_cpu(tally.align_errors);
3274 data[6] = le32_to_cpu(tally.tx_one_collision);
3275 data[7] = le32_to_cpu(tally.tx_multi_collision);
3276 data[8] = le64_to_cpu(tally.rx_unicast);
3277 data[9] = le64_to_cpu(tally.rx_broadcast);
3278 data[10] = le32_to_cpu(tally.rx_multicast);
3279 data[11] = le16_to_cpu(tally.tx_aborted);
3280 data[12] = le16_to_cpu(tally.tx_underun);
3283 static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
3285 switch (stringset) {
3287 memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
3292 static struct ethtool_ops ops = {
3293 .get_drvinfo = rtl8152_get_drvinfo,
3294 .get_settings = rtl8152_get_settings,
3295 .set_settings = rtl8152_set_settings,
3296 .get_link = ethtool_op_get_link,
3297 .get_msglevel = rtl8152_get_msglevel,
3298 .set_msglevel = rtl8152_set_msglevel,
3299 .get_wol = rtl8152_get_wol,
3300 .set_wol = rtl8152_set_wol,
3301 .get_strings = rtl8152_get_strings,
3302 .get_sset_count = rtl8152_get_sset_count,
3303 .get_ethtool_stats = rtl8152_get_ethtool_stats,
3306 static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
3308 struct r8152 *tp = netdev_priv(netdev);
3309 struct mii_ioctl_data *data = if_mii(rq);
3312 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3315 res = usb_autopm_get_interface(tp->intf);
3321 data->phy_id = R8152_PHY_ID; /* Internal PHY */
3325 data->val_out = r8152_mdio_read(tp, data->reg_num);
3329 if (!capable(CAP_NET_ADMIN)) {
3333 r8152_mdio_write(tp, data->reg_num, data->val_in);
3340 usb_autopm_put_interface(tp->intf);
3346 static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
3348 struct r8152 *tp = netdev_priv(dev);
3350 switch (tp->version) {
3353 return eth_change_mtu(dev, new_mtu);
3358 if (new_mtu < 68 || new_mtu > RTL8153_MAX_MTU)
3366 static const struct net_device_ops rtl8152_netdev_ops = {
3367 .ndo_open = rtl8152_open,
3368 .ndo_stop = rtl8152_close,
3369 .ndo_do_ioctl = rtl8152_ioctl,
3370 .ndo_start_xmit = rtl8152_start_xmit,
3371 .ndo_tx_timeout = rtl8152_tx_timeout,
3372 .ndo_set_rx_mode = rtl8152_set_rx_mode,
3373 .ndo_set_mac_address = rtl8152_set_mac_address,
3374 .ndo_change_mtu = rtl8152_change_mtu,
3375 .ndo_validate_addr = eth_validate_addr,
3378 static void r8152b_get_version(struct r8152 *tp)
3383 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1);
3384 version = (u16)(ocp_data & VERSION_MASK);
3388 tp->version = RTL_VER_01;
3391 tp->version = RTL_VER_02;
3394 tp->version = RTL_VER_03;
3395 tp->mii.supports_gmii = 1;
3398 tp->version = RTL_VER_04;
3399 tp->mii.supports_gmii = 1;
3402 tp->version = RTL_VER_05;
3403 tp->mii.supports_gmii = 1;
3406 netif_info(tp, probe, tp->netdev,
3407 "Unknown version 0x%04x\n", version);
3412 static void rtl8152_unload(struct r8152 *tp)
3414 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3417 if (tp->version != RTL_VER_01)
3418 r8152_power_cut_en(tp, true);
3421 static void rtl8153_unload(struct r8152 *tp)
3423 if (test_bit(RTL8152_UNPLUG, &tp->flags))
3426 r8153_power_cut_en(tp, true);
3429 static int rtl_ops_init(struct r8152 *tp, const struct usb_device_id *id)
3431 struct rtl_ops *ops = &tp->rtl_ops;
3434 switch (id->idVendor) {
3435 case VENDOR_ID_REALTEK:
3436 switch (id->idProduct) {
3437 case PRODUCT_ID_RTL8152:
3438 ops->init = r8152b_init;
3439 ops->enable = rtl8152_enable;
3440 ops->disable = rtl8152_disable;
3441 ops->up = rtl8152_up;
3442 ops->down = rtl8152_down;
3443 ops->unload = rtl8152_unload;
3446 case PRODUCT_ID_RTL8153:
3447 ops->init = r8153_init;
3448 ops->enable = rtl8153_enable;
3449 ops->disable = rtl8153_disable;
3450 ops->up = rtl8153_up;
3451 ops->down = rtl8153_down;
3452 ops->unload = rtl8153_unload;
3460 case VENDOR_ID_SAMSUNG:
3461 switch (id->idProduct) {
3462 case PRODUCT_ID_SAMSUNG:
3463 ops->init = r8153_init;
3464 ops->enable = rtl8153_enable;
3465 ops->disable = rtl8153_disable;
3466 ops->up = rtl8153_up;
3467 ops->down = rtl8153_down;
3468 ops->unload = rtl8153_unload;
3481 netif_err(tp, probe, tp->netdev, "Unknown Device\n");
3486 static int rtl8152_probe(struct usb_interface *intf,
3487 const struct usb_device_id *id)
3489 struct usb_device *udev = interface_to_usbdev(intf);
3491 struct net_device *netdev;
3494 if (udev->actconfig->desc.bConfigurationValue != 1) {
3495 usb_driver_set_configuration(udev, 1);
3499 usb_reset_device(udev);
3500 netdev = alloc_etherdev(sizeof(struct r8152));
3502 dev_err(&intf->dev, "Out of memory\n");
3506 SET_NETDEV_DEV(netdev, &intf->dev);
3507 tp = netdev_priv(netdev);
3508 tp->msg_enable = 0x7FFF;
3511 tp->netdev = netdev;
3514 ret = rtl_ops_init(tp, id);
3518 tasklet_init(&tp->tl, bottom_half, (unsigned long)tp);
3519 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
3521 netdev->netdev_ops = &rtl8152_netdev_ops;
3522 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
3524 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3525 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
3527 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
3528 NETIF_F_TSO | NETIF_F_FRAGLIST |
3529 NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
3531 netdev->ethtool_ops = &ops;
3532 netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
3534 tp->mii.dev = netdev;
3535 tp->mii.mdio_read = read_mii_word;
3536 tp->mii.mdio_write = write_mii_word;
3537 tp->mii.phy_id_mask = 0x3f;
3538 tp->mii.reg_num_mask = 0x1f;
3539 tp->mii.phy_id = R8152_PHY_ID;
3540 tp->mii.supports_gmii = 0;
3542 intf->needs_remote_wakeup = 1;
3544 r8152b_get_version(tp);
3545 tp->rtl_ops.init(tp);
3546 set_ethernet_addr(tp);
3548 usb_set_intfdata(intf, tp);
3550 ret = register_netdev(netdev);
3552 netif_err(tp, probe, netdev, "couldn't register the device\n");
3556 tp->saved_wolopts = __rtl_get_wol(tp);
3557 if (tp->saved_wolopts)
3558 device_set_wakeup_enable(&udev->dev, true);
3560 device_set_wakeup_enable(&udev->dev, false);
3562 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
3567 usb_set_intfdata(intf, NULL);
3569 free_netdev(netdev);
3573 static void rtl8152_disconnect(struct usb_interface *intf)
3575 struct r8152 *tp = usb_get_intfdata(intf);
3577 usb_set_intfdata(intf, NULL);
3579 struct usb_device *udev = tp->udev;
3581 if (udev->state == USB_STATE_NOTATTACHED)
3582 set_bit(RTL8152_UNPLUG, &tp->flags);
3584 tasklet_kill(&tp->tl);
3585 unregister_netdev(tp->netdev);
3586 tp->rtl_ops.unload(tp);
3587 free_netdev(tp->netdev);
3591 /* table of devices that work with this driver */
3592 static struct usb_device_id rtl8152_table[] = {
3593 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8152)},
3594 {USB_DEVICE(VENDOR_ID_REALTEK, PRODUCT_ID_RTL8153)},
3595 {USB_DEVICE(VENDOR_ID_SAMSUNG, PRODUCT_ID_SAMSUNG)},
3599 MODULE_DEVICE_TABLE(usb, rtl8152_table);
3601 static struct usb_driver rtl8152_driver = {
3603 .id_table = rtl8152_table,
3604 .probe = rtl8152_probe,
3605 .disconnect = rtl8152_disconnect,
3606 .suspend = rtl8152_suspend,
3607 .resume = rtl8152_resume,
3608 .reset_resume = rtl8152_resume,
3609 .supports_autosuspend = 1,
3610 .disable_hub_initiated_lpm = 1,
3613 module_usb_driver(rtl8152_driver);
3615 MODULE_AUTHOR(DRIVER_AUTHOR);
3616 MODULE_DESCRIPTION(DRIVER_DESC);
3617 MODULE_LICENSE("GPL");