drivers/net/typhoon.c

   1 /* typhoon.c: A Linux Ethernet device driver for 3Com 3CR990 family of NICs */
   2 /*
   3         Written 2002-2004 by David Dillow <dave@thedillows.org>
   4         Based on code written 1998-2000 by Donald Becker <becker@scyld.com> and
   5         Linux 2.2.x driver by David P. McLean <davidpmclean@yahoo.com>.
   6
   7         This software may be used and distributed according to the terms of
   8         the GNU General Public License (GPL), incorporated herein by reference.
   9         Drivers based on or derived from this code fall under the GPL and must
  10         retain the authorship, copyright and license notice.  This file is not
  11         a complete program and may only be used when the entire operating
  12         system is licensed under the GPL.
  13
  14         This software is available on a public web site. It may enable
  15         cryptographic capabilities of the 3Com hardware, and may be
  16         exported from the United States under License Exception "TSU"
  17         pursuant to 15 C.F.R. Section 740.13(e).
  18
  19         This work was funded by the National Library of Medicine under
  20         the Department of Energy project number 0274DD06D1 and NLM project
  21         number Y1-LM-2015-01.
  22
  23         This driver is designed for the 3Com 3CR990 Family of cards with the
  24         3XP Processor. It has been tested on x86 and sparc64.
  25
  26         KNOWN ISSUES:
  27         *) Cannot DMA Rx packets to a 2 byte aligned address. Also firmware
  28                 issue. Hopefully 3Com will fix it.
  29         *) Waiting for a command response takes 8ms due to non-preemptable
  30                 polling. Only significant for getting stats and creating
  31                 SAs, but an ugly wart never the less.
  32
  33         TODO:
  34         *) Doesn't do IPSEC offloading. Yet. Keep yer pants on, it's coming.
  35         *) Add more support for ethtool (especially for NIC stats)
  36         *) Allow disabling of RX checksum offloading
  37         *) Fix MAC changing to work while the interface is up
  38                 (Need to put commands on the TX ring, which changes
  39                 the locking)
  40         *) Add in FCS to {rx,tx}_bytes, since the hardware doesn't. See
  41                 http://oss.sgi.com/cgi-bin/mesg.cgi?a=netdev&i=20031215152211.7003fe8e.rddunlap%40osdl.org
  42 */
  43
  44 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
  45  * Setting to > 1518 effectively disables this feature.
  46  */
  47 static int rx_copybreak = 200;
  48
  49 /* Should we use MMIO or Port IO?
  50  * 0: Port IO
  51  * 1: MMIO
  52  * 2: Try MMIO, fallback to Port IO
  53  */
  54 static unsigned int use_mmio = 2;
  55
  56 /* end user-configurable values */
  57
  58 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
  59  */
  60 static const int multicast_filter_limit = 32;
  61
  62 /* Operational parameters that are set at compile time. */
  63
  64 /* Keep the ring sizes a power of two for compile efficiency.
  65  * The compiler will convert <unsigned>'%'<2^N> into a bit mask.
  66  * Making the Tx ring too large decreases the effectiveness of channel
  67  * bonding and packet priority.
  68  * There are no ill effects from too-large receive rings.
  69  *
  70  * We don't currently use the Hi Tx ring so, don't make it very big.
  71  *
  72  * Beware that if we start using the Hi Tx ring, we will need to change
  73  * typhoon_num_free_tx() and typhoon_tx_complete() to account for that.
  74  */
  75 #define TXHI_ENTRIES            2
  76 #define TXLO_ENTRIES            128
  77 #define RX_ENTRIES              32
  78 #define COMMAND_ENTRIES         16
  79 #define RESPONSE_ENTRIES        32
  80
  81 #define COMMAND_RING_SIZE       (COMMAND_ENTRIES * sizeof(struct cmd_desc))
  82 #define RESPONSE_RING_SIZE      (RESPONSE_ENTRIES * sizeof(struct resp_desc))
  83
  84 /* The 3XP will preload and remove 64 entries from the free buffer
  85  * list, and we need one entry to keep the ring from wrapping, so
  86  * to keep this a power of two, we use 128 entries.
  87  */
  88 #define RXFREE_ENTRIES          128
  89 #define RXENT_ENTRIES           (RXFREE_ENTRIES - 1)
  90
  91 /* Operational parameters that usually are not changed. */
  92
  93 /* Time in jiffies before concluding the transmitter is hung. */
  94 #define TX_TIMEOUT  (2*HZ)
  95
  96 #define PKT_BUF_SZ              1536
  97 #define FIRMWARE_NAME           "3com/typhoon.bin"
  98
  99 #define pr_fmt(fmt)             KBUILD_MODNAME " " fmt
 100
 101 #include <linux/module.h>
 102 #include <linux/kernel.h>
 103 #include <linux/sched.h>
 104 #include <linux/string.h>
 105 #include <linux/timer.h>
 106 #include <linux/errno.h>
 107 #include <linux/ioport.h>
 108 #include <linux/interrupt.h>
 109 #include <linux/pci.h>
 110 #include <linux/netdevice.h>
 111 #include <linux/etherdevice.h>
 112 #include <linux/skbuff.h>
 113 #include <linux/mm.h>
 114 #include <linux/init.h>
 115 #include <linux/delay.h>
 116 #include <linux/ethtool.h>
 117 #include <linux/if_vlan.h>
 118 #include <linux/crc32.h>
 119 #include <linux/bitops.h>
 120 #include <asm/processor.h>
 121 #include <asm/io.h>
 122 #include <asm/uaccess.h>
 123 #include <linux/in6.h>
 124 #include <linux/dma-mapping.h>
 125 #include <linux/firmware.h>
 126
 127 #include "typhoon.h"
 128
 129 MODULE_AUTHOR("David Dillow <dave@thedillows.org>");
 130 MODULE_VERSION("1.0");
 131 MODULE_LICENSE("GPL");
 132 MODULE_FIRMWARE(FIRMWARE_NAME);
 133 MODULE_DESCRIPTION("3Com Typhoon Family (3C990, 3CR990, and variants)");
 134 MODULE_PARM_DESC(rx_copybreak, "Packets smaller than this are copied and "
 135                                "the buffer given back to the NIC. Default "
 136                                "is 200.");
 137 MODULE_PARM_DESC(use_mmio, "Use MMIO (1) or PIO(0) to access the NIC. "
 138                            "Default is to try MMIO and fallback to PIO.");
 139 module_param(rx_copybreak, int, 0);
 140 module_param(use_mmio, int, 0);
 141
 142 #if defined(NETIF_F_TSO) && MAX_SKB_FRAGS > 32
 143 #warning Typhoon only supports 32 entries in its SG list for TSO, disabling TSO
 144 #undef NETIF_F_TSO
 145 #endif
 146
 147 #if TXLO_ENTRIES <= (2 * MAX_SKB_FRAGS)
 148 #error TX ring too small!
 149 #endif
 150
 151 struct typhoon_card_info {
 152         const char *name;
 153         const int capabilities;
 154 };
 155
 156 #define TYPHOON_CRYPTO_NONE             0x00
 157 #define TYPHOON_CRYPTO_DES              0x01
 158 #define TYPHOON_CRYPTO_3DES             0x02
 159 #define TYPHOON_CRYPTO_VARIABLE         0x04
 160 #define TYPHOON_FIBER                   0x08
 161 #define TYPHOON_WAKEUP_NEEDS_RESET      0x10
 162
 163 enum typhoon_cards {
 164         TYPHOON_TX = 0, TYPHOON_TX95, TYPHOON_TX97, TYPHOON_SVR,
 165         TYPHOON_SVR95, TYPHOON_SVR97, TYPHOON_TXM, TYPHOON_BSVR,
 166         TYPHOON_FX95, TYPHOON_FX97, TYPHOON_FX95SVR, TYPHOON_FX97SVR,
 167         TYPHOON_FXM,
 168 };
 169
 170 /* directly indexed by enum typhoon_cards, above */
 171 static struct typhoon_card_info typhoon_card_info[] __devinitdata = {
 172         { "3Com Typhoon (3C990-TX)",
 173                 TYPHOON_CRYPTO_NONE},
 174         { "3Com Typhoon (3CR990-TX-95)",
 175                 TYPHOON_CRYPTO_DES},
 176         { "3Com Typhoon (3CR990-TX-97)",
 177                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 178         { "3Com Typhoon (3C990SVR)",
 179                 TYPHOON_CRYPTO_NONE},
 180         { "3Com Typhoon (3CR990SVR95)",
 181                 TYPHOON_CRYPTO_DES},
 182         { "3Com Typhoon (3CR990SVR97)",
 183                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES},
 184         { "3Com Typhoon2 (3C990B-TX-M)",
 185                 TYPHOON_CRYPTO_VARIABLE},
 186         { "3Com Typhoon2 (3C990BSVR)",
 187                 TYPHOON_CRYPTO_VARIABLE},
 188         { "3Com Typhoon (3CR990-FX-95)",
 189                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 190         { "3Com Typhoon (3CR990-FX-97)",
 191                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 192         { "3Com Typhoon (3CR990-FX-95 Server)",
 193                 TYPHOON_CRYPTO_DES | TYPHOON_FIBER},
 194         { "3Com Typhoon (3CR990-FX-97 Server)",
 195                 TYPHOON_CRYPTO_DES | TYPHOON_CRYPTO_3DES | TYPHOON_FIBER},
 196         { "3Com Typhoon2 (3C990B-FX-97)",
 197                 TYPHOON_CRYPTO_VARIABLE | TYPHOON_FIBER},
 198 };
 199
 200 /* Notes on the new subsystem numbering scheme:
 201  * bits 0-1 indicate crypto capabilities: (0) variable, (1) DES, or (2) 3DES
 202  * bit 4 indicates if this card has secured firmware (we don't support it)
 203  * bit 8 indicates if this is a (0) copper or (1) fiber card
 204  * bits 12-16 indicate card type: (0) client and (1) server
 205  */
 206 static DEFINE_PCI_DEVICE_TABLE(typhoon_pci_tbl) = {
 207         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990,
 208           PCI_ANY_ID, PCI_ANY_ID, 0, 0,TYPHOON_TX },
 209         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_95,
 210           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX95 },
 211         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_TX_97,
 212           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_TX97 },
 213         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 214           PCI_ANY_ID, 0x1000, 0, 0, TYPHOON_TXM },
 215         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 216           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FXM },
 217         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990B,
 218           PCI_ANY_ID, 0x2000, 0, 0, TYPHOON_BSVR },
 219         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 220           PCI_ANY_ID, 0x1101, 0, 0, TYPHOON_FX95 },
 221         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 222           PCI_ANY_ID, 0x1102, 0, 0, TYPHOON_FX97 },
 223         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 224           PCI_ANY_ID, 0x2101, 0, 0, TYPHOON_FX95SVR },
 225         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990_FX,
 226           PCI_ANY_ID, 0x2102, 0, 0, TYPHOON_FX97SVR },
 227         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR95,
 228           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR95 },
 229         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR97,
 230           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR97 },
 231         { PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3CR990SVR,
 232           PCI_ANY_ID, PCI_ANY_ID, 0, 0, TYPHOON_SVR },
 233         { 0, }
 234 };
 235 MODULE_DEVICE_TABLE(pci, typhoon_pci_tbl);
 236
 237 /* Define the shared memory area
 238  * Align everything the 3XP will normally be using.
 239  * We'll need to move/align txHi if we start using that ring.
 240  */
 241 #define __3xp_aligned   ____cacheline_aligned
 242 struct typhoon_shared {
 243         struct typhoon_interface        iface;
 244         struct typhoon_indexes          indexes                 __3xp_aligned;
 245         struct tx_desc                  txLo[TXLO_ENTRIES]      __3xp_aligned;
 246         struct rx_desc                  rxLo[RX_ENTRIES]        __3xp_aligned;
 247         struct rx_desc                  rxHi[RX_ENTRIES]        __3xp_aligned;
 248         struct cmd_desc                 cmd[COMMAND_ENTRIES]    __3xp_aligned;
 249         struct resp_desc                resp[RESPONSE_ENTRIES]  __3xp_aligned;
 250         struct rx_free                  rxBuff[RXFREE_ENTRIES]  __3xp_aligned;
 251         u32                             zeroWord;
 252         struct tx_desc                  txHi[TXHI_ENTRIES];
 253 } __packed;
 254
 255 struct rxbuff_ent {
 256         struct sk_buff *skb;
 257         dma_addr_t      dma_addr;
 258 };
 259
 260 struct typhoon {
 261         /* Tx cache line section */
 262         struct transmit_ring    txLoRing        ____cacheline_aligned;
 263         struct pci_dev *        tx_pdev;
 264         void __iomem            *tx_ioaddr;
 265         u32                     txlo_dma_addr;
 266
 267         /* Irq/Rx cache line section */
 268         void __iomem            *ioaddr         ____cacheline_aligned;
 269         struct typhoon_indexes *indexes;
 270         u8                      awaiting_resp;
 271         u8                      duplex;
 272         u8                      speed;
 273         u8                      card_state;
 274         struct basic_ring       rxLoRing;
 275         struct pci_dev *        pdev;
 276         struct net_device *     dev;
 277         struct napi_struct      napi;
 278         struct basic_ring       rxHiRing;
 279         struct basic_ring       rxBuffRing;
 280         struct rxbuff_ent       rxbuffers[RXENT_ENTRIES];
 281
 282         /* general section */
 283         spinlock_t              command_lock    ____cacheline_aligned;
 284         struct basic_ring       cmdRing;
 285         struct basic_ring       respRing;
 286         struct net_device_stats stats;
 287         struct net_device_stats stats_saved;
 288         struct typhoon_shared * shared;
 289         dma_addr_t              shared_dma;
 290         __le16                  xcvr_select;
 291         __le16                  wol_events;
 292         __le32                  offload;
 293
 294         /* unused stuff (future use) */
 295         int                     capabilities;
 296         struct transmit_ring    txHiRing;
 297 };
 298
 299 enum completion_wait_values {
 300         NoWait = 0, WaitNoSleep, WaitSleep,
 301 };
 302
 303 /* These are the values for the typhoon.card_state variable.
 304  * These determine where the statistics will come from in get_stats().
 305  * The sleep image does not support the statistics we need.
 306  */
 307 enum state_values {
 308         Sleeping = 0, Running,
 309 };
 310
 311 /* PCI writes are not guaranteed to be posted in order, but outstanding writes
 312  * cannot pass a read, so this forces current writes to post.
 313  */
 314 #define typhoon_post_pci_writes(x) \
 315         do { if(likely(use_mmio)) ioread32(x+TYPHOON_REG_HEARTBEAT); } while(0)
 316
 317 /* We'll wait up to six seconds for a reset, and half a second normally.
 318  */
 319 #define TYPHOON_UDELAY                  50
 320 #define TYPHOON_RESET_TIMEOUT_SLEEP     (6 * HZ)
 321 #define TYPHOON_RESET_TIMEOUT_NOSLEEP   ((6 * 1000000) / TYPHOON_UDELAY)
 322 #define TYPHOON_WAIT_TIMEOUT            ((1000000 / 2) / TYPHOON_UDELAY)
 323
 324 #if defined(NETIF_F_TSO)
 325 #define skb_tso_size(x)         (skb_shinfo(x)->gso_size)
 326 #define TSO_NUM_DESCRIPTORS     2
 327 #define TSO_OFFLOAD_ON          TYPHOON_OFFLOAD_TCP_SEGMENT
 328 #else
 329 #define NETIF_F_TSO             0
 330 #define skb_tso_size(x)         0
 331 #define TSO_NUM_DESCRIPTORS     0
 332 #define TSO_OFFLOAD_ON          0
 333 #endif
 334
 335 static inline void
 336 typhoon_inc_index(u32 *index, const int count, const int num_entries)
 337 {
 338         /* Increment a ring index -- we can use this for all rings execept
 339          * the Rx rings, as they use different size descriptors
 340          * otherwise, everything is the same size as a cmd_desc
 341          */
 342         *index += count * sizeof(struct cmd_desc);
 343         *index %= num_entries * sizeof(struct cmd_desc);
 344 }
 345
 346 static inline void
 347 typhoon_inc_cmd_index(u32 *index, const int count)
 348 {
 349         typhoon_inc_index(index, count, COMMAND_ENTRIES);
 350 }
 351
 352 static inline void
 353 typhoon_inc_resp_index(u32 *index, const int count)
 354 {
 355         typhoon_inc_index(index, count, RESPONSE_ENTRIES);
 356 }
 357
 358 static inline void
 359 typhoon_inc_rxfree_index(u32 *index, const int count)
 360 {
 361         typhoon_inc_index(index, count, RXFREE_ENTRIES);
 362 }
 363
 364 static inline void
 365 typhoon_inc_tx_index(u32 *index, const int count)
 366 {
 367         /* if we start using the Hi Tx ring, this needs updateing */
 368         typhoon_inc_index(index, count, TXLO_ENTRIES);
 369 }
 370
 371 static inline void
 372 typhoon_inc_rx_index(u32 *index, const int count)
 373 {
 374         /* sizeof(struct rx_desc) != sizeof(struct cmd_desc) */
 375         *index += count * sizeof(struct rx_desc);
 376         *index %= RX_ENTRIES * sizeof(struct rx_desc);
 377 }
 378
 379 static int
 380 typhoon_reset(void __iomem *ioaddr, int wait_type)
 381 {
 382         int i, err = 0;
 383         int timeout;
 384
 385         if(wait_type == WaitNoSleep)
 386                 timeout = TYPHOON_RESET_TIMEOUT_NOSLEEP;
 387         else
 388                 timeout = TYPHOON_RESET_TIMEOUT_SLEEP;
 389
 390         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 391         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 392
 393         iowrite32(TYPHOON_RESET_ALL, ioaddr + TYPHOON_REG_SOFT_RESET);
 394         typhoon_post_pci_writes(ioaddr);
 395         udelay(1);
 396         iowrite32(TYPHOON_RESET_NONE, ioaddr + TYPHOON_REG_SOFT_RESET);
 397
 398         if(wait_type != NoWait) {
 399                 for(i = 0; i < timeout; i++) {
 400                         if(ioread32(ioaddr + TYPHOON_REG_STATUS) ==
 401                            TYPHOON_STATUS_WAITING_FOR_HOST)
 402                                 goto out;
 403
 404                         if(wait_type == WaitSleep)
 405                                 schedule_timeout_uninterruptible(1);
 406                         else
 407                                 udelay(TYPHOON_UDELAY);
 408                 }
 409
 410                 err = -ETIMEDOUT;
 411         }
 412
 413 out:
 414         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
 415         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
 416
 417         /* The 3XP seems to need a little extra time to complete the load
 418          * of the sleep image before we can reliably boot it. Failure to
 419          * do this occasionally results in a hung adapter after boot in
 420          * typhoon_init_one() while trying to read the MAC address or
 421          * putting the card to sleep. 3Com's driver waits 5ms, but
 422          * that seems to be overkill. However, if we can sleep, we might
 423          * as well give it that much time. Otherwise, we'll give it 500us,
 424          * which should be enough (I've see it work well at 100us, but still
 425          * saw occasional problems.)
 426          */
 427         if(wait_type == WaitSleep)
 428                 msleep(5);
 429         else
 430                 udelay(500);
 431         return err;
 432 }
 433
 434 static int
 435 typhoon_wait_status(void __iomem *ioaddr, u32 wait_value)
 436 {
 437         int i, err = 0;
 438
 439         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
 440                 if(ioread32(ioaddr + TYPHOON_REG_STATUS) == wait_value)
 441                         goto out;
 442                 udelay(TYPHOON_UDELAY);
 443         }
 444
 445         err = -ETIMEDOUT;
 446
 447 out:
 448         return err;
 449 }
 450
 451 static inline void
 452 typhoon_media_status(struct net_device *dev, struct resp_desc *resp)
 453 {
 454         if(resp->parm1 & TYPHOON_MEDIA_STAT_NO_LINK)
 455                 netif_carrier_off(dev);
 456         else
 457                 netif_carrier_on(dev);
 458 }
 459
 460 static inline void
 461 typhoon_hello(struct typhoon *tp)
 462 {
 463         struct basic_ring *ring = &tp->cmdRing;
 464         struct cmd_desc *cmd;
 465
 466         /* We only get a hello request if we've not sent anything to the
 467          * card in a long while. If the lock is held, then we're in the
 468          * process of issuing a command, so we don't need to respond.
 469          */
 470         if(spin_trylock(&tp->command_lock)) {
 471                 cmd = (struct cmd_desc *)(ring->ringBase + ring->lastWrite);
 472                 typhoon_inc_cmd_index(&ring->lastWrite, 1);
 473
 474                 INIT_COMMAND_NO_RESPONSE(cmd, TYPHOON_CMD_HELLO_RESP);
 475                 wmb();
 476                 iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 477                 spin_unlock(&tp->command_lock);
 478         }
 479 }
 480
 481 static int
 482 typhoon_process_response(struct typhoon *tp, int resp_size,
 483                                 struct resp_desc *resp_save)
 484 {
 485         struct typhoon_indexes *indexes = tp->indexes;
 486         struct resp_desc *resp;
 487         u8 *base = tp->respRing.ringBase;
 488         int count, len, wrap_len;
 489         u32 cleared;
 490         u32 ready;
 491
 492         cleared = le32_to_cpu(indexes->respCleared);
 493         ready = le32_to_cpu(indexes->respReady);
 494         while(cleared != ready) {
 495                 resp = (struct resp_desc *)(base + cleared);
 496                 count = resp->numDesc + 1;
 497                 if(resp_save && resp->seqNo) {
 498                         if(count > resp_size) {
 499                                 resp_save->flags = TYPHOON_RESP_ERROR;
 500                                 goto cleanup;
 501                         }
 502
 503                         wrap_len = 0;
 504                         len = count * sizeof(*resp);
 505                         if(unlikely(cleared + len > RESPONSE_RING_SIZE)) {
 506                                 wrap_len = cleared + len - RESPONSE_RING_SIZE;
 507                                 len = RESPONSE_RING_SIZE - cleared;
 508                         }
 509
 510                         memcpy(resp_save, resp, len);
 511                         if(unlikely(wrap_len)) {
 512                                 resp_save += len / sizeof(*resp);
 513                                 memcpy(resp_save, base, wrap_len);
 514                         }
 515
 516                         resp_save = NULL;
 517                 } else if(resp->cmd == TYPHOON_CMD_READ_MEDIA_STATUS) {
 518                         typhoon_media_status(tp->dev, resp);
 519                 } else if(resp->cmd == TYPHOON_CMD_HELLO_RESP) {
 520                         typhoon_hello(tp);
 521                 } else {
 522                         netdev_err(tp->dev,
 523                                    "dumping unexpected response 0x%04x:%d:0x%02x:0x%04x:%08x:%08x\n",
 524                                    le16_to_cpu(resp->cmd),
 525                                    resp->numDesc, resp->flags,
 526                                    le16_to_cpu(resp->parm1),
 527                                    le32_to_cpu(resp->parm2),
 528                                    le32_to_cpu(resp->parm3));
 529                 }
 530
 531 cleanup:
 532                 typhoon_inc_resp_index(&cleared, count);
 533         }
 534
 535         indexes->respCleared = cpu_to_le32(cleared);
 536         wmb();
 537         return resp_save == NULL;
 538 }
 539
 540 static inline int
 541 typhoon_num_free(int lastWrite, int lastRead, int ringSize)
 542 {
 543         /* this works for all descriptors but rx_desc, as they are a
 544          * different size than the cmd_desc -- everyone else is the same
 545          */
 546         lastWrite /= sizeof(struct cmd_desc);
 547         lastRead /= sizeof(struct cmd_desc);
 548         return (ringSize + lastRead - lastWrite - 1) % ringSize;
 549 }
 550
 551 static inline int
 552 typhoon_num_free_cmd(struct typhoon *tp)
 553 {
 554         int lastWrite = tp->cmdRing.lastWrite;
 555         int cmdCleared = le32_to_cpu(tp->indexes->cmdCleared);
 556
 557         return typhoon_num_free(lastWrite, cmdCleared, COMMAND_ENTRIES);
 558 }
 559
 560 static inline int
 561 typhoon_num_free_resp(struct typhoon *tp)
 562 {
 563         int respReady = le32_to_cpu(tp->indexes->respReady);
 564         int respCleared = le32_to_cpu(tp->indexes->respCleared);
 565
 566         return typhoon_num_free(respReady, respCleared, RESPONSE_ENTRIES);
 567 }
 568
 569 static inline int
 570 typhoon_num_free_tx(struct transmit_ring *ring)
 571 {
 572         /* if we start using the Hi Tx ring, this needs updating */
 573         return typhoon_num_free(ring->lastWrite, ring->lastRead, TXLO_ENTRIES);
 574 }
 575
 576 static int
 577 typhoon_issue_command(struct typhoon *tp, int num_cmd, struct cmd_desc *cmd,
 578                       int num_resp, struct resp_desc *resp)
 579 {
 580         struct typhoon_indexes *indexes = tp->indexes;
 581         struct basic_ring *ring = &tp->cmdRing;
 582         struct resp_desc local_resp;
 583         int i, err = 0;
 584         int got_resp;
 585         int freeCmd, freeResp;
 586         int len, wrap_len;
 587
 588         spin_lock(&tp->command_lock);
 589
 590         freeCmd = typhoon_num_free_cmd(tp);
 591         freeResp = typhoon_num_free_resp(tp);
 592
 593         if(freeCmd < num_cmd || freeResp < num_resp) {
 594                 netdev_err(tp->dev, "no descs for cmd, had (needed) %d (%d) cmd, %d (%d) resp\n",
 595                            freeCmd, num_cmd, freeResp, num_resp);
 596                 err = -ENOMEM;
 597                 goto out;
 598         }
 599
 600         if(cmd->flags & TYPHOON_CMD_RESPOND) {
 601                 /* If we're expecting a response, but the caller hasn't given
 602                  * us a place to put it, we'll provide one.
 603                  */
 604                 tp->awaiting_resp = 1;
 605                 if(resp == NULL) {
 606                         resp = &local_resp;
 607                         num_resp = 1;
 608                 }
 609         }
 610
 611         wrap_len = 0;
 612         len = num_cmd * sizeof(*cmd);
 613         if(unlikely(ring->lastWrite + len > COMMAND_RING_SIZE)) {
 614                 wrap_len = ring->lastWrite + len - COMMAND_RING_SIZE;
 615                 len = COMMAND_RING_SIZE - ring->lastWrite;
 616         }
 617
 618         memcpy(ring->ringBase + ring->lastWrite, cmd, len);
 619         if(unlikely(wrap_len)) {
 620                 struct cmd_desc *wrap_ptr = cmd;
 621                 wrap_ptr += len / sizeof(*cmd);
 622                 memcpy(ring->ringBase, wrap_ptr, wrap_len);
 623         }
 624
 625         typhoon_inc_cmd_index(&ring->lastWrite, num_cmd);
 626
 627         /* "I feel a presence... another warrior is on the mesa."
 628          */
 629         wmb();
 630         iowrite32(ring->lastWrite, tp->ioaddr + TYPHOON_REG_CMD_READY);
 631         typhoon_post_pci_writes(tp->ioaddr);
 632
 633         if((cmd->flags & TYPHOON_CMD_RESPOND) == 0)
 634                 goto out;
 635
 636         /* Ugh. We'll be here about 8ms, spinning our thumbs, unable to
 637          * preempt or do anything other than take interrupts. So, don't
 638          * wait for a response unless you have to.
 639          *
 640          * I've thought about trying to sleep here, but we're called
 641          * from many contexts that don't allow that. Also, given the way
 642          * 3Com has implemented irq coalescing, we would likely timeout --
 643          * this has been observed in real life!
 644          *
 645          * The big killer is we have to wait to get stats from the card,
 646          * though we could go to a periodic refresh of those if we don't
 647          * mind them getting somewhat stale. The rest of the waiting
 648          * commands occur during open/close/suspend/resume, so they aren't
 649          * time critical. Creating SAs in the future will also have to
 650          * wait here.
 651          */
 652         got_resp = 0;
 653         for(i = 0; i < TYPHOON_WAIT_TIMEOUT && !got_resp; i++) {
 654                 if(indexes->respCleared != indexes->respReady)
 655                         got_resp = typhoon_process_response(tp, num_resp,
 656                                                                 resp);
 657                 udelay(TYPHOON_UDELAY);
 658         }
 659
 660         if(!got_resp) {
 661                 err = -ETIMEDOUT;
 662                 goto out;
 663         }
 664
 665         /* Collect the error response even if we don't care about the
 666          * rest of the response
 667          */
 668         if(resp->flags & TYPHOON_RESP_ERROR)
 669                 err = -EIO;
 670
 671 out:
 672         if(tp->awaiting_resp) {
 673                 tp->awaiting_resp = 0;
 674                 smp_wmb();
 675
 676                 /* Ugh. If a response was added to the ring between
 677                  * the call to typhoon_process_response() and the clearing
 678                  * of tp->awaiting_resp, we could have missed the interrupt
 679                  * and it could hang in the ring an indeterminate amount of
 680                  * time. So, check for it, and interrupt ourselves if this
 681                  * is the case.
 682                  */
 683                 if(indexes->respCleared != indexes->respReady)
 684                         iowrite32(1, tp->ioaddr + TYPHOON_REG_SELF_INTERRUPT);
 685         }
 686
 687         spin_unlock(&tp->command_lock);
 688         return err;
 689 }
 690
 691 static inline void
 692 typhoon_tso_fill(struct sk_buff *skb, struct transmit_ring *txRing,
 693                         u32 ring_dma)
 694 {
 695         struct tcpopt_desc *tcpd;
 696         u32 tcpd_offset = ring_dma;
 697
 698         tcpd = (struct tcpopt_desc *) (txRing->ringBase + txRing->lastWrite);
 699         tcpd_offset += txRing->lastWrite;
 700         tcpd_offset += offsetof(struct tcpopt_desc, bytesTx);
 701         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 702
 703         tcpd->flags = TYPHOON_OPT_DESC | TYPHOON_OPT_TCP_SEG;
 704         tcpd->numDesc = 1;
 705         tcpd->mss_flags = cpu_to_le16(skb_tso_size(skb));
 706         tcpd->mss_flags |= TYPHOON_TSO_FIRST | TYPHOON_TSO_LAST;
 707         tcpd->respAddrLo = cpu_to_le32(tcpd_offset);
 708         tcpd->bytesTx = cpu_to_le32(skb->len);
 709         tcpd->status = 0;
 710 }
 711
 712 static netdev_tx_t
 713 typhoon_start_tx(struct sk_buff *skb, struct net_device *dev)
 714 {
 715         struct typhoon *tp = netdev_priv(dev);
 716         struct transmit_ring *txRing;
 717         struct tx_desc *txd, *first_txd;
 718         dma_addr_t skb_dma;
 719         int numDesc;
 720
 721         /* we have two rings to choose from, but we only use txLo for now
 722          * If we start using the Hi ring as well, we'll need to update
 723          * typhoon_stop_runtime(), typhoon_interrupt(), typhoon_num_free_tx(),
 724          * and TXHI_ENTRIES to match, as well as update the TSO code below
 725          * to get the right DMA address
 726          */
 727         txRing = &tp->txLoRing;
 728
 729         /* We need one descriptor for each fragment of the sk_buff, plus the
 730          * one for the ->data area of it.
 731          *
 732          * The docs say a maximum of 16 fragment descriptors per TCP option
 733          * descriptor, then make a new packet descriptor and option descriptor
 734          * for the next 16 fragments. The engineers say just an option
 735          * descriptor is needed. I've tested up to 26 fragments with a single
 736          * packet descriptor/option descriptor combo, so I use that for now.
 737          *
 738          * If problems develop with TSO, check this first.
 739          */
 740         numDesc = skb_shinfo(skb)->nr_frags + 1;
 741         if (skb_is_gso(skb))
 742                 numDesc++;
 743
 744         /* When checking for free space in the ring, we need to also
 745          * account for the initial Tx descriptor, and we always must leave
 746          * at least one descriptor unused in the ring so that it doesn't
 747          * wrap and look empty.
 748          *
 749          * The only time we should loop here is when we hit the race
 750          * between marking the queue awake and updating the cleared index.
 751          * Just loop and it will appear. This comes from the acenic driver.
 752          */
 753         while(unlikely(typhoon_num_free_tx(txRing) < (numDesc + 2)))
 754                 smp_rmb();
 755
 756         first_txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 757         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 758
 759         first_txd->flags = TYPHOON_TX_DESC | TYPHOON_DESC_VALID;
 760         first_txd->numDesc = 0;
 761         first_txd->len = 0;
 762         first_txd->tx_addr = (u64)((unsigned long) skb);
 763         first_txd->processFlags = 0;
 764
 765         if(skb->ip_summed == CHECKSUM_PARTIAL) {
 766                 /* The 3XP will figure out if this is UDP/TCP */
 767                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_CHKSUM;
 768                 first_txd->processFlags |= TYPHOON_TX_PF_UDP_CHKSUM;
 769                 first_txd->processFlags |= TYPHOON_TX_PF_IP_CHKSUM;
 770         }
 771
 772         if(vlan_tx_tag_present(skb)) {
 773                 first_txd->processFlags |=
 774                     TYPHOON_TX_PF_INSERT_VLAN | TYPHOON_TX_PF_VLAN_PRIORITY;
 775                 first_txd->processFlags |=
 776                     cpu_to_le32(htons(vlan_tx_tag_get(skb)) <<
 777                                 TYPHOON_TX_PF_VLAN_TAG_SHIFT);
 778         }
 779
 780         if (skb_is_gso(skb)) {
 781                 first_txd->processFlags |= TYPHOON_TX_PF_TCP_SEGMENT;
 782                 first_txd->numDesc++;
 783
 784                 typhoon_tso_fill(skb, txRing, tp->txlo_dma_addr);
 785         }
 786
 787         txd = (struct tx_desc *) (txRing->ringBase + txRing->lastWrite);
 788         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 789
 790         /* No need to worry about padding packet -- the firmware pads
 791          * it with zeros to ETH_ZLEN for us.
 792          */
 793         if(skb_shinfo(skb)->nr_frags == 0) {
 794                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, skb->len,
 795                                        PCI_DMA_TODEVICE);
 796                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 797                 txd->len = cpu_to_le16(skb->len);
 798                 txd->frag.addr = cpu_to_le32(skb_dma);
 799                 txd->frag.addrHi = 0;
 800                 first_txd->numDesc++;
 801         } else {
 802                 int i, len;
 803
 804                 len = skb_headlen(skb);
 805                 skb_dma = pci_map_single(tp->tx_pdev, skb->data, len,
 806                                          PCI_DMA_TODEVICE);
 807                 txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 808                 txd->len = cpu_to_le16(len);
 809                 txd->frag.addr = cpu_to_le32(skb_dma);
 810                 txd->frag.addrHi = 0;
 811                 first_txd->numDesc++;
 812
 813                 for(i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
 814                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
 815                         void *frag_addr;
 816
 817                         txd = (struct tx_desc *) (txRing->ringBase +
 818                                                 txRing->lastWrite);
 819                         typhoon_inc_tx_index(&txRing->lastWrite, 1);
 820
 821                         len = frag->size;
 822                         frag_addr = (void *) page_address(frag->page) +
 823                                                 frag->page_offset;
 824                         skb_dma = pci_map_single(tp->tx_pdev, frag_addr, len,
 825                                          PCI_DMA_TODEVICE);
 826                         txd->flags = TYPHOON_FRAG_DESC | TYPHOON_DESC_VALID;
 827                         txd->len = cpu_to_le16(len);
 828                         txd->frag.addr = cpu_to_le32(skb_dma);
 829                         txd->frag.addrHi = 0;
 830                         first_txd->numDesc++;
 831                 }
 832         }
 833
 834         /* Kick the 3XP
 835          */
 836         wmb();
 837         iowrite32(txRing->lastWrite, tp->tx_ioaddr + txRing->writeRegister);
 838
 839         /* If we don't have room to put the worst case packet on the
 840          * queue, then we must stop the queue. We need 2 extra
 841          * descriptors -- one to prevent ring wrap, and one for the
 842          * Tx header.
 843          */
 844         numDesc = MAX_SKB_FRAGS + TSO_NUM_DESCRIPTORS + 1;
 845
 846         if(typhoon_num_free_tx(txRing) < (numDesc + 2)) {
 847                 netif_stop_queue(dev);
 848
 849                 /* A Tx complete IRQ could have gotten between, making
 850                  * the ring free again. Only need to recheck here, since
 851                  * Tx is serialized.
 852                  */
 853                 if(typhoon_num_free_tx(txRing) >= (numDesc + 2))
 854                         netif_wake_queue(dev);
 855         }
 856
 857         return NETDEV_TX_OK;
 858 }
 859
 860 static void
 861 typhoon_set_rx_mode(struct net_device *dev)
 862 {
 863         struct typhoon *tp = netdev_priv(dev);
 864         struct cmd_desc xp_cmd;
 865         u32 mc_filter[2];
 866         __le16 filter;
 867
 868         filter = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
 869         if(dev->flags & IFF_PROMISC) {
 870                 filter |= TYPHOON_RX_FILTER_PROMISCOUS;
 871         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
 872                   (dev->flags & IFF_ALLMULTI)) {
 873                 /* Too many to match, or accept all multicasts. */
 874                 filter |= TYPHOON_RX_FILTER_ALL_MCAST;
 875         } else if (!netdev_mc_empty(dev)) {
 876                 struct netdev_hw_addr *ha;
 877
 878                 memset(mc_filter, 0, sizeof(mc_filter));
 879                 netdev_for_each_mc_addr(ha, dev) {
 880                         int bit = ether_crc(ETH_ALEN, ha->addr) & 0x3f;
 881                         mc_filter[bit >> 5] |= 1 << (bit & 0x1f);
 882                 }
 883
 884                 INIT_COMMAND_NO_RESPONSE(&xp_cmd,
 885                                          TYPHOON_CMD_SET_MULTICAST_HASH);
 886                 xp_cmd.parm1 = TYPHOON_MCAST_HASH_SET;
 887                 xp_cmd.parm2 = cpu_to_le32(mc_filter[0]);
 888                 xp_cmd.parm3 = cpu_to_le32(mc_filter[1]);
 889                 typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 890
 891                 filter |= TYPHOON_RX_FILTER_MCAST_HASH;
 892         }
 893
 894         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
 895         xp_cmd.parm1 = filter;
 896         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
 897 }
 898
 899 static int
 900 typhoon_do_get_stats(struct typhoon *tp)
 901 {
 902         struct net_device_stats *stats = &tp->stats;
 903         struct net_device_stats *saved = &tp->stats_saved;
 904         struct cmd_desc xp_cmd;
 905         struct resp_desc xp_resp[7];
 906         struct stats_resp *s = (struct stats_resp *) xp_resp;
 907         int err;
 908
 909         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_STATS);
 910         err = typhoon_issue_command(tp, 1, &xp_cmd, 7, xp_resp);
 911         if(err < 0)
 912                 return err;
 913
 914         /* 3Com's Linux driver uses txMultipleCollisions as it's
 915          * collisions value, but there is some other collision info as well...
 916          *
 917          * The extra status reported would be a good candidate for
 918          * ethtool_ops->get_{strings,stats}()
 919          */
 920         stats->tx_packets = le32_to_cpu(s->txPackets) +
 921                         saved->tx_packets;
 922         stats->tx_bytes = le64_to_cpu(s->txBytes) +
 923                         saved->tx_bytes;
 924         stats->tx_errors = le32_to_cpu(s->txCarrierLost) +
 925                         saved->tx_errors;
 926         stats->tx_carrier_errors = le32_to_cpu(s->txCarrierLost) +
 927                         saved->tx_carrier_errors;
 928         stats->collisions = le32_to_cpu(s->txMultipleCollisions) +
 929                         saved->collisions;
 930         stats->rx_packets = le32_to_cpu(s->rxPacketsGood) +
 931                         saved->rx_packets;
 932         stats->rx_bytes = le64_to_cpu(s->rxBytesGood) +
 933                         saved->rx_bytes;
 934         stats->rx_fifo_errors = le32_to_cpu(s->rxFifoOverruns) +
 935                         saved->rx_fifo_errors;
 936         stats->rx_errors = le32_to_cpu(s->rxFifoOverruns) +
 937                         le32_to_cpu(s->BadSSD) + le32_to_cpu(s->rxCrcErrors) +
 938                         saved->rx_errors;
 939         stats->rx_crc_errors = le32_to_cpu(s->rxCrcErrors) +
 940                         saved->rx_crc_errors;
 941         stats->rx_length_errors = le32_to_cpu(s->rxOversized) +
 942                         saved->rx_length_errors;
 943         tp->speed = (s->linkStatus & TYPHOON_LINK_100MBPS) ?
 944                         SPEED_100 : SPEED_10;
 945         tp->duplex = (s->linkStatus & TYPHOON_LINK_FULL_DUPLEX) ?
 946                         DUPLEX_FULL : DUPLEX_HALF;
 947
 948         return 0;
 949 }
 950
 951 static struct net_device_stats *
 952 typhoon_get_stats(struct net_device *dev)
 953 {
 954         struct typhoon *tp = netdev_priv(dev);
 955         struct net_device_stats *stats = &tp->stats;
 956         struct net_device_stats *saved = &tp->stats_saved;
 957
 958         smp_rmb();
 959         if(tp->card_state == Sleeping)
 960                 return saved;
 961
 962         if(typhoon_do_get_stats(tp) < 0) {
 963                 netdev_err(dev, "error getting stats\n");
 964                 return saved;
 965         }
 966
 967         return stats;
 968 }
 969
 970 static int
 971 typhoon_set_mac_address(struct net_device *dev, void *addr)
 972 {
 973         struct sockaddr *saddr = (struct sockaddr *) addr;
 974
 975         if(netif_running(dev))
 976                 return -EBUSY;
 977
 978         memcpy(dev->dev_addr, saddr->sa_data, dev->addr_len);
 979         return 0;
 980 }
 981
 982 static void
 983 typhoon_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
 984 {
 985         struct typhoon *tp = netdev_priv(dev);
 986         struct pci_dev *pci_dev = tp->pdev;
 987         struct cmd_desc xp_cmd;
 988         struct resp_desc xp_resp[3];
 989
 990         smp_rmb();
 991         if(tp->card_state == Sleeping) {
 992                 strcpy(info->fw_version, "Sleep image");
 993         } else {
 994                 INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
 995                 if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
 996                         strcpy(info->fw_version, "Unknown runtime");
 997                 } else {
 998                         u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
 999                         snprintf(info->fw_version, 32, "%02x.%03x.%03x",
1000                                  sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
1001                                  sleep_ver & 0xfff);
1002                 }
1003         }
1004
1005         strcpy(info->driver, KBUILD_MODNAME);
1006         strcpy(info->bus_info, pci_name(pci_dev));
1007 }
1008
1009 static int
1010 typhoon_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1011 {
1012         struct typhoon *tp = netdev_priv(dev);
1013
1014         cmd->supported = SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
1015                                 SUPPORTED_Autoneg;
1016
1017         switch (tp->xcvr_select) {
1018         case TYPHOON_XCVR_10HALF:
1019                 cmd->advertising = ADVERTISED_10baseT_Half;
1020                 break;
1021         case TYPHOON_XCVR_10FULL:
1022                 cmd->advertising = ADVERTISED_10baseT_Full;
1023                 break;
1024         case TYPHOON_XCVR_100HALF:
1025                 cmd->advertising = ADVERTISED_100baseT_Half;
1026                 break;
1027         case TYPHOON_XCVR_100FULL:
1028                 cmd->advertising = ADVERTISED_100baseT_Full;
1029                 break;
1030         case TYPHOON_XCVR_AUTONEG:
1031                 cmd->advertising = ADVERTISED_10baseT_Half |
1032                                             ADVERTISED_10baseT_Full |
1033                                             ADVERTISED_100baseT_Half |
1034                                             ADVERTISED_100baseT_Full |
1035                                             ADVERTISED_Autoneg;
1036                 break;
1037         }
1038
1039         if(tp->capabilities & TYPHOON_FIBER) {
1040                 cmd->supported |= SUPPORTED_FIBRE;
1041                 cmd->advertising |= ADVERTISED_FIBRE;
1042                 cmd->port = PORT_FIBRE;
1043         } else {
1044                 cmd->supported |= SUPPORTED_10baseT_Half |
1045                                         SUPPORTED_10baseT_Full |
1046                                         SUPPORTED_TP;
1047                 cmd->advertising |= ADVERTISED_TP;
1048                 cmd->port = PORT_TP;
1049         }
1050
1051         /* need to get stats to make these link speed/duplex valid */
1052         typhoon_do_get_stats(tp);
1053         cmd->speed = tp->speed;
1054         cmd->duplex = tp->duplex;
1055         cmd->phy_address = 0;
1056         cmd->transceiver = XCVR_INTERNAL;
1057         if(tp->xcvr_select == TYPHOON_XCVR_AUTONEG)
1058                 cmd->autoneg = AUTONEG_ENABLE;
1059         else
1060                 cmd->autoneg = AUTONEG_DISABLE;
1061         cmd->maxtxpkt = 1;
1062         cmd->maxrxpkt = 1;
1063
1064         return 0;
1065 }
1066
1067 static int
1068 typhoon_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1069 {
1070         struct typhoon *tp = netdev_priv(dev);
1071         struct cmd_desc xp_cmd;
1072         __le16 xcvr;
1073         int err;
1074
1075         err = -EINVAL;
1076         if(cmd->autoneg == AUTONEG_ENABLE) {
1077                 xcvr = TYPHOON_XCVR_AUTONEG;
1078         } else {
1079                 if(cmd->duplex == DUPLEX_HALF) {
1080                         if(cmd->speed == SPEED_10)
1081                                 xcvr = TYPHOON_XCVR_10HALF;
1082                         else if(cmd->speed == SPEED_100)
1083                                 xcvr = TYPHOON_XCVR_100HALF;
1084                         else
1085                                 goto out;
1086                 } else if(cmd->duplex == DUPLEX_FULL) {
1087                         if(cmd->speed == SPEED_10)
1088                                 xcvr = TYPHOON_XCVR_10FULL;
1089                         else if(cmd->speed == SPEED_100)
1090                                 xcvr = TYPHOON_XCVR_100FULL;
1091                         else
1092                                 goto out;
1093                 } else
1094                         goto out;
1095         }
1096
1097         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1098         xp_cmd.parm1 = xcvr;
1099         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1100         if(err < 0)
1101                 goto out;
1102
1103         tp->xcvr_select = xcvr;
1104         if(cmd->autoneg == AUTONEG_ENABLE) {
1105                 tp->speed = 0xff;       /* invalid */
1106                 tp->duplex = 0xff;      /* invalid */
1107         } else {
1108                 tp->speed = cmd->speed;
1109                 tp->duplex = cmd->duplex;
1110         }
1111
1112 out:
1113         return err;
1114 }
1115
1116 static void
1117 typhoon_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1118 {
1119         struct typhoon *tp = netdev_priv(dev);
1120
1121         wol->supported = WAKE_PHY | WAKE_MAGIC;
1122         wol->wolopts = 0;
1123         if(tp->wol_events & TYPHOON_WAKE_LINK_EVENT)
1124                 wol->wolopts |= WAKE_PHY;
1125         if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
1126                 wol->wolopts |= WAKE_MAGIC;
1127         memset(&wol->sopass, 0, sizeof(wol->sopass));
1128 }
1129
1130 static int
1131 typhoon_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1132 {
1133         struct typhoon *tp = netdev_priv(dev);
1134
1135         if(wol->wolopts & ~(WAKE_PHY | WAKE_MAGIC))
1136                 return -EINVAL;
1137
1138         tp->wol_events = 0;
1139         if(wol->wolopts & WAKE_PHY)
1140                 tp->wol_events |= TYPHOON_WAKE_LINK_EVENT;
1141         if(wol->wolopts & WAKE_MAGIC)
1142                 tp->wol_events |= TYPHOON_WAKE_MAGIC_PKT;
1143
1144         return 0;
1145 }
1146
1147 static void
1148 typhoon_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
1149 {
1150         ering->rx_max_pending = RXENT_ENTRIES;
1151         ering->rx_mini_max_pending = 0;
1152         ering->rx_jumbo_max_pending = 0;
1153         ering->tx_max_pending = TXLO_ENTRIES - 1;
1154
1155         ering->rx_pending = RXENT_ENTRIES;
1156         ering->rx_mini_pending = 0;
1157         ering->rx_jumbo_pending = 0;
1158         ering->tx_pending = TXLO_ENTRIES - 1;
1159 }
1160
1161 static const struct ethtool_ops typhoon_ethtool_ops = {
1162         .get_settings           = typhoon_get_settings,
1163         .set_settings           = typhoon_set_settings,
1164         .get_drvinfo            = typhoon_get_drvinfo,
1165         .get_wol                = typhoon_get_wol,
1166         .set_wol                = typhoon_set_wol,
1167         .get_link               = ethtool_op_get_link,
1168         .get_ringparam          = typhoon_get_ringparam,
1169 };
1170
1171 static int
1172 typhoon_wait_interrupt(void __iomem *ioaddr)
1173 {
1174         int i, err = 0;
1175
1176         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1177                 if(ioread32(ioaddr + TYPHOON_REG_INTR_STATUS) &
1178                    TYPHOON_INTR_BOOTCMD)
1179                         goto out;
1180                 udelay(TYPHOON_UDELAY);
1181         }
1182
1183         err = -ETIMEDOUT;
1184
1185 out:
1186         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1187         return err;
1188 }
1189
1190 #define shared_offset(x)        offsetof(struct typhoon_shared, x)
1191
1192 static void
1193 typhoon_init_interface(struct typhoon *tp)
1194 {
1195         struct typhoon_interface *iface = &tp->shared->iface;
1196         dma_addr_t shared_dma;
1197
1198         memset(tp->shared, 0, sizeof(struct typhoon_shared));
1199
1200         /* The *Hi members of iface are all init'd to zero by the memset().
1201          */
1202         shared_dma = tp->shared_dma + shared_offset(indexes);
1203         iface->ringIndex = cpu_to_le32(shared_dma);
1204
1205         shared_dma = tp->shared_dma + shared_offset(txLo);
1206         iface->txLoAddr = cpu_to_le32(shared_dma);
1207         iface->txLoSize = cpu_to_le32(TXLO_ENTRIES * sizeof(struct tx_desc));
1208
1209         shared_dma = tp->shared_dma + shared_offset(txHi);
1210         iface->txHiAddr = cpu_to_le32(shared_dma);
1211         iface->txHiSize = cpu_to_le32(TXHI_ENTRIES * sizeof(struct tx_desc));
1212
1213         shared_dma = tp->shared_dma + shared_offset(rxBuff);
1214         iface->rxBuffAddr = cpu_to_le32(shared_dma);
1215         iface->rxBuffSize = cpu_to_le32(RXFREE_ENTRIES *
1216                                         sizeof(struct rx_free));
1217
1218         shared_dma = tp->shared_dma + shared_offset(rxLo);
1219         iface->rxLoAddr = cpu_to_le32(shared_dma);
1220         iface->rxLoSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1221
1222         shared_dma = tp->shared_dma + shared_offset(rxHi);
1223         iface->rxHiAddr = cpu_to_le32(shared_dma);
1224         iface->rxHiSize = cpu_to_le32(RX_ENTRIES * sizeof(struct rx_desc));
1225
1226         shared_dma = tp->shared_dma + shared_offset(cmd);
1227         iface->cmdAddr = cpu_to_le32(shared_dma);
1228         iface->cmdSize = cpu_to_le32(COMMAND_RING_SIZE);
1229
1230         shared_dma = tp->shared_dma + shared_offset(resp);
1231         iface->respAddr = cpu_to_le32(shared_dma);
1232         iface->respSize = cpu_to_le32(RESPONSE_RING_SIZE);
1233
1234         shared_dma = tp->shared_dma + shared_offset(zeroWord);
1235         iface->zeroAddr = cpu_to_le32(shared_dma);
1236
1237         tp->indexes = &tp->shared->indexes;
1238         tp->txLoRing.ringBase = (u8 *) tp->shared->txLo;
1239         tp->txHiRing.ringBase = (u8 *) tp->shared->txHi;
1240         tp->rxLoRing.ringBase = (u8 *) tp->shared->rxLo;
1241         tp->rxHiRing.ringBase = (u8 *) tp->shared->rxHi;
1242         tp->rxBuffRing.ringBase = (u8 *) tp->shared->rxBuff;
1243         tp->cmdRing.ringBase = (u8 *) tp->shared->cmd;
1244         tp->respRing.ringBase = (u8 *) tp->shared->resp;
1245
1246         tp->txLoRing.writeRegister = TYPHOON_REG_TX_LO_READY;
1247         tp->txHiRing.writeRegister = TYPHOON_REG_TX_HI_READY;
1248
1249         tp->txlo_dma_addr = le32_to_cpu(iface->txLoAddr);
1250         tp->card_state = Sleeping;
1251
1252         tp->offload = TYPHOON_OFFLOAD_IP_CHKSUM | TYPHOON_OFFLOAD_TCP_CHKSUM;
1253         tp->offload |= TYPHOON_OFFLOAD_UDP_CHKSUM | TSO_OFFLOAD_ON;
1254         tp->offload |= TYPHOON_OFFLOAD_VLAN;
1255
1256         spin_lock_init(&tp->command_lock);
1257
1258         /* Force the writes to the shared memory area out before continuing. */
1259         wmb();
1260 }
1261
1262 static void
1263 typhoon_init_rings(struct typhoon *tp)
1264 {
1265         memset(tp->indexes, 0, sizeof(struct typhoon_indexes));
1266
1267         tp->txLoRing.lastWrite = 0;
1268         tp->txHiRing.lastWrite = 0;
1269         tp->rxLoRing.lastWrite = 0;
1270         tp->rxHiRing.lastWrite = 0;
1271         tp->rxBuffRing.lastWrite = 0;
1272         tp->cmdRing.lastWrite = 0;
1273         tp->respRing.lastWrite = 0;
1274
1275         tp->txLoRing.lastRead = 0;
1276         tp->txHiRing.lastRead = 0;
1277 }
1278
1279 static const struct firmware *typhoon_fw;
1280
1281 static int
1282 typhoon_request_firmware(struct typhoon *tp)
1283 {
1284         const struct typhoon_file_header *fHdr;
1285         const struct typhoon_section_header *sHdr;
1286         const u8 *image_data;
1287         u32 numSections;
1288         u32 section_len;
1289         u32 remaining;
1290         int err;
1291
1292         if (typhoon_fw)
1293                 return 0;
1294
1295         err = request_firmware(&typhoon_fw, FIRMWARE_NAME, &tp->pdev->dev);
1296         if (err) {
1297                 netdev_err(tp->dev, "Failed to load firmware \"%s\"\n",
1298                            FIRMWARE_NAME);
1299                 return err;
1300         }
1301
1302         image_data = (u8 *) typhoon_fw->data;
1303         remaining = typhoon_fw->size;
1304         if (remaining < sizeof(struct typhoon_file_header))
1305                 goto invalid_fw;
1306
1307         fHdr = (struct typhoon_file_header *) image_data;
1308         if (memcmp(fHdr->tag, "TYPHOON", 8))
1309                 goto invalid_fw;
1310
1311         numSections = le32_to_cpu(fHdr->numSections);
1312         image_data += sizeof(struct typhoon_file_header);
1313         remaining -= sizeof(struct typhoon_file_header);
1314
1315         while (numSections--) {
1316                 if (remaining < sizeof(struct typhoon_section_header))
1317                         goto invalid_fw;
1318
1319                 sHdr = (struct typhoon_section_header *) image_data;
1320                 image_data += sizeof(struct typhoon_section_header);
1321                 section_len = le32_to_cpu(sHdr->len);
1322
1323                 if (remaining < section_len)
1324                         goto invalid_fw;
1325
1326                 image_data += section_len;
1327                 remaining -= section_len;
1328         }
1329
1330         return 0;
1331
1332 invalid_fw:
1333         netdev_err(tp->dev, "Invalid firmware image\n");
1334         release_firmware(typhoon_fw);
1335         typhoon_fw = NULL;
1336         return -EINVAL;
1337 }
1338
1339 static int
1340 typhoon_download_firmware(struct typhoon *tp)
1341 {
1342         void __iomem *ioaddr = tp->ioaddr;
1343         struct pci_dev *pdev = tp->pdev;
1344         const struct typhoon_file_header *fHdr;
1345         const struct typhoon_section_header *sHdr;
1346         const u8 *image_data;
1347         void *dpage;
1348         dma_addr_t dpage_dma;
1349         __sum16 csum;
1350         u32 irqEnabled;
1351         u32 irqMasked;
1352         u32 numSections;
1353         u32 section_len;
1354         u32 len;
1355         u32 load_addr;
1356         u32 hmac;
1357         int i;
1358         int err;
1359
1360         image_data = (u8 *) typhoon_fw->data;
1361         fHdr = (struct typhoon_file_header *) image_data;
1362
1363         /* Cannot just map the firmware image using pci_map_single() as
1364          * the firmware is vmalloc()'d and may not be physically contiguous,
1365          * so we allocate some consistent memory to copy the sections into.
1366          */
1367         err = -ENOMEM;
1368         dpage = pci_alloc_consistent(pdev, PAGE_SIZE, &dpage_dma);
1369         if(!dpage) {
1370                 netdev_err(tp->dev, "no DMA mem for firmware\n");
1371                 goto err_out;
1372         }
1373
1374         irqEnabled = ioread32(ioaddr + TYPHOON_REG_INTR_ENABLE);
1375         iowrite32(irqEnabled | TYPHOON_INTR_BOOTCMD,
1376                ioaddr + TYPHOON_REG_INTR_ENABLE);
1377         irqMasked = ioread32(ioaddr + TYPHOON_REG_INTR_MASK);
1378         iowrite32(irqMasked | TYPHOON_INTR_BOOTCMD,
1379                ioaddr + TYPHOON_REG_INTR_MASK);
1380
1381         err = -ETIMEDOUT;
1382         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
1383                 netdev_err(tp->dev, "card ready timeout\n");
1384                 goto err_out_irq;
1385         }
1386
1387         numSections = le32_to_cpu(fHdr->numSections);
1388         load_addr = le32_to_cpu(fHdr->startAddr);
1389
1390         iowrite32(TYPHOON_INTR_BOOTCMD, ioaddr + TYPHOON_REG_INTR_STATUS);
1391         iowrite32(load_addr, ioaddr + TYPHOON_REG_DOWNLOAD_BOOT_ADDR);
1392         hmac = le32_to_cpu(fHdr->hmacDigest[0]);
1393         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_0);
1394         hmac = le32_to_cpu(fHdr->hmacDigest[1]);
1395         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_1);
1396         hmac = le32_to_cpu(fHdr->hmacDigest[2]);
1397         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_2);
1398         hmac = le32_to_cpu(fHdr->hmacDigest[3]);
1399         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_3);
1400         hmac = le32_to_cpu(fHdr->hmacDigest[4]);
1401         iowrite32(hmac, ioaddr + TYPHOON_REG_DOWNLOAD_HMAC_4);
1402         typhoon_post_pci_writes(ioaddr);
1403         iowrite32(TYPHOON_BOOTCMD_RUNTIME_IMAGE, ioaddr + TYPHOON_REG_COMMAND);
1404
1405         image_data += sizeof(struct typhoon_file_header);
1406
1407         /* The ioread32() in typhoon_wait_interrupt() will force the
1408          * last write to the command register to post, so
1409          * we don't need a typhoon_post_pci_writes() after it.
1410          */
1411         for(i = 0; i < numSections; i++) {
1412                 sHdr = (struct typhoon_section_header *) image_data;
1413                 image_data += sizeof(struct typhoon_section_header);
1414                 load_addr = le32_to_cpu(sHdr->startAddr);
1415                 section_len = le32_to_cpu(sHdr->len);
1416
1417                 while(section_len) {
1418                         len = min_t(u32, section_len, PAGE_SIZE);
1419
1420                         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1421                            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1422                            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1423                                 netdev_err(tp->dev, "segment ready timeout\n");
1424                                 goto err_out_irq;
1425                         }
1426
1427                         /* Do an pseudo IPv4 checksum on the data -- first
1428                          * need to convert each u16 to cpu order before
1429                          * summing. Fortunately, due to the properties of
1430                          * the checksum, we can do this once, at the end.
1431                          */
1432                         csum = csum_fold(csum_partial_copy_nocheck(image_data,
1433                                                                    dpage, len,
1434                                                                    0));
1435
1436                         iowrite32(len, ioaddr + TYPHOON_REG_BOOT_LENGTH);
1437                         iowrite32(le16_to_cpu((__force __le16)csum),
1438                                         ioaddr + TYPHOON_REG_BOOT_CHECKSUM);
1439                         iowrite32(load_addr,
1440                                         ioaddr + TYPHOON_REG_BOOT_DEST_ADDR);
1441                         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_DATA_HI);
1442                         iowrite32(dpage_dma, ioaddr + TYPHOON_REG_BOOT_DATA_LO);
1443                         typhoon_post_pci_writes(ioaddr);
1444                         iowrite32(TYPHOON_BOOTCMD_SEG_AVAILABLE,
1445                                         ioaddr + TYPHOON_REG_COMMAND);
1446
1447                         image_data += len;
1448                         load_addr += len;
1449                         section_len -= len;
1450                 }
1451         }
1452
1453         if(typhoon_wait_interrupt(ioaddr) < 0 ||
1454            ioread32(ioaddr + TYPHOON_REG_STATUS) !=
1455            TYPHOON_STATUS_WAITING_FOR_SEGMENT) {
1456                 netdev_err(tp->dev, "final segment ready timeout\n");
1457                 goto err_out_irq;
1458         }
1459
1460         iowrite32(TYPHOON_BOOTCMD_DNLD_COMPLETE, ioaddr + TYPHOON_REG_COMMAND);
1461
1462         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1463                 netdev_err(tp->dev, "boot ready timeout, status 0x%0x\n",
1464                            ioread32(ioaddr + TYPHOON_REG_STATUS));
1465                 goto err_out_irq;
1466         }
1467
1468         err = 0;
1469
1470 err_out_irq:
1471         iowrite32(irqMasked, ioaddr + TYPHOON_REG_INTR_MASK);
1472         iowrite32(irqEnabled, ioaddr + TYPHOON_REG_INTR_ENABLE);
1473
1474         pci_free_consistent(pdev, PAGE_SIZE, dpage, dpage_dma);
1475
1476 err_out:
1477         return err;
1478 }
1479
1480 static int
1481 typhoon_boot_3XP(struct typhoon *tp, u32 initial_status)
1482 {
1483         void __iomem *ioaddr = tp->ioaddr;
1484
1485         if(typhoon_wait_status(ioaddr, initial_status) < 0) {
1486                 netdev_err(tp->dev, "boot ready timeout\n");
1487                 goto out_timeout;
1488         }
1489
1490         iowrite32(0, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_HI);
1491         iowrite32(tp->shared_dma, ioaddr + TYPHOON_REG_BOOT_RECORD_ADDR_LO);
1492         typhoon_post_pci_writes(ioaddr);
1493         iowrite32(TYPHOON_BOOTCMD_REG_BOOT_RECORD,
1494                                 ioaddr + TYPHOON_REG_COMMAND);
1495
1496         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_RUNNING) < 0) {
1497                 netdev_err(tp->dev, "boot finish timeout (status 0x%x)\n",
1498                            ioread32(ioaddr + TYPHOON_REG_STATUS));
1499                 goto out_timeout;
1500         }
1501
1502         /* Clear the Transmit and Command ready registers
1503          */
1504         iowrite32(0, ioaddr + TYPHOON_REG_TX_HI_READY);
1505         iowrite32(0, ioaddr + TYPHOON_REG_CMD_READY);
1506         iowrite32(0, ioaddr + TYPHOON_REG_TX_LO_READY);
1507         typhoon_post_pci_writes(ioaddr);
1508         iowrite32(TYPHOON_BOOTCMD_BOOT, ioaddr + TYPHOON_REG_COMMAND);
1509
1510         return 0;
1511
1512 out_timeout:
1513         return -ETIMEDOUT;
1514 }
1515
1516 static u32
1517 typhoon_clean_tx(struct typhoon *tp, struct transmit_ring *txRing,
1518                         volatile __le32 * index)
1519 {
1520         u32 lastRead = txRing->lastRead;
1521         struct tx_desc *tx;
1522         dma_addr_t skb_dma;
1523         int dma_len;
1524         int type;
1525
1526         while(lastRead != le32_to_cpu(*index)) {
1527                 tx = (struct tx_desc *) (txRing->ringBase + lastRead);
1528                 type = tx->flags & TYPHOON_TYPE_MASK;
1529
1530                 if(type == TYPHOON_TX_DESC) {
1531                         /* This tx_desc describes a packet.
1532                          */
1533                         unsigned long ptr = tx->tx_addr;
1534                         struct sk_buff *skb = (struct sk_buff *) ptr;
1535                         dev_kfree_skb_irq(skb);
1536                 } else if(type == TYPHOON_FRAG_DESC) {
1537                         /* This tx_desc describes a memory mapping. Free it.
1538                          */
1539                         skb_dma = (dma_addr_t) le32_to_cpu(tx->frag.addr);
1540                         dma_len = le16_to_cpu(tx->len);
1541                         pci_unmap_single(tp->pdev, skb_dma, dma_len,
1542                                        PCI_DMA_TODEVICE);
1543                 }
1544
1545                 tx->flags = 0;
1546                 typhoon_inc_tx_index(&lastRead, 1);
1547         }
1548
1549         return lastRead;
1550 }
1551
1552 static void
1553 typhoon_tx_complete(struct typhoon *tp, struct transmit_ring *txRing,
1554                         volatile __le32 * index)
1555 {
1556         u32 lastRead;
1557         int numDesc = MAX_SKB_FRAGS + 1;
1558
1559         /* This will need changing if we start to use the Hi Tx ring. */
1560         lastRead = typhoon_clean_tx(tp, txRing, index);
1561         if(netif_queue_stopped(tp->dev) && typhoon_num_free(txRing->lastWrite,
1562                                 lastRead, TXLO_ENTRIES) > (numDesc + 2))
1563                 netif_wake_queue(tp->dev);
1564
1565         txRing->lastRead = lastRead;
1566         smp_wmb();
1567 }
1568
1569 static void
1570 typhoon_recycle_rx_skb(struct typhoon *tp, u32 idx)
1571 {
1572         struct typhoon_indexes *indexes = tp->indexes;
1573         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1574         struct basic_ring *ring = &tp->rxBuffRing;
1575         struct rx_free *r;
1576
1577         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1578                                 le32_to_cpu(indexes->rxBuffCleared)) {
1579                 /* no room in ring, just drop the skb
1580                  */
1581                 dev_kfree_skb_any(rxb->skb);
1582                 rxb->skb = NULL;
1583                 return;
1584         }
1585
1586         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1587         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1588         r->virtAddr = idx;
1589         r->physAddr = cpu_to_le32(rxb->dma_addr);
1590
1591         /* Tell the card about it */
1592         wmb();
1593         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1594 }
1595
1596 static int
1597 typhoon_alloc_rx_skb(struct typhoon *tp, u32 idx)
1598 {
1599         struct typhoon_indexes *indexes = tp->indexes;
1600         struct rxbuff_ent *rxb = &tp->rxbuffers[idx];
1601         struct basic_ring *ring = &tp->rxBuffRing;
1602         struct rx_free *r;
1603         struct sk_buff *skb;
1604         dma_addr_t dma_addr;
1605
1606         rxb->skb = NULL;
1607
1608         if((ring->lastWrite + sizeof(*r)) % (RXFREE_ENTRIES * sizeof(*r)) ==
1609                                 le32_to_cpu(indexes->rxBuffCleared))
1610                 return -ENOMEM;
1611
1612         skb = dev_alloc_skb(PKT_BUF_SZ);
1613         if(!skb)
1614                 return -ENOMEM;
1615
1616 #if 0
1617         /* Please, 3com, fix the firmware to allow DMA to a unaligned
1618          * address! Pretty please?
1619          */
1620         skb_reserve(skb, 2);
1621 #endif
1622
1623         skb->dev = tp->dev;
1624         dma_addr = pci_map_single(tp->pdev, skb->data,
1625                                   PKT_BUF_SZ, PCI_DMA_FROMDEVICE);
1626
1627         /* Since no card does 64 bit DAC, the high bits will never
1628          * change from zero.
1629          */
1630         r = (struct rx_free *) (ring->ringBase + ring->lastWrite);
1631         typhoon_inc_rxfree_index(&ring->lastWrite, 1);
1632         r->virtAddr = idx;
1633         r->physAddr = cpu_to_le32(dma_addr);
1634         rxb->skb = skb;
1635         rxb->dma_addr = dma_addr;
1636
1637         /* Tell the card about it */
1638         wmb();
1639         indexes->rxBuffReady = cpu_to_le32(ring->lastWrite);
1640         return 0;
1641 }
1642
1643 static int
1644 typhoon_rx(struct typhoon *tp, struct basic_ring *rxRing, volatile __le32 * ready,
1645            volatile __le32 * cleared, int budget)
1646 {
1647         struct rx_desc *rx;
1648         struct sk_buff *skb, *new_skb;
1649         struct rxbuff_ent *rxb;
1650         dma_addr_t dma_addr;
1651         u32 local_ready;
1652         u32 rxaddr;
1653         int pkt_len;
1654         u32 idx;
1655         __le32 csum_bits;
1656         int received;
1657
1658         received = 0;
1659         local_ready = le32_to_cpu(*ready);
1660         rxaddr = le32_to_cpu(*cleared);
1661         while(rxaddr != local_ready && budget > 0) {
1662                 rx = (struct rx_desc *) (rxRing->ringBase + rxaddr);
1663                 idx = rx->addr;
1664                 rxb = &tp->rxbuffers[idx];
1665                 skb = rxb->skb;
1666                 dma_addr = rxb->dma_addr;
1667
1668                 typhoon_inc_rx_index(&rxaddr, 1);
1669
1670                 if(rx->flags & TYPHOON_RX_ERROR) {
1671                         typhoon_recycle_rx_skb(tp, idx);
1672                         continue;
1673                 }
1674
1675                 pkt_len = le16_to_cpu(rx->frameLen);
1676
1677                 if(pkt_len < rx_copybreak &&
1678                    (new_skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1679                         skb_reserve(new_skb, 2);
1680                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr,
1681                                                     PKT_BUF_SZ,
1682                                                     PCI_DMA_FROMDEVICE);
1683                         skb_copy_to_linear_data(new_skb, skb->data, pkt_len);
1684                         pci_dma_sync_single_for_device(tp->pdev, dma_addr,
1685                                                        PKT_BUF_SZ,
1686                                                        PCI_DMA_FROMDEVICE);
1687                         skb_put(new_skb, pkt_len);
1688                         typhoon_recycle_rx_skb(tp, idx);
1689                 } else {
1690                         new_skb = skb;
1691                         skb_put(new_skb, pkt_len);
1692                         pci_unmap_single(tp->pdev, dma_addr, PKT_BUF_SZ,
1693                                        PCI_DMA_FROMDEVICE);
1694                         typhoon_alloc_rx_skb(tp, idx);
1695                 }
1696                 new_skb->protocol = eth_type_trans(new_skb, tp->dev);
1697                 csum_bits = rx->rxStatus & (TYPHOON_RX_IP_CHK_GOOD |
1698                         TYPHOON_RX_UDP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD);
1699                 if(csum_bits ==
1700                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_TCP_CHK_GOOD) ||
1701                    csum_bits ==
1702                    (TYPHOON_RX_IP_CHK_GOOD | TYPHOON_RX_UDP_CHK_GOOD)) {
1703                         new_skb->ip_summed = CHECKSUM_UNNECESSARY;
1704                 } else
1705                         skb_checksum_none_assert(new_skb);
1706
1707                 if (rx->rxStatus & TYPHOON_RX_VLAN)
1708                         __vlan_hwaccel_put_tag(new_skb,
1709                                                ntohl(rx->vlanTag) & 0xffff);
1710                 netif_receive_skb(new_skb);
1711
1712                 received++;
1713                 budget--;
1714         }
1715         *cleared = cpu_to_le32(rxaddr);
1716
1717         return received;
1718 }
1719
1720 static void
1721 typhoon_fill_free_ring(struct typhoon *tp)
1722 {
1723         u32 i;
1724
1725         for(i = 0; i < RXENT_ENTRIES; i++) {
1726                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1727                 if(rxb->skb)
1728                         continue;
1729                 if(typhoon_alloc_rx_skb(tp, i) < 0)
1730                         break;
1731         }
1732 }
1733
1734 static int
1735 typhoon_poll(struct napi_struct *napi, int budget)
1736 {
1737         struct typhoon *tp = container_of(napi, struct typhoon, napi);
1738         struct typhoon_indexes *indexes = tp->indexes;
1739         int work_done;
1740
1741         rmb();
1742         if(!tp->awaiting_resp && indexes->respReady != indexes->respCleared)
1743                         typhoon_process_response(tp, 0, NULL);
1744
1745         if(le32_to_cpu(indexes->txLoCleared) != tp->txLoRing.lastRead)
1746                 typhoon_tx_complete(tp, &tp->txLoRing, &indexes->txLoCleared);
1747
1748         work_done = 0;
1749
1750         if(indexes->rxHiCleared != indexes->rxHiReady) {
1751                 work_done += typhoon_rx(tp, &tp->rxHiRing, &indexes->rxHiReady,
1752                                         &indexes->rxHiCleared, budget);
1753         }
1754
1755         if(indexes->rxLoCleared != indexes->rxLoReady) {
1756                 work_done += typhoon_rx(tp, &tp->rxLoRing, &indexes->rxLoReady,
1757                                         &indexes->rxLoCleared, budget - work_done);
1758         }
1759
1760         if(le32_to_cpu(indexes->rxBuffCleared) == tp->rxBuffRing.lastWrite) {
1761                 /* rxBuff ring is empty, try to fill it. */
1762                 typhoon_fill_free_ring(tp);
1763         }
1764
1765         if (work_done < budget) {
1766                 napi_complete(napi);
1767                 iowrite32(TYPHOON_INTR_NONE,
1768                                 tp->ioaddr + TYPHOON_REG_INTR_MASK);
1769                 typhoon_post_pci_writes(tp->ioaddr);
1770         }
1771
1772         return work_done;
1773 }
1774
1775 static irqreturn_t
1776 typhoon_interrupt(int irq, void *dev_instance)
1777 {
1778         struct net_device *dev = dev_instance;
1779         struct typhoon *tp = netdev_priv(dev);
1780         void __iomem *ioaddr = tp->ioaddr;
1781         u32 intr_status;
1782
1783         intr_status = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
1784         if(!(intr_status & TYPHOON_INTR_HOST_INT))
1785                 return IRQ_NONE;
1786
1787         iowrite32(intr_status, ioaddr + TYPHOON_REG_INTR_STATUS);
1788
1789         if (napi_schedule_prep(&tp->napi)) {
1790                 iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
1791                 typhoon_post_pci_writes(ioaddr);
1792                 __napi_schedule(&tp->napi);
1793         } else {
1794                 netdev_err(dev, "Error, poll already scheduled\n");
1795         }
1796         return IRQ_HANDLED;
1797 }
1798
1799 static void
1800 typhoon_free_rx_rings(struct typhoon *tp)
1801 {
1802         u32 i;
1803
1804         for(i = 0; i < RXENT_ENTRIES; i++) {
1805                 struct rxbuff_ent *rxb = &tp->rxbuffers[i];
1806                 if(rxb->skb) {
1807                         pci_unmap_single(tp->pdev, rxb->dma_addr, PKT_BUF_SZ,
1808                                        PCI_DMA_FROMDEVICE);
1809                         dev_kfree_skb(rxb->skb);
1810                         rxb->skb = NULL;
1811                 }
1812         }
1813 }
1814
1815 static int
1816 typhoon_sleep(struct typhoon *tp, pci_power_t state, __le16 events)
1817 {
1818         struct pci_dev *pdev = tp->pdev;
1819         void __iomem *ioaddr = tp->ioaddr;
1820         struct cmd_desc xp_cmd;
1821         int err;
1822
1823         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_ENABLE_WAKE_EVENTS);
1824         xp_cmd.parm1 = events;
1825         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1826         if(err < 0) {
1827                 netdev_err(tp->dev, "typhoon_sleep(): wake events cmd err %d\n",
1828                            err);
1829                 return err;
1830         }
1831
1832         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_GOTO_SLEEP);
1833         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1834         if(err < 0) {
1835                 netdev_err(tp->dev, "typhoon_sleep(): sleep cmd err %d\n", err);
1836                 return err;
1837         }
1838
1839         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_SLEEPING) < 0)
1840                 return -ETIMEDOUT;
1841
1842         /* Since we cannot monitor the status of the link while sleeping,
1843          * tell the world it went away.
1844          */
1845         netif_carrier_off(tp->dev);
1846
1847         pci_enable_wake(tp->pdev, state, 1);
1848         pci_disable_device(pdev);
1849         return pci_set_power_state(pdev, state);
1850 }
1851
1852 static int
1853 typhoon_wakeup(struct typhoon *tp, int wait_type)
1854 {
1855         struct pci_dev *pdev = tp->pdev;
1856         void __iomem *ioaddr = tp->ioaddr;
1857
1858         pci_set_power_state(pdev, PCI_D0);
1859         pci_restore_state(pdev);
1860
1861         /* Post 2.x.x versions of the Sleep Image require a reset before
1862          * we can download the Runtime Image. But let's not make users of
1863          * the old firmware pay for the reset.
1864          */
1865         iowrite32(TYPHOON_BOOTCMD_WAKEUP, ioaddr + TYPHOON_REG_COMMAND);
1866         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_WAITING_FOR_HOST) < 0 ||
1867                         (tp->capabilities & TYPHOON_WAKEUP_NEEDS_RESET))
1868                 return typhoon_reset(ioaddr, wait_type);
1869
1870         return 0;
1871 }
1872
1873 static int
1874 typhoon_start_runtime(struct typhoon *tp)
1875 {
1876         struct net_device *dev = tp->dev;
1877         void __iomem *ioaddr = tp->ioaddr;
1878         struct cmd_desc xp_cmd;
1879         int err;
1880
1881         typhoon_init_rings(tp);
1882         typhoon_fill_free_ring(tp);
1883
1884         err = typhoon_download_firmware(tp);
1885         if(err < 0) {
1886                 netdev_err(tp->dev, "cannot load runtime on 3XP\n");
1887                 goto error_out;
1888         }
1889
1890         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_BOOT) < 0) {
1891                 netdev_err(tp->dev, "cannot boot 3XP\n");
1892                 err = -EIO;
1893                 goto error_out;
1894         }
1895
1896         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAX_PKT_SIZE);
1897         xp_cmd.parm1 = cpu_to_le16(PKT_BUF_SZ);
1898         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1899         if(err < 0)
1900                 goto error_out;
1901
1902         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
1903         xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
1904         xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
1905         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1906         if(err < 0)
1907                 goto error_out;
1908
1909         /* Disable IRQ coalescing -- we can reenable it when 3Com gives
1910          * us some more information on how to control it.
1911          */
1912         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_IRQ_COALESCE_CTRL);
1913         xp_cmd.parm1 = 0;
1914         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1915         if(err < 0)
1916                 goto error_out;
1917
1918         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_XCVR_SELECT);
1919         xp_cmd.parm1 = tp->xcvr_select;
1920         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1921         if(err < 0)
1922                 goto error_out;
1923
1924         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_VLAN_TYPE_WRITE);
1925         xp_cmd.parm1 = cpu_to_le16(ETH_P_8021Q);
1926         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1927         if(err < 0)
1928                 goto error_out;
1929
1930         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_OFFLOAD_TASKS);
1931         xp_cmd.parm2 = tp->offload;
1932         xp_cmd.parm3 = tp->offload;
1933         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1934         if(err < 0)
1935                 goto error_out;
1936
1937         typhoon_set_rx_mode(dev);
1938
1939         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_ENABLE);
1940         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1941         if(err < 0)
1942                 goto error_out;
1943
1944         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_ENABLE);
1945         err = typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1946         if(err < 0)
1947                 goto error_out;
1948
1949         tp->card_state = Running;
1950         smp_wmb();
1951
1952         iowrite32(TYPHOON_INTR_ENABLE_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
1953         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_MASK);
1954         typhoon_post_pci_writes(ioaddr);
1955
1956         return 0;
1957
1958 error_out:
1959         typhoon_reset(ioaddr, WaitNoSleep);
1960         typhoon_free_rx_rings(tp);
1961         typhoon_init_rings(tp);
1962         return err;
1963 }
1964
1965 static int
1966 typhoon_stop_runtime(struct typhoon *tp, int wait_type)
1967 {
1968         struct typhoon_indexes *indexes = tp->indexes;
1969         struct transmit_ring *txLo = &tp->txLoRing;
1970         void __iomem *ioaddr = tp->ioaddr;
1971         struct cmd_desc xp_cmd;
1972         int i;
1973
1974         /* Disable interrupts early, since we can't schedule a poll
1975          * when called with !netif_running(). This will be posted
1976          * when we force the posting of the command.
1977          */
1978         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
1979
1980         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_RX_DISABLE);
1981         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1982
1983         /* Wait 1/2 sec for any outstanding transmits to occur
1984          * We'll cleanup after the reset if this times out.
1985          */
1986         for(i = 0; i < TYPHOON_WAIT_TIMEOUT; i++) {
1987                 if(indexes->txLoCleared == cpu_to_le32(txLo->lastWrite))
1988                         break;
1989                 udelay(TYPHOON_UDELAY);
1990         }
1991
1992         if(i == TYPHOON_WAIT_TIMEOUT)
1993                 netdev_err(tp->dev, "halt timed out waiting for Tx to complete\n");
1994
1995         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_TX_DISABLE);
1996         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
1997
1998         /* save the statistics so when we bring the interface up again,
1999          * the values reported to userspace are correct.
2000          */
2001         tp->card_state = Sleeping;
2002         smp_wmb();
2003         typhoon_do_get_stats(tp);
2004         memcpy(&tp->stats_saved, &tp->stats, sizeof(struct net_device_stats));
2005
2006         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_HALT);
2007         typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL);
2008
2009         if(typhoon_wait_status(ioaddr, TYPHOON_STATUS_HALTED) < 0)
2010                 netdev_err(tp->dev, "timed out waiting for 3XP to halt\n");
2011
2012         if(typhoon_reset(ioaddr, wait_type) < 0) {
2013                 netdev_err(tp->dev, "unable to reset 3XP\n");
2014                 return -ETIMEDOUT;
2015         }
2016
2017         /* cleanup any outstanding Tx packets */
2018         if(indexes->txLoCleared != cpu_to_le32(txLo->lastWrite)) {
2019                 indexes->txLoCleared = cpu_to_le32(txLo->lastWrite);
2020                 typhoon_clean_tx(tp, &tp->txLoRing, &indexes->txLoCleared);
2021         }
2022
2023         return 0;
2024 }
2025
2026 static void
2027 typhoon_tx_timeout(struct net_device *dev)
2028 {
2029         struct typhoon *tp = netdev_priv(dev);
2030
2031         if(typhoon_reset(tp->ioaddr, WaitNoSleep) < 0) {
2032                 netdev_warn(dev, "could not reset in tx timeout\n");
2033                 goto truly_dead;
2034         }
2035
2036         /* If we ever start using the Hi ring, it will need cleaning too */
2037         typhoon_clean_tx(tp, &tp->txLoRing, &tp->indexes->txLoCleared);
2038         typhoon_free_rx_rings(tp);
2039
2040         if(typhoon_start_runtime(tp) < 0) {
2041                 netdev_err(dev, "could not start runtime in tx timeout\n");
2042                 goto truly_dead;
2043         }
2044
2045         netif_wake_queue(dev);
2046         return;
2047
2048 truly_dead:
2049         /* Reset the hardware, and turn off carrier to avoid more timeouts */
2050         typhoon_reset(tp->ioaddr, NoWait);
2051         netif_carrier_off(dev);
2052 }
2053
2054 static int
2055 typhoon_open(struct net_device *dev)
2056 {
2057         struct typhoon *tp = netdev_priv(dev);
2058         int err;
2059
2060         err = typhoon_request_firmware(tp);
2061         if (err)
2062                 goto out;
2063
2064         err = typhoon_wakeup(tp, WaitSleep);
2065         if(err < 0) {
2066                 netdev_err(dev, "unable to wakeup device\n");
2067                 goto out_sleep;
2068         }
2069
2070         err = request_irq(dev->irq, typhoon_interrupt, IRQF_SHARED,
2071                                 dev->name, dev);
2072         if(err < 0)
2073                 goto out_sleep;
2074
2075         napi_enable(&tp->napi);
2076
2077         err = typhoon_start_runtime(tp);
2078         if(err < 0) {
2079                 napi_disable(&tp->napi);
2080                 goto out_irq;
2081         }
2082
2083         netif_start_queue(dev);
2084         return 0;
2085
2086 out_irq:
2087         free_irq(dev->irq, dev);
2088
2089 out_sleep:
2090         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2091                 netdev_err(dev, "unable to reboot into sleep img\n");
2092                 typhoon_reset(tp->ioaddr, NoWait);
2093                 goto out;
2094         }
2095
2096         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2097                 netdev_err(dev, "unable to go back to sleep\n");
2098
2099 out:
2100         return err;
2101 }
2102
2103 static int
2104 typhoon_close(struct net_device *dev)
2105 {
2106         struct typhoon *tp = netdev_priv(dev);
2107
2108         netif_stop_queue(dev);
2109         napi_disable(&tp->napi);
2110
2111         if(typhoon_stop_runtime(tp, WaitSleep) < 0)
2112                 netdev_err(dev, "unable to stop runtime\n");
2113
2114         /* Make sure there is no irq handler running on a different CPU. */
2115         free_irq(dev->irq, dev);
2116
2117         typhoon_free_rx_rings(tp);
2118         typhoon_init_rings(tp);
2119
2120         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0)
2121                 netdev_err(dev, "unable to boot sleep image\n");
2122
2123         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0)
2124                 netdev_err(dev, "unable to put card to sleep\n");
2125
2126         return 0;
2127 }
2128
2129 #ifdef CONFIG_PM
2130 static int
2131 typhoon_resume(struct pci_dev *pdev)
2132 {
2133         struct net_device *dev = pci_get_drvdata(pdev);
2134         struct typhoon *tp = netdev_priv(dev);
2135
2136         /* If we're down, resume when we are upped.
2137          */
2138         if(!netif_running(dev))
2139                 return 0;
2140
2141         if(typhoon_wakeup(tp, WaitNoSleep) < 0) {
2142                 netdev_err(dev, "critical: could not wake up in resume\n");
2143                 goto reset;
2144         }
2145
2146         if(typhoon_start_runtime(tp) < 0) {
2147                 netdev_err(dev, "critical: could not start runtime in resume\n");
2148                 goto reset;
2149         }
2150
2151         netif_device_attach(dev);
2152         return 0;
2153
2154 reset:
2155         typhoon_reset(tp->ioaddr, NoWait);
2156         return -EBUSY;
2157 }
2158
2159 static int
2160 typhoon_suspend(struct pci_dev *pdev, pm_message_t state)
2161 {
2162         struct net_device *dev = pci_get_drvdata(pdev);
2163         struct typhoon *tp = netdev_priv(dev);
2164         struct cmd_desc xp_cmd;
2165
2166         /* If we're down, we're already suspended.
2167          */
2168         if(!netif_running(dev))
2169                 return 0;
2170
2171         /* TYPHOON_OFFLOAD_VLAN is always on now, so this doesn't work */
2172         if(tp->wol_events & TYPHOON_WAKE_MAGIC_PKT)
2173                 netdev_warn(dev, "cannot do WAKE_MAGIC with VLAN offloading\n");
2174
2175         netif_device_detach(dev);
2176
2177         if(typhoon_stop_runtime(tp, WaitNoSleep) < 0) {
2178                 netdev_err(dev, "unable to stop runtime\n");
2179                 goto need_resume;
2180         }
2181
2182         typhoon_free_rx_rings(tp);
2183         typhoon_init_rings(tp);
2184
2185         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2186                 netdev_err(dev, "unable to boot sleep image\n");
2187                 goto need_resume;
2188         }
2189
2190         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_MAC_ADDRESS);
2191         xp_cmd.parm1 = cpu_to_le16(ntohs(*(__be16 *)&dev->dev_addr[0]));
2192         xp_cmd.parm2 = cpu_to_le32(ntohl(*(__be32 *)&dev->dev_addr[2]));
2193         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2194                 netdev_err(dev, "unable to set mac address in suspend\n");
2195                 goto need_resume;
2196         }
2197
2198         INIT_COMMAND_NO_RESPONSE(&xp_cmd, TYPHOON_CMD_SET_RX_FILTER);
2199         xp_cmd.parm1 = TYPHOON_RX_FILTER_DIRECTED | TYPHOON_RX_FILTER_BROADCAST;
2200         if(typhoon_issue_command(tp, 1, &xp_cmd, 0, NULL) < 0) {
2201                 netdev_err(dev, "unable to set rx filter in suspend\n");
2202                 goto need_resume;
2203         }
2204
2205         if(typhoon_sleep(tp, pci_choose_state(pdev, state), tp->wol_events) < 0) {
2206                 netdev_err(dev, "unable to put card to sleep\n");
2207                 goto need_resume;
2208         }
2209
2210         return 0;
2211
2212 need_resume:
2213         typhoon_resume(pdev);
2214         return -EBUSY;
2215 }
2216 #endif
2217
2218 static int __devinit
2219 typhoon_test_mmio(struct pci_dev *pdev)
2220 {
2221         void __iomem *ioaddr = pci_iomap(pdev, 1, 128);
2222         int mode = 0;
2223         u32 val;
2224
2225         if(!ioaddr)
2226                 goto out;
2227
2228         if(ioread32(ioaddr + TYPHOON_REG_STATUS) !=
2229                                 TYPHOON_STATUS_WAITING_FOR_HOST)
2230                 goto out_unmap;
2231
2232         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2233         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2234         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_ENABLE);
2235
2236         /* Ok, see if we can change our interrupt status register by
2237          * sending ourselves an interrupt. If so, then MMIO works.
2238          * The 50usec delay is arbitrary -- it could probably be smaller.
2239          */
2240         val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2241         if((val & TYPHOON_INTR_SELF) == 0) {
2242                 iowrite32(1, ioaddr + TYPHOON_REG_SELF_INTERRUPT);
2243                 ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2244                 udelay(50);
2245                 val = ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2246                 if(val & TYPHOON_INTR_SELF)
2247                         mode = 1;
2248         }
2249
2250         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_MASK);
2251         iowrite32(TYPHOON_INTR_ALL, ioaddr + TYPHOON_REG_INTR_STATUS);
2252         iowrite32(TYPHOON_INTR_NONE, ioaddr + TYPHOON_REG_INTR_ENABLE);
2253         ioread32(ioaddr + TYPHOON_REG_INTR_STATUS);
2254
2255 out_unmap:
2256         pci_iounmap(pdev, ioaddr);
2257
2258 out:
2259         if(!mode)
2260                 pr_info("%s: falling back to port IO\n", pci_name(pdev));
2261         return mode;
2262 }
2263
2264 static const struct net_device_ops typhoon_netdev_ops = {
2265         .ndo_open               = typhoon_open,
2266         .ndo_stop               = typhoon_close,
2267         .ndo_start_xmit         = typhoon_start_tx,
2268         .ndo_set_multicast_list = typhoon_set_rx_mode,
2269         .ndo_tx_timeout         = typhoon_tx_timeout,
2270         .ndo_get_stats          = typhoon_get_stats,
2271         .ndo_validate_addr      = eth_validate_addr,
2272         .ndo_set_mac_address    = typhoon_set_mac_address,
2273         .ndo_change_mtu         = eth_change_mtu,
2274 };
2275
2276 static int __devinit
2277 typhoon_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
2278 {
2279         struct net_device *dev;
2280         struct typhoon *tp;
2281         int card_id = (int) ent->driver_data;
2282         void __iomem *ioaddr;
2283         void *shared;
2284         dma_addr_t shared_dma;
2285         struct cmd_desc xp_cmd;
2286         struct resp_desc xp_resp[3];
2287         int err = 0;
2288         const char *err_msg;
2289
2290         dev = alloc_etherdev(sizeof(*tp));
2291         if(dev == NULL) {
2292                 err_msg = "unable to alloc new net device";
2293                 err = -ENOMEM;
2294                 goto error_out;
2295         }
2296         SET_NETDEV_DEV(dev, &pdev->dev);
2297
2298         err = pci_enable_device(pdev);
2299         if(err < 0) {
2300                 err_msg = "unable to enable device";
2301                 goto error_out_dev;
2302         }
2303
2304         err = pci_set_mwi(pdev);
2305         if(err < 0) {
2306                 err_msg = "unable to set MWI";
2307                 goto error_out_disable;
2308         }
2309
2310         err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
2311         if(err < 0) {
2312                 err_msg = "No usable DMA configuration";
2313                 goto error_out_mwi;
2314         }
2315
2316         /* sanity checks on IO and MMIO BARs
2317          */
2318         if(!(pci_resource_flags(pdev, 0) & IORESOURCE_IO)) {
2319                 err_msg = "region #1 not a PCI IO resource, aborting";
2320                 err = -ENODEV;
2321                 goto error_out_mwi;
2322         }
2323         if(pci_resource_len(pdev, 0) < 128) {
2324                 err_msg = "Invalid PCI IO region size, aborting";
2325                 err = -ENODEV;
2326                 goto error_out_mwi;
2327         }
2328         if(!(pci_resource_flags(pdev, 1) & IORESOURCE_MEM)) {
2329                 err_msg = "region #1 not a PCI MMIO resource, aborting";
2330                 err = -ENODEV;
2331                 goto error_out_mwi;
2332         }
2333         if(pci_resource_len(pdev, 1) < 128) {
2334                 err_msg = "Invalid PCI MMIO region size, aborting";
2335                 err = -ENODEV;
2336                 goto error_out_mwi;
2337         }
2338
2339         err = pci_request_regions(pdev, KBUILD_MODNAME);
2340         if(err < 0) {
2341                 err_msg = "could not request regions";
2342                 goto error_out_mwi;
2343         }
2344
2345         /* map our registers
2346          */
2347         if(use_mmio != 0 && use_mmio != 1)
2348                 use_mmio = typhoon_test_mmio(pdev);
2349
2350         ioaddr = pci_iomap(pdev, use_mmio, 128);
2351         if (!ioaddr) {
2352                 err_msg = "cannot remap registers, aborting";
2353                 err = -EIO;
2354                 goto error_out_regions;
2355         }
2356
2357         /* allocate pci dma space for rx and tx descriptor rings
2358          */
2359         shared = pci_alloc_consistent(pdev, sizeof(struct typhoon_shared),
2360                                       &shared_dma);
2361         if(!shared) {
2362                 err_msg = "could not allocate DMA memory";
2363                 err = -ENOMEM;
2364                 goto error_out_remap;
2365         }
2366
2367         dev->irq = pdev->irq;
2368         tp = netdev_priv(dev);
2369         tp->shared = (struct typhoon_shared *) shared;
2370         tp->shared_dma = shared_dma;
2371         tp->pdev = pdev;
2372         tp->tx_pdev = pdev;
2373         tp->ioaddr = ioaddr;
2374         tp->tx_ioaddr = ioaddr;
2375         tp->dev = dev;
2376
2377         /* Init sequence:
2378          * 1) Reset the adapter to clear any bad juju
2379          * 2) Reload the sleep image
2380          * 3) Boot the sleep image
2381          * 4) Get the hardware address.
2382          * 5) Put the card to sleep.
2383          */
2384         if (typhoon_reset(ioaddr, WaitSleep) < 0) {
2385                 err_msg = "could not reset 3XP";
2386                 err = -EIO;
2387                 goto error_out_dma;
2388         }
2389
2390         /* Now that we've reset the 3XP and are sure it's not going to
2391          * write all over memory, enable bus mastering, and save our
2392          * state for resuming after a suspend.
2393          */
2394         pci_set_master(pdev);
2395         pci_save_state(pdev);
2396
2397         typhoon_init_interface(tp);
2398         typhoon_init_rings(tp);
2399
2400         if(typhoon_boot_3XP(tp, TYPHOON_STATUS_WAITING_FOR_HOST) < 0) {
2401                 err_msg = "cannot boot 3XP sleep image";
2402                 err = -EIO;
2403                 goto error_out_reset;
2404         }
2405
2406         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_MAC_ADDRESS);
2407         if(typhoon_issue_command(tp, 1, &xp_cmd, 1, xp_resp) < 0) {
2408                 err_msg = "cannot read MAC address";
2409                 err = -EIO;
2410                 goto error_out_reset;
2411         }
2412
2413         *(__be16 *)&dev->dev_addr[0] = htons(le16_to_cpu(xp_resp[0].parm1));
2414         *(__be32 *)&dev->dev_addr[2] = htonl(le32_to_cpu(xp_resp[0].parm2));
2415
2416         if(!is_valid_ether_addr(dev->dev_addr)) {
2417                 err_msg = "Could not obtain valid ethernet address, aborting";
2418                 goto error_out_reset;
2419         }
2420
2421         /* Read the Sleep Image version last, so the response is valid
2422          * later when we print out the version reported.
2423          */
2424         INIT_COMMAND_WITH_RESPONSE(&xp_cmd, TYPHOON_CMD_READ_VERSIONS);
2425         if(typhoon_issue_command(tp, 1, &xp_cmd, 3, xp_resp) < 0) {
2426                 err_msg = "Could not get Sleep Image version";
2427                 goto error_out_reset;
2428         }
2429
2430         tp->capabilities = typhoon_card_info[card_id].capabilities;
2431         tp->xcvr_select = TYPHOON_XCVR_AUTONEG;
2432
2433         /* Typhoon 1.0 Sleep Images return one response descriptor to the
2434          * READ_VERSIONS command. Those versions are OK after waking up
2435          * from sleep without needing a reset. Typhoon 1.1+ Sleep Images
2436          * seem to need a little extra help to get started. Since we don't
2437          * know how to nudge it along, just kick it.
2438          */
2439         if(xp_resp[0].numDesc != 0)
2440                 tp->capabilities |= TYPHOON_WAKEUP_NEEDS_RESET;
2441
2442         if(typhoon_sleep(tp, PCI_D3hot, 0) < 0) {
2443                 err_msg = "cannot put adapter to sleep";
2444                 err = -EIO;
2445                 goto error_out_reset;
2446         }
2447
2448         /* The chip-specific entries in the device structure. */
2449         dev->netdev_ops         = &typhoon_netdev_ops;
2450         netif_napi_add(dev, &tp->napi, typhoon_poll, 16);
2451         dev->watchdog_timeo     = TX_TIMEOUT;
2452
2453         SET_ETHTOOL_OPS(dev, &typhoon_ethtool_ops);
2454
2455         /* We can handle scatter gather, up to 16 entries, and
2456          * we can do IP checksumming (only version 4, doh...)
2457          *
2458          * There's no way to turn off the RX VLAN offloading and stripping
2459          * on the current 3XP firmware -- it does not respect the offload
2460          * settings -- so we only allow the user to toggle the TX processing.
2461          */
2462         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
2463                 NETIF_F_HW_VLAN_TX;
2464         dev->features = dev->hw_features |
2465                 NETIF_F_HW_VLAN_RX | NETIF_F_RXCSUM;
2466
2467         if(register_netdev(dev) < 0) {
2468                 err_msg = "unable to register netdev";
2469                 goto error_out_reset;
2470         }
2471
2472         pci_set_drvdata(pdev, dev);
2473
2474         netdev_info(dev, "%s at %s 0x%llx, %pM\n",
2475                     typhoon_card_info[card_id].name,
2476                     use_mmio ? "MMIO" : "IO",
2477                     (unsigned long long)pci_resource_start(pdev, use_mmio),
2478                     dev->dev_addr);
2479
2480         /* xp_resp still contains the response to the READ_VERSIONS command.
2481          * For debugging, let the user know what version he has.
2482          */
2483         if(xp_resp[0].numDesc == 0) {
2484                 /* This is the Typhoon 1.0 type Sleep Image, last 16 bits
2485                  * of version is Month/Day of build.
2486                  */
2487                 u16 monthday = le32_to_cpu(xp_resp[0].parm2) & 0xffff;
2488                 netdev_info(dev, "Typhoon 1.0 Sleep Image built %02u/%02u/2000\n",
2489                             monthday >> 8, monthday & 0xff);
2490         } else if(xp_resp[0].numDesc == 2) {
2491                 /* This is the Typhoon 1.1+ type Sleep Image
2492                  */
2493                 u32 sleep_ver = le32_to_cpu(xp_resp[0].parm2);
2494                 u8 *ver_string = (u8 *) &xp_resp[1];
2495                 ver_string[25] = 0;
2496                 netdev_info(dev, "Typhoon 1.1+ Sleep Image version %02x.%03x.%03x %s\n",
2497                             sleep_ver >> 24, (sleep_ver >> 12) & 0xfff,
2498                             sleep_ver & 0xfff, ver_string);
2499         } else {
2500                 netdev_warn(dev, "Unknown Sleep Image version (%u:%04x)\n",
2501                             xp_resp[0].numDesc, le32_to_cpu(xp_resp[0].parm2));
2502         }
2503
2504         return 0;
2505
2506 error_out_reset:
2507         typhoon_reset(ioaddr, NoWait);
2508
2509 error_out_dma:
2510         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2511                             shared, shared_dma);
2512 error_out_remap:
2513         pci_iounmap(pdev, ioaddr);
2514 error_out_regions:
2515         pci_release_regions(pdev);
2516 error_out_mwi:
2517         pci_clear_mwi(pdev);
2518 error_out_disable:
2519         pci_disable_device(pdev);
2520 error_out_dev:
2521         free_netdev(dev);
2522 error_out:
2523         pr_err("%s: %s\n", pci_name(pdev), err_msg);
2524         return err;
2525 }
2526
2527 static void __devexit
2528 typhoon_remove_one(struct pci_dev *pdev)
2529 {
2530         struct net_device *dev = pci_get_drvdata(pdev);
2531         struct typhoon *tp = netdev_priv(dev);
2532
2533         unregister_netdev(dev);
2534         pci_set_power_state(pdev, PCI_D0);
2535         pci_restore_state(pdev);
2536         typhoon_reset(tp->ioaddr, NoWait);
2537         pci_iounmap(pdev, tp->ioaddr);
2538         pci_free_consistent(pdev, sizeof(struct typhoon_shared),
2539                             tp->shared, tp->shared_dma);
2540         pci_release_regions(pdev);
2541         pci_clear_mwi(pdev);
2542         pci_disable_device(pdev);
2543         pci_set_drvdata(pdev, NULL);
2544         free_netdev(dev);
2545 }
2546
2547 static struct pci_driver typhoon_driver = {
2548         .name           = KBUILD_MODNAME,
2549         .id_table       = typhoon_pci_tbl,
2550         .probe          = typhoon_init_one,
2551         .remove         = __devexit_p(typhoon_remove_one),
2552 #ifdef CONFIG_PM
2553         .suspend        = typhoon_suspend,
2554         .resume         = typhoon_resume,
2555 #endif
2556 };
2557
2558 static int __init
2559 typhoon_init(void)
2560 {
2561         return pci_register_driver(&typhoon_driver);
2562 }
2563
2564 static void __exit
2565 typhoon_cleanup(void)
2566 {
2567         if (typhoon_fw)
2568                 release_firmware(typhoon_fw);
2569         pci_unregister_driver(&typhoon_driver);
2570 }
2571
2572 module_init(typhoon_init);
2573 module_exit(typhoon_cleanup);