2 This program is free software; you can redistribute it and/or
3 modify it under the terms of the GNU General Public License
4 as published by the Free Software Foundation; either version 2
5 of the License, or (at your option) any later version.
7 This program is distributed in the hope that it will be useful,
8 but WITHOUT ANY WARRANTY; without even the implied warranty of
9 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 GNU General Public License for more details.
15 #define DRV_NAME "uli526x"
16 #define DRV_VERSION "0.9.3"
17 #define DRV_RELDATE "2005-7-29"
19 #include <linux/module.h>
21 #include <linux/kernel.h>
22 #include <linux/string.h>
23 #include <linux/timer.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/slab.h>
27 #include <linux/interrupt.h>
28 #include <linux/pci.h>
29 #include <linux/init.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/skbuff.h>
34 #include <linux/delay.h>
35 #include <linux/spinlock.h>
36 #include <linux/dma-mapping.h>
37 #include <linux/bitops.h>
39 #include <asm/processor.h>
42 #include <asm/uaccess.h>
45 /* Board/System/Debug information/definition ---------------- */
46 #define PCI_ULI5261_ID 0x526110B9 /* ULi M5261 ID*/
47 #define PCI_ULI5263_ID 0x526310B9 /* ULi M5263 ID*/
49 #define ULI526X_IO_SIZE 0x100
50 #define TX_DESC_CNT 0x20 /* Allocated Tx descriptors */
51 #define RX_DESC_CNT 0x30 /* Allocated Rx descriptors */
52 #define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
53 #define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
54 #define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
55 #define TX_BUF_ALLOC 0x600
56 #define RX_ALLOC_SIZE 0x620
57 #define ULI526X_RESET 1
59 #define CR6_DEFAULT 0x22200000
60 #define CR7_DEFAULT 0x180c1
61 #define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
62 #define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
63 #define MAX_PACKET_SIZE 1514
64 #define ULI5261_MAX_MULTICAST 14
65 #define RX_COPY_SIZE 100
66 #define MAX_CHECK_PACKET 0x8000
68 #define ULI526X_10MHF 0
69 #define ULI526X_100MHF 1
70 #define ULI526X_10MFD 4
71 #define ULI526X_100MFD 5
72 #define ULI526X_AUTO 8
74 #define ULI526X_TXTH_72 0x400000 /* TX TH 72 byte */
75 #define ULI526X_TXTH_96 0x404000 /* TX TH 96 byte */
76 #define ULI526X_TXTH_128 0x0000 /* TX TH 128 byte */
77 #define ULI526X_TXTH_256 0x4000 /* TX TH 256 byte */
78 #define ULI526X_TXTH_512 0x8000 /* TX TH 512 byte */
79 #define ULI526X_TXTH_1K 0xC000 /* TX TH 1K byte */
81 #define ULI526X_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
82 #define ULI526X_TX_TIMEOUT ((16*HZ)/2) /* tx packet time-out time 8 s" */
83 #define ULI526X_TX_KICK (4*HZ/2) /* tx packet Kick-out time 2 s" */
85 #define ULI526X_DBUG(dbug_now, msg, value) if (uli526x_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
87 #define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
90 /* CR9 definition: SROM/MII */
91 #define CR9_SROM_READ 0x4800
94 #define CR9_CRDOUT 0x8
95 #define SROM_DATA_0 0x0
96 #define SROM_DATA_1 0x4
97 #define PHY_DATA_1 0x20000
98 #define PHY_DATA_0 0x00000
99 #define MDCLKH 0x10000
101 #define PHY_POWER_DOWN 0x800
103 #define SROM_V41_CODE 0x14
105 #define SROM_CLK_WRITE(data, ioaddr) \
106 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
108 outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr); \
110 outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr); \
113 /* Structure/enum declaration ------------------------------- */
115 __le32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
116 char *tx_buf_ptr; /* Data for us */
117 struct tx_desc *next_tx_desc;
118 } __attribute__(( aligned(32) ));
121 __le32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
122 struct sk_buff *rx_skb_ptr; /* Data for us */
123 struct rx_desc *next_rx_desc;
124 } __attribute__(( aligned(32) ));
126 struct uli526x_board_info {
127 u32 chip_id; /* Chip vendor/Device ID */
128 struct net_device *next_dev; /* next device */
129 struct pci_dev *pdev; /* PCI device */
132 long ioaddr; /* I/O base address */
139 /* pointer for memory physical address */
140 dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
141 dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
142 dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
143 dma_addr_t first_tx_desc_dma;
144 dma_addr_t first_rx_desc_dma;
146 /* descriptor pointer */
147 unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
148 unsigned char *buf_pool_start; /* Tx buffer pool align dword */
149 unsigned char *desc_pool_ptr; /* descriptor pool memory */
150 struct tx_desc *first_tx_desc;
151 struct tx_desc *tx_insert_ptr;
152 struct tx_desc *tx_remove_ptr;
153 struct rx_desc *first_rx_desc;
154 struct rx_desc *rx_insert_ptr;
155 struct rx_desc *rx_ready_ptr; /* packet come pointer */
156 unsigned long tx_packet_cnt; /* transmitted packet count */
157 unsigned long rx_avail_cnt; /* available rx descriptor count */
158 unsigned long interval_rx_cnt; /* rx packet count a callback time */
161 u16 NIC_capability; /* NIC media capability */
162 u16 PHY_reg4; /* Saved Phyxcer register 4 value */
164 u8 media_mode; /* user specify media mode */
165 u8 op_mode; /* real work media mode */
167 u8 link_failed; /* Ever link failed */
168 u8 wait_reset; /* Hardware failed, need to reset */
169 struct timer_list timer;
171 /* System defined statistic counter */
172 struct net_device_stats stats;
174 /* Driver defined statistic counter */
175 unsigned long tx_fifo_underrun;
176 unsigned long tx_loss_carrier;
177 unsigned long tx_no_carrier;
178 unsigned long tx_late_collision;
179 unsigned long tx_excessive_collision;
180 unsigned long tx_jabber_timeout;
181 unsigned long reset_count;
182 unsigned long reset_cr8;
183 unsigned long reset_fatal;
184 unsigned long reset_TXtimeout;
187 unsigned char srom[128];
191 enum uli526x_offsets {
192 DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
193 DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
194 DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
198 enum uli526x_CR6_bits {
199 CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
200 CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
201 CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
204 /* Global variable declaration ----------------------------- */
205 static int __devinitdata printed_version;
206 static char version[] __devinitdata =
207 KERN_INFO DRV_NAME ": ULi M5261/M5263 net driver, version "
208 DRV_VERSION " (" DRV_RELDATE ")\n";
210 static int uli526x_debug;
211 static unsigned char uli526x_media_mode = ULI526X_AUTO;
212 static u32 uli526x_cr6_user_set;
214 /* For module input parameter */
219 /* function declaration ------------------------------------- */
220 static int uli526x_open(struct net_device *);
221 static int uli526x_start_xmit(struct sk_buff *, struct net_device *);
222 static int uli526x_stop(struct net_device *);
223 static struct net_device_stats * uli526x_get_stats(struct net_device *);
224 static void uli526x_set_filter_mode(struct net_device *);
225 static const struct ethtool_ops netdev_ethtool_ops;
226 static u16 read_srom_word(long, int);
227 static irqreturn_t uli526x_interrupt(int, void *);
228 #ifdef CONFIG_NET_POLL_CONTROLLER
229 static void uli526x_poll(struct net_device *dev);
231 static void uli526x_descriptor_init(struct uli526x_board_info *, unsigned long);
232 static void allocate_rx_buffer(struct uli526x_board_info *);
233 static void update_cr6(u32, unsigned long);
234 static void send_filter_frame(struct net_device *, int);
235 static u16 phy_read(unsigned long, u8, u8, u32);
236 static u16 phy_readby_cr10(unsigned long, u8, u8);
237 static void phy_write(unsigned long, u8, u8, u16, u32);
238 static void phy_writeby_cr10(unsigned long, u8, u8, u16);
239 static void phy_write_1bit(unsigned long, u32, u32);
240 static u16 phy_read_1bit(unsigned long, u32);
241 static u8 uli526x_sense_speed(struct uli526x_board_info *);
242 static void uli526x_process_mode(struct uli526x_board_info *);
243 static void uli526x_timer(unsigned long);
244 static void uli526x_rx_packet(struct net_device *, struct uli526x_board_info *);
245 static void uli526x_free_tx_pkt(struct net_device *, struct uli526x_board_info *);
246 static void uli526x_reuse_skb(struct uli526x_board_info *, struct sk_buff *);
247 static void uli526x_dynamic_reset(struct net_device *);
248 static void uli526x_free_rxbuffer(struct uli526x_board_info *);
249 static void uli526x_init(struct net_device *);
250 static void uli526x_set_phyxcer(struct uli526x_board_info *);
252 /* ULI526X network board routine ---------------------------- */
255 * Search ULI526X board, allocate space and register it
258 static int __devinit uli526x_init_one (struct pci_dev *pdev,
259 const struct pci_device_id *ent)
261 struct uli526x_board_info *db; /* board information structure */
262 struct net_device *dev;
265 ULI526X_DBUG(0, "uli526x_init_one()", 0);
267 if (!printed_version++)
270 /* Init network device */
271 dev = alloc_etherdev(sizeof(*db));
274 SET_NETDEV_DEV(dev, &pdev->dev);
276 if (pci_set_dma_mask(pdev, DMA_32BIT_MASK)) {
277 printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
282 /* Enable Master/IO access, Disable memory access */
283 err = pci_enable_device(pdev);
287 if (!pci_resource_start(pdev, 0)) {
288 printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
290 goto err_out_disable;
293 if (pci_resource_len(pdev, 0) < (ULI526X_IO_SIZE) ) {
294 printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
296 goto err_out_disable;
299 if (pci_request_regions(pdev, DRV_NAME)) {
300 printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
302 goto err_out_disable;
305 /* Init system & device */
306 db = netdev_priv(dev);
308 /* Allocate Tx/Rx descriptor memory */
309 db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
310 if(db->desc_pool_ptr == NULL)
315 db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
316 if(db->buf_pool_ptr == NULL)
322 db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
323 db->first_tx_desc_dma = db->desc_pool_dma_ptr;
324 db->buf_pool_start = db->buf_pool_ptr;
325 db->buf_pool_dma_start = db->buf_pool_dma_ptr;
327 db->chip_id = ent->driver_data;
328 db->ioaddr = pci_resource_start(pdev, 0);
333 dev->base_addr = db->ioaddr;
334 dev->irq = pdev->irq;
335 pci_set_drvdata(pdev, dev);
337 /* Register some necessary functions */
338 dev->open = &uli526x_open;
339 dev->hard_start_xmit = &uli526x_start_xmit;
340 dev->stop = &uli526x_stop;
341 dev->get_stats = &uli526x_get_stats;
342 dev->set_multicast_list = &uli526x_set_filter_mode;
343 dev->ethtool_ops = &netdev_ethtool_ops;
344 #ifdef CONFIG_NET_POLL_CONTROLLER
345 dev->poll_controller = &uli526x_poll;
347 spin_lock_init(&db->lock);
350 /* read 64 word srom data */
351 for (i = 0; i < 64; i++)
352 ((__le16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
354 /* Set Node address */
355 if(((u16 *) db->srom)[0] == 0xffff || ((u16 *) db->srom)[0] == 0) /* SROM absent, so read MAC address from ID Table */
357 outl(0x10000, db->ioaddr + DCR0); //Diagnosis mode
358 outl(0x1c0, db->ioaddr + DCR13); //Reset dianostic pointer port
359 outl(0, db->ioaddr + DCR14); //Clear reset port
360 outl(0x10, db->ioaddr + DCR14); //Reset ID Table pointer
361 outl(0, db->ioaddr + DCR14); //Clear reset port
362 outl(0, db->ioaddr + DCR13); //Clear CR13
363 outl(0x1b0, db->ioaddr + DCR13); //Select ID Table access port
364 //Read MAC address from CR14
365 for (i = 0; i < 6; i++)
366 dev->dev_addr[i] = inl(db->ioaddr + DCR14);
368 outl(0, db->ioaddr + DCR13); //Clear CR13
369 outl(0, db->ioaddr + DCR0); //Clear CR0
374 for (i = 0; i < 6; i++)
375 dev->dev_addr[i] = db->srom[20 + i];
377 err = register_netdev (dev);
381 printk(KERN_INFO "%s: ULi M%04lx at pci%s, %pM, irq %d.\n",
382 dev->name,ent->driver_data >> 16,pci_name(pdev),
383 dev->dev_addr, dev->irq);
385 pci_set_master(pdev);
390 pci_release_regions(pdev);
392 if(db->desc_pool_ptr)
393 pci_free_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20,
394 db->desc_pool_ptr, db->desc_pool_dma_ptr);
396 if(db->buf_pool_ptr != NULL)
397 pci_free_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
398 db->buf_pool_ptr, db->buf_pool_dma_ptr);
400 pci_disable_device(pdev);
402 pci_set_drvdata(pdev, NULL);
409 static void __devexit uli526x_remove_one (struct pci_dev *pdev)
411 struct net_device *dev = pci_get_drvdata(pdev);
412 struct uli526x_board_info *db = netdev_priv(dev);
414 ULI526X_DBUG(0, "uli526x_remove_one()", 0);
416 pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
417 DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
418 db->desc_pool_dma_ptr);
419 pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
420 db->buf_pool_ptr, db->buf_pool_dma_ptr);
421 unregister_netdev(dev);
422 pci_release_regions(pdev);
423 free_netdev(dev); /* free board information */
424 pci_set_drvdata(pdev, NULL);
425 pci_disable_device(pdev);
426 ULI526X_DBUG(0, "uli526x_remove_one() exit", 0);
431 * Open the interface.
432 * The interface is opened whenever "ifconfig" activates it.
435 static int uli526x_open(struct net_device *dev)
438 struct uli526x_board_info *db = netdev_priv(dev);
440 ULI526X_DBUG(0, "uli526x_open", 0);
442 /* system variable init */
443 db->cr6_data = CR6_DEFAULT | uli526x_cr6_user_set;
444 db->tx_packet_cnt = 0;
445 db->rx_avail_cnt = 0;
447 netif_carrier_off(dev);
450 db->NIC_capability = 0xf; /* All capability*/
451 db->PHY_reg4 = 0x1e0;
453 /* CR6 operation mode decision */
454 db->cr6_data |= ULI526X_TXTH_256;
455 db->cr0_data = CR0_DEFAULT;
457 /* Initialize ULI526X board */
460 ret = request_irq(dev->irq, &uli526x_interrupt, IRQF_SHARED, dev->name, dev);
464 /* Active System Interface */
465 netif_wake_queue(dev);
467 /* set and active a timer process */
468 init_timer(&db->timer);
469 db->timer.expires = ULI526X_TIMER_WUT + HZ * 2;
470 db->timer.data = (unsigned long)dev;
471 db->timer.function = &uli526x_timer;
472 add_timer(&db->timer);
478 /* Initialize ULI526X board
479 * Reset ULI526X board
480 * Initialize TX/Rx descriptor chain structure
481 * Send the set-up frame
482 * Enable Tx/Rx machine
485 static void uli526x_init(struct net_device *dev)
487 struct uli526x_board_info *db = netdev_priv(dev);
488 unsigned long ioaddr = db->ioaddr;
495 ULI526X_DBUG(0, "uli526x_init()", 0);
497 /* Reset M526x MAC controller */
498 outl(ULI526X_RESET, ioaddr + DCR0); /* RESET MAC */
500 outl(db->cr0_data, ioaddr + DCR0);
503 /* Phy addr : In some boards,M5261/M5263 phy address != 1 */
505 for(phy_tmp=0;phy_tmp<32;phy_tmp++)
507 phy_value=phy_read(db->ioaddr,phy_tmp,3,db->chip_id);//peer add
508 if(phy_value != 0xffff&&phy_value!=0)
510 db->phy_addr = phy_tmp;
515 printk(KERN_WARNING "Can not find the phy address!!!");
516 /* Parser SROM and media mode */
517 db->media_mode = uli526x_media_mode;
519 /* phyxcer capability setting */
520 phy_reg_reset = phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id);
521 phy_reg_reset = (phy_reg_reset | 0x8000);
522 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg_reset, db->chip_id);
524 /* See IEEE 802.3-2002.pdf (Section 2, Chapter "22.2.4 Management
525 * functions") or phy data sheet for details on phy reset
530 phy_read(db->ioaddr, db->phy_addr, 0, db->chip_id) & 0x8000)
533 /* Process Phyxcer Media Mode */
534 uli526x_set_phyxcer(db);
536 /* Media Mode Process */
537 if ( !(db->media_mode & ULI526X_AUTO) )
538 db->op_mode = db->media_mode; /* Force Mode */
540 /* Initialize Transmit/Receive decriptor and CR3/4 */
541 uli526x_descriptor_init(db, ioaddr);
543 /* Init CR6 to program M526X operation */
544 update_cr6(db->cr6_data, ioaddr);
546 /* Send setup frame */
547 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
549 /* Init CR7, interrupt active bit */
550 db->cr7_data = CR7_DEFAULT;
551 outl(db->cr7_data, ioaddr + DCR7);
553 /* Init CR15, Tx jabber and Rx watchdog timer */
554 outl(db->cr15_data, ioaddr + DCR15);
556 /* Enable ULI526X Tx/Rx function */
557 db->cr6_data |= CR6_RXSC | CR6_TXSC;
558 update_cr6(db->cr6_data, ioaddr);
563 * Hardware start transmission.
564 * Send a packet to media from the upper layer.
567 static int uli526x_start_xmit(struct sk_buff *skb, struct net_device *dev)
569 struct uli526x_board_info *db = netdev_priv(dev);
570 struct tx_desc *txptr;
573 ULI526X_DBUG(0, "uli526x_start_xmit", 0);
575 /* Resource flag check */
576 netif_stop_queue(dev);
578 /* Too large packet check */
579 if (skb->len > MAX_PACKET_SIZE) {
580 printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
585 spin_lock_irqsave(&db->lock, flags);
587 /* No Tx resource check, it never happen nromally */
588 if (db->tx_packet_cnt >= TX_FREE_DESC_CNT) {
589 spin_unlock_irqrestore(&db->lock, flags);
590 printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_packet_cnt);
594 /* Disable NIC interrupt */
595 outl(0, dev->base_addr + DCR7);
597 /* transmit this packet */
598 txptr = db->tx_insert_ptr;
599 skb_copy_from_linear_data(skb, txptr->tx_buf_ptr, skb->len);
600 txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
602 /* Point to next transmit free descriptor */
603 db->tx_insert_ptr = txptr->next_tx_desc;
605 /* Transmit Packet Process */
606 if ( (db->tx_packet_cnt < TX_DESC_CNT) ) {
607 txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
608 db->tx_packet_cnt++; /* Ready to send */
609 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
610 dev->trans_start = jiffies; /* saved time stamp */
613 /* Tx resource check */
614 if ( db->tx_packet_cnt < TX_FREE_DESC_CNT )
615 netif_wake_queue(dev);
617 /* Restore CR7 to enable interrupt */
618 spin_unlock_irqrestore(&db->lock, flags);
619 outl(db->cr7_data, dev->base_addr + DCR7);
629 * Stop the interface.
630 * The interface is stopped when it is brought.
633 static int uli526x_stop(struct net_device *dev)
635 struct uli526x_board_info *db = netdev_priv(dev);
636 unsigned long ioaddr = dev->base_addr;
638 ULI526X_DBUG(0, "uli526x_stop", 0);
641 netif_stop_queue(dev);
644 del_timer_sync(&db->timer);
646 /* Reset & stop ULI526X board */
647 outl(ULI526X_RESET, ioaddr + DCR0);
649 phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
652 free_irq(dev->irq, dev);
654 /* free allocated rx buffer */
655 uli526x_free_rxbuffer(db);
658 /* show statistic counter */
659 printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
660 db->tx_fifo_underrun, db->tx_excessive_collision,
661 db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
662 db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
663 db->reset_fatal, db->reset_TXtimeout);
671 * M5261/M5263 insterrupt handler
672 * receive the packet to upper layer, free the transmitted packet
675 static irqreturn_t uli526x_interrupt(int irq, void *dev_id)
677 struct net_device *dev = dev_id;
678 struct uli526x_board_info *db = netdev_priv(dev);
679 unsigned long ioaddr = dev->base_addr;
682 spin_lock_irqsave(&db->lock, flags);
683 outl(0, ioaddr + DCR7);
685 /* Got ULI526X status */
686 db->cr5_data = inl(ioaddr + DCR5);
687 outl(db->cr5_data, ioaddr + DCR5);
688 if ( !(db->cr5_data & 0x180c1) ) {
689 /* Restore CR7 to enable interrupt mask */
690 outl(db->cr7_data, ioaddr + DCR7);
691 spin_unlock_irqrestore(&db->lock, flags);
695 /* Check system status */
696 if (db->cr5_data & 0x2000) {
697 /* system bus error happen */
698 ULI526X_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
700 db->wait_reset = 1; /* Need to RESET */
701 spin_unlock_irqrestore(&db->lock, flags);
705 /* Received the coming packet */
706 if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
707 uli526x_rx_packet(dev, db);
709 /* reallocate rx descriptor buffer */
710 if (db->rx_avail_cnt<RX_DESC_CNT)
711 allocate_rx_buffer(db);
713 /* Free the transmitted descriptor */
714 if ( db->cr5_data & 0x01)
715 uli526x_free_tx_pkt(dev, db);
717 /* Restore CR7 to enable interrupt mask */
718 outl(db->cr7_data, ioaddr + DCR7);
720 spin_unlock_irqrestore(&db->lock, flags);
724 #ifdef CONFIG_NET_POLL_CONTROLLER
725 static void uli526x_poll(struct net_device *dev)
727 /* ISR grabs the irqsave lock, so this should be safe */
728 uli526x_interrupt(dev->irq, dev);
733 * Free TX resource after TX complete
736 static void uli526x_free_tx_pkt(struct net_device *dev, struct uli526x_board_info * db)
738 struct tx_desc *txptr;
741 txptr = db->tx_remove_ptr;
742 while(db->tx_packet_cnt) {
743 tdes0 = le32_to_cpu(txptr->tdes0);
744 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
745 if (tdes0 & 0x80000000)
748 /* A packet sent completed */
750 db->stats.tx_packets++;
752 /* Transmit statistic counter */
753 if ( tdes0 != 0x7fffffff ) {
754 /* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
755 db->stats.collisions += (tdes0 >> 3) & 0xf;
756 db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
757 if (tdes0 & TDES0_ERR_MASK) {
758 db->stats.tx_errors++;
759 if (tdes0 & 0x0002) { /* UnderRun */
760 db->tx_fifo_underrun++;
761 if ( !(db->cr6_data & CR6_SFT) ) {
762 db->cr6_data = db->cr6_data | CR6_SFT;
763 update_cr6(db->cr6_data, db->ioaddr);
767 db->tx_excessive_collision++;
769 db->tx_late_collision++;
773 db->tx_loss_carrier++;
775 db->tx_jabber_timeout++;
779 txptr = txptr->next_tx_desc;
782 /* Update TX remove pointer to next */
783 db->tx_remove_ptr = txptr;
785 /* Resource available check */
786 if ( db->tx_packet_cnt < TX_WAKE_DESC_CNT )
787 netif_wake_queue(dev); /* Active upper layer, send again */
792 * Receive the come packet and pass to upper layer
795 static void uli526x_rx_packet(struct net_device *dev, struct uli526x_board_info * db)
797 struct rx_desc *rxptr;
802 rxptr = db->rx_ready_ptr;
804 while(db->rx_avail_cnt) {
805 rdes0 = le32_to_cpu(rxptr->rdes0);
806 if (rdes0 & 0x80000000) /* packet owner check */
812 db->interval_rx_cnt++;
814 pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
815 if ( (rdes0 & 0x300) != 0x300) {
816 /* A packet without First/Last flag */
818 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
819 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
821 /* A packet with First/Last flag */
822 rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
824 /* error summary bit check */
825 if (rdes0 & 0x8000) {
826 /* This is a error packet */
827 //printk(DRV_NAME ": rdes0: %lx\n", rdes0);
828 db->stats.rx_errors++;
830 db->stats.rx_fifo_errors++;
832 db->stats.rx_crc_errors++;
834 db->stats.rx_length_errors++;
837 if ( !(rdes0 & 0x8000) ||
838 ((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
839 skb = rxptr->rx_skb_ptr;
841 /* Good packet, send to upper layer */
842 /* Shorst packet used new SKB */
843 if ( (rxlen < RX_COPY_SIZE) &&
844 ( (skb = dev_alloc_skb(rxlen + 2) )
846 /* size less than COPY_SIZE, allocate a rxlen SKB */
847 skb_reserve(skb, 2); /* 16byte align */
848 memcpy(skb_put(skb, rxlen),
849 skb_tail_pointer(rxptr->rx_skb_ptr),
851 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
855 skb->protocol = eth_type_trans(skb, dev);
857 dev->last_rx = jiffies;
858 db->stats.rx_packets++;
859 db->stats.rx_bytes += rxlen;
862 /* Reuse SKB buffer when the packet is error */
863 ULI526X_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
864 uli526x_reuse_skb(db, rxptr->rx_skb_ptr);
868 rxptr = rxptr->next_rx_desc;
871 db->rx_ready_ptr = rxptr;
876 * Get statistics from driver.
879 static struct net_device_stats * uli526x_get_stats(struct net_device *dev)
881 struct uli526x_board_info *db = netdev_priv(dev);
883 ULI526X_DBUG(0, "uli526x_get_stats", 0);
889 * Set ULI526X multicast address
892 static void uli526x_set_filter_mode(struct net_device * dev)
894 struct uli526x_board_info *db = dev->priv;
897 ULI526X_DBUG(0, "uli526x_set_filter_mode()", 0);
898 spin_lock_irqsave(&db->lock, flags);
900 if (dev->flags & IFF_PROMISC) {
901 ULI526X_DBUG(0, "Enable PROM Mode", 0);
902 db->cr6_data |= CR6_PM | CR6_PBF;
903 update_cr6(db->cr6_data, db->ioaddr);
904 spin_unlock_irqrestore(&db->lock, flags);
908 if (dev->flags & IFF_ALLMULTI || dev->mc_count > ULI5261_MAX_MULTICAST) {
909 ULI526X_DBUG(0, "Pass all multicast address", dev->mc_count);
910 db->cr6_data &= ~(CR6_PM | CR6_PBF);
911 db->cr6_data |= CR6_PAM;
912 spin_unlock_irqrestore(&db->lock, flags);
916 ULI526X_DBUG(0, "Set multicast address", dev->mc_count);
917 send_filter_frame(dev, dev->mc_count); /* M5261/M5263 */
918 spin_unlock_irqrestore(&db->lock, flags);
922 ULi_ethtool_gset(struct uli526x_board_info *db, struct ethtool_cmd *ecmd)
924 ecmd->supported = (SUPPORTED_10baseT_Half |
925 SUPPORTED_10baseT_Full |
926 SUPPORTED_100baseT_Half |
927 SUPPORTED_100baseT_Full |
931 ecmd->advertising = (ADVERTISED_10baseT_Half |
932 ADVERTISED_10baseT_Full |
933 ADVERTISED_100baseT_Half |
934 ADVERTISED_100baseT_Full |
939 ecmd->port = PORT_MII;
940 ecmd->phy_address = db->phy_addr;
942 ecmd->transceiver = XCVR_EXTERNAL;
945 ecmd->duplex = DUPLEX_HALF;
947 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
951 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
953 ecmd->duplex = DUPLEX_FULL;
961 if (db->media_mode & ULI526X_AUTO)
963 ecmd->autoneg = AUTONEG_ENABLE;
967 static void netdev_get_drvinfo(struct net_device *dev,
968 struct ethtool_drvinfo *info)
970 struct uli526x_board_info *np = netdev_priv(dev);
972 strcpy(info->driver, DRV_NAME);
973 strcpy(info->version, DRV_VERSION);
975 strcpy(info->bus_info, pci_name(np->pdev));
977 sprintf(info->bus_info, "EISA 0x%lx %d",
978 dev->base_addr, dev->irq);
981 static int netdev_get_settings(struct net_device *dev, struct ethtool_cmd *cmd) {
982 struct uli526x_board_info *np = netdev_priv(dev);
984 ULi_ethtool_gset(np, cmd);
989 static u32 netdev_get_link(struct net_device *dev) {
990 struct uli526x_board_info *np = netdev_priv(dev);
998 static void uli526x_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1000 wol->supported = WAKE_PHY | WAKE_MAGIC;
1004 static const struct ethtool_ops netdev_ethtool_ops = {
1005 .get_drvinfo = netdev_get_drvinfo,
1006 .get_settings = netdev_get_settings,
1007 .get_link = netdev_get_link,
1008 .get_wol = uli526x_get_wol,
1012 * A periodic timer routine
1013 * Dynamic media sense, allocate Rx buffer...
1016 static void uli526x_timer(unsigned long data)
1019 unsigned char tmp_cr12=0;
1020 struct net_device *dev = (struct net_device *) data;
1021 struct uli526x_board_info *db = netdev_priv(dev);
1022 unsigned long flags;
1025 //ULI526X_DBUG(0, "uli526x_timer()", 0);
1026 spin_lock_irqsave(&db->lock, flags);
1029 /* Dynamic reset ULI526X : system error or transmit time-out */
1030 tmp_cr8 = inl(db->ioaddr + DCR8);
1031 if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
1035 db->interval_rx_cnt = 0;
1037 /* TX polling kick monitor */
1038 if ( db->tx_packet_cnt &&
1039 time_after(jiffies, dev->trans_start + ULI526X_TX_KICK) ) {
1040 outl(0x1, dev->base_addr + DCR1); // Tx polling again
1043 if ( time_after(jiffies, dev->trans_start + ULI526X_TX_TIMEOUT) ) {
1044 db->reset_TXtimeout++;
1046 printk( "%s: Tx timeout - resetting\n",
1051 if (db->wait_reset) {
1052 ULI526X_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
1054 uli526x_dynamic_reset(dev);
1055 db->timer.expires = ULI526X_TIMER_WUT;
1056 add_timer(&db->timer);
1057 spin_unlock_irqrestore(&db->lock, flags);
1061 /* Link status check, Dynamic media type change */
1062 if((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)!=0)
1065 if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
1067 ULI526X_DBUG(0, "Link Failed", tmp_cr12);
1068 netif_carrier_off(dev);
1069 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1070 db->link_failed = 1;
1072 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
1073 /* AUTO don't need */
1074 if ( !(db->media_mode & 0x8) )
1075 phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
1077 /* AUTO mode, if INT phyxcer link failed, select EXT device */
1078 if (db->media_mode & ULI526X_AUTO) {
1079 db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
1080 update_cr6(db->cr6_data, db->ioaddr);
1083 if ((tmp_cr12 & 0x3) && db->link_failed) {
1084 ULI526X_DBUG(0, "Link link OK", tmp_cr12);
1085 db->link_failed = 0;
1087 /* Auto Sense Speed */
1088 if ( (db->media_mode & ULI526X_AUTO) &&
1089 uli526x_sense_speed(db) )
1090 db->link_failed = 1;
1091 uli526x_process_mode(db);
1093 if(db->link_failed==0)
1095 if(db->op_mode==ULI526X_100MHF || db->op_mode==ULI526X_100MFD)
1099 if(db->op_mode==ULI526X_10MFD || db->op_mode==ULI526X_100MFD)
1101 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Full duplex\n",dev->name,TmpSpeed);
1105 printk(KERN_INFO "uli526x: %s NIC Link is Up %d Mbps Half duplex\n",dev->name,TmpSpeed);
1107 netif_carrier_on(dev);
1109 /* SHOW_MEDIA_TYPE(db->op_mode); */
1111 else if(!(tmp_cr12 & 0x3) && db->link_failed)
1115 printk(KERN_INFO "uli526x: %s NIC Link is Down\n",dev->name);
1116 netif_carrier_off(dev);
1121 /* Timer active again */
1122 db->timer.expires = ULI526X_TIMER_WUT;
1123 add_timer(&db->timer);
1124 spin_unlock_irqrestore(&db->lock, flags);
1129 * Stop ULI526X board
1130 * Free Tx/Rx allocated memory
1131 * Init system variable
1134 static void uli526x_reset_prepare(struct net_device *dev)
1136 struct uli526x_board_info *db = netdev_priv(dev);
1138 /* Sopt MAC controller */
1139 db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
1140 update_cr6(db->cr6_data, dev->base_addr);
1141 outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
1142 outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
1144 /* Disable upper layer interface */
1145 netif_stop_queue(dev);
1147 /* Free Rx Allocate buffer */
1148 uli526x_free_rxbuffer(db);
1150 /* system variable init */
1151 db->tx_packet_cnt = 0;
1152 db->rx_avail_cnt = 0;
1153 db->link_failed = 1;
1160 * Dynamic reset the ULI526X board
1161 * Stop ULI526X board
1162 * Free Tx/Rx allocated memory
1163 * Reset ULI526X board
1164 * Re-initialize ULI526X board
1167 static void uli526x_dynamic_reset(struct net_device *dev)
1169 ULI526X_DBUG(0, "uli526x_dynamic_reset()", 0);
1171 uli526x_reset_prepare(dev);
1173 /* Re-initialize ULI526X board */
1176 /* Restart upper layer interface */
1177 netif_wake_queue(dev);
1184 * Suspend the interface.
1187 static int uli526x_suspend(struct pci_dev *pdev, pm_message_t state)
1189 struct net_device *dev = pci_get_drvdata(pdev);
1190 pci_power_t power_state;
1193 ULI526X_DBUG(0, "uli526x_suspend", 0);
1195 if (!netdev_priv(dev))
1198 pci_save_state(pdev);
1200 if (!netif_running(dev))
1203 netif_device_detach(dev);
1204 uli526x_reset_prepare(dev);
1206 power_state = pci_choose_state(pdev, state);
1207 pci_enable_wake(pdev, power_state, 0);
1208 err = pci_set_power_state(pdev, power_state);
1210 netif_device_attach(dev);
1211 /* Re-initialize ULI526X board */
1213 /* Restart upper layer interface */
1214 netif_wake_queue(dev);
1221 * Resume the interface.
1224 static int uli526x_resume(struct pci_dev *pdev)
1226 struct net_device *dev = pci_get_drvdata(pdev);
1229 ULI526X_DBUG(0, "uli526x_resume", 0);
1231 if (!netdev_priv(dev))
1234 pci_restore_state(pdev);
1236 if (!netif_running(dev))
1239 err = pci_set_power_state(pdev, PCI_D0);
1241 printk(KERN_WARNING "%s: Could not put device into D0\n",
1246 netif_device_attach(dev);
1247 /* Re-initialize ULI526X board */
1249 /* Restart upper layer interface */
1250 netif_wake_queue(dev);
1255 #else /* !CONFIG_PM */
1257 #define uli526x_suspend NULL
1258 #define uli526x_resume NULL
1260 #endif /* !CONFIG_PM */
1264 * free all allocated rx buffer
1267 static void uli526x_free_rxbuffer(struct uli526x_board_info * db)
1269 ULI526X_DBUG(0, "uli526x_free_rxbuffer()", 0);
1271 /* free allocated rx buffer */
1272 while (db->rx_avail_cnt) {
1273 dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
1274 db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
1281 * Reuse the SK buffer
1284 static void uli526x_reuse_skb(struct uli526x_board_info *db, struct sk_buff * skb)
1286 struct rx_desc *rxptr = db->rx_insert_ptr;
1288 if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
1289 rxptr->rx_skb_ptr = skb;
1290 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1291 skb_tail_pointer(skb),
1293 PCI_DMA_FROMDEVICE));
1295 rxptr->rdes0 = cpu_to_le32(0x80000000);
1297 db->rx_insert_ptr = rxptr->next_rx_desc;
1299 ULI526X_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
1304 * Initialize transmit/Receive descriptor
1305 * Using Chain structure, and allocate Tx/Rx buffer
1308 static void uli526x_descriptor_init(struct uli526x_board_info *db, unsigned long ioaddr)
1310 struct tx_desc *tmp_tx;
1311 struct rx_desc *tmp_rx;
1312 unsigned char *tmp_buf;
1313 dma_addr_t tmp_tx_dma, tmp_rx_dma;
1314 dma_addr_t tmp_buf_dma;
1317 ULI526X_DBUG(0, "uli526x_descriptor_init()", 0);
1319 /* tx descriptor start pointer */
1320 db->tx_insert_ptr = db->first_tx_desc;
1321 db->tx_remove_ptr = db->first_tx_desc;
1322 outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
1324 /* rx descriptor start pointer */
1325 db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
1326 db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
1327 db->rx_insert_ptr = db->first_rx_desc;
1328 db->rx_ready_ptr = db->first_rx_desc;
1329 outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
1331 /* Init Transmit chain */
1332 tmp_buf = db->buf_pool_start;
1333 tmp_buf_dma = db->buf_pool_dma_start;
1334 tmp_tx_dma = db->first_tx_desc_dma;
1335 for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
1336 tmp_tx->tx_buf_ptr = tmp_buf;
1337 tmp_tx->tdes0 = cpu_to_le32(0);
1338 tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
1339 tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
1340 tmp_tx_dma += sizeof(struct tx_desc);
1341 tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
1342 tmp_tx->next_tx_desc = tmp_tx + 1;
1343 tmp_buf = tmp_buf + TX_BUF_ALLOC;
1344 tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
1346 (--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
1347 tmp_tx->next_tx_desc = db->first_tx_desc;
1349 /* Init Receive descriptor chain */
1350 tmp_rx_dma=db->first_rx_desc_dma;
1351 for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
1352 tmp_rx->rdes0 = cpu_to_le32(0);
1353 tmp_rx->rdes1 = cpu_to_le32(0x01000600);
1354 tmp_rx_dma += sizeof(struct rx_desc);
1355 tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
1356 tmp_rx->next_rx_desc = tmp_rx + 1;
1358 (--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
1359 tmp_rx->next_rx_desc = db->first_rx_desc;
1361 /* pre-allocate Rx buffer */
1362 allocate_rx_buffer(db);
1368 * Firstly stop ULI526X, then written value and start
1371 static void update_cr6(u32 cr6_data, unsigned long ioaddr)
1374 outl(cr6_data, ioaddr + DCR6);
1380 * Send a setup frame for M5261/M5263
1381 * This setup frame initialize ULI526X address filter mode
1385 #define FLT_SHIFT 16
1390 static void send_filter_frame(struct net_device *dev, int mc_cnt)
1392 struct uli526x_board_info *db = netdev_priv(dev);
1393 struct dev_mc_list *mcptr;
1394 struct tx_desc *txptr;
1399 ULI526X_DBUG(0, "send_filter_frame()", 0);
1401 txptr = db->tx_insert_ptr;
1402 suptr = (u32 *) txptr->tx_buf_ptr;
1405 addrptr = (u16 *) dev->dev_addr;
1406 *suptr++ = addrptr[0] << FLT_SHIFT;
1407 *suptr++ = addrptr[1] << FLT_SHIFT;
1408 *suptr++ = addrptr[2] << FLT_SHIFT;
1410 /* broadcast address */
1411 *suptr++ = 0xffff << FLT_SHIFT;
1412 *suptr++ = 0xffff << FLT_SHIFT;
1413 *suptr++ = 0xffff << FLT_SHIFT;
1415 /* fit the multicast address */
1416 for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
1417 addrptr = (u16 *) mcptr->dmi_addr;
1418 *suptr++ = addrptr[0] << FLT_SHIFT;
1419 *suptr++ = addrptr[1] << FLT_SHIFT;
1420 *suptr++ = addrptr[2] << FLT_SHIFT;
1424 *suptr++ = 0xffff << FLT_SHIFT;
1425 *suptr++ = 0xffff << FLT_SHIFT;
1426 *suptr++ = 0xffff << FLT_SHIFT;
1429 /* prepare the setup frame */
1430 db->tx_insert_ptr = txptr->next_tx_desc;
1431 txptr->tdes1 = cpu_to_le32(0x890000c0);
1433 /* Resource Check and Send the setup packet */
1434 if (db->tx_packet_cnt < TX_DESC_CNT) {
1435 /* Resource Empty */
1436 db->tx_packet_cnt++;
1437 txptr->tdes0 = cpu_to_le32(0x80000000);
1438 update_cr6(db->cr6_data | 0x2000, dev->base_addr);
1439 outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
1440 update_cr6(db->cr6_data, dev->base_addr);
1441 dev->trans_start = jiffies;
1443 printk(KERN_ERR DRV_NAME ": No Tx resource - Send_filter_frame!\n");
1448 * Allocate rx buffer,
1449 * As possible as allocate maxiumn Rx buffer
1452 static void allocate_rx_buffer(struct uli526x_board_info *db)
1454 struct rx_desc *rxptr;
1455 struct sk_buff *skb;
1457 rxptr = db->rx_insert_ptr;
1459 while(db->rx_avail_cnt < RX_DESC_CNT) {
1460 if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
1462 rxptr->rx_skb_ptr = skb; /* FIXME (?) */
1463 rxptr->rdes2 = cpu_to_le32(pci_map_single(db->pdev,
1464 skb_tail_pointer(skb),
1466 PCI_DMA_FROMDEVICE));
1468 rxptr->rdes0 = cpu_to_le32(0x80000000);
1469 rxptr = rxptr->next_rx_desc;
1473 db->rx_insert_ptr = rxptr;
1478 * Read one word data from the serial ROM
1481 static u16 read_srom_word(long ioaddr, int offset)
1485 long cr9_ioaddr = ioaddr + DCR9;
1487 outl(CR9_SROM_READ, cr9_ioaddr);
1488 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1490 /* Send the Read Command 110b */
1491 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1492 SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
1493 SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
1495 /* Send the offset */
1496 for (i = 5; i >= 0; i--) {
1497 srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
1498 SROM_CLK_WRITE(srom_data, cr9_ioaddr);
1501 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1503 for (i = 16; i > 0; i--) {
1504 outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
1506 srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
1507 outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
1511 outl(CR9_SROM_READ, cr9_ioaddr);
1517 * Auto sense the media mode
1520 static u8 uli526x_sense_speed(struct uli526x_board_info * db)
1525 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1526 phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
1528 if ( (phy_mode & 0x24) == 0x24 ) {
1530 phy_mode = ((phy_read(db->ioaddr, db->phy_addr, 5, db->chip_id) & 0x01e0)<<7);
1533 else if(phy_mode&0x4000)
1535 else if(phy_mode&0x2000)
1540 /* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
1542 case 0x1000: db->op_mode = ULI526X_10MHF; break;
1543 case 0x2000: db->op_mode = ULI526X_10MFD; break;
1544 case 0x4000: db->op_mode = ULI526X_100MHF; break;
1545 case 0x8000: db->op_mode = ULI526X_100MFD; break;
1546 default: db->op_mode = ULI526X_10MHF; ErrFlag = 1; break;
1549 db->op_mode = ULI526X_10MHF;
1550 ULI526X_DBUG(0, "Link Failed :", phy_mode);
1559 * Set 10/100 phyxcer capability
1560 * AUTO mode : phyxcer register4 is NIC capability
1561 * Force mode: phyxcer register4 is the force media
1564 static void uli526x_set_phyxcer(struct uli526x_board_info *db)
1568 /* Phyxcer capability setting */
1569 phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
1571 if (db->media_mode & ULI526X_AUTO) {
1573 phy_reg |= db->PHY_reg4;
1576 switch(db->media_mode) {
1577 case ULI526X_10MHF: phy_reg |= 0x20; break;
1578 case ULI526X_10MFD: phy_reg |= 0x40; break;
1579 case ULI526X_100MHF: phy_reg |= 0x80; break;
1580 case ULI526X_100MFD: phy_reg |= 0x100; break;
1585 /* Write new capability to Phyxcer Reg4 */
1586 if ( !(phy_reg & 0x01e0)) {
1587 phy_reg|=db->PHY_reg4;
1588 db->media_mode|=ULI526X_AUTO;
1590 phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
1592 /* Restart Auto-Negotiation */
1593 phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
1600 AUTO mode : PHY controller in Auto-negotiation Mode
1601 * Force mode: PHY controller in force mode with HUB
1602 * N-way force capability with SWITCH
1605 static void uli526x_process_mode(struct uli526x_board_info *db)
1609 /* Full Duplex Mode Check */
1610 if (db->op_mode & 0x4)
1611 db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
1613 db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
1615 update_cr6(db->cr6_data, db->ioaddr);
1617 /* 10/100M phyxcer force mode need */
1618 if ( !(db->media_mode & 0x8)) {
1620 phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
1621 if ( !(phy_reg & 0x1) ) {
1622 /* parter without N-Way capability */
1624 switch(db->op_mode) {
1625 case ULI526X_10MHF: phy_reg = 0x0; break;
1626 case ULI526X_10MFD: phy_reg = 0x100; break;
1627 case ULI526X_100MHF: phy_reg = 0x2000; break;
1628 case ULI526X_100MFD: phy_reg = 0x2100; break;
1630 phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
1637 * Write a word to Phy register
1640 static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
1643 unsigned long ioaddr;
1645 if(chip_id == PCI_ULI5263_ID)
1647 phy_writeby_cr10(iobase, phy_addr, offset, phy_data);
1650 /* M5261/M5263 Chip */
1651 ioaddr = iobase + DCR9;
1653 /* Send 33 synchronization clock to Phy controller */
1654 for (i = 0; i < 35; i++)
1655 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1657 /* Send start command(01) to Phy */
1658 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1659 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1661 /* Send write command(01) to Phy */
1662 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1663 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1665 /* Send Phy address */
1666 for (i = 0x10; i > 0; i = i >> 1)
1667 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1669 /* Send register address */
1670 for (i = 0x10; i > 0; i = i >> 1)
1671 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1673 /* written trasnition */
1674 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1675 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1677 /* Write a word data to PHY controller */
1678 for ( i = 0x8000; i > 0; i >>= 1)
1679 phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1685 * Read a word data from phy register
1688 static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
1692 unsigned long ioaddr;
1694 if(chip_id == PCI_ULI5263_ID)
1695 return phy_readby_cr10(iobase, phy_addr, offset);
1696 /* M5261/M5263 Chip */
1697 ioaddr = iobase + DCR9;
1699 /* Send 33 synchronization clock to Phy controller */
1700 for (i = 0; i < 35; i++)
1701 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1703 /* Send start command(01) to Phy */
1704 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1705 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1707 /* Send read command(10) to Phy */
1708 phy_write_1bit(ioaddr, PHY_DATA_1, chip_id);
1709 phy_write_1bit(ioaddr, PHY_DATA_0, chip_id);
1711 /* Send Phy address */
1712 for (i = 0x10; i > 0; i = i >> 1)
1713 phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1715 /* Send register address */
1716 for (i = 0x10; i > 0; i = i >> 1)
1717 phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0, chip_id);
1719 /* Skip transition state */
1720 phy_read_1bit(ioaddr, chip_id);
1722 /* read 16bit data */
1723 for (phy_data = 0, i = 0; i < 16; i++) {
1725 phy_data |= phy_read_1bit(ioaddr, chip_id);
1731 static u16 phy_readby_cr10(unsigned long iobase, u8 phy_addr, u8 offset)
1733 unsigned long ioaddr,cr10_value;
1735 ioaddr = iobase + DCR10;
1736 cr10_value = phy_addr;
1737 cr10_value = (cr10_value<<5) + offset;
1738 cr10_value = (cr10_value<<16) + 0x08000000;
1739 outl(cr10_value,ioaddr);
1743 cr10_value = inl(ioaddr);
1744 if(cr10_value&0x10000000)
1747 return (cr10_value&0x0ffff);
1750 static void phy_writeby_cr10(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data)
1752 unsigned long ioaddr,cr10_value;
1754 ioaddr = iobase + DCR10;
1755 cr10_value = phy_addr;
1756 cr10_value = (cr10_value<<5) + offset;
1757 cr10_value = (cr10_value<<16) + 0x04000000 + phy_data;
1758 outl(cr10_value,ioaddr);
1762 * Write one bit data to Phy Controller
1765 static void phy_write_1bit(unsigned long ioaddr, u32 phy_data, u32 chip_id)
1767 outl(phy_data , ioaddr); /* MII Clock Low */
1769 outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
1771 outl(phy_data , ioaddr); /* MII Clock Low */
1777 * Read one bit phy data from PHY controller
1780 static u16 phy_read_1bit(unsigned long ioaddr, u32 chip_id)
1784 outl(0x50000 , ioaddr);
1786 phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
1787 outl(0x40000 , ioaddr);
1794 static struct pci_device_id uli526x_pci_tbl[] = {
1795 { 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5261_ID },
1796 { 0x10B9, 0x5263, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_ULI5263_ID },
1799 MODULE_DEVICE_TABLE(pci, uli526x_pci_tbl);
1802 static struct pci_driver uli526x_driver = {
1804 .id_table = uli526x_pci_tbl,
1805 .probe = uli526x_init_one,
1806 .remove = __devexit_p(uli526x_remove_one),
1807 .suspend = uli526x_suspend,
1808 .resume = uli526x_resume,
1811 MODULE_AUTHOR("Peer Chen, peer.chen@uli.com.tw");
1812 MODULE_DESCRIPTION("ULi M5261/M5263 fast ethernet driver");
1813 MODULE_LICENSE("GPL");
1815 module_param(debug, int, 0644);
1816 module_param(mode, int, 0);
1817 module_param(cr6set, int, 0);
1818 MODULE_PARM_DESC(debug, "ULi M5261/M5263 enable debugging (0-1)");
1819 MODULE_PARM_DESC(mode, "ULi M5261/M5263: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
1822 * when user used insmod to add module, system invoked init_module()
1823 * to register the services.
1826 static int __init uli526x_init_module(void)
1830 printed_version = 1;
1832 ULI526X_DBUG(0, "init_module() ", debug);
1835 uli526x_debug = debug; /* set debug flag */
1837 uli526x_cr6_user_set = cr6set;
1841 case ULI526X_100MHF:
1843 case ULI526X_100MFD:
1844 uli526x_media_mode = mode;
1847 uli526x_media_mode = ULI526X_AUTO;
1851 return pci_register_driver(&uli526x_driver);
1857 * when user used rmmod to delete module, system invoked clean_module()
1858 * to un-register all registered services.
1861 static void __exit uli526x_cleanup_module(void)
1863 ULI526X_DBUG(0, "uli526x_clean_module() ", debug);
1864 pci_unregister_driver(&uli526x_driver);
1867 module_init(uli526x_init_module);
1868 module_exit(uli526x_cleanup_module);