2 * tg3.c: Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2005-2009 Broadcom Corporation.
10 * Derived from proprietary unpublished source code,
11 * Copyright (C) 2000-2003 Broadcom Corporation.
13 * Permission is hereby granted for the distribution of this firmware
14 * data in hexadecimal or equivalent format, provided this copyright
15 * notice is accompanying it.
19 #include <linux/module.h>
20 #include <linux/moduleparam.h>
21 #include <linux/kernel.h>
22 #include <linux/types.h>
23 #include <linux/compiler.h>
24 #include <linux/slab.h>
25 #include <linux/delay.h>
27 #include <linux/init.h>
28 #include <linux/ioport.h>
29 #include <linux/pci.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/skbuff.h>
33 #include <linux/ethtool.h>
34 #include <linux/mii.h>
35 #include <linux/phy.h>
36 #include <linux/brcmphy.h>
37 #include <linux/if_vlan.h>
39 #include <linux/tcp.h>
40 #include <linux/workqueue.h>
41 #include <linux/prefetch.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/firmware.h>
45 #include <net/checksum.h>
48 #include <asm/system.h>
50 #include <asm/byteorder.h>
51 #include <asm/uaccess.h>
54 #include <asm/idprom.h>
61 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
62 #define TG3_VLAN_TAG_USED 1
64 #define TG3_VLAN_TAG_USED 0
69 #define DRV_MODULE_NAME "tg3"
70 #define PFX DRV_MODULE_NAME ": "
71 #define DRV_MODULE_VERSION "3.105"
72 #define DRV_MODULE_RELDATE "December 2, 2009"
74 #define TG3_DEF_MAC_MODE 0
75 #define TG3_DEF_RX_MODE 0
76 #define TG3_DEF_TX_MODE 0
77 #define TG3_DEF_MSG_ENABLE \
87 /* length of time before we decide the hardware is borked,
88 * and dev->tx_timeout() should be called to fix the problem
90 #define TG3_TX_TIMEOUT (5 * HZ)
92 /* hardware minimum and maximum for a single frame's data payload */
93 #define TG3_MIN_MTU 60
94 #define TG3_MAX_MTU(tp) \
95 ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) ? 9000 : 1500)
97 /* These numbers seem to be hard coded in the NIC firmware somehow.
98 * You can't change the ring sizes, but you can change where you place
99 * them in the NIC onboard memory.
101 #define TG3_RX_RING_SIZE 512
102 #define TG3_DEF_RX_RING_PENDING 200
103 #define TG3_RX_JUMBO_RING_SIZE 256
104 #define TG3_DEF_RX_JUMBO_RING_PENDING 100
105 #define TG3_RSS_INDIR_TBL_SIZE 128
107 /* Do not place this n-ring entries value into the tp struct itself,
108 * we really want to expose these constants to GCC so that modulo et
109 * al. operations are done with shifts and masks instead of with
110 * hw multiply/modulo instructions. Another solution would be to
111 * replace things like '% foo' with '& (foo - 1)'.
113 #define TG3_RX_RCB_RING_SIZE(tp) \
114 (((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
115 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 1024 : 512)
117 #define TG3_TX_RING_SIZE 512
118 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
120 #define TG3_RX_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
122 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_ext_rx_buffer_desc) * \
123 TG3_RX_JUMBO_RING_SIZE)
124 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
125 TG3_RX_RCB_RING_SIZE(tp))
126 #define TG3_TX_RING_BYTES (sizeof(struct tg3_tx_buffer_desc) * \
128 #define NEXT_TX(N) (((N) + 1) & (TG3_TX_RING_SIZE - 1))
130 #define TG3_DMA_BYTE_ENAB 64
132 #define TG3_RX_STD_DMA_SZ 1536
133 #define TG3_RX_JMB_DMA_SZ 9046
135 #define TG3_RX_DMA_TO_MAP_SZ(x) ((x) + TG3_DMA_BYTE_ENAB)
137 #define TG3_RX_STD_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_STD_DMA_SZ)
138 #define TG3_RX_JMB_MAP_SZ TG3_RX_DMA_TO_MAP_SZ(TG3_RX_JMB_DMA_SZ)
140 #define TG3_RX_STD_BUFF_RING_SIZE \
141 (sizeof(struct ring_info) * TG3_RX_RING_SIZE)
143 #define TG3_RX_JMB_BUFF_RING_SIZE \
144 (sizeof(struct ring_info) * TG3_RX_JUMBO_RING_SIZE)
146 /* minimum number of free TX descriptors required to wake up TX process */
147 #define TG3_TX_WAKEUP_THRESH(tnapi) ((tnapi)->tx_pending / 4)
149 #define TG3_RAW_IP_ALIGN 2
151 /* number of ETHTOOL_GSTATS u64's */
152 #define TG3_NUM_STATS (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
154 #define TG3_NUM_TEST 6
156 #define FIRMWARE_TG3 "tigon/tg3.bin"
157 #define FIRMWARE_TG3TSO "tigon/tg3_tso.bin"
158 #define FIRMWARE_TG3TSO5 "tigon/tg3_tso5.bin"
160 static char version[] __devinitdata =
161 DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
163 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
164 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
165 MODULE_LICENSE("GPL");
166 MODULE_VERSION(DRV_MODULE_VERSION);
167 MODULE_FIRMWARE(FIRMWARE_TG3);
168 MODULE_FIRMWARE(FIRMWARE_TG3TSO);
169 MODULE_FIRMWARE(FIRMWARE_TG3TSO5);
171 #define TG3_RSS_MIN_NUM_MSIX_VECS 2
173 static int tg3_debug = -1; /* -1 == use TG3_DEF_MSG_ENABLE as value */
174 module_param(tg3_debug, int, 0);
175 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
177 static DEFINE_PCI_DEVICE_TABLE(tg3_pci_tbl) = {
178 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
179 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
180 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
181 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
182 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
183 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
184 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
185 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
186 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
187 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
188 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
189 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
190 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
191 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
192 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
193 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
194 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
195 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
196 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
197 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
198 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
199 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
200 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
201 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
202 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
203 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
204 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
205 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
206 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
207 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
208 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
209 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
210 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
211 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
212 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
213 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
214 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
215 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
216 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
217 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
218 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
219 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
220 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
221 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
222 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
223 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
224 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
225 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
226 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
227 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
228 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
229 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
230 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
231 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5784)},
232 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5764)},
233 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5723)},
234 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761)},
235 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5761E)},
236 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761S)},
237 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5761SE)},
238 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_G)},
239 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5785_F)},
240 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57780)},
241 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57760)},
242 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57790)},
243 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_57788)},
244 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5717)},
245 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5718)},
246 {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, TG3PCI_DEVICE_TIGON3_5724)},
247 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
248 {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
249 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
250 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
251 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
252 {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
253 {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
257 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
259 static const struct {
260 const char string[ETH_GSTRING_LEN];
261 } ethtool_stats_keys[TG3_NUM_STATS] = {
264 { "rx_ucast_packets" },
265 { "rx_mcast_packets" },
266 { "rx_bcast_packets" },
268 { "rx_align_errors" },
269 { "rx_xon_pause_rcvd" },
270 { "rx_xoff_pause_rcvd" },
271 { "rx_mac_ctrl_rcvd" },
272 { "rx_xoff_entered" },
273 { "rx_frame_too_long_errors" },
275 { "rx_undersize_packets" },
276 { "rx_in_length_errors" },
277 { "rx_out_length_errors" },
278 { "rx_64_or_less_octet_packets" },
279 { "rx_65_to_127_octet_packets" },
280 { "rx_128_to_255_octet_packets" },
281 { "rx_256_to_511_octet_packets" },
282 { "rx_512_to_1023_octet_packets" },
283 { "rx_1024_to_1522_octet_packets" },
284 { "rx_1523_to_2047_octet_packets" },
285 { "rx_2048_to_4095_octet_packets" },
286 { "rx_4096_to_8191_octet_packets" },
287 { "rx_8192_to_9022_octet_packets" },
294 { "tx_flow_control" },
296 { "tx_single_collisions" },
297 { "tx_mult_collisions" },
299 { "tx_excessive_collisions" },
300 { "tx_late_collisions" },
301 { "tx_collide_2times" },
302 { "tx_collide_3times" },
303 { "tx_collide_4times" },
304 { "tx_collide_5times" },
305 { "tx_collide_6times" },
306 { "tx_collide_7times" },
307 { "tx_collide_8times" },
308 { "tx_collide_9times" },
309 { "tx_collide_10times" },
310 { "tx_collide_11times" },
311 { "tx_collide_12times" },
312 { "tx_collide_13times" },
313 { "tx_collide_14times" },
314 { "tx_collide_15times" },
315 { "tx_ucast_packets" },
316 { "tx_mcast_packets" },
317 { "tx_bcast_packets" },
318 { "tx_carrier_sense_errors" },
322 { "dma_writeq_full" },
323 { "dma_write_prioq_full" },
327 { "rx_threshold_hit" },
329 { "dma_readq_full" },
330 { "dma_read_prioq_full" },
331 { "tx_comp_queue_full" },
333 { "ring_set_send_prod_index" },
334 { "ring_status_update" },
336 { "nic_avoided_irqs" },
337 { "nic_tx_threshold_hit" }
340 static const struct {
341 const char string[ETH_GSTRING_LEN];
342 } ethtool_test_keys[TG3_NUM_TEST] = {
343 { "nvram test (online) " },
344 { "link test (online) " },
345 { "register test (offline)" },
346 { "memory test (offline)" },
347 { "loopback test (offline)" },
348 { "interrupt test (offline)" },
351 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
353 writel(val, tp->regs + off);
356 static u32 tg3_read32(struct tg3 *tp, u32 off)
358 return (readl(tp->regs + off));
361 static void tg3_ape_write32(struct tg3 *tp, u32 off, u32 val)
363 writel(val, tp->aperegs + off);
366 static u32 tg3_ape_read32(struct tg3 *tp, u32 off)
368 return (readl(tp->aperegs + off));
371 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
375 spin_lock_irqsave(&tp->indirect_lock, flags);
376 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
377 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
378 spin_unlock_irqrestore(&tp->indirect_lock, flags);
381 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
383 writel(val, tp->regs + off);
384 readl(tp->regs + off);
387 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
392 spin_lock_irqsave(&tp->indirect_lock, flags);
393 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
394 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
395 spin_unlock_irqrestore(&tp->indirect_lock, flags);
399 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
403 if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
404 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
405 TG3_64BIT_REG_LOW, val);
408 if (off == TG3_RX_STD_PROD_IDX_REG) {
409 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
410 TG3_64BIT_REG_LOW, val);
414 spin_lock_irqsave(&tp->indirect_lock, flags);
415 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
416 pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
417 spin_unlock_irqrestore(&tp->indirect_lock, flags);
419 /* In indirect mode when disabling interrupts, we also need
420 * to clear the interrupt bit in the GRC local ctrl register.
422 if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
424 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
425 tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
429 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
434 spin_lock_irqsave(&tp->indirect_lock, flags);
435 pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
436 pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
437 spin_unlock_irqrestore(&tp->indirect_lock, flags);
441 /* usec_wait specifies the wait time in usec when writing to certain registers
442 * where it is unsafe to read back the register without some delay.
443 * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
444 * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
446 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
448 if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
449 (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
450 /* Non-posted methods */
451 tp->write32(tp, off, val);
454 tg3_write32(tp, off, val);
459 /* Wait again after the read for the posted method to guarantee that
460 * the wait time is met.
466 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
468 tp->write32_mbox(tp, off, val);
469 if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
470 !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
471 tp->read32_mbox(tp, off);
474 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
476 void __iomem *mbox = tp->regs + off;
478 if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
480 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
484 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
486 return (readl(tp->regs + off + GRCMBOX_BASE));
489 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
491 writel(val, tp->regs + off + GRCMBOX_BASE);
494 #define tw32_mailbox(reg, val) tp->write32_mbox(tp, reg, val)
495 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
496 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
497 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
498 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
500 #define tw32(reg,val) tp->write32(tp, reg, val)
501 #define tw32_f(reg,val) _tw32_flush(tp,(reg),(val), 0)
502 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
503 #define tr32(reg) tp->read32(tp, reg)
505 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
509 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
510 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
513 spin_lock_irqsave(&tp->indirect_lock, flags);
514 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
515 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
516 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
518 /* Always leave this as zero. */
519 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
521 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
522 tw32_f(TG3PCI_MEM_WIN_DATA, val);
524 /* Always leave this as zero. */
525 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
527 spin_unlock_irqrestore(&tp->indirect_lock, flags);
530 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
534 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
535 (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
540 spin_lock_irqsave(&tp->indirect_lock, flags);
541 if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
542 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
543 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
545 /* Always leave this as zero. */
546 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
548 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
549 *val = tr32(TG3PCI_MEM_WIN_DATA);
551 /* Always leave this as zero. */
552 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
554 spin_unlock_irqrestore(&tp->indirect_lock, flags);
557 static void tg3_ape_lock_init(struct tg3 *tp)
561 /* Make sure the driver hasn't any stale locks. */
562 for (i = 0; i < 8; i++)
563 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + 4 * i,
564 APE_LOCK_GRANT_DRIVER);
567 static int tg3_ape_lock(struct tg3 *tp, int locknum)
573 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
577 case TG3_APE_LOCK_GRC:
578 case TG3_APE_LOCK_MEM:
586 tg3_ape_write32(tp, TG3_APE_LOCK_REQ + off, APE_LOCK_REQ_DRIVER);
588 /* Wait for up to 1 millisecond to acquire lock. */
589 for (i = 0; i < 100; i++) {
590 status = tg3_ape_read32(tp, TG3_APE_LOCK_GRANT + off);
591 if (status == APE_LOCK_GRANT_DRIVER)
596 if (status != APE_LOCK_GRANT_DRIVER) {
597 /* Revoke the lock request. */
598 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off,
599 APE_LOCK_GRANT_DRIVER);
607 static void tg3_ape_unlock(struct tg3 *tp, int locknum)
611 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
615 case TG3_APE_LOCK_GRC:
616 case TG3_APE_LOCK_MEM:
623 tg3_ape_write32(tp, TG3_APE_LOCK_GRANT + off, APE_LOCK_GRANT_DRIVER);
626 static void tg3_disable_ints(struct tg3 *tp)
630 tw32(TG3PCI_MISC_HOST_CTRL,
631 (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
632 for (i = 0; i < tp->irq_max; i++)
633 tw32_mailbox_f(tp->napi[i].int_mbox, 0x00000001);
636 static void tg3_enable_ints(struct tg3 *tp)
644 tw32(TG3PCI_MISC_HOST_CTRL,
645 (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
647 for (i = 0; i < tp->irq_cnt; i++) {
648 struct tg3_napi *tnapi = &tp->napi[i];
649 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
650 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
651 tw32_mailbox_f(tnapi->int_mbox, tnapi->last_tag << 24);
653 coal_now |= tnapi->coal_now;
656 /* Force an initial interrupt */
657 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
658 (tp->napi[0].hw_status->status & SD_STATUS_UPDATED))
659 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
661 tw32(HOSTCC_MODE, tp->coalesce_mode |
662 HOSTCC_MODE_ENABLE | coal_now);
665 static inline unsigned int tg3_has_work(struct tg3_napi *tnapi)
667 struct tg3 *tp = tnapi->tp;
668 struct tg3_hw_status *sblk = tnapi->hw_status;
669 unsigned int work_exists = 0;
671 /* check for phy events */
672 if (!(tp->tg3_flags &
673 (TG3_FLAG_USE_LINKCHG_REG |
674 TG3_FLAG_POLL_SERDES))) {
675 if (sblk->status & SD_STATUS_LINK_CHG)
678 /* check for RX/TX work to do */
679 if (sblk->idx[0].tx_consumer != tnapi->tx_cons ||
680 *(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
687 * similar to tg3_enable_ints, but it accurately determines whether there
688 * is new work pending and can return without flushing the PIO write
689 * which reenables interrupts
691 static void tg3_int_reenable(struct tg3_napi *tnapi)
693 struct tg3 *tp = tnapi->tp;
695 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
698 /* When doing tagged status, this work check is unnecessary.
699 * The last_tag we write above tells the chip which piece of
700 * work we've completed.
702 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
704 tw32(HOSTCC_MODE, tp->coalesce_mode |
705 HOSTCC_MODE_ENABLE | tnapi->coal_now);
708 static void tg3_napi_disable(struct tg3 *tp)
712 for (i = tp->irq_cnt - 1; i >= 0; i--)
713 napi_disable(&tp->napi[i].napi);
716 static void tg3_napi_enable(struct tg3 *tp)
720 for (i = 0; i < tp->irq_cnt; i++)
721 napi_enable(&tp->napi[i].napi);
724 static inline void tg3_netif_stop(struct tg3 *tp)
726 tp->dev->trans_start = jiffies; /* prevent tx timeout */
727 tg3_napi_disable(tp);
728 netif_tx_disable(tp->dev);
731 static inline void tg3_netif_start(struct tg3 *tp)
733 /* NOTE: unconditional netif_tx_wake_all_queues is only
734 * appropriate so long as all callers are assured to
735 * have free tx slots (such as after tg3_init_hw)
737 netif_tx_wake_all_queues(tp->dev);
740 tp->napi[0].hw_status->status |= SD_STATUS_UPDATED;
744 static void tg3_switch_clocks(struct tg3 *tp)
749 if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
750 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
753 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
755 orig_clock_ctrl = clock_ctrl;
756 clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
757 CLOCK_CTRL_CLKRUN_OENABLE |
759 tp->pci_clock_ctrl = clock_ctrl;
761 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
762 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
763 tw32_wait_f(TG3PCI_CLOCK_CTRL,
764 clock_ctrl | CLOCK_CTRL_625_CORE, 40);
766 } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
767 tw32_wait_f(TG3PCI_CLOCK_CTRL,
769 (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
771 tw32_wait_f(TG3PCI_CLOCK_CTRL,
772 clock_ctrl | (CLOCK_CTRL_ALTCLK),
775 tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
778 #define PHY_BUSY_LOOPS 5000
780 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
786 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
788 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
794 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
795 MI_COM_PHY_ADDR_MASK);
796 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
797 MI_COM_REG_ADDR_MASK);
798 frame_val |= (MI_COM_CMD_READ | MI_COM_START);
800 tw32_f(MAC_MI_COM, frame_val);
802 loops = PHY_BUSY_LOOPS;
805 frame_val = tr32(MAC_MI_COM);
807 if ((frame_val & MI_COM_BUSY) == 0) {
809 frame_val = tr32(MAC_MI_COM);
817 *val = frame_val & MI_COM_DATA_MASK;
821 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
822 tw32_f(MAC_MI_MODE, tp->mi_mode);
829 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
835 if ((tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
836 (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
839 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
841 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
845 frame_val = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
846 MI_COM_PHY_ADDR_MASK);
847 frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
848 MI_COM_REG_ADDR_MASK);
849 frame_val |= (val & MI_COM_DATA_MASK);
850 frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
852 tw32_f(MAC_MI_COM, frame_val);
854 loops = PHY_BUSY_LOOPS;
857 frame_val = tr32(MAC_MI_COM);
858 if ((frame_val & MI_COM_BUSY) == 0) {
860 frame_val = tr32(MAC_MI_COM);
870 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
871 tw32_f(MAC_MI_MODE, tp->mi_mode);
878 static int tg3_bmcr_reset(struct tg3 *tp)
883 /* OK, reset it, and poll the BMCR_RESET bit until it
884 * clears or we time out.
886 phy_control = BMCR_RESET;
887 err = tg3_writephy(tp, MII_BMCR, phy_control);
893 err = tg3_readphy(tp, MII_BMCR, &phy_control);
897 if ((phy_control & BMCR_RESET) == 0) {
909 static int tg3_mdio_read(struct mii_bus *bp, int mii_id, int reg)
911 struct tg3 *tp = bp->priv;
914 spin_lock_bh(&tp->lock);
916 if (tg3_readphy(tp, reg, &val))
919 spin_unlock_bh(&tp->lock);
924 static int tg3_mdio_write(struct mii_bus *bp, int mii_id, int reg, u16 val)
926 struct tg3 *tp = bp->priv;
929 spin_lock_bh(&tp->lock);
931 if (tg3_writephy(tp, reg, val))
934 spin_unlock_bh(&tp->lock);
939 static int tg3_mdio_reset(struct mii_bus *bp)
944 static void tg3_mdio_config_5785(struct tg3 *tp)
947 struct phy_device *phydev;
949 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
950 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
951 case TG3_PHY_ID_BCM50610:
952 case TG3_PHY_ID_BCM50610M:
953 val = MAC_PHYCFG2_50610_LED_MODES;
955 case TG3_PHY_ID_BCMAC131:
956 val = MAC_PHYCFG2_AC131_LED_MODES;
958 case TG3_PHY_ID_RTL8211C:
959 val = MAC_PHYCFG2_RTL8211C_LED_MODES;
961 case TG3_PHY_ID_RTL8201E:
962 val = MAC_PHYCFG2_RTL8201E_LED_MODES;
968 if (phydev->interface != PHY_INTERFACE_MODE_RGMII) {
969 tw32(MAC_PHYCFG2, val);
971 val = tr32(MAC_PHYCFG1);
972 val &= ~(MAC_PHYCFG1_RGMII_INT |
973 MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK);
974 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT;
975 tw32(MAC_PHYCFG1, val);
980 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE))
981 val |= MAC_PHYCFG2_EMODE_MASK_MASK |
982 MAC_PHYCFG2_FMODE_MASK_MASK |
983 MAC_PHYCFG2_GMODE_MASK_MASK |
984 MAC_PHYCFG2_ACT_MASK_MASK |
985 MAC_PHYCFG2_QUAL_MASK_MASK |
986 MAC_PHYCFG2_INBAND_ENABLE;
988 tw32(MAC_PHYCFG2, val);
990 val = tr32(MAC_PHYCFG1);
991 val &= ~(MAC_PHYCFG1_RXCLK_TO_MASK | MAC_PHYCFG1_TXCLK_TO_MASK |
992 MAC_PHYCFG1_RGMII_EXT_RX_DEC | MAC_PHYCFG1_RGMII_SND_STAT_EN);
993 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
994 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
995 val |= MAC_PHYCFG1_RGMII_EXT_RX_DEC;
996 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
997 val |= MAC_PHYCFG1_RGMII_SND_STAT_EN;
999 val |= MAC_PHYCFG1_RXCLK_TIMEOUT | MAC_PHYCFG1_TXCLK_TIMEOUT |
1000 MAC_PHYCFG1_RGMII_INT | MAC_PHYCFG1_TXC_DRV;
1001 tw32(MAC_PHYCFG1, val);
1003 val = tr32(MAC_EXT_RGMII_MODE);
1004 val &= ~(MAC_RGMII_MODE_RX_INT_B |
1005 MAC_RGMII_MODE_RX_QUALITY |
1006 MAC_RGMII_MODE_RX_ACTIVITY |
1007 MAC_RGMII_MODE_RX_ENG_DET |
1008 MAC_RGMII_MODE_TX_ENABLE |
1009 MAC_RGMII_MODE_TX_LOWPWR |
1010 MAC_RGMII_MODE_TX_RESET);
1011 if (!(tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)) {
1012 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1013 val |= MAC_RGMII_MODE_RX_INT_B |
1014 MAC_RGMII_MODE_RX_QUALITY |
1015 MAC_RGMII_MODE_RX_ACTIVITY |
1016 MAC_RGMII_MODE_RX_ENG_DET;
1017 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1018 val |= MAC_RGMII_MODE_TX_ENABLE |
1019 MAC_RGMII_MODE_TX_LOWPWR |
1020 MAC_RGMII_MODE_TX_RESET;
1022 tw32(MAC_EXT_RGMII_MODE, val);
1025 static void tg3_mdio_start(struct tg3 *tp)
1027 tp->mi_mode &= ~MAC_MI_MODE_AUTO_POLL;
1028 tw32_f(MAC_MI_MODE, tp->mi_mode);
1031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
1032 u32 funcnum, is_serdes;
1034 funcnum = tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC;
1040 is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
1044 tp->phy_addr = TG3_PHY_MII_ADDR;
1046 if ((tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) &&
1047 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1048 tg3_mdio_config_5785(tp);
1051 static int tg3_mdio_init(struct tg3 *tp)
1055 struct phy_device *phydev;
1059 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) ||
1060 (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED))
1063 tp->mdio_bus = mdiobus_alloc();
1064 if (tp->mdio_bus == NULL)
1067 tp->mdio_bus->name = "tg3 mdio bus";
1068 snprintf(tp->mdio_bus->id, MII_BUS_ID_SIZE, "%x",
1069 (tp->pdev->bus->number << 8) | tp->pdev->devfn);
1070 tp->mdio_bus->priv = tp;
1071 tp->mdio_bus->parent = &tp->pdev->dev;
1072 tp->mdio_bus->read = &tg3_mdio_read;
1073 tp->mdio_bus->write = &tg3_mdio_write;
1074 tp->mdio_bus->reset = &tg3_mdio_reset;
1075 tp->mdio_bus->phy_mask = ~(1 << TG3_PHY_MII_ADDR);
1076 tp->mdio_bus->irq = &tp->mdio_irq[0];
1078 for (i = 0; i < PHY_MAX_ADDR; i++)
1079 tp->mdio_bus->irq[i] = PHY_POLL;
1081 /* The bus registration will look for all the PHYs on the mdio bus.
1082 * Unfortunately, it does not ensure the PHY is powered up before
1083 * accessing the PHY ID registers. A chip reset is the
1084 * quickest way to bring the device back to an operational state..
1086 if (tg3_readphy(tp, MII_BMCR, ®) || (reg & BMCR_PDOWN))
1089 i = mdiobus_register(tp->mdio_bus);
1091 printk(KERN_WARNING "%s: mdiobus_reg failed (0x%x)\n",
1093 mdiobus_free(tp->mdio_bus);
1097 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1099 if (!phydev || !phydev->drv) {
1100 printk(KERN_WARNING "%s: No PHY devices\n", tp->dev->name);
1101 mdiobus_unregister(tp->mdio_bus);
1102 mdiobus_free(tp->mdio_bus);
1106 switch (phydev->drv->phy_id & phydev->drv->phy_id_mask) {
1107 case TG3_PHY_ID_BCM57780:
1108 phydev->interface = PHY_INTERFACE_MODE_GMII;
1109 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1111 case TG3_PHY_ID_BCM50610:
1112 case TG3_PHY_ID_BCM50610M:
1113 phydev->dev_flags |= PHY_BRCM_CLEAR_RGMII_MODE |
1114 PHY_BRCM_RX_REFCLK_UNUSED |
1115 PHY_BRCM_DIS_TXCRXC_NOENRGY |
1116 PHY_BRCM_AUTO_PWRDWN_ENABLE;
1117 if (tp->tg3_flags3 & TG3_FLG3_RGMII_STD_IBND_DISABLE)
1118 phydev->dev_flags |= PHY_BRCM_STD_IBND_DISABLE;
1119 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_RX_EN)
1120 phydev->dev_flags |= PHY_BRCM_EXT_IBND_RX_ENABLE;
1121 if (tp->tg3_flags3 & TG3_FLG3_RGMII_EXT_IBND_TX_EN)
1122 phydev->dev_flags |= PHY_BRCM_EXT_IBND_TX_ENABLE;
1124 case TG3_PHY_ID_RTL8211C:
1125 phydev->interface = PHY_INTERFACE_MODE_RGMII;
1127 case TG3_PHY_ID_RTL8201E:
1128 case TG3_PHY_ID_BCMAC131:
1129 phydev->interface = PHY_INTERFACE_MODE_MII;
1130 phydev->dev_flags |= PHY_BRCM_AUTO_PWRDWN_ENABLE;
1131 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
1135 tp->tg3_flags3 |= TG3_FLG3_MDIOBUS_INITED;
1137 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
1138 tg3_mdio_config_5785(tp);
1143 static void tg3_mdio_fini(struct tg3 *tp)
1145 if (tp->tg3_flags3 & TG3_FLG3_MDIOBUS_INITED) {
1146 tp->tg3_flags3 &= ~TG3_FLG3_MDIOBUS_INITED;
1147 mdiobus_unregister(tp->mdio_bus);
1148 mdiobus_free(tp->mdio_bus);
1152 /* tp->lock is held. */
1153 static inline void tg3_generate_fw_event(struct tg3 *tp)
1157 val = tr32(GRC_RX_CPU_EVENT);
1158 val |= GRC_RX_CPU_DRIVER_EVENT;
1159 tw32_f(GRC_RX_CPU_EVENT, val);
1161 tp->last_event_jiffies = jiffies;
1164 #define TG3_FW_EVENT_TIMEOUT_USEC 2500
1166 /* tp->lock is held. */
1167 static void tg3_wait_for_event_ack(struct tg3 *tp)
1170 unsigned int delay_cnt;
1173 /* If enough time has passed, no wait is necessary. */
1174 time_remain = (long)(tp->last_event_jiffies + 1 +
1175 usecs_to_jiffies(TG3_FW_EVENT_TIMEOUT_USEC)) -
1177 if (time_remain < 0)
1180 /* Check if we can shorten the wait time. */
1181 delay_cnt = jiffies_to_usecs(time_remain);
1182 if (delay_cnt > TG3_FW_EVENT_TIMEOUT_USEC)
1183 delay_cnt = TG3_FW_EVENT_TIMEOUT_USEC;
1184 delay_cnt = (delay_cnt >> 3) + 1;
1186 for (i = 0; i < delay_cnt; i++) {
1187 if (!(tr32(GRC_RX_CPU_EVENT) & GRC_RX_CPU_DRIVER_EVENT))
1193 /* tp->lock is held. */
1194 static void tg3_ump_link_report(struct tg3 *tp)
1199 if (!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1200 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1203 tg3_wait_for_event_ack(tp);
1205 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1207 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1210 if (!tg3_readphy(tp, MII_BMCR, ®))
1212 if (!tg3_readphy(tp, MII_BMSR, ®))
1213 val |= (reg & 0xffff);
1214 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1217 if (!tg3_readphy(tp, MII_ADVERTISE, ®))
1219 if (!tg3_readphy(tp, MII_LPA, ®))
1220 val |= (reg & 0xffff);
1221 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1224 if (!(tp->tg3_flags2 & TG3_FLG2_MII_SERDES)) {
1225 if (!tg3_readphy(tp, MII_CTRL1000, ®))
1227 if (!tg3_readphy(tp, MII_STAT1000, ®))
1228 val |= (reg & 0xffff);
1230 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1232 if (!tg3_readphy(tp, MII_PHYADDR, ®))
1236 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1238 tg3_generate_fw_event(tp);
1241 static void tg3_link_report(struct tg3 *tp)
1243 if (!netif_carrier_ok(tp->dev)) {
1244 if (netif_msg_link(tp))
1245 printk(KERN_INFO PFX "%s: Link is down.\n",
1247 tg3_ump_link_report(tp);
1248 } else if (netif_msg_link(tp)) {
1249 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1251 (tp->link_config.active_speed == SPEED_1000 ?
1253 (tp->link_config.active_speed == SPEED_100 ?
1255 (tp->link_config.active_duplex == DUPLEX_FULL ?
1258 printk(KERN_INFO PFX
1259 "%s: Flow control is %s for TX and %s for RX.\n",
1261 (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1263 (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1265 tg3_ump_link_report(tp);
1269 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
1273 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1274 miireg = ADVERTISE_PAUSE_CAP;
1275 else if (flow_ctrl & FLOW_CTRL_TX)
1276 miireg = ADVERTISE_PAUSE_ASYM;
1277 else if (flow_ctrl & FLOW_CTRL_RX)
1278 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1285 static u16 tg3_advert_flowctrl_1000X(u8 flow_ctrl)
1289 if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
1290 miireg = ADVERTISE_1000XPAUSE;
1291 else if (flow_ctrl & FLOW_CTRL_TX)
1292 miireg = ADVERTISE_1000XPSE_ASYM;
1293 else if (flow_ctrl & FLOW_CTRL_RX)
1294 miireg = ADVERTISE_1000XPAUSE | ADVERTISE_1000XPSE_ASYM;
1301 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1305 if (lcladv & ADVERTISE_1000XPAUSE) {
1306 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1307 if (rmtadv & LPA_1000XPAUSE)
1308 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1309 else if (rmtadv & LPA_1000XPAUSE_ASYM)
1312 if (rmtadv & LPA_1000XPAUSE)
1313 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1315 } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1316 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1323 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1327 u32 old_rx_mode = tp->rx_mode;
1328 u32 old_tx_mode = tp->tx_mode;
1330 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
1331 autoneg = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]->autoneg;
1333 autoneg = tp->link_config.autoneg;
1335 if (autoneg == AUTONEG_ENABLE &&
1336 (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)) {
1337 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
1338 flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1340 flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1342 flowctrl = tp->link_config.flowctrl;
1344 tp->link_config.active_flowctrl = flowctrl;
1346 if (flowctrl & FLOW_CTRL_RX)
1347 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1349 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1351 if (old_rx_mode != tp->rx_mode)
1352 tw32_f(MAC_RX_MODE, tp->rx_mode);
1354 if (flowctrl & FLOW_CTRL_TX)
1355 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1357 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1359 if (old_tx_mode != tp->tx_mode)
1360 tw32_f(MAC_TX_MODE, tp->tx_mode);
1363 static void tg3_adjust_link(struct net_device *dev)
1365 u8 oldflowctrl, linkmesg = 0;
1366 u32 mac_mode, lcl_adv, rmt_adv;
1367 struct tg3 *tp = netdev_priv(dev);
1368 struct phy_device *phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1370 spin_lock_bh(&tp->lock);
1372 mac_mode = tp->mac_mode & ~(MAC_MODE_PORT_MODE_MASK |
1373 MAC_MODE_HALF_DUPLEX);
1375 oldflowctrl = tp->link_config.active_flowctrl;
1381 if (phydev->speed == SPEED_100 || phydev->speed == SPEED_10)
1382 mac_mode |= MAC_MODE_PORT_MODE_MII;
1383 else if (phydev->speed == SPEED_1000 ||
1384 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785)
1385 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1387 mac_mode |= MAC_MODE_PORT_MODE_MII;
1389 if (phydev->duplex == DUPLEX_HALF)
1390 mac_mode |= MAC_MODE_HALF_DUPLEX;
1392 lcl_adv = tg3_advert_flowctrl_1000T(
1393 tp->link_config.flowctrl);
1396 rmt_adv = LPA_PAUSE_CAP;
1397 if (phydev->asym_pause)
1398 rmt_adv |= LPA_PAUSE_ASYM;
1401 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1403 mac_mode |= MAC_MODE_PORT_MODE_GMII;
1405 if (mac_mode != tp->mac_mode) {
1406 tp->mac_mode = mac_mode;
1407 tw32_f(MAC_MODE, tp->mac_mode);
1411 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
1412 if (phydev->speed == SPEED_10)
1414 MAC_MI_STAT_10MBPS_MODE |
1415 MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1417 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
1420 if (phydev->speed == SPEED_1000 && phydev->duplex == DUPLEX_HALF)
1421 tw32(MAC_TX_LENGTHS,
1422 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1423 (6 << TX_LENGTHS_IPG_SHIFT) |
1424 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
1426 tw32(MAC_TX_LENGTHS,
1427 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1428 (6 << TX_LENGTHS_IPG_SHIFT) |
1429 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
1431 if ((phydev->link && tp->link_config.active_speed == SPEED_INVALID) ||
1432 (!phydev->link && tp->link_config.active_speed != SPEED_INVALID) ||
1433 phydev->speed != tp->link_config.active_speed ||
1434 phydev->duplex != tp->link_config.active_duplex ||
1435 oldflowctrl != tp->link_config.active_flowctrl)
1438 tp->link_config.active_speed = phydev->speed;
1439 tp->link_config.active_duplex = phydev->duplex;
1441 spin_unlock_bh(&tp->lock);
1444 tg3_link_report(tp);
1447 static int tg3_phy_init(struct tg3 *tp)
1449 struct phy_device *phydev;
1451 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED)
1454 /* Bring the PHY back to a known state. */
1457 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1459 /* Attach the MAC to the PHY. */
1460 phydev = phy_connect(tp->dev, dev_name(&phydev->dev), tg3_adjust_link,
1461 phydev->dev_flags, phydev->interface);
1462 if (IS_ERR(phydev)) {
1463 printk(KERN_ERR "%s: Could not attach to PHY\n", tp->dev->name);
1464 return PTR_ERR(phydev);
1467 /* Mask with MAC supported features. */
1468 switch (phydev->interface) {
1469 case PHY_INTERFACE_MODE_GMII:
1470 case PHY_INTERFACE_MODE_RGMII:
1471 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1472 phydev->supported &= (PHY_GBIT_FEATURES |
1474 SUPPORTED_Asym_Pause);
1478 case PHY_INTERFACE_MODE_MII:
1479 phydev->supported &= (PHY_BASIC_FEATURES |
1481 SUPPORTED_Asym_Pause);
1484 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1488 tp->tg3_flags3 |= TG3_FLG3_PHY_CONNECTED;
1490 phydev->advertising = phydev->supported;
1495 static void tg3_phy_start(struct tg3 *tp)
1497 struct phy_device *phydev;
1499 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1502 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
1504 if (tp->link_config.phy_is_low_power) {
1505 tp->link_config.phy_is_low_power = 0;
1506 phydev->speed = tp->link_config.orig_speed;
1507 phydev->duplex = tp->link_config.orig_duplex;
1508 phydev->autoneg = tp->link_config.orig_autoneg;
1509 phydev->advertising = tp->link_config.orig_advertising;
1514 phy_start_aneg(phydev);
1517 static void tg3_phy_stop(struct tg3 *tp)
1519 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
1522 phy_stop(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1525 static void tg3_phy_fini(struct tg3 *tp)
1527 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
1528 phy_disconnect(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
1529 tp->tg3_flags3 &= ~TG3_FLG3_PHY_CONNECTED;
1533 static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
1535 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
1536 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
1539 static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
1543 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
1546 tg3_writephy(tp, MII_TG3_FET_TEST,
1547 phytest | MII_TG3_FET_SHADOW_EN);
1548 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXSTAT2, &phy)) {
1550 phy |= MII_TG3_FET_SHDW_AUXSTAT2_APD;
1552 phy &= ~MII_TG3_FET_SHDW_AUXSTAT2_APD;
1553 tg3_writephy(tp, MII_TG3_FET_SHDW_AUXSTAT2, phy);
1555 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
1559 static void tg3_phy_toggle_apd(struct tg3 *tp, bool enable)
1563 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1564 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1565 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1568 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1569 tg3_phy_fet_toggle_apd(tp, enable);
1573 reg = MII_TG3_MISC_SHDW_WREN |
1574 MII_TG3_MISC_SHDW_SCR5_SEL |
1575 MII_TG3_MISC_SHDW_SCR5_LPED |
1576 MII_TG3_MISC_SHDW_SCR5_DLPTLM |
1577 MII_TG3_MISC_SHDW_SCR5_SDTL |
1578 MII_TG3_MISC_SHDW_SCR5_C125OE;
1579 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 || !enable)
1580 reg |= MII_TG3_MISC_SHDW_SCR5_DLLAPD;
1582 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1585 reg = MII_TG3_MISC_SHDW_WREN |
1586 MII_TG3_MISC_SHDW_APD_SEL |
1587 MII_TG3_MISC_SHDW_APD_WKTM_84MS;
1589 reg |= MII_TG3_MISC_SHDW_APD_ENABLE;
1591 tg3_writephy(tp, MII_TG3_MISC_SHDW, reg);
1594 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
1598 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
1599 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
1602 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
1605 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
1606 u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
1608 tg3_writephy(tp, MII_TG3_FET_TEST,
1609 ephy | MII_TG3_FET_SHADOW_EN);
1610 if (!tg3_readphy(tp, reg, &phy)) {
1612 phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1614 phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
1615 tg3_writephy(tp, reg, phy);
1617 tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
1620 phy = MII_TG3_AUXCTL_MISC_RDSEL_MISC |
1621 MII_TG3_AUXCTL_SHDWSEL_MISC;
1622 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, phy) &&
1623 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy)) {
1625 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1627 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
1628 phy |= MII_TG3_AUXCTL_MISC_WREN;
1629 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1634 static void tg3_phy_set_wirespeed(struct tg3 *tp)
1638 if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
1641 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
1642 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
1643 tg3_writephy(tp, MII_TG3_AUX_CTRL,
1644 (val | (1 << 15) | (1 << 4)));
1647 static void tg3_phy_apply_otp(struct tg3 *tp)
1656 /* Enable SM_DSP clock and tx 6dB coding. */
1657 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1658 MII_TG3_AUXCTL_ACTL_SMDSP_ENA |
1659 MII_TG3_AUXCTL_ACTL_TX_6DB;
1660 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1662 phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
1663 phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
1664 tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
1666 phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
1667 ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
1668 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
1670 phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
1671 phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
1672 tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
1674 phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
1675 tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
1677 phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
1678 tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
1680 phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
1681 ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
1682 tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
1684 /* Turn off SM_DSP clock. */
1685 phy = MII_TG3_AUXCTL_SHDWSEL_AUXCTL |
1686 MII_TG3_AUXCTL_ACTL_TX_6DB;
1687 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy);
1690 static int tg3_wait_macro_done(struct tg3 *tp)
1697 if (!tg3_readphy(tp, 0x16, &tmp32)) {
1698 if ((tmp32 & 0x1000) == 0)
1708 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
1710 static const u32 test_pat[4][6] = {
1711 { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
1712 { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
1713 { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
1714 { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
1718 for (chan = 0; chan < 4; chan++) {
1721 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1722 (chan * 0x2000) | 0x0200);
1723 tg3_writephy(tp, 0x16, 0x0002);
1725 for (i = 0; i < 6; i++)
1726 tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
1729 tg3_writephy(tp, 0x16, 0x0202);
1730 if (tg3_wait_macro_done(tp)) {
1735 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1736 (chan * 0x2000) | 0x0200);
1737 tg3_writephy(tp, 0x16, 0x0082);
1738 if (tg3_wait_macro_done(tp)) {
1743 tg3_writephy(tp, 0x16, 0x0802);
1744 if (tg3_wait_macro_done(tp)) {
1749 for (i = 0; i < 6; i += 2) {
1752 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
1753 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
1754 tg3_wait_macro_done(tp)) {
1760 if (low != test_pat[chan][i] ||
1761 high != test_pat[chan][i+1]) {
1762 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
1763 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
1764 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
1774 static int tg3_phy_reset_chanpat(struct tg3 *tp)
1778 for (chan = 0; chan < 4; chan++) {
1781 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
1782 (chan * 0x2000) | 0x0200);
1783 tg3_writephy(tp, 0x16, 0x0002);
1784 for (i = 0; i < 6; i++)
1785 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
1786 tg3_writephy(tp, 0x16, 0x0202);
1787 if (tg3_wait_macro_done(tp))
1794 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
1796 u32 reg32, phy9_orig;
1797 int retries, do_phy_reset, err;
1803 err = tg3_bmcr_reset(tp);
1809 /* Disable transmitter and interrupt. */
1810 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32))
1814 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1816 /* Set full-duplex, 1000 mbps. */
1817 tg3_writephy(tp, MII_BMCR,
1818 BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
1820 /* Set to master mode. */
1821 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
1824 tg3_writephy(tp, MII_TG3_CTRL,
1825 (MII_TG3_CTRL_AS_MASTER |
1826 MII_TG3_CTRL_ENABLE_AS_MASTER));
1828 /* Enable SM_DSP_CLOCK and 6dB. */
1829 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1831 /* Block the PHY control access. */
1832 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1833 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
1835 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
1838 } while (--retries);
1840 err = tg3_phy_reset_chanpat(tp);
1844 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
1845 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
1847 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
1848 tg3_writephy(tp, 0x16, 0x0000);
1850 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1851 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1852 /* Set Extended packet length bit for jumbo frames */
1853 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
1856 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1859 tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
1861 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, ®32)) {
1863 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
1870 /* This will reset the tigon3 PHY if there is no valid
1871 * link unless the FORCE argument is non-zero.
1873 static int tg3_phy_reset(struct tg3 *tp)
1879 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1882 val = tr32(GRC_MISC_CFG);
1883 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
1886 err = tg3_readphy(tp, MII_BMSR, &phy_status);
1887 err |= tg3_readphy(tp, MII_BMSR, &phy_status);
1891 if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
1892 netif_carrier_off(tp->dev);
1893 tg3_link_report(tp);
1896 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1897 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1898 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
1899 err = tg3_phy_reset_5703_4_5(tp);
1906 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
1907 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
1908 cpmuctrl = tr32(TG3_CPMU_CTRL);
1909 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
1911 cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
1914 err = tg3_bmcr_reset(tp);
1918 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
1921 phy = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
1922 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, phy);
1924 tw32(TG3_CPMU_CTRL, cpmuctrl);
1927 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
1928 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
1931 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
1932 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
1933 CPMU_LSPD_1000MB_MACCLK_12_5) {
1934 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
1936 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
1940 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
1941 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES))
1944 tg3_phy_apply_otp(tp);
1946 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
1947 tg3_phy_toggle_apd(tp, true);
1949 tg3_phy_toggle_apd(tp, false);
1952 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
1953 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1954 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1955 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
1956 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1957 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
1958 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1960 if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
1961 tg3_writephy(tp, 0x1c, 0x8d68);
1962 tg3_writephy(tp, 0x1c, 0x8d68);
1964 if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1965 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1966 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1967 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1968 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1969 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1970 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1971 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1972 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1974 else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1975 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1976 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1977 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1978 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1979 tg3_writephy(tp, MII_TG3_TEST1,
1980 MII_TG3_TEST1_TRIM_EN | 0x4);
1982 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1983 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1985 /* Set Extended packet length bit (bit 14) on all chips that */
1986 /* support jumbo frames */
1987 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1988 /* Cannot do read-modify-write on 5401 */
1989 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1990 } else if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
1993 /* Set bit 14 with read-modify-write to preserve other bits */
1994 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1995 !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1996 tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1999 /* Set phy register 0x10 bit 0 to high fifo elasticity to support
2000 * jumbo frames transmission.
2002 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
2005 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
2006 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2007 phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
2010 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2011 /* adjust output voltage */
2012 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
2015 tg3_phy_toggle_automdix(tp, 1);
2016 tg3_phy_set_wirespeed(tp);
2020 static void tg3_frob_aux_power(struct tg3 *tp)
2022 struct tg3 *tp_peer = tp;
2024 if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
2027 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
2029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
2030 struct net_device *dev_peer;
2032 dev_peer = pci_get_drvdata(tp->pdev_peer);
2033 /* remove_one() may have been run on the peer. */
2037 tp_peer = netdev_priv(dev_peer);
2040 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2041 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
2042 (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
2043 (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
2044 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2045 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2046 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2047 (GRC_LCLCTRL_GPIO_OE0 |
2048 GRC_LCLCTRL_GPIO_OE1 |
2049 GRC_LCLCTRL_GPIO_OE2 |
2050 GRC_LCLCTRL_GPIO_OUTPUT0 |
2051 GRC_LCLCTRL_GPIO_OUTPUT1),
2053 } else if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
2054 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
2055 /* The 5761 non-e device swaps GPIO 0 and GPIO 2. */
2056 u32 grc_local_ctrl = GRC_LCLCTRL_GPIO_OE0 |
2057 GRC_LCLCTRL_GPIO_OE1 |
2058 GRC_LCLCTRL_GPIO_OE2 |
2059 GRC_LCLCTRL_GPIO_OUTPUT0 |
2060 GRC_LCLCTRL_GPIO_OUTPUT1 |
2062 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2064 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT2;
2065 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2067 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT0;
2068 tw32_wait_f(GRC_LOCAL_CTRL, grc_local_ctrl, 100);
2071 u32 grc_local_ctrl = 0;
2073 if (tp_peer != tp &&
2074 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2077 /* Workaround to prevent overdrawing Amps. */
2078 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2080 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
2081 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2082 grc_local_ctrl, 100);
2085 /* On 5753 and variants, GPIO2 cannot be used. */
2086 no_gpio2 = tp->nic_sram_data_cfg &
2087 NIC_SRAM_DATA_CFG_NO_GPIO2;
2089 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
2090 GRC_LCLCTRL_GPIO_OE1 |
2091 GRC_LCLCTRL_GPIO_OE2 |
2092 GRC_LCLCTRL_GPIO_OUTPUT1 |
2093 GRC_LCLCTRL_GPIO_OUTPUT2;
2095 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
2096 GRC_LCLCTRL_GPIO_OUTPUT2);
2098 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2099 grc_local_ctrl, 100);
2101 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
2103 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2104 grc_local_ctrl, 100);
2107 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
2108 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2109 grc_local_ctrl, 100);
2113 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
2114 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
2115 if (tp_peer != tp &&
2116 (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
2119 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2120 (GRC_LCLCTRL_GPIO_OE1 |
2121 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2123 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2124 GRC_LCLCTRL_GPIO_OE1, 100);
2126 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
2127 (GRC_LCLCTRL_GPIO_OE1 |
2128 GRC_LCLCTRL_GPIO_OUTPUT1), 100);
2133 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
2135 if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
2137 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411) {
2138 if (speed != SPEED_10)
2140 } else if (speed == SPEED_10)
2146 static int tg3_setup_phy(struct tg3 *, int);
2148 #define RESET_KIND_SHUTDOWN 0
2149 #define RESET_KIND_INIT 1
2150 #define RESET_KIND_SUSPEND 2
2152 static void tg3_write_sig_post_reset(struct tg3 *, int);
2153 static int tg3_halt_cpu(struct tg3 *, u32);
2155 static void tg3_power_down_phy(struct tg3 *tp, bool do_low_power)
2159 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2160 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2161 u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
2162 u32 serdes_cfg = tr32(MAC_SERDES_CFG);
2165 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
2166 tw32(SG_DIG_CTRL, sg_dig_ctrl);
2167 tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
2172 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2174 val = tr32(GRC_MISC_CFG);
2175 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
2178 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2180 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &phytest)) {
2183 tg3_writephy(tp, MII_ADVERTISE, 0);
2184 tg3_writephy(tp, MII_BMCR,
2185 BMCR_ANENABLE | BMCR_ANRESTART);
2187 tg3_writephy(tp, MII_TG3_FET_TEST,
2188 phytest | MII_TG3_FET_SHADOW_EN);
2189 if (!tg3_readphy(tp, MII_TG3_FET_SHDW_AUXMODE4, &phy)) {
2190 phy |= MII_TG3_FET_SHDW_AUXMODE4_SBPD;
2192 MII_TG3_FET_SHDW_AUXMODE4,
2195 tg3_writephy(tp, MII_TG3_FET_TEST, phytest);
2198 } else if (do_low_power) {
2199 tg3_writephy(tp, MII_TG3_EXT_CTRL,
2200 MII_TG3_EXT_CTRL_FORCE_LED_OFF);
2202 tg3_writephy(tp, MII_TG3_AUX_CTRL,
2203 MII_TG3_AUXCTL_SHDWSEL_PWRCTL |
2204 MII_TG3_AUXCTL_PCTL_100TX_LPWR |
2205 MII_TG3_AUXCTL_PCTL_SPR_ISOLATE |
2206 MII_TG3_AUXCTL_PCTL_VREG_11V);
2209 /* The PHY should not be powered down on some chips because
2212 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2213 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
2214 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
2215 (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
2218 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
2219 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
2220 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
2221 val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
2222 val |= CPMU_LSPD_1000MB_MACCLK_12_5;
2223 tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
2226 tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
2229 /* tp->lock is held. */
2230 static int tg3_nvram_lock(struct tg3 *tp)
2232 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2235 if (tp->nvram_lock_cnt == 0) {
2236 tw32(NVRAM_SWARB, SWARB_REQ_SET1);
2237 for (i = 0; i < 8000; i++) {
2238 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
2243 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
2247 tp->nvram_lock_cnt++;
2252 /* tp->lock is held. */
2253 static void tg3_nvram_unlock(struct tg3 *tp)
2255 if (tp->tg3_flags & TG3_FLAG_NVRAM) {
2256 if (tp->nvram_lock_cnt > 0)
2257 tp->nvram_lock_cnt--;
2258 if (tp->nvram_lock_cnt == 0)
2259 tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
2263 /* tp->lock is held. */
2264 static void tg3_enable_nvram_access(struct tg3 *tp)
2266 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2267 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2268 u32 nvaccess = tr32(NVRAM_ACCESS);
2270 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
2274 /* tp->lock is held. */
2275 static void tg3_disable_nvram_access(struct tg3 *tp)
2277 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2278 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM)) {
2279 u32 nvaccess = tr32(NVRAM_ACCESS);
2281 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
2285 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
2286 u32 offset, u32 *val)
2291 if (offset > EEPROM_ADDR_ADDR_MASK || (offset % 4) != 0)
2294 tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
2295 EEPROM_ADDR_DEVID_MASK |
2297 tw32(GRC_EEPROM_ADDR,
2299 (0 << EEPROM_ADDR_DEVID_SHIFT) |
2300 ((offset << EEPROM_ADDR_ADDR_SHIFT) &
2301 EEPROM_ADDR_ADDR_MASK) |
2302 EEPROM_ADDR_READ | EEPROM_ADDR_START);
2304 for (i = 0; i < 1000; i++) {
2305 tmp = tr32(GRC_EEPROM_ADDR);
2307 if (tmp & EEPROM_ADDR_COMPLETE)
2311 if (!(tmp & EEPROM_ADDR_COMPLETE))
2314 tmp = tr32(GRC_EEPROM_DATA);
2317 * The data will always be opposite the native endian
2318 * format. Perform a blind byteswap to compensate.
2325 #define NVRAM_CMD_TIMEOUT 10000
2327 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
2331 tw32(NVRAM_CMD, nvram_cmd);
2332 for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
2334 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
2340 if (i == NVRAM_CMD_TIMEOUT)
2346 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
2348 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2349 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2350 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2351 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2352 (tp->nvram_jedecnum == JEDEC_ATMEL))
2354 addr = ((addr / tp->nvram_pagesize) <<
2355 ATMEL_AT45DB0X1B_PAGE_POS) +
2356 (addr % tp->nvram_pagesize);
2361 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
2363 if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
2364 (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
2365 (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
2366 !(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM_ADDR_TRANS) &&
2367 (tp->nvram_jedecnum == JEDEC_ATMEL))
2369 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
2370 tp->nvram_pagesize) +
2371 (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
2376 /* NOTE: Data read in from NVRAM is byteswapped according to
2377 * the byteswapping settings for all other register accesses.
2378 * tg3 devices are BE devices, so on a BE machine, the data
2379 * returned will be exactly as it is seen in NVRAM. On a LE
2380 * machine, the 32-bit value will be byteswapped.
2382 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
2386 if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
2387 return tg3_nvram_read_using_eeprom(tp, offset, val);
2389 offset = tg3_nvram_phys_addr(tp, offset);
2391 if (offset > NVRAM_ADDR_MSK)
2394 ret = tg3_nvram_lock(tp);
2398 tg3_enable_nvram_access(tp);
2400 tw32(NVRAM_ADDR, offset);
2401 ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
2402 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
2405 *val = tr32(NVRAM_RDDATA);
2407 tg3_disable_nvram_access(tp);
2409 tg3_nvram_unlock(tp);
2414 /* Ensures NVRAM data is in bytestream format. */
2415 static int tg3_nvram_read_be32(struct tg3 *tp, u32 offset, __be32 *val)
2418 int res = tg3_nvram_read(tp, offset, &v);
2420 *val = cpu_to_be32(v);
2424 /* tp->lock is held. */
2425 static void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1)
2427 u32 addr_high, addr_low;
2430 addr_high = ((tp->dev->dev_addr[0] << 8) |
2431 tp->dev->dev_addr[1]);
2432 addr_low = ((tp->dev->dev_addr[2] << 24) |
2433 (tp->dev->dev_addr[3] << 16) |
2434 (tp->dev->dev_addr[4] << 8) |
2435 (tp->dev->dev_addr[5] << 0));
2436 for (i = 0; i < 4; i++) {
2437 if (i == 1 && skip_mac_1)
2439 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
2440 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
2443 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
2444 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
2445 for (i = 0; i < 12; i++) {
2446 tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
2447 tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
2451 addr_high = (tp->dev->dev_addr[0] +
2452 tp->dev->dev_addr[1] +
2453 tp->dev->dev_addr[2] +
2454 tp->dev->dev_addr[3] +
2455 tp->dev->dev_addr[4] +
2456 tp->dev->dev_addr[5]) &
2457 TX_BACKOFF_SEED_MASK;
2458 tw32(MAC_TX_BACKOFF_SEED, addr_high);
2461 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
2464 bool device_should_wake, do_low_power;
2466 /* Make sure register accesses (indirect or otherwise)
2467 * will function correctly.
2469 pci_write_config_dword(tp->pdev,
2470 TG3PCI_MISC_HOST_CTRL,
2471 tp->misc_host_ctrl);
2475 pci_enable_wake(tp->pdev, state, false);
2476 pci_set_power_state(tp->pdev, PCI_D0);
2478 /* Switch out of Vaux if it is a NIC */
2479 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
2480 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
2490 printk(KERN_ERR PFX "%s: Invalid power state (D%d) requested\n",
2491 tp->dev->name, state);
2495 /* Restore the CLKREQ setting. */
2496 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
2499 pci_read_config_word(tp->pdev,
2500 tp->pcie_cap + PCI_EXP_LNKCTL,
2502 lnkctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
2503 pci_write_config_word(tp->pdev,
2504 tp->pcie_cap + PCI_EXP_LNKCTL,
2508 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
2509 tw32(TG3PCI_MISC_HOST_CTRL,
2510 misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
2512 device_should_wake = pci_pme_capable(tp->pdev, state) &&
2513 device_may_wakeup(&tp->pdev->dev) &&
2514 (tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
2516 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
2517 do_low_power = false;
2518 if ((tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) &&
2519 !tp->link_config.phy_is_low_power) {
2520 struct phy_device *phydev;
2521 u32 phyid, advertising;
2523 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
2525 tp->link_config.phy_is_low_power = 1;
2527 tp->link_config.orig_speed = phydev->speed;
2528 tp->link_config.orig_duplex = phydev->duplex;
2529 tp->link_config.orig_autoneg = phydev->autoneg;
2530 tp->link_config.orig_advertising = phydev->advertising;
2532 advertising = ADVERTISED_TP |
2534 ADVERTISED_Autoneg |
2535 ADVERTISED_10baseT_Half;
2537 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2538 device_should_wake) {
2539 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2541 ADVERTISED_100baseT_Half |
2542 ADVERTISED_100baseT_Full |
2543 ADVERTISED_10baseT_Full;
2545 advertising |= ADVERTISED_10baseT_Full;
2548 phydev->advertising = advertising;
2550 phy_start_aneg(phydev);
2552 phyid = phydev->drv->phy_id & phydev->drv->phy_id_mask;
2553 if (phyid != TG3_PHY_ID_BCMAC131) {
2554 phyid &= TG3_PHY_OUI_MASK;
2555 if (phyid == TG3_PHY_OUI_1 ||
2556 phyid == TG3_PHY_OUI_2 ||
2557 phyid == TG3_PHY_OUI_3)
2558 do_low_power = true;
2562 do_low_power = true;
2564 if (tp->link_config.phy_is_low_power == 0) {
2565 tp->link_config.phy_is_low_power = 1;
2566 tp->link_config.orig_speed = tp->link_config.speed;
2567 tp->link_config.orig_duplex = tp->link_config.duplex;
2568 tp->link_config.orig_autoneg = tp->link_config.autoneg;
2571 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
2572 tp->link_config.speed = SPEED_10;
2573 tp->link_config.duplex = DUPLEX_HALF;
2574 tp->link_config.autoneg = AUTONEG_ENABLE;
2575 tg3_setup_phy(tp, 0);
2579 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
2582 val = tr32(GRC_VCPU_EXT_CTRL);
2583 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
2584 } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2588 for (i = 0; i < 200; i++) {
2589 tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
2590 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
2595 if (tp->tg3_flags & TG3_FLAG_WOL_CAP)
2596 tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
2597 WOL_DRV_STATE_SHUTDOWN |
2601 if (device_should_wake) {
2604 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
2606 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
2610 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
2611 mac_mode = MAC_MODE_PORT_MODE_GMII;
2613 mac_mode = MAC_MODE_PORT_MODE_MII;
2615 mac_mode |= tp->mac_mode & MAC_MODE_LINK_POLARITY;
2616 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2618 u32 speed = (tp->tg3_flags &
2619 TG3_FLAG_WOL_SPEED_100MB) ?
2620 SPEED_100 : SPEED_10;
2621 if (tg3_5700_link_polarity(tp, speed))
2622 mac_mode |= MAC_MODE_LINK_POLARITY;
2624 mac_mode &= ~MAC_MODE_LINK_POLARITY;
2627 mac_mode = MAC_MODE_PORT_MODE_TBI;
2630 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
2631 tw32(MAC_LED_CTRL, tp->led_ctrl);
2633 mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
2634 if (((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
2635 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) &&
2636 ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
2637 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)))
2638 mac_mode |= MAC_MODE_KEEP_FRAME_IN_WOL;
2640 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
2641 mac_mode |= tp->mac_mode &
2642 (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
2643 if (mac_mode & MAC_MODE_APE_TX_EN)
2644 mac_mode |= MAC_MODE_TDE_ENABLE;
2647 tw32_f(MAC_MODE, mac_mode);
2650 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
2654 if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
2655 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2656 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
2659 base_val = tp->pci_clock_ctrl;
2660 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
2661 CLOCK_CTRL_TXCLK_DISABLE);
2663 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
2664 CLOCK_CTRL_PWRDOWN_PLL133, 40);
2665 } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
2666 (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
2667 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
2669 } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
2670 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
2671 u32 newbits1, newbits2;
2673 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2674 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2675 newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
2676 CLOCK_CTRL_TXCLK_DISABLE |
2678 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2679 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
2680 newbits1 = CLOCK_CTRL_625_CORE;
2681 newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
2683 newbits1 = CLOCK_CTRL_ALTCLK;
2684 newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
2687 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
2690 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
2693 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
2696 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
2697 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
2698 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
2699 CLOCK_CTRL_TXCLK_DISABLE |
2700 CLOCK_CTRL_44MHZ_CORE);
2702 newbits3 = CLOCK_CTRL_44MHZ_CORE;
2705 tw32_wait_f(TG3PCI_CLOCK_CTRL,
2706 tp->pci_clock_ctrl | newbits3, 40);
2710 if (!(device_should_wake) &&
2711 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
2712 tg3_power_down_phy(tp, do_low_power);
2714 tg3_frob_aux_power(tp);
2716 /* Workaround for unstable PLL clock */
2717 if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
2718 (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
2719 u32 val = tr32(0x7d00);
2721 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
2723 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
2726 err = tg3_nvram_lock(tp);
2727 tg3_halt_cpu(tp, RX_CPU_BASE);
2729 tg3_nvram_unlock(tp);
2733 tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
2735 if (device_should_wake)
2736 pci_enable_wake(tp->pdev, state, true);
2738 /* Finally, set the new power state. */
2739 pci_set_power_state(tp->pdev, state);
2744 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
2746 switch (val & MII_TG3_AUX_STAT_SPDMASK) {
2747 case MII_TG3_AUX_STAT_10HALF:
2749 *duplex = DUPLEX_HALF;
2752 case MII_TG3_AUX_STAT_10FULL:
2754 *duplex = DUPLEX_FULL;
2757 case MII_TG3_AUX_STAT_100HALF:
2759 *duplex = DUPLEX_HALF;
2762 case MII_TG3_AUX_STAT_100FULL:
2764 *duplex = DUPLEX_FULL;
2767 case MII_TG3_AUX_STAT_1000HALF:
2768 *speed = SPEED_1000;
2769 *duplex = DUPLEX_HALF;
2772 case MII_TG3_AUX_STAT_1000FULL:
2773 *speed = SPEED_1000;
2774 *duplex = DUPLEX_FULL;
2778 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
2779 *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
2781 *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
2785 *speed = SPEED_INVALID;
2786 *duplex = DUPLEX_INVALID;
2791 static void tg3_phy_copper_begin(struct tg3 *tp)
2796 if (tp->link_config.phy_is_low_power) {
2797 /* Entering low power mode. Disable gigabit and
2798 * 100baseT advertisements.
2800 tg3_writephy(tp, MII_TG3_CTRL, 0);
2802 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
2803 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
2804 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
2805 new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
2807 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2808 } else if (tp->link_config.speed == SPEED_INVALID) {
2809 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
2810 tp->link_config.advertising &=
2811 ~(ADVERTISED_1000baseT_Half |
2812 ADVERTISED_1000baseT_Full);
2814 new_adv = ADVERTISE_CSMA;
2815 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
2816 new_adv |= ADVERTISE_10HALF;
2817 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
2818 new_adv |= ADVERTISE_10FULL;
2819 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
2820 new_adv |= ADVERTISE_100HALF;
2821 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
2822 new_adv |= ADVERTISE_100FULL;
2824 new_adv |= tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2826 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2828 if (tp->link_config.advertising &
2829 (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
2831 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2832 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
2833 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2834 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
2835 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
2836 (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2837 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
2838 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2839 MII_TG3_CTRL_ENABLE_AS_MASTER);
2840 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2842 tg3_writephy(tp, MII_TG3_CTRL, 0);
2845 new_adv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
2846 new_adv |= ADVERTISE_CSMA;
2848 /* Asking for a specific link mode. */
2849 if (tp->link_config.speed == SPEED_1000) {
2850 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2852 if (tp->link_config.duplex == DUPLEX_FULL)
2853 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
2855 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
2856 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
2857 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
2858 new_adv |= (MII_TG3_CTRL_AS_MASTER |
2859 MII_TG3_CTRL_ENABLE_AS_MASTER);
2861 if (tp->link_config.speed == SPEED_100) {
2862 if (tp->link_config.duplex == DUPLEX_FULL)
2863 new_adv |= ADVERTISE_100FULL;
2865 new_adv |= ADVERTISE_100HALF;
2867 if (tp->link_config.duplex == DUPLEX_FULL)
2868 new_adv |= ADVERTISE_10FULL;
2870 new_adv |= ADVERTISE_10HALF;
2872 tg3_writephy(tp, MII_ADVERTISE, new_adv);
2877 tg3_writephy(tp, MII_TG3_CTRL, new_adv);
2880 if (tp->link_config.autoneg == AUTONEG_DISABLE &&
2881 tp->link_config.speed != SPEED_INVALID) {
2882 u32 bmcr, orig_bmcr;
2884 tp->link_config.active_speed = tp->link_config.speed;
2885 tp->link_config.active_duplex = tp->link_config.duplex;
2888 switch (tp->link_config.speed) {
2894 bmcr |= BMCR_SPEED100;
2898 bmcr |= TG3_BMCR_SPEED1000;
2902 if (tp->link_config.duplex == DUPLEX_FULL)
2903 bmcr |= BMCR_FULLDPLX;
2905 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
2906 (bmcr != orig_bmcr)) {
2907 tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
2908 for (i = 0; i < 1500; i++) {
2912 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
2913 tg3_readphy(tp, MII_BMSR, &tmp))
2915 if (!(tmp & BMSR_LSTATUS)) {
2920 tg3_writephy(tp, MII_BMCR, bmcr);
2924 tg3_writephy(tp, MII_BMCR,
2925 BMCR_ANENABLE | BMCR_ANRESTART);
2929 static int tg3_init_5401phy_dsp(struct tg3 *tp)
2933 /* Turn off tap power management. */
2934 /* Set Extended packet length bit */
2935 err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
2937 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
2938 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
2940 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
2941 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
2943 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2944 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
2946 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
2947 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
2949 err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
2950 err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
2957 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
2959 u32 adv_reg, all_mask = 0;
2961 if (mask & ADVERTISED_10baseT_Half)
2962 all_mask |= ADVERTISE_10HALF;
2963 if (mask & ADVERTISED_10baseT_Full)
2964 all_mask |= ADVERTISE_10FULL;
2965 if (mask & ADVERTISED_100baseT_Half)
2966 all_mask |= ADVERTISE_100HALF;
2967 if (mask & ADVERTISED_100baseT_Full)
2968 all_mask |= ADVERTISE_100FULL;
2970 if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
2973 if ((adv_reg & all_mask) != all_mask)
2975 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
2979 if (mask & ADVERTISED_1000baseT_Half)
2980 all_mask |= ADVERTISE_1000HALF;
2981 if (mask & ADVERTISED_1000baseT_Full)
2982 all_mask |= ADVERTISE_1000FULL;
2984 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
2987 if ((tg3_ctrl & all_mask) != all_mask)
2993 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
2997 if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
3000 curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
3001 reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
3003 if (tp->link_config.active_duplex == DUPLEX_FULL) {
3004 if (curadv != reqadv)
3007 if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG)
3008 tg3_readphy(tp, MII_LPA, rmtadv);
3010 /* Reprogram the advertisement register, even if it
3011 * does not affect the current link. If the link
3012 * gets renegotiated in the future, we can save an
3013 * additional renegotiation cycle by advertising
3014 * it correctly in the first place.
3016 if (curadv != reqadv) {
3017 *lcladv &= ~(ADVERTISE_PAUSE_CAP |
3018 ADVERTISE_PAUSE_ASYM);
3019 tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
3026 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
3028 int current_link_up;
3030 u32 lcl_adv, rmt_adv;
3038 (MAC_STATUS_SYNC_CHANGED |
3039 MAC_STATUS_CFG_CHANGED |
3040 MAC_STATUS_MI_COMPLETION |
3041 MAC_STATUS_LNKSTATE_CHANGED));
3044 if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
3046 (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
3050 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
3052 /* Some third-party PHYs need to be reset on link going
3055 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
3056 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
3057 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
3058 netif_carrier_ok(tp->dev)) {
3059 tg3_readphy(tp, MII_BMSR, &bmsr);
3060 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3061 !(bmsr & BMSR_LSTATUS))
3067 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
3068 tg3_readphy(tp, MII_BMSR, &bmsr);
3069 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
3070 !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
3073 if (!(bmsr & BMSR_LSTATUS)) {
3074 err = tg3_init_5401phy_dsp(tp);
3078 tg3_readphy(tp, MII_BMSR, &bmsr);
3079 for (i = 0; i < 1000; i++) {
3081 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3082 (bmsr & BMSR_LSTATUS)) {
3088 if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
3089 !(bmsr & BMSR_LSTATUS) &&
3090 tp->link_config.active_speed == SPEED_1000) {
3091 err = tg3_phy_reset(tp);
3093 err = tg3_init_5401phy_dsp(tp);
3098 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
3099 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
3100 /* 5701 {A0,B0} CRC bug workaround */
3101 tg3_writephy(tp, 0x15, 0x0a75);
3102 tg3_writephy(tp, 0x1c, 0x8c68);
3103 tg3_writephy(tp, 0x1c, 0x8d68);
3104 tg3_writephy(tp, 0x1c, 0x8c68);
3107 /* Clear pending interrupts... */
3108 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3109 tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
3111 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
3112 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
3113 else if (!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
3114 tg3_writephy(tp, MII_TG3_IMASK, ~0);
3116 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
3117 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
3118 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
3119 tg3_writephy(tp, MII_TG3_EXT_CTRL,
3120 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
3122 tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
3125 current_link_up = 0;
3126 current_speed = SPEED_INVALID;
3127 current_duplex = DUPLEX_INVALID;
3129 if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
3132 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
3133 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
3134 if (!(val & (1 << 10))) {
3136 tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
3142 for (i = 0; i < 100; i++) {
3143 tg3_readphy(tp, MII_BMSR, &bmsr);
3144 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
3145 (bmsr & BMSR_LSTATUS))
3150 if (bmsr & BMSR_LSTATUS) {
3153 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
3154 for (i = 0; i < 2000; i++) {
3156 if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
3161 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
3166 for (i = 0; i < 200; i++) {
3167 tg3_readphy(tp, MII_BMCR, &bmcr);
3168 if (tg3_readphy(tp, MII_BMCR, &bmcr))
3170 if (bmcr && bmcr != 0x7fff)
3178 tp->link_config.active_speed = current_speed;
3179 tp->link_config.active_duplex = current_duplex;
3181 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3182 if ((bmcr & BMCR_ANENABLE) &&
3183 tg3_copper_is_advertising_all(tp,
3184 tp->link_config.advertising)) {
3185 if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
3187 current_link_up = 1;
3190 if (!(bmcr & BMCR_ANENABLE) &&
3191 tp->link_config.speed == current_speed &&
3192 tp->link_config.duplex == current_duplex &&
3193 tp->link_config.flowctrl ==
3194 tp->link_config.active_flowctrl) {
3195 current_link_up = 1;
3199 if (current_link_up == 1 &&
3200 tp->link_config.active_duplex == DUPLEX_FULL)
3201 tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
3205 if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
3208 tg3_phy_copper_begin(tp);
3210 tg3_readphy(tp, MII_BMSR, &tmp);
3211 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
3212 (tmp & BMSR_LSTATUS))
3213 current_link_up = 1;
3216 tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
3217 if (current_link_up == 1) {
3218 if (tp->link_config.active_speed == SPEED_100 ||
3219 tp->link_config.active_speed == SPEED_10)
3220 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3222 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3223 } else if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)
3224 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
3226 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
3228 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
3229 if (tp->link_config.active_duplex == DUPLEX_HALF)
3230 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
3232 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
3233 if (current_link_up == 1 &&
3234 tg3_5700_link_polarity(tp, tp->link_config.active_speed))
3235 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
3237 tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
3240 /* ??? Without this setting Netgear GA302T PHY does not
3241 * ??? send/receive packets...
3243 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
3244 tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
3245 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
3246 tw32_f(MAC_MI_MODE, tp->mi_mode);
3250 tw32_f(MAC_MODE, tp->mac_mode);
3253 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
3254 /* Polled via timer. */
3255 tw32_f(MAC_EVENT, 0);
3257 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3261 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
3262 current_link_up == 1 &&
3263 tp->link_config.active_speed == SPEED_1000 &&
3264 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
3265 (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
3268 (MAC_STATUS_SYNC_CHANGED |
3269 MAC_STATUS_CFG_CHANGED));
3272 NIC_SRAM_FIRMWARE_MBOX,
3273 NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
3276 /* Prevent send BD corruption. */
3277 if (tp->tg3_flags3 & TG3_FLG3_CLKREQ_BUG) {
3278 u16 oldlnkctl, newlnkctl;
3280 pci_read_config_word(tp->pdev,
3281 tp->pcie_cap + PCI_EXP_LNKCTL,
3283 if (tp->link_config.active_speed == SPEED_100 ||
3284 tp->link_config.active_speed == SPEED_10)
3285 newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
3287 newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
3288 if (newlnkctl != oldlnkctl)
3289 pci_write_config_word(tp->pdev,
3290 tp->pcie_cap + PCI_EXP_LNKCTL,
3294 if (current_link_up != netif_carrier_ok(tp->dev)) {
3295 if (current_link_up)
3296 netif_carrier_on(tp->dev);
3298 netif_carrier_off(tp->dev);
3299 tg3_link_report(tp);
3305 struct tg3_fiber_aneginfo {
3307 #define ANEG_STATE_UNKNOWN 0
3308 #define ANEG_STATE_AN_ENABLE 1
3309 #define ANEG_STATE_RESTART_INIT 2
3310 #define ANEG_STATE_RESTART 3
3311 #define ANEG_STATE_DISABLE_LINK_OK 4
3312 #define ANEG_STATE_ABILITY_DETECT_INIT 5
3313 #define ANEG_STATE_ABILITY_DETECT 6
3314 #define ANEG_STATE_ACK_DETECT_INIT 7
3315 #define ANEG_STATE_ACK_DETECT 8
3316 #define ANEG_STATE_COMPLETE_ACK_INIT 9
3317 #define ANEG_STATE_COMPLETE_ACK 10
3318 #define ANEG_STATE_IDLE_DETECT_INIT 11
3319 #define ANEG_STATE_IDLE_DETECT 12
3320 #define ANEG_STATE_LINK_OK 13
3321 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT 14
3322 #define ANEG_STATE_NEXT_PAGE_WAIT 15
3325 #define MR_AN_ENABLE 0x00000001
3326 #define MR_RESTART_AN 0x00000002
3327 #define MR_AN_COMPLETE 0x00000004
3328 #define MR_PAGE_RX 0x00000008
3329 #define MR_NP_LOADED 0x00000010
3330 #define MR_TOGGLE_TX 0x00000020
3331 #define MR_LP_ADV_FULL_DUPLEX 0x00000040
3332 #define MR_LP_ADV_HALF_DUPLEX 0x00000080
3333 #define MR_LP_ADV_SYM_PAUSE 0x00000100
3334 #define MR_LP_ADV_ASYM_PAUSE 0x00000200
3335 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
3336 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
3337 #define MR_LP_ADV_NEXT_PAGE 0x00001000
3338 #define MR_TOGGLE_RX 0x00002000
3339 #define MR_NP_RX 0x00004000
3341 #define MR_LINK_OK 0x80000000
3343 unsigned long link_time, cur_time;
3345 u32 ability_match_cfg;
3346 int ability_match_count;
3348 char ability_match, idle_match, ack_match;
3350 u32 txconfig, rxconfig;
3351 #define ANEG_CFG_NP 0x00000080
3352 #define ANEG_CFG_ACK 0x00000040
3353 #define ANEG_CFG_RF2 0x00000020
3354 #define ANEG_CFG_RF1 0x00000010
3355 #define ANEG_CFG_PS2 0x00000001
3356 #define ANEG_CFG_PS1 0x00008000
3357 #define ANEG_CFG_HD 0x00004000
3358 #define ANEG_CFG_FD 0x00002000
3359 #define ANEG_CFG_INVAL 0x00001f06
3364 #define ANEG_TIMER_ENAB 2
3365 #define ANEG_FAILED -1
3367 #define ANEG_STATE_SETTLE_TIME 10000
3369 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
3370 struct tg3_fiber_aneginfo *ap)
3373 unsigned long delta;
3377 if (ap->state == ANEG_STATE_UNKNOWN) {
3381 ap->ability_match_cfg = 0;
3382 ap->ability_match_count = 0;
3383 ap->ability_match = 0;
3389 if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
3390 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
3392 if (rx_cfg_reg != ap->ability_match_cfg) {
3393 ap->ability_match_cfg = rx_cfg_reg;
3394 ap->ability_match = 0;
3395 ap->ability_match_count = 0;
3397 if (++ap->ability_match_count > 1) {
3398 ap->ability_match = 1;
3399 ap->ability_match_cfg = rx_cfg_reg;
3402 if (rx_cfg_reg & ANEG_CFG_ACK)
3410 ap->ability_match_cfg = 0;
3411 ap->ability_match_count = 0;
3412 ap->ability_match = 0;
3418 ap->rxconfig = rx_cfg_reg;
3422 case ANEG_STATE_UNKNOWN:
3423 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
3424 ap->state = ANEG_STATE_AN_ENABLE;
3427 case ANEG_STATE_AN_ENABLE:
3428 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
3429 if (ap->flags & MR_AN_ENABLE) {
3432 ap->ability_match_cfg = 0;
3433 ap->ability_match_count = 0;
3434 ap->ability_match = 0;
3438 ap->state = ANEG_STATE_RESTART_INIT;
3440 ap->state = ANEG_STATE_DISABLE_LINK_OK;
3444 case ANEG_STATE_RESTART_INIT:
3445 ap->link_time = ap->cur_time;
3446 ap->flags &= ~(MR_NP_LOADED);
3448 tw32(MAC_TX_AUTO_NEG, 0);
3449 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3450 tw32_f(MAC_MODE, tp->mac_mode);
3453 ret = ANEG_TIMER_ENAB;
3454 ap->state = ANEG_STATE_RESTART;
3457 case ANEG_STATE_RESTART:
3458 delta = ap->cur_time - ap->link_time;
3459 if (delta > ANEG_STATE_SETTLE_TIME) {
3460 ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
3462 ret = ANEG_TIMER_ENAB;
3466 case ANEG_STATE_DISABLE_LINK_OK:
3470 case ANEG_STATE_ABILITY_DETECT_INIT:
3471 ap->flags &= ~(MR_TOGGLE_TX);
3472 ap->txconfig = ANEG_CFG_FD;
3473 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3474 if (flowctrl & ADVERTISE_1000XPAUSE)
3475 ap->txconfig |= ANEG_CFG_PS1;
3476 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3477 ap->txconfig |= ANEG_CFG_PS2;
3478 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3479 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3480 tw32_f(MAC_MODE, tp->mac_mode);
3483 ap->state = ANEG_STATE_ABILITY_DETECT;
3486 case ANEG_STATE_ABILITY_DETECT:
3487 if (ap->ability_match != 0 && ap->rxconfig != 0) {
3488 ap->state = ANEG_STATE_ACK_DETECT_INIT;
3492 case ANEG_STATE_ACK_DETECT_INIT:
3493 ap->txconfig |= ANEG_CFG_ACK;
3494 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
3495 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
3496 tw32_f(MAC_MODE, tp->mac_mode);
3499 ap->state = ANEG_STATE_ACK_DETECT;
3502 case ANEG_STATE_ACK_DETECT:
3503 if (ap->ack_match != 0) {
3504 if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
3505 (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
3506 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
3508 ap->state = ANEG_STATE_AN_ENABLE;
3510 } else if (ap->ability_match != 0 &&
3511 ap->rxconfig == 0) {
3512 ap->state = ANEG_STATE_AN_ENABLE;
3516 case ANEG_STATE_COMPLETE_ACK_INIT:
3517 if (ap->rxconfig & ANEG_CFG_INVAL) {
3521 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
3522 MR_LP_ADV_HALF_DUPLEX |
3523 MR_LP_ADV_SYM_PAUSE |
3524 MR_LP_ADV_ASYM_PAUSE |
3525 MR_LP_ADV_REMOTE_FAULT1 |
3526 MR_LP_ADV_REMOTE_FAULT2 |
3527 MR_LP_ADV_NEXT_PAGE |
3530 if (ap->rxconfig & ANEG_CFG_FD)
3531 ap->flags |= MR_LP_ADV_FULL_DUPLEX;
3532 if (ap->rxconfig & ANEG_CFG_HD)
3533 ap->flags |= MR_LP_ADV_HALF_DUPLEX;
3534 if (ap->rxconfig & ANEG_CFG_PS1)
3535 ap->flags |= MR_LP_ADV_SYM_PAUSE;
3536 if (ap->rxconfig & ANEG_CFG_PS2)
3537 ap->flags |= MR_LP_ADV_ASYM_PAUSE;
3538 if (ap->rxconfig & ANEG_CFG_RF1)
3539 ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
3540 if (ap->rxconfig & ANEG_CFG_RF2)
3541 ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
3542 if (ap->rxconfig & ANEG_CFG_NP)
3543 ap->flags |= MR_LP_ADV_NEXT_PAGE;
3545 ap->link_time = ap->cur_time;
3547 ap->flags ^= (MR_TOGGLE_TX);
3548 if (ap->rxconfig & 0x0008)
3549 ap->flags |= MR_TOGGLE_RX;
3550 if (ap->rxconfig & ANEG_CFG_NP)
3551 ap->flags |= MR_NP_RX;
3552 ap->flags |= MR_PAGE_RX;
3554 ap->state = ANEG_STATE_COMPLETE_ACK;
3555 ret = ANEG_TIMER_ENAB;
3558 case ANEG_STATE_COMPLETE_ACK:
3559 if (ap->ability_match != 0 &&
3560 ap->rxconfig == 0) {
3561 ap->state = ANEG_STATE_AN_ENABLE;
3564 delta = ap->cur_time - ap->link_time;
3565 if (delta > ANEG_STATE_SETTLE_TIME) {
3566 if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
3567 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3569 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
3570 !(ap->flags & MR_NP_RX)) {
3571 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
3579 case ANEG_STATE_IDLE_DETECT_INIT:
3580 ap->link_time = ap->cur_time;
3581 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3582 tw32_f(MAC_MODE, tp->mac_mode);
3585 ap->state = ANEG_STATE_IDLE_DETECT;
3586 ret = ANEG_TIMER_ENAB;
3589 case ANEG_STATE_IDLE_DETECT:
3590 if (ap->ability_match != 0 &&
3591 ap->rxconfig == 0) {
3592 ap->state = ANEG_STATE_AN_ENABLE;
3595 delta = ap->cur_time - ap->link_time;
3596 if (delta > ANEG_STATE_SETTLE_TIME) {
3597 /* XXX another gem from the Broadcom driver :( */
3598 ap->state = ANEG_STATE_LINK_OK;
3602 case ANEG_STATE_LINK_OK:
3603 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
3607 case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
3608 /* ??? unimplemented */
3611 case ANEG_STATE_NEXT_PAGE_WAIT:
3612 /* ??? unimplemented */
3623 static int fiber_autoneg(struct tg3 *tp, u32 *txflags, u32 *rxflags)
3626 struct tg3_fiber_aneginfo aninfo;
3627 int status = ANEG_FAILED;
3631 tw32_f(MAC_TX_AUTO_NEG, 0);
3633 tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
3634 tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
3637 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
3640 memset(&aninfo, 0, sizeof(aninfo));
3641 aninfo.flags |= MR_AN_ENABLE;
3642 aninfo.state = ANEG_STATE_UNKNOWN;
3643 aninfo.cur_time = 0;
3645 while (++tick < 195000) {
3646 status = tg3_fiber_aneg_smachine(tp, &aninfo);
3647 if (status == ANEG_DONE || status == ANEG_FAILED)
3653 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
3654 tw32_f(MAC_MODE, tp->mac_mode);
3657 *txflags = aninfo.txconfig;
3658 *rxflags = aninfo.flags;
3660 if (status == ANEG_DONE &&
3661 (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
3662 MR_LP_ADV_FULL_DUPLEX)))
3668 static void tg3_init_bcm8002(struct tg3 *tp)
3670 u32 mac_status = tr32(MAC_STATUS);
3673 /* Reset when initting first time or we have a link. */
3674 if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
3675 !(mac_status & MAC_STATUS_PCS_SYNCED))
3678 /* Set PLL lock range. */
3679 tg3_writephy(tp, 0x16, 0x8007);
3682 tg3_writephy(tp, MII_BMCR, BMCR_RESET);
3684 /* Wait for reset to complete. */
3685 /* XXX schedule_timeout() ... */
3686 for (i = 0; i < 500; i++)
3689 /* Config mode; select PMA/Ch 1 regs. */
3690 tg3_writephy(tp, 0x10, 0x8411);
3692 /* Enable auto-lock and comdet, select txclk for tx. */
3693 tg3_writephy(tp, 0x11, 0x0a10);
3695 tg3_writephy(tp, 0x18, 0x00a0);
3696 tg3_writephy(tp, 0x16, 0x41ff);
3698 /* Assert and deassert POR. */
3699 tg3_writephy(tp, 0x13, 0x0400);
3701 tg3_writephy(tp, 0x13, 0x0000);
3703 tg3_writephy(tp, 0x11, 0x0a50);
3705 tg3_writephy(tp, 0x11, 0x0a10);
3707 /* Wait for signal to stabilize */
3708 /* XXX schedule_timeout() ... */
3709 for (i = 0; i < 15000; i++)
3712 /* Deselect the channel register so we can read the PHYID
3715 tg3_writephy(tp, 0x10, 0x8011);
3718 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
3721 u32 sg_dig_ctrl, sg_dig_status;
3722 u32 serdes_cfg, expected_sg_dig_ctrl;
3723 int workaround, port_a;
3724 int current_link_up;
3727 expected_sg_dig_ctrl = 0;
3730 current_link_up = 0;
3732 if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
3733 tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
3735 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
3738 /* preserve bits 0-11,13,14 for signal pre-emphasis */
3739 /* preserve bits 20-23 for voltage regulator */
3740 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
3743 sg_dig_ctrl = tr32(SG_DIG_CTRL);
3745 if (tp->link_config.autoneg != AUTONEG_ENABLE) {
3746 if (sg_dig_ctrl & SG_DIG_USING_HW_AUTONEG) {
3748 u32 val = serdes_cfg;
3754 tw32_f(MAC_SERDES_CFG, val);
3757 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3759 if (mac_status & MAC_STATUS_PCS_SYNCED) {
3760 tg3_setup_flow_control(tp, 0, 0);
3761 current_link_up = 1;
3766 /* Want auto-negotiation. */
3767 expected_sg_dig_ctrl = SG_DIG_USING_HW_AUTONEG | SG_DIG_COMMON_SETUP;
3769 flowctrl = tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
3770 if (flowctrl & ADVERTISE_1000XPAUSE)
3771 expected_sg_dig_ctrl |= SG_DIG_PAUSE_CAP;
3772 if (flowctrl & ADVERTISE_1000XPSE_ASYM)
3773 expected_sg_dig_ctrl |= SG_DIG_ASYM_PAUSE;
3775 if (sg_dig_ctrl != expected_sg_dig_ctrl) {
3776 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
3777 tp->serdes_counter &&
3778 ((mac_status & (MAC_STATUS_PCS_SYNCED |
3779 MAC_STATUS_RCVD_CFG)) ==
3780 MAC_STATUS_PCS_SYNCED)) {
3781 tp->serdes_counter--;
3782 current_link_up = 1;
3787 tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
3788 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | SG_DIG_SOFT_RESET);
3790 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
3792 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3793 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3794 } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
3795 MAC_STATUS_SIGNAL_DET)) {
3796 sg_dig_status = tr32(SG_DIG_STATUS);
3797 mac_status = tr32(MAC_STATUS);
3799 if ((sg_dig_status & SG_DIG_AUTONEG_COMPLETE) &&
3800 (mac_status & MAC_STATUS_PCS_SYNCED)) {
3801 u32 local_adv = 0, remote_adv = 0;
3803 if (sg_dig_ctrl & SG_DIG_PAUSE_CAP)
3804 local_adv |= ADVERTISE_1000XPAUSE;
3805 if (sg_dig_ctrl & SG_DIG_ASYM_PAUSE)
3806 local_adv |= ADVERTISE_1000XPSE_ASYM;
3808 if (sg_dig_status & SG_DIG_PARTNER_PAUSE_CAPABLE)
3809 remote_adv |= LPA_1000XPAUSE;
3810 if (sg_dig_status & SG_DIG_PARTNER_ASYM_PAUSE)
3811 remote_adv |= LPA_1000XPAUSE_ASYM;
3813 tg3_setup_flow_control(tp, local_adv, remote_adv);
3814 current_link_up = 1;
3815 tp->serdes_counter = 0;
3816 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3817 } else if (!(sg_dig_status & SG_DIG_AUTONEG_COMPLETE)) {
3818 if (tp->serdes_counter)
3819 tp->serdes_counter--;
3822 u32 val = serdes_cfg;
3829 tw32_f(MAC_SERDES_CFG, val);
3832 tw32_f(SG_DIG_CTRL, SG_DIG_COMMON_SETUP);
3835 /* Link parallel detection - link is up */
3836 /* only if we have PCS_SYNC and not */
3837 /* receiving config code words */
3838 mac_status = tr32(MAC_STATUS);
3839 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
3840 !(mac_status & MAC_STATUS_RCVD_CFG)) {
3841 tg3_setup_flow_control(tp, 0, 0);
3842 current_link_up = 1;
3844 TG3_FLG2_PARALLEL_DETECT;
3845 tp->serdes_counter =
3846 SERDES_PARALLEL_DET_TIMEOUT;
3848 goto restart_autoneg;
3852 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
3853 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
3857 return current_link_up;
3860 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
3862 int current_link_up = 0;
3864 if (!(mac_status & MAC_STATUS_PCS_SYNCED))
3867 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
3868 u32 txflags, rxflags;
3871 if (fiber_autoneg(tp, &txflags, &rxflags)) {
3872 u32 local_adv = 0, remote_adv = 0;
3874 if (txflags & ANEG_CFG_PS1)
3875 local_adv |= ADVERTISE_1000XPAUSE;
3876 if (txflags & ANEG_CFG_PS2)
3877 local_adv |= ADVERTISE_1000XPSE_ASYM;
3879 if (rxflags & MR_LP_ADV_SYM_PAUSE)
3880 remote_adv |= LPA_1000XPAUSE;
3881 if (rxflags & MR_LP_ADV_ASYM_PAUSE)
3882 remote_adv |= LPA_1000XPAUSE_ASYM;
3884 tg3_setup_flow_control(tp, local_adv, remote_adv);
3886 current_link_up = 1;
3888 for (i = 0; i < 30; i++) {
3891 (MAC_STATUS_SYNC_CHANGED |
3892 MAC_STATUS_CFG_CHANGED));
3894 if ((tr32(MAC_STATUS) &
3895 (MAC_STATUS_SYNC_CHANGED |
3896 MAC_STATUS_CFG_CHANGED)) == 0)
3900 mac_status = tr32(MAC_STATUS);
3901 if (current_link_up == 0 &&
3902 (mac_status & MAC_STATUS_PCS_SYNCED) &&
3903 !(mac_status & MAC_STATUS_RCVD_CFG))
3904 current_link_up = 1;
3906 tg3_setup_flow_control(tp, 0, 0);
3908 /* Forcing 1000FD link up. */
3909 current_link_up = 1;
3911 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
3914 tw32_f(MAC_MODE, tp->mac_mode);
3919 return current_link_up;
3922 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
3925 u16 orig_active_speed;
3926 u8 orig_active_duplex;
3928 int current_link_up;
3931 orig_pause_cfg = tp->link_config.active_flowctrl;
3932 orig_active_speed = tp->link_config.active_speed;
3933 orig_active_duplex = tp->link_config.active_duplex;
3935 if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
3936 netif_carrier_ok(tp->dev) &&
3937 (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
3938 mac_status = tr32(MAC_STATUS);
3939 mac_status &= (MAC_STATUS_PCS_SYNCED |
3940 MAC_STATUS_SIGNAL_DET |
3941 MAC_STATUS_CFG_CHANGED |
3942 MAC_STATUS_RCVD_CFG);
3943 if (mac_status == (MAC_STATUS_PCS_SYNCED |
3944 MAC_STATUS_SIGNAL_DET)) {
3945 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3946 MAC_STATUS_CFG_CHANGED));
3951 tw32_f(MAC_TX_AUTO_NEG, 0);
3953 tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
3954 tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
3955 tw32_f(MAC_MODE, tp->mac_mode);
3958 if (tp->phy_id == PHY_ID_BCM8002)
3959 tg3_init_bcm8002(tp);
3961 /* Enable link change event even when serdes polling. */
3962 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
3965 current_link_up = 0;
3966 mac_status = tr32(MAC_STATUS);
3968 if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
3969 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
3971 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
3973 tp->napi[0].hw_status->status =
3974 (SD_STATUS_UPDATED |
3975 (tp->napi[0].hw_status->status & ~SD_STATUS_LINK_CHG));
3977 for (i = 0; i < 100; i++) {
3978 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
3979 MAC_STATUS_CFG_CHANGED));
3981 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
3982 MAC_STATUS_CFG_CHANGED |
3983 MAC_STATUS_LNKSTATE_CHANGED)) == 0)
3987 mac_status = tr32(MAC_STATUS);
3988 if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
3989 current_link_up = 0;
3990 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
3991 tp->serdes_counter == 0) {
3992 tw32_f(MAC_MODE, (tp->mac_mode |
3993 MAC_MODE_SEND_CONFIGS));
3995 tw32_f(MAC_MODE, tp->mac_mode);
3999 if (current_link_up == 1) {
4000 tp->link_config.active_speed = SPEED_1000;
4001 tp->link_config.active_duplex = DUPLEX_FULL;
4002 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4003 LED_CTRL_LNKLED_OVERRIDE |
4004 LED_CTRL_1000MBPS_ON));
4006 tp->link_config.active_speed = SPEED_INVALID;
4007 tp->link_config.active_duplex = DUPLEX_INVALID;
4008 tw32(MAC_LED_CTRL, (tp->led_ctrl |
4009 LED_CTRL_LNKLED_OVERRIDE |
4010 LED_CTRL_TRAFFIC_OVERRIDE));
4013 if (current_link_up != netif_carrier_ok(tp->dev)) {
4014 if (current_link_up)
4015 netif_carrier_on(tp->dev);
4017 netif_carrier_off(tp->dev);
4018 tg3_link_report(tp);
4020 u32 now_pause_cfg = tp->link_config.active_flowctrl;
4021 if (orig_pause_cfg != now_pause_cfg ||
4022 orig_active_speed != tp->link_config.active_speed ||
4023 orig_active_duplex != tp->link_config.active_duplex)
4024 tg3_link_report(tp);
4030 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
4032 int current_link_up, err = 0;
4036 u32 local_adv, remote_adv;
4038 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
4039 tw32_f(MAC_MODE, tp->mac_mode);
4045 (MAC_STATUS_SYNC_CHANGED |
4046 MAC_STATUS_CFG_CHANGED |
4047 MAC_STATUS_MI_COMPLETION |
4048 MAC_STATUS_LNKSTATE_CHANGED));
4054 current_link_up = 0;
4055 current_speed = SPEED_INVALID;
4056 current_duplex = DUPLEX_INVALID;
4058 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4059 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
4061 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4062 bmsr |= BMSR_LSTATUS;
4064 bmsr &= ~BMSR_LSTATUS;
4067 err |= tg3_readphy(tp, MII_BMCR, &bmcr);
4069 if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
4070 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4071 /* do nothing, just check for link up at the end */
4072 } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
4075 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4076 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
4077 ADVERTISE_1000XPAUSE |
4078 ADVERTISE_1000XPSE_ASYM |
4081 new_adv |= tg3_advert_flowctrl_1000X(tp->link_config.flowctrl);
4083 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
4084 new_adv |= ADVERTISE_1000XHALF;
4085 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
4086 new_adv |= ADVERTISE_1000XFULL;
4088 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
4089 tg3_writephy(tp, MII_ADVERTISE, new_adv);
4090 bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
4091 tg3_writephy(tp, MII_BMCR, bmcr);
4093 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4094 tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
4095 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4102 bmcr &= ~BMCR_SPEED1000;
4103 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
4105 if (tp->link_config.duplex == DUPLEX_FULL)
4106 new_bmcr |= BMCR_FULLDPLX;
4108 if (new_bmcr != bmcr) {
4109 /* BMCR_SPEED1000 is a reserved bit that needs
4110 * to be set on write.
4112 new_bmcr |= BMCR_SPEED1000;
4114 /* Force a linkdown */
4115 if (netif_carrier_ok(tp->dev)) {
4118 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
4119 adv &= ~(ADVERTISE_1000XFULL |
4120 ADVERTISE_1000XHALF |
4122 tg3_writephy(tp, MII_ADVERTISE, adv);
4123 tg3_writephy(tp, MII_BMCR, bmcr |
4127 netif_carrier_off(tp->dev);
4129 tg3_writephy(tp, MII_BMCR, new_bmcr);
4131 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4132 err |= tg3_readphy(tp, MII_BMSR, &bmsr);
4133 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
4135 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
4136 bmsr |= BMSR_LSTATUS;
4138 bmsr &= ~BMSR_LSTATUS;
4140 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4144 if (bmsr & BMSR_LSTATUS) {
4145 current_speed = SPEED_1000;
4146 current_link_up = 1;
4147 if (bmcr & BMCR_FULLDPLX)
4148 current_duplex = DUPLEX_FULL;
4150 current_duplex = DUPLEX_HALF;
4155 if (bmcr & BMCR_ANENABLE) {
4158 err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
4159 err |= tg3_readphy(tp, MII_LPA, &remote_adv);
4160 common = local_adv & remote_adv;
4161 if (common & (ADVERTISE_1000XHALF |
4162 ADVERTISE_1000XFULL)) {
4163 if (common & ADVERTISE_1000XFULL)
4164 current_duplex = DUPLEX_FULL;
4166 current_duplex = DUPLEX_HALF;
4169 current_link_up = 0;
4173 if (current_link_up == 1 && current_duplex == DUPLEX_FULL)
4174 tg3_setup_flow_control(tp, local_adv, remote_adv);
4176 tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
4177 if (tp->link_config.active_duplex == DUPLEX_HALF)
4178 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
4180 tw32_f(MAC_MODE, tp->mac_mode);
4183 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
4185 tp->link_config.active_speed = current_speed;
4186 tp->link_config.active_duplex = current_duplex;
4188 if (current_link_up != netif_carrier_ok(tp->dev)) {
4189 if (current_link_up)
4190 netif_carrier_on(tp->dev);
4192 netif_carrier_off(tp->dev);
4193 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4195 tg3_link_report(tp);
4200 static void tg3_serdes_parallel_detect(struct tg3 *tp)
4202 if (tp->serdes_counter) {
4203 /* Give autoneg time to complete. */
4204 tp->serdes_counter--;
4207 if (!netif_carrier_ok(tp->dev) &&
4208 (tp->link_config.autoneg == AUTONEG_ENABLE)) {
4211 tg3_readphy(tp, MII_BMCR, &bmcr);
4212 if (bmcr & BMCR_ANENABLE) {
4215 /* Select shadow register 0x1f */
4216 tg3_writephy(tp, 0x1c, 0x7c00);
4217 tg3_readphy(tp, 0x1c, &phy1);
4219 /* Select expansion interrupt status register */
4220 tg3_writephy(tp, 0x17, 0x0f01);
4221 tg3_readphy(tp, 0x15, &phy2);
4222 tg3_readphy(tp, 0x15, &phy2);
4224 if ((phy1 & 0x10) && !(phy2 & 0x20)) {
4225 /* We have signal detect and not receiving
4226 * config code words, link is up by parallel
4230 bmcr &= ~BMCR_ANENABLE;
4231 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
4232 tg3_writephy(tp, MII_BMCR, bmcr);
4233 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
4237 else if (netif_carrier_ok(tp->dev) &&
4238 (tp->link_config.autoneg == AUTONEG_ENABLE) &&
4239 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
4242 /* Select expansion interrupt status register */
4243 tg3_writephy(tp, 0x17, 0x0f01);
4244 tg3_readphy(tp, 0x15, &phy2);
4248 /* Config code words received, turn on autoneg. */
4249 tg3_readphy(tp, MII_BMCR, &bmcr);
4250 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
4252 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
4258 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
4262 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4263 err = tg3_setup_fiber_phy(tp, force_reset);
4264 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4265 err = tg3_setup_fiber_mii_phy(tp, force_reset);
4267 err = tg3_setup_copper_phy(tp, force_reset);
4270 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
4273 val = tr32(TG3_CPMU_CLCK_STAT) & CPMU_CLCK_STAT_MAC_CLCK_MASK;
4274 if (val == CPMU_CLCK_STAT_MAC_CLCK_62_5)
4276 else if (val == CPMU_CLCK_STAT_MAC_CLCK_6_25)
4281 val = tr32(GRC_MISC_CFG) & ~GRC_MISC_CFG_PRESCALAR_MASK;
4282 val |= (scale << GRC_MISC_CFG_PRESCALAR_SHIFT);
4283 tw32(GRC_MISC_CFG, val);
4286 if (tp->link_config.active_speed == SPEED_1000 &&
4287 tp->link_config.active_duplex == DUPLEX_HALF)
4288 tw32(MAC_TX_LENGTHS,
4289 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4290 (6 << TX_LENGTHS_IPG_SHIFT) |
4291 (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
4293 tw32(MAC_TX_LENGTHS,
4294 ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
4295 (6 << TX_LENGTHS_IPG_SHIFT) |
4296 (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
4298 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
4299 if (netif_carrier_ok(tp->dev)) {
4300 tw32(HOSTCC_STAT_COAL_TICKS,
4301 tp->coal.stats_block_coalesce_usecs);
4303 tw32(HOSTCC_STAT_COAL_TICKS, 0);
4307 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND) {
4308 u32 val = tr32(PCIE_PWR_MGMT_THRESH);
4309 if (!netif_carrier_ok(tp->dev))
4310 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK) |
4313 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
4314 tw32(PCIE_PWR_MGMT_THRESH, val);
4320 /* This is called whenever we suspect that the system chipset is re-
4321 * ordering the sequence of MMIO to the tx send mailbox. The symptom
4322 * is bogus tx completions. We try to recover by setting the
4323 * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
4326 static void tg3_tx_recover(struct tg3 *tp)
4328 BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
4329 tp->write32_tx_mbox == tg3_write_indirect_mbox);
4331 printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
4332 "mapped I/O cycles to the network device, attempting to "
4333 "recover. Please report the problem to the driver maintainer "
4334 "and include system chipset information.\n", tp->dev->name);
4336 spin_lock(&tp->lock);
4337 tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
4338 spin_unlock(&tp->lock);
4341 static inline u32 tg3_tx_avail(struct tg3_napi *tnapi)
4344 return tnapi->tx_pending -
4345 ((tnapi->tx_prod - tnapi->tx_cons) & (TG3_TX_RING_SIZE - 1));
4348 /* Tigon3 never reports partial packet sends. So we do not
4349 * need special logic to handle SKBs that have not had all
4350 * of their frags sent yet, like SunGEM does.
4352 static void tg3_tx(struct tg3_napi *tnapi)
4354 struct tg3 *tp = tnapi->tp;
4355 u32 hw_idx = tnapi->hw_status->idx[0].tx_consumer;
4356 u32 sw_idx = tnapi->tx_cons;
4357 struct netdev_queue *txq;
4358 int index = tnapi - tp->napi;
4360 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
4363 txq = netdev_get_tx_queue(tp->dev, index);
4365 while (sw_idx != hw_idx) {
4366 struct ring_info *ri = &tnapi->tx_buffers[sw_idx];
4367 struct sk_buff *skb = ri->skb;
4370 if (unlikely(skb == NULL)) {
4375 pci_unmap_single(tp->pdev,
4376 pci_unmap_addr(ri, mapping),
4382 sw_idx = NEXT_TX(sw_idx);
4384 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
4385 ri = &tnapi->tx_buffers[sw_idx];
4386 if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
4389 pci_unmap_page(tp->pdev,
4390 pci_unmap_addr(ri, mapping),
4391 skb_shinfo(skb)->frags[i].size,
4393 sw_idx = NEXT_TX(sw_idx);
4398 if (unlikely(tx_bug)) {
4404 tnapi->tx_cons = sw_idx;
4406 /* Need to make the tx_cons update visible to tg3_start_xmit()
4407 * before checking for netif_queue_stopped(). Without the
4408 * memory barrier, there is a small possibility that tg3_start_xmit()
4409 * will miss it and cause the queue to be stopped forever.
4413 if (unlikely(netif_tx_queue_stopped(txq) &&
4414 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))) {
4415 __netif_tx_lock(txq, smp_processor_id());
4416 if (netif_tx_queue_stopped(txq) &&
4417 (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi)))
4418 netif_tx_wake_queue(txq);
4419 __netif_tx_unlock(txq);
4423 static void tg3_rx_skb_free(struct tg3 *tp, struct ring_info *ri, u32 map_sz)
4428 pci_unmap_single(tp->pdev, pci_unmap_addr(ri, mapping),
4429 map_sz, PCI_DMA_FROMDEVICE);
4430 dev_kfree_skb_any(ri->skb);
4434 /* Returns size of skb allocated or < 0 on error.
4436 * We only need to fill in the address because the other members
4437 * of the RX descriptor are invariant, see tg3_init_rings.
4439 * Note the purposeful assymetry of cpu vs. chip accesses. For
4440 * posting buffers we only dirty the first cache line of the RX
4441 * descriptor (containing the address). Whereas for the RX status
4442 * buffers the cpu only reads the last cacheline of the RX descriptor
4443 * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
4445 static int tg3_alloc_rx_skb(struct tg3 *tp, struct tg3_rx_prodring_set *tpr,
4446 u32 opaque_key, u32 dest_idx_unmasked)
4448 struct tg3_rx_buffer_desc *desc;
4449 struct ring_info *map, *src_map;
4450 struct sk_buff *skb;
4452 int skb_size, dest_idx;
4455 switch (opaque_key) {
4456 case RXD_OPAQUE_RING_STD:
4457 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4458 desc = &tpr->rx_std[dest_idx];
4459 map = &tpr->rx_std_buffers[dest_idx];
4460 skb_size = tp->rx_pkt_map_sz;
4463 case RXD_OPAQUE_RING_JUMBO:
4464 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4465 desc = &tpr->rx_jmb[dest_idx].std;
4466 map = &tpr->rx_jmb_buffers[dest_idx];
4467 skb_size = TG3_RX_JMB_MAP_SZ;
4474 /* Do not overwrite any of the map or rp information
4475 * until we are sure we can commit to a new buffer.
4477 * Callers depend upon this behavior and assume that
4478 * we leave everything unchanged if we fail.
4480 skb = netdev_alloc_skb(tp->dev, skb_size + tp->rx_offset);
4484 skb_reserve(skb, tp->rx_offset);
4486 mapping = pci_map_single(tp->pdev, skb->data, skb_size,
4487 PCI_DMA_FROMDEVICE);
4488 if (pci_dma_mapping_error(tp->pdev, mapping)) {
4494 pci_unmap_addr_set(map, mapping, mapping);
4496 desc->addr_hi = ((u64)mapping >> 32);
4497 desc->addr_lo = ((u64)mapping & 0xffffffff);
4502 /* We only need to move over in the address because the other
4503 * members of the RX descriptor are invariant. See notes above
4504 * tg3_alloc_rx_skb for full details.
4506 static void tg3_recycle_rx(struct tg3_napi *tnapi,
4507 struct tg3_rx_prodring_set *dpr,
4508 u32 opaque_key, int src_idx,
4509 u32 dest_idx_unmasked)
4511 struct tg3 *tp = tnapi->tp;
4512 struct tg3_rx_buffer_desc *src_desc, *dest_desc;
4513 struct ring_info *src_map, *dest_map;
4515 struct tg3_rx_prodring_set *spr = &tp->prodring[0];
4517 switch (opaque_key) {
4518 case RXD_OPAQUE_RING_STD:
4519 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
4520 dest_desc = &dpr->rx_std[dest_idx];
4521 dest_map = &dpr->rx_std_buffers[dest_idx];
4522 src_desc = &spr->rx_std[src_idx];
4523 src_map = &spr->rx_std_buffers[src_idx];
4526 case RXD_OPAQUE_RING_JUMBO:
4527 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
4528 dest_desc = &dpr->rx_jmb[dest_idx].std;
4529 dest_map = &dpr->rx_jmb_buffers[dest_idx];
4530 src_desc = &spr->rx_jmb[src_idx].std;
4531 src_map = &spr->rx_jmb_buffers[src_idx];
4538 dest_map->skb = src_map->skb;
4539 pci_unmap_addr_set(dest_map, mapping,
4540 pci_unmap_addr(src_map, mapping));
4541 dest_desc->addr_hi = src_desc->addr_hi;
4542 dest_desc->addr_lo = src_desc->addr_lo;
4543 src_map->skb = NULL;
4546 /* The RX ring scheme is composed of multiple rings which post fresh
4547 * buffers to the chip, and one special ring the chip uses to report
4548 * status back to the host.
4550 * The special ring reports the status of received packets to the
4551 * host. The chip does not write into the original descriptor the
4552 * RX buffer was obtained from. The chip simply takes the original
4553 * descriptor as provided by the host, updates the status and length
4554 * field, then writes this into the next status ring entry.
4556 * Each ring the host uses to post buffers to the chip is described
4557 * by a TG3_BDINFO entry in the chips SRAM area. When a packet arrives,
4558 * it is first placed into the on-chip ram. When the packet's length
4559 * is known, it walks down the TG3_BDINFO entries to select the ring.
4560 * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
4561 * which is within the range of the new packet's length is chosen.
4563 * The "separate ring for rx status" scheme may sound queer, but it makes
4564 * sense from a cache coherency perspective. If only the host writes
4565 * to the buffer post rings, and only the chip writes to the rx status
4566 * rings, then cache lines never move beyond shared-modified state.
4567 * If both the host and chip were to write into the same ring, cache line
4568 * eviction could occur since both entities want it in an exclusive state.
4570 static int tg3_rx(struct tg3_napi *tnapi, int budget)
4572 struct tg3 *tp = tnapi->tp;
4573 u32 work_mask, rx_std_posted = 0;
4574 u32 std_prod_idx, jmb_prod_idx;
4575 u32 sw_idx = tnapi->rx_rcb_ptr;
4578 struct tg3_rx_prodring_set *tpr = tnapi->prodring;
4580 hw_idx = *(tnapi->rx_rcb_prod_idx);
4582 * We need to order the read of hw_idx and the read of
4583 * the opaque cookie.
4588 std_prod_idx = tpr->rx_std_prod_idx;
4589 jmb_prod_idx = tpr->rx_jmb_prod_idx;
4590 while (sw_idx != hw_idx && budget > 0) {
4591 struct ring_info *ri;
4592 struct tg3_rx_buffer_desc *desc = &tnapi->rx_rcb[sw_idx];
4594 struct sk_buff *skb;
4595 dma_addr_t dma_addr;
4596 u32 opaque_key, desc_idx, *post_ptr;
4598 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
4599 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
4600 if (opaque_key == RXD_OPAQUE_RING_STD) {
4601 ri = &tp->prodring[0].rx_std_buffers[desc_idx];
4602 dma_addr = pci_unmap_addr(ri, mapping);
4604 post_ptr = &std_prod_idx;
4606 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
4607 ri = &tp->prodring[0].rx_jmb_buffers[desc_idx];
4608 dma_addr = pci_unmap_addr(ri, mapping);
4610 post_ptr = &jmb_prod_idx;
4612 goto next_pkt_nopost;
4614 work_mask |= opaque_key;
4616 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
4617 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
4619 tg3_recycle_rx(tnapi, tpr, opaque_key,
4620 desc_idx, *post_ptr);
4622 /* Other statistics kept track of by card. */
4623 tp->net_stats.rx_dropped++;
4627 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) -
4630 if (len > RX_COPY_THRESHOLD &&
4631 tp->rx_offset == NET_IP_ALIGN) {
4632 /* rx_offset will likely not equal NET_IP_ALIGN
4633 * if this is a 5701 card running in PCI-X mode
4634 * [see tg3_get_invariants()]
4638 skb_size = tg3_alloc_rx_skb(tp, tpr, opaque_key,
4645 pci_unmap_single(tp->pdev, dma_addr, skb_size,
4646 PCI_DMA_FROMDEVICE);
4650 struct sk_buff *copy_skb;
4652 tg3_recycle_rx(tnapi, tpr, opaque_key,
4653 desc_idx, *post_ptr);
4655 copy_skb = netdev_alloc_skb(tp->dev,
4656 len + TG3_RAW_IP_ALIGN);
4657 if (copy_skb == NULL)
4658 goto drop_it_no_recycle;
4660 skb_reserve(copy_skb, TG3_RAW_IP_ALIGN);
4661 skb_put(copy_skb, len);
4662 pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4663 skb_copy_from_linear_data(skb, copy_skb->data, len);
4664 pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
4666 /* We'll reuse the original ring buffer. */
4670 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
4671 (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
4672 (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
4673 >> RXD_TCPCSUM_SHIFT) == 0xffff))
4674 skb->ip_summed = CHECKSUM_UNNECESSARY;
4676 skb->ip_summed = CHECKSUM_NONE;
4678 skb->protocol = eth_type_trans(skb, tp->dev);
4680 if (len > (tp->dev->mtu + ETH_HLEN) &&
4681 skb->protocol != htons(ETH_P_8021Q)) {
4686 #if TG3_VLAN_TAG_USED
4687 if (tp->vlgrp != NULL &&
4688 desc->type_flags & RXD_FLAG_VLAN) {
4689 vlan_gro_receive(&tnapi->napi, tp->vlgrp,
4690 desc->err_vlan & RXD_VLAN_MASK, skb);
4693 napi_gro_receive(&tnapi->napi, skb);
4701 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
4702 u32 idx = *post_ptr % TG3_RX_RING_SIZE;
4703 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, idx);
4704 work_mask &= ~RXD_OPAQUE_RING_STD;
4709 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
4711 /* Refresh hw_idx to see if there is new work */
4712 if (sw_idx == hw_idx) {
4713 hw_idx = *(tnapi->rx_rcb_prod_idx);
4718 /* ACK the status ring. */
4719 tnapi->rx_rcb_ptr = sw_idx;
4720 tw32_rx_mbox(tnapi->consmbox, sw_idx);
4722 /* Refill RX ring(s). */
4723 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) || tnapi == &tp->napi[1]) {
4724 if (work_mask & RXD_OPAQUE_RING_STD) {
4725 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4726 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG,
4727 tpr->rx_std_prod_idx);
4729 if (work_mask & RXD_OPAQUE_RING_JUMBO) {
4730 tpr->rx_jmb_prod_idx = jmb_prod_idx %
4731 TG3_RX_JUMBO_RING_SIZE;
4732 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG,
4733 tpr->rx_jmb_prod_idx);
4736 } else if (work_mask) {
4737 /* rx_std_buffers[] and rx_jmb_buffers[] entries must be
4738 * updated before the producer indices can be updated.
4742 tpr->rx_std_prod_idx = std_prod_idx % TG3_RX_RING_SIZE;
4743 tpr->rx_jmb_prod_idx = jmb_prod_idx % TG3_RX_JUMBO_RING_SIZE;
4745 napi_schedule(&tp->napi[1].napi);
4751 static void tg3_poll_link(struct tg3 *tp)
4753 /* handle link change and other phy events */
4754 if (!(tp->tg3_flags &
4755 (TG3_FLAG_USE_LINKCHG_REG |
4756 TG3_FLAG_POLL_SERDES))) {
4757 struct tg3_hw_status *sblk = tp->napi[0].hw_status;
4759 if (sblk->status & SD_STATUS_LINK_CHG) {
4760 sblk->status = SD_STATUS_UPDATED |
4761 (sblk->status & ~SD_STATUS_LINK_CHG);
4762 spin_lock(&tp->lock);
4763 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
4765 (MAC_STATUS_SYNC_CHANGED |
4766 MAC_STATUS_CFG_CHANGED |
4767 MAC_STATUS_MI_COMPLETION |
4768 MAC_STATUS_LNKSTATE_CHANGED));
4771 tg3_setup_phy(tp, 0);
4772 spin_unlock(&tp->lock);
4777 static void tg3_rx_prodring_xfer(struct tg3 *tp,
4778 struct tg3_rx_prodring_set *dpr,
4779 struct tg3_rx_prodring_set *spr)
4781 u32 si, di, cpycnt, src_prod_idx;
4785 src_prod_idx = spr->rx_std_prod_idx;
4787 /* Make sure updates to the rx_std_buffers[] entries and the
4788 * standard producer index are seen in the correct order.
4792 if (spr->rx_std_cons_idx == src_prod_idx)
4795 if (spr->rx_std_cons_idx < src_prod_idx)
4796 cpycnt = src_prod_idx - spr->rx_std_cons_idx;
4798 cpycnt = TG3_RX_RING_SIZE - spr->rx_std_cons_idx;
4800 cpycnt = min(cpycnt, TG3_RX_RING_SIZE - dpr->rx_std_prod_idx);
4802 si = spr->rx_std_cons_idx;
4803 di = dpr->rx_std_prod_idx;
4805 memcpy(&dpr->rx_std_buffers[di],
4806 &spr->rx_std_buffers[si],
4807 cpycnt * sizeof(struct ring_info));
4809 for (i = 0; i < cpycnt; i++, di++, si++) {
4810 struct tg3_rx_buffer_desc *sbd, *dbd;
4811 sbd = &spr->rx_std[si];
4812 dbd = &dpr->rx_std[di];
4813 dbd->addr_hi = sbd->addr_hi;
4814 dbd->addr_lo = sbd->addr_lo;
4817 spr->rx_std_cons_idx = (spr->rx_std_cons_idx + cpycnt) %
4819 dpr->rx_std_prod_idx = (dpr->rx_std_prod_idx + cpycnt) %
4824 src_prod_idx = spr->rx_jmb_prod_idx;
4826 /* Make sure updates to the rx_jmb_buffers[] entries and
4827 * the jumbo producer index are seen in the correct order.
4831 if (spr->rx_jmb_cons_idx == src_prod_idx)
4834 if (spr->rx_jmb_cons_idx < src_prod_idx)
4835 cpycnt = src_prod_idx - spr->rx_jmb_cons_idx;
4837 cpycnt = TG3_RX_JUMBO_RING_SIZE - spr->rx_jmb_cons_idx;
4839 cpycnt = min(cpycnt,
4840 TG3_RX_JUMBO_RING_SIZE - dpr->rx_jmb_prod_idx);
4842 si = spr->rx_jmb_cons_idx;
4843 di = dpr->rx_jmb_prod_idx;
4845 memcpy(&dpr->rx_jmb_buffers[di],
4846 &spr->rx_jmb_buffers[si],
4847 cpycnt * sizeof(struct ring_info));
4849 for (i = 0; i < cpycnt; i++, di++, si++) {
4850 struct tg3_rx_buffer_desc *sbd, *dbd;
4851 sbd = &spr->rx_jmb[si].std;
4852 dbd = &dpr->rx_jmb[di].std;
4853 dbd->addr_hi = sbd->addr_hi;
4854 dbd->addr_lo = sbd->addr_lo;
4857 spr->rx_jmb_cons_idx = (spr->rx_jmb_cons_idx + cpycnt) %
4858 TG3_RX_JUMBO_RING_SIZE;
4859 dpr->rx_jmb_prod_idx = (dpr->rx_jmb_prod_idx + cpycnt) %
4860 TG3_RX_JUMBO_RING_SIZE;
4864 static int tg3_poll_work(struct tg3_napi *tnapi, int work_done, int budget)
4866 struct tg3 *tp = tnapi->tp;
4868 /* run TX completion thread */
4869 if (tnapi->hw_status->idx[0].tx_consumer != tnapi->tx_cons) {
4871 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4875 /* run RX thread, within the bounds set by NAPI.
4876 * All RX "locking" is done by ensuring outside
4877 * code synchronizes with tg3->napi.poll()
4879 if (*(tnapi->rx_rcb_prod_idx) != tnapi->rx_rcb_ptr)
4880 work_done += tg3_rx(tnapi, budget - work_done);
4882 if ((tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) && tnapi == &tp->napi[1]) {
4884 u32 std_prod_idx = tp->prodring[0].rx_std_prod_idx;
4885 u32 jmb_prod_idx = tp->prodring[0].rx_jmb_prod_idx;
4887 for (i = 2; i < tp->irq_cnt; i++)
4888 tg3_rx_prodring_xfer(tp, tnapi->prodring,
4889 tp->napi[i].prodring);
4893 if (std_prod_idx != tp->prodring[0].rx_std_prod_idx) {
4894 u32 mbox = TG3_RX_STD_PROD_IDX_REG;
4895 tw32_rx_mbox(mbox, tp->prodring[0].rx_std_prod_idx);
4898 if (jmb_prod_idx != tp->prodring[0].rx_jmb_prod_idx) {
4899 u32 mbox = TG3_RX_JMB_PROD_IDX_REG;
4900 tw32_rx_mbox(mbox, tp->prodring[0].rx_jmb_prod_idx);
4909 static int tg3_poll_msix(struct napi_struct *napi, int budget)
4911 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4912 struct tg3 *tp = tnapi->tp;
4914 struct tg3_hw_status *sblk = tnapi->hw_status;
4917 work_done = tg3_poll_work(tnapi, work_done, budget);
4919 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4922 if (unlikely(work_done >= budget))
4925 /* tp->last_tag is used in tg3_restart_ints() below
4926 * to tell the hw how much work has been processed,
4927 * so we must read it before checking for more work.
4929 tnapi->last_tag = sblk->status_tag;
4930 tnapi->last_irq_tag = tnapi->last_tag;
4933 /* check for RX/TX work to do */
4934 if (sblk->idx[0].tx_consumer == tnapi->tx_cons &&
4935 *(tnapi->rx_rcb_prod_idx) == tnapi->rx_rcb_ptr) {
4936 napi_complete(napi);
4937 /* Reenable interrupts. */
4938 tw32_mailbox(tnapi->int_mbox, tnapi->last_tag << 24);
4947 /* work_done is guaranteed to be less than budget. */
4948 napi_complete(napi);
4949 schedule_work(&tp->reset_task);
4953 static int tg3_poll(struct napi_struct *napi, int budget)
4955 struct tg3_napi *tnapi = container_of(napi, struct tg3_napi, napi);
4956 struct tg3 *tp = tnapi->tp;
4958 struct tg3_hw_status *sblk = tnapi->hw_status;
4963 work_done = tg3_poll_work(tnapi, work_done, budget);
4965 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING))
4968 if (unlikely(work_done >= budget))
4971 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
4972 /* tp->last_tag is used in tg3_int_reenable() below
4973 * to tell the hw how much work has been processed,
4974 * so we must read it before checking for more work.
4976 tnapi->last_tag = sblk->status_tag;
4977 tnapi->last_irq_tag = tnapi->last_tag;
4980 sblk->status &= ~SD_STATUS_UPDATED;
4982 if (likely(!tg3_has_work(tnapi))) {
4983 napi_complete(napi);
4984 tg3_int_reenable(tnapi);
4992 /* work_done is guaranteed to be less than budget. */
4993 napi_complete(napi);
4994 schedule_work(&tp->reset_task);
4998 static void tg3_irq_quiesce(struct tg3 *tp)
5002 BUG_ON(tp->irq_sync);
5007 for (i = 0; i < tp->irq_cnt; i++)
5008 synchronize_irq(tp->napi[i].irq_vec);
5011 static inline int tg3_irq_sync(struct tg3 *tp)
5013 return tp->irq_sync;
5016 /* Fully shutdown all tg3 driver activity elsewhere in the system.
5017 * If irq_sync is non-zero, then the IRQ handler must be synchronized
5018 * with as well. Most of the time, this is not necessary except when
5019 * shutting down the device.
5021 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
5023 spin_lock_bh(&tp->lock);
5025 tg3_irq_quiesce(tp);
5028 static inline void tg3_full_unlock(struct tg3 *tp)
5030 spin_unlock_bh(&tp->lock);
5033 /* One-shot MSI handler - Chip automatically disables interrupt
5034 * after sending MSI so driver doesn't have to do it.
5036 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
5038 struct tg3_napi *tnapi = dev_id;
5039 struct tg3 *tp = tnapi->tp;
5041 prefetch(tnapi->hw_status);
5043 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5045 if (likely(!tg3_irq_sync(tp)))
5046 napi_schedule(&tnapi->napi);
5051 /* MSI ISR - No need to check for interrupt sharing and no need to
5052 * flush status block and interrupt mailbox. PCI ordering rules
5053 * guarantee that MSI will arrive after the status block.
5055 static irqreturn_t tg3_msi(int irq, void *dev_id)
5057 struct tg3_napi *tnapi = dev_id;
5058 struct tg3 *tp = tnapi->tp;
5060 prefetch(tnapi->hw_status);
5062 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5064 * Writing any value to intr-mbox-0 clears PCI INTA# and
5065 * chip-internal interrupt pending events.
5066 * Writing non-zero to intr-mbox-0 additional tells the
5067 * NIC to stop sending us irqs, engaging "in-intr-handler"
5070 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5071 if (likely(!tg3_irq_sync(tp)))
5072 napi_schedule(&tnapi->napi);
5074 return IRQ_RETVAL(1);
5077 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
5079 struct tg3_napi *tnapi = dev_id;
5080 struct tg3 *tp = tnapi->tp;
5081 struct tg3_hw_status *sblk = tnapi->hw_status;
5082 unsigned int handled = 1;
5084 /* In INTx mode, it is possible for the interrupt to arrive at
5085 * the CPU before the status block posted prior to the interrupt.
5086 * Reading the PCI State register will confirm whether the
5087 * interrupt is ours and will flush the status block.
5089 if (unlikely(!(sblk->status & SD_STATUS_UPDATED))) {
5090 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5091 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5098 * Writing any value to intr-mbox-0 clears PCI INTA# and
5099 * chip-internal interrupt pending events.
5100 * Writing non-zero to intr-mbox-0 additional tells the
5101 * NIC to stop sending us irqs, engaging "in-intr-handler"
5104 * Flush the mailbox to de-assert the IRQ immediately to prevent
5105 * spurious interrupts. The flush impacts performance but
5106 * excessive spurious interrupts can be worse in some cases.
5108 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5109 if (tg3_irq_sync(tp))
5111 sblk->status &= ~SD_STATUS_UPDATED;
5112 if (likely(tg3_has_work(tnapi))) {
5113 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5114 napi_schedule(&tnapi->napi);
5116 /* No work, shared interrupt perhaps? re-enable
5117 * interrupts, and flush that PCI write
5119 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
5123 return IRQ_RETVAL(handled);
5126 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
5128 struct tg3_napi *tnapi = dev_id;
5129 struct tg3 *tp = tnapi->tp;
5130 struct tg3_hw_status *sblk = tnapi->hw_status;
5131 unsigned int handled = 1;
5133 /* In INTx mode, it is possible for the interrupt to arrive at
5134 * the CPU before the status block posted prior to the interrupt.
5135 * Reading the PCI State register will confirm whether the
5136 * interrupt is ours and will flush the status block.
5138 if (unlikely(sblk->status_tag == tnapi->last_irq_tag)) {
5139 if ((tp->tg3_flags & TG3_FLAG_CHIP_RESETTING) ||
5140 (tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5147 * writing any value to intr-mbox-0 clears PCI INTA# and
5148 * chip-internal interrupt pending events.
5149 * writing non-zero to intr-mbox-0 additional tells the
5150 * NIC to stop sending us irqs, engaging "in-intr-handler"
5153 * Flush the mailbox to de-assert the IRQ immediately to prevent
5154 * spurious interrupts. The flush impacts performance but
5155 * excessive spurious interrupts can be worse in some cases.
5157 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
5160 * In a shared interrupt configuration, sometimes other devices'
5161 * interrupts will scream. We record the current status tag here
5162 * so that the above check can report that the screaming interrupts
5163 * are unhandled. Eventually they will be silenced.
5165 tnapi->last_irq_tag = sblk->status_tag;
5167 if (tg3_irq_sync(tp))
5170 prefetch(&tnapi->rx_rcb[tnapi->rx_rcb_ptr]);
5172 napi_schedule(&tnapi->napi);
5175 return IRQ_RETVAL(handled);
5178 /* ISR for interrupt test */
5179 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
5181 struct tg3_napi *tnapi = dev_id;
5182 struct tg3 *tp = tnapi->tp;
5183 struct tg3_hw_status *sblk = tnapi->hw_status;
5185 if ((sblk->status & SD_STATUS_UPDATED) ||
5186 !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
5187 tg3_disable_ints(tp);
5188 return IRQ_RETVAL(1);
5190 return IRQ_RETVAL(0);
5193 static int tg3_init_hw(struct tg3 *, int);
5194 static int tg3_halt(struct tg3 *, int, int);
5196 /* Restart hardware after configuration changes, self-test, etc.
5197 * Invoked with tp->lock held.
5199 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
5200 __releases(tp->lock)
5201 __acquires(tp->lock)
5205 err = tg3_init_hw(tp, reset_phy);
5207 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
5208 "aborting.\n", tp->dev->name);
5209 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5210 tg3_full_unlock(tp);
5211 del_timer_sync(&tp->timer);
5213 tg3_napi_enable(tp);
5215 tg3_full_lock(tp, 0);
5220 #ifdef CONFIG_NET_POLL_CONTROLLER
5221 static void tg3_poll_controller(struct net_device *dev)
5224 struct tg3 *tp = netdev_priv(dev);
5226 for (i = 0; i < tp->irq_cnt; i++)
5227 tg3_interrupt(tp->napi[i].irq_vec, dev);
5231 static void tg3_reset_task(struct work_struct *work)
5233 struct tg3 *tp = container_of(work, struct tg3, reset_task);
5235 unsigned int restart_timer;
5237 tg3_full_lock(tp, 0);
5239 if (!netif_running(tp->dev)) {
5240 tg3_full_unlock(tp);
5244 tg3_full_unlock(tp);
5250 tg3_full_lock(tp, 1);
5252 restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
5253 tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
5255 if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
5256 tp->write32_tx_mbox = tg3_write32_tx_mbox;
5257 tp->write32_rx_mbox = tg3_write_flush_reg32;
5258 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
5259 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
5262 tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
5263 err = tg3_init_hw(tp, 1);
5267 tg3_netif_start(tp);
5270 mod_timer(&tp->timer, jiffies + 1);
5273 tg3_full_unlock(tp);
5279 static void tg3_dump_short_state(struct tg3 *tp)
5281 printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
5282 tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
5283 printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
5284 tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
5287 static void tg3_tx_timeout(struct net_device *dev)
5289 struct tg3 *tp = netdev_priv(dev);
5291 if (netif_msg_tx_err(tp)) {
5292 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
5294 tg3_dump_short_state(tp);
5297 schedule_work(&tp->reset_task);
5300 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
5301 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
5303 u32 base = (u32) mapping & 0xffffffff;
5305 return ((base > 0xffffdcc0) &&
5306 (base + len + 8 < base));
5309 /* Test for DMA addresses > 40-bit */
5310 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
5313 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
5314 if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
5315 return (((u64) mapping + len) > DMA_BIT_MASK(40));
5322 static void tg3_set_txd(struct tg3_napi *, int, dma_addr_t, int, u32, u32);
5324 /* Workaround 4GB and 40-bit hardware DMA bugs. */
5325 static int tigon3_dma_hwbug_workaround(struct tg3_napi *tnapi,
5326 struct sk_buff *skb, u32 last_plus_one,
5327 u32 *start, u32 base_flags, u32 mss)
5329 struct tg3 *tp = tnapi->tp;
5330 struct sk_buff *new_skb;
5331 dma_addr_t new_addr = 0;
5335 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
5336 new_skb = skb_copy(skb, GFP_ATOMIC);
5338 int more_headroom = 4 - ((unsigned long)skb->data & 3);
5340 new_skb = skb_copy_expand(skb,
5341 skb_headroom(skb) + more_headroom,
5342 skb_tailroom(skb), GFP_ATOMIC);
5348 /* New SKB is guaranteed to be linear. */
5350 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
5352 /* Make sure the mapping succeeded */
5353 if (pci_dma_mapping_error(tp->pdev, new_addr)) {
5355 dev_kfree_skb(new_skb);
5358 /* Make sure new skb does not cross any 4G boundaries.
5359 * Drop the packet if it does.
5361 } else if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5362 tg3_4g_overflow_test(new_addr, new_skb->len)) {
5363 pci_unmap_single(tp->pdev, new_addr, new_skb->len,
5366 dev_kfree_skb(new_skb);
5369 tg3_set_txd(tnapi, entry, new_addr, new_skb->len,
5370 base_flags, 1 | (mss << 1));
5371 *start = NEXT_TX(entry);
5375 /* Now clean up the sw ring entries. */
5377 while (entry != last_plus_one) {
5381 len = skb_headlen(skb);
5383 len = skb_shinfo(skb)->frags[i-1].size;
5385 pci_unmap_single(tp->pdev,
5386 pci_unmap_addr(&tnapi->tx_buffers[entry],
5388 len, PCI_DMA_TODEVICE);
5390 tnapi->tx_buffers[entry].skb = new_skb;
5391 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5394 tnapi->tx_buffers[entry].skb = NULL;
5396 entry = NEXT_TX(entry);
5405 static void tg3_set_txd(struct tg3_napi *tnapi, int entry,
5406 dma_addr_t mapping, int len, u32 flags,
5409 struct tg3_tx_buffer_desc *txd = &tnapi->tx_ring[entry];
5410 int is_end = (mss_and_is_end & 0x1);
5411 u32 mss = (mss_and_is_end >> 1);
5415 flags |= TXD_FLAG_END;
5416 if (flags & TXD_FLAG_VLAN) {
5417 vlan_tag = flags >> 16;
5420 vlan_tag |= (mss << TXD_MSS_SHIFT);
5422 txd->addr_hi = ((u64) mapping >> 32);
5423 txd->addr_lo = ((u64) mapping & 0xffffffff);
5424 txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
5425 txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
5428 /* hard_start_xmit for devices that don't have any bugs and
5429 * support TG3_FLG2_HW_TSO_2 and TG3_FLG2_HW_TSO_3 only.
5431 static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
5432 struct net_device *dev)
5434 struct tg3 *tp = netdev_priv(dev);
5435 u32 len, entry, base_flags, mss;
5437 struct tg3_napi *tnapi;
5438 struct netdev_queue *txq;
5439 unsigned int i, last;
5442 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5443 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5444 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5447 /* We are running in BH disabled context with netif_tx_lock
5448 * and TX reclaim runs via tp->napi.poll inside of a software
5449 * interrupt. Furthermore, IRQ processing runs lockless so we have
5450 * no IRQ context deadlocks to worry about either. Rejoice!
5452 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5453 if (!netif_tx_queue_stopped(txq)) {
5454 netif_tx_stop_queue(txq);
5456 /* This is a hard error, log it. */
5457 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5458 "queue awake!\n", dev->name);
5460 return NETDEV_TX_BUSY;
5463 entry = tnapi->tx_prod;
5466 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5467 int tcp_opt_len, ip_tcp_len;
5470 if (skb_header_cloned(skb) &&
5471 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5476 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
5477 hdrlen = skb_headlen(skb) - ETH_HLEN;
5479 struct iphdr *iph = ip_hdr(skb);
5481 tcp_opt_len = tcp_optlen(skb);
5482 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5485 iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
5486 hdrlen = ip_tcp_len + tcp_opt_len;
5489 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5490 mss |= (hdrlen & 0xc) << 12;
5492 base_flags |= 0x00000010;
5493 base_flags |= (hdrlen & 0x3e0) << 5;
5497 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5498 TXD_FLAG_CPU_POST_DMA);
5500 tcp_hdr(skb)->check = 0;
5503 else if (skb->ip_summed == CHECKSUM_PARTIAL)
5504 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5505 #if TG3_VLAN_TAG_USED
5506 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5507 base_flags |= (TXD_FLAG_VLAN |
5508 (vlan_tx_tag_get(skb) << 16));
5511 len = skb_headlen(skb);
5513 /* Queue skb data, a.k.a. the main skb fragment. */
5514 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5515 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5520 tnapi->tx_buffers[entry].skb = skb;
5521 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5523 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5524 !mss && skb->len > ETH_DATA_LEN)
5525 base_flags |= TXD_FLAG_JMB_PKT;
5527 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5528 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5530 entry = NEXT_TX(entry);
5532 /* Now loop through additional data fragments, and queue them. */
5533 if (skb_shinfo(skb)->nr_frags > 0) {
5534 last = skb_shinfo(skb)->nr_frags - 1;
5535 for (i = 0; i <= last; i++) {
5536 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5539 mapping = pci_map_page(tp->pdev,
5542 len, PCI_DMA_TODEVICE);
5543 if (pci_dma_mapping_error(tp->pdev, mapping))
5546 tnapi->tx_buffers[entry].skb = NULL;
5547 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5550 tg3_set_txd(tnapi, entry, mapping, len,
5551 base_flags, (i == last) | (mss << 1));
5553 entry = NEXT_TX(entry);
5557 /* Packets are ready, update Tx producer idx local and on card. */
5558 tw32_tx_mbox(tnapi->prodmbox, entry);
5560 tnapi->tx_prod = entry;
5561 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5562 netif_tx_stop_queue(txq);
5563 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5564 netif_tx_wake_queue(txq);
5570 return NETDEV_TX_OK;
5574 entry = tnapi->tx_prod;
5575 tnapi->tx_buffers[entry].skb = NULL;
5576 pci_unmap_single(tp->pdev,
5577 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5580 for (i = 0; i <= last; i++) {
5581 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5582 entry = NEXT_TX(entry);
5584 pci_unmap_page(tp->pdev,
5585 pci_unmap_addr(&tnapi->tx_buffers[entry],
5587 frag->size, PCI_DMA_TODEVICE);
5591 return NETDEV_TX_OK;
5594 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *,
5595 struct net_device *);
5597 /* Use GSO to workaround a rare TSO bug that may be triggered when the
5598 * TSO header is greater than 80 bytes.
5600 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
5602 struct sk_buff *segs, *nskb;
5603 u32 frag_cnt_est = skb_shinfo(skb)->gso_segs * 3;
5605 /* Estimate the number of fragments in the worst case */
5606 if (unlikely(tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)) {
5607 netif_stop_queue(tp->dev);
5608 if (tg3_tx_avail(&tp->napi[0]) <= frag_cnt_est)
5609 return NETDEV_TX_BUSY;
5611 netif_wake_queue(tp->dev);
5614 segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
5616 goto tg3_tso_bug_end;
5622 tg3_start_xmit_dma_bug(nskb, tp->dev);
5628 return NETDEV_TX_OK;
5631 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
5632 * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
5634 static netdev_tx_t tg3_start_xmit_dma_bug(struct sk_buff *skb,
5635 struct net_device *dev)
5637 struct tg3 *tp = netdev_priv(dev);
5638 u32 len, entry, base_flags, mss;
5639 int would_hit_hwbug;
5641 struct tg3_napi *tnapi;
5642 struct netdev_queue *txq;
5643 unsigned int i, last;
5646 txq = netdev_get_tx_queue(dev, skb_get_queue_mapping(skb));
5647 tnapi = &tp->napi[skb_get_queue_mapping(skb)];
5648 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
5651 /* We are running in BH disabled context with netif_tx_lock
5652 * and TX reclaim runs via tp->napi.poll inside of a software
5653 * interrupt. Furthermore, IRQ processing runs lockless so we have
5654 * no IRQ context deadlocks to worry about either. Rejoice!
5656 if (unlikely(tg3_tx_avail(tnapi) <= (skb_shinfo(skb)->nr_frags + 1))) {
5657 if (!netif_tx_queue_stopped(txq)) {
5658 netif_tx_stop_queue(txq);
5660 /* This is a hard error, log it. */
5661 printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
5662 "queue awake!\n", dev->name);
5664 return NETDEV_TX_BUSY;
5667 entry = tnapi->tx_prod;
5669 if (skb->ip_summed == CHECKSUM_PARTIAL)
5670 base_flags |= TXD_FLAG_TCPUDP_CSUM;
5672 if ((mss = skb_shinfo(skb)->gso_size) != 0) {
5674 u32 tcp_opt_len, ip_tcp_len, hdr_len;
5676 if (skb_header_cloned(skb) &&
5677 pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
5682 tcp_opt_len = tcp_optlen(skb);
5683 ip_tcp_len = ip_hdrlen(skb) + sizeof(struct tcphdr);
5685 hdr_len = ip_tcp_len + tcp_opt_len;
5686 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
5687 (tp->tg3_flags2 & TG3_FLG2_TSO_BUG))
5688 return (tg3_tso_bug(tp, skb));
5690 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
5691 TXD_FLAG_CPU_POST_DMA);
5695 iph->tot_len = htons(mss + hdr_len);
5696 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
5697 tcp_hdr(skb)->check = 0;
5698 base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
5700 tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
5705 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) {
5706 mss |= (hdr_len & 0xc) << 12;
5708 base_flags |= 0x00000010;
5709 base_flags |= (hdr_len & 0x3e0) << 5;
5710 } else if (tp->tg3_flags2 & TG3_FLG2_HW_TSO_2)
5711 mss |= hdr_len << 9;
5712 else if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1) ||
5713 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5714 if (tcp_opt_len || iph->ihl > 5) {
5717 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5718 mss |= (tsflags << 11);
5721 if (tcp_opt_len || iph->ihl > 5) {
5724 tsflags = (iph->ihl - 5) + (tcp_opt_len >> 2);
5725 base_flags |= tsflags << 12;
5729 #if TG3_VLAN_TAG_USED
5730 if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
5731 base_flags |= (TXD_FLAG_VLAN |
5732 (vlan_tx_tag_get(skb) << 16));
5735 if ((tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG) &&
5736 !mss && skb->len > ETH_DATA_LEN)
5737 base_flags |= TXD_FLAG_JMB_PKT;
5739 len = skb_headlen(skb);
5741 mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
5742 if (pci_dma_mapping_error(tp->pdev, mapping)) {
5747 tnapi->tx_buffers[entry].skb = skb;
5748 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping, mapping);
5750 would_hit_hwbug = 0;
5752 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) && len <= 8)
5753 would_hit_hwbug = 1;
5755 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5756 tg3_4g_overflow_test(mapping, len))
5757 would_hit_hwbug = 1;
5759 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5760 tg3_40bit_overflow_test(tp, mapping, len))
5761 would_hit_hwbug = 1;
5763 if (tp->tg3_flags3 & TG3_FLG3_5701_DMA_BUG)
5764 would_hit_hwbug = 1;
5766 tg3_set_txd(tnapi, entry, mapping, len, base_flags,
5767 (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
5769 entry = NEXT_TX(entry);
5771 /* Now loop through additional data fragments, and queue them. */
5772 if (skb_shinfo(skb)->nr_frags > 0) {
5773 last = skb_shinfo(skb)->nr_frags - 1;
5774 for (i = 0; i <= last; i++) {
5775 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5778 mapping = pci_map_page(tp->pdev,
5781 len, PCI_DMA_TODEVICE);
5783 tnapi->tx_buffers[entry].skb = NULL;
5784 pci_unmap_addr_set(&tnapi->tx_buffers[entry], mapping,
5786 if (pci_dma_mapping_error(tp->pdev, mapping))
5789 if ((tp->tg3_flags3 & TG3_FLG3_SHORT_DMA_BUG) &&
5791 would_hit_hwbug = 1;
5793 if ((tp->tg3_flags3 & TG3_FLG3_4G_DMA_BNDRY_BUG) &&
5794 tg3_4g_overflow_test(mapping, len))
5795 would_hit_hwbug = 1;
5797 if ((tp->tg3_flags3 & TG3_FLG3_40BIT_DMA_LIMIT_BUG) &&
5798 tg3_40bit_overflow_test(tp, mapping, len))
5799 would_hit_hwbug = 1;
5801 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5802 tg3_set_txd(tnapi, entry, mapping, len,
5803 base_flags, (i == last)|(mss << 1));
5805 tg3_set_txd(tnapi, entry, mapping, len,
5806 base_flags, (i == last));
5808 entry = NEXT_TX(entry);
5812 if (would_hit_hwbug) {
5813 u32 last_plus_one = entry;
5816 start = entry - 1 - skb_shinfo(skb)->nr_frags;
5817 start &= (TG3_TX_RING_SIZE - 1);
5819 /* If the workaround fails due to memory/mapping
5820 * failure, silently drop this packet.
5822 if (tigon3_dma_hwbug_workaround(tnapi, skb, last_plus_one,
5823 &start, base_flags, mss))
5829 /* Packets are ready, update Tx producer idx local and on card. */
5830 tw32_tx_mbox(tnapi->prodmbox, entry);
5832 tnapi->tx_prod = entry;
5833 if (unlikely(tg3_tx_avail(tnapi) <= (MAX_SKB_FRAGS + 1))) {
5834 netif_tx_stop_queue(txq);
5835 if (tg3_tx_avail(tnapi) > TG3_TX_WAKEUP_THRESH(tnapi))
5836 netif_tx_wake_queue(txq);
5842 return NETDEV_TX_OK;
5846 entry = tnapi->tx_prod;
5847 tnapi->tx_buffers[entry].skb = NULL;
5848 pci_unmap_single(tp->pdev,
5849 pci_unmap_addr(&tnapi->tx_buffers[entry], mapping),
5852 for (i = 0; i <= last; i++) {
5853 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
5854 entry = NEXT_TX(entry);
5856 pci_unmap_page(tp->pdev,
5857 pci_unmap_addr(&tnapi->tx_buffers[entry],
5859 frag->size, PCI_DMA_TODEVICE);
5863 return NETDEV_TX_OK;
5866 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
5871 if (new_mtu > ETH_DATA_LEN) {
5872 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
5873 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
5874 ethtool_op_set_tso(dev, 0);
5877 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
5879 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
5880 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
5881 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
5885 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
5887 struct tg3 *tp = netdev_priv(dev);
5890 if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
5893 if (!netif_running(dev)) {
5894 /* We'll just catch it later when the
5897 tg3_set_mtu(dev, tp, new_mtu);
5905 tg3_full_lock(tp, 1);
5907 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5909 tg3_set_mtu(dev, tp, new_mtu);
5911 err = tg3_restart_hw(tp, 0);
5914 tg3_netif_start(tp);
5916 tg3_full_unlock(tp);
5924 static void tg3_rx_prodring_free(struct tg3 *tp,
5925 struct tg3_rx_prodring_set *tpr)
5929 if (tpr != &tp->prodring[0]) {
5930 for (i = tpr->rx_std_cons_idx; i != tpr->rx_std_prod_idx;
5931 i = (i + 1) % TG3_RX_RING_SIZE)
5932 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5935 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5936 for (i = tpr->rx_jmb_cons_idx;
5937 i != tpr->rx_jmb_prod_idx;
5938 i = (i + 1) % TG3_RX_JUMBO_RING_SIZE) {
5939 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5947 for (i = 0; i < TG3_RX_RING_SIZE; i++)
5948 tg3_rx_skb_free(tp, &tpr->rx_std_buffers[i],
5951 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
5952 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++)
5953 tg3_rx_skb_free(tp, &tpr->rx_jmb_buffers[i],
5958 /* Initialize tx/rx rings for packet processing.
5960 * The chip has been shut down and the driver detached from
5961 * the networking, so no interrupts or new tx packets will
5962 * end up in the driver. tp->{tx,}lock are held and thus
5965 static int tg3_rx_prodring_alloc(struct tg3 *tp,
5966 struct tg3_rx_prodring_set *tpr)
5968 u32 i, rx_pkt_dma_sz;
5970 tpr->rx_std_cons_idx = 0;
5971 tpr->rx_std_prod_idx = 0;
5972 tpr->rx_jmb_cons_idx = 0;
5973 tpr->rx_jmb_prod_idx = 0;
5975 if (tpr != &tp->prodring[0]) {
5976 memset(&tpr->rx_std_buffers[0], 0, TG3_RX_STD_BUFF_RING_SIZE);
5977 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE)
5978 memset(&tpr->rx_jmb_buffers[0], 0,
5979 TG3_RX_JMB_BUFF_RING_SIZE);
5983 /* Zero out all descriptors. */
5984 memset(tpr->rx_std, 0, TG3_RX_RING_BYTES);
5986 rx_pkt_dma_sz = TG3_RX_STD_DMA_SZ;
5987 if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
5988 tp->dev->mtu > ETH_DATA_LEN)
5989 rx_pkt_dma_sz = TG3_RX_JMB_DMA_SZ;
5990 tp->rx_pkt_map_sz = TG3_RX_DMA_TO_MAP_SZ(rx_pkt_dma_sz);
5992 /* Initialize invariants of the rings, we only set this
5993 * stuff once. This works because the card does not
5994 * write into the rx buffer posting rings.
5996 for (i = 0; i < TG3_RX_RING_SIZE; i++) {
5997 struct tg3_rx_buffer_desc *rxd;
5999 rxd = &tpr->rx_std[i];
6000 rxd->idx_len = rx_pkt_dma_sz << RXD_LEN_SHIFT;
6001 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
6002 rxd->opaque = (RXD_OPAQUE_RING_STD |
6003 (i << RXD_OPAQUE_INDEX_SHIFT));
6006 /* Now allocate fresh SKBs for each rx ring. */
6007 for (i = 0; i < tp->rx_pending; i++) {
6008 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_STD, i) < 0) {
6009 printk(KERN_WARNING PFX
6010 "%s: Using a smaller RX standard ring, "
6011 "only %d out of %d buffers were allocated "
6013 tp->dev->name, i, tp->rx_pending);
6021 if (!(tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE))
6024 memset(tpr->rx_jmb, 0, TG3_RX_JUMBO_RING_BYTES);
6026 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6027 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
6028 struct tg3_rx_buffer_desc *rxd;
6030 rxd = &tpr->rx_jmb[i].std;
6031 rxd->idx_len = TG3_RX_JMB_DMA_SZ << RXD_LEN_SHIFT;
6032 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
6034 rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
6035 (i << RXD_OPAQUE_INDEX_SHIFT));
6038 for (i = 0; i < tp->rx_jumbo_pending; i++) {
6039 if (tg3_alloc_rx_skb(tp, tpr, RXD_OPAQUE_RING_JUMBO,
6041 printk(KERN_WARNING PFX
6042 "%s: Using a smaller RX jumbo ring, "
6043 "only %d out of %d buffers were "
6044 "allocated successfully.\n",
6045 tp->dev->name, i, tp->rx_jumbo_pending);
6048 tp->rx_jumbo_pending = i;
6058 tg3_rx_prodring_free(tp, tpr);
6062 static void tg3_rx_prodring_fini(struct tg3 *tp,
6063 struct tg3_rx_prodring_set *tpr)
6065 kfree(tpr->rx_std_buffers);
6066 tpr->rx_std_buffers = NULL;
6067 kfree(tpr->rx_jmb_buffers);
6068 tpr->rx_jmb_buffers = NULL;
6070 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
6071 tpr->rx_std, tpr->rx_std_mapping);
6075 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
6076 tpr->rx_jmb, tpr->rx_jmb_mapping);
6081 static int tg3_rx_prodring_init(struct tg3 *tp,
6082 struct tg3_rx_prodring_set *tpr)
6084 tpr->rx_std_buffers = kzalloc(TG3_RX_STD_BUFF_RING_SIZE, GFP_KERNEL);
6085 if (!tpr->rx_std_buffers)
6088 tpr->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
6089 &tpr->rx_std_mapping);
6093 if (tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) {
6094 tpr->rx_jmb_buffers = kzalloc(TG3_RX_JMB_BUFF_RING_SIZE,
6096 if (!tpr->rx_jmb_buffers)
6099 tpr->rx_jmb = pci_alloc_consistent(tp->pdev,
6100 TG3_RX_JUMBO_RING_BYTES,
6101 &tpr->rx_jmb_mapping);
6109 tg3_rx_prodring_fini(tp, tpr);
6113 /* Free up pending packets in all rx/tx rings.
6115 * The chip has been shut down and the driver detached from
6116 * the networking, so no interrupts or new tx packets will
6117 * end up in the driver. tp->{tx,}lock is not held and we are not
6118 * in an interrupt context and thus may sleep.
6120 static void tg3_free_rings(struct tg3 *tp)
6124 for (j = 0; j < tp->irq_cnt; j++) {
6125 struct tg3_napi *tnapi = &tp->napi[j];
6127 if (!tnapi->tx_buffers)
6130 for (i = 0; i < TG3_TX_RING_SIZE; ) {
6131 struct ring_info *txp;
6132 struct sk_buff *skb;
6135 txp = &tnapi->tx_buffers[i];
6143 pci_unmap_single(tp->pdev,
6144 pci_unmap_addr(txp, mapping),
6151 for (k = 0; k < skb_shinfo(skb)->nr_frags; k++) {
6152 txp = &tnapi->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
6153 pci_unmap_page(tp->pdev,
6154 pci_unmap_addr(txp, mapping),
6155 skb_shinfo(skb)->frags[k].size,
6160 dev_kfree_skb_any(skb);
6163 if (tp->irq_cnt == 1 || j != tp->irq_cnt - 1)
6164 tg3_rx_prodring_free(tp, &tp->prodring[j]);
6168 /* Initialize tx/rx rings for packet processing.
6170 * The chip has been shut down and the driver detached from
6171 * the networking, so no interrupts or new tx packets will
6172 * end up in the driver. tp->{tx,}lock are held and thus
6175 static int tg3_init_rings(struct tg3 *tp)
6179 /* Free up all the SKBs. */
6182 for (i = 0; i < tp->irq_cnt; i++) {
6183 struct tg3_napi *tnapi = &tp->napi[i];
6185 tnapi->last_tag = 0;
6186 tnapi->last_irq_tag = 0;
6187 tnapi->hw_status->status = 0;
6188 tnapi->hw_status->status_tag = 0;
6189 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6194 memset(tnapi->tx_ring, 0, TG3_TX_RING_BYTES);
6196 tnapi->rx_rcb_ptr = 0;
6198 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6200 if ((tp->irq_cnt == 1 || i != tp->irq_cnt - 1) &&
6201 tg3_rx_prodring_alloc(tp, &tp->prodring[i]))
6209 * Must not be invoked with interrupt sources disabled and
6210 * the hardware shutdown down.
6212 static void tg3_free_consistent(struct tg3 *tp)
6216 for (i = 0; i < tp->irq_cnt; i++) {
6217 struct tg3_napi *tnapi = &tp->napi[i];
6219 if (tnapi->tx_ring) {
6220 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
6221 tnapi->tx_ring, tnapi->tx_desc_mapping);
6222 tnapi->tx_ring = NULL;
6225 kfree(tnapi->tx_buffers);
6226 tnapi->tx_buffers = NULL;
6228 if (tnapi->rx_rcb) {
6229 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
6231 tnapi->rx_rcb_mapping);
6232 tnapi->rx_rcb = NULL;
6235 if (tnapi->hw_status) {
6236 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
6238 tnapi->status_mapping);
6239 tnapi->hw_status = NULL;
6244 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
6245 tp->hw_stats, tp->stats_mapping);
6246 tp->hw_stats = NULL;
6249 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++)
6250 tg3_rx_prodring_fini(tp, &tp->prodring[i]);
6254 * Must not be invoked with interrupt sources disabled and
6255 * the hardware shutdown down. Can sleep.
6257 static int tg3_alloc_consistent(struct tg3 *tp)
6261 for (i = 0; i < (tp->irq_cnt == 1 ? 1 : tp->irq_cnt - 1); i++) {
6262 if (tg3_rx_prodring_init(tp, &tp->prodring[i]))
6266 tp->hw_stats = pci_alloc_consistent(tp->pdev,
6267 sizeof(struct tg3_hw_stats),
6268 &tp->stats_mapping);
6272 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6274 for (i = 0; i < tp->irq_cnt; i++) {
6275 struct tg3_napi *tnapi = &tp->napi[i];
6276 struct tg3_hw_status *sblk;
6278 tnapi->hw_status = pci_alloc_consistent(tp->pdev,
6280 &tnapi->status_mapping);
6281 if (!tnapi->hw_status)
6284 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6285 sblk = tnapi->hw_status;
6287 /* If multivector TSS is enabled, vector 0 does not handle
6288 * tx interrupts. Don't allocate any resources for it.
6290 if ((!i && !(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) ||
6291 (i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))) {
6292 tnapi->tx_buffers = kzalloc(sizeof(struct ring_info) *
6295 if (!tnapi->tx_buffers)
6298 tnapi->tx_ring = pci_alloc_consistent(tp->pdev,
6300 &tnapi->tx_desc_mapping);
6301 if (!tnapi->tx_ring)
6306 * When RSS is enabled, the status block format changes
6307 * slightly. The "rx_jumbo_consumer", "reserved",
6308 * and "rx_mini_consumer" members get mapped to the
6309 * other three rx return ring producer indexes.
6313 tnapi->rx_rcb_prod_idx = &sblk->idx[0].rx_producer;
6316 tnapi->rx_rcb_prod_idx = &sblk->rx_jumbo_consumer;
6319 tnapi->rx_rcb_prod_idx = &sblk->reserved;
6322 tnapi->rx_rcb_prod_idx = &sblk->rx_mini_consumer;
6326 if (tp->irq_cnt == 1)
6327 tnapi->prodring = &tp->prodring[0];
6329 tnapi->prodring = &tp->prodring[i - 1];
6332 * If multivector RSS is enabled, vector 0 does not handle
6333 * rx or tx interrupts. Don't allocate any resources for it.
6335 if (!i && (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS))
6338 tnapi->rx_rcb = pci_alloc_consistent(tp->pdev,
6339 TG3_RX_RCB_RING_BYTES(tp),
6340 &tnapi->rx_rcb_mapping);
6344 memset(tnapi->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
6350 tg3_free_consistent(tp);
6354 #define MAX_WAIT_CNT 1000
6356 /* To stop a block, clear the enable bit and poll till it
6357 * clears. tp->lock is held.
6359 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
6364 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6371 /* We can't enable/disable these bits of the
6372 * 5705/5750, just say success.
6385 for (i = 0; i < MAX_WAIT_CNT; i++) {
6388 if ((val & enable_bit) == 0)
6392 if (i == MAX_WAIT_CNT && !silent) {
6393 printk(KERN_ERR PFX "tg3_stop_block timed out, "
6394 "ofs=%lx enable_bit=%x\n",
6402 /* tp->lock is held. */
6403 static int tg3_abort_hw(struct tg3 *tp, int silent)
6407 tg3_disable_ints(tp);
6409 tp->rx_mode &= ~RX_MODE_ENABLE;
6410 tw32_f(MAC_RX_MODE, tp->rx_mode);
6413 err = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
6414 err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
6415 err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
6416 err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
6417 err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
6418 err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
6420 err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
6421 err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
6422 err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
6423 err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
6424 err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
6425 err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
6426 err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
6428 tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
6429 tw32_f(MAC_MODE, tp->mac_mode);
6432 tp->tx_mode &= ~TX_MODE_ENABLE;
6433 tw32_f(MAC_TX_MODE, tp->tx_mode);
6435 for (i = 0; i < MAX_WAIT_CNT; i++) {
6437 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
6440 if (i >= MAX_WAIT_CNT) {
6441 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
6442 "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
6443 tp->dev->name, tr32(MAC_TX_MODE));
6447 err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
6448 err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
6449 err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
6451 tw32(FTQ_RESET, 0xffffffff);
6452 tw32(FTQ_RESET, 0x00000000);
6454 err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
6455 err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
6457 for (i = 0; i < tp->irq_cnt; i++) {
6458 struct tg3_napi *tnapi = &tp->napi[i];
6459 if (tnapi->hw_status)
6460 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
6463 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
6468 static void tg3_ape_send_event(struct tg3 *tp, u32 event)
6473 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
6474 if (apedata != APE_SEG_SIG_MAGIC)
6477 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
6478 if (!(apedata & APE_FW_STATUS_READY))
6481 /* Wait for up to 1 millisecond for APE to service previous event. */
6482 for (i = 0; i < 10; i++) {
6483 if (tg3_ape_lock(tp, TG3_APE_LOCK_MEM))
6486 apedata = tg3_ape_read32(tp, TG3_APE_EVENT_STATUS);
6488 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6489 tg3_ape_write32(tp, TG3_APE_EVENT_STATUS,
6490 event | APE_EVENT_STATUS_EVENT_PENDING);
6492 tg3_ape_unlock(tp, TG3_APE_LOCK_MEM);
6494 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6500 if (!(apedata & APE_EVENT_STATUS_EVENT_PENDING))
6501 tg3_ape_write32(tp, TG3_APE_EVENT, APE_EVENT_1);
6504 static void tg3_ape_driver_state_change(struct tg3 *tp, int kind)
6509 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
6513 case RESET_KIND_INIT:
6514 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG,
6515 APE_HOST_SEG_SIG_MAGIC);
6516 tg3_ape_write32(tp, TG3_APE_HOST_SEG_LEN,
6517 APE_HOST_SEG_LEN_MAGIC);
6518 apedata = tg3_ape_read32(tp, TG3_APE_HOST_INIT_COUNT);
6519 tg3_ape_write32(tp, TG3_APE_HOST_INIT_COUNT, ++apedata);
6520 tg3_ape_write32(tp, TG3_APE_HOST_DRIVER_ID,
6521 APE_HOST_DRIVER_ID_MAGIC);
6522 tg3_ape_write32(tp, TG3_APE_HOST_BEHAVIOR,
6523 APE_HOST_BEHAV_NO_PHYLOCK);
6525 event = APE_EVENT_STATUS_STATE_START;
6527 case RESET_KIND_SHUTDOWN:
6528 /* With the interface we are currently using,
6529 * APE does not track driver state. Wiping
6530 * out the HOST SEGMENT SIGNATURE forces
6531 * the APE to assume OS absent status.
6533 tg3_ape_write32(tp, TG3_APE_HOST_SEG_SIG, 0x0);
6535 event = APE_EVENT_STATUS_STATE_UNLOAD;
6537 case RESET_KIND_SUSPEND:
6538 event = APE_EVENT_STATUS_STATE_SUSPEND;
6544 event |= APE_EVENT_STATUS_DRIVER_EVNT | APE_EVENT_STATUS_STATE_CHNGE;
6546 tg3_ape_send_event(tp, event);
6549 /* tp->lock is held. */
6550 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
6552 tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
6553 NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
6555 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6557 case RESET_KIND_INIT:
6558 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6562 case RESET_KIND_SHUTDOWN:
6563 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6567 case RESET_KIND_SUSPEND:
6568 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6577 if (kind == RESET_KIND_INIT ||
6578 kind == RESET_KIND_SUSPEND)
6579 tg3_ape_driver_state_change(tp, kind);
6582 /* tp->lock is held. */
6583 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
6585 if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
6587 case RESET_KIND_INIT:
6588 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6589 DRV_STATE_START_DONE);
6592 case RESET_KIND_SHUTDOWN:
6593 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6594 DRV_STATE_UNLOAD_DONE);
6602 if (kind == RESET_KIND_SHUTDOWN)
6603 tg3_ape_driver_state_change(tp, kind);
6606 /* tp->lock is held. */
6607 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
6609 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6611 case RESET_KIND_INIT:
6612 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6616 case RESET_KIND_SHUTDOWN:
6617 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6621 case RESET_KIND_SUSPEND:
6622 tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
6632 static int tg3_poll_fw(struct tg3 *tp)
6637 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6638 /* Wait up to 20ms for init done. */
6639 for (i = 0; i < 200; i++) {
6640 if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
6647 /* Wait for firmware initialization to complete. */
6648 for (i = 0; i < 100000; i++) {
6649 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
6650 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
6655 /* Chip might not be fitted with firmware. Some Sun onboard
6656 * parts are configured like that. So don't signal the timeout
6657 * of the above loop as an error, but do report the lack of
6658 * running firmware once.
6661 !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
6662 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
6664 printk(KERN_INFO PFX "%s: No firmware running.\n",
6671 /* Save PCI command register before chip reset */
6672 static void tg3_save_pci_state(struct tg3 *tp)
6674 pci_read_config_word(tp->pdev, PCI_COMMAND, &tp->pci_cmd);
6677 /* Restore PCI state after chip reset */
6678 static void tg3_restore_pci_state(struct tg3 *tp)
6682 /* Re-enable indirect register accesses. */
6683 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
6684 tp->misc_host_ctrl);
6686 /* Set MAX PCI retry to zero. */
6687 val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
6688 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6689 (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
6690 val |= PCISTATE_RETRY_SAME_DMA;
6691 /* Allow reads and writes to the APE register and memory space. */
6692 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
6693 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
6694 PCISTATE_ALLOW_APE_SHMEM_WR;
6695 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
6697 pci_write_config_word(tp->pdev, PCI_COMMAND, tp->pci_cmd);
6699 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785) {
6700 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6701 pcie_set_readrq(tp->pdev, 4096);
6703 pci_write_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
6704 tp->pci_cacheline_sz);
6705 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
6710 /* Make sure PCI-X relaxed ordering bit is clear. */
6711 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
6714 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6716 pcix_cmd &= ~PCI_X_CMD_ERO;
6717 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
6721 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
6723 /* Chip reset on 5780 will reset MSI enable bit,
6724 * so need to restore it.
6726 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6729 pci_read_config_word(tp->pdev,
6730 tp->msi_cap + PCI_MSI_FLAGS,
6732 pci_write_config_word(tp->pdev,
6733 tp->msi_cap + PCI_MSI_FLAGS,
6734 ctrl | PCI_MSI_FLAGS_ENABLE);
6735 val = tr32(MSGINT_MODE);
6736 tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
6741 static void tg3_stop_fw(struct tg3 *);
6743 /* tp->lock is held. */
6744 static int tg3_chip_reset(struct tg3 *tp)
6747 void (*write_op)(struct tg3 *, u32, u32);
6752 tg3_ape_lock(tp, TG3_APE_LOCK_GRC);
6754 /* No matching tg3_nvram_unlock() after this because
6755 * chip reset below will undo the nvram lock.
6757 tp->nvram_lock_cnt = 0;
6759 /* GRC_MISC_CFG core clock reset will clear the memory
6760 * enable bit in PCI register 4 and the MSI enable bit
6761 * on some chips, so we save relevant registers here.
6763 tg3_save_pci_state(tp);
6765 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
6766 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
6767 tw32(GRC_FASTBOOT_PC, 0);
6770 * We must avoid the readl() that normally takes place.
6771 * It locks machines, causes machine checks, and other
6772 * fun things. So, temporarily disable the 5701
6773 * hardware workaround, while we do the reset.
6775 write_op = tp->write32;
6776 if (write_op == tg3_write_flush_reg32)
6777 tp->write32 = tg3_write32;
6779 /* Prevent the irq handler from reading or writing PCI registers
6780 * during chip reset when the memory enable bit in the PCI command
6781 * register may be cleared. The chip does not generate interrupt
6782 * at this time, but the irq handler may still be called due to irq
6783 * sharing or irqpoll.
6785 tp->tg3_flags |= TG3_FLAG_CHIP_RESETTING;
6786 for (i = 0; i < tp->irq_cnt; i++) {
6787 struct tg3_napi *tnapi = &tp->napi[i];
6788 if (tnapi->hw_status) {
6789 tnapi->hw_status->status = 0;
6790 tnapi->hw_status->status_tag = 0;
6792 tnapi->last_tag = 0;
6793 tnapi->last_irq_tag = 0;
6797 for (i = 0; i < tp->irq_cnt; i++)
6798 synchronize_irq(tp->napi[i].irq_vec);
6800 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6801 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
6802 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
6806 val = GRC_MISC_CFG_CORECLK_RESET;
6808 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
6809 if (tr32(0x7e2c) == 0x60) {
6812 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
6813 tw32(GRC_MISC_CFG, (1 << 29));
6818 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6819 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
6820 tw32(GRC_VCPU_EXT_CTRL,
6821 tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
6824 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6825 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
6826 tw32(GRC_MISC_CFG, val);
6828 /* restore 5701 hardware bug workaround write method */
6829 tp->write32 = write_op;
6831 /* Unfortunately, we have to delay before the PCI read back.
6832 * Some 575X chips even will not respond to a PCI cfg access
6833 * when the reset command is given to the chip.
6835 * How do these hardware designers expect things to work
6836 * properly if the PCI write is posted for a long period
6837 * of time? It is always necessary to have some method by
6838 * which a register read back can occur to push the write
6839 * out which does the reset.
6841 * For most tg3 variants the trick below was working.
6846 /* Flush PCI posted writes. The normal MMIO registers
6847 * are inaccessible at this time so this is the only
6848 * way to make this reliably (actually, this is no longer
6849 * the case, see above). I tried to use indirect
6850 * register read/write but this upset some 5701 variants.
6852 pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
6856 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) && tp->pcie_cap) {
6859 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
6863 /* Wait for link training to complete. */
6864 for (i = 0; i < 5000; i++)
6867 pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
6868 pci_write_config_dword(tp->pdev, 0xc4,
6869 cfg_val | (1 << 15));
6872 /* Clear the "no snoop" and "relaxed ordering" bits. */
6873 pci_read_config_word(tp->pdev,
6874 tp->pcie_cap + PCI_EXP_DEVCTL,
6876 val16 &= ~(PCI_EXP_DEVCTL_RELAX_EN |
6877 PCI_EXP_DEVCTL_NOSNOOP_EN);
6879 * Older PCIe devices only support the 128 byte
6880 * MPS setting. Enforce the restriction.
6882 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
6883 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784))
6884 val16 &= ~PCI_EXP_DEVCTL_PAYLOAD;
6885 pci_write_config_word(tp->pdev,
6886 tp->pcie_cap + PCI_EXP_DEVCTL,
6889 pcie_set_readrq(tp->pdev, 4096);
6891 /* Clear error status */
6892 pci_write_config_word(tp->pdev,
6893 tp->pcie_cap + PCI_EXP_DEVSTA,
6894 PCI_EXP_DEVSTA_CED |
6895 PCI_EXP_DEVSTA_NFED |
6896 PCI_EXP_DEVSTA_FED |
6897 PCI_EXP_DEVSTA_URD);
6900 tg3_restore_pci_state(tp);
6902 tp->tg3_flags &= ~TG3_FLAG_CHIP_RESETTING;
6905 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
6906 val = tr32(MEMARB_MODE);
6907 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
6909 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
6911 tw32(0x5000, 0x400);
6914 tw32(GRC_MODE, tp->grc_mode);
6916 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
6919 tw32(0xc4, val | (1 << 15));
6922 if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
6923 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
6924 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
6925 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
6926 tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
6927 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6930 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6931 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
6932 tw32_f(MAC_MODE, tp->mac_mode);
6933 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6934 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
6935 tw32_f(MAC_MODE, tp->mac_mode);
6936 } else if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
6937 tp->mac_mode &= (MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN);
6938 if (tp->mac_mode & MAC_MODE_APE_TX_EN)
6939 tp->mac_mode |= MAC_MODE_TDE_ENABLE;
6940 tw32_f(MAC_MODE, tp->mac_mode);
6942 tw32_f(MAC_MODE, 0);
6945 tg3_ape_unlock(tp, TG3_APE_LOCK_GRC);
6947 err = tg3_poll_fw(tp);
6953 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
6956 phy_addr = tp->phy_addr;
6957 tp->phy_addr = TG3_PHY_PCIE_ADDR;
6959 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6960 TG3_PCIEPHY_TXB_BLK << TG3_PCIEPHY_BLOCK_SHIFT);
6961 val = TG3_PCIEPHY_TX0CTRL1_TXOCM | TG3_PCIEPHY_TX0CTRL1_RDCTL |
6962 TG3_PCIEPHY_TX0CTRL1_TXCMV | TG3_PCIEPHY_TX0CTRL1_TKSEL |
6963 TG3_PCIEPHY_TX0CTRL1_NB_EN;
6964 tg3_writephy(tp, TG3_PCIEPHY_TX0CTRL1, val);
6967 tg3_writephy(tp, TG3_PCIEPHY_BLOCK_ADDR,
6968 TG3_PCIEPHY_XGXS_BLK1 << TG3_PCIEPHY_BLOCK_SHIFT);
6969 val = TG3_PCIEPHY_PWRMGMT4_LOWPWR_EN |
6970 TG3_PCIEPHY_PWRMGMT4_L1PLLPD_EN;
6971 tg3_writephy(tp, TG3_PCIEPHY_PWRMGMT4, val);
6974 tp->phy_addr = phy_addr;
6977 if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
6978 tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
6979 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
6980 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
6981 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
6984 tw32(0x7c00, val | (1 << 25));
6987 /* Reprobe ASF enable state. */
6988 tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
6989 tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
6990 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
6991 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
6994 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
6995 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
6996 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
6997 tp->last_event_jiffies = jiffies;
6998 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
6999 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
7006 /* tp->lock is held. */
7007 static void tg3_stop_fw(struct tg3 *tp)
7009 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
7010 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
7011 /* Wait for RX cpu to ACK the previous event. */
7012 tg3_wait_for_event_ack(tp);
7014 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
7016 tg3_generate_fw_event(tp);
7018 /* Wait for RX cpu to ACK this event. */
7019 tg3_wait_for_event_ack(tp);
7023 /* tp->lock is held. */
7024 static int tg3_halt(struct tg3 *tp, int kind, int silent)
7030 tg3_write_sig_pre_reset(tp, kind);
7032 tg3_abort_hw(tp, silent);
7033 err = tg3_chip_reset(tp);
7035 __tg3_set_mac_addr(tp, 0);
7037 tg3_write_sig_legacy(tp, kind);
7038 tg3_write_sig_post_reset(tp, kind);
7046 #define RX_CPU_SCRATCH_BASE 0x30000
7047 #define RX_CPU_SCRATCH_SIZE 0x04000
7048 #define TX_CPU_SCRATCH_BASE 0x34000
7049 #define TX_CPU_SCRATCH_SIZE 0x04000
7051 /* tp->lock is held. */
7052 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
7056 BUG_ON(offset == TX_CPU_BASE &&
7057 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
7059 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7060 u32 val = tr32(GRC_VCPU_EXT_CTRL);
7062 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
7065 if (offset == RX_CPU_BASE) {
7066 for (i = 0; i < 10000; i++) {
7067 tw32(offset + CPU_STATE, 0xffffffff);
7068 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7069 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7073 tw32(offset + CPU_STATE, 0xffffffff);
7074 tw32_f(offset + CPU_MODE, CPU_MODE_HALT);
7077 for (i = 0; i < 10000; i++) {
7078 tw32(offset + CPU_STATE, 0xffffffff);
7079 tw32(offset + CPU_MODE, CPU_MODE_HALT);
7080 if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
7086 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
7089 (offset == RX_CPU_BASE ? "RX" : "TX"));
7093 /* Clear firmware's nvram arbitration. */
7094 if (tp->tg3_flags & TG3_FLAG_NVRAM)
7095 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
7100 unsigned int fw_base;
7101 unsigned int fw_len;
7102 const __be32 *fw_data;
7105 /* tp->lock is held. */
7106 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
7107 int cpu_scratch_size, struct fw_info *info)
7109 int err, lock_err, i;
7110 void (*write_op)(struct tg3 *, u32, u32);
7112 if (cpu_base == TX_CPU_BASE &&
7113 (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7114 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
7115 "TX cpu firmware on %s which is 5705.\n",
7120 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
7121 write_op = tg3_write_mem;
7123 write_op = tg3_write_indirect_reg32;
7125 /* It is possible that bootcode is still loading at this point.
7126 * Get the nvram lock first before halting the cpu.
7128 lock_err = tg3_nvram_lock(tp);
7129 err = tg3_halt_cpu(tp, cpu_base);
7131 tg3_nvram_unlock(tp);
7135 for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
7136 write_op(tp, cpu_scratch_base + i, 0);
7137 tw32(cpu_base + CPU_STATE, 0xffffffff);
7138 tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
7139 for (i = 0; i < (info->fw_len / sizeof(u32)); i++)
7140 write_op(tp, (cpu_scratch_base +
7141 (info->fw_base & 0xffff) +
7143 be32_to_cpu(info->fw_data[i]));
7151 /* tp->lock is held. */
7152 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
7154 struct fw_info info;
7155 const __be32 *fw_data;
7158 fw_data = (void *)tp->fw->data;
7160 /* Firmware blob starts with version numbers, followed by
7161 start address and length. We are setting complete length.
7162 length = end_address_of_bss - start_address_of_text.
7163 Remainder is the blob to be loaded contiguously
7164 from start address. */
7166 info.fw_base = be32_to_cpu(fw_data[1]);
7167 info.fw_len = tp->fw->size - 12;
7168 info.fw_data = &fw_data[3];
7170 err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
7171 RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
7176 err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
7177 TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
7182 /* Now startup only the RX cpu. */
7183 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7184 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7186 for (i = 0; i < 5; i++) {
7187 if (tr32(RX_CPU_BASE + CPU_PC) == info.fw_base)
7189 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7190 tw32(RX_CPU_BASE + CPU_MODE, CPU_MODE_HALT);
7191 tw32_f(RX_CPU_BASE + CPU_PC, info.fw_base);
7195 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
7196 "to set RX CPU PC, is %08x should be %08x\n",
7197 tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
7201 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
7202 tw32_f(RX_CPU_BASE + CPU_MODE, 0x00000000);
7207 /* 5705 needs a special version of the TSO firmware. */
7209 /* tp->lock is held. */
7210 static int tg3_load_tso_firmware(struct tg3 *tp)
7212 struct fw_info info;
7213 const __be32 *fw_data;
7214 unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
7217 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7220 fw_data = (void *)tp->fw->data;
7222 /* Firmware blob starts with version numbers, followed by
7223 start address and length. We are setting complete length.
7224 length = end_address_of_bss - start_address_of_text.
7225 Remainder is the blob to be loaded contiguously
7226 from start address. */
7228 info.fw_base = be32_to_cpu(fw_data[1]);
7229 cpu_scratch_size = tp->fw_len;
7230 info.fw_len = tp->fw->size - 12;
7231 info.fw_data = &fw_data[3];
7233 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7234 cpu_base = RX_CPU_BASE;
7235 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
7237 cpu_base = TX_CPU_BASE;
7238 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
7239 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
7242 err = tg3_load_firmware_cpu(tp, cpu_base,
7243 cpu_scratch_base, cpu_scratch_size,
7248 /* Now startup the cpu. */
7249 tw32(cpu_base + CPU_STATE, 0xffffffff);
7250 tw32_f(cpu_base + CPU_PC, info.fw_base);
7252 for (i = 0; i < 5; i++) {
7253 if (tr32(cpu_base + CPU_PC) == info.fw_base)
7255 tw32(cpu_base + CPU_STATE, 0xffffffff);
7256 tw32(cpu_base + CPU_MODE, CPU_MODE_HALT);
7257 tw32_f(cpu_base + CPU_PC, info.fw_base);
7261 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
7262 "to set CPU PC, is %08x should be %08x\n",
7263 tp->dev->name, tr32(cpu_base + CPU_PC),
7267 tw32(cpu_base + CPU_STATE, 0xffffffff);
7268 tw32_f(cpu_base + CPU_MODE, 0x00000000);
7273 static int tg3_set_mac_addr(struct net_device *dev, void *p)
7275 struct tg3 *tp = netdev_priv(dev);
7276 struct sockaddr *addr = p;
7277 int err = 0, skip_mac_1 = 0;
7279 if (!is_valid_ether_addr(addr->sa_data))
7282 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
7284 if (!netif_running(dev))
7287 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
7288 u32 addr0_high, addr0_low, addr1_high, addr1_low;
7290 addr0_high = tr32(MAC_ADDR_0_HIGH);
7291 addr0_low = tr32(MAC_ADDR_0_LOW);
7292 addr1_high = tr32(MAC_ADDR_1_HIGH);
7293 addr1_low = tr32(MAC_ADDR_1_LOW);
7295 /* Skip MAC addr 1 if ASF is using it. */
7296 if ((addr0_high != addr1_high || addr0_low != addr1_low) &&
7297 !(addr1_high == 0 && addr1_low == 0))
7300 spin_lock_bh(&tp->lock);
7301 __tg3_set_mac_addr(tp, skip_mac_1);
7302 spin_unlock_bh(&tp->lock);
7307 /* tp->lock is held. */
7308 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
7309 dma_addr_t mapping, u32 maxlen_flags,
7313 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
7314 ((u64) mapping >> 32));
7316 (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
7317 ((u64) mapping & 0xffffffff));
7319 (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
7322 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7324 (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
7328 static void __tg3_set_rx_mode(struct net_device *);
7329 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
7333 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)) {
7334 tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
7335 tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
7336 tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
7338 tw32(HOSTCC_TXCOL_TICKS, 0);
7339 tw32(HOSTCC_TXMAX_FRAMES, 0);
7340 tw32(HOSTCC_TXCOAL_MAXF_INT, 0);
7343 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
7344 tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
7345 tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
7346 tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
7348 tw32(HOSTCC_RXCOL_TICKS, 0);
7349 tw32(HOSTCC_RXMAX_FRAMES, 0);
7350 tw32(HOSTCC_RXCOAL_MAXF_INT, 0);
7353 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7354 u32 val = ec->stats_block_coalesce_usecs;
7356 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
7357 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
7359 if (!netif_carrier_ok(tp->dev))
7362 tw32(HOSTCC_STAT_COAL_TICKS, val);
7365 for (i = 0; i < tp->irq_cnt - 1; i++) {
7368 reg = HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18;
7369 tw32(reg, ec->rx_coalesce_usecs);
7370 reg = HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18;
7371 tw32(reg, ec->rx_max_coalesced_frames);
7372 reg = HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18;
7373 tw32(reg, ec->rx_max_coalesced_frames_irq);
7375 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7376 reg = HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18;
7377 tw32(reg, ec->tx_coalesce_usecs);
7378 reg = HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18;
7379 tw32(reg, ec->tx_max_coalesced_frames);
7380 reg = HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18;
7381 tw32(reg, ec->tx_max_coalesced_frames_irq);
7385 for (; i < tp->irq_max - 1; i++) {
7386 tw32(HOSTCC_RXCOL_TICKS_VEC1 + i * 0x18, 0);
7387 tw32(HOSTCC_RXMAX_FRAMES_VEC1 + i * 0x18, 0);
7388 tw32(HOSTCC_RXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7390 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS) {
7391 tw32(HOSTCC_TXCOL_TICKS_VEC1 + i * 0x18, 0);
7392 tw32(HOSTCC_TXMAX_FRAMES_VEC1 + i * 0x18, 0);
7393 tw32(HOSTCC_TXCOAL_MAXF_INT_VEC1 + i * 0x18, 0);
7398 /* tp->lock is held. */
7399 static void tg3_rings_reset(struct tg3 *tp)
7402 u32 stblk, txrcb, rxrcb, limit;
7403 struct tg3_napi *tnapi = &tp->napi[0];
7405 /* Disable all transmit rings but the first. */
7406 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7407 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16;
7408 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7409 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2;
7411 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7413 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE;
7414 txrcb < limit; txrcb += TG3_BDINFO_SIZE)
7415 tg3_write_mem(tp, txrcb + TG3_BDINFO_MAXLEN_FLAGS,
7416 BDINFO_FLAGS_DISABLED);
7419 /* Disable all receive return rings but the first. */
7420 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
7421 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
7422 else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7423 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
7424 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
7425 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7426 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
7428 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7430 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE;
7431 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE)
7432 tg3_write_mem(tp, rxrcb + TG3_BDINFO_MAXLEN_FLAGS,
7433 BDINFO_FLAGS_DISABLED);
7435 /* Disable interrupts */
7436 tw32_mailbox_f(tp->napi[0].int_mbox, 1);
7438 /* Zero mailbox registers. */
7439 if (tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) {
7440 for (i = 1; i < TG3_IRQ_MAX_VECS; i++) {
7441 tp->napi[i].tx_prod = 0;
7442 tp->napi[i].tx_cons = 0;
7443 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
7444 tw32_mailbox(tp->napi[i].prodmbox, 0);
7445 tw32_rx_mbox(tp->napi[i].consmbox, 0);
7446 tw32_mailbox_f(tp->napi[i].int_mbox, 1);
7448 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS))
7449 tw32_mailbox(tp->napi[0].prodmbox, 0);
7451 tp->napi[0].tx_prod = 0;
7452 tp->napi[0].tx_cons = 0;
7453 tw32_mailbox(tp->napi[0].prodmbox, 0);
7454 tw32_rx_mbox(tp->napi[0].consmbox, 0);
7457 /* Make sure the NIC-based send BD rings are disabled. */
7458 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7459 u32 mbox = MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW;
7460 for (i = 0; i < 16; i++)
7461 tw32_tx_mbox(mbox + i * 8, 0);
7464 txrcb = NIC_SRAM_SEND_RCB;
7465 rxrcb = NIC_SRAM_RCV_RET_RCB;
7467 /* Clear status block in ram. */
7468 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7470 /* Set status block DMA address */
7471 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7472 ((u64) tnapi->status_mapping >> 32));
7473 tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7474 ((u64) tnapi->status_mapping & 0xffffffff));
7476 if (tnapi->tx_ring) {
7477 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7478 (TG3_TX_RING_SIZE <<
7479 BDINFO_FLAGS_MAXLEN_SHIFT),
7480 NIC_SRAM_TX_BUFFER_DESC);
7481 txrcb += TG3_BDINFO_SIZE;
7484 if (tnapi->rx_rcb) {
7485 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7486 (TG3_RX_RCB_RING_SIZE(tp) <<
7487 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7488 rxrcb += TG3_BDINFO_SIZE;
7491 stblk = HOSTCC_STATBLCK_RING1;
7493 for (i = 1, tnapi++; i < tp->irq_cnt; i++, tnapi++) {
7494 u64 mapping = (u64)tnapi->status_mapping;
7495 tw32(stblk + TG3_64BIT_REG_HIGH, mapping >> 32);
7496 tw32(stblk + TG3_64BIT_REG_LOW, mapping & 0xffffffff);
7498 /* Clear status block in ram. */
7499 memset(tnapi->hw_status, 0, TG3_HW_STATUS_SIZE);
7501 if (tnapi->tx_ring) {
7502 tg3_set_bdinfo(tp, txrcb, tnapi->tx_desc_mapping,
7503 (TG3_TX_RING_SIZE <<
7504 BDINFO_FLAGS_MAXLEN_SHIFT),
7505 NIC_SRAM_TX_BUFFER_DESC);
7506 txrcb += TG3_BDINFO_SIZE;
7509 tg3_set_bdinfo(tp, rxrcb, tnapi->rx_rcb_mapping,
7510 (TG3_RX_RCB_RING_SIZE(tp) <<
7511 BDINFO_FLAGS_MAXLEN_SHIFT), 0);
7514 rxrcb += TG3_BDINFO_SIZE;
7518 /* tp->lock is held. */
7519 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
7521 u32 val, rdmac_mode;
7523 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
7525 tg3_disable_ints(tp);
7529 tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
7531 if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
7532 tg3_abort_hw(tp, 1);
7536 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB))
7539 err = tg3_chip_reset(tp);
7543 tg3_write_sig_legacy(tp, RESET_KIND_INIT);
7545 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX) {
7546 val = tr32(TG3_CPMU_CTRL);
7547 val &= ~(CPMU_CTRL_LINK_AWARE_MODE | CPMU_CTRL_LINK_IDLE_MODE);
7548 tw32(TG3_CPMU_CTRL, val);
7550 val = tr32(TG3_CPMU_LSPD_10MB_CLK);
7551 val &= ~CPMU_LSPD_10MB_MACCLK_MASK;
7552 val |= CPMU_LSPD_10MB_MACCLK_6_25;
7553 tw32(TG3_CPMU_LSPD_10MB_CLK, val);
7555 val = tr32(TG3_CPMU_LNK_AWARE_PWRMD);
7556 val &= ~CPMU_LNK_AWARE_MACCLK_MASK;
7557 val |= CPMU_LNK_AWARE_MACCLK_6_25;
7558 tw32(TG3_CPMU_LNK_AWARE_PWRMD, val);
7560 val = tr32(TG3_CPMU_HST_ACC);
7561 val &= ~CPMU_HST_ACC_MACCLK_MASK;
7562 val |= CPMU_HST_ACC_MACCLK_6_25;
7563 tw32(TG3_CPMU_HST_ACC, val);
7566 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) {
7567 val = tr32(PCIE_PWR_MGMT_THRESH) & ~PCIE_PWR_MGMT_L1_THRESH_MSK;
7568 val |= PCIE_PWR_MGMT_EXT_ASPM_TMR_EN |
7569 PCIE_PWR_MGMT_L1_THRESH_4MS;
7570 tw32(PCIE_PWR_MGMT_THRESH, val);
7572 val = tr32(TG3_PCIE_EIDLE_DELAY) & ~TG3_PCIE_EIDLE_DELAY_MASK;
7573 tw32(TG3_PCIE_EIDLE_DELAY, val | TG3_PCIE_EIDLE_DELAY_13_CLKS);
7575 tw32(TG3_CORR_ERR_STAT, TG3_CORR_ERR_STAT_CLEAR);
7577 val = tr32(TG3_PCIE_LNKCTL) & ~TG3_PCIE_LNKCTL_L1_PLL_PD_EN;
7578 tw32(TG3_PCIE_LNKCTL, val | TG3_PCIE_LNKCTL_L1_PLL_PD_DIS);
7581 if (tp->tg3_flags3 & TG3_FLG3_L1PLLPD_EN) {
7582 u32 grc_mode = tr32(GRC_MODE);
7584 /* Access the lower 1K of PL PCIE block registers. */
7585 val = grc_mode & ~GRC_MODE_PCIE_PORT_MASK;
7586 tw32(GRC_MODE, val | GRC_MODE_PCIE_PL_SEL);
7588 val = tr32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1);
7589 tw32(TG3_PCIE_TLDLPL_PORT + TG3_PCIE_PL_LO_PHYCTL1,
7590 val | TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN);
7592 tw32(GRC_MODE, grc_mode);
7595 /* This works around an issue with Athlon chipsets on
7596 * B3 tigon3 silicon. This bit has no effect on any
7597 * other revision. But do not set this on PCI Express
7598 * chips and don't even touch the clocks if the CPMU is present.
7600 if (!(tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)) {
7601 if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
7602 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
7603 tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
7606 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
7607 (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
7608 val = tr32(TG3PCI_PCISTATE);
7609 val |= PCISTATE_RETRY_SAME_DMA;
7610 tw32(TG3PCI_PCISTATE, val);
7613 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
7614 /* Allow reads and writes to the
7615 * APE register and memory space.
7617 val = tr32(TG3PCI_PCISTATE);
7618 val |= PCISTATE_ALLOW_APE_CTLSPC_WR |
7619 PCISTATE_ALLOW_APE_SHMEM_WR;
7620 tw32(TG3PCI_PCISTATE, val);
7623 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
7624 /* Enable some hw fixes. */
7625 val = tr32(TG3PCI_MSI_DATA);
7626 val |= (1 << 26) | (1 << 28) | (1 << 29);
7627 tw32(TG3PCI_MSI_DATA, val);
7630 /* Descriptor ring init may make accesses to the
7631 * NIC SRAM area to setup the TX descriptors, so we
7632 * can only do this after the hardware has been
7633 * successfully reset.
7635 err = tg3_init_rings(tp);
7639 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7640 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7641 val = tr32(TG3PCI_DMA_RW_CTRL) &
7642 ~DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
7643 tw32(TG3PCI_DMA_RW_CTRL, val | tp->dma_rwctrl);
7644 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
7645 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
7646 /* This value is determined during the probe time DMA
7647 * engine test, tg3_test_dma.
7649 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
7652 tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
7653 GRC_MODE_4X_NIC_SEND_RINGS |
7654 GRC_MODE_NO_TX_PHDR_CSUM |
7655 GRC_MODE_NO_RX_PHDR_CSUM);
7656 tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
7658 /* Pseudo-header checksum is done by hardware logic and not
7659 * the offload processers, so make the chip do the pseudo-
7660 * header checksums on receive. For transmit it is more
7661 * convenient to do the pseudo-header checksum in software
7662 * as Linux does that on transmit for us in all cases.
7664 tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
7668 (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
7670 /* Setup the timer prescalar register. Clock is always 66Mhz. */
7671 val = tr32(GRC_MISC_CFG);
7673 val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
7674 tw32(GRC_MISC_CFG, val);
7676 /* Initialize MBUF/DESC pool. */
7677 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7679 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
7680 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
7681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
7682 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
7684 tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
7685 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
7686 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
7688 else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
7691 fw_len = tp->fw_len;
7692 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
7693 tw32(BUFMGR_MB_POOL_ADDR,
7694 NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
7695 tw32(BUFMGR_MB_POOL_SIZE,
7696 NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
7699 if (tp->dev->mtu <= ETH_DATA_LEN) {
7700 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7701 tp->bufmgr_config.mbuf_read_dma_low_water);
7702 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7703 tp->bufmgr_config.mbuf_mac_rx_low_water);
7704 tw32(BUFMGR_MB_HIGH_WATER,
7705 tp->bufmgr_config.mbuf_high_water);
7707 tw32(BUFMGR_MB_RDMA_LOW_WATER,
7708 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
7709 tw32(BUFMGR_MB_MACRX_LOW_WATER,
7710 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
7711 tw32(BUFMGR_MB_HIGH_WATER,
7712 tp->bufmgr_config.mbuf_high_water_jumbo);
7714 tw32(BUFMGR_DMA_LOW_WATER,
7715 tp->bufmgr_config.dma_low_water);
7716 tw32(BUFMGR_DMA_HIGH_WATER,
7717 tp->bufmgr_config.dma_high_water);
7719 tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
7720 for (i = 0; i < 2000; i++) {
7721 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
7726 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
7731 /* Setup replenish threshold. */
7732 val = tp->rx_pending / 8;
7735 else if (val > tp->rx_std_max_post)
7736 val = tp->rx_std_max_post;
7737 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
7738 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
7739 tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
7741 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
7742 val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
7745 tw32(RCVBDI_STD_THRESH, val);
7747 /* Initialize TG3_BDINFO's at:
7748 * RCVDBDI_STD_BD: standard eth size rx ring
7749 * RCVDBDI_JUMBO_BD: jumbo frame rx ring
7750 * RCVDBDI_MINI_BD: small frame rx ring (??? does not work)
7753 * TG3_BDINFO_HOST_ADDR: high/low parts of DMA address of ring
7754 * TG3_BDINFO_MAXLEN_FLAGS: (rx max buffer size << 16) |
7755 * ring attribute flags
7756 * TG3_BDINFO_NIC_ADDR: location of descriptors in nic SRAM
7758 * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
7759 * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
7761 * The size of each ring is fixed in the firmware, but the location is
7764 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7765 ((u64) tpr->rx_std_mapping >> 32));
7766 tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7767 ((u64) tpr->rx_std_mapping & 0xffffffff));
7768 if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS))
7769 tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
7770 NIC_SRAM_RX_BUFFER_DESC);
7772 /* Disable the mini ring */
7773 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7774 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
7775 BDINFO_FLAGS_DISABLED);
7777 /* Program the jumbo buffer descriptor ring control
7778 * blocks on those devices that have them.
7780 if ((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) &&
7781 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
7782 /* Setup replenish threshold. */
7783 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
7785 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
7786 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
7787 ((u64) tpr->rx_jmb_mapping >> 32));
7788 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
7789 ((u64) tpr->rx_jmb_mapping & 0xffffffff));
7790 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7791 (RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT) |
7792 BDINFO_FLAGS_USE_EXT_RECV);
7793 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717)
7794 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
7795 NIC_SRAM_RX_JUMBO_BUFFER_DESC);
7797 tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
7798 BDINFO_FLAGS_DISABLED);
7801 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7802 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
7803 val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
7804 (RX_STD_MAX_SIZE << 2);
7806 val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
7808 val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
7810 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS, val);
7812 tpr->rx_std_prod_idx = tp->rx_pending;
7813 tw32_rx_mbox(TG3_RX_STD_PROD_IDX_REG, tpr->rx_std_prod_idx);
7815 tpr->rx_jmb_prod_idx = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
7816 tp->rx_jumbo_pending : 0;
7817 tw32_rx_mbox(TG3_RX_JMB_PROD_IDX_REG, tpr->rx_jmb_prod_idx);
7819 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
7820 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
7821 tw32(STD_REPLENISH_LWM, 32);
7822 tw32(JMB_REPLENISH_LWM, 16);
7825 tg3_rings_reset(tp);
7827 /* Initialize MAC address and backoff seed. */
7828 __tg3_set_mac_addr(tp, 0);
7830 /* MTU + ethernet header + FCS + optional VLAN tag */
7831 tw32(MAC_RX_MTU_SIZE,
7832 tp->dev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN);
7834 /* The slot time is changed by tg3_setup_phy if we
7835 * run at gigabit with half duplex.
7837 tw32(MAC_TX_LENGTHS,
7838 (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
7839 (6 << TX_LENGTHS_IPG_SHIFT) |
7840 (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
7842 /* Receive rules. */
7843 tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
7844 tw32(RCVLPC_CONFIG, 0x0181);
7846 /* Calculate RDMAC_MODE setting early, we need it to determine
7847 * the RCVLPC_STATE_ENABLE mask.
7849 rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
7850 RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
7851 RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
7852 RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
7853 RDMAC_MODE_LNGREAD_ENAB);
7855 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
7856 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7857 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7858 rdmac_mode |= RDMAC_MODE_BD_SBD_CRPT_ENAB |
7859 RDMAC_MODE_MBUF_RBD_CRPT_ENAB |
7860 RDMAC_MODE_MBUF_SBD_CRPT_ENAB;
7862 /* If statement applies to 5705 and 5750 PCI devices only */
7863 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
7864 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
7865 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
7866 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
7867 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
7868 rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
7869 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
7870 !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
7871 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7875 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
7876 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
7878 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
7879 rdmac_mode |= RDMAC_MODE_IPV4_LSO_EN;
7881 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
7882 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
7883 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
7884 rdmac_mode |= RDMAC_MODE_IPV6_LSO_EN;
7886 /* Receive/send statistics. */
7887 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
7888 val = tr32(RCVLPC_STATS_ENABLE);
7889 val &= ~RCVLPC_STATSENAB_DACK_FIX;
7890 tw32(RCVLPC_STATS_ENABLE, val);
7891 } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
7892 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
7893 val = tr32(RCVLPC_STATS_ENABLE);
7894 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
7895 tw32(RCVLPC_STATS_ENABLE, val);
7897 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
7899 tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
7900 tw32(SNDDATAI_STATSENAB, 0xffffff);
7901 tw32(SNDDATAI_STATSCTRL,
7902 (SNDDATAI_SCTRL_ENABLE |
7903 SNDDATAI_SCTRL_FASTUPD));
7905 /* Setup host coalescing engine. */
7906 tw32(HOSTCC_MODE, 0);
7907 for (i = 0; i < 2000; i++) {
7908 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
7913 __tg3_set_coalesce(tp, &tp->coal);
7915 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
7916 /* Status/statistics block address. See tg3_timer,
7917 * the tg3_periodic_fetch_stats call there, and
7918 * tg3_get_stats to see how this works for 5705/5750 chips.
7920 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
7921 ((u64) tp->stats_mapping >> 32));
7922 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
7923 ((u64) tp->stats_mapping & 0xffffffff));
7924 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
7926 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
7928 /* Clear statistics and status block memory areas */
7929 for (i = NIC_SRAM_STATS_BLK;
7930 i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
7932 tg3_write_mem(tp, i, 0);
7937 tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
7939 tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
7940 tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
7941 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
7942 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
7944 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
7945 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
7946 /* reset to prevent losing 1st rx packet intermittently */
7947 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
7951 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
7952 tp->mac_mode &= MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
7955 tp->mac_mode |= MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
7956 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
7957 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
7958 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7959 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700)
7960 tp->mac_mode |= MAC_MODE_LINK_POLARITY;
7961 tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
7964 /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
7965 * If TG3_FLG2_IS_NIC is zero, we should read the
7966 * register to preserve the GPIO settings for LOMs. The GPIOs,
7967 * whether used as inputs or outputs, are set by boot code after
7970 if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
7973 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
7974 GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
7975 GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
7977 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
7978 gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
7979 GRC_LCLCTRL_GPIO_OUTPUT3;
7981 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
7982 gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
7984 tp->grc_local_ctrl &= ~gpio_mask;
7985 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
7987 /* GPIO1 must be driven high for eeprom write protect */
7988 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
7989 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
7990 GRC_LCLCTRL_GPIO_OUTPUT1);
7992 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
7995 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX) {
7996 val = tr32(MSGINT_MODE);
7997 val |= MSGINT_MODE_MULTIVEC_EN | MSGINT_MODE_ENABLE;
7998 tw32(MSGINT_MODE, val);
8001 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
8002 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
8006 val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
8007 WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
8008 WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
8009 WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
8010 WDMAC_MODE_LNGREAD_ENAB);
8012 /* If statement applies to 5705 and 5750 PCI devices only */
8013 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
8014 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
8015 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
8016 if ((tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
8017 (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
8018 tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
8020 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
8021 !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8022 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
8023 val |= WDMAC_MODE_RX_ACCEL;
8027 /* Enable host coalescing bug fix */
8028 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8029 val |= WDMAC_MODE_STATUS_TAG_FIX;
8031 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
8032 val |= WDMAC_MODE_BURST_ALL_DATA;
8034 tw32_f(WDMAC_MODE, val);
8037 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
8040 pci_read_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8042 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
8043 pcix_cmd &= ~PCI_X_CMD_MAX_READ;
8044 pcix_cmd |= PCI_X_CMD_READ_2K;
8045 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
8046 pcix_cmd &= ~(PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ);
8047 pcix_cmd |= PCI_X_CMD_READ_2K;
8049 pci_write_config_word(tp->pdev, tp->pcix_cap + PCI_X_CMD,
8053 tw32_f(RDMAC_MODE, rdmac_mode);
8056 tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
8057 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8058 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
8060 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
8062 SNDDATAC_MODE_ENABLE | SNDDATAC_MODE_CDELAY);
8064 tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
8066 tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
8067 tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
8068 tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
8069 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
8070 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
8071 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
8072 val = SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE;
8073 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_TSS)
8074 val |= SNDBDI_MODE_MULTI_TXQ_EN;
8075 tw32(SNDBDI_MODE, val);
8076 tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
8078 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8079 err = tg3_load_5701_a0_firmware_fix(tp);
8084 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
8085 err = tg3_load_tso_firmware(tp);
8090 tp->tx_mode = TX_MODE_ENABLE;
8091 tw32_f(MAC_TX_MODE, tp->tx_mode);
8094 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS) {
8095 u32 reg = MAC_RSS_INDIR_TBL_0;
8096 u8 *ent = (u8 *)&val;
8098 /* Setup the indirection table */
8099 for (i = 0; i < TG3_RSS_INDIR_TBL_SIZE; i++) {
8100 int idx = i % sizeof(val);
8102 ent[idx] = i % (tp->irq_cnt - 1);
8103 if (idx == sizeof(val) - 1) {
8109 /* Setup the "secret" hash key. */
8110 tw32(MAC_RSS_HASH_KEY_0, 0x5f865437);
8111 tw32(MAC_RSS_HASH_KEY_1, 0xe4ac62cc);
8112 tw32(MAC_RSS_HASH_KEY_2, 0x50103a45);
8113 tw32(MAC_RSS_HASH_KEY_3, 0x36621985);
8114 tw32(MAC_RSS_HASH_KEY_4, 0xbf14c0e8);
8115 tw32(MAC_RSS_HASH_KEY_5, 0x1bc27a1e);
8116 tw32(MAC_RSS_HASH_KEY_6, 0x84f4b556);
8117 tw32(MAC_RSS_HASH_KEY_7, 0x094ea6fe);
8118 tw32(MAC_RSS_HASH_KEY_8, 0x7dda01e7);
8119 tw32(MAC_RSS_HASH_KEY_9, 0xc04d7481);
8122 tp->rx_mode = RX_MODE_ENABLE;
8123 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
8124 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
8126 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_RSS)
8127 tp->rx_mode |= RX_MODE_RSS_ENABLE |
8128 RX_MODE_RSS_ITBL_HASH_BITS_7 |
8129 RX_MODE_RSS_IPV6_HASH_EN |
8130 RX_MODE_RSS_TCP_IPV6_HASH_EN |
8131 RX_MODE_RSS_IPV4_HASH_EN |
8132 RX_MODE_RSS_TCP_IPV4_HASH_EN;
8134 tw32_f(MAC_RX_MODE, tp->rx_mode);
8137 tw32(MAC_LED_CTRL, tp->led_ctrl);
8139 tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
8140 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8141 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8144 tw32_f(MAC_RX_MODE, tp->rx_mode);
8147 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
8148 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
8149 !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
8150 /* Set drive transmission level to 1.2V */
8151 /* only if the signal pre-emphasis bit is not set */
8152 val = tr32(MAC_SERDES_CFG);
8155 tw32(MAC_SERDES_CFG, val);
8157 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
8158 tw32(MAC_SERDES_CFG, 0x616000);
8161 /* Prevent chip from dropping frames when flow control
8164 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
8168 tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, val);
8170 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
8171 (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8172 /* Use hardware link auto-negotiation */
8173 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
8176 if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
8177 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
8180 tmp = tr32(SERDES_RX_CTRL);
8181 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
8182 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
8183 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
8184 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
8187 if (!(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
8188 if (tp->link_config.phy_is_low_power) {
8189 tp->link_config.phy_is_low_power = 0;
8190 tp->link_config.speed = tp->link_config.orig_speed;
8191 tp->link_config.duplex = tp->link_config.orig_duplex;
8192 tp->link_config.autoneg = tp->link_config.orig_autoneg;
8195 err = tg3_setup_phy(tp, 0);
8199 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
8200 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET)) {
8203 /* Clear CRC stats. */
8204 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
8205 tg3_writephy(tp, MII_TG3_TEST1,
8206 tmp | MII_TG3_TEST1_CRC_EN);
8207 tg3_readphy(tp, 0x14, &tmp);
8212 __tg3_set_rx_mode(tp->dev);
8214 /* Initialize receive rules. */
8215 tw32(MAC_RCV_RULE_0, 0xc2000000 & RCV_RULE_DISABLE_MASK);
8216 tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
8217 tw32(MAC_RCV_RULE_1, 0x86000004 & RCV_RULE_DISABLE_MASK);
8218 tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
8220 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
8221 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
8225 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
8229 tw32(MAC_RCV_RULE_15, 0); tw32(MAC_RCV_VALUE_15, 0);
8231 tw32(MAC_RCV_RULE_14, 0); tw32(MAC_RCV_VALUE_14, 0);
8233 tw32(MAC_RCV_RULE_13, 0); tw32(MAC_RCV_VALUE_13, 0);
8235 tw32(MAC_RCV_RULE_12, 0); tw32(MAC_RCV_VALUE_12, 0);
8237 tw32(MAC_RCV_RULE_11, 0); tw32(MAC_RCV_VALUE_11, 0);
8239 tw32(MAC_RCV_RULE_10, 0); tw32(MAC_RCV_VALUE_10, 0);
8241 tw32(MAC_RCV_RULE_9, 0); tw32(MAC_RCV_VALUE_9, 0);
8243 tw32(MAC_RCV_RULE_8, 0); tw32(MAC_RCV_VALUE_8, 0);
8245 tw32(MAC_RCV_RULE_7, 0); tw32(MAC_RCV_VALUE_7, 0);
8247 tw32(MAC_RCV_RULE_6, 0); tw32(MAC_RCV_VALUE_6, 0);
8249 tw32(MAC_RCV_RULE_5, 0); tw32(MAC_RCV_VALUE_5, 0);
8251 tw32(MAC_RCV_RULE_4, 0); tw32(MAC_RCV_VALUE_4, 0);
8253 /* tw32(MAC_RCV_RULE_3, 0); tw32(MAC_RCV_VALUE_3, 0); */
8255 /* tw32(MAC_RCV_RULE_2, 0); tw32(MAC_RCV_VALUE_2, 0); */
8263 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
8264 /* Write our heartbeat update interval to APE. */
8265 tg3_ape_write32(tp, TG3_APE_HOST_HEARTBEAT_INT_MS,
8266 APE_HOST_HEARTBEAT_INT_DISABLE);
8268 tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
8273 /* Called at device open time to get the chip ready for
8274 * packet processing. Invoked with tp->lock held.
8276 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
8278 tg3_switch_clocks(tp);
8280 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
8282 return tg3_reset_hw(tp, reset_phy);
8285 #define TG3_STAT_ADD32(PSTAT, REG) \
8286 do { u32 __val = tr32(REG); \
8287 (PSTAT)->low += __val; \
8288 if ((PSTAT)->low < __val) \
8289 (PSTAT)->high += 1; \
8292 static void tg3_periodic_fetch_stats(struct tg3 *tp)
8294 struct tg3_hw_stats *sp = tp->hw_stats;
8296 if (!netif_carrier_ok(tp->dev))
8299 TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
8300 TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
8301 TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
8302 TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
8303 TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
8304 TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
8305 TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
8306 TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
8307 TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
8308 TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
8309 TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
8310 TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
8311 TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
8313 TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
8314 TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
8315 TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
8316 TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
8317 TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
8318 TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
8319 TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
8320 TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
8321 TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
8322 TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
8323 TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
8324 TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
8325 TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
8326 TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
8328 TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
8329 TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
8330 TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
8333 static void tg3_timer(unsigned long __opaque)
8335 struct tg3 *tp = (struct tg3 *) __opaque;
8340 spin_lock(&tp->lock);
8342 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8343 /* All of this garbage is because when using non-tagged
8344 * IRQ status the mailbox/status_block protocol the chip
8345 * uses with the cpu is race prone.
8347 if (tp->napi[0].hw_status->status & SD_STATUS_UPDATED) {
8348 tw32(GRC_LOCAL_CTRL,
8349 tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
8351 tw32(HOSTCC_MODE, tp->coalesce_mode |
8352 HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW);
8355 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
8356 tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
8357 spin_unlock(&tp->lock);
8358 schedule_work(&tp->reset_task);
8363 /* This part only runs once per second. */
8364 if (!--tp->timer_counter) {
8365 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
8366 tg3_periodic_fetch_stats(tp);
8368 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
8372 mac_stat = tr32(MAC_STATUS);
8375 if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
8376 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
8378 } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
8382 tg3_setup_phy(tp, 0);
8383 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
8384 u32 mac_stat = tr32(MAC_STATUS);
8387 if (netif_carrier_ok(tp->dev) &&
8388 (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
8391 if (! netif_carrier_ok(tp->dev) &&
8392 (mac_stat & (MAC_STATUS_PCS_SYNCED |
8393 MAC_STATUS_SIGNAL_DET))) {
8397 if (!tp->serdes_counter) {
8400 ~MAC_MODE_PORT_MODE_MASK));
8402 tw32_f(MAC_MODE, tp->mac_mode);
8405 tg3_setup_phy(tp, 0);
8407 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8408 tg3_serdes_parallel_detect(tp);
8410 tp->timer_counter = tp->timer_multiplier;
8413 /* Heartbeat is only sent once every 2 seconds.
8415 * The heartbeat is to tell the ASF firmware that the host
8416 * driver is still alive. In the event that the OS crashes,
8417 * ASF needs to reset the hardware to free up the FIFO space
8418 * that may be filled with rx packets destined for the host.
8419 * If the FIFO is full, ASF will no longer function properly.
8421 * Unintended resets have been reported on real time kernels
8422 * where the timer doesn't run on time. Netpoll will also have
8425 * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
8426 * to check the ring condition when the heartbeat is expiring
8427 * before doing the reset. This will prevent most unintended
8430 if (!--tp->asf_counter) {
8431 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) &&
8432 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
8433 tg3_wait_for_event_ack(tp);
8435 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
8436 FWCMD_NICDRV_ALIVE3);
8437 tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
8438 /* 5 seconds timeout */
8439 tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
8441 tg3_generate_fw_event(tp);
8443 tp->asf_counter = tp->asf_multiplier;
8446 spin_unlock(&tp->lock);
8449 tp->timer.expires = jiffies + tp->timer_offset;
8450 add_timer(&tp->timer);
8453 static int tg3_request_irq(struct tg3 *tp, int irq_num)
8456 unsigned long flags;
8458 struct tg3_napi *tnapi = &tp->napi[irq_num];
8460 if (tp->irq_cnt == 1)
8461 name = tp->dev->name;
8463 name = &tnapi->irq_lbl[0];
8464 snprintf(name, IFNAMSIZ, "%s-%d", tp->dev->name, irq_num);
8465 name[IFNAMSIZ-1] = 0;
8468 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8470 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
8472 flags = IRQF_SAMPLE_RANDOM;
8475 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8476 fn = tg3_interrupt_tagged;
8477 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
8480 return request_irq(tnapi->irq_vec, fn, flags, name, tnapi);
8483 static int tg3_test_interrupt(struct tg3 *tp)
8485 struct tg3_napi *tnapi = &tp->napi[0];
8486 struct net_device *dev = tp->dev;
8487 int err, i, intr_ok = 0;
8490 if (!netif_running(dev))
8493 tg3_disable_ints(tp);
8495 free_irq(tnapi->irq_vec, tnapi);
8498 * Turn off MSI one shot mode. Otherwise this test has no
8499 * observable way to know whether the interrupt was delivered.
8501 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8502 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8503 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8504 val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
8505 tw32(MSGINT_MODE, val);
8508 err = request_irq(tnapi->irq_vec, tg3_test_isr,
8509 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
8513 tnapi->hw_status->status &= ~SD_STATUS_UPDATED;
8514 tg3_enable_ints(tp);
8516 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8519 for (i = 0; i < 5; i++) {
8520 u32 int_mbox, misc_host_ctrl;
8522 int_mbox = tr32_mailbox(tnapi->int_mbox);
8523 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
8525 if ((int_mbox != 0) ||
8526 (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
8534 tg3_disable_ints(tp);
8536 free_irq(tnapi->irq_vec, tnapi);
8538 err = tg3_request_irq(tp, 0);
8544 /* Reenable MSI one shot mode. */
8545 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
8546 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) &&
8547 (tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
8548 val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
8549 tw32(MSGINT_MODE, val);
8557 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
8558 * successfully restored
8560 static int tg3_test_msi(struct tg3 *tp)
8565 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
8568 /* Turn off SERR reporting in case MSI terminates with Master
8571 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
8572 pci_write_config_word(tp->pdev, PCI_COMMAND,
8573 pci_cmd & ~PCI_COMMAND_SERR);
8575 err = tg3_test_interrupt(tp);
8577 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
8582 /* other failures */
8586 /* MSI test failed, go back to INTx mode */
8587 printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
8588 "switching to INTx mode. Please report this failure to "
8589 "the PCI maintainer and include system chipset information.\n",
8592 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8594 pci_disable_msi(tp->pdev);
8596 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
8598 err = tg3_request_irq(tp, 0);
8602 /* Need to reset the chip because the MSI cycle may have terminated
8603 * with Master Abort.
8605 tg3_full_lock(tp, 1);
8607 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8608 err = tg3_init_hw(tp, 1);
8610 tg3_full_unlock(tp);
8613 free_irq(tp->napi[0].irq_vec, &tp->napi[0]);
8618 static int tg3_request_firmware(struct tg3 *tp)
8620 const __be32 *fw_data;
8622 if (request_firmware(&tp->fw, tp->fw_needed, &tp->pdev->dev)) {
8623 printk(KERN_ERR "%s: Failed to load firmware \"%s\"\n",
8624 tp->dev->name, tp->fw_needed);
8628 fw_data = (void *)tp->fw->data;
8630 /* Firmware blob starts with version numbers, followed by
8631 * start address and _full_ length including BSS sections
8632 * (which must be longer than the actual data, of course
8635 tp->fw_len = be32_to_cpu(fw_data[2]); /* includes bss */
8636 if (tp->fw_len < (tp->fw->size - 12)) {
8637 printk(KERN_ERR "%s: bogus length %d in \"%s\"\n",
8638 tp->dev->name, tp->fw_len, tp->fw_needed);
8639 release_firmware(tp->fw);
8644 /* We no longer need firmware; we have it. */
8645 tp->fw_needed = NULL;
8649 static bool tg3_enable_msix(struct tg3 *tp)
8651 int i, rc, cpus = num_online_cpus();
8652 struct msix_entry msix_ent[tp->irq_max];
8655 /* Just fallback to the simpler MSI mode. */
8659 * We want as many rx rings enabled as there are cpus.
8660 * The first MSIX vector only deals with link interrupts, etc,
8661 * so we add one to the number of vectors we are requesting.
8663 tp->irq_cnt = min_t(unsigned, cpus + 1, tp->irq_max);
8665 for (i = 0; i < tp->irq_max; i++) {
8666 msix_ent[i].entry = i;
8667 msix_ent[i].vector = 0;
8670 rc = pci_enable_msix(tp->pdev, msix_ent, tp->irq_cnt);
8672 if (rc < TG3_RSS_MIN_NUM_MSIX_VECS)
8674 if (pci_enable_msix(tp->pdev, msix_ent, rc))
8677 "%s: Requested %d MSI-X vectors, received %d\n",
8678 tp->dev->name, tp->irq_cnt, rc);
8682 tp->tg3_flags3 |= TG3_FLG3_ENABLE_RSS;
8684 for (i = 0; i < tp->irq_max; i++)
8685 tp->napi[i].irq_vec = msix_ent[i].vector;
8687 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
8688 tp->tg3_flags3 |= TG3_FLG3_ENABLE_TSS;
8689 tp->dev->real_num_tx_queues = tp->irq_cnt - 1;
8691 tp->dev->real_num_tx_queues = 1;
8696 static void tg3_ints_init(struct tg3 *tp)
8698 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI_OR_MSIX) &&
8699 !(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
8700 /* All MSI supporting chips should support tagged
8701 * status. Assert that this is the case.
8703 printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
8704 "Not using MSI.\n", tp->dev->name);
8708 if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX) && tg3_enable_msix(tp))
8709 tp->tg3_flags2 |= TG3_FLG2_USING_MSIX;
8710 else if ((tp->tg3_flags & TG3_FLAG_SUPPORT_MSI) &&
8711 pci_enable_msi(tp->pdev) == 0)
8712 tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
8714 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI_OR_MSIX) {
8715 u32 msi_mode = tr32(MSGINT_MODE);
8716 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8717 msi_mode |= MSGINT_MODE_MULTIVEC_EN;
8718 tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
8721 if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSIX)) {
8723 tp->napi[0].irq_vec = tp->pdev->irq;
8724 tp->dev->real_num_tx_queues = 1;
8728 static void tg3_ints_fini(struct tg3 *tp)
8730 if (tp->tg3_flags2 & TG3_FLG2_USING_MSIX)
8731 pci_disable_msix(tp->pdev);
8732 else if (tp->tg3_flags2 & TG3_FLG2_USING_MSI)
8733 pci_disable_msi(tp->pdev);
8734 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI_OR_MSIX;
8735 tp->tg3_flags3 &= ~TG3_FLG3_ENABLE_RSS;
8738 static int tg3_open(struct net_device *dev)
8740 struct tg3 *tp = netdev_priv(dev);
8743 if (tp->fw_needed) {
8744 err = tg3_request_firmware(tp);
8745 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
8749 printk(KERN_WARNING "%s: TSO capability disabled.\n",
8751 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
8752 } else if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8753 printk(KERN_NOTICE "%s: TSO capability restored.\n",
8755 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
8759 netif_carrier_off(tp->dev);
8761 err = tg3_set_power_state(tp, PCI_D0);
8765 tg3_full_lock(tp, 0);
8767 tg3_disable_ints(tp);
8768 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
8770 tg3_full_unlock(tp);
8773 * Setup interrupts first so we know how
8774 * many NAPI resources to allocate
8778 /* The placement of this call is tied
8779 * to the setup and use of Host TX descriptors.
8781 err = tg3_alloc_consistent(tp);
8785 tg3_napi_enable(tp);
8787 for (i = 0; i < tp->irq_cnt; i++) {
8788 struct tg3_napi *tnapi = &tp->napi[i];
8789 err = tg3_request_irq(tp, i);
8791 for (i--; i >= 0; i--)
8792 free_irq(tnapi->irq_vec, tnapi);
8800 tg3_full_lock(tp, 0);
8802 err = tg3_init_hw(tp, 1);
8804 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8807 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
8808 tp->timer_offset = HZ;
8810 tp->timer_offset = HZ / 10;
8812 BUG_ON(tp->timer_offset > HZ);
8813 tp->timer_counter = tp->timer_multiplier =
8814 (HZ / tp->timer_offset);
8815 tp->asf_counter = tp->asf_multiplier =
8816 ((HZ / tp->timer_offset) * 2);
8818 init_timer(&tp->timer);
8819 tp->timer.expires = jiffies + tp->timer_offset;
8820 tp->timer.data = (unsigned long) tp;
8821 tp->timer.function = tg3_timer;
8824 tg3_full_unlock(tp);
8829 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
8830 err = tg3_test_msi(tp);
8833 tg3_full_lock(tp, 0);
8834 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8836 tg3_full_unlock(tp);
8841 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
8842 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765 &&
8843 (tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
8844 (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
8845 u32 val = tr32(PCIE_TRANSACTION_CFG);
8847 tw32(PCIE_TRANSACTION_CFG,
8848 val | PCIE_TRANS_CFG_1SHOT_MSI);
8854 tg3_full_lock(tp, 0);
8856 add_timer(&tp->timer);
8857 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
8858 tg3_enable_ints(tp);
8860 tg3_full_unlock(tp);
8862 netif_tx_start_all_queues(dev);
8867 for (i = tp->irq_cnt - 1; i >= 0; i--) {
8868 struct tg3_napi *tnapi = &tp->napi[i];
8869 free_irq(tnapi->irq_vec, tnapi);
8873 tg3_napi_disable(tp);
8874 tg3_free_consistent(tp);
8882 /*static*/ void tg3_dump_state(struct tg3 *tp)
8884 u32 val32, val32_2, val32_3, val32_4, val32_5;
8887 struct tg3_hw_status *sblk = tp->napi[0]->hw_status;
8889 pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
8890 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
8891 printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
8895 printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
8896 tr32(MAC_MODE), tr32(MAC_STATUS));
8897 printk(" MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
8898 tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
8899 printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
8900 tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
8901 printk(" MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
8902 tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
8904 /* Send data initiator control block */
8905 printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
8906 tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
8907 printk(" SNDDATAI_STATSCTRL[%08x]\n",
8908 tr32(SNDDATAI_STATSCTRL));
8910 /* Send data completion control block */
8911 printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
8913 /* Send BD ring selector block */
8914 printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
8915 tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
8917 /* Send BD initiator control block */
8918 printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
8919 tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
8921 /* Send BD completion control block */
8922 printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
8924 /* Receive list placement control block */
8925 printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
8926 tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
8927 printk(" RCVLPC_STATSCTRL[%08x]\n",
8928 tr32(RCVLPC_STATSCTRL));
8930 /* Receive data and receive BD initiator control block */
8931 printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
8932 tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
8934 /* Receive data completion control block */
8935 printk("DEBUG: RCVDCC_MODE[%08x]\n",
8938 /* Receive BD initiator control block */
8939 printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
8940 tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
8942 /* Receive BD completion control block */
8943 printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
8944 tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
8946 /* Receive list selector control block */
8947 printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
8948 tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
8950 /* Mbuf cluster free block */
8951 printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
8952 tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
8954 /* Host coalescing control block */
8955 printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
8956 tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
8957 printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
8958 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8959 tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8960 printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
8961 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
8962 tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
8963 printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
8964 tr32(HOSTCC_STATS_BLK_NIC_ADDR));
8965 printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
8966 tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
8968 /* Memory arbiter control block */
8969 printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
8970 tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
8972 /* Buffer manager control block */
8973 printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
8974 tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
8975 printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
8976 tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
8977 printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
8978 "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
8979 tr32(BUFMGR_DMA_DESC_POOL_ADDR),
8980 tr32(BUFMGR_DMA_DESC_POOL_SIZE));
8982 /* Read DMA control block */
8983 printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
8984 tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
8986 /* Write DMA control block */
8987 printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
8988 tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
8990 /* DMA completion block */
8991 printk("DEBUG: DMAC_MODE[%08x]\n",
8995 printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
8996 tr32(GRC_MODE), tr32(GRC_MISC_CFG));
8997 printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
8998 tr32(GRC_LOCAL_CTRL));
9001 printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
9002 tr32(RCVDBDI_JUMBO_BD + 0x0),
9003 tr32(RCVDBDI_JUMBO_BD + 0x4),
9004 tr32(RCVDBDI_JUMBO_BD + 0x8),
9005 tr32(RCVDBDI_JUMBO_BD + 0xc));
9006 printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
9007 tr32(RCVDBDI_STD_BD + 0x0),
9008 tr32(RCVDBDI_STD_BD + 0x4),
9009 tr32(RCVDBDI_STD_BD + 0x8),
9010 tr32(RCVDBDI_STD_BD + 0xc));
9011 printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
9012 tr32(RCVDBDI_MINI_BD + 0x0),
9013 tr32(RCVDBDI_MINI_BD + 0x4),
9014 tr32(RCVDBDI_MINI_BD + 0x8),
9015 tr32(RCVDBDI_MINI_BD + 0xc));
9017 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
9018 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
9019 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
9020 tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
9021 printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
9022 val32, val32_2, val32_3, val32_4);
9024 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
9025 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
9026 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
9027 tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
9028 printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
9029 val32, val32_2, val32_3, val32_4);
9031 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
9032 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
9033 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
9034 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
9035 tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
9036 printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
9037 val32, val32_2, val32_3, val32_4, val32_5);
9039 /* SW status block */
9041 "Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
9044 sblk->rx_jumbo_consumer,
9046 sblk->rx_mini_consumer,
9047 sblk->idx[0].rx_producer,
9048 sblk->idx[0].tx_consumer);
9050 /* SW statistics block */
9051 printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
9052 ((u32 *)tp->hw_stats)[0],
9053 ((u32 *)tp->hw_stats)[1],
9054 ((u32 *)tp->hw_stats)[2],
9055 ((u32 *)tp->hw_stats)[3]);
9058 printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
9059 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
9060 tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
9061 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
9062 tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
9064 /* NIC side send descriptors. */
9065 for (i = 0; i < 6; i++) {
9068 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
9069 + (i * sizeof(struct tg3_tx_buffer_desc));
9070 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
9072 readl(txd + 0x0), readl(txd + 0x4),
9073 readl(txd + 0x8), readl(txd + 0xc));
9076 /* NIC side RX descriptors. */
9077 for (i = 0; i < 6; i++) {
9080 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
9081 + (i * sizeof(struct tg3_rx_buffer_desc));
9082 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
9084 readl(rxd + 0x0), readl(rxd + 0x4),
9085 readl(rxd + 0x8), readl(rxd + 0xc));
9086 rxd += (4 * sizeof(u32));
9087 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
9089 readl(rxd + 0x0), readl(rxd + 0x4),
9090 readl(rxd + 0x8), readl(rxd + 0xc));
9093 for (i = 0; i < 6; i++) {
9096 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
9097 + (i * sizeof(struct tg3_rx_buffer_desc));
9098 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
9100 readl(rxd + 0x0), readl(rxd + 0x4),
9101 readl(rxd + 0x8), readl(rxd + 0xc));
9102 rxd += (4 * sizeof(u32));
9103 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
9105 readl(rxd + 0x0), readl(rxd + 0x4),
9106 readl(rxd + 0x8), readl(rxd + 0xc));
9111 static struct net_device_stats *tg3_get_stats(struct net_device *);
9112 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
9114 static int tg3_close(struct net_device *dev)
9117 struct tg3 *tp = netdev_priv(dev);
9119 tg3_napi_disable(tp);
9120 cancel_work_sync(&tp->reset_task);
9122 netif_tx_stop_all_queues(dev);
9124 del_timer_sync(&tp->timer);
9128 tg3_full_lock(tp, 1);
9133 tg3_disable_ints(tp);
9135 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9137 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
9139 tg3_full_unlock(tp);
9141 for (i = tp->irq_cnt - 1; i >= 0; i--) {
9142 struct tg3_napi *tnapi = &tp->napi[i];
9143 free_irq(tnapi->irq_vec, tnapi);
9148 memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
9149 sizeof(tp->net_stats_prev));
9150 memcpy(&tp->estats_prev, tg3_get_estats(tp),
9151 sizeof(tp->estats_prev));
9153 tg3_free_consistent(tp);
9155 tg3_set_power_state(tp, PCI_D3hot);
9157 netif_carrier_off(tp->dev);
9162 static inline unsigned long get_stat64(tg3_stat64_t *val)
9166 #if (BITS_PER_LONG == 32)
9169 ret = ((u64)val->high << 32) | ((u64)val->low);
9174 static inline u64 get_estat64(tg3_stat64_t *val)
9176 return ((u64)val->high << 32) | ((u64)val->low);
9179 static unsigned long calc_crc_errors(struct tg3 *tp)
9181 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9183 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
9184 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
9185 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
9188 spin_lock_bh(&tp->lock);
9189 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
9190 tg3_writephy(tp, MII_TG3_TEST1,
9191 val | MII_TG3_TEST1_CRC_EN);
9192 tg3_readphy(tp, 0x14, &val);
9195 spin_unlock_bh(&tp->lock);
9197 tp->phy_crc_errors += val;
9199 return tp->phy_crc_errors;
9202 return get_stat64(&hw_stats->rx_fcs_errors);
9205 #define ESTAT_ADD(member) \
9206 estats->member = old_estats->member + \
9207 get_estat64(&hw_stats->member)
9209 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
9211 struct tg3_ethtool_stats *estats = &tp->estats;
9212 struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
9213 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9218 ESTAT_ADD(rx_octets);
9219 ESTAT_ADD(rx_fragments);
9220 ESTAT_ADD(rx_ucast_packets);
9221 ESTAT_ADD(rx_mcast_packets);
9222 ESTAT_ADD(rx_bcast_packets);
9223 ESTAT_ADD(rx_fcs_errors);
9224 ESTAT_ADD(rx_align_errors);
9225 ESTAT_ADD(rx_xon_pause_rcvd);
9226 ESTAT_ADD(rx_xoff_pause_rcvd);
9227 ESTAT_ADD(rx_mac_ctrl_rcvd);
9228 ESTAT_ADD(rx_xoff_entered);
9229 ESTAT_ADD(rx_frame_too_long_errors);
9230 ESTAT_ADD(rx_jabbers);
9231 ESTAT_ADD(rx_undersize_packets);
9232 ESTAT_ADD(rx_in_length_errors);
9233 ESTAT_ADD(rx_out_length_errors);
9234 ESTAT_ADD(rx_64_or_less_octet_packets);
9235 ESTAT_ADD(rx_65_to_127_octet_packets);
9236 ESTAT_ADD(rx_128_to_255_octet_packets);
9237 ESTAT_ADD(rx_256_to_511_octet_packets);
9238 ESTAT_ADD(rx_512_to_1023_octet_packets);
9239 ESTAT_ADD(rx_1024_to_1522_octet_packets);
9240 ESTAT_ADD(rx_1523_to_2047_octet_packets);
9241 ESTAT_ADD(rx_2048_to_4095_octet_packets);
9242 ESTAT_ADD(rx_4096_to_8191_octet_packets);
9243 ESTAT_ADD(rx_8192_to_9022_octet_packets);
9245 ESTAT_ADD(tx_octets);
9246 ESTAT_ADD(tx_collisions);
9247 ESTAT_ADD(tx_xon_sent);
9248 ESTAT_ADD(tx_xoff_sent);
9249 ESTAT_ADD(tx_flow_control);
9250 ESTAT_ADD(tx_mac_errors);
9251 ESTAT_ADD(tx_single_collisions);
9252 ESTAT_ADD(tx_mult_collisions);
9253 ESTAT_ADD(tx_deferred);
9254 ESTAT_ADD(tx_excessive_collisions);
9255 ESTAT_ADD(tx_late_collisions);
9256 ESTAT_ADD(tx_collide_2times);
9257 ESTAT_ADD(tx_collide_3times);
9258 ESTAT_ADD(tx_collide_4times);
9259 ESTAT_ADD(tx_collide_5times);
9260 ESTAT_ADD(tx_collide_6times);
9261 ESTAT_ADD(tx_collide_7times);
9262 ESTAT_ADD(tx_collide_8times);
9263 ESTAT_ADD(tx_collide_9times);
9264 ESTAT_ADD(tx_collide_10times);
9265 ESTAT_ADD(tx_collide_11times);
9266 ESTAT_ADD(tx_collide_12times);
9267 ESTAT_ADD(tx_collide_13times);
9268 ESTAT_ADD(tx_collide_14times);
9269 ESTAT_ADD(tx_collide_15times);
9270 ESTAT_ADD(tx_ucast_packets);
9271 ESTAT_ADD(tx_mcast_packets);
9272 ESTAT_ADD(tx_bcast_packets);
9273 ESTAT_ADD(tx_carrier_sense_errors);
9274 ESTAT_ADD(tx_discards);
9275 ESTAT_ADD(tx_errors);
9277 ESTAT_ADD(dma_writeq_full);
9278 ESTAT_ADD(dma_write_prioq_full);
9279 ESTAT_ADD(rxbds_empty);
9280 ESTAT_ADD(rx_discards);
9281 ESTAT_ADD(rx_errors);
9282 ESTAT_ADD(rx_threshold_hit);
9284 ESTAT_ADD(dma_readq_full);
9285 ESTAT_ADD(dma_read_prioq_full);
9286 ESTAT_ADD(tx_comp_queue_full);
9288 ESTAT_ADD(ring_set_send_prod_index);
9289 ESTAT_ADD(ring_status_update);
9290 ESTAT_ADD(nic_irqs);
9291 ESTAT_ADD(nic_avoided_irqs);
9292 ESTAT_ADD(nic_tx_threshold_hit);
9297 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
9299 struct tg3 *tp = netdev_priv(dev);
9300 struct net_device_stats *stats = &tp->net_stats;
9301 struct net_device_stats *old_stats = &tp->net_stats_prev;
9302 struct tg3_hw_stats *hw_stats = tp->hw_stats;
9307 stats->rx_packets = old_stats->rx_packets +
9308 get_stat64(&hw_stats->rx_ucast_packets) +
9309 get_stat64(&hw_stats->rx_mcast_packets) +
9310 get_stat64(&hw_stats->rx_bcast_packets);
9312 stats->tx_packets = old_stats->tx_packets +
9313 get_stat64(&hw_stats->tx_ucast_packets) +
9314 get_stat64(&hw_stats->tx_mcast_packets) +
9315 get_stat64(&hw_stats->tx_bcast_packets);
9317 stats->rx_bytes = old_stats->rx_bytes +
9318 get_stat64(&hw_stats->rx_octets);
9319 stats->tx_bytes = old_stats->tx_bytes +
9320 get_stat64(&hw_stats->tx_octets);
9322 stats->rx_errors = old_stats->rx_errors +
9323 get_stat64(&hw_stats->rx_errors);
9324 stats->tx_errors = old_stats->tx_errors +
9325 get_stat64(&hw_stats->tx_errors) +
9326 get_stat64(&hw_stats->tx_mac_errors) +
9327 get_stat64(&hw_stats->tx_carrier_sense_errors) +
9328 get_stat64(&hw_stats->tx_discards);
9330 stats->multicast = old_stats->multicast +
9331 get_stat64(&hw_stats->rx_mcast_packets);
9332 stats->collisions = old_stats->collisions +
9333 get_stat64(&hw_stats->tx_collisions);
9335 stats->rx_length_errors = old_stats->rx_length_errors +
9336 get_stat64(&hw_stats->rx_frame_too_long_errors) +
9337 get_stat64(&hw_stats->rx_undersize_packets);
9339 stats->rx_over_errors = old_stats->rx_over_errors +
9340 get_stat64(&hw_stats->rxbds_empty);
9341 stats->rx_frame_errors = old_stats->rx_frame_errors +
9342 get_stat64(&hw_stats->rx_align_errors);
9343 stats->tx_aborted_errors = old_stats->tx_aborted_errors +
9344 get_stat64(&hw_stats->tx_discards);
9345 stats->tx_carrier_errors = old_stats->tx_carrier_errors +
9346 get_stat64(&hw_stats->tx_carrier_sense_errors);
9348 stats->rx_crc_errors = old_stats->rx_crc_errors +
9349 calc_crc_errors(tp);
9351 stats->rx_missed_errors = old_stats->rx_missed_errors +
9352 get_stat64(&hw_stats->rx_discards);
9357 static inline u32 calc_crc(unsigned char *buf, int len)
9365 for (j = 0; j < len; j++) {
9368 for (k = 0; k < 8; k++) {
9382 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
9384 /* accept or reject all multicast frames */
9385 tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
9386 tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
9387 tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
9388 tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
9391 static void __tg3_set_rx_mode(struct net_device *dev)
9393 struct tg3 *tp = netdev_priv(dev);
9396 rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
9397 RX_MODE_KEEP_VLAN_TAG);
9399 /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
9402 #if TG3_VLAN_TAG_USED
9404 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9405 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9407 /* By definition, VLAN is disabled always in this
9410 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
9411 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
9414 if (dev->flags & IFF_PROMISC) {
9415 /* Promiscuous mode. */
9416 rx_mode |= RX_MODE_PROMISC;
9417 } else if (dev->flags & IFF_ALLMULTI) {
9418 /* Accept all multicast. */
9419 tg3_set_multi (tp, 1);
9420 } else if (dev->mc_count < 1) {
9421 /* Reject all multicast. */
9422 tg3_set_multi (tp, 0);
9424 /* Accept one or more multicast(s). */
9425 struct dev_mc_list *mclist;
9427 u32 mc_filter[4] = { 0, };
9432 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
9433 i++, mclist = mclist->next) {
9435 crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
9437 regidx = (bit & 0x60) >> 5;
9439 mc_filter[regidx] |= (1 << bit);
9442 tw32(MAC_HASH_REG_0, mc_filter[0]);
9443 tw32(MAC_HASH_REG_1, mc_filter[1]);
9444 tw32(MAC_HASH_REG_2, mc_filter[2]);
9445 tw32(MAC_HASH_REG_3, mc_filter[3]);
9448 if (rx_mode != tp->rx_mode) {
9449 tp->rx_mode = rx_mode;
9450 tw32_f(MAC_RX_MODE, rx_mode);
9455 static void tg3_set_rx_mode(struct net_device *dev)
9457 struct tg3 *tp = netdev_priv(dev);
9459 if (!netif_running(dev))
9462 tg3_full_lock(tp, 0);
9463 __tg3_set_rx_mode(dev);
9464 tg3_full_unlock(tp);
9467 #define TG3_REGDUMP_LEN (32 * 1024)
9469 static int tg3_get_regs_len(struct net_device *dev)
9471 return TG3_REGDUMP_LEN;
9474 static void tg3_get_regs(struct net_device *dev,
9475 struct ethtool_regs *regs, void *_p)
9478 struct tg3 *tp = netdev_priv(dev);
9484 memset(p, 0, TG3_REGDUMP_LEN);
9486 if (tp->link_config.phy_is_low_power)
9489 tg3_full_lock(tp, 0);
9491 #define __GET_REG32(reg) (*(p)++ = tr32(reg))
9492 #define GET_REG32_LOOP(base,len) \
9493 do { p = (u32 *)(orig_p + (base)); \
9494 for (i = 0; i < len; i += 4) \
9495 __GET_REG32((base) + i); \
9497 #define GET_REG32_1(reg) \
9498 do { p = (u32 *)(orig_p + (reg)); \
9499 __GET_REG32((reg)); \
9502 GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
9503 GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
9504 GET_REG32_LOOP(MAC_MODE, 0x4f0);
9505 GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
9506 GET_REG32_1(SNDDATAC_MODE);
9507 GET_REG32_LOOP(SNDBDS_MODE, 0x80);
9508 GET_REG32_LOOP(SNDBDI_MODE, 0x48);
9509 GET_REG32_1(SNDBDC_MODE);
9510 GET_REG32_LOOP(RCVLPC_MODE, 0x20);
9511 GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
9512 GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
9513 GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
9514 GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
9515 GET_REG32_1(RCVDCC_MODE);
9516 GET_REG32_LOOP(RCVBDI_MODE, 0x20);
9517 GET_REG32_LOOP(RCVCC_MODE, 0x14);
9518 GET_REG32_LOOP(RCVLSC_MODE, 0x08);
9519 GET_REG32_1(MBFREE_MODE);
9520 GET_REG32_LOOP(HOSTCC_MODE, 0x100);
9521 GET_REG32_LOOP(MEMARB_MODE, 0x10);
9522 GET_REG32_LOOP(BUFMGR_MODE, 0x58);
9523 GET_REG32_LOOP(RDMAC_MODE, 0x08);
9524 GET_REG32_LOOP(WDMAC_MODE, 0x08);
9525 GET_REG32_1(RX_CPU_MODE);
9526 GET_REG32_1(RX_CPU_STATE);
9527 GET_REG32_1(RX_CPU_PGMCTR);
9528 GET_REG32_1(RX_CPU_HWBKPT);
9529 GET_REG32_1(TX_CPU_MODE);
9530 GET_REG32_1(TX_CPU_STATE);
9531 GET_REG32_1(TX_CPU_PGMCTR);
9532 GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
9533 GET_REG32_LOOP(FTQ_RESET, 0x120);
9534 GET_REG32_LOOP(MSGINT_MODE, 0x0c);
9535 GET_REG32_1(DMAC_MODE);
9536 GET_REG32_LOOP(GRC_MODE, 0x4c);
9537 if (tp->tg3_flags & TG3_FLAG_NVRAM)
9538 GET_REG32_LOOP(NVRAM_CMD, 0x24);
9541 #undef GET_REG32_LOOP
9544 tg3_full_unlock(tp);
9547 static int tg3_get_eeprom_len(struct net_device *dev)
9549 struct tg3 *tp = netdev_priv(dev);
9551 return tp->nvram_size;
9554 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9556 struct tg3 *tp = netdev_priv(dev);
9559 u32 i, offset, len, b_offset, b_count;
9562 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
9565 if (tp->link_config.phy_is_low_power)
9568 offset = eeprom->offset;
9572 eeprom->magic = TG3_EEPROM_MAGIC;
9575 /* adjustments to start on required 4 byte boundary */
9576 b_offset = offset & 3;
9577 b_count = 4 - b_offset;
9578 if (b_count > len) {
9579 /* i.e. offset=1 len=2 */
9582 ret = tg3_nvram_read_be32(tp, offset-b_offset, &val);
9585 memcpy(data, ((char*)&val) + b_offset, b_count);
9588 eeprom->len += b_count;
9591 /* read bytes upto the last 4 byte boundary */
9592 pd = &data[eeprom->len];
9593 for (i = 0; i < (len - (len & 3)); i += 4) {
9594 ret = tg3_nvram_read_be32(tp, offset + i, &val);
9599 memcpy(pd + i, &val, 4);
9604 /* read last bytes not ending on 4 byte boundary */
9605 pd = &data[eeprom->len];
9607 b_offset = offset + len - b_count;
9608 ret = tg3_nvram_read_be32(tp, b_offset, &val);
9611 memcpy(pd, &val, b_count);
9612 eeprom->len += b_count;
9617 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
9619 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
9621 struct tg3 *tp = netdev_priv(dev);
9623 u32 offset, len, b_offset, odd_len;
9627 if (tp->link_config.phy_is_low_power)
9630 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
9631 eeprom->magic != TG3_EEPROM_MAGIC)
9634 offset = eeprom->offset;
9637 if ((b_offset = (offset & 3))) {
9638 /* adjustments to start on required 4 byte boundary */
9639 ret = tg3_nvram_read_be32(tp, offset-b_offset, &start);
9650 /* adjustments to end on required 4 byte boundary */
9652 len = (len + 3) & ~3;
9653 ret = tg3_nvram_read_be32(tp, offset+len-4, &end);
9659 if (b_offset || odd_len) {
9660 buf = kmalloc(len, GFP_KERNEL);
9664 memcpy(buf, &start, 4);
9666 memcpy(buf+len-4, &end, 4);
9667 memcpy(buf + b_offset, data, eeprom->len);
9670 ret = tg3_nvram_write_block(tp, offset, len, buf);
9678 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9680 struct tg3 *tp = netdev_priv(dev);
9682 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9683 struct phy_device *phydev;
9684 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9686 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9687 return phy_ethtool_gset(phydev, cmd);
9690 cmd->supported = (SUPPORTED_Autoneg);
9692 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
9693 cmd->supported |= (SUPPORTED_1000baseT_Half |
9694 SUPPORTED_1000baseT_Full);
9696 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
9697 cmd->supported |= (SUPPORTED_100baseT_Half |
9698 SUPPORTED_100baseT_Full |
9699 SUPPORTED_10baseT_Half |
9700 SUPPORTED_10baseT_Full |
9702 cmd->port = PORT_TP;
9704 cmd->supported |= SUPPORTED_FIBRE;
9705 cmd->port = PORT_FIBRE;
9708 cmd->advertising = tp->link_config.advertising;
9709 if (netif_running(dev)) {
9710 cmd->speed = tp->link_config.active_speed;
9711 cmd->duplex = tp->link_config.active_duplex;
9713 cmd->phy_address = tp->phy_addr;
9714 cmd->transceiver = XCVR_INTERNAL;
9715 cmd->autoneg = tp->link_config.autoneg;
9721 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
9723 struct tg3 *tp = netdev_priv(dev);
9725 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9726 struct phy_device *phydev;
9727 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9729 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
9730 return phy_ethtool_sset(phydev, cmd);
9733 if (cmd->autoneg != AUTONEG_ENABLE &&
9734 cmd->autoneg != AUTONEG_DISABLE)
9737 if (cmd->autoneg == AUTONEG_DISABLE &&
9738 cmd->duplex != DUPLEX_FULL &&
9739 cmd->duplex != DUPLEX_HALF)
9742 if (cmd->autoneg == AUTONEG_ENABLE) {
9743 u32 mask = ADVERTISED_Autoneg |
9745 ADVERTISED_Asym_Pause;
9747 if (!(tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
9748 mask |= ADVERTISED_1000baseT_Half |
9749 ADVERTISED_1000baseT_Full;
9751 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
9752 mask |= ADVERTISED_100baseT_Half |
9753 ADVERTISED_100baseT_Full |
9754 ADVERTISED_10baseT_Half |
9755 ADVERTISED_10baseT_Full |
9758 mask |= ADVERTISED_FIBRE;
9760 if (cmd->advertising & ~mask)
9763 mask &= (ADVERTISED_1000baseT_Half |
9764 ADVERTISED_1000baseT_Full |
9765 ADVERTISED_100baseT_Half |
9766 ADVERTISED_100baseT_Full |
9767 ADVERTISED_10baseT_Half |
9768 ADVERTISED_10baseT_Full);
9770 cmd->advertising &= mask;
9772 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
9773 if (cmd->speed != SPEED_1000)
9776 if (cmd->duplex != DUPLEX_FULL)
9779 if (cmd->speed != SPEED_100 &&
9780 cmd->speed != SPEED_10)
9785 tg3_full_lock(tp, 0);
9787 tp->link_config.autoneg = cmd->autoneg;
9788 if (cmd->autoneg == AUTONEG_ENABLE) {
9789 tp->link_config.advertising = (cmd->advertising |
9790 ADVERTISED_Autoneg);
9791 tp->link_config.speed = SPEED_INVALID;
9792 tp->link_config.duplex = DUPLEX_INVALID;
9794 tp->link_config.advertising = 0;
9795 tp->link_config.speed = cmd->speed;
9796 tp->link_config.duplex = cmd->duplex;
9799 tp->link_config.orig_speed = tp->link_config.speed;
9800 tp->link_config.orig_duplex = tp->link_config.duplex;
9801 tp->link_config.orig_autoneg = tp->link_config.autoneg;
9803 if (netif_running(dev))
9804 tg3_setup_phy(tp, 1);
9806 tg3_full_unlock(tp);
9811 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
9813 struct tg3 *tp = netdev_priv(dev);
9815 strcpy(info->driver, DRV_MODULE_NAME);
9816 strcpy(info->version, DRV_MODULE_VERSION);
9817 strcpy(info->fw_version, tp->fw_ver);
9818 strcpy(info->bus_info, pci_name(tp->pdev));
9821 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9823 struct tg3 *tp = netdev_priv(dev);
9825 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
9826 device_can_wakeup(&tp->pdev->dev))
9827 wol->supported = WAKE_MAGIC;
9831 if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
9832 device_can_wakeup(&tp->pdev->dev))
9833 wol->wolopts = WAKE_MAGIC;
9834 memset(&wol->sopass, 0, sizeof(wol->sopass));
9837 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
9839 struct tg3 *tp = netdev_priv(dev);
9840 struct device *dp = &tp->pdev->dev;
9842 if (wol->wolopts & ~WAKE_MAGIC)
9844 if ((wol->wolopts & WAKE_MAGIC) &&
9845 !((tp->tg3_flags & TG3_FLAG_WOL_CAP) && device_can_wakeup(dp)))
9848 spin_lock_bh(&tp->lock);
9849 if (wol->wolopts & WAKE_MAGIC) {
9850 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
9851 device_set_wakeup_enable(dp, true);
9853 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
9854 device_set_wakeup_enable(dp, false);
9856 spin_unlock_bh(&tp->lock);
9861 static u32 tg3_get_msglevel(struct net_device *dev)
9863 struct tg3 *tp = netdev_priv(dev);
9864 return tp->msg_enable;
9867 static void tg3_set_msglevel(struct net_device *dev, u32 value)
9869 struct tg3 *tp = netdev_priv(dev);
9870 tp->msg_enable = value;
9873 static int tg3_set_tso(struct net_device *dev, u32 value)
9875 struct tg3 *tp = netdev_priv(dev);
9877 if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
9882 if ((dev->features & NETIF_F_IPV6_CSUM) &&
9883 ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
9884 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3))) {
9886 dev->features |= NETIF_F_TSO6;
9887 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
9888 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
9889 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
9890 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
9891 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
9892 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
9893 dev->features |= NETIF_F_TSO_ECN;
9895 dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
9897 return ethtool_op_set_tso(dev, value);
9900 static int tg3_nway_reset(struct net_device *dev)
9902 struct tg3 *tp = netdev_priv(dev);
9905 if (!netif_running(dev))
9908 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9911 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
9912 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
9914 r = phy_start_aneg(tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR]);
9918 spin_lock_bh(&tp->lock);
9920 tg3_readphy(tp, MII_BMCR, &bmcr);
9921 if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
9922 ((bmcr & BMCR_ANENABLE) ||
9923 (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
9924 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
9928 spin_unlock_bh(&tp->lock);
9934 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9936 struct tg3 *tp = netdev_priv(dev);
9938 ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
9939 ering->rx_mini_max_pending = 0;
9940 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9941 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
9943 ering->rx_jumbo_max_pending = 0;
9945 ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
9947 ering->rx_pending = tp->rx_pending;
9948 ering->rx_mini_pending = 0;
9949 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
9950 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
9952 ering->rx_jumbo_pending = 0;
9954 ering->tx_pending = tp->napi[0].tx_pending;
9957 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
9959 struct tg3 *tp = netdev_priv(dev);
9960 int i, irq_sync = 0, err = 0;
9962 if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
9963 (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
9964 (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
9965 (ering->tx_pending <= MAX_SKB_FRAGS) ||
9966 ((tp->tg3_flags2 & TG3_FLG2_TSO_BUG) &&
9967 (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
9970 if (netif_running(dev)) {
9976 tg3_full_lock(tp, irq_sync);
9978 tp->rx_pending = ering->rx_pending;
9980 if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
9981 tp->rx_pending > 63)
9982 tp->rx_pending = 63;
9983 tp->rx_jumbo_pending = ering->rx_jumbo_pending;
9985 for (i = 0; i < TG3_IRQ_MAX_VECS; i++)
9986 tp->napi[i].tx_pending = ering->tx_pending;
9988 if (netif_running(dev)) {
9989 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9990 err = tg3_restart_hw(tp, 1);
9992 tg3_netif_start(tp);
9995 tg3_full_unlock(tp);
9997 if (irq_sync && !err)
10003 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10005 struct tg3 *tp = netdev_priv(dev);
10007 epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
10009 if (tp->link_config.active_flowctrl & FLOW_CTRL_RX)
10010 epause->rx_pause = 1;
10012 epause->rx_pause = 0;
10014 if (tp->link_config.active_flowctrl & FLOW_CTRL_TX)
10015 epause->tx_pause = 1;
10017 epause->tx_pause = 0;
10020 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
10022 struct tg3 *tp = netdev_priv(dev);
10025 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
10026 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
10029 if (epause->autoneg) {
10031 struct phy_device *phydev;
10033 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
10035 if (epause->rx_pause) {
10036 if (epause->tx_pause)
10037 newadv = ADVERTISED_Pause;
10039 newadv = ADVERTISED_Pause |
10040 ADVERTISED_Asym_Pause;
10041 } else if (epause->tx_pause) {
10042 newadv = ADVERTISED_Asym_Pause;
10046 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
10047 u32 oldadv = phydev->advertising &
10048 (ADVERTISED_Pause |
10049 ADVERTISED_Asym_Pause);
10050 if (oldadv != newadv) {
10051 phydev->advertising &=
10052 ~(ADVERTISED_Pause |
10053 ADVERTISED_Asym_Pause);
10054 phydev->advertising |= newadv;
10055 err = phy_start_aneg(phydev);
10058 tp->link_config.advertising &=
10059 ~(ADVERTISED_Pause |
10060 ADVERTISED_Asym_Pause);
10061 tp->link_config.advertising |= newadv;
10064 if (epause->rx_pause)
10065 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10067 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10069 if (epause->tx_pause)
10070 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10072 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10074 if (netif_running(dev))
10075 tg3_setup_flow_control(tp, 0, 0);
10080 if (netif_running(dev)) {
10081 tg3_netif_stop(tp);
10085 tg3_full_lock(tp, irq_sync);
10087 if (epause->autoneg)
10088 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
10090 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
10091 if (epause->rx_pause)
10092 tp->link_config.flowctrl |= FLOW_CTRL_RX;
10094 tp->link_config.flowctrl &= ~FLOW_CTRL_RX;
10095 if (epause->tx_pause)
10096 tp->link_config.flowctrl |= FLOW_CTRL_TX;
10098 tp->link_config.flowctrl &= ~FLOW_CTRL_TX;
10100 if (netif_running(dev)) {
10101 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
10102 err = tg3_restart_hw(tp, 1);
10104 tg3_netif_start(tp);
10107 tg3_full_unlock(tp);
10113 static u32 tg3_get_rx_csum(struct net_device *dev)
10115 struct tg3 *tp = netdev_priv(dev);
10116 return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
10119 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
10121 struct tg3 *tp = netdev_priv(dev);
10123 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10129 spin_lock_bh(&tp->lock);
10131 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
10133 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
10134 spin_unlock_bh(&tp->lock);
10139 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
10141 struct tg3 *tp = netdev_priv(dev);
10143 if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
10149 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10150 ethtool_op_set_tx_ipv6_csum(dev, data);
10152 ethtool_op_set_tx_csum(dev, data);
10157 static int tg3_get_sset_count (struct net_device *dev, int sset)
10161 return TG3_NUM_TEST;
10163 return TG3_NUM_STATS;
10165 return -EOPNOTSUPP;
10169 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
10171 switch (stringset) {
10173 memcpy(buf, ðtool_stats_keys, sizeof(ethtool_stats_keys));
10176 memcpy(buf, ðtool_test_keys, sizeof(ethtool_test_keys));
10179 WARN_ON(1); /* we need a WARN() */
10184 static int tg3_phys_id(struct net_device *dev, u32 data)
10186 struct tg3 *tp = netdev_priv(dev);
10189 if (!netif_running(tp->dev))
10193 data = UINT_MAX / 2;
10195 for (i = 0; i < (data * 2); i++) {
10197 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10198 LED_CTRL_1000MBPS_ON |
10199 LED_CTRL_100MBPS_ON |
10200 LED_CTRL_10MBPS_ON |
10201 LED_CTRL_TRAFFIC_OVERRIDE |
10202 LED_CTRL_TRAFFIC_BLINK |
10203 LED_CTRL_TRAFFIC_LED);
10206 tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
10207 LED_CTRL_TRAFFIC_OVERRIDE);
10209 if (msleep_interruptible(500))
10212 tw32(MAC_LED_CTRL, tp->led_ctrl);
10216 static void tg3_get_ethtool_stats (struct net_device *dev,
10217 struct ethtool_stats *estats, u64 *tmp_stats)
10219 struct tg3 *tp = netdev_priv(dev);
10220 memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
10223 #define NVRAM_TEST_SIZE 0x100
10224 #define NVRAM_SELFBOOT_FORMAT1_0_SIZE 0x14
10225 #define NVRAM_SELFBOOT_FORMAT1_2_SIZE 0x18
10226 #define NVRAM_SELFBOOT_FORMAT1_3_SIZE 0x1c
10227 #define NVRAM_SELFBOOT_HW_SIZE 0x20
10228 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
10230 static int tg3_test_nvram(struct tg3 *tp)
10234 int i, j, k, err = 0, size;
10236 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM)
10239 if (tg3_nvram_read(tp, 0, &magic) != 0)
10242 if (magic == TG3_EEPROM_MAGIC)
10243 size = NVRAM_TEST_SIZE;
10244 else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
10245 if ((magic & TG3_EEPROM_SB_FORMAT_MASK) ==
10246 TG3_EEPROM_SB_FORMAT_1) {
10247 switch (magic & TG3_EEPROM_SB_REVISION_MASK) {
10248 case TG3_EEPROM_SB_REVISION_0:
10249 size = NVRAM_SELFBOOT_FORMAT1_0_SIZE;
10251 case TG3_EEPROM_SB_REVISION_2:
10252 size = NVRAM_SELFBOOT_FORMAT1_2_SIZE;
10254 case TG3_EEPROM_SB_REVISION_3:
10255 size = NVRAM_SELFBOOT_FORMAT1_3_SIZE;
10262 } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
10263 size = NVRAM_SELFBOOT_HW_SIZE;
10267 buf = kmalloc(size, GFP_KERNEL);
10272 for (i = 0, j = 0; i < size; i += 4, j++) {
10273 err = tg3_nvram_read_be32(tp, i, &buf[j]);
10280 /* Selfboot format */
10281 magic = be32_to_cpu(buf[0]);
10282 if ((magic & TG3_EEPROM_MAGIC_FW_MSK) ==
10283 TG3_EEPROM_MAGIC_FW) {
10284 u8 *buf8 = (u8 *) buf, csum8 = 0;
10286 if ((magic & TG3_EEPROM_SB_REVISION_MASK) ==
10287 TG3_EEPROM_SB_REVISION_2) {
10288 /* For rev 2, the csum doesn't include the MBA. */
10289 for (i = 0; i < TG3_EEPROM_SB_F1R2_MBA_OFF; i++)
10291 for (i = TG3_EEPROM_SB_F1R2_MBA_OFF + 4; i < size; i++)
10294 for (i = 0; i < size; i++)
10307 if ((magic & TG3_EEPROM_MAGIC_HW_MSK) ==
10308 TG3_EEPROM_MAGIC_HW) {
10309 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
10310 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
10311 u8 *buf8 = (u8 *) buf;
10313 /* Separate the parity bits and the data bytes. */
10314 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
10315 if ((i == 0) || (i == 8)) {
10319 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
10320 parity[k++] = buf8[i] & msk;
10323 else if (i == 16) {
10327 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
10328 parity[k++] = buf8[i] & msk;
10331 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
10332 parity[k++] = buf8[i] & msk;
10335 data[j++] = buf8[i];
10339 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
10340 u8 hw8 = hweight8(data[i]);
10342 if ((hw8 & 0x1) && parity[i])
10344 else if (!(hw8 & 0x1) && !parity[i])
10351 /* Bootstrap checksum at offset 0x10 */
10352 csum = calc_crc((unsigned char *) buf, 0x10);
10353 if (csum != be32_to_cpu(buf[0x10/4]))
10356 /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
10357 csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
10358 if (csum != be32_to_cpu(buf[0xfc/4]))
10368 #define TG3_SERDES_TIMEOUT_SEC 2
10369 #define TG3_COPPER_TIMEOUT_SEC 6
10371 static int tg3_test_link(struct tg3 *tp)
10375 if (!netif_running(tp->dev))
10378 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10379 max = TG3_SERDES_TIMEOUT_SEC;
10381 max = TG3_COPPER_TIMEOUT_SEC;
10383 for (i = 0; i < max; i++) {
10384 if (netif_carrier_ok(tp->dev))
10387 if (msleep_interruptible(1000))
10394 /* Only test the commonly used registers */
10395 static int tg3_test_registers(struct tg3 *tp)
10397 int i, is_5705, is_5750;
10398 u32 offset, read_mask, write_mask, val, save_val, read_val;
10402 #define TG3_FL_5705 0x1
10403 #define TG3_FL_NOT_5705 0x2
10404 #define TG3_FL_NOT_5788 0x4
10405 #define TG3_FL_NOT_5750 0x8
10409 /* MAC Control Registers */
10410 { MAC_MODE, TG3_FL_NOT_5705,
10411 0x00000000, 0x00ef6f8c },
10412 { MAC_MODE, TG3_FL_5705,
10413 0x00000000, 0x01ef6b8c },
10414 { MAC_STATUS, TG3_FL_NOT_5705,
10415 0x03800107, 0x00000000 },
10416 { MAC_STATUS, TG3_FL_5705,
10417 0x03800100, 0x00000000 },
10418 { MAC_ADDR_0_HIGH, 0x0000,
10419 0x00000000, 0x0000ffff },
10420 { MAC_ADDR_0_LOW, 0x0000,
10421 0x00000000, 0xffffffff },
10422 { MAC_RX_MTU_SIZE, 0x0000,
10423 0x00000000, 0x0000ffff },
10424 { MAC_TX_MODE, 0x0000,
10425 0x00000000, 0x00000070 },
10426 { MAC_TX_LENGTHS, 0x0000,
10427 0x00000000, 0x00003fff },
10428 { MAC_RX_MODE, TG3_FL_NOT_5705,
10429 0x00000000, 0x000007fc },
10430 { MAC_RX_MODE, TG3_FL_5705,
10431 0x00000000, 0x000007dc },
10432 { MAC_HASH_REG_0, 0x0000,
10433 0x00000000, 0xffffffff },
10434 { MAC_HASH_REG_1, 0x0000,
10435 0x00000000, 0xffffffff },
10436 { MAC_HASH_REG_2, 0x0000,
10437 0x00000000, 0xffffffff },
10438 { MAC_HASH_REG_3, 0x0000,
10439 0x00000000, 0xffffffff },
10441 /* Receive Data and Receive BD Initiator Control Registers. */
10442 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
10443 0x00000000, 0xffffffff },
10444 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
10445 0x00000000, 0xffffffff },
10446 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
10447 0x00000000, 0x00000003 },
10448 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
10449 0x00000000, 0xffffffff },
10450 { RCVDBDI_STD_BD+0, 0x0000,
10451 0x00000000, 0xffffffff },
10452 { RCVDBDI_STD_BD+4, 0x0000,
10453 0x00000000, 0xffffffff },
10454 { RCVDBDI_STD_BD+8, 0x0000,
10455 0x00000000, 0xffff0002 },
10456 { RCVDBDI_STD_BD+0xc, 0x0000,
10457 0x00000000, 0xffffffff },
10459 /* Receive BD Initiator Control Registers. */
10460 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
10461 0x00000000, 0xffffffff },
10462 { RCVBDI_STD_THRESH, TG3_FL_5705,
10463 0x00000000, 0x000003ff },
10464 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
10465 0x00000000, 0xffffffff },
10467 /* Host Coalescing Control Registers. */
10468 { HOSTCC_MODE, TG3_FL_NOT_5705,
10469 0x00000000, 0x00000004 },
10470 { HOSTCC_MODE, TG3_FL_5705,
10471 0x00000000, 0x000000f6 },
10472 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
10473 0x00000000, 0xffffffff },
10474 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
10475 0x00000000, 0x000003ff },
10476 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
10477 0x00000000, 0xffffffff },
10478 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
10479 0x00000000, 0x000003ff },
10480 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
10481 0x00000000, 0xffffffff },
10482 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10483 0x00000000, 0x000000ff },
10484 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
10485 0x00000000, 0xffffffff },
10486 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
10487 0x00000000, 0x000000ff },
10488 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
10489 0x00000000, 0xffffffff },
10490 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
10491 0x00000000, 0xffffffff },
10492 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10493 0x00000000, 0xffffffff },
10494 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10495 0x00000000, 0x000000ff },
10496 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
10497 0x00000000, 0xffffffff },
10498 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
10499 0x00000000, 0x000000ff },
10500 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
10501 0x00000000, 0xffffffff },
10502 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
10503 0x00000000, 0xffffffff },
10504 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
10505 0x00000000, 0xffffffff },
10506 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
10507 0x00000000, 0xffffffff },
10508 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
10509 0x00000000, 0xffffffff },
10510 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
10511 0xffffffff, 0x00000000 },
10512 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
10513 0xffffffff, 0x00000000 },
10515 /* Buffer Manager Control Registers. */
10516 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
10517 0x00000000, 0x007fff80 },
10518 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
10519 0x00000000, 0x007fffff },
10520 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
10521 0x00000000, 0x0000003f },
10522 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
10523 0x00000000, 0x000001ff },
10524 { BUFMGR_MB_HIGH_WATER, 0x0000,
10525 0x00000000, 0x000001ff },
10526 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
10527 0xffffffff, 0x00000000 },
10528 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
10529 0xffffffff, 0x00000000 },
10531 /* Mailbox Registers */
10532 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
10533 0x00000000, 0x000001ff },
10534 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
10535 0x00000000, 0x000001ff },
10536 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
10537 0x00000000, 0x000007ff },
10538 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
10539 0x00000000, 0x000001ff },
10541 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
10544 is_5705 = is_5750 = 0;
10545 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10547 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10551 for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
10552 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
10555 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
10558 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10559 (reg_tbl[i].flags & TG3_FL_NOT_5788))
10562 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
10565 offset = (u32) reg_tbl[i].offset;
10566 read_mask = reg_tbl[i].read_mask;
10567 write_mask = reg_tbl[i].write_mask;
10569 /* Save the original register content */
10570 save_val = tr32(offset);
10572 /* Determine the read-only value. */
10573 read_val = save_val & read_mask;
10575 /* Write zero to the register, then make sure the read-only bits
10576 * are not changed and the read/write bits are all zeros.
10580 val = tr32(offset);
10582 /* Test the read-only and read/write bits. */
10583 if (((val & read_mask) != read_val) || (val & write_mask))
10586 /* Write ones to all the bits defined by RdMask and WrMask, then
10587 * make sure the read-only bits are not changed and the
10588 * read/write bits are all ones.
10590 tw32(offset, read_mask | write_mask);
10592 val = tr32(offset);
10594 /* Test the read-only bits. */
10595 if ((val & read_mask) != read_val)
10598 /* Test the read/write bits. */
10599 if ((val & write_mask) != write_mask)
10602 tw32(offset, save_val);
10608 if (netif_msg_hw(tp))
10609 printk(KERN_ERR PFX "Register test failed at offset %x\n",
10611 tw32(offset, save_val);
10615 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
10617 static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
10621 for (i = 0; i < ARRAY_SIZE(test_pattern); i++) {
10622 for (j = 0; j < len; j += 4) {
10625 tg3_write_mem(tp, offset + j, test_pattern[i]);
10626 tg3_read_mem(tp, offset + j, &val);
10627 if (val != test_pattern[i])
10634 static int tg3_test_memory(struct tg3 *tp)
10636 static struct mem_entry {
10639 } mem_tbl_570x[] = {
10640 { 0x00000000, 0x00b50},
10641 { 0x00002000, 0x1c000},
10642 { 0xffffffff, 0x00000}
10643 }, mem_tbl_5705[] = {
10644 { 0x00000100, 0x0000c},
10645 { 0x00000200, 0x00008},
10646 { 0x00004000, 0x00800},
10647 { 0x00006000, 0x01000},
10648 { 0x00008000, 0x02000},
10649 { 0x00010000, 0x0e000},
10650 { 0xffffffff, 0x00000}
10651 }, mem_tbl_5755[] = {
10652 { 0x00000200, 0x00008},
10653 { 0x00004000, 0x00800},
10654 { 0x00006000, 0x00800},
10655 { 0x00008000, 0x02000},
10656 { 0x00010000, 0x0c000},
10657 { 0xffffffff, 0x00000}
10658 }, mem_tbl_5906[] = {
10659 { 0x00000200, 0x00008},
10660 { 0x00004000, 0x00400},
10661 { 0x00006000, 0x00400},
10662 { 0x00008000, 0x01000},
10663 { 0x00010000, 0x01000},
10664 { 0xffffffff, 0x00000}
10665 }, mem_tbl_5717[] = {
10666 { 0x00000200, 0x00008},
10667 { 0x00010000, 0x0a000},
10668 { 0x00020000, 0x13c00},
10669 { 0xffffffff, 0x00000}
10670 }, mem_tbl_57765[] = {
10671 { 0x00000200, 0x00008},
10672 { 0x00004000, 0x00800},
10673 { 0x00006000, 0x09800},
10674 { 0x00010000, 0x0a000},
10675 { 0xffffffff, 0x00000}
10677 struct mem_entry *mem_tbl;
10681 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
10682 mem_tbl = mem_tbl_5717;
10683 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
10684 mem_tbl = mem_tbl_57765;
10685 else if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
10686 mem_tbl = mem_tbl_5755;
10687 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10688 mem_tbl = mem_tbl_5906;
10689 else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
10690 mem_tbl = mem_tbl_5705;
10692 mem_tbl = mem_tbl_570x;
10694 for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
10695 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
10696 mem_tbl[i].len)) != 0)
10703 #define TG3_MAC_LOOPBACK 0
10704 #define TG3_PHY_LOOPBACK 1
10706 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
10708 u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
10709 u32 desc_idx, coal_now;
10710 struct sk_buff *skb, *rx_skb;
10713 int num_pkts, tx_len, rx_len, i, err;
10714 struct tg3_rx_buffer_desc *desc;
10715 struct tg3_napi *tnapi, *rnapi;
10716 struct tg3_rx_prodring_set *tpr = &tp->prodring[0];
10718 if (tp->irq_cnt > 1) {
10719 tnapi = &tp->napi[1];
10720 rnapi = &tp->napi[1];
10722 tnapi = &tp->napi[0];
10723 rnapi = &tp->napi[0];
10725 coal_now = tnapi->coal_now | rnapi->coal_now;
10727 if (loopback_mode == TG3_MAC_LOOPBACK) {
10728 /* HW errata - mac loopback fails in some cases on 5780.
10729 * Normal traffic and PHY loopback are not affected by
10732 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
10735 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
10736 MAC_MODE_PORT_INT_LPBACK;
10737 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10738 mac_mode |= MAC_MODE_LINK_POLARITY;
10739 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10740 mac_mode |= MAC_MODE_PORT_MODE_MII;
10742 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10743 tw32(MAC_MODE, mac_mode);
10744 } else if (loopback_mode == TG3_PHY_LOOPBACK) {
10747 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10748 tg3_phy_fet_toggle_apd(tp, false);
10749 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
10751 val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
10753 tg3_phy_toggle_automdix(tp, 0);
10755 tg3_writephy(tp, MII_BMCR, val);
10758 mac_mode = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
10759 if (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) {
10760 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10761 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x1800);
10762 mac_mode |= MAC_MODE_PORT_MODE_MII;
10764 mac_mode |= MAC_MODE_PORT_MODE_GMII;
10766 /* reset to prevent losing 1st rx packet intermittently */
10767 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
10768 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
10770 tw32_f(MAC_RX_MODE, tp->rx_mode);
10772 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
10773 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)
10774 mac_mode &= ~MAC_MODE_LINK_POLARITY;
10775 else if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411)
10776 mac_mode |= MAC_MODE_LINK_POLARITY;
10777 tg3_writephy(tp, MII_TG3_EXT_CTRL,
10778 MII_TG3_EXT_CTRL_LNK3_LED_MODE);
10780 tw32(MAC_MODE, mac_mode);
10788 skb = netdev_alloc_skb(tp->dev, tx_len);
10792 tx_data = skb_put(skb, tx_len);
10793 memcpy(tx_data, tp->dev->dev_addr, 6);
10794 memset(tx_data + 6, 0x0, 8);
10796 tw32(MAC_RX_MTU_SIZE, tx_len + 4);
10798 for (i = 14; i < tx_len; i++)
10799 tx_data[i] = (u8) (i & 0xff);
10801 map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
10802 if (pci_dma_mapping_error(tp->pdev, map)) {
10803 dev_kfree_skb(skb);
10807 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10812 rx_start_idx = rnapi->hw_status->idx[0].rx_producer;
10816 tg3_set_txd(tnapi, tnapi->tx_prod, map, tx_len, 0, 1);
10821 tw32_tx_mbox(tnapi->prodmbox, tnapi->tx_prod);
10822 tr32_mailbox(tnapi->prodmbox);
10826 /* 350 usec to allow enough time on some 10/100 Mbps devices. */
10827 for (i = 0; i < 35; i++) {
10828 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
10833 tx_idx = tnapi->hw_status->idx[0].tx_consumer;
10834 rx_idx = rnapi->hw_status->idx[0].rx_producer;
10835 if ((tx_idx == tnapi->tx_prod) &&
10836 (rx_idx == (rx_start_idx + num_pkts)))
10840 pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
10841 dev_kfree_skb(skb);
10843 if (tx_idx != tnapi->tx_prod)
10846 if (rx_idx != rx_start_idx + num_pkts)
10849 desc = &rnapi->rx_rcb[rx_start_idx];
10850 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
10851 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
10852 if (opaque_key != RXD_OPAQUE_RING_STD)
10855 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
10856 (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
10859 rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
10860 if (rx_len != tx_len)
10863 rx_skb = tpr->rx_std_buffers[desc_idx].skb;
10865 map = pci_unmap_addr(&tpr->rx_std_buffers[desc_idx], mapping);
10866 pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
10868 for (i = 14; i < tx_len; i++) {
10869 if (*(rx_skb->data + i) != (u8) (i & 0xff))
10874 /* tg3_free_rings will unmap and free the rx_skb */
10879 #define TG3_MAC_LOOPBACK_FAILED 1
10880 #define TG3_PHY_LOOPBACK_FAILED 2
10881 #define TG3_LOOPBACK_FAILED (TG3_MAC_LOOPBACK_FAILED | \
10882 TG3_PHY_LOOPBACK_FAILED)
10884 static int tg3_test_loopback(struct tg3 *tp)
10889 if (!netif_running(tp->dev))
10890 return TG3_LOOPBACK_FAILED;
10892 err = tg3_reset_hw(tp, 1);
10894 return TG3_LOOPBACK_FAILED;
10896 /* Turn off gphy autopowerdown. */
10897 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10898 tg3_phy_toggle_apd(tp, false);
10900 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10904 tw32(TG3_CPMU_MUTEX_REQ, CPMU_MUTEX_REQ_DRIVER);
10906 /* Wait for up to 40 microseconds to acquire lock. */
10907 for (i = 0; i < 4; i++) {
10908 status = tr32(TG3_CPMU_MUTEX_GNT);
10909 if (status == CPMU_MUTEX_GNT_DRIVER)
10914 if (status != CPMU_MUTEX_GNT_DRIVER)
10915 return TG3_LOOPBACK_FAILED;
10917 /* Turn off link-based power management. */
10918 cpmuctrl = tr32(TG3_CPMU_CTRL);
10919 tw32(TG3_CPMU_CTRL,
10920 cpmuctrl & ~(CPMU_CTRL_LINK_SPEED_MODE |
10921 CPMU_CTRL_LINK_AWARE_MODE));
10924 if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
10925 err |= TG3_MAC_LOOPBACK_FAILED;
10927 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) {
10928 tw32(TG3_CPMU_CTRL, cpmuctrl);
10930 /* Release the mutex */
10931 tw32(TG3_CPMU_MUTEX_GNT, CPMU_MUTEX_GNT_DRIVER);
10934 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
10935 !(tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)) {
10936 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
10937 err |= TG3_PHY_LOOPBACK_FAILED;
10940 /* Re-enable gphy autopowerdown. */
10941 if (tp->tg3_flags3 & TG3_FLG3_PHY_ENABLE_APD)
10942 tg3_phy_toggle_apd(tp, true);
10947 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
10950 struct tg3 *tp = netdev_priv(dev);
10952 if (tp->link_config.phy_is_low_power)
10953 tg3_set_power_state(tp, PCI_D0);
10955 memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
10957 if (tg3_test_nvram(tp) != 0) {
10958 etest->flags |= ETH_TEST_FL_FAILED;
10961 if (tg3_test_link(tp) != 0) {
10962 etest->flags |= ETH_TEST_FL_FAILED;
10965 if (etest->flags & ETH_TEST_FL_OFFLINE) {
10966 int err, err2 = 0, irq_sync = 0;
10968 if (netif_running(dev)) {
10970 tg3_netif_stop(tp);
10974 tg3_full_lock(tp, irq_sync);
10976 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
10977 err = tg3_nvram_lock(tp);
10978 tg3_halt_cpu(tp, RX_CPU_BASE);
10979 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
10980 tg3_halt_cpu(tp, TX_CPU_BASE);
10982 tg3_nvram_unlock(tp);
10984 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
10987 if (tg3_test_registers(tp) != 0) {
10988 etest->flags |= ETH_TEST_FL_FAILED;
10991 if (tg3_test_memory(tp) != 0) {
10992 etest->flags |= ETH_TEST_FL_FAILED;
10995 if ((data[4] = tg3_test_loopback(tp)) != 0)
10996 etest->flags |= ETH_TEST_FL_FAILED;
10998 tg3_full_unlock(tp);
11000 if (tg3_test_interrupt(tp) != 0) {
11001 etest->flags |= ETH_TEST_FL_FAILED;
11005 tg3_full_lock(tp, 0);
11007 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11008 if (netif_running(dev)) {
11009 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
11010 err2 = tg3_restart_hw(tp, 1);
11012 tg3_netif_start(tp);
11015 tg3_full_unlock(tp);
11017 if (irq_sync && !err2)
11020 if (tp->link_config.phy_is_low_power)
11021 tg3_set_power_state(tp, PCI_D3hot);
11025 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
11027 struct mii_ioctl_data *data = if_mii(ifr);
11028 struct tg3 *tp = netdev_priv(dev);
11031 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
11032 struct phy_device *phydev;
11033 if (!(tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED))
11035 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
11036 return phy_mii_ioctl(phydev, data, cmd);
11041 data->phy_id = tp->phy_addr;
11044 case SIOCGMIIREG: {
11047 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11048 break; /* We have no PHY */
11050 if (tp->link_config.phy_is_low_power)
11053 spin_lock_bh(&tp->lock);
11054 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
11055 spin_unlock_bh(&tp->lock);
11057 data->val_out = mii_regval;
11063 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
11064 break; /* We have no PHY */
11066 if (tp->link_config.phy_is_low_power)
11069 spin_lock_bh(&tp->lock);
11070 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
11071 spin_unlock_bh(&tp->lock);
11079 return -EOPNOTSUPP;
11082 #if TG3_VLAN_TAG_USED
11083 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
11085 struct tg3 *tp = netdev_priv(dev);
11087 if (!netif_running(dev)) {
11092 tg3_netif_stop(tp);
11094 tg3_full_lock(tp, 0);
11098 /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
11099 __tg3_set_rx_mode(dev);
11101 tg3_netif_start(tp);
11103 tg3_full_unlock(tp);
11107 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11109 struct tg3 *tp = netdev_priv(dev);
11111 memcpy(ec, &tp->coal, sizeof(*ec));
11115 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
11117 struct tg3 *tp = netdev_priv(dev);
11118 u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
11119 u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
11121 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
11122 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
11123 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
11124 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
11125 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
11128 if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
11129 (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
11130 (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
11131 (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
11132 (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
11133 (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
11134 (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
11135 (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
11136 (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
11137 (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
11140 /* No rx interrupts will be generated if both are zero */
11141 if ((ec->rx_coalesce_usecs == 0) &&
11142 (ec->rx_max_coalesced_frames == 0))
11145 /* No tx interrupts will be generated if both are zero */
11146 if ((ec->tx_coalesce_usecs == 0) &&
11147 (ec->tx_max_coalesced_frames == 0))
11150 /* Only copy relevant parameters, ignore all others. */
11151 tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
11152 tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
11153 tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
11154 tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
11155 tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
11156 tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
11157 tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
11158 tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
11159 tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
11161 if (netif_running(dev)) {
11162 tg3_full_lock(tp, 0);
11163 __tg3_set_coalesce(tp, &tp->coal);
11164 tg3_full_unlock(tp);
11169 static const struct ethtool_ops tg3_ethtool_ops = {
11170 .get_settings = tg3_get_settings,
11171 .set_settings = tg3_set_settings,
11172 .get_drvinfo = tg3_get_drvinfo,
11173 .get_regs_len = tg3_get_regs_len,
11174 .get_regs = tg3_get_regs,
11175 .get_wol = tg3_get_wol,
11176 .set_wol = tg3_set_wol,
11177 .get_msglevel = tg3_get_msglevel,
11178 .set_msglevel = tg3_set_msglevel,
11179 .nway_reset = tg3_nway_reset,
11180 .get_link = ethtool_op_get_link,
11181 .get_eeprom_len = tg3_get_eeprom_len,
11182 .get_eeprom = tg3_get_eeprom,
11183 .set_eeprom = tg3_set_eeprom,
11184 .get_ringparam = tg3_get_ringparam,
11185 .set_ringparam = tg3_set_ringparam,
11186 .get_pauseparam = tg3_get_pauseparam,
11187 .set_pauseparam = tg3_set_pauseparam,
11188 .get_rx_csum = tg3_get_rx_csum,
11189 .set_rx_csum = tg3_set_rx_csum,
11190 .set_tx_csum = tg3_set_tx_csum,
11191 .set_sg = ethtool_op_set_sg,
11192 .set_tso = tg3_set_tso,
11193 .self_test = tg3_self_test,
11194 .get_strings = tg3_get_strings,
11195 .phys_id = tg3_phys_id,
11196 .get_ethtool_stats = tg3_get_ethtool_stats,
11197 .get_coalesce = tg3_get_coalesce,
11198 .set_coalesce = tg3_set_coalesce,
11199 .get_sset_count = tg3_get_sset_count,
11202 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
11204 u32 cursize, val, magic;
11206 tp->nvram_size = EEPROM_CHIP_SIZE;
11208 if (tg3_nvram_read(tp, 0, &magic) != 0)
11211 if ((magic != TG3_EEPROM_MAGIC) &&
11212 ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
11213 ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
11217 * Size the chip by reading offsets at increasing powers of two.
11218 * When we encounter our validation signature, we know the addressing
11219 * has wrapped around, and thus have our chip size.
11223 while (cursize < tp->nvram_size) {
11224 if (tg3_nvram_read(tp, cursize, &val) != 0)
11233 tp->nvram_size = cursize;
11236 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
11240 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
11241 tg3_nvram_read(tp, 0, &val) != 0)
11244 /* Selfboot format */
11245 if (val != TG3_EEPROM_MAGIC) {
11246 tg3_get_eeprom_size(tp);
11250 if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
11252 /* This is confusing. We want to operate on the
11253 * 16-bit value at offset 0xf2. The tg3_nvram_read()
11254 * call will read from NVRAM and byteswap the data
11255 * according to the byteswapping settings for all
11256 * other register accesses. This ensures the data we
11257 * want will always reside in the lower 16-bits.
11258 * However, the data in NVRAM is in LE format, which
11259 * means the data from the NVRAM read will always be
11260 * opposite the endianness of the CPU. The 16-bit
11261 * byteswap then brings the data to CPU endianness.
11263 tp->nvram_size = swab16((u16)(val & 0x0000ffff)) * 1024;
11267 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11270 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
11274 nvcfg1 = tr32(NVRAM_CFG1);
11275 if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
11276 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11278 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11279 tw32(NVRAM_CFG1, nvcfg1);
11282 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
11283 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11284 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
11285 case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
11286 tp->nvram_jedecnum = JEDEC_ATMEL;
11287 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11288 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11290 case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
11291 tp->nvram_jedecnum = JEDEC_ATMEL;
11292 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
11294 case FLASH_VENDOR_ATMEL_EEPROM:
11295 tp->nvram_jedecnum = JEDEC_ATMEL;
11296 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11297 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11299 case FLASH_VENDOR_ST:
11300 tp->nvram_jedecnum = JEDEC_ST;
11301 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
11302 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11304 case FLASH_VENDOR_SAIFUN:
11305 tp->nvram_jedecnum = JEDEC_SAIFUN;
11306 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
11308 case FLASH_VENDOR_SST_SMALL:
11309 case FLASH_VENDOR_SST_LARGE:
11310 tp->nvram_jedecnum = JEDEC_SST;
11311 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
11315 tp->nvram_jedecnum = JEDEC_ATMEL;
11316 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
11317 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11321 static void __devinit tg3_nvram_get_pagesize(struct tg3 *tp, u32 nvmcfg1)
11323 switch (nvmcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
11324 case FLASH_5752PAGE_SIZE_256:
11325 tp->nvram_pagesize = 256;
11327 case FLASH_5752PAGE_SIZE_512:
11328 tp->nvram_pagesize = 512;
11330 case FLASH_5752PAGE_SIZE_1K:
11331 tp->nvram_pagesize = 1024;
11333 case FLASH_5752PAGE_SIZE_2K:
11334 tp->nvram_pagesize = 2048;
11336 case FLASH_5752PAGE_SIZE_4K:
11337 tp->nvram_pagesize = 4096;
11339 case FLASH_5752PAGE_SIZE_264:
11340 tp->nvram_pagesize = 264;
11342 case FLASH_5752PAGE_SIZE_528:
11343 tp->nvram_pagesize = 528;
11348 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
11352 nvcfg1 = tr32(NVRAM_CFG1);
11354 /* NVRAM protection for TPM */
11355 if (nvcfg1 & (1 << 27))
11356 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11358 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11359 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
11360 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
11361 tp->nvram_jedecnum = JEDEC_ATMEL;
11362 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11364 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11365 tp->nvram_jedecnum = JEDEC_ATMEL;
11366 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11367 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11369 case FLASH_5752VENDOR_ST_M45PE10:
11370 case FLASH_5752VENDOR_ST_M45PE20:
11371 case FLASH_5752VENDOR_ST_M45PE40:
11372 tp->nvram_jedecnum = JEDEC_ST;
11373 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11374 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11378 if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
11379 tg3_nvram_get_pagesize(tp, nvcfg1);
11381 /* For eeprom, set pagesize to maximum eeprom size */
11382 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11384 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11385 tw32(NVRAM_CFG1, nvcfg1);
11389 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
11391 u32 nvcfg1, protect = 0;
11393 nvcfg1 = tr32(NVRAM_CFG1);
11395 /* NVRAM protection for TPM */
11396 if (nvcfg1 & (1 << 27)) {
11397 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11401 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11403 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11404 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11405 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11406 case FLASH_5755VENDOR_ATMEL_FLASH_5:
11407 tp->nvram_jedecnum = JEDEC_ATMEL;
11408 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11409 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11410 tp->nvram_pagesize = 264;
11411 if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_1 ||
11412 nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_5)
11413 tp->nvram_size = (protect ? 0x3e200 :
11414 TG3_NVRAM_SIZE_512KB);
11415 else if (nvcfg1 == FLASH_5755VENDOR_ATMEL_FLASH_2)
11416 tp->nvram_size = (protect ? 0x1f200 :
11417 TG3_NVRAM_SIZE_256KB);
11419 tp->nvram_size = (protect ? 0x1f200 :
11420 TG3_NVRAM_SIZE_128KB);
11422 case FLASH_5752VENDOR_ST_M45PE10:
11423 case FLASH_5752VENDOR_ST_M45PE20:
11424 case FLASH_5752VENDOR_ST_M45PE40:
11425 tp->nvram_jedecnum = JEDEC_ST;
11426 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11427 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11428 tp->nvram_pagesize = 256;
11429 if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE10)
11430 tp->nvram_size = (protect ?
11431 TG3_NVRAM_SIZE_64KB :
11432 TG3_NVRAM_SIZE_128KB);
11433 else if (nvcfg1 == FLASH_5752VENDOR_ST_M45PE20)
11434 tp->nvram_size = (protect ?
11435 TG3_NVRAM_SIZE_64KB :
11436 TG3_NVRAM_SIZE_256KB);
11438 tp->nvram_size = (protect ?
11439 TG3_NVRAM_SIZE_128KB :
11440 TG3_NVRAM_SIZE_512KB);
11445 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
11449 nvcfg1 = tr32(NVRAM_CFG1);
11451 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11452 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
11453 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11454 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
11455 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11456 tp->nvram_jedecnum = JEDEC_ATMEL;
11457 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11458 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11460 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11461 tw32(NVRAM_CFG1, nvcfg1);
11463 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11464 case FLASH_5755VENDOR_ATMEL_FLASH_1:
11465 case FLASH_5755VENDOR_ATMEL_FLASH_2:
11466 case FLASH_5755VENDOR_ATMEL_FLASH_3:
11467 tp->nvram_jedecnum = JEDEC_ATMEL;
11468 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11469 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11470 tp->nvram_pagesize = 264;
11472 case FLASH_5752VENDOR_ST_M45PE10:
11473 case FLASH_5752VENDOR_ST_M45PE20:
11474 case FLASH_5752VENDOR_ST_M45PE40:
11475 tp->nvram_jedecnum = JEDEC_ST;
11476 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11477 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11478 tp->nvram_pagesize = 256;
11483 static void __devinit tg3_get_5761_nvram_info(struct tg3 *tp)
11485 u32 nvcfg1, protect = 0;
11487 nvcfg1 = tr32(NVRAM_CFG1);
11489 /* NVRAM protection for TPM */
11490 if (nvcfg1 & (1 << 27)) {
11491 tp->tg3_flags3 |= TG3_FLG3_PROTECTED_NVRAM;
11495 nvcfg1 &= NVRAM_CFG1_5752VENDOR_MASK;
11497 case FLASH_5761VENDOR_ATMEL_ADB021D:
11498 case FLASH_5761VENDOR_ATMEL_ADB041D:
11499 case FLASH_5761VENDOR_ATMEL_ADB081D:
11500 case FLASH_5761VENDOR_ATMEL_ADB161D:
11501 case FLASH_5761VENDOR_ATMEL_MDB021D:
11502 case FLASH_5761VENDOR_ATMEL_MDB041D:
11503 case FLASH_5761VENDOR_ATMEL_MDB081D:
11504 case FLASH_5761VENDOR_ATMEL_MDB161D:
11505 tp->nvram_jedecnum = JEDEC_ATMEL;
11506 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11507 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11508 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11509 tp->nvram_pagesize = 256;
11511 case FLASH_5761VENDOR_ST_A_M45PE20:
11512 case FLASH_5761VENDOR_ST_A_M45PE40:
11513 case FLASH_5761VENDOR_ST_A_M45PE80:
11514 case FLASH_5761VENDOR_ST_A_M45PE16:
11515 case FLASH_5761VENDOR_ST_M_M45PE20:
11516 case FLASH_5761VENDOR_ST_M_M45PE40:
11517 case FLASH_5761VENDOR_ST_M_M45PE80:
11518 case FLASH_5761VENDOR_ST_M_M45PE16:
11519 tp->nvram_jedecnum = JEDEC_ST;
11520 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11521 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11522 tp->nvram_pagesize = 256;
11527 tp->nvram_size = tr32(NVRAM_ADDR_LOCKOUT);
11530 case FLASH_5761VENDOR_ATMEL_ADB161D:
11531 case FLASH_5761VENDOR_ATMEL_MDB161D:
11532 case FLASH_5761VENDOR_ST_A_M45PE16:
11533 case FLASH_5761VENDOR_ST_M_M45PE16:
11534 tp->nvram_size = TG3_NVRAM_SIZE_2MB;
11536 case FLASH_5761VENDOR_ATMEL_ADB081D:
11537 case FLASH_5761VENDOR_ATMEL_MDB081D:
11538 case FLASH_5761VENDOR_ST_A_M45PE80:
11539 case FLASH_5761VENDOR_ST_M_M45PE80:
11540 tp->nvram_size = TG3_NVRAM_SIZE_1MB;
11542 case FLASH_5761VENDOR_ATMEL_ADB041D:
11543 case FLASH_5761VENDOR_ATMEL_MDB041D:
11544 case FLASH_5761VENDOR_ST_A_M45PE40:
11545 case FLASH_5761VENDOR_ST_M_M45PE40:
11546 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11548 case FLASH_5761VENDOR_ATMEL_ADB021D:
11549 case FLASH_5761VENDOR_ATMEL_MDB021D:
11550 case FLASH_5761VENDOR_ST_A_M45PE20:
11551 case FLASH_5761VENDOR_ST_M_M45PE20:
11552 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11558 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
11560 tp->nvram_jedecnum = JEDEC_ATMEL;
11561 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11562 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11565 static void __devinit tg3_get_57780_nvram_info(struct tg3 *tp)
11569 nvcfg1 = tr32(NVRAM_CFG1);
11571 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11572 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
11573 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
11574 tp->nvram_jedecnum = JEDEC_ATMEL;
11575 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11576 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11578 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11579 tw32(NVRAM_CFG1, nvcfg1);
11581 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11582 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11583 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11584 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11585 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11586 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11587 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11588 tp->nvram_jedecnum = JEDEC_ATMEL;
11589 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11590 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11592 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11593 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
11594 case FLASH_57780VENDOR_ATMEL_AT45DB011D:
11595 case FLASH_57780VENDOR_ATMEL_AT45DB011B:
11596 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11598 case FLASH_57780VENDOR_ATMEL_AT45DB021D:
11599 case FLASH_57780VENDOR_ATMEL_AT45DB021B:
11600 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11602 case FLASH_57780VENDOR_ATMEL_AT45DB041D:
11603 case FLASH_57780VENDOR_ATMEL_AT45DB041B:
11604 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11608 case FLASH_5752VENDOR_ST_M45PE10:
11609 case FLASH_5752VENDOR_ST_M45PE20:
11610 case FLASH_5752VENDOR_ST_M45PE40:
11611 tp->nvram_jedecnum = JEDEC_ST;
11612 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11613 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11615 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11616 case FLASH_5752VENDOR_ST_M45PE10:
11617 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11619 case FLASH_5752VENDOR_ST_M45PE20:
11620 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11622 case FLASH_5752VENDOR_ST_M45PE40:
11623 tp->nvram_size = TG3_NVRAM_SIZE_512KB;
11628 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11632 tg3_nvram_get_pagesize(tp, nvcfg1);
11633 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11634 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11638 static void __devinit tg3_get_5717_nvram_info(struct tg3 *tp)
11642 nvcfg1 = tr32(NVRAM_CFG1);
11644 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11645 case FLASH_5717VENDOR_ATMEL_EEPROM:
11646 case FLASH_5717VENDOR_MICRO_EEPROM:
11647 tp->nvram_jedecnum = JEDEC_ATMEL;
11648 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11649 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
11651 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
11652 tw32(NVRAM_CFG1, nvcfg1);
11654 case FLASH_5717VENDOR_ATMEL_MDB011D:
11655 case FLASH_5717VENDOR_ATMEL_ADB011B:
11656 case FLASH_5717VENDOR_ATMEL_ADB011D:
11657 case FLASH_5717VENDOR_ATMEL_MDB021D:
11658 case FLASH_5717VENDOR_ATMEL_ADB021B:
11659 case FLASH_5717VENDOR_ATMEL_ADB021D:
11660 case FLASH_5717VENDOR_ATMEL_45USPT:
11661 tp->nvram_jedecnum = JEDEC_ATMEL;
11662 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11663 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11665 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11666 case FLASH_5717VENDOR_ATMEL_MDB021D:
11667 case FLASH_5717VENDOR_ATMEL_ADB021B:
11668 case FLASH_5717VENDOR_ATMEL_ADB021D:
11669 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11672 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11676 case FLASH_5717VENDOR_ST_M_M25PE10:
11677 case FLASH_5717VENDOR_ST_A_M25PE10:
11678 case FLASH_5717VENDOR_ST_M_M45PE10:
11679 case FLASH_5717VENDOR_ST_A_M45PE10:
11680 case FLASH_5717VENDOR_ST_M_M25PE20:
11681 case FLASH_5717VENDOR_ST_A_M25PE20:
11682 case FLASH_5717VENDOR_ST_M_M45PE20:
11683 case FLASH_5717VENDOR_ST_A_M45PE20:
11684 case FLASH_5717VENDOR_ST_25USPT:
11685 case FLASH_5717VENDOR_ST_45USPT:
11686 tp->nvram_jedecnum = JEDEC_ST;
11687 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
11688 tp->tg3_flags2 |= TG3_FLG2_FLASH;
11690 switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
11691 case FLASH_5717VENDOR_ST_M_M25PE20:
11692 case FLASH_5717VENDOR_ST_A_M25PE20:
11693 case FLASH_5717VENDOR_ST_M_M45PE20:
11694 case FLASH_5717VENDOR_ST_A_M45PE20:
11695 tp->nvram_size = TG3_NVRAM_SIZE_256KB;
11698 tp->nvram_size = TG3_NVRAM_SIZE_128KB;
11703 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM;
11707 tg3_nvram_get_pagesize(tp, nvcfg1);
11708 if (tp->nvram_pagesize != 264 && tp->nvram_pagesize != 528)
11709 tp->tg3_flags3 |= TG3_FLG3_NO_NVRAM_ADDR_TRANS;
11712 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
11713 static void __devinit tg3_nvram_init(struct tg3 *tp)
11715 tw32_f(GRC_EEPROM_ADDR,
11716 (EEPROM_ADDR_FSM_RESET |
11717 (EEPROM_DEFAULT_CLOCK_PERIOD <<
11718 EEPROM_ADDR_CLKPERD_SHIFT)));
11722 /* Enable seeprom accesses. */
11723 tw32_f(GRC_LOCAL_CTRL,
11724 tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
11727 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11728 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
11729 tp->tg3_flags |= TG3_FLAG_NVRAM;
11731 if (tg3_nvram_lock(tp)) {
11732 printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
11733 "tg3_nvram_init failed.\n", tp->dev->name);
11736 tg3_enable_nvram_access(tp);
11738 tp->nvram_size = 0;
11740 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
11741 tg3_get_5752_nvram_info(tp);
11742 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
11743 tg3_get_5755_nvram_info(tp);
11744 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
11745 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
11746 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
11747 tg3_get_5787_nvram_info(tp);
11748 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761)
11749 tg3_get_5761_nvram_info(tp);
11750 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11751 tg3_get_5906_nvram_info(tp);
11752 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
11753 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
11754 tg3_get_57780_nvram_info(tp);
11755 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
11756 tg3_get_5717_nvram_info(tp);
11758 tg3_get_nvram_info(tp);
11760 if (tp->nvram_size == 0)
11761 tg3_get_nvram_size(tp);
11763 tg3_disable_nvram_access(tp);
11764 tg3_nvram_unlock(tp);
11767 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
11769 tg3_get_eeprom_size(tp);
11773 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
11774 u32 offset, u32 len, u8 *buf)
11779 for (i = 0; i < len; i += 4) {
11785 memcpy(&data, buf + i, 4);
11788 * The SEEPROM interface expects the data to always be opposite
11789 * the native endian format. We accomplish this by reversing
11790 * all the operations that would have been performed on the
11791 * data from a call to tg3_nvram_read_be32().
11793 tw32(GRC_EEPROM_DATA, swab32(be32_to_cpu(data)));
11795 val = tr32(GRC_EEPROM_ADDR);
11796 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
11798 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
11800 tw32(GRC_EEPROM_ADDR, val |
11801 (0 << EEPROM_ADDR_DEVID_SHIFT) |
11802 (addr & EEPROM_ADDR_ADDR_MASK) |
11803 EEPROM_ADDR_START |
11804 EEPROM_ADDR_WRITE);
11806 for (j = 0; j < 1000; j++) {
11807 val = tr32(GRC_EEPROM_ADDR);
11809 if (val & EEPROM_ADDR_COMPLETE)
11813 if (!(val & EEPROM_ADDR_COMPLETE)) {
11822 /* offset and length are dword aligned */
11823 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
11827 u32 pagesize = tp->nvram_pagesize;
11828 u32 pagemask = pagesize - 1;
11832 tmp = kmalloc(pagesize, GFP_KERNEL);
11838 u32 phy_addr, page_off, size;
11840 phy_addr = offset & ~pagemask;
11842 for (j = 0; j < pagesize; j += 4) {
11843 ret = tg3_nvram_read_be32(tp, phy_addr + j,
11844 (__be32 *) (tmp + j));
11851 page_off = offset & pagemask;
11858 memcpy(tmp + page_off, buf, size);
11860 offset = offset + (pagesize - page_off);
11862 tg3_enable_nvram_access(tp);
11865 * Before we can erase the flash page, we need
11866 * to issue a special "write enable" command.
11868 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11870 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11873 /* Erase the target page */
11874 tw32(NVRAM_ADDR, phy_addr);
11876 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
11877 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
11879 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11882 /* Issue another write enable to start the write. */
11883 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11885 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
11888 for (j = 0; j < pagesize; j += 4) {
11891 data = *((__be32 *) (tmp + j));
11893 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11895 tw32(NVRAM_ADDR, phy_addr + j);
11897 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
11901 nvram_cmd |= NVRAM_CMD_FIRST;
11902 else if (j == (pagesize - 4))
11903 nvram_cmd |= NVRAM_CMD_LAST;
11905 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11912 nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
11913 tg3_nvram_exec_cmd(tp, nvram_cmd);
11920 /* offset and length are dword aligned */
11921 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
11926 for (i = 0; i < len; i += 4, offset += 4) {
11927 u32 page_off, phy_addr, nvram_cmd;
11930 memcpy(&data, buf + i, 4);
11931 tw32(NVRAM_WRDATA, be32_to_cpu(data));
11933 page_off = offset % tp->nvram_pagesize;
11935 phy_addr = tg3_nvram_phys_addr(tp, offset);
11937 tw32(NVRAM_ADDR, phy_addr);
11939 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
11941 if ((page_off == 0) || (i == 0))
11942 nvram_cmd |= NVRAM_CMD_FIRST;
11943 if (page_off == (tp->nvram_pagesize - 4))
11944 nvram_cmd |= NVRAM_CMD_LAST;
11946 if (i == (len - 4))
11947 nvram_cmd |= NVRAM_CMD_LAST;
11949 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
11950 !(tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
11951 (tp->nvram_jedecnum == JEDEC_ST) &&
11952 (nvram_cmd & NVRAM_CMD_FIRST)) {
11954 if ((ret = tg3_nvram_exec_cmd(tp,
11955 NVRAM_CMD_WREN | NVRAM_CMD_GO |
11960 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
11961 /* We always do complete word writes to eeprom. */
11962 nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
11965 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
11971 /* offset and length are dword aligned */
11972 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
11976 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
11977 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
11978 ~GRC_LCLCTRL_GPIO_OUTPUT1);
11982 if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
11983 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
11988 ret = tg3_nvram_lock(tp);
11992 tg3_enable_nvram_access(tp);
11993 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
11994 !(tp->tg3_flags3 & TG3_FLG3_PROTECTED_NVRAM))
11995 tw32(NVRAM_WRITE1, 0x406);
11997 grc_mode = tr32(GRC_MODE);
11998 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
12000 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
12001 !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
12003 ret = tg3_nvram_write_block_buffered(tp, offset, len,
12007 ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
12011 grc_mode = tr32(GRC_MODE);
12012 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
12014 tg3_disable_nvram_access(tp);
12015 tg3_nvram_unlock(tp);
12018 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
12019 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
12026 struct subsys_tbl_ent {
12027 u16 subsys_vendor, subsys_devid;
12031 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
12032 /* Broadcom boards. */
12033 { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
12034 { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
12035 { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
12036 { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 }, /* BCM95700A9 */
12037 { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
12038 { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
12039 { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 }, /* BCM95701A7 */
12040 { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
12041 { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
12042 { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
12043 { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
12046 { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
12047 { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
12048 { PCI_VENDOR_ID_3COM, 0x1004, 0 }, /* 3C996SX */
12049 { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
12050 { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
12053 { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
12054 { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
12055 { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
12056 { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
12058 /* Compaq boards. */
12059 { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
12060 { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
12061 { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 }, /* CHANGELING */
12062 { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
12063 { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
12066 { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
12069 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
12073 for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
12074 if ((subsys_id_to_phy_id[i].subsys_vendor ==
12075 tp->pdev->subsystem_vendor) &&
12076 (subsys_id_to_phy_id[i].subsys_devid ==
12077 tp->pdev->subsystem_device))
12078 return &subsys_id_to_phy_id[i];
12083 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
12088 /* On some early chips the SRAM cannot be accessed in D3hot state,
12089 * so need make sure we're in D0.
12091 pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
12092 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
12093 pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
12096 /* Make sure register accesses (indirect or otherwise)
12097 * will function correctly.
12099 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12100 tp->misc_host_ctrl);
12102 /* The memory arbiter has to be enabled in order for SRAM accesses
12103 * to succeed. Normally on powerup the tg3 chip firmware will make
12104 * sure it is enabled, but other entities such as system netboot
12105 * code might disable it.
12107 val = tr32(MEMARB_MODE);
12108 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
12110 tp->phy_id = PHY_ID_INVALID;
12111 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12113 /* Assume an onboard device and WOL capable by default. */
12114 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT | TG3_FLAG_WOL_CAP;
12116 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
12117 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
12118 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12119 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12121 val = tr32(VCPU_CFGSHDW);
12122 if (val & VCPU_CFGSHDW_ASPM_DBNC)
12123 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12124 if ((val & VCPU_CFGSHDW_WOL_ENABLE) &&
12125 (val & VCPU_CFGSHDW_WOL_MAGPKT))
12126 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12130 tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
12131 if (val == NIC_SRAM_DATA_SIG_MAGIC) {
12132 u32 nic_cfg, led_cfg;
12133 u32 nic_phy_id, ver, cfg2 = 0, cfg4 = 0, eeprom_phy_id;
12134 int eeprom_phy_serdes = 0;
12136 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
12137 tp->nic_sram_data_cfg = nic_cfg;
12139 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
12140 ver >>= NIC_SRAM_DATA_VER_SHIFT;
12141 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
12142 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
12143 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
12144 (ver > 0) && (ver < 0x100))
12145 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
12147 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785)
12148 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_4, &cfg4);
12150 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
12151 NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
12152 eeprom_phy_serdes = 1;
12154 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
12155 if (nic_phy_id != 0) {
12156 u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
12157 u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
12159 eeprom_phy_id = (id1 >> 16) << 10;
12160 eeprom_phy_id |= (id2 & 0xfc00) << 16;
12161 eeprom_phy_id |= (id2 & 0x03ff) << 0;
12165 tp->phy_id = eeprom_phy_id;
12166 if (eeprom_phy_serdes) {
12167 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
12168 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
12170 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12173 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12174 led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
12175 SHASTA_EXT_LED_MODE_MASK);
12177 led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
12181 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
12182 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12185 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
12186 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12189 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
12190 tp->led_ctrl = LED_CTRL_MODE_MAC;
12192 /* Default to PHY_1_MODE if 0 (MAC_MODE) is
12193 * read on some older 5700/5701 bootcode.
12195 if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
12197 GET_ASIC_REV(tp->pci_chip_rev_id) ==
12199 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12203 case SHASTA_EXT_LED_SHARED:
12204 tp->led_ctrl = LED_CTRL_MODE_SHARED;
12205 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
12206 tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
12207 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12208 LED_CTRL_MODE_PHY_2);
12211 case SHASTA_EXT_LED_MAC:
12212 tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
12215 case SHASTA_EXT_LED_COMBO:
12216 tp->led_ctrl = LED_CTRL_MODE_COMBO;
12217 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
12218 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
12219 LED_CTRL_MODE_PHY_2);
12224 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
12225 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
12226 tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
12227 tp->led_ctrl = LED_CTRL_MODE_PHY_2;
12229 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX)
12230 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
12232 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
12233 tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
12234 if ((tp->pdev->subsystem_vendor ==
12235 PCI_VENDOR_ID_ARIMA) &&
12236 (tp->pdev->subsystem_device == 0x205a ||
12237 tp->pdev->subsystem_device == 0x2063))
12238 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12240 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
12241 tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
12244 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
12245 tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
12246 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
12247 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
12250 if ((nic_cfg & NIC_SRAM_DATA_CFG_APE_ENABLE) &&
12251 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
12252 tp->tg3_flags3 |= TG3_FLG3_ENABLE_APE;
12254 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
12255 !(nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL))
12256 tp->tg3_flags &= ~TG3_FLAG_WOL_CAP;
12258 if ((tp->tg3_flags & TG3_FLAG_WOL_CAP) &&
12259 (nic_cfg & NIC_SRAM_DATA_CFG_WOL_ENABLE))
12260 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
12262 if (cfg2 & (1 << 17))
12263 tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
12265 /* serdes signal pre-emphasis in register 0x590 set by */
12266 /* bootcode if bit 18 is set */
12267 if (cfg2 & (1 << 18))
12268 tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
12270 if (((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
12271 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX)) &&
12272 (cfg2 & NIC_SRAM_DATA_CFG_2_APD_EN))
12273 tp->tg3_flags3 |= TG3_FLG3_PHY_ENABLE_APD;
12275 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
12278 tg3_read_mem(tp, NIC_SRAM_DATA_CFG_3, &cfg3);
12279 if (cfg3 & NIC_SRAM_ASPM_DEBOUNCE)
12280 tp->tg3_flags |= TG3_FLAG_ASPM_WORKAROUND;
12283 if (cfg4 & NIC_SRAM_RGMII_STD_IBND_DISABLE)
12284 tp->tg3_flags3 |= TG3_FLG3_RGMII_STD_IBND_DISABLE;
12285 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_RX_EN)
12286 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_RX_EN;
12287 if (cfg4 & NIC_SRAM_RGMII_EXT_IBND_TX_EN)
12288 tp->tg3_flags3 |= TG3_FLG3_RGMII_EXT_IBND_TX_EN;
12291 device_init_wakeup(&tp->pdev->dev, tp->tg3_flags & TG3_FLAG_WOL_CAP);
12292 device_set_wakeup_enable(&tp->pdev->dev,
12293 tp->tg3_flags & TG3_FLAG_WOL_ENABLE);
12296 static int __devinit tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
12301 tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
12302 tw32(OTP_CTRL, cmd);
12304 /* Wait for up to 1 ms for command to execute. */
12305 for (i = 0; i < 100; i++) {
12306 val = tr32(OTP_STATUS);
12307 if (val & OTP_STATUS_CMD_DONE)
12312 return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
12315 /* Read the gphy configuration from the OTP region of the chip. The gphy
12316 * configuration is a 32-bit value that straddles the alignment boundary.
12317 * We do two 32-bit reads and then shift and merge the results.
12319 static u32 __devinit tg3_read_otp_phycfg(struct tg3 *tp)
12321 u32 bhalf_otp, thalf_otp;
12323 tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
12325 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
12328 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
12330 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12333 thalf_otp = tr32(OTP_READ_DATA);
12335 tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
12337 if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
12340 bhalf_otp = tr32(OTP_READ_DATA);
12342 return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
12345 static int __devinit tg3_phy_probe(struct tg3 *tp)
12347 u32 hw_phy_id_1, hw_phy_id_2;
12348 u32 hw_phy_id, hw_phy_id_masked;
12351 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB)
12352 return tg3_phy_init(tp);
12354 /* Reading the PHY ID register can conflict with ASF
12355 * firmware access to the PHY hardware.
12358 if ((tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12359 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)) {
12360 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
12362 /* Now read the physical PHY_ID from the chip and verify
12363 * that it is sane. If it doesn't look good, we fall back
12364 * to either the hard-coded table based PHY_ID and failing
12365 * that the value found in the eeprom area.
12367 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
12368 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
12370 hw_phy_id = (hw_phy_id_1 & 0xffff) << 10;
12371 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
12372 hw_phy_id |= (hw_phy_id_2 & 0x03ff) << 0;
12374 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
12377 if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
12378 tp->phy_id = hw_phy_id;
12379 if (hw_phy_id_masked == PHY_ID_BCM8002)
12380 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12382 tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
12384 if (tp->phy_id != PHY_ID_INVALID) {
12385 /* Do nothing, phy ID already set up in
12386 * tg3_get_eeprom_hw_cfg().
12389 struct subsys_tbl_ent *p;
12391 /* No eeprom signature? Try the hardcoded
12392 * subsys device table.
12394 p = lookup_by_subsys(tp);
12398 tp->phy_id = p->phy_id;
12400 tp->phy_id == PHY_ID_BCM8002)
12401 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
12405 if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
12406 !(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) &&
12407 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
12408 u32 bmsr, adv_reg, tg3_ctrl, mask;
12410 tg3_readphy(tp, MII_BMSR, &bmsr);
12411 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
12412 (bmsr & BMSR_LSTATUS))
12413 goto skip_phy_reset;
12415 err = tg3_phy_reset(tp);
12419 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
12420 ADVERTISE_100HALF | ADVERTISE_100FULL |
12421 ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
12423 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
12424 tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
12425 MII_TG3_CTRL_ADV_1000_FULL);
12426 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
12427 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
12428 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
12429 MII_TG3_CTRL_ENABLE_AS_MASTER);
12432 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
12433 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
12434 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
12435 if (!tg3_copper_is_advertising_all(tp, mask)) {
12436 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12438 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12439 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12441 tg3_writephy(tp, MII_BMCR,
12442 BMCR_ANENABLE | BMCR_ANRESTART);
12444 tg3_phy_set_wirespeed(tp);
12446 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
12447 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
12448 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
12452 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
12453 err = tg3_init_5401phy_dsp(tp);
12458 if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
12459 err = tg3_init_5401phy_dsp(tp);
12462 if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
12463 tp->link_config.advertising =
12464 (ADVERTISED_1000baseT_Half |
12465 ADVERTISED_1000baseT_Full |
12466 ADVERTISED_Autoneg |
12468 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
12469 tp->link_config.advertising &=
12470 ~(ADVERTISED_1000baseT_Half |
12471 ADVERTISED_1000baseT_Full);
12476 static void __devinit tg3_read_partno(struct tg3 *tp)
12478 unsigned char vpd_data[TG3_NVM_VPD_LEN]; /* in little-endian format */
12482 if ((tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) ||
12483 tg3_nvram_read(tp, 0x0, &magic))
12484 goto out_not_found;
12486 if (magic == TG3_EEPROM_MAGIC) {
12487 for (i = 0; i < TG3_NVM_VPD_LEN; i += 4) {
12490 /* The data is in little-endian format in NVRAM.
12491 * Use the big-endian read routines to preserve
12492 * the byte order as it exists in NVRAM.
12494 if (tg3_nvram_read_be32(tp, TG3_NVM_VPD_OFF + i, &tmp))
12495 goto out_not_found;
12497 memcpy(&vpd_data[i], &tmp, sizeof(tmp));
12501 unsigned int pos = 0, i = 0;
12503 for (; pos < TG3_NVM_VPD_LEN && i < 3; i++, pos += cnt) {
12504 cnt = pci_read_vpd(tp->pdev, pos,
12505 TG3_NVM_VPD_LEN - pos,
12507 if (cnt == -ETIMEDOUT || -EINTR)
12510 goto out_not_found;
12512 if (pos != TG3_NVM_VPD_LEN)
12513 goto out_not_found;
12516 /* Now parse and find the part number. */
12517 for (i = 0; i < TG3_NVM_VPD_LEN - 2; ) {
12518 unsigned char val = vpd_data[i];
12519 unsigned int block_end;
12521 if (val == 0x82 || val == 0x91) {
12524 (vpd_data[i + 2] << 8)));
12529 goto out_not_found;
12531 block_end = (i + 3 +
12533 (vpd_data[i + 2] << 8)));
12536 if (block_end > TG3_NVM_VPD_LEN)
12537 goto out_not_found;
12539 while (i < (block_end - 2)) {
12540 if (vpd_data[i + 0] == 'P' &&
12541 vpd_data[i + 1] == 'N') {
12542 int partno_len = vpd_data[i + 2];
12545 if (partno_len > TG3_BPN_SIZE ||
12546 (partno_len + i) > TG3_NVM_VPD_LEN)
12547 goto out_not_found;
12549 memcpy(tp->board_part_number,
12550 &vpd_data[i], partno_len);
12555 i += 3 + vpd_data[i + 2];
12558 /* Part number not found. */
12559 goto out_not_found;
12563 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
12564 strcpy(tp->board_part_number, "BCM95906");
12565 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12566 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57780)
12567 strcpy(tp->board_part_number, "BCM57780");
12568 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12569 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57760)
12570 strcpy(tp->board_part_number, "BCM57760");
12571 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12572 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790)
12573 strcpy(tp->board_part_number, "BCM57790");
12574 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 &&
12575 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57788)
12576 strcpy(tp->board_part_number, "BCM57788");
12577 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
12578 strcpy(tp->board_part_number, "BCM57765");
12580 strcpy(tp->board_part_number, "none");
12583 static int __devinit tg3_fw_img_is_valid(struct tg3 *tp, u32 offset)
12587 if (tg3_nvram_read(tp, offset, &val) ||
12588 (val & 0xfc000000) != 0x0c000000 ||
12589 tg3_nvram_read(tp, offset + 4, &val) ||
12596 static void __devinit tg3_read_bc_ver(struct tg3 *tp)
12598 u32 val, offset, start, ver_offset;
12600 bool newver = false;
12602 if (tg3_nvram_read(tp, 0xc, &offset) ||
12603 tg3_nvram_read(tp, 0x4, &start))
12606 offset = tg3_nvram_logical_addr(tp, offset);
12608 if (tg3_nvram_read(tp, offset, &val))
12611 if ((val & 0xfc000000) == 0x0c000000) {
12612 if (tg3_nvram_read(tp, offset + 4, &val))
12620 if (tg3_nvram_read(tp, offset + 8, &ver_offset))
12623 offset = offset + ver_offset - start;
12624 for (i = 0; i < 16; i += 4) {
12626 if (tg3_nvram_read_be32(tp, offset + i, &v))
12629 memcpy(tp->fw_ver + i, &v, sizeof(v));
12634 if (tg3_nvram_read(tp, TG3_NVM_PTREV_BCVER, &ver_offset))
12637 major = (ver_offset & TG3_NVM_BCVER_MAJMSK) >>
12638 TG3_NVM_BCVER_MAJSFT;
12639 minor = ver_offset & TG3_NVM_BCVER_MINMSK;
12640 snprintf(&tp->fw_ver[0], 32, "v%d.%02d", major, minor);
12644 static void __devinit tg3_read_hwsb_ver(struct tg3 *tp)
12646 u32 val, major, minor;
12648 /* Use native endian representation */
12649 if (tg3_nvram_read(tp, TG3_NVM_HWSB_CFG1, &val))
12652 major = (val & TG3_NVM_HWSB_CFG1_MAJMSK) >>
12653 TG3_NVM_HWSB_CFG1_MAJSFT;
12654 minor = (val & TG3_NVM_HWSB_CFG1_MINMSK) >>
12655 TG3_NVM_HWSB_CFG1_MINSFT;
12657 snprintf(&tp->fw_ver[0], 32, "sb v%d.%02d", major, minor);
12660 static void __devinit tg3_read_sb_ver(struct tg3 *tp, u32 val)
12662 u32 offset, major, minor, build;
12664 tp->fw_ver[0] = 's';
12665 tp->fw_ver[1] = 'b';
12666 tp->fw_ver[2] = '\0';
12668 if ((val & TG3_EEPROM_SB_FORMAT_MASK) != TG3_EEPROM_SB_FORMAT_1)
12671 switch (val & TG3_EEPROM_SB_REVISION_MASK) {
12672 case TG3_EEPROM_SB_REVISION_0:
12673 offset = TG3_EEPROM_SB_F1R0_EDH_OFF;
12675 case TG3_EEPROM_SB_REVISION_2:
12676 offset = TG3_EEPROM_SB_F1R2_EDH_OFF;
12678 case TG3_EEPROM_SB_REVISION_3:
12679 offset = TG3_EEPROM_SB_F1R3_EDH_OFF;
12685 if (tg3_nvram_read(tp, offset, &val))
12688 build = (val & TG3_EEPROM_SB_EDH_BLD_MASK) >>
12689 TG3_EEPROM_SB_EDH_BLD_SHFT;
12690 major = (val & TG3_EEPROM_SB_EDH_MAJ_MASK) >>
12691 TG3_EEPROM_SB_EDH_MAJ_SHFT;
12692 minor = val & TG3_EEPROM_SB_EDH_MIN_MASK;
12694 if (minor > 99 || build > 26)
12697 snprintf(&tp->fw_ver[2], 30, " v%d.%02d", major, minor);
12700 tp->fw_ver[8] = 'a' + build - 1;
12701 tp->fw_ver[9] = '\0';
12705 static void __devinit tg3_read_mgmtfw_ver(struct tg3 *tp)
12707 u32 val, offset, start;
12710 for (offset = TG3_NVM_DIR_START;
12711 offset < TG3_NVM_DIR_END;
12712 offset += TG3_NVM_DIRENT_SIZE) {
12713 if (tg3_nvram_read(tp, offset, &val))
12716 if ((val >> TG3_NVM_DIRTYPE_SHIFT) == TG3_NVM_DIRTYPE_ASFINI)
12720 if (offset == TG3_NVM_DIR_END)
12723 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
12724 start = 0x08000000;
12725 else if (tg3_nvram_read(tp, offset - 4, &start))
12728 if (tg3_nvram_read(tp, offset + 4, &offset) ||
12729 !tg3_fw_img_is_valid(tp, offset) ||
12730 tg3_nvram_read(tp, offset + 8, &val))
12733 offset += val - start;
12735 vlen = strlen(tp->fw_ver);
12737 tp->fw_ver[vlen++] = ',';
12738 tp->fw_ver[vlen++] = ' ';
12740 for (i = 0; i < 4; i++) {
12742 if (tg3_nvram_read_be32(tp, offset, &v))
12745 offset += sizeof(v);
12747 if (vlen > TG3_VER_SIZE - sizeof(v)) {
12748 memcpy(&tp->fw_ver[vlen], &v, TG3_VER_SIZE - vlen);
12752 memcpy(&tp->fw_ver[vlen], &v, sizeof(v));
12757 static void __devinit tg3_read_dash_ver(struct tg3 *tp)
12762 if (!(tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) ||
12763 !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
12766 apedata = tg3_ape_read32(tp, TG3_APE_SEG_SIG);
12767 if (apedata != APE_SEG_SIG_MAGIC)
12770 apedata = tg3_ape_read32(tp, TG3_APE_FW_STATUS);
12771 if (!(apedata & APE_FW_STATUS_READY))
12774 apedata = tg3_ape_read32(tp, TG3_APE_FW_VERSION);
12776 vlen = strlen(tp->fw_ver);
12778 snprintf(&tp->fw_ver[vlen], TG3_VER_SIZE - vlen, " DASH v%d.%d.%d.%d",
12779 (apedata & APE_FW_VERSION_MAJMSK) >> APE_FW_VERSION_MAJSFT,
12780 (apedata & APE_FW_VERSION_MINMSK) >> APE_FW_VERSION_MINSFT,
12781 (apedata & APE_FW_VERSION_REVMSK) >> APE_FW_VERSION_REVSFT,
12782 (apedata & APE_FW_VERSION_BLDMSK));
12785 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
12789 if (tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) {
12790 tp->fw_ver[0] = 's';
12791 tp->fw_ver[1] = 'b';
12792 tp->fw_ver[2] = '\0';
12797 if (tg3_nvram_read(tp, 0, &val))
12800 if (val == TG3_EEPROM_MAGIC)
12801 tg3_read_bc_ver(tp);
12802 else if ((val & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW)
12803 tg3_read_sb_ver(tp, val);
12804 else if ((val & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
12805 tg3_read_hwsb_ver(tp);
12809 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF) ||
12810 (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE))
12813 tg3_read_mgmtfw_ver(tp);
12815 tp->fw_ver[TG3_VER_SIZE - 1] = 0;
12818 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *);
12820 static int __devinit tg3_get_invariants(struct tg3 *tp)
12822 static struct pci_device_id write_reorder_chipsets[] = {
12823 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12824 PCI_DEVICE_ID_AMD_FE_GATE_700C) },
12825 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
12826 PCI_DEVICE_ID_AMD_8131_BRIDGE) },
12827 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
12828 PCI_DEVICE_ID_VIA_8385_0) },
12832 u32 pci_state_reg, grc_misc_cfg;
12837 /* Force memory write invalidate off. If we leave it on,
12838 * then on 5700_BX chips we have to enable a workaround.
12839 * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
12840 * to match the cacheline size. The Broadcom driver have this
12841 * workaround but turns MWI off all the times so never uses
12842 * it. This seems to suggest that the workaround is insufficient.
12844 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
12845 pci_cmd &= ~PCI_COMMAND_INVALIDATE;
12846 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
12848 /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
12849 * has the register indirect write enable bit set before
12850 * we try to access any of the MMIO registers. It is also
12851 * critical that the PCI-X hw workaround situation is decided
12852 * before that as well.
12854 pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
12857 tp->pci_chip_rev_id = (misc_ctrl_reg >>
12858 MISC_HOST_CTRL_CHIPREV_SHIFT);
12859 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
12860 u32 prod_id_asic_rev;
12862 if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717 ||
12863 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 ||
12864 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5724)
12865 pci_read_config_dword(tp->pdev,
12866 TG3PCI_GEN2_PRODID_ASICREV,
12867 &prod_id_asic_rev);
12868 else if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_57781 ||
12869 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57785 ||
12870 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57761 ||
12871 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57765 ||
12872 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57791 ||
12873 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57795)
12874 pci_read_config_dword(tp->pdev,
12875 TG3PCI_GEN15_PRODID_ASICREV,
12876 &prod_id_asic_rev);
12878 pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
12879 &prod_id_asic_rev);
12881 tp->pci_chip_rev_id = prod_id_asic_rev;
12884 /* Wrong chip ID in 5752 A0. This code can be removed later
12885 * as A0 is not in production.
12887 if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
12888 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
12890 /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
12891 * we need to disable memory and use config. cycles
12892 * only to access all registers. The 5702/03 chips
12893 * can mistakenly decode the special cycles from the
12894 * ICH chipsets as memory write cycles, causing corruption
12895 * of register and memory space. Only certain ICH bridges
12896 * will drive special cycles with non-zero data during the
12897 * address phase which can fall within the 5703's address
12898 * range. This is not an ICH bug as the PCI spec allows
12899 * non-zero address during special cycles. However, only
12900 * these ICH bridges are known to drive non-zero addresses
12901 * during special cycles.
12903 * Since special cycles do not cross PCI bridges, we only
12904 * enable this workaround if the 5703 is on the secondary
12905 * bus of these ICH bridges.
12907 if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
12908 (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
12909 static struct tg3_dev_id {
12913 } ich_chipsets[] = {
12914 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
12916 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
12918 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
12920 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
12924 struct tg3_dev_id *pci_id = &ich_chipsets[0];
12925 struct pci_dev *bridge = NULL;
12927 while (pci_id->vendor != 0) {
12928 bridge = pci_get_device(pci_id->vendor, pci_id->device,
12934 if (pci_id->rev != PCI_ANY_ID) {
12935 if (bridge->revision > pci_id->rev)
12938 if (bridge->subordinate &&
12939 (bridge->subordinate->number ==
12940 tp->pdev->bus->number)) {
12942 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
12943 pci_dev_put(bridge);
12949 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
12950 static struct tg3_dev_id {
12953 } bridge_chipsets[] = {
12954 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0 },
12955 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1 },
12958 struct tg3_dev_id *pci_id = &bridge_chipsets[0];
12959 struct pci_dev *bridge = NULL;
12961 while (pci_id->vendor != 0) {
12962 bridge = pci_get_device(pci_id->vendor,
12969 if (bridge->subordinate &&
12970 (bridge->subordinate->number <=
12971 tp->pdev->bus->number) &&
12972 (bridge->subordinate->subordinate >=
12973 tp->pdev->bus->number)) {
12974 tp->tg3_flags3 |= TG3_FLG3_5701_DMA_BUG;
12975 pci_dev_put(bridge);
12981 /* The EPB bridge inside 5714, 5715, and 5780 cannot support
12982 * DMA addresses > 40-bit. This bridge may have other additional
12983 * 57xx devices behind it in some 4-port NIC designs for example.
12984 * Any tg3 device found behind the bridge will also need the 40-bit
12987 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
12988 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
12989 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
12990 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
12991 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
12994 struct pci_dev *bridge = NULL;
12997 bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
12998 PCI_DEVICE_ID_SERVERWORKS_EPB,
13000 if (bridge && bridge->subordinate &&
13001 (bridge->subordinate->number <=
13002 tp->pdev->bus->number) &&
13003 (bridge->subordinate->subordinate >=
13004 tp->pdev->bus->number)) {
13005 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
13006 pci_dev_put(bridge);
13012 /* Initialize misc host control in PCI block. */
13013 tp->misc_host_ctrl |= (misc_ctrl_reg &
13014 MISC_HOST_CTRL_CHIPREV);
13015 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13016 tp->misc_host_ctrl);
13018 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
13019 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
13020 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
13021 tp->pdev_peer = tg3_find_peer(tp);
13023 /* Intentionally exclude ASIC_REV_5906 */
13024 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13025 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13026 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13027 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13028 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13029 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13030 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13031 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13032 tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
13034 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13035 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13036 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
13037 (tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13038 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13039 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
13041 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
13042 (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
13043 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
13045 /* 5700 B0 chips do not support checksumming correctly due
13046 * to hardware bugs.
13048 if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
13049 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
13051 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
13052 tp->dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
13053 if (tp->tg3_flags3 & TG3_FLG3_5755_PLUS)
13054 tp->dev->features |= NETIF_F_IPV6_CSUM;
13057 /* Determine TSO capabilities */
13058 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13059 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13060 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_3;
13061 else if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13062 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13063 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
13064 else if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13065 tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 | TG3_FLG2_TSO_BUG;
13066 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 &&
13067 tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
13068 tp->tg3_flags2 &= ~TG3_FLG2_TSO_BUG;
13069 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13070 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13071 tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
13072 tp->tg3_flags2 |= TG3_FLG2_TSO_BUG;
13073 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)
13074 tp->fw_needed = FIRMWARE_TG3TSO5;
13076 tp->fw_needed = FIRMWARE_TG3TSO;
13081 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
13082 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSI;
13083 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX ||
13084 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX ||
13085 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 &&
13086 tp->pci_chip_rev_id <= CHIPREV_ID_5714_A2 &&
13087 tp->pdev_peer == tp->pdev))
13088 tp->tg3_flags &= ~TG3_FLAG_SUPPORT_MSI;
13090 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) ||
13091 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13092 tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
13095 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13096 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13097 tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
13098 tp->irq_max = TG3_IRQ_MAX_VECS;
13102 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13103 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13104 tp->tg3_flags3 |= TG3_FLG3_SHORT_DMA_BUG;
13105 else if (!(tp->tg3_flags3 & TG3_FLG3_5755_PLUS)) {
13106 tp->tg3_flags3 |= TG3_FLG3_4G_DMA_BNDRY_BUG;
13107 tp->tg3_flags3 |= TG3_FLG3_40BIT_DMA_LIMIT_BUG;
13110 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13111 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13112 tp->tg3_flags3 |= TG3_FLG3_USE_JUMBO_BDFLAG;
13114 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13115 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
13116 (tp->tg3_flags3 & TG3_FLG3_USE_JUMBO_BDFLAG))
13117 tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
13119 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13122 tp->pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
13123 if (tp->pcie_cap != 0) {
13126 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13128 pcie_set_readrq(tp->pdev, 4096);
13130 pci_read_config_word(tp->pdev,
13131 tp->pcie_cap + PCI_EXP_LNKCTL,
13133 if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN) {
13134 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13135 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
13136 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13137 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13138 tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
13139 tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
13140 tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
13141 } else if (tp->pci_chip_rev_id == CHIPREV_ID_5717_A0) {
13142 tp->tg3_flags3 |= TG3_FLG3_L1PLLPD_EN;
13144 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
13145 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
13146 } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
13147 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13148 tp->pcix_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_PCIX);
13149 if (!tp->pcix_cap) {
13150 printk(KERN_ERR PFX "Cannot find PCI-X "
13151 "capability, aborting.\n");
13155 if (!(pci_state_reg & PCISTATE_CONV_PCI_MODE))
13156 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
13159 /* If we have an AMD 762 or VIA K8T800 chipset, write
13160 * reordering to the mailbox registers done by the host
13161 * controller can cause major troubles. We read back from
13162 * every mailbox register write to force the writes to be
13163 * posted to the chip in order.
13165 if (pci_dev_present(write_reorder_chipsets) &&
13166 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13167 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
13169 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE,
13170 &tp->pci_cacheline_sz);
13171 pci_read_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13172 &tp->pci_lat_timer);
13173 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13174 tp->pci_lat_timer < 64) {
13175 tp->pci_lat_timer = 64;
13176 pci_write_config_byte(tp->pdev, PCI_LATENCY_TIMER,
13177 tp->pci_lat_timer);
13180 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
13181 /* 5700 BX chips need to have their TX producer index
13182 * mailboxes written twice to workaround a bug.
13184 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
13186 /* If we are in PCI-X mode, enable register write workaround.
13188 * The workaround is to use indirect register accesses
13189 * for all chip writes not to mailbox registers.
13191 if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
13194 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13196 /* The chip can have it's power management PCI config
13197 * space registers clobbered due to this bug.
13198 * So explicitly force the chip into D0 here.
13200 pci_read_config_dword(tp->pdev,
13201 tp->pm_cap + PCI_PM_CTRL,
13203 pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
13204 pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
13205 pci_write_config_dword(tp->pdev,
13206 tp->pm_cap + PCI_PM_CTRL,
13209 /* Also, force SERR#/PERR# in PCI command. */
13210 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13211 pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
13212 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13216 if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
13217 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
13218 if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
13219 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
13221 /* Chip-specific fixup from Broadcom driver */
13222 if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
13223 (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
13224 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
13225 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
13228 /* Default fast path register access methods */
13229 tp->read32 = tg3_read32;
13230 tp->write32 = tg3_write32;
13231 tp->read32_mbox = tg3_read32;
13232 tp->write32_mbox = tg3_write32;
13233 tp->write32_tx_mbox = tg3_write32;
13234 tp->write32_rx_mbox = tg3_write32;
13236 /* Various workaround register access methods */
13237 if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
13238 tp->write32 = tg3_write_indirect_reg32;
13239 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
13240 ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
13241 tp->pci_chip_rev_id == CHIPREV_ID_5750_A0)) {
13243 * Back to back register writes can cause problems on these
13244 * chips, the workaround is to read back all reg writes
13245 * except those to mailbox regs.
13247 * See tg3_write_indirect_reg32().
13249 tp->write32 = tg3_write_flush_reg32;
13252 if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
13253 (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
13254 tp->write32_tx_mbox = tg3_write32_tx_mbox;
13255 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
13256 tp->write32_rx_mbox = tg3_write_flush_reg32;
13259 if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
13260 tp->read32 = tg3_read_indirect_reg32;
13261 tp->write32 = tg3_write_indirect_reg32;
13262 tp->read32_mbox = tg3_read_indirect_mbox;
13263 tp->write32_mbox = tg3_write_indirect_mbox;
13264 tp->write32_tx_mbox = tg3_write_indirect_mbox;
13265 tp->write32_rx_mbox = tg3_write_indirect_mbox;
13270 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
13271 pci_cmd &= ~PCI_COMMAND_MEMORY;
13272 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
13274 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
13275 tp->read32_mbox = tg3_read32_mbox_5906;
13276 tp->write32_mbox = tg3_write32_mbox_5906;
13277 tp->write32_tx_mbox = tg3_write32_mbox_5906;
13278 tp->write32_rx_mbox = tg3_write32_mbox_5906;
13281 if (tp->write32 == tg3_write_indirect_reg32 ||
13282 ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13283 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13284 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
13285 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
13287 /* Get eeprom hw config before calling tg3_set_power_state().
13288 * In particular, the TG3_FLG2_IS_NIC flag must be
13289 * determined before calling tg3_set_power_state() so that
13290 * we know whether or not to switch out of Vaux power.
13291 * When the flag is set, it means that GPIO1 is used for eeprom
13292 * write protect and also implies that it is a LOM where GPIOs
13293 * are not used to switch power.
13295 tg3_get_eeprom_hw_cfg(tp);
13297 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
13298 /* Allow reads and writes to the
13299 * APE register and memory space.
13301 pci_state_reg |= PCISTATE_ALLOW_APE_CTLSPC_WR |
13302 PCISTATE_ALLOW_APE_SHMEM_WR;
13303 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE,
13307 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13308 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
13309 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13310 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
13311 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13312 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13313 tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
13315 /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
13316 * GPIO1 driven high will bring 5700's external PHY out of reset.
13317 * It is also used as eeprom write protect on LOMs.
13319 tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
13320 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13321 (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
13322 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
13323 GRC_LCLCTRL_GPIO_OUTPUT1);
13324 /* Unused GPIO3 must be driven as output on 5752 because there
13325 * are no pull-up resistors on unused GPIO pins.
13327 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
13328 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
13330 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13331 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13332 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13334 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5761 ||
13335 tp->pdev->device == TG3PCI_DEVICE_TIGON3_5761S) {
13336 /* Turn off the debug UART. */
13337 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
13338 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
13339 /* Keep VMain power. */
13340 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
13341 GRC_LCLCTRL_GPIO_OUTPUT0;
13344 /* Force the chip into D0. */
13345 err = tg3_set_power_state(tp, PCI_D0);
13347 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
13348 pci_name(tp->pdev));
13352 /* Derive initial jumbo mode from MTU assigned in
13353 * ether_setup() via the alloc_etherdev() call
13355 if (tp->dev->mtu > ETH_DATA_LEN &&
13356 !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
13357 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
13359 /* Determine WakeOnLan speed to use. */
13360 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13361 tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
13362 tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
13363 tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
13364 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
13366 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
13369 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13370 tp->tg3_flags3 |= TG3_FLG3_PHY_IS_FET;
13372 /* A few boards don't want Ethernet@WireSpeed phy feature */
13373 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
13374 ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
13375 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
13376 (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
13377 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) ||
13378 (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
13379 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
13381 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
13382 GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
13383 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
13384 if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
13385 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
13387 if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
13388 !(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
13389 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
13390 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
13391 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
13392 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57765) {
13393 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
13394 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
13395 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
13396 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761) {
13397 if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
13398 tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
13399 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
13400 if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
13401 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
13403 tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
13406 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
13407 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
13408 tp->phy_otp = tg3_read_otp_phycfg(tp);
13409 if (tp->phy_otp == 0)
13410 tp->phy_otp = TG3_OTP_DEFAULT;
13413 if (tp->tg3_flags & TG3_FLAG_CPMU_PRESENT)
13414 tp->mi_mode = MAC_MI_MODE_500KHZ_CONST;
13416 tp->mi_mode = MAC_MI_MODE_BASE;
13418 tp->coalesce_mode = 0;
13419 if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
13420 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
13421 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
13423 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
13424 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
13425 tp->tg3_flags3 |= TG3_FLG3_USE_PHYLIB;
13427 err = tg3_mdio_init(tp);
13431 /* Initialize data/descriptor byte/word swapping. */
13432 val = tr32(GRC_MODE);
13433 val &= GRC_MODE_HOST_STACKUP;
13434 tw32(GRC_MODE, val | tp->grc_mode);
13436 tg3_switch_clocks(tp);
13438 /* Clear this out for sanity. */
13439 tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
13441 pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
13443 if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
13444 (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
13445 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
13447 if (chiprevid == CHIPREV_ID_5701_A0 ||
13448 chiprevid == CHIPREV_ID_5701_B0 ||
13449 chiprevid == CHIPREV_ID_5701_B2 ||
13450 chiprevid == CHIPREV_ID_5701_B5) {
13451 void __iomem *sram_base;
13453 /* Write some dummy words into the SRAM status block
13454 * area, see if it reads back correctly. If the return
13455 * value is bad, force enable the PCIX workaround.
13457 sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
13459 writel(0x00000000, sram_base);
13460 writel(0x00000000, sram_base + 4);
13461 writel(0xffffffff, sram_base + 4);
13462 if (readl(sram_base) != 0x00000000)
13463 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
13468 tg3_nvram_init(tp);
13470 grc_misc_cfg = tr32(GRC_MISC_CFG);
13471 grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
13473 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13474 (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
13475 grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
13476 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
13478 if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
13479 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
13480 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
13481 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
13482 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
13483 HOSTCC_MODE_CLRTICK_TXBD);
13485 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
13486 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
13487 tp->misc_host_ctrl);
13490 /* Preserve the APE MAC_MODE bits */
13491 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE)
13492 tp->mac_mode = tr32(MAC_MODE) |
13493 MAC_MODE_APE_TX_EN | MAC_MODE_APE_RX_EN;
13495 tp->mac_mode = TG3_DEF_MAC_MODE;
13497 /* these are limited to 10/100 only */
13498 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
13499 (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
13500 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
13501 tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13502 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
13503 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
13504 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
13505 (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
13506 (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
13507 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
13508 tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
13509 tp->pdev->device == TG3PCI_DEVICE_TIGON3_57790 ||
13510 (tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET))
13511 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
13513 err = tg3_phy_probe(tp);
13515 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
13516 pci_name(tp->pdev), err);
13517 /* ... but do not return immediately ... */
13521 tg3_read_partno(tp);
13522 tg3_read_fw_ver(tp);
13524 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
13525 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13527 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13528 tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
13530 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
13533 /* 5700 {AX,BX} chips have a broken status block link
13534 * change bit implementation, so we must use the
13535 * status register in those cases.
13537 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
13538 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
13540 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
13542 /* The led_ctrl is set during tg3_phy_probe, here we might
13543 * have to force the link status polling mechanism based
13544 * upon subsystem IDs.
13546 if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
13547 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13548 !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
13549 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
13550 TG3_FLAG_USE_LINKCHG_REG);
13553 /* For all SERDES we poll the MAC status register. */
13554 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
13555 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
13557 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
13559 tp->rx_offset = NET_IP_ALIGN;
13560 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
13561 (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
13564 tp->rx_std_max_post = TG3_RX_RING_SIZE;
13566 /* Increment the rx prod index on the rx std ring by at most
13567 * 8 for these chips to workaround hw errata.
13569 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
13570 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
13571 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
13572 tp->rx_std_max_post = 8;
13574 if (tp->tg3_flags & TG3_FLAG_ASPM_WORKAROUND)
13575 tp->pwrmgmt_thresh = tr32(PCIE_PWR_MGMT_THRESH) &
13576 PCIE_PWR_MGMT_L1_THRESH_MSK;
13581 #ifdef CONFIG_SPARC
13582 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
13584 struct net_device *dev = tp->dev;
13585 struct pci_dev *pdev = tp->pdev;
13586 struct device_node *dp = pci_device_to_OF_node(pdev);
13587 const unsigned char *addr;
13590 addr = of_get_property(dp, "local-mac-address", &len);
13591 if (addr && len == 6) {
13592 memcpy(dev->dev_addr, addr, 6);
13593 memcpy(dev->perm_addr, dev->dev_addr, 6);
13599 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
13601 struct net_device *dev = tp->dev;
13603 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
13604 memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
13609 static int __devinit tg3_get_device_address(struct tg3 *tp)
13611 struct net_device *dev = tp->dev;
13612 u32 hi, lo, mac_offset;
13615 #ifdef CONFIG_SPARC
13616 if (!tg3_get_macaddr_sparc(tp))
13621 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
13622 (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
13623 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
13625 if (tg3_nvram_lock(tp))
13626 tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
13628 tg3_nvram_unlock(tp);
13629 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
13630 if (tr32(TG3_CPMU_STATUS) & TG3_CPMU_STATUS_PCIE_FUNC)
13632 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
13635 /* First try to get it from MAC address mailbox. */
13636 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
13637 if ((hi >> 16) == 0x484b) {
13638 dev->dev_addr[0] = (hi >> 8) & 0xff;
13639 dev->dev_addr[1] = (hi >> 0) & 0xff;
13641 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
13642 dev->dev_addr[2] = (lo >> 24) & 0xff;
13643 dev->dev_addr[3] = (lo >> 16) & 0xff;
13644 dev->dev_addr[4] = (lo >> 8) & 0xff;
13645 dev->dev_addr[5] = (lo >> 0) & 0xff;
13647 /* Some old bootcode may report a 0 MAC address in SRAM */
13648 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
13651 /* Next, try NVRAM. */
13652 if (!(tp->tg3_flags3 & TG3_FLG3_NO_NVRAM) &&
13653 !tg3_nvram_read_be32(tp, mac_offset + 0, &hi) &&
13654 !tg3_nvram_read_be32(tp, mac_offset + 4, &lo)) {
13655 memcpy(&dev->dev_addr[0], ((char *)&hi) + 2, 2);
13656 memcpy(&dev->dev_addr[2], (char *)&lo, sizeof(lo));
13658 /* Finally just fetch it out of the MAC control regs. */
13660 hi = tr32(MAC_ADDR_0_HIGH);
13661 lo = tr32(MAC_ADDR_0_LOW);
13663 dev->dev_addr[5] = lo & 0xff;
13664 dev->dev_addr[4] = (lo >> 8) & 0xff;
13665 dev->dev_addr[3] = (lo >> 16) & 0xff;
13666 dev->dev_addr[2] = (lo >> 24) & 0xff;
13667 dev->dev_addr[1] = hi & 0xff;
13668 dev->dev_addr[0] = (hi >> 8) & 0xff;
13672 if (!is_valid_ether_addr(&dev->dev_addr[0])) {
13673 #ifdef CONFIG_SPARC
13674 if (!tg3_get_default_macaddr_sparc(tp))
13679 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
13683 #define BOUNDARY_SINGLE_CACHELINE 1
13684 #define BOUNDARY_MULTI_CACHELINE 2
13686 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
13688 int cacheline_size;
13692 pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
13694 cacheline_size = 1024;
13696 cacheline_size = (int) byte * 4;
13698 /* On 5703 and later chips, the boundary bits have no
13701 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
13702 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
13703 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
13706 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
13707 goal = BOUNDARY_MULTI_CACHELINE;
13709 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
13710 goal = BOUNDARY_SINGLE_CACHELINE;
13716 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13717 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
13718 val = goal ? 0 : DMA_RWCTRL_DIS_CACHE_ALIGNMENT;
13725 /* PCI controllers on most RISC systems tend to disconnect
13726 * when a device tries to burst across a cache-line boundary.
13727 * Therefore, letting tg3 do so just wastes PCI bandwidth.
13729 * Unfortunately, for PCI-E there are only limited
13730 * write-side controls for this, and thus for reads
13731 * we will still get the disconnects. We'll also waste
13732 * these PCI cycles for both read and write for chips
13733 * other than 5700 and 5701 which do not implement the
13736 if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
13737 !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
13738 switch (cacheline_size) {
13743 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13744 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
13745 DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
13747 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13748 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13753 val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
13754 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
13758 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
13759 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
13762 } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13763 switch (cacheline_size) {
13767 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13768 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13769 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
13775 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
13776 val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
13780 switch (cacheline_size) {
13782 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13783 val |= (DMA_RWCTRL_READ_BNDRY_16 |
13784 DMA_RWCTRL_WRITE_BNDRY_16);
13789 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13790 val |= (DMA_RWCTRL_READ_BNDRY_32 |
13791 DMA_RWCTRL_WRITE_BNDRY_32);
13796 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13797 val |= (DMA_RWCTRL_READ_BNDRY_64 |
13798 DMA_RWCTRL_WRITE_BNDRY_64);
13803 if (goal == BOUNDARY_SINGLE_CACHELINE) {
13804 val |= (DMA_RWCTRL_READ_BNDRY_128 |
13805 DMA_RWCTRL_WRITE_BNDRY_128);
13810 val |= (DMA_RWCTRL_READ_BNDRY_256 |
13811 DMA_RWCTRL_WRITE_BNDRY_256);
13814 val |= (DMA_RWCTRL_READ_BNDRY_512 |
13815 DMA_RWCTRL_WRITE_BNDRY_512);
13819 val |= (DMA_RWCTRL_READ_BNDRY_1024 |
13820 DMA_RWCTRL_WRITE_BNDRY_1024);
13829 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
13831 struct tg3_internal_buffer_desc test_desc;
13832 u32 sram_dma_descs;
13835 sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
13837 tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
13838 tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
13839 tw32(RDMAC_STATUS, 0);
13840 tw32(WDMAC_STATUS, 0);
13842 tw32(BUFMGR_MODE, 0);
13843 tw32(FTQ_RESET, 0);
13845 test_desc.addr_hi = ((u64) buf_dma) >> 32;
13846 test_desc.addr_lo = buf_dma & 0xffffffff;
13847 test_desc.nic_mbuf = 0x00002100;
13848 test_desc.len = size;
13851 * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
13852 * the *second* time the tg3 driver was getting loaded after an
13855 * Broadcom tells me:
13856 * ...the DMA engine is connected to the GRC block and a DMA
13857 * reset may affect the GRC block in some unpredictable way...
13858 * The behavior of resets to individual blocks has not been tested.
13860 * Broadcom noted the GRC reset will also reset all sub-components.
13863 test_desc.cqid_sqid = (13 << 8) | 2;
13865 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
13868 test_desc.cqid_sqid = (16 << 8) | 7;
13870 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
13873 test_desc.flags = 0x00000005;
13875 for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
13878 val = *(((u32 *)&test_desc) + i);
13879 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
13880 sram_dma_descs + (i * sizeof(u32)));
13881 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
13883 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
13886 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
13888 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
13892 for (i = 0; i < 40; i++) {
13896 val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
13898 val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
13899 if ((val & 0xffff) == sram_dma_descs) {
13910 #define TEST_BUFFER_SIZE 0x2000
13912 static int __devinit tg3_test_dma(struct tg3 *tp)
13914 dma_addr_t buf_dma;
13915 u32 *buf, saved_dma_rwctrl;
13918 buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
13924 tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
13925 (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
13927 tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
13929 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
13930 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765)
13933 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
13934 /* DMA read watermark not used on PCIE */
13935 tp->dma_rwctrl |= 0x00180000;
13936 } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
13937 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
13938 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
13939 tp->dma_rwctrl |= 0x003f0000;
13941 tp->dma_rwctrl |= 0x003f000f;
13943 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13944 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
13945 u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
13946 u32 read_water = 0x7;
13948 /* If the 5704 is behind the EPB bridge, we can
13949 * do the less restrictive ONE_DMA workaround for
13950 * better performance.
13952 if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
13953 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13954 tp->dma_rwctrl |= 0x8000;
13955 else if (ccval == 0x6 || ccval == 0x7)
13956 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
13958 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
13960 /* Set bit 23 to enable PCIX hw bug fix */
13962 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
13963 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
13965 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
13966 /* 5780 always in PCIX mode */
13967 tp->dma_rwctrl |= 0x00144000;
13968 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
13969 /* 5714 always in PCIX mode */
13970 tp->dma_rwctrl |= 0x00148000;
13972 tp->dma_rwctrl |= 0x001b000f;
13976 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
13977 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
13978 tp->dma_rwctrl &= 0xfffffff0;
13980 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
13981 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
13982 /* Remove this if it causes problems for some boards. */
13983 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
13985 /* On 5700/5701 chips, we need to set this bit.
13986 * Otherwise the chip will issue cacheline transactions
13987 * to streamable DMA memory with not all the byte
13988 * enables turned on. This is an error on several
13989 * RISC PCI controllers, in particular sparc64.
13991 * On 5703/5704 chips, this bit has been reassigned
13992 * a different meaning. In particular, it is used
13993 * on those chips to enable a PCI-X workaround.
13995 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
13998 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14001 /* Unneeded, already done by tg3_get_invariants. */
14002 tg3_switch_clocks(tp);
14005 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
14006 GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
14009 /* It is best to perform DMA test with maximum write burst size
14010 * to expose the 5700/5701 write DMA bug.
14012 saved_dma_rwctrl = tp->dma_rwctrl;
14013 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14014 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14019 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
14022 /* Send the buffer to the chip. */
14023 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
14025 printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
14030 /* validate data reached card RAM correctly. */
14031 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14033 tg3_read_mem(tp, 0x2100 + (i*4), &val);
14034 if (le32_to_cpu(val) != p[i]) {
14035 printk(KERN_ERR " tg3_test_dma() Card buffer corrupted on write! (%d != %d)\n", val, i);
14036 /* ret = -ENODEV here? */
14041 /* Now read it back. */
14042 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
14044 printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
14050 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
14054 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14055 DMA_RWCTRL_WRITE_BNDRY_16) {
14056 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14057 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14058 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14061 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
14067 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
14073 if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
14074 DMA_RWCTRL_WRITE_BNDRY_16) {
14075 static struct pci_device_id dma_wait_state_chipsets[] = {
14076 { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
14077 PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
14081 /* DMA test passed without adjusting DMA boundary,
14082 * now look for chipsets that are known to expose the
14083 * DMA bug without failing the test.
14085 if (pci_dev_present(dma_wait_state_chipsets)) {
14086 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
14087 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
14090 /* Safe to use the calculated DMA boundary. */
14091 tp->dma_rwctrl = saved_dma_rwctrl;
14093 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
14097 pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
14102 static void __devinit tg3_init_link_config(struct tg3 *tp)
14104 tp->link_config.advertising =
14105 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
14106 ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
14107 ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
14108 ADVERTISED_Autoneg | ADVERTISED_MII);
14109 tp->link_config.speed = SPEED_INVALID;
14110 tp->link_config.duplex = DUPLEX_INVALID;
14111 tp->link_config.autoneg = AUTONEG_ENABLE;
14112 tp->link_config.active_speed = SPEED_INVALID;
14113 tp->link_config.active_duplex = DUPLEX_INVALID;
14114 tp->link_config.phy_is_low_power = 0;
14115 tp->link_config.orig_speed = SPEED_INVALID;
14116 tp->link_config.orig_duplex = DUPLEX_INVALID;
14117 tp->link_config.orig_autoneg = AUTONEG_INVALID;
14120 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
14122 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 ||
14123 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765) {
14124 tp->bufmgr_config.mbuf_read_dma_low_water =
14125 DEFAULT_MB_RDMA_LOW_WATER_5705;
14126 tp->bufmgr_config.mbuf_mac_rx_low_water =
14127 DEFAULT_MB_MACRX_LOW_WATER_57765;
14128 tp->bufmgr_config.mbuf_high_water =
14129 DEFAULT_MB_HIGH_WATER_57765;
14131 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14132 DEFAULT_MB_RDMA_LOW_WATER_5705;
14133 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14134 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765;
14135 tp->bufmgr_config.mbuf_high_water_jumbo =
14136 DEFAULT_MB_HIGH_WATER_JUMBO_57765;
14137 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14138 tp->bufmgr_config.mbuf_read_dma_low_water =
14139 DEFAULT_MB_RDMA_LOW_WATER_5705;
14140 tp->bufmgr_config.mbuf_mac_rx_low_water =
14141 DEFAULT_MB_MACRX_LOW_WATER_5705;
14142 tp->bufmgr_config.mbuf_high_water =
14143 DEFAULT_MB_HIGH_WATER_5705;
14144 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
14145 tp->bufmgr_config.mbuf_mac_rx_low_water =
14146 DEFAULT_MB_MACRX_LOW_WATER_5906;
14147 tp->bufmgr_config.mbuf_high_water =
14148 DEFAULT_MB_HIGH_WATER_5906;
14151 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14152 DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
14153 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14154 DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
14155 tp->bufmgr_config.mbuf_high_water_jumbo =
14156 DEFAULT_MB_HIGH_WATER_JUMBO_5780;
14158 tp->bufmgr_config.mbuf_read_dma_low_water =
14159 DEFAULT_MB_RDMA_LOW_WATER;
14160 tp->bufmgr_config.mbuf_mac_rx_low_water =
14161 DEFAULT_MB_MACRX_LOW_WATER;
14162 tp->bufmgr_config.mbuf_high_water =
14163 DEFAULT_MB_HIGH_WATER;
14165 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
14166 DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
14167 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
14168 DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
14169 tp->bufmgr_config.mbuf_high_water_jumbo =
14170 DEFAULT_MB_HIGH_WATER_JUMBO;
14173 tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
14174 tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
14177 static char * __devinit tg3_phy_string(struct tg3 *tp)
14179 switch (tp->phy_id & PHY_ID_MASK) {
14180 case PHY_ID_BCM5400: return "5400";
14181 case PHY_ID_BCM5401: return "5401";
14182 case PHY_ID_BCM5411: return "5411";
14183 case PHY_ID_BCM5701: return "5701";
14184 case PHY_ID_BCM5703: return "5703";
14185 case PHY_ID_BCM5704: return "5704";
14186 case PHY_ID_BCM5705: return "5705";
14187 case PHY_ID_BCM5750: return "5750";
14188 case PHY_ID_BCM5752: return "5752";
14189 case PHY_ID_BCM5714: return "5714";
14190 case PHY_ID_BCM5780: return "5780";
14191 case PHY_ID_BCM5755: return "5755";
14192 case PHY_ID_BCM5787: return "5787";
14193 case PHY_ID_BCM5784: return "5784";
14194 case PHY_ID_BCM5756: return "5722/5756";
14195 case PHY_ID_BCM5906: return "5906";
14196 case PHY_ID_BCM5761: return "5761";
14197 case PHY_ID_BCM5718C: return "5718C";
14198 case PHY_ID_BCM5718S: return "5718S";
14199 case PHY_ID_BCM8002: return "8002/serdes";
14200 case 0: return "serdes";
14201 default: return "unknown";
14205 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
14207 if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
14208 strcpy(str, "PCI Express");
14210 } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
14211 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
14213 strcpy(str, "PCIX:");
14215 if ((clock_ctrl == 7) ||
14216 ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
14217 GRC_MISC_CFG_BOARD_ID_5704CIOBE))
14218 strcat(str, "133MHz");
14219 else if (clock_ctrl == 0)
14220 strcat(str, "33MHz");
14221 else if (clock_ctrl == 2)
14222 strcat(str, "50MHz");
14223 else if (clock_ctrl == 4)
14224 strcat(str, "66MHz");
14225 else if (clock_ctrl == 6)
14226 strcat(str, "100MHz");
14228 strcpy(str, "PCI:");
14229 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
14230 strcat(str, "66MHz");
14232 strcat(str, "33MHz");
14234 if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
14235 strcat(str, ":32-bit");
14237 strcat(str, ":64-bit");
14241 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
14243 struct pci_dev *peer;
14244 unsigned int func, devnr = tp->pdev->devfn & ~7;
14246 for (func = 0; func < 8; func++) {
14247 peer = pci_get_slot(tp->pdev->bus, devnr | func);
14248 if (peer && peer != tp->pdev)
14252 /* 5704 can be configured in single-port mode, set peer to
14253 * tp->pdev in that case.
14261 * We don't need to keep the refcount elevated; there's no way
14262 * to remove one half of this device without removing the other
14269 static void __devinit tg3_init_coal(struct tg3 *tp)
14271 struct ethtool_coalesce *ec = &tp->coal;
14273 memset(ec, 0, sizeof(*ec));
14274 ec->cmd = ETHTOOL_GCOALESCE;
14275 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
14276 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
14277 ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
14278 ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
14279 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
14280 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
14281 ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
14282 ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
14283 ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
14285 if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
14286 HOSTCC_MODE_CLRTICK_TXBD)) {
14287 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
14288 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
14289 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
14290 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
14293 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
14294 ec->rx_coalesce_usecs_irq = 0;
14295 ec->tx_coalesce_usecs_irq = 0;
14296 ec->stats_block_coalesce_usecs = 0;
14300 static const struct net_device_ops tg3_netdev_ops = {
14301 .ndo_open = tg3_open,
14302 .ndo_stop = tg3_close,
14303 .ndo_start_xmit = tg3_start_xmit,
14304 .ndo_get_stats = tg3_get_stats,
14305 .ndo_validate_addr = eth_validate_addr,
14306 .ndo_set_multicast_list = tg3_set_rx_mode,
14307 .ndo_set_mac_address = tg3_set_mac_addr,
14308 .ndo_do_ioctl = tg3_ioctl,
14309 .ndo_tx_timeout = tg3_tx_timeout,
14310 .ndo_change_mtu = tg3_change_mtu,
14311 #if TG3_VLAN_TAG_USED
14312 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14314 #ifdef CONFIG_NET_POLL_CONTROLLER
14315 .ndo_poll_controller = tg3_poll_controller,
14319 static const struct net_device_ops tg3_netdev_ops_dma_bug = {
14320 .ndo_open = tg3_open,
14321 .ndo_stop = tg3_close,
14322 .ndo_start_xmit = tg3_start_xmit_dma_bug,
14323 .ndo_get_stats = tg3_get_stats,
14324 .ndo_validate_addr = eth_validate_addr,
14325 .ndo_set_multicast_list = tg3_set_rx_mode,
14326 .ndo_set_mac_address = tg3_set_mac_addr,
14327 .ndo_do_ioctl = tg3_ioctl,
14328 .ndo_tx_timeout = tg3_tx_timeout,
14329 .ndo_change_mtu = tg3_change_mtu,
14330 #if TG3_VLAN_TAG_USED
14331 .ndo_vlan_rx_register = tg3_vlan_rx_register,
14333 #ifdef CONFIG_NET_POLL_CONTROLLER
14334 .ndo_poll_controller = tg3_poll_controller,
14338 static int __devinit tg3_init_one(struct pci_dev *pdev,
14339 const struct pci_device_id *ent)
14341 static int tg3_version_printed = 0;
14342 struct net_device *dev;
14344 int i, err, pm_cap;
14345 u32 sndmbx, rcvmbx, intmbx;
14347 u64 dma_mask, persist_dma_mask;
14349 if (tg3_version_printed++ == 0)
14350 printk(KERN_INFO "%s", version);
14352 err = pci_enable_device(pdev);
14354 printk(KERN_ERR PFX "Cannot enable PCI device, "
14359 err = pci_request_regions(pdev, DRV_MODULE_NAME);
14361 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
14363 goto err_out_disable_pdev;
14366 pci_set_master(pdev);
14368 /* Find power-management capability. */
14369 pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
14371 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
14374 goto err_out_free_res;
14377 dev = alloc_etherdev_mq(sizeof(*tp), TG3_IRQ_MAX_VECS);
14379 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
14381 goto err_out_free_res;
14384 SET_NETDEV_DEV(dev, &pdev->dev);
14386 #if TG3_VLAN_TAG_USED
14387 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
14390 tp = netdev_priv(dev);
14393 tp->pm_cap = pm_cap;
14394 tp->rx_mode = TG3_DEF_RX_MODE;
14395 tp->tx_mode = TG3_DEF_TX_MODE;
14398 tp->msg_enable = tg3_debug;
14400 tp->msg_enable = TG3_DEF_MSG_ENABLE;
14402 /* The word/byte swap controls here control register access byte
14403 * swapping. DMA data byte swapping is controlled in the GRC_MODE
14406 tp->misc_host_ctrl =
14407 MISC_HOST_CTRL_MASK_PCI_INT |
14408 MISC_HOST_CTRL_WORD_SWAP |
14409 MISC_HOST_CTRL_INDIR_ACCESS |
14410 MISC_HOST_CTRL_PCISTATE_RW;
14412 /* The NONFRM (non-frame) byte/word swap controls take effect
14413 * on descriptor entries, anything which isn't packet data.
14415 * The StrongARM chips on the board (one for tx, one for rx)
14416 * are running in big-endian mode.
14418 tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
14419 GRC_MODE_WSWAP_NONFRM_DATA);
14420 #ifdef __BIG_ENDIAN
14421 tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
14423 spin_lock_init(&tp->lock);
14424 spin_lock_init(&tp->indirect_lock);
14425 INIT_WORK(&tp->reset_task, tg3_reset_task);
14427 tp->regs = pci_ioremap_bar(pdev, BAR_0);
14429 printk(KERN_ERR PFX "Cannot map device registers, "
14432 goto err_out_free_dev;
14435 tg3_init_link_config(tp);
14437 tp->rx_pending = TG3_DEF_RX_RING_PENDING;
14438 tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
14440 dev->ethtool_ops = &tg3_ethtool_ops;
14441 dev->watchdog_timeo = TG3_TX_TIMEOUT;
14442 dev->irq = pdev->irq;
14444 err = tg3_get_invariants(tp);
14446 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
14448 goto err_out_iounmap;
14451 if ((tp->tg3_flags3 & TG3_FLG3_5755_PLUS) &&
14452 tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
14453 dev->netdev_ops = &tg3_netdev_ops;
14455 dev->netdev_ops = &tg3_netdev_ops_dma_bug;
14458 /* The EPB bridge inside 5714, 5715, and 5780 and any
14459 * device behind the EPB cannot support DMA addresses > 40-bit.
14460 * On 64-bit systems with IOMMU, use 40-bit dma_mask.
14461 * On 64-bit systems without IOMMU, use 64-bit dma_mask and
14462 * do DMA address check in tg3_start_xmit().
14464 if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
14465 persist_dma_mask = dma_mask = DMA_BIT_MASK(32);
14466 else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
14467 persist_dma_mask = dma_mask = DMA_BIT_MASK(40);
14468 #ifdef CONFIG_HIGHMEM
14469 dma_mask = DMA_BIT_MASK(64);
14472 persist_dma_mask = dma_mask = DMA_BIT_MASK(64);
14474 /* Configure DMA attributes. */
14475 if (dma_mask > DMA_BIT_MASK(32)) {
14476 err = pci_set_dma_mask(pdev, dma_mask);
14478 dev->features |= NETIF_F_HIGHDMA;
14479 err = pci_set_consistent_dma_mask(pdev,
14482 printk(KERN_ERR PFX "Unable to obtain 64 bit "
14483 "DMA for consistent allocations\n");
14484 goto err_out_iounmap;
14488 if (err || dma_mask == DMA_BIT_MASK(32)) {
14489 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
14491 printk(KERN_ERR PFX "No usable DMA configuration, "
14493 goto err_out_iounmap;
14497 tg3_init_bufmgr_config(tp);
14499 /* Selectively allow TSO based on operating conditions */
14500 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
14501 (tp->fw_needed && !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)))
14502 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
14504 tp->tg3_flags2 &= ~(TG3_FLG2_TSO_CAPABLE | TG3_FLG2_TSO_BUG);
14505 tp->fw_needed = NULL;
14508 if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0)
14509 tp->fw_needed = FIRMWARE_TG3;
14511 /* TSO is on by default on chips that support hardware TSO.
14512 * Firmware TSO on older chips gives lower performance, so it
14513 * is off by default, but can be enabled using ethtool.
14515 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) &&
14516 (dev->features & NETIF_F_IP_CSUM))
14517 dev->features |= NETIF_F_TSO;
14519 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) ||
14520 (tp->tg3_flags2 & TG3_FLG2_HW_TSO_3)) {
14521 if (dev->features & NETIF_F_IPV6_CSUM)
14522 dev->features |= NETIF_F_TSO6;
14523 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_3) ||
14524 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
14525 (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
14526 GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
14527 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
14528 GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
14529 dev->features |= NETIF_F_TSO_ECN;
14532 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
14533 !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
14534 !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
14535 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
14536 tp->rx_pending = 63;
14539 err = tg3_get_device_address(tp);
14541 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
14543 goto err_out_iounmap;
14546 if (tp->tg3_flags3 & TG3_FLG3_ENABLE_APE) {
14547 tp->aperegs = pci_ioremap_bar(pdev, BAR_2);
14548 if (!tp->aperegs) {
14549 printk(KERN_ERR PFX "Cannot map APE registers, "
14552 goto err_out_iounmap;
14555 tg3_ape_lock_init(tp);
14557 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
14558 tg3_read_dash_ver(tp);
14562 * Reset chip in case UNDI or EFI driver did not shutdown
14563 * DMA self test will enable WDMAC and we'll see (spurious)
14564 * pending DMA on the PCI bus at that point.
14566 if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
14567 (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
14568 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
14569 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14572 err = tg3_test_dma(tp);
14574 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
14575 goto err_out_apeunmap;
14578 /* flow control autonegotiation is default behavior */
14579 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
14580 tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
14582 intmbx = MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW;
14583 rcvmbx = MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW;
14584 sndmbx = MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW;
14585 for (i = 0; i < TG3_IRQ_MAX_VECS; i++) {
14586 struct tg3_napi *tnapi = &tp->napi[i];
14589 tnapi->tx_pending = TG3_DEF_TX_RING_PENDING;
14591 tnapi->int_mbox = intmbx;
14597 tnapi->consmbox = rcvmbx;
14598 tnapi->prodmbox = sndmbx;
14601 tnapi->coal_now = HOSTCC_MODE_COAL_VEC1_NOW << (i - 1);
14602 netif_napi_add(dev, &tnapi->napi, tg3_poll_msix, 64);
14604 tnapi->coal_now = HOSTCC_MODE_NOW;
14605 netif_napi_add(dev, &tnapi->napi, tg3_poll, 64);
14608 if (!(tp->tg3_flags & TG3_FLAG_SUPPORT_MSIX))
14612 * If we support MSIX, we'll be using RSS. If we're using
14613 * RSS, the first vector only handles link interrupts and the
14614 * remaining vectors handle rx and tx interrupts. Reuse the
14615 * mailbox values for the next iteration. The values we setup
14616 * above are still useful for the single vectored mode.
14631 pci_set_drvdata(pdev, dev);
14633 err = register_netdev(dev);
14635 printk(KERN_ERR PFX "Cannot register net device, "
14637 goto err_out_apeunmap;
14640 printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x] (%s) MAC address %pM\n",
14642 tp->board_part_number,
14643 tp->pci_chip_rev_id,
14644 tg3_bus_string(tp, str),
14647 if (tp->tg3_flags3 & TG3_FLG3_PHY_CONNECTED) {
14648 struct phy_device *phydev;
14649 phydev = tp->mdio_bus->phy_map[TG3_PHY_MII_ADDR];
14651 "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
14652 tp->dev->name, phydev->drv->name,
14653 dev_name(&phydev->dev));
14656 "%s: attached PHY is %s (%s Ethernet) (WireSpeed[%d])\n",
14657 tp->dev->name, tg3_phy_string(tp),
14658 ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
14659 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
14660 "10/100/1000Base-T")),
14661 (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0);
14663 printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] MIirq[%d] ASF[%d] TSOcap[%d]\n",
14665 (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
14666 (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
14667 (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
14668 (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
14669 (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
14670 printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
14671 dev->name, tp->dma_rwctrl,
14672 (pdev->dma_mask == DMA_BIT_MASK(32)) ? 32 :
14673 (((u64) pdev->dma_mask == DMA_BIT_MASK(40)) ? 40 : 64));
14679 iounmap(tp->aperegs);
14680 tp->aperegs = NULL;
14693 pci_release_regions(pdev);
14695 err_out_disable_pdev:
14696 pci_disable_device(pdev);
14697 pci_set_drvdata(pdev, NULL);
14701 static void __devexit tg3_remove_one(struct pci_dev *pdev)
14703 struct net_device *dev = pci_get_drvdata(pdev);
14706 struct tg3 *tp = netdev_priv(dev);
14709 release_firmware(tp->fw);
14711 flush_scheduled_work();
14713 if (tp->tg3_flags3 & TG3_FLG3_USE_PHYLIB) {
14718 unregister_netdev(dev);
14720 iounmap(tp->aperegs);
14721 tp->aperegs = NULL;
14728 pci_release_regions(pdev);
14729 pci_disable_device(pdev);
14730 pci_set_drvdata(pdev, NULL);
14734 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
14736 struct net_device *dev = pci_get_drvdata(pdev);
14737 struct tg3 *tp = netdev_priv(dev);
14738 pci_power_t target_state;
14741 /* PCI register 4 needs to be saved whether netif_running() or not.
14742 * MSI address and data need to be saved if using MSI and
14745 pci_save_state(pdev);
14747 if (!netif_running(dev))
14750 flush_scheduled_work();
14752 tg3_netif_stop(tp);
14754 del_timer_sync(&tp->timer);
14756 tg3_full_lock(tp, 1);
14757 tg3_disable_ints(tp);
14758 tg3_full_unlock(tp);
14760 netif_device_detach(dev);
14762 tg3_full_lock(tp, 0);
14763 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
14764 tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
14765 tg3_full_unlock(tp);
14767 target_state = pdev->pm_cap ? pci_target_state(pdev) : PCI_D3hot;
14769 err = tg3_set_power_state(tp, target_state);
14773 tg3_full_lock(tp, 0);
14775 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14776 err2 = tg3_restart_hw(tp, 1);
14780 tp->timer.expires = jiffies + tp->timer_offset;
14781 add_timer(&tp->timer);
14783 netif_device_attach(dev);
14784 tg3_netif_start(tp);
14787 tg3_full_unlock(tp);
14796 static int tg3_resume(struct pci_dev *pdev)
14798 struct net_device *dev = pci_get_drvdata(pdev);
14799 struct tg3 *tp = netdev_priv(dev);
14802 pci_restore_state(tp->pdev);
14804 if (!netif_running(dev))
14807 err = tg3_set_power_state(tp, PCI_D0);
14811 netif_device_attach(dev);
14813 tg3_full_lock(tp, 0);
14815 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
14816 err = tg3_restart_hw(tp, 1);
14820 tp->timer.expires = jiffies + tp->timer_offset;
14821 add_timer(&tp->timer);
14823 tg3_netif_start(tp);
14826 tg3_full_unlock(tp);
14834 static struct pci_driver tg3_driver = {
14835 .name = DRV_MODULE_NAME,
14836 .id_table = tg3_pci_tbl,
14837 .probe = tg3_init_one,
14838 .remove = __devexit_p(tg3_remove_one),
14839 .suspend = tg3_suspend,
14840 .resume = tg3_resume
14843 static int __init tg3_init(void)
14845 return pci_register_driver(&tg3_driver);
14848 static void __exit tg3_cleanup(void)
14850 pci_unregister_driver(&tg3_driver);
14853 module_init(tg3_init);
14854 module_exit(tg3_cleanup);