drivers/net/tg3.c

   1 /*
   2  * tg3.c: Broadcom Tigon3 ethernet driver.
   3  *
   4  * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
   5  * Copyright (C) 2001, 2002, 2003 Jeff Garzik (jgarzik@pobox.com)
   6  * Copyright (C) 2004 Sun Microsystems Inc.
   7  * Copyright (C) 2005 Broadcom Corporation.
   8  *
   9  * Firmware is:
  10  *      Derived from proprietary unpublished source code,
  11  *      Copyright (C) 2000-2003 Broadcom Corporation.
  12  *
  13  *      Permission is hereby granted for the distribution of this firmware
  14  *      data in hexadecimal or equivalent format, provided this copyright
  15  *      notice is accompanying it.
  16  */
  17
  18
  19 #include <linux/module.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kernel.h>
  22 #include <linux/types.h>
  23 #include <linux/compiler.h>
  24 #include <linux/slab.h>
  25 #include <linux/delay.h>
  26 #include <linux/in.h>
  27 #include <linux/init.h>
  28 #include <linux/ioport.h>
  29 #include <linux/pci.h>
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/skbuff.h>
  33 #include <linux/ethtool.h>
  34 #include <linux/mii.h>
  35 #include <linux/if_vlan.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/workqueue.h>
  39 #include <linux/prefetch.h>
  40 #include <linux/dma-mapping.h>
  41
  42 #include <net/checksum.h>
  43
  44 #include <asm/system.h>
  45 #include <asm/io.h>
  46 #include <asm/byteorder.h>
  47 #include <asm/uaccess.h>
  48
  49 #ifdef CONFIG_SPARC64
  50 #include <asm/idprom.h>
  51 #include <asm/oplib.h>
  52 #include <asm/pbm.h>
  53 #endif
  54
  55 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  56 #define TG3_VLAN_TAG_USED 1
  57 #else
  58 #define TG3_VLAN_TAG_USED 0
  59 #endif
  60
  61 #define TG3_TSO_SUPPORT 1
  62
  63 #include "tg3.h"
  64
  65 #define DRV_MODULE_NAME         "tg3"
  66 #define PFX DRV_MODULE_NAME     ": "
  67 #define DRV_MODULE_VERSION      "3.72"
  68 #define DRV_MODULE_RELDATE      "January 8, 2007"
  69
  70 #define TG3_DEF_MAC_MODE        0
  71 #define TG3_DEF_RX_MODE         0
  72 #define TG3_DEF_TX_MODE         0
  73 #define TG3_DEF_MSG_ENABLE        \
  74         (NETIF_MSG_DRV          | \
  75          NETIF_MSG_PROBE        | \
  76          NETIF_MSG_LINK         | \
  77          NETIF_MSG_TIMER        | \
  78          NETIF_MSG_IFDOWN       | \
  79          NETIF_MSG_IFUP         | \
  80          NETIF_MSG_RX_ERR       | \
  81          NETIF_MSG_TX_ERR)
  82
  83 /* length of time before we decide the hardware is borked,
  84  * and dev->tx_timeout() should be called to fix the problem
  85  */
  86 #define TG3_TX_TIMEOUT                  (5 * HZ)
  87
  88 /* hardware minimum and maximum for a single frame's data payload */
  89 #define TG3_MIN_MTU                     60
  90 #define TG3_MAX_MTU(tp) \
  91         ((tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) ? 9000 : 1500)
  92
  93 /* These numbers seem to be hard coded in the NIC firmware somehow.
  94  * You can't change the ring sizes, but you can change where you place
  95  * them in the NIC onboard memory.
  96  */
  97 #define TG3_RX_RING_SIZE                512
  98 #define TG3_DEF_RX_RING_PENDING         200
  99 #define TG3_RX_JUMBO_RING_SIZE          256
 100 #define TG3_DEF_RX_JUMBO_RING_PENDING   100
 101
 102 /* Do not place this n-ring entries value into the tp struct itself,
 103  * we really want to expose these constants to GCC so that modulo et
 104  * al.  operations are done with shifts and masks instead of with
 105  * hw multiply/modulo instructions.  Another solution would be to
 106  * replace things like '% foo' with '& (foo - 1)'.
 107  */
 108 #define TG3_RX_RCB_RING_SIZE(tp)        \
 109         ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ?  512 : 1024)
 110
 111 #define TG3_TX_RING_SIZE                512
 112 #define TG3_DEF_TX_RING_PENDING         (TG3_TX_RING_SIZE - 1)
 113
 114 #define TG3_RX_RING_BYTES       (sizeof(struct tg3_rx_buffer_desc) * \
 115                                  TG3_RX_RING_SIZE)
 116 #define TG3_RX_JUMBO_RING_BYTES (sizeof(struct tg3_rx_buffer_desc) * \
 117                                  TG3_RX_JUMBO_RING_SIZE)
 118 #define TG3_RX_RCB_RING_BYTES(tp) (sizeof(struct tg3_rx_buffer_desc) * \
 119                                    TG3_RX_RCB_RING_SIZE(tp))
 120 #define TG3_TX_RING_BYTES       (sizeof(struct tg3_tx_buffer_desc) * \
 121                                  TG3_TX_RING_SIZE)
 122 #define NEXT_TX(N)              (((N) + 1) & (TG3_TX_RING_SIZE - 1))
 123
 124 #define RX_PKT_BUF_SZ           (1536 + tp->rx_offset + 64)
 125 #define RX_JUMBO_PKT_BUF_SZ     (9046 + tp->rx_offset + 64)
 126
 127 /* minimum number of free TX descriptors required to wake up TX process */
 128 #define TG3_TX_WAKEUP_THRESH(tp)                ((tp)->tx_pending / 4)
 129
 130 /* number of ETHTOOL_GSTATS u64's */
 131 #define TG3_NUM_STATS           (sizeof(struct tg3_ethtool_stats)/sizeof(u64))
 132
 133 #define TG3_NUM_TEST            6
 134
 135 static char version[] __devinitdata =
 136         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
 137
 138 MODULE_AUTHOR("David S. Miller (davem@redhat.com) and Jeff Garzik (jgarzik@pobox.com)");
 139 MODULE_DESCRIPTION("Broadcom Tigon3 ethernet driver");
 140 MODULE_LICENSE("GPL");
 141 MODULE_VERSION(DRV_MODULE_VERSION);
 142
 143 static int tg3_debug = -1;      /* -1 == use TG3_DEF_MSG_ENABLE as value */
 144 module_param(tg3_debug, int, 0);
 145 MODULE_PARM_DESC(tg3_debug, "Tigon3 bitmapped debugging message enable value");
 146
 147 static struct pci_device_id tg3_pci_tbl[] = {
 148         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5700)},
 149         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5701)},
 150         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702)},
 151         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703)},
 152         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704)},
 153         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702FE)},
 154         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705)},
 155         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705_2)},
 156         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M)},
 157         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705M_2)},
 158         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702X)},
 159         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703X)},
 160         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S)},
 161         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5702A3)},
 162         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5703A3)},
 163         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5782)},
 164         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5788)},
 165         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5789)},
 166         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901)},
 167         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5901_2)},
 168         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5704S_2)},
 169         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5705F)},
 170         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5720)},
 171         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5721)},
 172         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5722)},
 173         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750)},
 174         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751)},
 175         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5750M)},
 176         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751M)},
 177         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F)},
 178         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752)},
 179         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752M)},
 180         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753)},
 181         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M)},
 182         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F)},
 183         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754)},
 184         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5754M)},
 185         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755)},
 186         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5755M)},
 187         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5756)},
 188         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5786)},
 189         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787)},
 190         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787M)},
 191         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5787F)},
 192         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714)},
 193         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5714S)},
 194         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715)},
 195         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5715S)},
 196         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780)},
 197         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S)},
 198         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781)},
 199         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906)},
 200         {PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5906M)},
 201         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX)},
 202         {PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9MXX)},
 203         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1000)},
 204         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1001)},
 205         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC1003)},
 206         {PCI_DEVICE(PCI_VENDOR_ID_ALTIMA, PCI_DEVICE_ID_ALTIMA_AC9100)},
 207         {PCI_DEVICE(PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_TIGON3)},
 208         {}
 209 };
 210
 211 MODULE_DEVICE_TABLE(pci, tg3_pci_tbl);
 212
 213 static const struct {
 214         const char string[ETH_GSTRING_LEN];
 215 } ethtool_stats_keys[TG3_NUM_STATS] = {
 216         { "rx_octets" },
 217         { "rx_fragments" },
 218         { "rx_ucast_packets" },
 219         { "rx_mcast_packets" },
 220         { "rx_bcast_packets" },
 221         { "rx_fcs_errors" },
 222         { "rx_align_errors" },
 223         { "rx_xon_pause_rcvd" },
 224         { "rx_xoff_pause_rcvd" },
 225         { "rx_mac_ctrl_rcvd" },
 226         { "rx_xoff_entered" },
 227         { "rx_frame_too_long_errors" },
 228         { "rx_jabbers" },
 229         { "rx_undersize_packets" },
 230         { "rx_in_length_errors" },
 231         { "rx_out_length_errors" },
 232         { "rx_64_or_less_octet_packets" },
 233         { "rx_65_to_127_octet_packets" },
 234         { "rx_128_to_255_octet_packets" },
 235         { "rx_256_to_511_octet_packets" },
 236         { "rx_512_to_1023_octet_packets" },
 237         { "rx_1024_to_1522_octet_packets" },
 238         { "rx_1523_to_2047_octet_packets" },
 239         { "rx_2048_to_4095_octet_packets" },
 240         { "rx_4096_to_8191_octet_packets" },
 241         { "rx_8192_to_9022_octet_packets" },
 242
 243         { "tx_octets" },
 244         { "tx_collisions" },
 245
 246         { "tx_xon_sent" },
 247         { "tx_xoff_sent" },
 248         { "tx_flow_control" },
 249         { "tx_mac_errors" },
 250         { "tx_single_collisions" },
 251         { "tx_mult_collisions" },
 252         { "tx_deferred" },
 253         { "tx_excessive_collisions" },
 254         { "tx_late_collisions" },
 255         { "tx_collide_2times" },
 256         { "tx_collide_3times" },
 257         { "tx_collide_4times" },
 258         { "tx_collide_5times" },
 259         { "tx_collide_6times" },
 260         { "tx_collide_7times" },
 261         { "tx_collide_8times" },
 262         { "tx_collide_9times" },
 263         { "tx_collide_10times" },
 264         { "tx_collide_11times" },
 265         { "tx_collide_12times" },
 266         { "tx_collide_13times" },
 267         { "tx_collide_14times" },
 268         { "tx_collide_15times" },
 269         { "tx_ucast_packets" },
 270         { "tx_mcast_packets" },
 271         { "tx_bcast_packets" },
 272         { "tx_carrier_sense_errors" },
 273         { "tx_discards" },
 274         { "tx_errors" },
 275
 276         { "dma_writeq_full" },
 277         { "dma_write_prioq_full" },
 278         { "rxbds_empty" },
 279         { "rx_discards" },
 280         { "rx_errors" },
 281         { "rx_threshold_hit" },
 282
 283         { "dma_readq_full" },
 284         { "dma_read_prioq_full" },
 285         { "tx_comp_queue_full" },
 286
 287         { "ring_set_send_prod_index" },
 288         { "ring_status_update" },
 289         { "nic_irqs" },
 290         { "nic_avoided_irqs" },
 291         { "nic_tx_threshold_hit" }
 292 };
 293
 294 static const struct {
 295         const char string[ETH_GSTRING_LEN];
 296 } ethtool_test_keys[TG3_NUM_TEST] = {
 297         { "nvram test     (online) " },
 298         { "link test      (online) " },
 299         { "register test  (offline)" },
 300         { "memory test    (offline)" },
 301         { "loopback test  (offline)" },
 302         { "interrupt test (offline)" },
 303 };
 304
 305 static void tg3_write32(struct tg3 *tp, u32 off, u32 val)
 306 {
 307         writel(val, tp->regs + off);
 308 }
 309
 310 static u32 tg3_read32(struct tg3 *tp, u32 off)
 311 {
 312         return (readl(tp->regs + off));
 313 }
 314
 315 static void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val)
 316 {
 317         unsigned long flags;
 318
 319         spin_lock_irqsave(&tp->indirect_lock, flags);
 320         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 321         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 322         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 323 }
 324
 325 static void tg3_write_flush_reg32(struct tg3 *tp, u32 off, u32 val)
 326 {
 327         writel(val, tp->regs + off);
 328         readl(tp->regs + off);
 329 }
 330
 331 static u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off)
 332 {
 333         unsigned long flags;
 334         u32 val;
 335
 336         spin_lock_irqsave(&tp->indirect_lock, flags);
 337         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off);
 338         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 339         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 340         return val;
 341 }
 342
 343 static void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val)
 344 {
 345         unsigned long flags;
 346
 347         if (off == (MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW)) {
 348                 pci_write_config_dword(tp->pdev, TG3PCI_RCV_RET_RING_CON_IDX +
 349                                        TG3_64BIT_REG_LOW, val);
 350                 return;
 351         }
 352         if (off == (MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW)) {
 353                 pci_write_config_dword(tp->pdev, TG3PCI_STD_RING_PROD_IDX +
 354                                        TG3_64BIT_REG_LOW, val);
 355                 return;
 356         }
 357
 358         spin_lock_irqsave(&tp->indirect_lock, flags);
 359         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 360         pci_write_config_dword(tp->pdev, TG3PCI_REG_DATA, val);
 361         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 362
 363         /* In indirect mode when disabling interrupts, we also need
 364          * to clear the interrupt bit in the GRC local ctrl register.
 365          */
 366         if ((off == (MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW)) &&
 367             (val == 0x1)) {
 368                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_LOCAL_CTRL,
 369                                        tp->grc_local_ctrl|GRC_LCLCTRL_CLEARINT);
 370         }
 371 }
 372
 373 static u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off)
 374 {
 375         unsigned long flags;
 376         u32 val;
 377
 378         spin_lock_irqsave(&tp->indirect_lock, flags);
 379         pci_write_config_dword(tp->pdev, TG3PCI_REG_BASE_ADDR, off + 0x5600);
 380         pci_read_config_dword(tp->pdev, TG3PCI_REG_DATA, &val);
 381         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 382         return val;
 383 }
 384
 385 /* usec_wait specifies the wait time in usec when writing to certain registers
 386  * where it is unsafe to read back the register without some delay.
 387  * GRC_LOCAL_CTRL is one example if the GPIOs are toggled to switch power.
 388  * TG3PCI_CLOCK_CTRL is another example if the clock frequencies are changed.
 389  */
 390 static void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait)
 391 {
 392         if ((tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) ||
 393             (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 394                 /* Non-posted methods */
 395                 tp->write32(tp, off, val);
 396         else {
 397                 /* Posted method */
 398                 tg3_write32(tp, off, val);
 399                 if (usec_wait)
 400                         udelay(usec_wait);
 401                 tp->read32(tp, off);
 402         }
 403         /* Wait again after the read for the posted method to guarantee that
 404          * the wait time is met.
 405          */
 406         if (usec_wait)
 407                 udelay(usec_wait);
 408 }
 409
 410 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
 411 {
 412         tp->write32_mbox(tp, off, val);
 413         if (!(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) &&
 414             !(tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND))
 415                 tp->read32_mbox(tp, off);
 416 }
 417
 418 static void tg3_write32_tx_mbox(struct tg3 *tp, u32 off, u32 val)
 419 {
 420         void __iomem *mbox = tp->regs + off;
 421         writel(val, mbox);
 422         if (tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG)
 423                 writel(val, mbox);
 424         if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
 425                 readl(mbox);
 426 }
 427
 428 static u32 tg3_read32_mbox_5906(struct tg3 *tp, u32 off)
 429 {
 430         return (readl(tp->regs + off + GRCMBOX_BASE));
 431 }
 432
 433 static void tg3_write32_mbox_5906(struct tg3 *tp, u32 off, u32 val)
 434 {
 435         writel(val, tp->regs + off + GRCMBOX_BASE);
 436 }
 437
 438 #define tw32_mailbox(reg, val)  tp->write32_mbox(tp, reg, val)
 439 #define tw32_mailbox_f(reg, val)        tw32_mailbox_flush(tp, (reg), (val))
 440 #define tw32_rx_mbox(reg, val)  tp->write32_rx_mbox(tp, reg, val)
 441 #define tw32_tx_mbox(reg, val)  tp->write32_tx_mbox(tp, reg, val)
 442 #define tr32_mailbox(reg)       tp->read32_mbox(tp, reg)
 443
 444 #define tw32(reg,val)           tp->write32(tp, reg, val)
 445 #define tw32_f(reg,val)         _tw32_flush(tp,(reg),(val), 0)
 446 #define tw32_wait_f(reg,val,us) _tw32_flush(tp,(reg),(val), (us))
 447 #define tr32(reg)               tp->read32(tp, reg)
 448
 449 static void tg3_write_mem(struct tg3 *tp, u32 off, u32 val)
 450 {
 451         unsigned long flags;
 452
 453         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 454             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC))
 455                 return;
 456
 457         spin_lock_irqsave(&tp->indirect_lock, flags);
 458         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 459                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 460                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 461
 462                 /* Always leave this as zero. */
 463                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 464         } else {
 465                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 466                 tw32_f(TG3PCI_MEM_WIN_DATA, val);
 467
 468                 /* Always leave this as zero. */
 469                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 470         }
 471         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 472 }
 473
 474 static void tg3_read_mem(struct tg3 *tp, u32 off, u32 *val)
 475 {
 476         unsigned long flags;
 477
 478         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) &&
 479             (off >= NIC_SRAM_STATS_BLK) && (off < NIC_SRAM_TX_BUFFER_DESC)) {
 480                 *val = 0;
 481                 return;
 482         }
 483
 484         spin_lock_irqsave(&tp->indirect_lock, flags);
 485         if (tp->tg3_flags & TG3_FLAG_SRAM_USE_CONFIG) {
 486                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, off);
 487                 pci_read_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
 488
 489                 /* Always leave this as zero. */
 490                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
 491         } else {
 492                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, off);
 493                 *val = tr32(TG3PCI_MEM_WIN_DATA);
 494
 495                 /* Always leave this as zero. */
 496                 tw32_f(TG3PCI_MEM_WIN_BASE_ADDR, 0);
 497         }
 498         spin_unlock_irqrestore(&tp->indirect_lock, flags);
 499 }
 500
 501 static void tg3_disable_ints(struct tg3 *tp)
 502 {
 503         tw32(TG3PCI_MISC_HOST_CTRL,
 504              (tp->misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT));
 505         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
 506 }
 507
 508 static inline void tg3_cond_int(struct tg3 *tp)
 509 {
 510         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 511             (tp->hw_status->status & SD_STATUS_UPDATED))
 512                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
 513         else
 514                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 515                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 516 }
 517
 518 static void tg3_enable_ints(struct tg3 *tp)
 519 {
 520         tp->irq_sync = 0;
 521         wmb();
 522
 523         tw32(TG3PCI_MISC_HOST_CTRL,
 524              (tp->misc_host_ctrl & ~MISC_HOST_CTRL_MASK_PCI_INT));
 525         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 526                        (tp->last_tag << 24));
 527         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
 528                 tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 529                                (tp->last_tag << 24));
 530         tg3_cond_int(tp);
 531 }
 532
 533 static inline unsigned int tg3_has_work(struct tg3 *tp)
 534 {
 535         struct tg3_hw_status *sblk = tp->hw_status;
 536         unsigned int work_exists = 0;
 537
 538         /* check for phy events */
 539         if (!(tp->tg3_flags &
 540               (TG3_FLAG_USE_LINKCHG_REG |
 541                TG3_FLAG_POLL_SERDES))) {
 542                 if (sblk->status & SD_STATUS_LINK_CHG)
 543                         work_exists = 1;
 544         }
 545         /* check for RX/TX work to do */
 546         if (sblk->idx[0].tx_consumer != tp->tx_cons ||
 547             sblk->idx[0].rx_producer != tp->rx_rcb_ptr)
 548                 work_exists = 1;
 549
 550         return work_exists;
 551 }
 552
 553 /* tg3_restart_ints
 554  *  similar to tg3_enable_ints, but it accurately determines whether there
 555  *  is new work pending and can return without flushing the PIO write
 556  *  which reenables interrupts
 557  */
 558 static void tg3_restart_ints(struct tg3 *tp)
 559 {
 560         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
 561                      tp->last_tag << 24);
 562         mmiowb();
 563
 564         /* When doing tagged status, this work check is unnecessary.
 565          * The last_tag we write above tells the chip which piece of
 566          * work we've completed.
 567          */
 568         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) &&
 569             tg3_has_work(tp))
 570                 tw32(HOSTCC_MODE, tp->coalesce_mode |
 571                      (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
 572 }
 573
 574 static inline void tg3_netif_stop(struct tg3 *tp)
 575 {
 576         tp->dev->trans_start = jiffies; /* prevent tx timeout */
 577         netif_poll_disable(tp->dev);
 578         netif_tx_disable(tp->dev);
 579 }
 580
 581 static inline void tg3_netif_start(struct tg3 *tp)
 582 {
 583         netif_wake_queue(tp->dev);
 584         /* NOTE: unconditional netif_wake_queue is only appropriate
 585          * so long as all callers are assured to have free tx slots
 586          * (such as after tg3_init_hw)
 587          */
 588         netif_poll_enable(tp->dev);
 589         tp->hw_status->status |= SD_STATUS_UPDATED;
 590         tg3_enable_ints(tp);
 591 }
 592
 593 static void tg3_switch_clocks(struct tg3 *tp)
 594 {
 595         u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
 596         u32 orig_clock_ctrl;
 597
 598         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
 599                 return;
 600
 601         orig_clock_ctrl = clock_ctrl;
 602         clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
 603                        CLOCK_CTRL_CLKRUN_OENABLE |
 604                        0x1f);
 605         tp->pci_clock_ctrl = clock_ctrl;
 606
 607         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
 608                 if (orig_clock_ctrl & CLOCK_CTRL_625_CORE) {
 609                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
 610                                     clock_ctrl | CLOCK_CTRL_625_CORE, 40);
 611                 }
 612         } else if ((orig_clock_ctrl & CLOCK_CTRL_44MHZ_CORE) != 0) {
 613                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 614                             clock_ctrl |
 615                             (CLOCK_CTRL_44MHZ_CORE | CLOCK_CTRL_ALTCLK),
 616                             40);
 617                 tw32_wait_f(TG3PCI_CLOCK_CTRL,
 618                             clock_ctrl | (CLOCK_CTRL_ALTCLK),
 619                             40);
 620         }
 621         tw32_wait_f(TG3PCI_CLOCK_CTRL, clock_ctrl, 40);
 622 }
 623
 624 #define PHY_BUSY_LOOPS  5000
 625
 626 static int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
 627 {
 628         u32 frame_val;
 629         unsigned int loops;
 630         int ret;
 631
 632         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 633                 tw32_f(MAC_MI_MODE,
 634                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 635                 udelay(80);
 636         }
 637
 638         *val = 0x0;
 639
 640         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 641                       MI_COM_PHY_ADDR_MASK);
 642         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 643                       MI_COM_REG_ADDR_MASK);
 644         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 645
 646         tw32_f(MAC_MI_COM, frame_val);
 647
 648         loops = PHY_BUSY_LOOPS;
 649         while (loops != 0) {
 650                 udelay(10);
 651                 frame_val = tr32(MAC_MI_COM);
 652
 653                 if ((frame_val & MI_COM_BUSY) == 0) {
 654                         udelay(5);
 655                         frame_val = tr32(MAC_MI_COM);
 656                         break;
 657                 }
 658                 loops -= 1;
 659         }
 660
 661         ret = -EBUSY;
 662         if (loops != 0) {
 663                 *val = frame_val & MI_COM_DATA_MASK;
 664                 ret = 0;
 665         }
 666
 667         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 668                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 669                 udelay(80);
 670         }
 671
 672         return ret;
 673 }
 674
 675 static int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 676 {
 677         u32 frame_val;
 678         unsigned int loops;
 679         int ret;
 680
 681         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 &&
 682             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 683                 return 0;
 684
 685         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 686                 tw32_f(MAC_MI_MODE,
 687                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 688                 udelay(80);
 689         }
 690
 691         frame_val  = ((PHY_ADDR << MI_COM_PHY_ADDR_SHIFT) &
 692                       MI_COM_PHY_ADDR_MASK);
 693         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 694                       MI_COM_REG_ADDR_MASK);
 695         frame_val |= (val & MI_COM_DATA_MASK);
 696         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 697
 698         tw32_f(MAC_MI_COM, frame_val);
 699
 700         loops = PHY_BUSY_LOOPS;
 701         while (loops != 0) {
 702                 udelay(10);
 703                 frame_val = tr32(MAC_MI_COM);
 704                 if ((frame_val & MI_COM_BUSY) == 0) {
 705                         udelay(5);
 706                         frame_val = tr32(MAC_MI_COM);
 707                         break;
 708                 }
 709                 loops -= 1;
 710         }
 711
 712         ret = -EBUSY;
 713         if (loops != 0)
 714                 ret = 0;
 715
 716         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 717                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 718                 udelay(80);
 719         }
 720
 721         return ret;
 722 }
 723
 724 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 725 {
 726         u32 val;
 727
 728         if (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED)
 729                 return;
 730
 731         if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x7007) &&
 732             !tg3_readphy(tp, MII_TG3_AUX_CTRL, &val))
 733                 tg3_writephy(tp, MII_TG3_AUX_CTRL,
 734                              (val | (1 << 15) | (1 << 4)));
 735 }
 736
 737 static int tg3_bmcr_reset(struct tg3 *tp)
 738 {
 739         u32 phy_control;
 740         int limit, err;
 741
 742         /* OK, reset it, and poll the BMCR_RESET bit until it
 743          * clears or we time out.
 744          */
 745         phy_control = BMCR_RESET;
 746         err = tg3_writephy(tp, MII_BMCR, phy_control);
 747         if (err != 0)
 748                 return -EBUSY;
 749
 750         limit = 5000;
 751         while (limit--) {
 752                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 753                 if (err != 0)
 754                         return -EBUSY;
 755
 756                 if ((phy_control & BMCR_RESET) == 0) {
 757                         udelay(40);
 758                         break;
 759                 }
 760                 udelay(10);
 761         }
 762         if (limit <= 0)
 763                 return -EBUSY;
 764
 765         return 0;
 766 }
 767
 768 static int tg3_wait_macro_done(struct tg3 *tp)
 769 {
 770         int limit = 100;
 771
 772         while (limit--) {
 773                 u32 tmp32;
 774
 775                 if (!tg3_readphy(tp, 0x16, &tmp32)) {
 776                         if ((tmp32 & 0x1000) == 0)
 777                                 break;
 778                 }
 779         }
 780         if (limit <= 0)
 781                 return -EBUSY;
 782
 783         return 0;
 784 }
 785
 786 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 787 {
 788         static const u32 test_pat[4][6] = {
 789         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 790         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 791         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 792         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 793         };
 794         int chan;
 795
 796         for (chan = 0; chan < 4; chan++) {
 797                 int i;
 798
 799                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 800                              (chan * 0x2000) | 0x0200);
 801                 tg3_writephy(tp, 0x16, 0x0002);
 802
 803                 for (i = 0; i < 6; i++)
 804                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 805                                      test_pat[chan][i]);
 806
 807                 tg3_writephy(tp, 0x16, 0x0202);
 808                 if (tg3_wait_macro_done(tp)) {
 809                         *resetp = 1;
 810                         return -EBUSY;
 811                 }
 812
 813                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 814                              (chan * 0x2000) | 0x0200);
 815                 tg3_writephy(tp, 0x16, 0x0082);
 816                 if (tg3_wait_macro_done(tp)) {
 817                         *resetp = 1;
 818                         return -EBUSY;
 819                 }
 820
 821                 tg3_writephy(tp, 0x16, 0x0802);
 822                 if (tg3_wait_macro_done(tp)) {
 823                         *resetp = 1;
 824                         return -EBUSY;
 825                 }
 826
 827                 for (i = 0; i < 6; i += 2) {
 828                         u32 low, high;
 829
 830                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 831                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 832                             tg3_wait_macro_done(tp)) {
 833                                 *resetp = 1;
 834                                 return -EBUSY;
 835                         }
 836                         low &= 0x7fff;
 837                         high &= 0x000f;
 838                         if (low != test_pat[chan][i] ||
 839                             high != test_pat[chan][i+1]) {
 840                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 841                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 842                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 843
 844                                 return -EBUSY;
 845                         }
 846                 }
 847         }
 848
 849         return 0;
 850 }
 851
 852 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 853 {
 854         int chan;
 855
 856         for (chan = 0; chan < 4; chan++) {
 857                 int i;
 858
 859                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 860                              (chan * 0x2000) | 0x0200);
 861                 tg3_writephy(tp, 0x16, 0x0002);
 862                 for (i = 0; i < 6; i++)
 863                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 864                 tg3_writephy(tp, 0x16, 0x0202);
 865                 if (tg3_wait_macro_done(tp))
 866                         return -EBUSY;
 867         }
 868
 869         return 0;
 870 }
 871
 872 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 873 {
 874         u32 reg32, phy9_orig;
 875         int retries, do_phy_reset, err;
 876
 877         retries = 10;
 878         do_phy_reset = 1;
 879         do {
 880                 if (do_phy_reset) {
 881                         err = tg3_bmcr_reset(tp);
 882                         if (err)
 883                                 return err;
 884                         do_phy_reset = 0;
 885                 }
 886
 887                 /* Disable transmitter and interrupt.  */
 888                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 889                         continue;
 890
 891                 reg32 |= 0x3000;
 892                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 893
 894                 /* Set full-duplex, 1000 mbps.  */
 895                 tg3_writephy(tp, MII_BMCR,
 896                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 897
 898                 /* Set to master mode.  */
 899                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 900                         continue;
 901
 902                 tg3_writephy(tp, MII_TG3_CTRL,
 903                              (MII_TG3_CTRL_AS_MASTER |
 904                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 905
 906                 /* Enable SM_DSP_CLOCK and 6dB.  */
 907                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 908
 909                 /* Block the PHY control access.  */
 910                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 911                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
 912
 913                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 914                 if (!err)
 915                         break;
 916         } while (--retries);
 917
 918         err = tg3_phy_reset_chanpat(tp);
 919         if (err)
 920                 return err;
 921
 922         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
 923         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
 924
 925         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 926         tg3_writephy(tp, 0x16, 0x0000);
 927
 928         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 929             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
 930                 /* Set Extended packet length bit for jumbo frames */
 931                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4400);
 932         }
 933         else {
 934                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 935         }
 936
 937         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 938
 939         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 940                 reg32 &= ~0x3000;
 941                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 942         } else if (!err)
 943                 err = -EBUSY;
 944
 945         return err;
 946 }
 947
 948 static void tg3_link_report(struct tg3 *);
 949
 950 /* This will reset the tigon3 PHY if there is no valid
 951  * link unless the FORCE argument is non-zero.
 952  */
 953 static int tg3_phy_reset(struct tg3 *tp)
 954 {
 955         u32 phy_status;
 956         int err;
 957
 958         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 959                 u32 val;
 960
 961                 val = tr32(GRC_MISC_CFG);
 962                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
 963                 udelay(40);
 964         }
 965         err  = tg3_readphy(tp, MII_BMSR, &phy_status);
 966         err |= tg3_readphy(tp, MII_BMSR, &phy_status);
 967         if (err != 0)
 968                 return -EBUSY;
 969
 970         if (netif_running(tp->dev) && netif_carrier_ok(tp->dev)) {
 971                 netif_carrier_off(tp->dev);
 972                 tg3_link_report(tp);
 973         }
 974
 975         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 976             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 977             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 978                 err = tg3_phy_reset_5703_4_5(tp);
 979                 if (err)
 980                         return err;
 981                 goto out;
 982         }
 983
 984         err = tg3_bmcr_reset(tp);
 985         if (err)
 986                 return err;
 987
 988 out:
 989         if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
 990                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
 991                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
 992                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
 993                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 994                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
 995                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
 996         }
 997         if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
 998                 tg3_writephy(tp, 0x1c, 0x8d68);
 999                 tg3_writephy(tp, 0x1c, 0x8d68);
1000         }
1001         if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
1002                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1003                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1004                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
1005                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1006                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
1007                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
1008                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
1009                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1010         }
1011         else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
1012                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
1013                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
1014                 if (tp->tg3_flags2 & TG3_FLG2_PHY_ADJUST_TRIM) {
1015                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
1016                         tg3_writephy(tp, MII_TG3_TEST1,
1017                                      MII_TG3_TEST1_TRIM_EN | 0x4);
1018                 } else
1019                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
1020                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
1021         }
1022         /* Set Extended packet length bit (bit 14) on all chips that */
1023         /* support jumbo frames */
1024         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1025                 /* Cannot do read-modify-write on 5401 */
1026                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1027         } else if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1028                 u32 phy_reg;
1029
1030                 /* Set bit 14 with read-modify-write to preserve other bits */
1031                 if (!tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0007) &&
1032                     !tg3_readphy(tp, MII_TG3_AUX_CTRL, &phy_reg))
1033                         tg3_writephy(tp, MII_TG3_AUX_CTRL, phy_reg | 0x4000);
1034         }
1035
1036         /* Set phy register 0x10 bit 0 to high fifo elasticity to support
1037          * jumbo frames transmission.
1038          */
1039         if (tp->tg3_flags2 & TG3_FLG2_JUMBO_CAPABLE) {
1040                 u32 phy_reg;
1041
1042                 if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
1043                     tg3_writephy(tp, MII_TG3_EXT_CTRL,
1044                                  phy_reg | MII_TG3_EXT_CTRL_FIFO_ELASTIC);
1045         }
1046
1047         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1048                 u32 phy_reg;
1049
1050                 /* adjust output voltage */
1051                 tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x12);
1052
1053                 if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phy_reg)) {
1054                         u32 phy_reg2;
1055
1056                         tg3_writephy(tp, MII_TG3_EPHY_TEST,
1057                                      phy_reg | MII_TG3_EPHY_SHADOW_EN);
1058                         /* Enable auto-MDIX */
1059                         if (!tg3_readphy(tp, 0x10, &phy_reg2))
1060                                 tg3_writephy(tp, 0x10, phy_reg2 | 0x4000);
1061                         tg3_writephy(tp, MII_TG3_EPHY_TEST, phy_reg);
1062                 }
1063         }
1064
1065         tg3_phy_set_wirespeed(tp);
1066         return 0;
1067 }
1068
1069 static void tg3_frob_aux_power(struct tg3 *tp)
1070 {
1071         struct tg3 *tp_peer = tp;
1072
1073         if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
1074                 return;
1075
1076         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
1077             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
1078                 struct net_device *dev_peer;
1079
1080                 dev_peer = pci_get_drvdata(tp->pdev_peer);
1081                 /* remove_one() may have been run on the peer. */
1082                 if (!dev_peer)
1083                         tp_peer = tp;
1084                 else
1085                         tp_peer = netdev_priv(dev_peer);
1086         }
1087
1088         if ((tp->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1089             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0 ||
1090             (tp_peer->tg3_flags & TG3_FLAG_WOL_ENABLE) != 0 ||
1091             (tp_peer->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
1092                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1093                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1094                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1095                                     (GRC_LCLCTRL_GPIO_OE0 |
1096                                      GRC_LCLCTRL_GPIO_OE1 |
1097                                      GRC_LCLCTRL_GPIO_OE2 |
1098                                      GRC_LCLCTRL_GPIO_OUTPUT0 |
1099                                      GRC_LCLCTRL_GPIO_OUTPUT1),
1100                                     100);
1101                 } else {
1102                         u32 no_gpio2;
1103                         u32 grc_local_ctrl = 0;
1104
1105                         if (tp_peer != tp &&
1106                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1107                                 return;
1108
1109                         /* Workaround to prevent overdrawing Amps. */
1110                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
1111                             ASIC_REV_5714) {
1112                                 grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
1113                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1114                                             grc_local_ctrl, 100);
1115                         }
1116
1117                         /* On 5753 and variants, GPIO2 cannot be used. */
1118                         no_gpio2 = tp->nic_sram_data_cfg &
1119                                     NIC_SRAM_DATA_CFG_NO_GPIO2;
1120
1121                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE0 |
1122                                          GRC_LCLCTRL_GPIO_OE1 |
1123                                          GRC_LCLCTRL_GPIO_OE2 |
1124                                          GRC_LCLCTRL_GPIO_OUTPUT1 |
1125                                          GRC_LCLCTRL_GPIO_OUTPUT2;
1126                         if (no_gpio2) {
1127                                 grc_local_ctrl &= ~(GRC_LCLCTRL_GPIO_OE2 |
1128                                                     GRC_LCLCTRL_GPIO_OUTPUT2);
1129                         }
1130                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1131                                                     grc_local_ctrl, 100);
1132
1133                         grc_local_ctrl |= GRC_LCLCTRL_GPIO_OUTPUT0;
1134
1135                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1136                                                     grc_local_ctrl, 100);
1137
1138                         if (!no_gpio2) {
1139                                 grc_local_ctrl &= ~GRC_LCLCTRL_GPIO_OUTPUT2;
1140                                 tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1141                                             grc_local_ctrl, 100);
1142                         }
1143                 }
1144         } else {
1145                 if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
1146                     GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
1147                         if (tp_peer != tp &&
1148                             (tp_peer->tg3_flags & TG3_FLAG_INIT_COMPLETE) != 0)
1149                                 return;
1150
1151                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1152                                     (GRC_LCLCTRL_GPIO_OE1 |
1153                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1154
1155                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1156                                     GRC_LCLCTRL_GPIO_OE1, 100);
1157
1158                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl |
1159                                     (GRC_LCLCTRL_GPIO_OE1 |
1160                                      GRC_LCLCTRL_GPIO_OUTPUT1), 100);
1161                 }
1162         }
1163 }
1164
1165 static int tg3_setup_phy(struct tg3 *, int);
1166
1167 #define RESET_KIND_SHUTDOWN     0
1168 #define RESET_KIND_INIT         1
1169 #define RESET_KIND_SUSPEND      2
1170
1171 static void tg3_write_sig_post_reset(struct tg3 *, int);
1172 static int tg3_halt_cpu(struct tg3 *, u32);
1173 static int tg3_nvram_lock(struct tg3 *);
1174 static void tg3_nvram_unlock(struct tg3 *);
1175
1176 static void tg3_power_down_phy(struct tg3 *tp)
1177 {
1178         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
1179                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
1180                         u32 sg_dig_ctrl = tr32(SG_DIG_CTRL);
1181                         u32 serdes_cfg = tr32(MAC_SERDES_CFG);
1182
1183                         sg_dig_ctrl |=
1184                                 SG_DIG_USING_HW_AUTONEG | SG_DIG_SOFT_RESET;
1185                         tw32(SG_DIG_CTRL, sg_dig_ctrl);
1186                         tw32(MAC_SERDES_CFG, serdes_cfg | (1 << 15));
1187                 }
1188                 return;
1189         }
1190
1191         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1192                 u32 val;
1193
1194                 tg3_bmcr_reset(tp);
1195                 val = tr32(GRC_MISC_CFG);
1196                 tw32_f(GRC_MISC_CFG, val | GRC_MISC_CFG_EPHY_IDDQ);
1197                 udelay(40);
1198                 return;
1199         } else {
1200                 tg3_writephy(tp, MII_TG3_EXT_CTRL,
1201                              MII_TG3_EXT_CTRL_FORCE_LED_OFF);
1202                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x01b2);
1203         }
1204
1205         /* The PHY should not be powered down on some chips because
1206          * of bugs.
1207          */
1208         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1209             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1210             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 &&
1211              (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)))
1212                 return;
1213         tg3_writephy(tp, MII_BMCR, BMCR_PDOWN);
1214 }
1215
1216 static int tg3_set_power_state(struct tg3 *tp, pci_power_t state)
1217 {
1218         u32 misc_host_ctrl;
1219         u16 power_control, power_caps;
1220         int pm = tp->pm_cap;
1221
1222         /* Make sure register accesses (indirect or otherwise)
1223          * will function correctly.
1224          */
1225         pci_write_config_dword(tp->pdev,
1226                                TG3PCI_MISC_HOST_CTRL,
1227                                tp->misc_host_ctrl);
1228
1229         pci_read_config_word(tp->pdev,
1230                              pm + PCI_PM_CTRL,
1231                              &power_control);
1232         power_control |= PCI_PM_CTRL_PME_STATUS;
1233         power_control &= ~(PCI_PM_CTRL_STATE_MASK);
1234         switch (state) {
1235         case PCI_D0:
1236                 power_control |= 0;
1237                 pci_write_config_word(tp->pdev,
1238                                       pm + PCI_PM_CTRL,
1239                                       power_control);
1240                 udelay(100);    /* Delay after power state change */
1241
1242                 /* Switch out of Vaux if it is a NIC */
1243                 if (tp->tg3_flags2 & TG3_FLG2_IS_NIC)
1244                         tw32_wait_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl, 100);
1245
1246                 return 0;
1247
1248         case PCI_D1:
1249                 power_control |= 1;
1250                 break;
1251
1252         case PCI_D2:
1253                 power_control |= 2;
1254                 break;
1255
1256         case PCI_D3hot:
1257                 power_control |= 3;
1258                 break;
1259
1260         default:
1261                 printk(KERN_WARNING PFX "%s: Invalid power state (%d) "
1262                        "requested.\n",
1263                        tp->dev->name, state);
1264                 return -EINVAL;
1265         };
1266
1267         power_control |= PCI_PM_CTRL_PME_ENABLE;
1268
1269         misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
1270         tw32(TG3PCI_MISC_HOST_CTRL,
1271              misc_host_ctrl | MISC_HOST_CTRL_MASK_PCI_INT);
1272
1273         if (tp->link_config.phy_is_low_power == 0) {
1274                 tp->link_config.phy_is_low_power = 1;
1275                 tp->link_config.orig_speed = tp->link_config.speed;
1276                 tp->link_config.orig_duplex = tp->link_config.duplex;
1277                 tp->link_config.orig_autoneg = tp->link_config.autoneg;
1278         }
1279
1280         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
1281                 tp->link_config.speed = SPEED_10;
1282                 tp->link_config.duplex = DUPLEX_HALF;
1283                 tp->link_config.autoneg = AUTONEG_ENABLE;
1284                 tg3_setup_phy(tp, 0);
1285         }
1286
1287         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1288                 u32 val;
1289
1290                 val = tr32(GRC_VCPU_EXT_CTRL);
1291                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_DISABLE_WOL);
1292         } else if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1293                 int i;
1294                 u32 val;
1295
1296                 for (i = 0; i < 200; i++) {
1297                         tg3_read_mem(tp, NIC_SRAM_FW_ASF_STATUS_MBOX, &val);
1298                         if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
1299                                 break;
1300                         msleep(1);
1301                 }
1302         }
1303         tg3_write_mem(tp, NIC_SRAM_WOL_MBOX, WOL_SIGNATURE |
1304                                              WOL_DRV_STATE_SHUTDOWN |
1305                                              WOL_DRV_WOL | WOL_SET_MAGIC_PKT);
1306
1307         pci_read_config_word(tp->pdev, pm + PCI_PM_PMC, &power_caps);
1308
1309         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE) {
1310                 u32 mac_mode;
1311
1312                 if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
1313                         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x5a);
1314                         udelay(40);
1315
1316                         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
1317                                 mac_mode = MAC_MODE_PORT_MODE_GMII;
1318                         else
1319                                 mac_mode = MAC_MODE_PORT_MODE_MII;
1320
1321                         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 ||
1322                             !(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB))
1323                                 mac_mode |= MAC_MODE_LINK_POLARITY;
1324                 } else {
1325                         mac_mode = MAC_MODE_PORT_MODE_TBI;
1326                 }
1327
1328                 if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
1329                         tw32(MAC_LED_CTRL, tp->led_ctrl);
1330
1331                 if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
1332                      (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)))
1333                         mac_mode |= MAC_MODE_MAGIC_PKT_ENABLE;
1334
1335                 tw32_f(MAC_MODE, mac_mode);
1336                 udelay(100);
1337
1338                 tw32_f(MAC_RX_MODE, RX_MODE_ENABLE);
1339                 udelay(10);
1340         }
1341
1342         if (!(tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB) &&
1343             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1344              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
1345                 u32 base_val;
1346
1347                 base_val = tp->pci_clock_ctrl;
1348                 base_val |= (CLOCK_CTRL_RXCLK_DISABLE |
1349                              CLOCK_CTRL_TXCLK_DISABLE);
1350
1351                 tw32_wait_f(TG3PCI_CLOCK_CTRL, base_val | CLOCK_CTRL_ALTCLK |
1352                             CLOCK_CTRL_PWRDOWN_PLL133, 40);
1353         } else if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
1354                    (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)) {
1355                 /* do nothing */
1356         } else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
1357                      (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {
1358                 u32 newbits1, newbits2;
1359
1360                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1361                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1362                         newbits1 = (CLOCK_CTRL_RXCLK_DISABLE |
1363                                     CLOCK_CTRL_TXCLK_DISABLE |
1364                                     CLOCK_CTRL_ALTCLK);
1365                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1366                 } else if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
1367                         newbits1 = CLOCK_CTRL_625_CORE;
1368                         newbits2 = newbits1 | CLOCK_CTRL_ALTCLK;
1369                 } else {
1370                         newbits1 = CLOCK_CTRL_ALTCLK;
1371                         newbits2 = newbits1 | CLOCK_CTRL_44MHZ_CORE;
1372                 }
1373
1374                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits1,
1375                             40);
1376
1377                 tw32_wait_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl | newbits2,
1378                             40);
1379
1380                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
1381                         u32 newbits3;
1382
1383                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1384                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1385                                 newbits3 = (CLOCK_CTRL_RXCLK_DISABLE |
1386                                             CLOCK_CTRL_TXCLK_DISABLE |
1387                                             CLOCK_CTRL_44MHZ_CORE);
1388                         } else {
1389                                 newbits3 = CLOCK_CTRL_44MHZ_CORE;
1390                         }
1391
1392                         tw32_wait_f(TG3PCI_CLOCK_CTRL,
1393                                     tp->pci_clock_ctrl | newbits3, 40);
1394                 }
1395         }
1396
1397         if (!(tp->tg3_flags & TG3_FLAG_WOL_ENABLE) &&
1398             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
1399                 tg3_power_down_phy(tp);
1400
1401         tg3_frob_aux_power(tp);
1402
1403         /* Workaround for unstable PLL clock */
1404         if ((GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_AX) ||
1405             (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5750_BX)) {
1406                 u32 val = tr32(0x7d00);
1407
1408                 val &= ~((1 << 16) | (1 << 4) | (1 << 2) | (1 << 1) | 1);
1409                 tw32(0x7d00, val);
1410                 if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
1411                         int err;
1412
1413                         err = tg3_nvram_lock(tp);
1414                         tg3_halt_cpu(tp, RX_CPU_BASE);
1415                         if (!err)
1416                                 tg3_nvram_unlock(tp);
1417                 }
1418         }
1419
1420         tg3_write_sig_post_reset(tp, RESET_KIND_SHUTDOWN);
1421
1422         /* Finally, set the new power state. */
1423         pci_write_config_word(tp->pdev, pm + PCI_PM_CTRL, power_control);
1424         udelay(100);    /* Delay after power state change */
1425
1426         return 0;
1427 }
1428
1429 static void tg3_link_report(struct tg3 *tp)
1430 {
1431         if (!netif_carrier_ok(tp->dev)) {
1432                 if (netif_msg_link(tp))
1433                         printk(KERN_INFO PFX "%s: Link is down.\n",
1434                                tp->dev->name);
1435         } else if (netif_msg_link(tp)) {
1436                 printk(KERN_INFO PFX "%s: Link is up at %d Mbps, %s duplex.\n",
1437                        tp->dev->name,
1438                        (tp->link_config.active_speed == SPEED_1000 ?
1439                         1000 :
1440                         (tp->link_config.active_speed == SPEED_100 ?
1441                          100 : 10)),
1442                        (tp->link_config.active_duplex == DUPLEX_FULL ?
1443                         "full" : "half"));
1444
1445                 printk(KERN_INFO PFX "%s: Flow control is %s for TX and "
1446                        "%s for RX.\n",
1447                        tp->dev->name,
1448                        (tp->tg3_flags & TG3_FLAG_TX_PAUSE) ? "on" : "off",
1449                        (tp->tg3_flags & TG3_FLAG_RX_PAUSE) ? "on" : "off");
1450         }
1451 }
1452
1453 static void tg3_setup_flow_control(struct tg3 *tp, u32 local_adv, u32 remote_adv)
1454 {
1455         u32 new_tg3_flags = 0;
1456         u32 old_rx_mode = tp->rx_mode;
1457         u32 old_tx_mode = tp->tx_mode;
1458
1459         if (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) {
1460
1461                 /* Convert 1000BaseX flow control bits to 1000BaseT
1462                  * bits before resolving flow control.
1463                  */
1464                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
1465                         local_adv &= ~(ADVERTISE_PAUSE_CAP |
1466                                        ADVERTISE_PAUSE_ASYM);
1467                         remote_adv &= ~(LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1468
1469                         if (local_adv & ADVERTISE_1000XPAUSE)
1470                                 local_adv |= ADVERTISE_PAUSE_CAP;
1471                         if (local_adv & ADVERTISE_1000XPSE_ASYM)
1472                                 local_adv |= ADVERTISE_PAUSE_ASYM;
1473                         if (remote_adv & LPA_1000XPAUSE)
1474                                 remote_adv |= LPA_PAUSE_CAP;
1475                         if (remote_adv & LPA_1000XPAUSE_ASYM)
1476                                 remote_adv |= LPA_PAUSE_ASYM;
1477                 }
1478
1479                 if (local_adv & ADVERTISE_PAUSE_CAP) {
1480                         if (local_adv & ADVERTISE_PAUSE_ASYM) {
1481                                 if (remote_adv & LPA_PAUSE_CAP)
1482                                         new_tg3_flags |=
1483                                                 (TG3_FLAG_RX_PAUSE |
1484                                                 TG3_FLAG_TX_PAUSE);
1485                                 else if (remote_adv & LPA_PAUSE_ASYM)
1486                                         new_tg3_flags |=
1487                                                 (TG3_FLAG_RX_PAUSE);
1488                         } else {
1489                                 if (remote_adv & LPA_PAUSE_CAP)
1490                                         new_tg3_flags |=
1491                                                 (TG3_FLAG_RX_PAUSE |
1492                                                 TG3_FLAG_TX_PAUSE);
1493                         }
1494                 } else if (local_adv & ADVERTISE_PAUSE_ASYM) {
1495                         if ((remote_adv & LPA_PAUSE_CAP) &&
1496                         (remote_adv & LPA_PAUSE_ASYM))
1497                                 new_tg3_flags |= TG3_FLAG_TX_PAUSE;
1498                 }
1499
1500                 tp->tg3_flags &= ~(TG3_FLAG_RX_PAUSE | TG3_FLAG_TX_PAUSE);
1501                 tp->tg3_flags |= new_tg3_flags;
1502         } else {
1503                 new_tg3_flags = tp->tg3_flags;
1504         }
1505
1506         if (new_tg3_flags & TG3_FLAG_RX_PAUSE)
1507                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1508         else
1509                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1510
1511         if (old_rx_mode != tp->rx_mode) {
1512                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1513         }
1514
1515         if (new_tg3_flags & TG3_FLAG_TX_PAUSE)
1516                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1517         else
1518                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1519
1520         if (old_tx_mode != tp->tx_mode) {
1521                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1522         }
1523 }
1524
1525 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1526 {
1527         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1528         case MII_TG3_AUX_STAT_10HALF:
1529                 *speed = SPEED_10;
1530                 *duplex = DUPLEX_HALF;
1531                 break;
1532
1533         case MII_TG3_AUX_STAT_10FULL:
1534                 *speed = SPEED_10;
1535                 *duplex = DUPLEX_FULL;
1536                 break;
1537
1538         case MII_TG3_AUX_STAT_100HALF:
1539                 *speed = SPEED_100;
1540                 *duplex = DUPLEX_HALF;
1541                 break;
1542
1543         case MII_TG3_AUX_STAT_100FULL:
1544                 *speed = SPEED_100;
1545                 *duplex = DUPLEX_FULL;
1546                 break;
1547
1548         case MII_TG3_AUX_STAT_1000HALF:
1549                 *speed = SPEED_1000;
1550                 *duplex = DUPLEX_HALF;
1551                 break;
1552
1553         case MII_TG3_AUX_STAT_1000FULL:
1554                 *speed = SPEED_1000;
1555                 *duplex = DUPLEX_FULL;
1556                 break;
1557
1558         default:
1559                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
1560                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1561                                  SPEED_10;
1562                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1563                                   DUPLEX_HALF;
1564                         break;
1565                 }
1566                 *speed = SPEED_INVALID;
1567                 *duplex = DUPLEX_INVALID;
1568                 break;
1569         };
1570 }
1571
1572 static void tg3_phy_copper_begin(struct tg3 *tp)
1573 {
1574         u32 new_adv;
1575         int i;
1576
1577         if (tp->link_config.phy_is_low_power) {
1578                 /* Entering low power mode.  Disable gigabit and
1579                  * 100baseT advertisements.
1580                  */
1581                 tg3_writephy(tp, MII_TG3_CTRL, 0);
1582
1583                 new_adv = (ADVERTISE_10HALF | ADVERTISE_10FULL |
1584                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1585                 if (tp->tg3_flags & TG3_FLAG_WOL_SPEED_100MB)
1586                         new_adv |= (ADVERTISE_100HALF | ADVERTISE_100FULL);
1587
1588                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1589         } else if (tp->link_config.speed == SPEED_INVALID) {
1590                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
1591                         tp->link_config.advertising &=
1592                                 ~(ADVERTISED_1000baseT_Half |
1593                                   ADVERTISED_1000baseT_Full);
1594
1595                 new_adv = (ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1596                 if (tp->link_config.advertising & ADVERTISED_10baseT_Half)
1597                         new_adv |= ADVERTISE_10HALF;
1598                 if (tp->link_config.advertising & ADVERTISED_10baseT_Full)
1599                         new_adv |= ADVERTISE_10FULL;
1600                 if (tp->link_config.advertising & ADVERTISED_100baseT_Half)
1601                         new_adv |= ADVERTISE_100HALF;
1602                 if (tp->link_config.advertising & ADVERTISED_100baseT_Full)
1603                         new_adv |= ADVERTISE_100FULL;
1604                 tg3_writephy(tp, MII_ADVERTISE, new_adv);
1605
1606                 if (tp->link_config.advertising &
1607                     (ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full)) {
1608                         new_adv = 0;
1609                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
1610                                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
1611                         if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
1612                                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
1613                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY) &&
1614                             (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1615                              tp->pci_chip_rev_id == CHIPREV_ID_5701_B0))
1616                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1617                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1618                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1619                 } else {
1620                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1621                 }
1622         } else {
1623                 /* Asking for a specific link mode. */
1624                 if (tp->link_config.speed == SPEED_1000) {
1625                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1626                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1627
1628                         if (tp->link_config.duplex == DUPLEX_FULL)
1629                                 new_adv = MII_TG3_CTRL_ADV_1000_FULL;
1630                         else
1631                                 new_adv = MII_TG3_CTRL_ADV_1000_HALF;
1632                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1633                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
1634                                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
1635                                             MII_TG3_CTRL_ENABLE_AS_MASTER);
1636                         tg3_writephy(tp, MII_TG3_CTRL, new_adv);
1637                 } else {
1638                         tg3_writephy(tp, MII_TG3_CTRL, 0);
1639
1640                         new_adv = ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP;
1641                         if (tp->link_config.speed == SPEED_100) {
1642                                 if (tp->link_config.duplex == DUPLEX_FULL)
1643                                         new_adv |= ADVERTISE_100FULL;
1644                                 else
1645                                         new_adv |= ADVERTISE_100HALF;
1646                         } else {
1647                                 if (tp->link_config.duplex == DUPLEX_FULL)
1648                                         new_adv |= ADVERTISE_10FULL;
1649                                 else
1650                                         new_adv |= ADVERTISE_10HALF;
1651                         }
1652                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
1653                 }
1654         }
1655
1656         if (tp->link_config.autoneg == AUTONEG_DISABLE &&
1657             tp->link_config.speed != SPEED_INVALID) {
1658                 u32 bmcr, orig_bmcr;
1659
1660                 tp->link_config.active_speed = tp->link_config.speed;
1661                 tp->link_config.active_duplex = tp->link_config.duplex;
1662
1663                 bmcr = 0;
1664                 switch (tp->link_config.speed) {
1665                 default:
1666                 case SPEED_10:
1667                         break;
1668
1669                 case SPEED_100:
1670                         bmcr |= BMCR_SPEED100;
1671                         break;
1672
1673                 case SPEED_1000:
1674                         bmcr |= TG3_BMCR_SPEED1000;
1675                         break;
1676                 };
1677
1678                 if (tp->link_config.duplex == DUPLEX_FULL)
1679                         bmcr |= BMCR_FULLDPLX;
1680
1681                 if (!tg3_readphy(tp, MII_BMCR, &orig_bmcr) &&
1682                     (bmcr != orig_bmcr)) {
1683                         tg3_writephy(tp, MII_BMCR, BMCR_LOOPBACK);
1684                         for (i = 0; i < 1500; i++) {
1685                                 u32 tmp;
1686
1687                                 udelay(10);
1688                                 if (tg3_readphy(tp, MII_BMSR, &tmp) ||
1689                                     tg3_readphy(tp, MII_BMSR, &tmp))
1690                                         continue;
1691                                 if (!(tmp & BMSR_LSTATUS)) {
1692                                         udelay(40);
1693                                         break;
1694                                 }
1695                         }
1696                         tg3_writephy(tp, MII_BMCR, bmcr);
1697                         udelay(40);
1698                 }
1699         } else {
1700                 tg3_writephy(tp, MII_BMCR,
1701                              BMCR_ANENABLE | BMCR_ANRESTART);
1702         }
1703 }
1704
1705 static int tg3_init_5401phy_dsp(struct tg3 *tp)
1706 {
1707         int err;
1708
1709         /* Turn off tap power management. */
1710         /* Set Extended packet length bit */
1711         err  = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
1712
1713         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
1714         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
1715
1716         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
1717         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
1718
1719         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1720         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
1721
1722         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
1723         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
1724
1725         err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
1726         err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
1727
1728         udelay(40);
1729
1730         return err;
1731 }
1732
1733 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
1734 {
1735         u32 adv_reg, all_mask = 0;
1736
1737         if (mask & ADVERTISED_10baseT_Half)
1738                 all_mask |= ADVERTISE_10HALF;
1739         if (mask & ADVERTISED_10baseT_Full)
1740                 all_mask |= ADVERTISE_10FULL;
1741         if (mask & ADVERTISED_100baseT_Half)
1742                 all_mask |= ADVERTISE_100HALF;
1743         if (mask & ADVERTISED_100baseT_Full)
1744                 all_mask |= ADVERTISE_100FULL;
1745
1746         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
1747                 return 0;
1748
1749         if ((adv_reg & all_mask) != all_mask)
1750                 return 0;
1751         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
1752                 u32 tg3_ctrl;
1753
1754                 all_mask = 0;
1755                 if (mask & ADVERTISED_1000baseT_Half)
1756                         all_mask |= ADVERTISE_1000HALF;
1757                 if (mask & ADVERTISED_1000baseT_Full)
1758                         all_mask |= ADVERTISE_1000FULL;
1759
1760                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
1761                         return 0;
1762
1763                 if ((tg3_ctrl & all_mask) != all_mask)
1764                         return 0;
1765         }
1766         return 1;
1767 }
1768
1769 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1770 {
1771         int current_link_up;
1772         u32 bmsr, dummy;
1773         u16 current_speed;
1774         u8 current_duplex;
1775         int i, err;
1776
1777         tw32(MAC_EVENT, 0);
1778
1779         tw32_f(MAC_STATUS,
1780              (MAC_STATUS_SYNC_CHANGED |
1781               MAC_STATUS_CFG_CHANGED |
1782               MAC_STATUS_MI_COMPLETION |
1783               MAC_STATUS_LNKSTATE_CHANGED));
1784         udelay(40);
1785
1786         tp->mi_mode = MAC_MI_MODE_BASE;
1787         tw32_f(MAC_MI_MODE, tp->mi_mode);
1788         udelay(80);
1789
1790         tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x02);
1791
1792         /* Some third-party PHYs need to be reset on link going
1793          * down.
1794          */
1795         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1796              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1797              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1798             netif_carrier_ok(tp->dev)) {
1799                 tg3_readphy(tp, MII_BMSR, &bmsr);
1800                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1801                     !(bmsr & BMSR_LSTATUS))
1802                         force_reset = 1;
1803         }
1804         if (force_reset)
1805                 tg3_phy_reset(tp);
1806
1807         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
1808                 tg3_readphy(tp, MII_BMSR, &bmsr);
1809                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1810                     !(tp->tg3_flags & TG3_FLAG_INIT_COMPLETE))
1811                         bmsr = 0;
1812
1813                 if (!(bmsr & BMSR_LSTATUS)) {
1814                         err = tg3_init_5401phy_dsp(tp);
1815                         if (err)
1816                                 return err;
1817
1818                         tg3_readphy(tp, MII_BMSR, &bmsr);
1819                         for (i = 0; i < 1000; i++) {
1820                                 udelay(10);
1821                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1822                                     (bmsr & BMSR_LSTATUS)) {
1823                                         udelay(40);
1824                                         break;
1825                                 }
1826                         }
1827
1828                         if ((tp->phy_id & PHY_ID_REV_MASK) == PHY_REV_BCM5401_B0 &&
1829                             !(bmsr & BMSR_LSTATUS) &&
1830                             tp->link_config.active_speed == SPEED_1000) {
1831                                 err = tg3_phy_reset(tp);
1832                                 if (!err)
1833                                         err = tg3_init_5401phy_dsp(tp);
1834                                 if (err)
1835                                         return err;
1836                         }
1837                 }
1838         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1839                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1840                 /* 5701 {A0,B0} CRC bug workaround */
1841                 tg3_writephy(tp, 0x15, 0x0a75);
1842                 tg3_writephy(tp, 0x1c, 0x8c68);
1843                 tg3_writephy(tp, 0x1c, 0x8d68);
1844                 tg3_writephy(tp, 0x1c, 0x8c68);
1845         }
1846
1847         /* Clear pending interrupts... */
1848         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1849         tg3_readphy(tp, MII_TG3_ISTAT, &dummy);
1850
1851         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT)
1852                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1853         else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
1854                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1855
1856         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1857             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1858                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1859                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1860                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1861                 else
1862                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1863         }
1864
1865         current_link_up = 0;
1866         current_speed = SPEED_INVALID;
1867         current_duplex = DUPLEX_INVALID;
1868
1869         if (tp->tg3_flags2 & TG3_FLG2_CAPACITIVE_COUPLING) {
1870                 u32 val;
1871
1872                 tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4007);
1873                 tg3_readphy(tp, MII_TG3_AUX_CTRL, &val);
1874                 if (!(val & (1 << 10))) {
1875                         val |= (1 << 10);
1876                         tg3_writephy(tp, MII_TG3_AUX_CTRL, val);
1877                         goto relink;
1878                 }
1879         }
1880
1881         bmsr = 0;
1882         for (i = 0; i < 100; i++) {
1883                 tg3_readphy(tp, MII_BMSR, &bmsr);
1884                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1885                     (bmsr & BMSR_LSTATUS))
1886                         break;
1887                 udelay(40);
1888         }
1889
1890         if (bmsr & BMSR_LSTATUS) {
1891                 u32 aux_stat, bmcr;
1892
1893                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1894                 for (i = 0; i < 2000; i++) {
1895                         udelay(10);
1896                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1897                             aux_stat)
1898                                 break;
1899                 }
1900
1901                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1902                                              &current_speed,
1903                                              &current_duplex);
1904
1905                 bmcr = 0;
1906                 for (i = 0; i < 200; i++) {
1907                         tg3_readphy(tp, MII_BMCR, &bmcr);
1908                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1909                                 continue;
1910                         if (bmcr && bmcr != 0x7fff)
1911                                 break;
1912                         udelay(10);
1913                 }
1914
1915                 if (tp->link_config.autoneg == AUTONEG_ENABLE) {
1916                         if (bmcr & BMCR_ANENABLE) {
1917                                 current_link_up = 1;
1918
1919                                 /* Force autoneg restart if we are exiting
1920                                  * low power mode.
1921                                  */
1922                                 if (!tg3_copper_is_advertising_all(tp,
1923                                                 tp->link_config.advertising))
1924                                         current_link_up = 0;
1925                         } else {
1926                                 current_link_up = 0;
1927                         }
1928                 } else {
1929                         if (!(bmcr & BMCR_ANENABLE) &&
1930                             tp->link_config.speed == current_speed &&
1931                             tp->link_config.duplex == current_duplex) {
1932                                 current_link_up = 1;
1933                         } else {
1934                                 current_link_up = 0;
1935                         }
1936                 }
1937
1938                 tp->link_config.active_speed = current_speed;
1939                 tp->link_config.active_duplex = current_duplex;
1940         }
1941
1942         if (current_link_up == 1 &&
1943             (tp->link_config.active_duplex == DUPLEX_FULL) &&
1944             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
1945                 u32 local_adv, remote_adv;
1946
1947                 if (tg3_readphy(tp, MII_ADVERTISE, &local_adv))
1948                         local_adv = 0;
1949                 local_adv &= (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1950
1951                 if (tg3_readphy(tp, MII_LPA, &remote_adv))
1952                         remote_adv = 0;
1953
1954                 remote_adv &= (LPA_PAUSE_CAP | LPA_PAUSE_ASYM);
1955
1956                 /* If we are not advertising full pause capability,
1957                  * something is wrong.  Bring the link down and reconfigure.
1958                  */
1959                 if (local_adv != ADVERTISE_PAUSE_CAP) {
1960                         current_link_up = 0;
1961                 } else {
1962                         tg3_setup_flow_control(tp, local_adv, remote_adv);
1963                 }
1964         }
1965 relink:
1966         if (current_link_up == 0 || tp->link_config.phy_is_low_power) {
1967                 u32 tmp;
1968
1969                 tg3_phy_copper_begin(tp);
1970
1971                 tg3_readphy(tp, MII_BMSR, &tmp);
1972                 if (!tg3_readphy(tp, MII_BMSR, &tmp) &&
1973                     (tmp & BMSR_LSTATUS))
1974                         current_link_up = 1;
1975         }
1976
1977         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1978         if (current_link_up == 1) {
1979                 if (tp->link_config.active_speed == SPEED_100 ||
1980                     tp->link_config.active_speed == SPEED_10)
1981                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1982                 else
1983                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1984         } else
1985                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1986
1987         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1988         if (tp->link_config.active_duplex == DUPLEX_HALF)
1989                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1990
1991         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1992         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1993                 if ((tp->led_ctrl == LED_CTRL_MODE_PHY_2) ||
1994                     (current_link_up == 1 &&
1995                      tp->link_config.active_speed == SPEED_10))
1996                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1997         } else {
1998                 if (current_link_up == 1)
1999                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
2000         }
2001
2002         /* ??? Without this setting Netgear GA302T PHY does not
2003          * ??? send/receive packets...
2004          */
2005         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5411 &&
2006             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
2007                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
2008                 tw32_f(MAC_MI_MODE, tp->mi_mode);
2009                 udelay(80);
2010         }
2011
2012         tw32_f(MAC_MODE, tp->mac_mode);
2013         udelay(40);
2014
2015         if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
2016                 /* Polled via timer. */
2017                 tw32_f(MAC_EVENT, 0);
2018         } else {
2019                 tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2020         }
2021         udelay(40);
2022
2023         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
2024             current_link_up == 1 &&
2025             tp->link_config.active_speed == SPEED_1000 &&
2026             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) ||
2027              (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED))) {
2028                 udelay(120);
2029                 tw32_f(MAC_STATUS,
2030                      (MAC_STATUS_SYNC_CHANGED |
2031                       MAC_STATUS_CFG_CHANGED));
2032                 udelay(40);
2033                 tg3_write_mem(tp,
2034                               NIC_SRAM_FIRMWARE_MBOX,
2035                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
2036         }
2037
2038         if (current_link_up != netif_carrier_ok(tp->dev)) {
2039                 if (current_link_up)
2040                         netif_carrier_on(tp->dev);
2041                 else
2042                         netif_carrier_off(tp->dev);
2043                 tg3_link_report(tp);
2044         }
2045
2046         return 0;
2047 }
2048
2049 struct tg3_fiber_aneginfo {
2050         int state;
2051 #define ANEG_STATE_UNKNOWN              0
2052 #define ANEG_STATE_AN_ENABLE            1
2053 #define ANEG_STATE_RESTART_INIT         2
2054 #define ANEG_STATE_RESTART              3
2055 #define ANEG_STATE_DISABLE_LINK_OK      4
2056 #define ANEG_STATE_ABILITY_DETECT_INIT  5
2057 #define ANEG_STATE_ABILITY_DETECT       6
2058 #define ANEG_STATE_ACK_DETECT_INIT      7
2059 #define ANEG_STATE_ACK_DETECT           8
2060 #define ANEG_STATE_COMPLETE_ACK_INIT    9
2061 #define ANEG_STATE_COMPLETE_ACK         10
2062 #define ANEG_STATE_IDLE_DETECT_INIT     11
2063 #define ANEG_STATE_IDLE_DETECT          12
2064 #define ANEG_STATE_LINK_OK              13
2065 #define ANEG_STATE_NEXT_PAGE_WAIT_INIT  14
2066 #define ANEG_STATE_NEXT_PAGE_WAIT       15
2067
2068         u32 flags;
2069 #define MR_AN_ENABLE            0x00000001
2070 #define MR_RESTART_AN           0x00000002
2071 #define MR_AN_COMPLETE          0x00000004
2072 #define MR_PAGE_RX              0x00000008
2073 #define MR_NP_LOADED            0x00000010
2074 #define MR_TOGGLE_TX            0x00000020
2075 #define MR_LP_ADV_FULL_DUPLEX   0x00000040
2076 #define MR_LP_ADV_HALF_DUPLEX   0x00000080
2077 #define MR_LP_ADV_SYM_PAUSE     0x00000100
2078 #define MR_LP_ADV_ASYM_PAUSE    0x00000200
2079 #define MR_LP_ADV_REMOTE_FAULT1 0x00000400
2080 #define MR_LP_ADV_REMOTE_FAULT2 0x00000800
2081 #define MR_LP_ADV_NEXT_PAGE     0x00001000
2082 #define MR_TOGGLE_RX            0x00002000
2083 #define MR_NP_RX                0x00004000
2084
2085 #define MR_LINK_OK              0x80000000
2086
2087         unsigned long link_time, cur_time;
2088
2089         u32 ability_match_cfg;
2090         int ability_match_count;
2091
2092         char ability_match, idle_match, ack_match;
2093
2094         u32 txconfig, rxconfig;
2095 #define ANEG_CFG_NP             0x00000080
2096 #define ANEG_CFG_ACK            0x00000040
2097 #define ANEG_CFG_RF2            0x00000020
2098 #define ANEG_CFG_RF1            0x00000010
2099 #define ANEG_CFG_PS2            0x00000001
2100 #define ANEG_CFG_PS1            0x00008000
2101 #define ANEG_CFG_HD             0x00004000
2102 #define ANEG_CFG_FD             0x00002000
2103 #define ANEG_CFG_INVAL          0x00001f06
2104
2105 };
2106 #define ANEG_OK         0
2107 #define ANEG_DONE       1
2108 #define ANEG_TIMER_ENAB 2
2109 #define ANEG_FAILED     -1
2110
2111 #define ANEG_STATE_SETTLE_TIME  10000
2112
2113 static int tg3_fiber_aneg_smachine(struct tg3 *tp,
2114                                    struct tg3_fiber_aneginfo *ap)
2115 {
2116         unsigned long delta;
2117         u32 rx_cfg_reg;
2118         int ret;
2119
2120         if (ap->state == ANEG_STATE_UNKNOWN) {
2121                 ap->rxconfig = 0;
2122                 ap->link_time = 0;
2123                 ap->cur_time = 0;
2124                 ap->ability_match_cfg = 0;
2125                 ap->ability_match_count = 0;
2126                 ap->ability_match = 0;
2127                 ap->idle_match = 0;
2128                 ap->ack_match = 0;
2129         }
2130         ap->cur_time++;
2131
2132         if (tr32(MAC_STATUS) & MAC_STATUS_RCVD_CFG) {
2133                 rx_cfg_reg = tr32(MAC_RX_AUTO_NEG);
2134
2135                 if (rx_cfg_reg != ap->ability_match_cfg) {
2136                         ap->ability_match_cfg = rx_cfg_reg;
2137                         ap->ability_match = 0;
2138                         ap->ability_match_count = 0;
2139                 } else {
2140                         if (++ap->ability_match_count > 1) {
2141                                 ap->ability_match = 1;
2142                                 ap->ability_match_cfg = rx_cfg_reg;
2143                         }
2144                 }
2145                 if (rx_cfg_reg & ANEG_CFG_ACK)
2146                         ap->ack_match = 1;
2147                 else
2148                         ap->ack_match = 0;
2149
2150                 ap->idle_match = 0;
2151         } else {
2152                 ap->idle_match = 1;
2153                 ap->ability_match_cfg = 0;
2154                 ap->ability_match_count = 0;
2155                 ap->ability_match = 0;
2156                 ap->ack_match = 0;
2157
2158                 rx_cfg_reg = 0;
2159         }
2160
2161         ap->rxconfig = rx_cfg_reg;
2162         ret = ANEG_OK;
2163
2164         switch(ap->state) {
2165         case ANEG_STATE_UNKNOWN:
2166                 if (ap->flags & (MR_AN_ENABLE | MR_RESTART_AN))
2167                         ap->state = ANEG_STATE_AN_ENABLE;
2168
2169                 /* fallthru */
2170         case ANEG_STATE_AN_ENABLE:
2171                 ap->flags &= ~(MR_AN_COMPLETE | MR_PAGE_RX);
2172                 if (ap->flags & MR_AN_ENABLE) {
2173                         ap->link_time = 0;
2174                         ap->cur_time = 0;
2175                         ap->ability_match_cfg = 0;
2176                         ap->ability_match_count = 0;
2177                         ap->ability_match = 0;
2178                         ap->idle_match = 0;
2179                         ap->ack_match = 0;
2180
2181                         ap->state = ANEG_STATE_RESTART_INIT;
2182                 } else {
2183                         ap->state = ANEG_STATE_DISABLE_LINK_OK;
2184                 }
2185                 break;
2186
2187         case ANEG_STATE_RESTART_INIT:
2188                 ap->link_time = ap->cur_time;
2189                 ap->flags &= ~(MR_NP_LOADED);
2190                 ap->txconfig = 0;
2191                 tw32(MAC_TX_AUTO_NEG, 0);
2192                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2193                 tw32_f(MAC_MODE, tp->mac_mode);
2194                 udelay(40);
2195
2196                 ret = ANEG_TIMER_ENAB;
2197                 ap->state = ANEG_STATE_RESTART;
2198
2199                 /* fallthru */
2200         case ANEG_STATE_RESTART:
2201                 delta = ap->cur_time - ap->link_time;
2202                 if (delta > ANEG_STATE_SETTLE_TIME) {
2203                         ap->state = ANEG_STATE_ABILITY_DETECT_INIT;
2204                 } else {
2205                         ret = ANEG_TIMER_ENAB;
2206                 }
2207                 break;
2208
2209         case ANEG_STATE_DISABLE_LINK_OK:
2210                 ret = ANEG_DONE;
2211                 break;
2212
2213         case ANEG_STATE_ABILITY_DETECT_INIT:
2214                 ap->flags &= ~(MR_TOGGLE_TX);
2215                 ap->txconfig = (ANEG_CFG_FD | ANEG_CFG_PS1);
2216                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2217                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2218                 tw32_f(MAC_MODE, tp->mac_mode);
2219                 udelay(40);
2220
2221                 ap->state = ANEG_STATE_ABILITY_DETECT;
2222                 break;
2223
2224         case ANEG_STATE_ABILITY_DETECT:
2225                 if (ap->ability_match != 0 && ap->rxconfig != 0) {
2226                         ap->state = ANEG_STATE_ACK_DETECT_INIT;
2227                 }
2228                 break;
2229
2230         case ANEG_STATE_ACK_DETECT_INIT:
2231                 ap->txconfig |= ANEG_CFG_ACK;
2232                 tw32(MAC_TX_AUTO_NEG, ap->txconfig);
2233                 tp->mac_mode |= MAC_MODE_SEND_CONFIGS;
2234                 tw32_f(MAC_MODE, tp->mac_mode);
2235                 udelay(40);
2236
2237                 ap->state = ANEG_STATE_ACK_DETECT;
2238
2239                 /* fallthru */
2240         case ANEG_STATE_ACK_DETECT:
2241                 if (ap->ack_match != 0) {
2242                         if ((ap->rxconfig & ~ANEG_CFG_ACK) ==
2243                             (ap->ability_match_cfg & ~ANEG_CFG_ACK)) {
2244                                 ap->state = ANEG_STATE_COMPLETE_ACK_INIT;
2245                         } else {
2246                                 ap->state = ANEG_STATE_AN_ENABLE;
2247                         }
2248                 } else if (ap->ability_match != 0 &&
2249                            ap->rxconfig == 0) {
2250                         ap->state = ANEG_STATE_AN_ENABLE;
2251                 }
2252                 break;
2253
2254         case ANEG_STATE_COMPLETE_ACK_INIT:
2255                 if (ap->rxconfig & ANEG_CFG_INVAL) {
2256                         ret = ANEG_FAILED;
2257                         break;
2258                 }
2259                 ap->flags &= ~(MR_LP_ADV_FULL_DUPLEX |
2260                                MR_LP_ADV_HALF_DUPLEX |
2261                                MR_LP_ADV_SYM_PAUSE |
2262                                MR_LP_ADV_ASYM_PAUSE |
2263                                MR_LP_ADV_REMOTE_FAULT1 |
2264                                MR_LP_ADV_REMOTE_FAULT2 |
2265                                MR_LP_ADV_NEXT_PAGE |
2266                                MR_TOGGLE_RX |
2267                                MR_NP_RX);
2268                 if (ap->rxconfig & ANEG_CFG_FD)
2269                         ap->flags |= MR_LP_ADV_FULL_DUPLEX;
2270                 if (ap->rxconfig & ANEG_CFG_HD)
2271                         ap->flags |= MR_LP_ADV_HALF_DUPLEX;
2272                 if (ap->rxconfig & ANEG_CFG_PS1)
2273                         ap->flags |= MR_LP_ADV_SYM_PAUSE;
2274                 if (ap->rxconfig & ANEG_CFG_PS2)
2275                         ap->flags |= MR_LP_ADV_ASYM_PAUSE;
2276                 if (ap->rxconfig & ANEG_CFG_RF1)
2277                         ap->flags |= MR_LP_ADV_REMOTE_FAULT1;
2278                 if (ap->rxconfig & ANEG_CFG_RF2)
2279                         ap->flags |= MR_LP_ADV_REMOTE_FAULT2;
2280                 if (ap->rxconfig & ANEG_CFG_NP)
2281                         ap->flags |= MR_LP_ADV_NEXT_PAGE;
2282
2283                 ap->link_time = ap->cur_time;
2284
2285                 ap->flags ^= (MR_TOGGLE_TX);
2286                 if (ap->rxconfig & 0x0008)
2287                         ap->flags |= MR_TOGGLE_RX;
2288                 if (ap->rxconfig & ANEG_CFG_NP)
2289                         ap->flags |= MR_NP_RX;
2290                 ap->flags |= MR_PAGE_RX;
2291
2292                 ap->state = ANEG_STATE_COMPLETE_ACK;
2293                 ret = ANEG_TIMER_ENAB;
2294                 break;
2295
2296         case ANEG_STATE_COMPLETE_ACK:
2297                 if (ap->ability_match != 0 &&
2298                     ap->rxconfig == 0) {
2299                         ap->state = ANEG_STATE_AN_ENABLE;
2300                         break;
2301                 }
2302                 delta = ap->cur_time - ap->link_time;
2303                 if (delta > ANEG_STATE_SETTLE_TIME) {
2304                         if (!(ap->flags & (MR_LP_ADV_NEXT_PAGE))) {
2305                                 ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2306                         } else {
2307                                 if ((ap->txconfig & ANEG_CFG_NP) == 0 &&
2308                                     !(ap->flags & MR_NP_RX)) {
2309                                         ap->state = ANEG_STATE_IDLE_DETECT_INIT;
2310                                 } else {
2311                                         ret = ANEG_FAILED;
2312                                 }
2313                         }
2314                 }
2315                 break;
2316
2317         case ANEG_STATE_IDLE_DETECT_INIT:
2318                 ap->link_time = ap->cur_time;
2319                 tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2320                 tw32_f(MAC_MODE, tp->mac_mode);
2321                 udelay(40);
2322
2323                 ap->state = ANEG_STATE_IDLE_DETECT;
2324                 ret = ANEG_TIMER_ENAB;
2325                 break;
2326
2327         case ANEG_STATE_IDLE_DETECT:
2328                 if (ap->ability_match != 0 &&
2329                     ap->rxconfig == 0) {
2330                         ap->state = ANEG_STATE_AN_ENABLE;
2331                         break;
2332                 }
2333                 delta = ap->cur_time - ap->link_time;
2334                 if (delta > ANEG_STATE_SETTLE_TIME) {
2335                         /* XXX another gem from the Broadcom driver :( */
2336                         ap->state = ANEG_STATE_LINK_OK;
2337                 }
2338                 break;
2339
2340         case ANEG_STATE_LINK_OK:
2341                 ap->flags |= (MR_AN_COMPLETE | MR_LINK_OK);
2342                 ret = ANEG_DONE;
2343                 break;
2344
2345         case ANEG_STATE_NEXT_PAGE_WAIT_INIT:
2346                 /* ??? unimplemented */
2347                 break;
2348
2349         case ANEG_STATE_NEXT_PAGE_WAIT:
2350                 /* ??? unimplemented */
2351                 break;
2352
2353         default:
2354                 ret = ANEG_FAILED;
2355                 break;
2356         };
2357
2358         return ret;
2359 }
2360
2361 static int fiber_autoneg(struct tg3 *tp, u32 *flags)
2362 {
2363         int res = 0;
2364         struct tg3_fiber_aneginfo aninfo;
2365         int status = ANEG_FAILED;
2366         unsigned int tick;
2367         u32 tmp;
2368
2369         tw32_f(MAC_TX_AUTO_NEG, 0);
2370
2371         tmp = tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK;
2372         tw32_f(MAC_MODE, tmp | MAC_MODE_PORT_MODE_GMII);
2373         udelay(40);
2374
2375         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_SEND_CONFIGS);
2376         udelay(40);
2377
2378         memset(&aninfo, 0, sizeof(aninfo));
2379         aninfo.flags |= MR_AN_ENABLE;
2380         aninfo.state = ANEG_STATE_UNKNOWN;
2381         aninfo.cur_time = 0;
2382         tick = 0;
2383         while (++tick < 195000) {
2384                 status = tg3_fiber_aneg_smachine(tp, &aninfo);
2385                 if (status == ANEG_DONE || status == ANEG_FAILED)
2386                         break;
2387
2388                 udelay(1);
2389         }
2390
2391         tp->mac_mode &= ~MAC_MODE_SEND_CONFIGS;
2392         tw32_f(MAC_MODE, tp->mac_mode);
2393         udelay(40);
2394
2395         *flags = aninfo.flags;
2396
2397         if (status == ANEG_DONE &&
2398             (aninfo.flags & (MR_AN_COMPLETE | MR_LINK_OK |
2399                              MR_LP_ADV_FULL_DUPLEX)))
2400                 res = 1;
2401
2402         return res;
2403 }
2404
2405 static void tg3_init_bcm8002(struct tg3 *tp)
2406 {
2407         u32 mac_status = tr32(MAC_STATUS);
2408         int i;
2409
2410         /* Reset when initting first time or we have a link. */
2411         if ((tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) &&
2412             !(mac_status & MAC_STATUS_PCS_SYNCED))
2413                 return;
2414
2415         /* Set PLL lock range. */
2416         tg3_writephy(tp, 0x16, 0x8007);
2417
2418         /* SW reset */
2419         tg3_writephy(tp, MII_BMCR, BMCR_RESET);
2420
2421         /* Wait for reset to complete. */
2422         /* XXX schedule_timeout() ... */
2423         for (i = 0; i < 500; i++)
2424                 udelay(10);
2425
2426         /* Config mode; select PMA/Ch 1 regs. */
2427         tg3_writephy(tp, 0x10, 0x8411);
2428
2429         /* Enable auto-lock and comdet, select txclk for tx. */
2430         tg3_writephy(tp, 0x11, 0x0a10);
2431
2432         tg3_writephy(tp, 0x18, 0x00a0);
2433         tg3_writephy(tp, 0x16, 0x41ff);
2434
2435         /* Assert and deassert POR. */
2436         tg3_writephy(tp, 0x13, 0x0400);
2437         udelay(40);
2438         tg3_writephy(tp, 0x13, 0x0000);
2439
2440         tg3_writephy(tp, 0x11, 0x0a50);
2441         udelay(40);
2442         tg3_writephy(tp, 0x11, 0x0a10);
2443
2444         /* Wait for signal to stabilize */
2445         /* XXX schedule_timeout() ... */
2446         for (i = 0; i < 15000; i++)
2447                 udelay(10);
2448
2449         /* Deselect the channel register so we can read the PHYID
2450          * later.
2451          */
2452         tg3_writephy(tp, 0x10, 0x8011);
2453 }
2454
2455 static int tg3_setup_fiber_hw_autoneg(struct tg3 *tp, u32 mac_status)
2456 {
2457         u32 sg_dig_ctrl, sg_dig_status;
2458         u32 serdes_cfg, expected_sg_dig_ctrl;
2459         int workaround, port_a;
2460         int current_link_up;
2461
2462         serdes_cfg = 0;
2463         expected_sg_dig_ctrl = 0;
2464         workaround = 0;
2465         port_a = 1;
2466         current_link_up = 0;
2467
2468         if (tp->pci_chip_rev_id != CHIPREV_ID_5704_A0 &&
2469             tp->pci_chip_rev_id != CHIPREV_ID_5704_A1) {
2470                 workaround = 1;
2471                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
2472                         port_a = 0;
2473
2474                 /* preserve bits 0-11,13,14 for signal pre-emphasis */
2475                 /* preserve bits 20-23 for voltage regulator */
2476                 serdes_cfg = tr32(MAC_SERDES_CFG) & 0x00f06fff;
2477         }
2478
2479         sg_dig_ctrl = tr32(SG_DIG_CTRL);
2480
2481         if (tp->link_config.autoneg != AUTONEG_ENABLE) {
2482                 if (sg_dig_ctrl & (1 << 31)) {
2483                         if (workaround) {
2484                                 u32 val = serdes_cfg;
2485
2486                                 if (port_a)
2487                                         val |= 0xc010000;
2488                                 else
2489                                         val |= 0x4010000;
2490                                 tw32_f(MAC_SERDES_CFG, val);
2491                         }
2492                         tw32_f(SG_DIG_CTRL, 0x01388400);
2493                 }
2494                 if (mac_status & MAC_STATUS_PCS_SYNCED) {
2495                         tg3_setup_flow_control(tp, 0, 0);
2496                         current_link_up = 1;
2497                 }
2498                 goto out;
2499         }
2500
2501         /* Want auto-negotiation.  */
2502         expected_sg_dig_ctrl = 0x81388400;
2503
2504         /* Pause capability */
2505         expected_sg_dig_ctrl |= (1 << 11);
2506
2507         /* Asymettric pause */
2508         expected_sg_dig_ctrl |= (1 << 12);
2509
2510         if (sg_dig_ctrl != expected_sg_dig_ctrl) {
2511                 if ((tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT) &&
2512                     tp->serdes_counter &&
2513                     ((mac_status & (MAC_STATUS_PCS_SYNCED |
2514                                     MAC_STATUS_RCVD_CFG)) ==
2515                      MAC_STATUS_PCS_SYNCED)) {
2516                         tp->serdes_counter--;
2517                         current_link_up = 1;
2518                         goto out;
2519                 }
2520 restart_autoneg:
2521                 if (workaround)
2522                         tw32_f(MAC_SERDES_CFG, serdes_cfg | 0xc011000);
2523                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl | (1 << 30));
2524                 udelay(5);
2525                 tw32_f(SG_DIG_CTRL, expected_sg_dig_ctrl);
2526
2527                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2528                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2529         } else if (mac_status & (MAC_STATUS_PCS_SYNCED |
2530                                  MAC_STATUS_SIGNAL_DET)) {
2531                 sg_dig_status = tr32(SG_DIG_STATUS);
2532                 mac_status = tr32(MAC_STATUS);
2533
2534                 if ((sg_dig_status & (1 << 1)) &&
2535                     (mac_status & MAC_STATUS_PCS_SYNCED)) {
2536                         u32 local_adv, remote_adv;
2537
2538                         local_adv = ADVERTISE_PAUSE_CAP;
2539                         remote_adv = 0;
2540                         if (sg_dig_status & (1 << 19))
2541                                 remote_adv |= LPA_PAUSE_CAP;
2542                         if (sg_dig_status & (1 << 20))
2543                                 remote_adv |= LPA_PAUSE_ASYM;
2544
2545                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2546                         current_link_up = 1;
2547                         tp->serdes_counter = 0;
2548                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2549                 } else if (!(sg_dig_status & (1 << 1))) {
2550                         if (tp->serdes_counter)
2551                                 tp->serdes_counter--;
2552                         else {
2553                                 if (workaround) {
2554                                         u32 val = serdes_cfg;
2555
2556                                         if (port_a)
2557                                                 val |= 0xc010000;
2558                                         else
2559                                                 val |= 0x4010000;
2560
2561                                         tw32_f(MAC_SERDES_CFG, val);
2562                                 }
2563
2564                                 tw32_f(SG_DIG_CTRL, 0x01388400);
2565                                 udelay(40);
2566
2567                                 /* Link parallel detection - link is up */
2568                                 /* only if we have PCS_SYNC and not */
2569                                 /* receiving config code words */
2570                                 mac_status = tr32(MAC_STATUS);
2571                                 if ((mac_status & MAC_STATUS_PCS_SYNCED) &&
2572                                     !(mac_status & MAC_STATUS_RCVD_CFG)) {
2573                                         tg3_setup_flow_control(tp, 0, 0);
2574                                         current_link_up = 1;
2575                                         tp->tg3_flags2 |=
2576                                                 TG3_FLG2_PARALLEL_DETECT;
2577                                         tp->serdes_counter =
2578                                                 SERDES_PARALLEL_DET_TIMEOUT;
2579                                 } else
2580                                         goto restart_autoneg;
2581                         }
2582                 }
2583         } else {
2584                 tp->serdes_counter = SERDES_AN_TIMEOUT_5704S;
2585                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2586         }
2587
2588 out:
2589         return current_link_up;
2590 }
2591
2592 static int tg3_setup_fiber_by_hand(struct tg3 *tp, u32 mac_status)
2593 {
2594         int current_link_up = 0;
2595
2596         if (!(mac_status & MAC_STATUS_PCS_SYNCED)) {
2597                 tp->tg3_flags &= ~TG3_FLAG_GOT_SERDES_FLOWCTL;
2598                 goto out;
2599         }
2600
2601         if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2602                 u32 flags;
2603                 int i;
2604
2605                 if (fiber_autoneg(tp, &flags)) {
2606                         u32 local_adv, remote_adv;
2607
2608                         local_adv = ADVERTISE_PAUSE_CAP;
2609                         remote_adv = 0;
2610                         if (flags & MR_LP_ADV_SYM_PAUSE)
2611                                 remote_adv |= LPA_PAUSE_CAP;
2612                         if (flags & MR_LP_ADV_ASYM_PAUSE)
2613                                 remote_adv |= LPA_PAUSE_ASYM;
2614
2615                         tg3_setup_flow_control(tp, local_adv, remote_adv);
2616
2617                         tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2618                         current_link_up = 1;
2619                 }
2620                 for (i = 0; i < 30; i++) {
2621                         udelay(20);
2622                         tw32_f(MAC_STATUS,
2623                                (MAC_STATUS_SYNC_CHANGED |
2624                                 MAC_STATUS_CFG_CHANGED));
2625                         udelay(40);
2626                         if ((tr32(MAC_STATUS) &
2627                              (MAC_STATUS_SYNC_CHANGED |
2628                               MAC_STATUS_CFG_CHANGED)) == 0)
2629                                 break;
2630                 }
2631
2632                 mac_status = tr32(MAC_STATUS);
2633                 if (current_link_up == 0 &&
2634                     (mac_status & MAC_STATUS_PCS_SYNCED) &&
2635                     !(mac_status & MAC_STATUS_RCVD_CFG))
2636                         current_link_up = 1;
2637         } else {
2638                 /* Forcing 1000FD link up. */
2639                 current_link_up = 1;
2640                 tp->tg3_flags |= TG3_FLAG_GOT_SERDES_FLOWCTL;
2641
2642                 tw32_f(MAC_MODE, (tp->mac_mode | MAC_MODE_SEND_CONFIGS));
2643                 udelay(40);
2644         }
2645
2646 out:
2647         return current_link_up;
2648 }
2649
2650 static int tg3_setup_fiber_phy(struct tg3 *tp, int force_reset)
2651 {
2652         u32 orig_pause_cfg;
2653         u16 orig_active_speed;
2654         u8 orig_active_duplex;
2655         u32 mac_status;
2656         int current_link_up;
2657         int i;
2658
2659         orig_pause_cfg =
2660                 (tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2661                                   TG3_FLAG_TX_PAUSE));
2662         orig_active_speed = tp->link_config.active_speed;
2663         orig_active_duplex = tp->link_config.active_duplex;
2664
2665         if (!(tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG) &&
2666             netif_carrier_ok(tp->dev) &&
2667             (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE)) {
2668                 mac_status = tr32(MAC_STATUS);
2669                 mac_status &= (MAC_STATUS_PCS_SYNCED |
2670                                MAC_STATUS_SIGNAL_DET |
2671                                MAC_STATUS_CFG_CHANGED |
2672                                MAC_STATUS_RCVD_CFG);
2673                 if (mac_status == (MAC_STATUS_PCS_SYNCED |
2674                                    MAC_STATUS_SIGNAL_DET)) {
2675                         tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2676                                             MAC_STATUS_CFG_CHANGED));
2677                         return 0;
2678                 }
2679         }
2680
2681         tw32_f(MAC_TX_AUTO_NEG, 0);
2682
2683         tp->mac_mode &= ~(MAC_MODE_PORT_MODE_MASK | MAC_MODE_HALF_DUPLEX);
2684         tp->mac_mode |= MAC_MODE_PORT_MODE_TBI;
2685         tw32_f(MAC_MODE, tp->mac_mode);
2686         udelay(40);
2687
2688         if (tp->phy_id == PHY_ID_BCM8002)
2689                 tg3_init_bcm8002(tp);
2690
2691         /* Enable link change event even when serdes polling.  */
2692         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2693         udelay(40);
2694
2695         current_link_up = 0;
2696         mac_status = tr32(MAC_STATUS);
2697
2698         if (tp->tg3_flags2 & TG3_FLG2_HW_AUTONEG)
2699                 current_link_up = tg3_setup_fiber_hw_autoneg(tp, mac_status);
2700         else
2701                 current_link_up = tg3_setup_fiber_by_hand(tp, mac_status);
2702
2703         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
2704         tw32_f(MAC_MODE, tp->mac_mode);
2705         udelay(40);
2706
2707         tp->hw_status->status =
2708                 (SD_STATUS_UPDATED |
2709                  (tp->hw_status->status & ~SD_STATUS_LINK_CHG));
2710
2711         for (i = 0; i < 100; i++) {
2712                 tw32_f(MAC_STATUS, (MAC_STATUS_SYNC_CHANGED |
2713                                     MAC_STATUS_CFG_CHANGED));
2714                 udelay(5);
2715                 if ((tr32(MAC_STATUS) & (MAC_STATUS_SYNC_CHANGED |
2716                                          MAC_STATUS_CFG_CHANGED |
2717                                          MAC_STATUS_LNKSTATE_CHANGED)) == 0)
2718                         break;
2719         }
2720
2721         mac_status = tr32(MAC_STATUS);
2722         if ((mac_status & MAC_STATUS_PCS_SYNCED) == 0) {
2723                 current_link_up = 0;
2724                 if (tp->link_config.autoneg == AUTONEG_ENABLE &&
2725                     tp->serdes_counter == 0) {
2726                         tw32_f(MAC_MODE, (tp->mac_mode |
2727                                           MAC_MODE_SEND_CONFIGS));
2728                         udelay(1);
2729                         tw32_f(MAC_MODE, tp->mac_mode);
2730                 }
2731         }
2732
2733         if (current_link_up == 1) {
2734                 tp->link_config.active_speed = SPEED_1000;
2735                 tp->link_config.active_duplex = DUPLEX_FULL;
2736                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2737                                     LED_CTRL_LNKLED_OVERRIDE |
2738                                     LED_CTRL_1000MBPS_ON));
2739         } else {
2740                 tp->link_config.active_speed = SPEED_INVALID;
2741                 tp->link_config.active_duplex = DUPLEX_INVALID;
2742                 tw32(MAC_LED_CTRL, (tp->led_ctrl |
2743                                     LED_CTRL_LNKLED_OVERRIDE |
2744                                     LED_CTRL_TRAFFIC_OVERRIDE));
2745         }
2746
2747         if (current_link_up != netif_carrier_ok(tp->dev)) {
2748                 if (current_link_up)
2749                         netif_carrier_on(tp->dev);
2750                 else
2751                         netif_carrier_off(tp->dev);
2752                 tg3_link_report(tp);
2753         } else {
2754                 u32 now_pause_cfg =
2755                         tp->tg3_flags & (TG3_FLAG_RX_PAUSE |
2756                                          TG3_FLAG_TX_PAUSE);
2757                 if (orig_pause_cfg != now_pause_cfg ||
2758                     orig_active_speed != tp->link_config.active_speed ||
2759                     orig_active_duplex != tp->link_config.active_duplex)
2760                         tg3_link_report(tp);
2761         }
2762
2763         return 0;
2764 }
2765
2766 static int tg3_setup_fiber_mii_phy(struct tg3 *tp, int force_reset)
2767 {
2768         int current_link_up, err = 0;
2769         u32 bmsr, bmcr;
2770         u16 current_speed;
2771         u8 current_duplex;
2772
2773         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
2774         tw32_f(MAC_MODE, tp->mac_mode);
2775         udelay(40);
2776
2777         tw32(MAC_EVENT, 0);
2778
2779         tw32_f(MAC_STATUS,
2780              (MAC_STATUS_SYNC_CHANGED |
2781               MAC_STATUS_CFG_CHANGED |
2782               MAC_STATUS_MI_COMPLETION |
2783               MAC_STATUS_LNKSTATE_CHANGED));
2784         udelay(40);
2785
2786         if (force_reset)
2787                 tg3_phy_reset(tp);
2788
2789         current_link_up = 0;
2790         current_speed = SPEED_INVALID;
2791         current_duplex = DUPLEX_INVALID;
2792
2793         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2794         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2795         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
2796                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2797                         bmsr |= BMSR_LSTATUS;
2798                 else
2799                         bmsr &= ~BMSR_LSTATUS;
2800         }
2801
2802         err |= tg3_readphy(tp, MII_BMCR, &bmcr);
2803
2804         if ((tp->link_config.autoneg == AUTONEG_ENABLE) && !force_reset &&
2805             (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2806                 /* do nothing, just check for link up at the end */
2807         } else if (tp->link_config.autoneg == AUTONEG_ENABLE) {
2808                 u32 adv, new_adv;
2809
2810                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2811                 new_adv = adv & ~(ADVERTISE_1000XFULL | ADVERTISE_1000XHALF |
2812                                   ADVERTISE_1000XPAUSE |
2813                                   ADVERTISE_1000XPSE_ASYM |
2814                                   ADVERTISE_SLCT);
2815
2816                 /* Always advertise symmetric PAUSE just like copper */
2817                 new_adv |= ADVERTISE_1000XPAUSE;
2818
2819                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Half)
2820                         new_adv |= ADVERTISE_1000XHALF;
2821                 if (tp->link_config.advertising & ADVERTISED_1000baseT_Full)
2822                         new_adv |= ADVERTISE_1000XFULL;
2823
2824                 if ((new_adv != adv) || !(bmcr & BMCR_ANENABLE)) {
2825                         tg3_writephy(tp, MII_ADVERTISE, new_adv);
2826                         bmcr |= BMCR_ANENABLE | BMCR_ANRESTART;
2827                         tg3_writephy(tp, MII_BMCR, bmcr);
2828
2829                         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2830                         tp->serdes_counter = SERDES_AN_TIMEOUT_5714S;
2831                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2832
2833                         return err;
2834                 }
2835         } else {
2836                 u32 new_bmcr;
2837
2838                 bmcr &= ~BMCR_SPEED1000;
2839                 new_bmcr = bmcr & ~(BMCR_ANENABLE | BMCR_FULLDPLX);
2840
2841                 if (tp->link_config.duplex == DUPLEX_FULL)
2842                         new_bmcr |= BMCR_FULLDPLX;
2843
2844                 if (new_bmcr != bmcr) {
2845                         /* BMCR_SPEED1000 is a reserved bit that needs
2846                          * to be set on write.
2847                          */
2848                         new_bmcr |= BMCR_SPEED1000;
2849
2850                         /* Force a linkdown */
2851                         if (netif_carrier_ok(tp->dev)) {
2852                                 u32 adv;
2853
2854                                 err |= tg3_readphy(tp, MII_ADVERTISE, &adv);
2855                                 adv &= ~(ADVERTISE_1000XFULL |
2856                                          ADVERTISE_1000XHALF |
2857                                          ADVERTISE_SLCT);
2858                                 tg3_writephy(tp, MII_ADVERTISE, adv);
2859                                 tg3_writephy(tp, MII_BMCR, bmcr |
2860                                                            BMCR_ANRESTART |
2861                                                            BMCR_ANENABLE);
2862                                 udelay(10);
2863                                 netif_carrier_off(tp->dev);
2864                         }
2865                         tg3_writephy(tp, MII_BMCR, new_bmcr);
2866                         bmcr = new_bmcr;
2867                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2868                         err |= tg3_readphy(tp, MII_BMSR, &bmsr);
2869                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
2870                             ASIC_REV_5714) {
2871                                 if (tr32(MAC_TX_STATUS) & TX_STATUS_LINK_UP)
2872                                         bmsr |= BMSR_LSTATUS;
2873                                 else
2874                                         bmsr &= ~BMSR_LSTATUS;
2875                         }
2876                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2877                 }
2878         }
2879
2880         if (bmsr & BMSR_LSTATUS) {
2881                 current_speed = SPEED_1000;
2882                 current_link_up = 1;
2883                 if (bmcr & BMCR_FULLDPLX)
2884                         current_duplex = DUPLEX_FULL;
2885                 else
2886                         current_duplex = DUPLEX_HALF;
2887
2888                 if (bmcr & BMCR_ANENABLE) {
2889                         u32 local_adv, remote_adv, common;
2890
2891                         err |= tg3_readphy(tp, MII_ADVERTISE, &local_adv);
2892                         err |= tg3_readphy(tp, MII_LPA, &remote_adv);
2893                         common = local_adv & remote_adv;
2894                         if (common & (ADVERTISE_1000XHALF |
2895                                       ADVERTISE_1000XFULL)) {
2896                                 if (common & ADVERTISE_1000XFULL)
2897                                         current_duplex = DUPLEX_FULL;
2898                                 else
2899                                         current_duplex = DUPLEX_HALF;
2900
2901                                 tg3_setup_flow_control(tp, local_adv,
2902                                                        remote_adv);
2903                         }
2904                         else
2905                                 current_link_up = 0;
2906                 }
2907         }
2908
2909         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
2910         if (tp->link_config.active_duplex == DUPLEX_HALF)
2911                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
2912
2913         tw32_f(MAC_MODE, tp->mac_mode);
2914         udelay(40);
2915
2916         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
2917
2918         tp->link_config.active_speed = current_speed;
2919         tp->link_config.active_duplex = current_duplex;
2920
2921         if (current_link_up != netif_carrier_ok(tp->dev)) {
2922                 if (current_link_up)
2923                         netif_carrier_on(tp->dev);
2924                 else {
2925                         netif_carrier_off(tp->dev);
2926                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2927                 }
2928                 tg3_link_report(tp);
2929         }
2930         return err;
2931 }
2932
2933 static void tg3_serdes_parallel_detect(struct tg3 *tp)
2934 {
2935         if (tp->serdes_counter) {
2936                 /* Give autoneg time to complete. */
2937                 tp->serdes_counter--;
2938                 return;
2939         }
2940         if (!netif_carrier_ok(tp->dev) &&
2941             (tp->link_config.autoneg == AUTONEG_ENABLE)) {
2942                 u32 bmcr;
2943
2944                 tg3_readphy(tp, MII_BMCR, &bmcr);
2945                 if (bmcr & BMCR_ANENABLE) {
2946                         u32 phy1, phy2;
2947
2948                         /* Select shadow register 0x1f */
2949                         tg3_writephy(tp, 0x1c, 0x7c00);
2950                         tg3_readphy(tp, 0x1c, &phy1);
2951
2952                         /* Select expansion interrupt status register */
2953                         tg3_writephy(tp, 0x17, 0x0f01);
2954                         tg3_readphy(tp, 0x15, &phy2);
2955                         tg3_readphy(tp, 0x15, &phy2);
2956
2957                         if ((phy1 & 0x10) && !(phy2 & 0x20)) {
2958                                 /* We have signal detect and not receiving
2959                                  * config code words, link is up by parallel
2960                                  * detection.
2961                                  */
2962
2963                                 bmcr &= ~BMCR_ANENABLE;
2964                                 bmcr |= BMCR_SPEED1000 | BMCR_FULLDPLX;
2965                                 tg3_writephy(tp, MII_BMCR, bmcr);
2966                                 tp->tg3_flags2 |= TG3_FLG2_PARALLEL_DETECT;
2967                         }
2968                 }
2969         }
2970         else if (netif_carrier_ok(tp->dev) &&
2971                  (tp->link_config.autoneg == AUTONEG_ENABLE) &&
2972                  (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT)) {
2973                 u32 phy2;
2974
2975                 /* Select expansion interrupt status register */
2976                 tg3_writephy(tp, 0x17, 0x0f01);
2977                 tg3_readphy(tp, 0x15, &phy2);
2978                 if (phy2 & 0x20) {
2979                         u32 bmcr;
2980
2981                         /* Config code words received, turn on autoneg. */
2982                         tg3_readphy(tp, MII_BMCR, &bmcr);
2983                         tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANENABLE);
2984
2985                         tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
2986
2987                 }
2988         }
2989 }
2990
2991 static int tg3_setup_phy(struct tg3 *tp, int force_reset)
2992 {
2993         int err;
2994
2995         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
2996                 err = tg3_setup_fiber_phy(tp, force_reset);
2997         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
2998                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
2999         } else {
3000                 err = tg3_setup_copper_phy(tp, force_reset);
3001         }
3002
3003         if (tp->link_config.active_speed == SPEED_1000 &&
3004             tp->link_config.active_duplex == DUPLEX_HALF)
3005                 tw32(MAC_TX_LENGTHS,
3006                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3007                       (6 << TX_LENGTHS_IPG_SHIFT) |
3008                       (0xff << TX_LENGTHS_SLOT_TIME_SHIFT)));
3009         else
3010                 tw32(MAC_TX_LENGTHS,
3011                      ((2 << TX_LENGTHS_IPG_CRS_SHIFT) |
3012                       (6 << TX_LENGTHS_IPG_SHIFT) |
3013                       (32 << TX_LENGTHS_SLOT_TIME_SHIFT)));
3014
3015         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
3016                 if (netif_carrier_ok(tp->dev)) {
3017                         tw32(HOSTCC_STAT_COAL_TICKS,
3018                              tp->coal.stats_block_coalesce_usecs);
3019                 } else {
3020                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
3021                 }
3022         }
3023
3024         return err;
3025 }
3026
3027 /* This is called whenever we suspect that the system chipset is re-
3028  * ordering the sequence of MMIO to the tx send mailbox. The symptom
3029  * is bogus tx completions. We try to recover by setting the
3030  * TG3_FLAG_MBOX_WRITE_REORDER flag and resetting the chip later
3031  * in the workqueue.
3032  */
3033 static void tg3_tx_recover(struct tg3 *tp)
3034 {
3035         BUG_ON((tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER) ||
3036                tp->write32_tx_mbox == tg3_write_indirect_mbox);
3037
3038         printk(KERN_WARNING PFX "%s: The system may be re-ordering memory-"
3039                "mapped I/O cycles to the network device, attempting to "
3040                "recover. Please report the problem to the driver maintainer "
3041                "and include system chipset information.\n", tp->dev->name);
3042
3043         spin_lock(&tp->lock);
3044         tp->tg3_flags |= TG3_FLAG_TX_RECOVERY_PENDING;
3045         spin_unlock(&tp->lock);
3046 }
3047
3048 static inline u32 tg3_tx_avail(struct tg3 *tp)
3049 {
3050         smp_mb();
3051         return (tp->tx_pending -
3052                 ((tp->tx_prod - tp->tx_cons) & (TG3_TX_RING_SIZE - 1)));
3053 }
3054
3055 /* Tigon3 never reports partial packet sends.  So we do not
3056  * need special logic to handle SKBs that have not had all
3057  * of their frags sent yet, like SunGEM does.
3058  */
3059 static void tg3_tx(struct tg3 *tp)
3060 {
3061         u32 hw_idx = tp->hw_status->idx[0].tx_consumer;
3062         u32 sw_idx = tp->tx_cons;
3063
3064         while (sw_idx != hw_idx) {
3065                 struct tx_ring_info *ri = &tp->tx_buffers[sw_idx];
3066                 struct sk_buff *skb = ri->skb;
3067                 int i, tx_bug = 0;
3068
3069                 if (unlikely(skb == NULL)) {
3070                         tg3_tx_recover(tp);
3071                         return;
3072                 }
3073
3074                 pci_unmap_single(tp->pdev,
3075                                  pci_unmap_addr(ri, mapping),
3076                                  skb_headlen(skb),
3077                                  PCI_DMA_TODEVICE);
3078
3079                 ri->skb = NULL;
3080
3081                 sw_idx = NEXT_TX(sw_idx);
3082
3083                 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
3084                         ri = &tp->tx_buffers[sw_idx];
3085                         if (unlikely(ri->skb != NULL || sw_idx == hw_idx))
3086                                 tx_bug = 1;
3087
3088                         pci_unmap_page(tp->pdev,
3089                                        pci_unmap_addr(ri, mapping),
3090                                        skb_shinfo(skb)->frags[i].size,
3091                                        PCI_DMA_TODEVICE);
3092
3093                         sw_idx = NEXT_TX(sw_idx);
3094                 }
3095
3096                 dev_kfree_skb(skb);
3097
3098                 if (unlikely(tx_bug)) {
3099                         tg3_tx_recover(tp);
3100                         return;
3101                 }
3102         }
3103
3104         tp->tx_cons = sw_idx;
3105
3106         /* Need to make the tx_cons update visible to tg3_start_xmit()
3107          * before checking for netif_queue_stopped().  Without the
3108          * memory barrier, there is a small possibility that tg3_start_xmit()
3109          * will miss it and cause the queue to be stopped forever.
3110          */
3111         smp_mb();
3112
3113         if (unlikely(netif_queue_stopped(tp->dev) &&
3114                      (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))) {
3115                 netif_tx_lock(tp->dev);
3116                 if (netif_queue_stopped(tp->dev) &&
3117                     (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp)))
3118                         netif_wake_queue(tp->dev);
3119                 netif_tx_unlock(tp->dev);
3120         }
3121 }
3122
3123 /* Returns size of skb allocated or < 0 on error.
3124  *
3125  * We only need to fill in the address because the other members
3126  * of the RX descriptor are invariant, see tg3_init_rings.
3127  *
3128  * Note the purposeful assymetry of cpu vs. chip accesses.  For
3129  * posting buffers we only dirty the first cache line of the RX
3130  * descriptor (containing the address).  Whereas for the RX status
3131  * buffers the cpu only reads the last cacheline of the RX descriptor
3132  * (to fetch the error flags, vlan tag, checksum, and opaque cookie).
3133  */
3134 static int tg3_alloc_rx_skb(struct tg3 *tp, u32 opaque_key,
3135                             int src_idx, u32 dest_idx_unmasked)
3136 {
3137         struct tg3_rx_buffer_desc *desc;
3138         struct ring_info *map, *src_map;
3139         struct sk_buff *skb;
3140         dma_addr_t mapping;
3141         int skb_size, dest_idx;
3142
3143         src_map = NULL;
3144         switch (opaque_key) {
3145         case RXD_OPAQUE_RING_STD:
3146                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3147                 desc = &tp->rx_std[dest_idx];
3148                 map = &tp->rx_std_buffers[dest_idx];
3149                 if (src_idx >= 0)
3150                         src_map = &tp->rx_std_buffers[src_idx];
3151                 skb_size = tp->rx_pkt_buf_sz;
3152                 break;
3153
3154         case RXD_OPAQUE_RING_JUMBO:
3155                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3156                 desc = &tp->rx_jumbo[dest_idx];
3157                 map = &tp->rx_jumbo_buffers[dest_idx];
3158                 if (src_idx >= 0)
3159                         src_map = &tp->rx_jumbo_buffers[src_idx];
3160                 skb_size = RX_JUMBO_PKT_BUF_SZ;
3161                 break;
3162
3163         default:
3164                 return -EINVAL;
3165         };
3166
3167         /* Do not overwrite any of the map or rp information
3168          * until we are sure we can commit to a new buffer.
3169          *
3170          * Callers depend upon this behavior and assume that
3171          * we leave everything unchanged if we fail.
3172          */
3173         skb = netdev_alloc_skb(tp->dev, skb_size);
3174         if (skb == NULL)
3175                 return -ENOMEM;
3176
3177         skb_reserve(skb, tp->rx_offset);
3178
3179         mapping = pci_map_single(tp->pdev, skb->data,
3180                                  skb_size - tp->rx_offset,
3181                                  PCI_DMA_FROMDEVICE);
3182
3183         map->skb = skb;
3184         pci_unmap_addr_set(map, mapping, mapping);
3185
3186         if (src_map != NULL)
3187                 src_map->skb = NULL;
3188
3189         desc->addr_hi = ((u64)mapping >> 32);
3190         desc->addr_lo = ((u64)mapping & 0xffffffff);
3191
3192         return skb_size;
3193 }
3194
3195 /* We only need to move over in the address because the other
3196  * members of the RX descriptor are invariant.  See notes above
3197  * tg3_alloc_rx_skb for full details.
3198  */
3199 static void tg3_recycle_rx(struct tg3 *tp, u32 opaque_key,
3200                            int src_idx, u32 dest_idx_unmasked)
3201 {
3202         struct tg3_rx_buffer_desc *src_desc, *dest_desc;
3203         struct ring_info *src_map, *dest_map;
3204         int dest_idx;
3205
3206         switch (opaque_key) {
3207         case RXD_OPAQUE_RING_STD:
3208                 dest_idx = dest_idx_unmasked % TG3_RX_RING_SIZE;
3209                 dest_desc = &tp->rx_std[dest_idx];
3210                 dest_map = &tp->rx_std_buffers[dest_idx];
3211                 src_desc = &tp->rx_std[src_idx];
3212                 src_map = &tp->rx_std_buffers[src_idx];
3213                 break;
3214
3215         case RXD_OPAQUE_RING_JUMBO:
3216                 dest_idx = dest_idx_unmasked % TG3_RX_JUMBO_RING_SIZE;
3217                 dest_desc = &tp->rx_jumbo[dest_idx];
3218                 dest_map = &tp->rx_jumbo_buffers[dest_idx];
3219                 src_desc = &tp->rx_jumbo[src_idx];
3220                 src_map = &tp->rx_jumbo_buffers[src_idx];
3221                 break;
3222
3223         default:
3224                 return;
3225         };
3226
3227         dest_map->skb = src_map->skb;
3228         pci_unmap_addr_set(dest_map, mapping,
3229                            pci_unmap_addr(src_map, mapping));
3230         dest_desc->addr_hi = src_desc->addr_hi;
3231         dest_desc->addr_lo = src_desc->addr_lo;
3232
3233         src_map->skb = NULL;
3234 }
3235
3236 #if TG3_VLAN_TAG_USED
3237 static int tg3_vlan_rx(struct tg3 *tp, struct sk_buff *skb, u16 vlan_tag)
3238 {
3239         return vlan_hwaccel_receive_skb(skb, tp->vlgrp, vlan_tag);
3240 }
3241 #endif
3242
3243 /* The RX ring scheme is composed of multiple rings which post fresh
3244  * buffers to the chip, and one special ring the chip uses to report
3245  * status back to the host.
3246  *
3247  * The special ring reports the status of received packets to the
3248  * host.  The chip does not write into the original descriptor the
3249  * RX buffer was obtained from.  The chip simply takes the original
3250  * descriptor as provided by the host, updates the status and length
3251  * field, then writes this into the next status ring entry.
3252  *
3253  * Each ring the host uses to post buffers to the chip is described
3254  * by a TG3_BDINFO entry in the chips SRAM area.  When a packet arrives,
3255  * it is first placed into the on-chip ram.  When the packet's length
3256  * is known, it walks down the TG3_BDINFO entries to select the ring.
3257  * Each TG3_BDINFO specifies a MAXLEN field and the first TG3_BDINFO
3258  * which is within the range of the new packet's length is chosen.
3259  *
3260  * The "separate ring for rx status" scheme may sound queer, but it makes
3261  * sense from a cache coherency perspective.  If only the host writes
3262  * to the buffer post rings, and only the chip writes to the rx status
3263  * rings, then cache lines never move beyond shared-modified state.
3264  * If both the host and chip were to write into the same ring, cache line
3265  * eviction could occur since both entities want it in an exclusive state.
3266  */
3267 static int tg3_rx(struct tg3 *tp, int budget)
3268 {
3269         u32 work_mask, rx_std_posted = 0;
3270         u32 sw_idx = tp->rx_rcb_ptr;
3271         u16 hw_idx;
3272         int received;
3273
3274         hw_idx = tp->hw_status->idx[0].rx_producer;
3275         /*
3276          * We need to order the read of hw_idx and the read of
3277          * the opaque cookie.
3278          */
3279         rmb();
3280         work_mask = 0;
3281         received = 0;
3282         while (sw_idx != hw_idx && budget > 0) {
3283                 struct tg3_rx_buffer_desc *desc = &tp->rx_rcb[sw_idx];
3284                 unsigned int len;
3285                 struct sk_buff *skb;
3286                 dma_addr_t dma_addr;
3287                 u32 opaque_key, desc_idx, *post_ptr;
3288
3289                 desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
3290                 opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
3291                 if (opaque_key == RXD_OPAQUE_RING_STD) {
3292                         dma_addr = pci_unmap_addr(&tp->rx_std_buffers[desc_idx],
3293                                                   mapping);
3294                         skb = tp->rx_std_buffers[desc_idx].skb;
3295                         post_ptr = &tp->rx_std_ptr;
3296                         rx_std_posted++;
3297                 } else if (opaque_key == RXD_OPAQUE_RING_JUMBO) {
3298                         dma_addr = pci_unmap_addr(&tp->rx_jumbo_buffers[desc_idx],
3299                                                   mapping);
3300                         skb = tp->rx_jumbo_buffers[desc_idx].skb;
3301                         post_ptr = &tp->rx_jumbo_ptr;
3302                 }
3303                 else {
3304                         goto next_pkt_nopost;
3305                 }
3306
3307                 work_mask |= opaque_key;
3308
3309                 if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
3310                     (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII)) {
3311                 drop_it:
3312                         tg3_recycle_rx(tp, opaque_key,
3313                                        desc_idx, *post_ptr);
3314                 drop_it_no_recycle:
3315                         /* Other statistics kept track of by card. */
3316                         tp->net_stats.rx_dropped++;
3317                         goto next_pkt;
3318                 }
3319
3320                 len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4; /* omit crc */
3321
3322                 if (len > RX_COPY_THRESHOLD
3323                         && tp->rx_offset == 2
3324                         /* rx_offset != 2 iff this is a 5701 card running
3325                          * in PCI-X mode [see tg3_get_invariants()] */
3326                 ) {
3327                         int skb_size;
3328
3329                         skb_size = tg3_alloc_rx_skb(tp, opaque_key,
3330                                                     desc_idx, *post_ptr);
3331                         if (skb_size < 0)
3332                                 goto drop_it;
3333
3334                         pci_unmap_single(tp->pdev, dma_addr,
3335                                          skb_size - tp->rx_offset,
3336                                          PCI_DMA_FROMDEVICE);
3337
3338                         skb_put(skb, len);
3339                 } else {
3340                         struct sk_buff *copy_skb;
3341
3342                         tg3_recycle_rx(tp, opaque_key,
3343                                        desc_idx, *post_ptr);
3344
3345                         copy_skb = netdev_alloc_skb(tp->dev, len + 2);
3346                         if (copy_skb == NULL)
3347                                 goto drop_it_no_recycle;
3348
3349                         skb_reserve(copy_skb, 2);
3350                         skb_put(copy_skb, len);
3351                         pci_dma_sync_single_for_cpu(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3352                         memcpy(copy_skb->data, skb->data, len);
3353                         pci_dma_sync_single_for_device(tp->pdev, dma_addr, len, PCI_DMA_FROMDEVICE);
3354
3355                         /* We'll reuse the original ring buffer. */
3356                         skb = copy_skb;
3357                 }
3358
3359                 if ((tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) &&
3360                     (desc->type_flags & RXD_FLAG_TCPUDP_CSUM) &&
3361                     (((desc->ip_tcp_csum & RXD_TCPCSUM_MASK)
3362                       >> RXD_TCPCSUM_SHIFT) == 0xffff))
3363                         skb->ip_summed = CHECKSUM_UNNECESSARY;
3364                 else
3365                         skb->ip_summed = CHECKSUM_NONE;
3366
3367                 skb->protocol = eth_type_trans(skb, tp->dev);
3368 #if TG3_VLAN_TAG_USED
3369                 if (tp->vlgrp != NULL &&
3370                     desc->type_flags & RXD_FLAG_VLAN) {
3371                         tg3_vlan_rx(tp, skb,
3372                                     desc->err_vlan & RXD_VLAN_MASK);
3373                 } else
3374 #endif
3375                         netif_receive_skb(skb);
3376
3377                 tp->dev->last_rx = jiffies;
3378                 received++;
3379                 budget--;
3380
3381 next_pkt:
3382                 (*post_ptr)++;
3383
3384                 if (unlikely(rx_std_posted >= tp->rx_std_max_post)) {
3385                         u32 idx = *post_ptr % TG3_RX_RING_SIZE;
3386
3387                         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX +
3388                                      TG3_64BIT_REG_LOW, idx);
3389                         work_mask &= ~RXD_OPAQUE_RING_STD;
3390                         rx_std_posted = 0;
3391                 }
3392 next_pkt_nopost:
3393                 sw_idx++;
3394                 sw_idx &= (TG3_RX_RCB_RING_SIZE(tp) - 1);
3395
3396                 /* Refresh hw_idx to see if there is new work */
3397                 if (sw_idx == hw_idx) {
3398                         hw_idx = tp->hw_status->idx[0].rx_producer;
3399                         rmb();
3400                 }
3401         }
3402
3403         /* ACK the status ring. */
3404         tp->rx_rcb_ptr = sw_idx;
3405         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, sw_idx);
3406
3407         /* Refill RX ring(s). */
3408         if (work_mask & RXD_OPAQUE_RING_STD) {
3409                 sw_idx = tp->rx_std_ptr % TG3_RX_RING_SIZE;
3410                 tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
3411                              sw_idx);
3412         }
3413         if (work_mask & RXD_OPAQUE_RING_JUMBO) {
3414                 sw_idx = tp->rx_jumbo_ptr % TG3_RX_JUMBO_RING_SIZE;
3415                 tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
3416                              sw_idx);
3417         }
3418         mmiowb();
3419
3420         return received;
3421 }
3422
3423 static int tg3_poll(struct net_device *netdev, int *budget)
3424 {
3425         struct tg3 *tp = netdev_priv(netdev);
3426         struct tg3_hw_status *sblk = tp->hw_status;
3427         int done;
3428
3429         /* handle link change and other phy events */
3430         if (!(tp->tg3_flags &
3431               (TG3_FLAG_USE_LINKCHG_REG |
3432                TG3_FLAG_POLL_SERDES))) {
3433                 if (sblk->status & SD_STATUS_LINK_CHG) {
3434                         sblk->status = SD_STATUS_UPDATED |
3435                                 (sblk->status & ~SD_STATUS_LINK_CHG);
3436                         spin_lock(&tp->lock);
3437                         tg3_setup_phy(tp, 0);
3438                         spin_unlock(&tp->lock);
3439                 }
3440         }
3441
3442         /* run TX completion thread */
3443         if (sblk->idx[0].tx_consumer != tp->tx_cons) {
3444                 tg3_tx(tp);
3445                 if (unlikely(tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING)) {
3446                         netif_rx_complete(netdev);
3447                         schedule_work(&tp->reset_task);
3448                         return 0;
3449                 }
3450         }
3451
3452         /* run RX thread, within the bounds set by NAPI.
3453          * All RX "locking" is done by ensuring outside
3454          * code synchronizes with dev->poll()
3455          */
3456         if (sblk->idx[0].rx_producer != tp->rx_rcb_ptr) {
3457                 int orig_budget = *budget;
3458                 int work_done;
3459
3460                 if (orig_budget > netdev->quota)
3461                         orig_budget = netdev->quota;
3462
3463                 work_done = tg3_rx(tp, orig_budget);
3464
3465                 *budget -= work_done;
3466                 netdev->quota -= work_done;
3467         }
3468
3469         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
3470                 tp->last_tag = sblk->status_tag;
3471                 rmb();
3472         } else
3473                 sblk->status &= ~SD_STATUS_UPDATED;
3474
3475         /* if no more work, tell net stack and NIC we're done */
3476         done = !tg3_has_work(tp);
3477         if (done) {
3478                 netif_rx_complete(netdev);
3479                 tg3_restart_ints(tp);
3480         }
3481
3482         return (done ? 0 : 1);
3483 }
3484
3485 static void tg3_irq_quiesce(struct tg3 *tp)
3486 {
3487         BUG_ON(tp->irq_sync);
3488
3489         tp->irq_sync = 1;
3490         smp_mb();
3491
3492         synchronize_irq(tp->pdev->irq);
3493 }
3494
3495 static inline int tg3_irq_sync(struct tg3 *tp)
3496 {
3497         return tp->irq_sync;
3498 }
3499
3500 /* Fully shutdown all tg3 driver activity elsewhere in the system.
3501  * If irq_sync is non-zero, then the IRQ handler must be synchronized
3502  * with as well.  Most of the time, this is not necessary except when
3503  * shutting down the device.
3504  */
3505 static inline void tg3_full_lock(struct tg3 *tp, int irq_sync)
3506 {
3507         if (irq_sync)
3508                 tg3_irq_quiesce(tp);
3509         spin_lock_bh(&tp->lock);
3510 }
3511
3512 static inline void tg3_full_unlock(struct tg3 *tp)
3513 {
3514         spin_unlock_bh(&tp->lock);
3515 }
3516
3517 /* One-shot MSI handler - Chip automatically disables interrupt
3518  * after sending MSI so driver doesn't have to do it.
3519  */
3520 static irqreturn_t tg3_msi_1shot(int irq, void *dev_id)
3521 {
3522         struct net_device *dev = dev_id;
3523         struct tg3 *tp = netdev_priv(dev);
3524
3525         prefetch(tp->hw_status);
3526         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3527
3528         if (likely(!tg3_irq_sync(tp)))
3529                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3530
3531         return IRQ_HANDLED;
3532 }
3533
3534 /* MSI ISR - No need to check for interrupt sharing and no need to
3535  * flush status block and interrupt mailbox. PCI ordering rules
3536  * guarantee that MSI will arrive after the status block.
3537  */
3538 static irqreturn_t tg3_msi(int irq, void *dev_id)
3539 {
3540         struct net_device *dev = dev_id;
3541         struct tg3 *tp = netdev_priv(dev);
3542
3543         prefetch(tp->hw_status);
3544         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3545         /*
3546          * Writing any value to intr-mbox-0 clears PCI INTA# and
3547          * chip-internal interrupt pending events.
3548          * Writing non-zero to intr-mbox-0 additional tells the
3549          * NIC to stop sending us irqs, engaging "in-intr-handler"
3550          * event coalescing.
3551          */
3552         tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0x00000001);
3553         if (likely(!tg3_irq_sync(tp)))
3554                 netif_rx_schedule(dev);         /* schedule NAPI poll */
3555
3556         return IRQ_RETVAL(1);
3557 }
3558
3559 static irqreturn_t tg3_interrupt(int irq, void *dev_id)
3560 {
3561         struct net_device *dev = dev_id;
3562         struct tg3 *tp = netdev_priv(dev);
3563         struct tg3_hw_status *sblk = tp->hw_status;
3564         unsigned int handled = 1;
3565
3566         /* In INTx mode, it is possible for the interrupt to arrive at
3567          * the CPU before the status block posted prior to the interrupt.
3568          * Reading the PCI State register will confirm whether the
3569          * interrupt is ours and will flush the status block.
3570          */
3571         if ((sblk->status & SD_STATUS_UPDATED) ||
3572             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3573                 /*
3574                  * Writing any value to intr-mbox-0 clears PCI INTA# and
3575                  * chip-internal interrupt pending events.
3576                  * Writing non-zero to intr-mbox-0 additional tells the
3577                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3578                  * event coalescing.
3579                  */
3580                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3581                              0x00000001);
3582                 if (tg3_irq_sync(tp))
3583                         goto out;
3584                 sblk->status &= ~SD_STATUS_UPDATED;
3585                 if (likely(tg3_has_work(tp))) {
3586                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3587                         netif_rx_schedule(dev);         /* schedule NAPI poll */
3588                 } else {
3589                         /* No work, shared interrupt perhaps?  re-enable
3590                          * interrupts, and flush that PCI write
3591                          */
3592                         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3593                                 0x00000000);
3594                 }
3595         } else {        /* shared interrupt */
3596                 handled = 0;
3597         }
3598 out:
3599         return IRQ_RETVAL(handled);
3600 }
3601
3602 static irqreturn_t tg3_interrupt_tagged(int irq, void *dev_id)
3603 {
3604         struct net_device *dev = dev_id;
3605         struct tg3 *tp = netdev_priv(dev);
3606         struct tg3_hw_status *sblk = tp->hw_status;
3607         unsigned int handled = 1;
3608
3609         /* In INTx mode, it is possible for the interrupt to arrive at
3610          * the CPU before the status block posted prior to the interrupt.
3611          * Reading the PCI State register will confirm whether the
3612          * interrupt is ours and will flush the status block.
3613          */
3614         if ((sblk->status_tag != tp->last_tag) ||
3615             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3616                 /*
3617                  * writing any value to intr-mbox-0 clears PCI INTA# and
3618                  * chip-internal interrupt pending events.
3619                  * writing non-zero to intr-mbox-0 additional tells the
3620                  * NIC to stop sending us irqs, engaging "in-intr-handler"
3621                  * event coalescing.
3622                  */
3623                 tw32_mailbox(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW,
3624                              0x00000001);
3625                 if (tg3_irq_sync(tp))
3626                         goto out;
3627                 if (netif_rx_schedule_prep(dev)) {
3628                         prefetch(&tp->rx_rcb[tp->rx_rcb_ptr]);
3629                         /* Update last_tag to mark that this status has been
3630                          * seen. Because interrupt may be shared, we may be
3631                          * racing with tg3_poll(), so only update last_tag
3632                          * if tg3_poll() is not scheduled.
3633                          */
3634                         tp->last_tag = sblk->status_tag;
3635                         __netif_rx_schedule(dev);
3636                 }
3637         } else {        /* shared interrupt */
3638                 handled = 0;
3639         }
3640 out:
3641         return IRQ_RETVAL(handled);
3642 }
3643
3644 /* ISR for interrupt test */
3645 static irqreturn_t tg3_test_isr(int irq, void *dev_id)
3646 {
3647         struct net_device *dev = dev_id;
3648         struct tg3 *tp = netdev_priv(dev);
3649         struct tg3_hw_status *sblk = tp->hw_status;
3650
3651         if ((sblk->status & SD_STATUS_UPDATED) ||
3652             !(tr32(TG3PCI_PCISTATE) & PCISTATE_INT_NOT_ACTIVE)) {
3653                 tg3_disable_ints(tp);
3654                 return IRQ_RETVAL(1);
3655         }
3656         return IRQ_RETVAL(0);
3657 }
3658
3659 static int tg3_init_hw(struct tg3 *, int);
3660 static int tg3_halt(struct tg3 *, int, int);
3661
3662 /* Restart hardware after configuration changes, self-test, etc.
3663  * Invoked with tp->lock held.
3664  */
3665 static int tg3_restart_hw(struct tg3 *tp, int reset_phy)
3666 {
3667         int err;
3668
3669         err = tg3_init_hw(tp, reset_phy);
3670         if (err) {
3671                 printk(KERN_ERR PFX "%s: Failed to re-initialize device, "
3672                        "aborting.\n", tp->dev->name);
3673                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
3674                 tg3_full_unlock(tp);
3675                 del_timer_sync(&tp->timer);
3676                 tp->irq_sync = 0;
3677                 netif_poll_enable(tp->dev);
3678                 dev_close(tp->dev);
3679                 tg3_full_lock(tp, 0);
3680         }
3681         return err;
3682 }
3683
3684 #ifdef CONFIG_NET_POLL_CONTROLLER
3685 static void tg3_poll_controller(struct net_device *dev)
3686 {
3687         struct tg3 *tp = netdev_priv(dev);
3688
3689         tg3_interrupt(tp->pdev->irq, dev);
3690 }
3691 #endif
3692
3693 static void tg3_reset_task(struct work_struct *work)
3694 {
3695         struct tg3 *tp = container_of(work, struct tg3, reset_task);
3696         unsigned int restart_timer;
3697
3698         tg3_full_lock(tp, 0);
3699         tp->tg3_flags |= TG3_FLAG_IN_RESET_TASK;
3700
3701         if (!netif_running(tp->dev)) {
3702                 tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3703                 tg3_full_unlock(tp);
3704                 return;
3705         }
3706
3707         tg3_full_unlock(tp);
3708
3709         tg3_netif_stop(tp);
3710
3711         tg3_full_lock(tp, 1);
3712
3713         restart_timer = tp->tg3_flags2 & TG3_FLG2_RESTART_TIMER;
3714         tp->tg3_flags2 &= ~TG3_FLG2_RESTART_TIMER;
3715
3716         if (tp->tg3_flags & TG3_FLAG_TX_RECOVERY_PENDING) {
3717                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
3718                 tp->write32_rx_mbox = tg3_write_flush_reg32;
3719                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
3720                 tp->tg3_flags &= ~TG3_FLAG_TX_RECOVERY_PENDING;
3721         }
3722
3723         tg3_halt(tp, RESET_KIND_SHUTDOWN, 0);
3724         if (tg3_init_hw(tp, 1))
3725                 goto out;
3726
3727         tg3_netif_start(tp);
3728
3729         if (restart_timer)
3730                 mod_timer(&tp->timer, jiffies + 1);
3731
3732 out:
3733         tp->tg3_flags &= ~TG3_FLAG_IN_RESET_TASK;
3734
3735         tg3_full_unlock(tp);
3736 }
3737
3738 static void tg3_dump_short_state(struct tg3 *tp)
3739 {
3740         printk(KERN_ERR PFX "DEBUG: MAC_TX_STATUS[%08x] MAC_RX_STATUS[%08x]\n",
3741                tr32(MAC_TX_STATUS), tr32(MAC_RX_STATUS));
3742         printk(KERN_ERR PFX "DEBUG: RDMAC_STATUS[%08x] WDMAC_STATUS[%08x]\n",
3743                tr32(RDMAC_STATUS), tr32(WDMAC_STATUS));
3744 }
3745
3746 static void tg3_tx_timeout(struct net_device *dev)
3747 {
3748         struct tg3 *tp = netdev_priv(dev);
3749
3750         if (netif_msg_tx_err(tp)) {
3751                 printk(KERN_ERR PFX "%s: transmit timed out, resetting\n",
3752                        dev->name);
3753                 tg3_dump_short_state(tp);
3754         }
3755
3756         schedule_work(&tp->reset_task);
3757 }
3758
3759 /* Test for DMA buffers crossing any 4GB boundaries: 4G, 8G, etc */
3760 static inline int tg3_4g_overflow_test(dma_addr_t mapping, int len)
3761 {
3762         u32 base = (u32) mapping & 0xffffffff;
3763
3764         return ((base > 0xffffdcc0) &&
3765                 (base + len + 8 < base));
3766 }
3767
3768 /* Test for DMA addresses > 40-bit */
3769 static inline int tg3_40bit_overflow_test(struct tg3 *tp, dma_addr_t mapping,
3770                                           int len)
3771 {
3772 #if defined(CONFIG_HIGHMEM) && (BITS_PER_LONG == 64)
3773         if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG)
3774                 return (((u64) mapping + len) > DMA_40BIT_MASK);
3775         return 0;
3776 #else
3777         return 0;
3778 #endif
3779 }
3780
3781 static void tg3_set_txd(struct tg3 *, int, dma_addr_t, int, u32, u32);
3782
3783 /* Workaround 4GB and 40-bit hardware DMA bugs. */
3784 static int tigon3_dma_hwbug_workaround(struct tg3 *tp, struct sk_buff *skb,
3785                                        u32 last_plus_one, u32 *start,
3786                                        u32 base_flags, u32 mss)
3787 {
3788         struct sk_buff *new_skb = skb_copy(skb, GFP_ATOMIC);
3789         dma_addr_t new_addr = 0;
3790         u32 entry = *start;
3791         int i, ret = 0;
3792
3793         if (!new_skb) {
3794                 ret = -1;
3795         } else {
3796                 /* New SKB is guaranteed to be linear. */
3797                 entry = *start;
3798                 new_addr = pci_map_single(tp->pdev, new_skb->data, new_skb->len,
3799                                           PCI_DMA_TODEVICE);
3800                 /* Make sure new skb does not cross any 4G boundaries.
3801                  * Drop the packet if it does.
3802                  */
3803                 if (tg3_4g_overflow_test(new_addr, new_skb->len)) {
3804                         ret = -1;
3805                         dev_kfree_skb(new_skb);
3806                         new_skb = NULL;
3807                 } else {
3808                         tg3_set_txd(tp, entry, new_addr, new_skb->len,
3809                                     base_flags, 1 | (mss << 1));
3810                         *start = NEXT_TX(entry);
3811                 }
3812         }
3813
3814         /* Now clean up the sw ring entries. */
3815         i = 0;
3816         while (entry != last_plus_one) {
3817                 int len;
3818
3819                 if (i == 0)
3820                         len = skb_headlen(skb);
3821                 else
3822                         len = skb_shinfo(skb)->frags[i-1].size;
3823                 pci_unmap_single(tp->pdev,
3824                                  pci_unmap_addr(&tp->tx_buffers[entry], mapping),
3825                                  len, PCI_DMA_TODEVICE);
3826                 if (i == 0) {
3827                         tp->tx_buffers[entry].skb = new_skb;
3828                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, new_addr);
3829                 } else {
3830                         tp->tx_buffers[entry].skb = NULL;
3831                 }
3832                 entry = NEXT_TX(entry);
3833                 i++;
3834         }
3835
3836         dev_kfree_skb(skb);
3837
3838         return ret;
3839 }
3840
3841 static void tg3_set_txd(struct tg3 *tp, int entry,
3842                         dma_addr_t mapping, int len, u32 flags,
3843                         u32 mss_and_is_end)
3844 {
3845         struct tg3_tx_buffer_desc *txd = &tp->tx_ring[entry];
3846         int is_end = (mss_and_is_end & 0x1);
3847         u32 mss = (mss_and_is_end >> 1);
3848         u32 vlan_tag = 0;
3849
3850         if (is_end)
3851                 flags |= TXD_FLAG_END;
3852         if (flags & TXD_FLAG_VLAN) {
3853                 vlan_tag = flags >> 16;
3854                 flags &= 0xffff;
3855         }
3856         vlan_tag |= (mss << TXD_MSS_SHIFT);
3857
3858         txd->addr_hi = ((u64) mapping >> 32);
3859         txd->addr_lo = ((u64) mapping & 0xffffffff);
3860         txd->len_flags = (len << TXD_LEN_SHIFT) | flags;
3861         txd->vlan_tag = vlan_tag << TXD_VLAN_TAG_SHIFT;
3862 }
3863
3864 /* hard_start_xmit for devices that don't have any bugs and
3865  * support TG3_FLG2_HW_TSO_2 only.
3866  */
3867 static int tg3_start_xmit(struct sk_buff *skb, struct net_device *dev)
3868 {
3869         struct tg3 *tp = netdev_priv(dev);
3870         dma_addr_t mapping;
3871         u32 len, entry, base_flags, mss;
3872
3873         len = skb_headlen(skb);
3874
3875         /* We are running in BH disabled context with netif_tx_lock
3876          * and TX reclaim runs via tp->poll inside of a software
3877          * interrupt.  Furthermore, IRQ processing runs lockless so we have
3878          * no IRQ context deadlocks to worry about either.  Rejoice!
3879          */
3880         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
3881                 if (!netif_queue_stopped(dev)) {
3882                         netif_stop_queue(dev);
3883
3884                         /* This is a hard error, log it. */
3885                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
3886                                "queue awake!\n", dev->name);
3887                 }
3888                 return NETDEV_TX_BUSY;
3889         }
3890
3891         entry = tp->tx_prod;
3892         base_flags = 0;
3893         mss = 0;
3894         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
3895             (mss = skb_shinfo(skb)->gso_size) != 0) {
3896                 int tcp_opt_len, ip_tcp_len;
3897
3898                 if (skb_header_cloned(skb) &&
3899                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
3900                         dev_kfree_skb(skb);
3901                         goto out_unlock;
3902                 }
3903
3904                 if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
3905                         mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
3906                 else {
3907                         tcp_opt_len = ((skb->h.th->doff - 5) * 4);
3908                         ip_tcp_len = (skb->nh.iph->ihl * 4) +
3909                                      sizeof(struct tcphdr);
3910
3911                         skb->nh.iph->check = 0;
3912                         skb->nh.iph->tot_len = htons(mss + ip_tcp_len +
3913                                                      tcp_opt_len);
3914                         mss |= (ip_tcp_len + tcp_opt_len) << 9;
3915                 }
3916
3917                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
3918                                TXD_FLAG_CPU_POST_DMA);
3919
3920                 skb->h.th->check = 0;
3921
3922         }
3923         else if (skb->ip_summed == CHECKSUM_PARTIAL)
3924                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
3925 #if TG3_VLAN_TAG_USED
3926         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
3927                 base_flags |= (TXD_FLAG_VLAN |
3928                                (vlan_tx_tag_get(skb) << 16));
3929 #endif
3930
3931         /* Queue skb data, a.k.a. the main skb fragment. */
3932         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
3933
3934         tp->tx_buffers[entry].skb = skb;
3935         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3936
3937         tg3_set_txd(tp, entry, mapping, len, base_flags,
3938                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
3939
3940         entry = NEXT_TX(entry);
3941
3942         /* Now loop through additional data fragments, and queue them. */
3943         if (skb_shinfo(skb)->nr_frags > 0) {
3944                 unsigned int i, last;
3945
3946                 last = skb_shinfo(skb)->nr_frags - 1;
3947                 for (i = 0; i <= last; i++) {
3948                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
3949
3950                         len = frag->size;
3951                         mapping = pci_map_page(tp->pdev,
3952                                                frag->page,
3953                                                frag->page_offset,
3954                                                len, PCI_DMA_TODEVICE);
3955
3956                         tp->tx_buffers[entry].skb = NULL;
3957                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
3958
3959                         tg3_set_txd(tp, entry, mapping, len,
3960                                     base_flags, (i == last) | (mss << 1));
3961
3962                         entry = NEXT_TX(entry);
3963                 }
3964         }
3965
3966         /* Packets are ready, update Tx producer idx local and on card. */
3967         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
3968
3969         tp->tx_prod = entry;
3970         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
3971                 netif_stop_queue(dev);
3972                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
3973                         netif_wake_queue(tp->dev);
3974         }
3975
3976 out_unlock:
3977         mmiowb();
3978
3979         dev->trans_start = jiffies;
3980
3981         return NETDEV_TX_OK;
3982 }
3983
3984 static int tg3_start_xmit_dma_bug(struct sk_buff *, struct net_device *);
3985
3986 /* Use GSO to workaround a rare TSO bug that may be triggered when the
3987  * TSO header is greater than 80 bytes.
3988  */
3989 static int tg3_tso_bug(struct tg3 *tp, struct sk_buff *skb)
3990 {
3991         struct sk_buff *segs, *nskb;
3992
3993         /* Estimate the number of fragments in the worst case */
3994         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->gso_segs * 3))) {
3995                 netif_stop_queue(tp->dev);
3996                 return NETDEV_TX_BUSY;
3997         }
3998
3999         segs = skb_gso_segment(skb, tp->dev->features & ~NETIF_F_TSO);
4000         if (unlikely(IS_ERR(segs)))
4001                 goto tg3_tso_bug_end;
4002
4003         do {
4004                 nskb = segs;
4005                 segs = segs->next;
4006                 nskb->next = NULL;
4007                 tg3_start_xmit_dma_bug(nskb, tp->dev);
4008         } while (segs);
4009
4010 tg3_tso_bug_end:
4011         dev_kfree_skb(skb);
4012
4013         return NETDEV_TX_OK;
4014 }
4015
4016 /* hard_start_xmit for devices that have the 4G bug and/or 40-bit bug and
4017  * support TG3_FLG2_HW_TSO_1 or firmware TSO only.
4018  */
4019 static int tg3_start_xmit_dma_bug(struct sk_buff *skb, struct net_device *dev)
4020 {
4021         struct tg3 *tp = netdev_priv(dev);
4022         dma_addr_t mapping;
4023         u32 len, entry, base_flags, mss;
4024         int would_hit_hwbug;
4025
4026         len = skb_headlen(skb);
4027
4028         /* We are running in BH disabled context with netif_tx_lock
4029          * and TX reclaim runs via tp->poll inside of a software
4030          * interrupt.  Furthermore, IRQ processing runs lockless so we have
4031          * no IRQ context deadlocks to worry about either.  Rejoice!
4032          */
4033         if (unlikely(tg3_tx_avail(tp) <= (skb_shinfo(skb)->nr_frags + 1))) {
4034                 if (!netif_queue_stopped(dev)) {
4035                         netif_stop_queue(dev);
4036
4037                         /* This is a hard error, log it. */
4038                         printk(KERN_ERR PFX "%s: BUG! Tx Ring full when "
4039                                "queue awake!\n", dev->name);
4040                 }
4041                 return NETDEV_TX_BUSY;
4042         }
4043
4044         entry = tp->tx_prod;
4045         base_flags = 0;
4046         if (skb->ip_summed == CHECKSUM_PARTIAL)
4047                 base_flags |= TXD_FLAG_TCPUDP_CSUM;
4048         mss = 0;
4049         if (skb->len > (tp->dev->mtu + ETH_HLEN) &&
4050             (mss = skb_shinfo(skb)->gso_size) != 0) {
4051                 int tcp_opt_len, ip_tcp_len, hdr_len;
4052
4053                 if (skb_header_cloned(skb) &&
4054                     pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
4055                         dev_kfree_skb(skb);
4056                         goto out_unlock;
4057                 }
4058
4059                 tcp_opt_len = ((skb->h.th->doff - 5) * 4);
4060                 ip_tcp_len = (skb->nh.iph->ihl * 4) + sizeof(struct tcphdr);
4061
4062                 hdr_len = ip_tcp_len + tcp_opt_len;
4063                 if (unlikely((ETH_HLEN + hdr_len) > 80) &&
4064                              (tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG))
4065                         return (tg3_tso_bug(tp, skb));
4066
4067                 base_flags |= (TXD_FLAG_CPU_PRE_DMA |
4068                                TXD_FLAG_CPU_POST_DMA);
4069
4070                 skb->nh.iph->check = 0;
4071                 skb->nh.iph->tot_len = htons(mss + hdr_len);
4072                 if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
4073                         skb->h.th->check = 0;
4074                         base_flags &= ~TXD_FLAG_TCPUDP_CSUM;
4075                 }
4076                 else {
4077                         skb->h.th->check =
4078                                 ~csum_tcpudp_magic(skb->nh.iph->saddr,
4079                                                    skb->nh.iph->daddr,
4080                                                    0, IPPROTO_TCP, 0);
4081                 }
4082
4083                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO) ||
4084                     (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705)) {
4085                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4086                                 int tsflags;
4087
4088                                 tsflags = ((skb->nh.iph->ihl - 5) +
4089                                            (tcp_opt_len >> 2));
4090                                 mss |= (tsflags << 11);
4091                         }
4092                 } else {
4093                         if (tcp_opt_len || skb->nh.iph->ihl > 5) {
4094                                 int tsflags;
4095
4096                                 tsflags = ((skb->nh.iph->ihl - 5) +
4097                                            (tcp_opt_len >> 2));
4098                                 base_flags |= tsflags << 12;
4099                         }
4100                 }
4101         }
4102 #if TG3_VLAN_TAG_USED
4103         if (tp->vlgrp != NULL && vlan_tx_tag_present(skb))
4104                 base_flags |= (TXD_FLAG_VLAN |
4105                                (vlan_tx_tag_get(skb) << 16));
4106 #endif
4107
4108         /* Queue skb data, a.k.a. the main skb fragment. */
4109         mapping = pci_map_single(tp->pdev, skb->data, len, PCI_DMA_TODEVICE);
4110
4111         tp->tx_buffers[entry].skb = skb;
4112         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4113
4114         would_hit_hwbug = 0;
4115
4116         if (tg3_4g_overflow_test(mapping, len))
4117                 would_hit_hwbug = 1;
4118
4119         tg3_set_txd(tp, entry, mapping, len, base_flags,
4120                     (skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
4121
4122         entry = NEXT_TX(entry);
4123
4124         /* Now loop through additional data fragments, and queue them. */
4125         if (skb_shinfo(skb)->nr_frags > 0) {
4126                 unsigned int i, last;
4127
4128                 last = skb_shinfo(skb)->nr_frags - 1;
4129                 for (i = 0; i <= last; i++) {
4130                         skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
4131
4132                         len = frag->size;
4133                         mapping = pci_map_page(tp->pdev,
4134                                                frag->page,
4135                                                frag->page_offset,
4136                                                len, PCI_DMA_TODEVICE);
4137
4138                         tp->tx_buffers[entry].skb = NULL;
4139                         pci_unmap_addr_set(&tp->tx_buffers[entry], mapping, mapping);
4140
4141                         if (tg3_4g_overflow_test(mapping, len))
4142                                 would_hit_hwbug = 1;
4143
4144                         if (tg3_40bit_overflow_test(tp, mapping, len))
4145                                 would_hit_hwbug = 1;
4146
4147                         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
4148                                 tg3_set_txd(tp, entry, mapping, len,
4149                                             base_flags, (i == last)|(mss << 1));
4150                         else
4151                                 tg3_set_txd(tp, entry, mapping, len,
4152                                             base_flags, (i == last));
4153
4154                         entry = NEXT_TX(entry);
4155                 }
4156         }
4157
4158         if (would_hit_hwbug) {
4159                 u32 last_plus_one = entry;
4160                 u32 start;
4161
4162                 start = entry - 1 - skb_shinfo(skb)->nr_frags;
4163                 start &= (TG3_TX_RING_SIZE - 1);
4164
4165                 /* If the workaround fails due to memory/mapping
4166                  * failure, silently drop this packet.
4167                  */
4168                 if (tigon3_dma_hwbug_workaround(tp, skb, last_plus_one,
4169                                                 &start, base_flags, mss))
4170                         goto out_unlock;
4171
4172                 entry = start;
4173         }
4174
4175         /* Packets are ready, update Tx producer idx local and on card. */
4176         tw32_tx_mbox((MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW), entry);
4177
4178         tp->tx_prod = entry;
4179         if (unlikely(tg3_tx_avail(tp) <= (MAX_SKB_FRAGS + 1))) {
4180                 netif_stop_queue(dev);
4181                 if (tg3_tx_avail(tp) > TG3_TX_WAKEUP_THRESH(tp))
4182                         netif_wake_queue(tp->dev);
4183         }
4184
4185 out_unlock:
4186         mmiowb();
4187
4188         dev->trans_start = jiffies;
4189
4190         return NETDEV_TX_OK;
4191 }
4192
4193 static inline void tg3_set_mtu(struct net_device *dev, struct tg3 *tp,
4194                                int new_mtu)
4195 {
4196         dev->mtu = new_mtu;
4197
4198         if (new_mtu > ETH_DATA_LEN) {
4199                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4200                         tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
4201                         ethtool_op_set_tso(dev, 0);
4202                 }
4203                 else
4204                         tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
4205         } else {
4206                 if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
4207                         tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
4208                 tp->tg3_flags &= ~TG3_FLAG_JUMBO_RING_ENABLE;
4209         }
4210 }
4211
4212 static int tg3_change_mtu(struct net_device *dev, int new_mtu)
4213 {
4214         struct tg3 *tp = netdev_priv(dev);
4215         int err;
4216
4217         if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
4218                 return -EINVAL;
4219
4220         if (!netif_running(dev)) {
4221                 /* We'll just catch it later when the
4222                  * device is up'd.
4223                  */
4224                 tg3_set_mtu(dev, tp, new_mtu);
4225                 return 0;
4226         }
4227
4228         tg3_netif_stop(tp);
4229
4230         tg3_full_lock(tp, 1);
4231
4232         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
4233
4234         tg3_set_mtu(dev, tp, new_mtu);
4235
4236         err = tg3_restart_hw(tp, 0);
4237
4238         if (!err)
4239                 tg3_netif_start(tp);
4240
4241         tg3_full_unlock(tp);
4242
4243         return err;
4244 }
4245
4246 /* Free up pending packets in all rx/tx rings.
4247  *
4248  * The chip has been shut down and the driver detached from
4249  * the networking, so no interrupts or new tx packets will
4250  * end up in the driver.  tp->{tx,}lock is not held and we are not
4251  * in an interrupt context and thus may sleep.
4252  */
4253 static void tg3_free_rings(struct tg3 *tp)
4254 {
4255         struct ring_info *rxp;
4256         int i;
4257
4258         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4259                 rxp = &tp->rx_std_buffers[i];
4260
4261                 if (rxp->skb == NULL)
4262                         continue;
4263                 pci_unmap_single(tp->pdev,
4264                                  pci_unmap_addr(rxp, mapping),
4265                                  tp->rx_pkt_buf_sz - tp->rx_offset,
4266                                  PCI_DMA_FROMDEVICE);
4267                 dev_kfree_skb_any(rxp->skb);
4268                 rxp->skb = NULL;
4269         }
4270
4271         for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4272                 rxp = &tp->rx_jumbo_buffers[i];
4273
4274                 if (rxp->skb == NULL)
4275                         continue;
4276                 pci_unmap_single(tp->pdev,
4277                                  pci_unmap_addr(rxp, mapping),
4278                                  RX_JUMBO_PKT_BUF_SZ - tp->rx_offset,
4279                                  PCI_DMA_FROMDEVICE);
4280                 dev_kfree_skb_any(rxp->skb);
4281                 rxp->skb = NULL;
4282         }
4283
4284         for (i = 0; i < TG3_TX_RING_SIZE; ) {
4285                 struct tx_ring_info *txp;
4286                 struct sk_buff *skb;
4287                 int j;
4288
4289                 txp = &tp->tx_buffers[i];
4290                 skb = txp->skb;
4291
4292                 if (skb == NULL) {
4293                         i++;
4294                         continue;
4295                 }
4296
4297                 pci_unmap_single(tp->pdev,
4298                                  pci_unmap_addr(txp, mapping),
4299                                  skb_headlen(skb),
4300                                  PCI_DMA_TODEVICE);
4301                 txp->skb = NULL;
4302
4303                 i++;
4304
4305                 for (j = 0; j < skb_shinfo(skb)->nr_frags; j++) {
4306                         txp = &tp->tx_buffers[i & (TG3_TX_RING_SIZE - 1)];
4307                         pci_unmap_page(tp->pdev,
4308                                        pci_unmap_addr(txp, mapping),
4309                                        skb_shinfo(skb)->frags[j].size,
4310                                        PCI_DMA_TODEVICE);
4311                         i++;
4312                 }
4313
4314                 dev_kfree_skb_any(skb);
4315         }
4316 }
4317
4318 /* Initialize tx/rx rings for packet processing.
4319  *
4320  * The chip has been shut down and the driver detached from
4321  * the networking, so no interrupts or new tx packets will
4322  * end up in the driver.  tp->{tx,}lock are held and thus
4323  * we may not sleep.
4324  */
4325 static int tg3_init_rings(struct tg3 *tp)
4326 {
4327         u32 i;
4328
4329         /* Free up all the SKBs. */
4330         tg3_free_rings(tp);
4331
4332         /* Zero out all descriptors. */
4333         memset(tp->rx_std, 0, TG3_RX_RING_BYTES);
4334         memset(tp->rx_jumbo, 0, TG3_RX_JUMBO_RING_BYTES);
4335         memset(tp->rx_rcb, 0, TG3_RX_RCB_RING_BYTES(tp));
4336         memset(tp->tx_ring, 0, TG3_TX_RING_BYTES);
4337
4338         tp->rx_pkt_buf_sz = RX_PKT_BUF_SZ;
4339         if ((tp->tg3_flags2 & TG3_FLG2_5780_CLASS) &&
4340             (tp->dev->mtu > ETH_DATA_LEN))
4341                 tp->rx_pkt_buf_sz = RX_JUMBO_PKT_BUF_SZ;
4342
4343         /* Initialize invariants of the rings, we only set this
4344          * stuff once.  This works because the card does not
4345          * write into the rx buffer posting rings.
4346          */
4347         for (i = 0; i < TG3_RX_RING_SIZE; i++) {
4348                 struct tg3_rx_buffer_desc *rxd;
4349
4350                 rxd = &tp->rx_std[i];
4351                 rxd->idx_len = (tp->rx_pkt_buf_sz - tp->rx_offset - 64)
4352                         << RXD_LEN_SHIFT;
4353                 rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT);
4354                 rxd->opaque = (RXD_OPAQUE_RING_STD |
4355                                (i << RXD_OPAQUE_INDEX_SHIFT));
4356         }
4357
4358         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4359                 for (i = 0; i < TG3_RX_JUMBO_RING_SIZE; i++) {
4360                         struct tg3_rx_buffer_desc *rxd;
4361
4362                         rxd = &tp->rx_jumbo[i];
4363                         rxd->idx_len = (RX_JUMBO_PKT_BUF_SZ - tp->rx_offset - 64)
4364                                 << RXD_LEN_SHIFT;
4365                         rxd->type_flags = (RXD_FLAG_END << RXD_FLAGS_SHIFT) |
4366                                 RXD_FLAG_JUMBO;
4367                         rxd->opaque = (RXD_OPAQUE_RING_JUMBO |
4368                                (i << RXD_OPAQUE_INDEX_SHIFT));
4369                 }
4370         }
4371
4372         /* Now allocate fresh SKBs for each rx ring. */
4373         for (i = 0; i < tp->rx_pending; i++) {
4374                 if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_STD, -1, i) < 0) {
4375                         printk(KERN_WARNING PFX
4376                                "%s: Using a smaller RX standard ring, "
4377                                "only %d out of %d buffers were allocated "
4378                                "successfully.\n",
4379                                tp->dev->name, i, tp->rx_pending);
4380                         if (i == 0)
4381                                 return -ENOMEM;
4382                         tp->rx_pending = i;
4383                         break;
4384                 }
4385         }
4386
4387         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
4388                 for (i = 0; i < tp->rx_jumbo_pending; i++) {
4389                         if (tg3_alloc_rx_skb(tp, RXD_OPAQUE_RING_JUMBO,
4390                                              -1, i) < 0) {
4391                                 printk(KERN_WARNING PFX
4392                                        "%s: Using a smaller RX jumbo ring, "
4393                                        "only %d out of %d buffers were "
4394                                        "allocated successfully.\n",
4395                                        tp->dev->name, i, tp->rx_jumbo_pending);
4396                                 if (i == 0) {
4397                                         tg3_free_rings(tp);
4398                                         return -ENOMEM;
4399                                 }
4400                                 tp->rx_jumbo_pending = i;
4401                                 break;
4402                         }
4403                 }
4404         }
4405         return 0;
4406 }
4407
4408 /*
4409  * Must not be invoked with interrupt sources disabled and
4410  * the hardware shutdown down.
4411  */
4412 static void tg3_free_consistent(struct tg3 *tp)
4413 {
4414         kfree(tp->rx_std_buffers);
4415         tp->rx_std_buffers = NULL;
4416         if (tp->rx_std) {
4417                 pci_free_consistent(tp->pdev, TG3_RX_RING_BYTES,
4418                                     tp->rx_std, tp->rx_std_mapping);
4419                 tp->rx_std = NULL;
4420         }
4421         if (tp->rx_jumbo) {
4422                 pci_free_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4423                                     tp->rx_jumbo, tp->rx_jumbo_mapping);
4424                 tp->rx_jumbo = NULL;
4425         }
4426         if (tp->rx_rcb) {
4427                 pci_free_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4428                                     tp->rx_rcb, tp->rx_rcb_mapping);
4429                 tp->rx_rcb = NULL;
4430         }
4431         if (tp->tx_ring) {
4432                 pci_free_consistent(tp->pdev, TG3_TX_RING_BYTES,
4433                         tp->tx_ring, tp->tx_desc_mapping);
4434                 tp->tx_ring = NULL;
4435         }
4436         if (tp->hw_status) {
4437                 pci_free_consistent(tp->pdev, TG3_HW_STATUS_SIZE,
4438                                     tp->hw_status, tp->status_mapping);
4439                 tp->hw_status = NULL;
4440         }
4441         if (tp->hw_stats) {
4442                 pci_free_consistent(tp->pdev, sizeof(struct tg3_hw_stats),
4443                                     tp->hw_stats, tp->stats_mapping);
4444                 tp->hw_stats = NULL;
4445         }
4446 }
4447
4448 /*
4449  * Must not be invoked with interrupt sources disabled and
4450  * the hardware shutdown down.  Can sleep.
4451  */
4452 static int tg3_alloc_consistent(struct tg3 *tp)
4453 {
4454         tp->rx_std_buffers = kzalloc((sizeof(struct ring_info) *
4455                                       (TG3_RX_RING_SIZE +
4456                                        TG3_RX_JUMBO_RING_SIZE)) +
4457                                      (sizeof(struct tx_ring_info) *
4458                                       TG3_TX_RING_SIZE),
4459                                      GFP_KERNEL);
4460         if (!tp->rx_std_buffers)
4461                 return -ENOMEM;
4462
4463         tp->rx_jumbo_buffers = &tp->rx_std_buffers[TG3_RX_RING_SIZE];
4464         tp->tx_buffers = (struct tx_ring_info *)
4465                 &tp->rx_jumbo_buffers[TG3_RX_JUMBO_RING_SIZE];
4466
4467         tp->rx_std = pci_alloc_consistent(tp->pdev, TG3_RX_RING_BYTES,
4468                                           &tp->rx_std_mapping);
4469         if (!tp->rx_std)
4470                 goto err_out;
4471
4472         tp->rx_jumbo = pci_alloc_consistent(tp->pdev, TG3_RX_JUMBO_RING_BYTES,
4473                                             &tp->rx_jumbo_mapping);
4474
4475         if (!tp->rx_jumbo)
4476                 goto err_out;
4477
4478         tp->rx_rcb = pci_alloc_consistent(tp->pdev, TG3_RX_RCB_RING_BYTES(tp),
4479                                           &tp->rx_rcb_mapping);
4480         if (!tp->rx_rcb)
4481                 goto err_out;
4482
4483         tp->tx_ring = pci_alloc_consistent(tp->pdev, TG3_TX_RING_BYTES,
4484                                            &tp->tx_desc_mapping);
4485         if (!tp->tx_ring)
4486                 goto err_out;
4487
4488         tp->hw_status = pci_alloc_consistent(tp->pdev,
4489                                              TG3_HW_STATUS_SIZE,
4490                                              &tp->status_mapping);
4491         if (!tp->hw_status)
4492                 goto err_out;
4493
4494         tp->hw_stats = pci_alloc_consistent(tp->pdev,
4495                                             sizeof(struct tg3_hw_stats),
4496                                             &tp->stats_mapping);
4497         if (!tp->hw_stats)
4498                 goto err_out;
4499
4500         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4501         memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4502
4503         return 0;
4504
4505 err_out:
4506         tg3_free_consistent(tp);
4507         return -ENOMEM;
4508 }
4509
4510 #define MAX_WAIT_CNT 1000
4511
4512 /* To stop a block, clear the enable bit and poll till it
4513  * clears.  tp->lock is held.
4514  */
4515 static int tg3_stop_block(struct tg3 *tp, unsigned long ofs, u32 enable_bit, int silent)
4516 {
4517         unsigned int i;
4518         u32 val;
4519
4520         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
4521                 switch (ofs) {
4522                 case RCVLSC_MODE:
4523                 case DMAC_MODE:
4524                 case MBFREE_MODE:
4525                 case BUFMGR_MODE:
4526                 case MEMARB_MODE:
4527                         /* We can't enable/disable these bits of the
4528                          * 5705/5750, just say success.
4529                          */
4530                         return 0;
4531
4532                 default:
4533                         break;
4534                 };
4535         }
4536
4537         val = tr32(ofs);
4538         val &= ~enable_bit;
4539         tw32_f(ofs, val);
4540
4541         for (i = 0; i < MAX_WAIT_CNT; i++) {
4542                 udelay(100);
4543                 val = tr32(ofs);
4544                 if ((val & enable_bit) == 0)
4545                         break;
4546         }
4547
4548         if (i == MAX_WAIT_CNT && !silent) {
4549                 printk(KERN_ERR PFX "tg3_stop_block timed out, "
4550                        "ofs=%lx enable_bit=%x\n",
4551                        ofs, enable_bit);
4552                 return -ENODEV;
4553         }
4554
4555         return 0;
4556 }
4557
4558 /* tp->lock is held. */
4559 static int tg3_abort_hw(struct tg3 *tp, int silent)
4560 {
4561         int i, err;
4562
4563         tg3_disable_ints(tp);
4564
4565         tp->rx_mode &= ~RX_MODE_ENABLE;
4566         tw32_f(MAC_RX_MODE, tp->rx_mode);
4567         udelay(10);
4568
4569         err  = tg3_stop_block(tp, RCVBDI_MODE, RCVBDI_MODE_ENABLE, silent);
4570         err |= tg3_stop_block(tp, RCVLPC_MODE, RCVLPC_MODE_ENABLE, silent);
4571         err |= tg3_stop_block(tp, RCVLSC_MODE, RCVLSC_MODE_ENABLE, silent);
4572         err |= tg3_stop_block(tp, RCVDBDI_MODE, RCVDBDI_MODE_ENABLE, silent);
4573         err |= tg3_stop_block(tp, RCVDCC_MODE, RCVDCC_MODE_ENABLE, silent);
4574         err |= tg3_stop_block(tp, RCVCC_MODE, RCVCC_MODE_ENABLE, silent);
4575
4576         err |= tg3_stop_block(tp, SNDBDS_MODE, SNDBDS_MODE_ENABLE, silent);
4577         err |= tg3_stop_block(tp, SNDBDI_MODE, SNDBDI_MODE_ENABLE, silent);
4578         err |= tg3_stop_block(tp, SNDDATAI_MODE, SNDDATAI_MODE_ENABLE, silent);
4579         err |= tg3_stop_block(tp, RDMAC_MODE, RDMAC_MODE_ENABLE, silent);
4580         err |= tg3_stop_block(tp, SNDDATAC_MODE, SNDDATAC_MODE_ENABLE, silent);
4581         err |= tg3_stop_block(tp, DMAC_MODE, DMAC_MODE_ENABLE, silent);
4582         err |= tg3_stop_block(tp, SNDBDC_MODE, SNDBDC_MODE_ENABLE, silent);
4583
4584         tp->mac_mode &= ~MAC_MODE_TDE_ENABLE;
4585         tw32_f(MAC_MODE, tp->mac_mode);
4586         udelay(40);
4587
4588         tp->tx_mode &= ~TX_MODE_ENABLE;
4589         tw32_f(MAC_TX_MODE, tp->tx_mode);
4590
4591         for (i = 0; i < MAX_WAIT_CNT; i++) {
4592                 udelay(100);
4593                 if (!(tr32(MAC_TX_MODE) & TX_MODE_ENABLE))
4594                         break;
4595         }
4596         if (i >= MAX_WAIT_CNT) {
4597                 printk(KERN_ERR PFX "tg3_abort_hw timed out for %s, "
4598                        "TX_MODE_ENABLE will not clear MAC_TX_MODE=%08x\n",
4599                        tp->dev->name, tr32(MAC_TX_MODE));
4600                 err |= -ENODEV;
4601         }
4602
4603         err |= tg3_stop_block(tp, HOSTCC_MODE, HOSTCC_MODE_ENABLE, silent);
4604         err |= tg3_stop_block(tp, WDMAC_MODE, WDMAC_MODE_ENABLE, silent);
4605         err |= tg3_stop_block(tp, MBFREE_MODE, MBFREE_MODE_ENABLE, silent);
4606
4607         tw32(FTQ_RESET, 0xffffffff);
4608         tw32(FTQ_RESET, 0x00000000);
4609
4610         err |= tg3_stop_block(tp, BUFMGR_MODE, BUFMGR_MODE_ENABLE, silent);
4611         err |= tg3_stop_block(tp, MEMARB_MODE, MEMARB_MODE_ENABLE, silent);
4612
4613         if (tp->hw_status)
4614                 memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
4615         if (tp->hw_stats)
4616                 memset(tp->hw_stats, 0, sizeof(struct tg3_hw_stats));
4617
4618         return err;
4619 }
4620
4621 /* tp->lock is held. */
4622 static int tg3_nvram_lock(struct tg3 *tp)
4623 {
4624         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4625                 int i;
4626
4627                 if (tp->nvram_lock_cnt == 0) {
4628                         tw32(NVRAM_SWARB, SWARB_REQ_SET1);
4629                         for (i = 0; i < 8000; i++) {
4630                                 if (tr32(NVRAM_SWARB) & SWARB_GNT1)
4631                                         break;
4632                                 udelay(20);
4633                         }
4634                         if (i == 8000) {
4635                                 tw32(NVRAM_SWARB, SWARB_REQ_CLR1);
4636                                 return -ENODEV;
4637                         }
4638                 }
4639                 tp->nvram_lock_cnt++;
4640         }
4641         return 0;
4642 }
4643
4644 /* tp->lock is held. */
4645 static void tg3_nvram_unlock(struct tg3 *tp)
4646 {
4647         if (tp->tg3_flags & TG3_FLAG_NVRAM) {
4648                 if (tp->nvram_lock_cnt > 0)
4649                         tp->nvram_lock_cnt--;
4650                 if (tp->nvram_lock_cnt == 0)
4651                         tw32_f(NVRAM_SWARB, SWARB_REQ_CLR1);
4652         }
4653 }
4654
4655 /* tp->lock is held. */
4656 static void tg3_enable_nvram_access(struct tg3 *tp)
4657 {
4658         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4659             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4660                 u32 nvaccess = tr32(NVRAM_ACCESS);
4661
4662                 tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
4663         }
4664 }
4665
4666 /* tp->lock is held. */
4667 static void tg3_disable_nvram_access(struct tg3 *tp)
4668 {
4669         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
4670             !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM)) {
4671                 u32 nvaccess = tr32(NVRAM_ACCESS);
4672
4673                 tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
4674         }
4675 }
4676
4677 /* tp->lock is held. */
4678 static void tg3_write_sig_pre_reset(struct tg3 *tp, int kind)
4679 {
4680         tg3_write_mem(tp, NIC_SRAM_FIRMWARE_MBOX,
4681                       NIC_SRAM_FIRMWARE_MBOX_MAGIC1);
4682
4683         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4684                 switch (kind) {
4685                 case RESET_KIND_INIT:
4686                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4687                                       DRV_STATE_START);
4688                         break;
4689
4690                 case RESET_KIND_SHUTDOWN:
4691                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4692                                       DRV_STATE_UNLOAD);
4693                         break;
4694
4695                 case RESET_KIND_SUSPEND:
4696                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4697                                       DRV_STATE_SUSPEND);
4698                         break;
4699
4700                 default:
4701                         break;
4702                 };
4703         }
4704 }
4705
4706 /* tp->lock is held. */
4707 static void tg3_write_sig_post_reset(struct tg3 *tp, int kind)
4708 {
4709         if (tp->tg3_flags2 & TG3_FLG2_ASF_NEW_HANDSHAKE) {
4710                 switch (kind) {
4711                 case RESET_KIND_INIT:
4712                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4713                                       DRV_STATE_START_DONE);
4714                         break;
4715
4716                 case RESET_KIND_SHUTDOWN:
4717                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4718                                       DRV_STATE_UNLOAD_DONE);
4719                         break;
4720
4721                 default:
4722                         break;
4723                 };
4724         }
4725 }
4726
4727 /* tp->lock is held. */
4728 static void tg3_write_sig_legacy(struct tg3 *tp, int kind)
4729 {
4730         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4731                 switch (kind) {
4732                 case RESET_KIND_INIT:
4733                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4734                                       DRV_STATE_START);
4735                         break;
4736
4737                 case RESET_KIND_SHUTDOWN:
4738                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4739                                       DRV_STATE_UNLOAD);
4740                         break;
4741
4742                 case RESET_KIND_SUSPEND:
4743                         tg3_write_mem(tp, NIC_SRAM_FW_DRV_STATE_MBOX,
4744                                       DRV_STATE_SUSPEND);
4745                         break;
4746
4747                 default:
4748                         break;
4749                 };
4750         }
4751 }
4752
4753 static int tg3_poll_fw(struct tg3 *tp)
4754 {
4755         int i;
4756         u32 val;
4757
4758         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4759                 /* Wait up to 20ms for init done. */
4760                 for (i = 0; i < 200; i++) {
4761                         if (tr32(VCPU_STATUS) & VCPU_STATUS_INIT_DONE)
4762                                 return 0;
4763                         udelay(100);
4764                 }
4765                 return -ENODEV;
4766         }
4767
4768         /* Wait for firmware initialization to complete. */
4769         for (i = 0; i < 100000; i++) {
4770                 tg3_read_mem(tp, NIC_SRAM_FIRMWARE_MBOX, &val);
4771                 if (val == ~NIC_SRAM_FIRMWARE_MBOX_MAGIC1)
4772                         break;
4773                 udelay(10);
4774         }
4775
4776         /* Chip might not be fitted with firmware.  Some Sun onboard
4777          * parts are configured like that.  So don't signal the timeout
4778          * of the above loop as an error, but do report the lack of
4779          * running firmware once.
4780          */
4781         if (i >= 100000 &&
4782             !(tp->tg3_flags2 & TG3_FLG2_NO_FWARE_REPORTED)) {
4783                 tp->tg3_flags2 |= TG3_FLG2_NO_FWARE_REPORTED;
4784
4785                 printk(KERN_INFO PFX "%s: No firmware running.\n",
4786                        tp->dev->name);
4787         }
4788
4789         return 0;
4790 }
4791
4792 static void tg3_stop_fw(struct tg3 *);
4793
4794 /* tp->lock is held. */
4795 static int tg3_chip_reset(struct tg3 *tp)
4796 {
4797         u32 val;
4798         void (*write_op)(struct tg3 *, u32, u32);
4799         int err;
4800
4801         tg3_nvram_lock(tp);
4802
4803         /* No matching tg3_nvram_unlock() after this because
4804          * chip reset below will undo the nvram lock.
4805          */
4806         tp->nvram_lock_cnt = 0;
4807
4808         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
4809             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
4810             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
4811                 tw32(GRC_FASTBOOT_PC, 0);
4812
4813         /*
4814          * We must avoid the readl() that normally takes place.
4815          * It locks machines, causes machine checks, and other
4816          * fun things.  So, temporarily disable the 5701
4817          * hardware workaround, while we do the reset.
4818          */
4819         write_op = tp->write32;
4820         if (write_op == tg3_write_flush_reg32)
4821                 tp->write32 = tg3_write32;
4822
4823         /* do the reset */
4824         val = GRC_MISC_CFG_CORECLK_RESET;
4825
4826         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4827                 if (tr32(0x7e2c) == 0x60) {
4828                         tw32(0x7e2c, 0x20);
4829                 }
4830                 if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4831                         tw32(GRC_MISC_CFG, (1 << 29));
4832                         val |= (1 << 29);
4833                 }
4834         }
4835
4836         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
4837                 tw32(VCPU_STATUS, tr32(VCPU_STATUS) | VCPU_STATUS_DRV_RESET);
4838                 tw32(GRC_VCPU_EXT_CTRL,
4839                      tr32(GRC_VCPU_EXT_CTRL) & ~GRC_VCPU_EXT_CTRL_HALT_CPU);
4840         }
4841
4842         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
4843                 val |= GRC_MISC_CFG_KEEP_GPHY_POWER;
4844         tw32(GRC_MISC_CFG, val);
4845
4846         /* restore 5701 hardware bug workaround write method */
4847         tp->write32 = write_op;
4848
4849         /* Unfortunately, we have to delay before the PCI read back.
4850          * Some 575X chips even will not respond to a PCI cfg access
4851          * when the reset command is given to the chip.
4852          *
4853          * How do these hardware designers expect things to work
4854          * properly if the PCI write is posted for a long period
4855          * of time?  It is always necessary to have some method by
4856          * which a register read back can occur to push the write
4857          * out which does the reset.
4858          *
4859          * For most tg3 variants the trick below was working.
4860          * Ho hum...
4861          */
4862         udelay(120);
4863
4864         /* Flush PCI posted writes.  The normal MMIO registers
4865          * are inaccessible at this time so this is the only
4866          * way to make this reliably (actually, this is no longer
4867          * the case, see above).  I tried to use indirect
4868          * register read/write but this upset some 5701 variants.
4869          */
4870         pci_read_config_dword(tp->pdev, PCI_COMMAND, &val);
4871
4872         udelay(120);
4873
4874         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
4875                 if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A0) {
4876                         int i;
4877                         u32 cfg_val;
4878
4879                         /* Wait for link training to complete.  */
4880                         for (i = 0; i < 5000; i++)
4881                                 udelay(100);
4882
4883                         pci_read_config_dword(tp->pdev, 0xc4, &cfg_val);
4884                         pci_write_config_dword(tp->pdev, 0xc4,
4885                                                cfg_val | (1 << 15));
4886                 }
4887                 /* Set PCIE max payload size and clear error status.  */
4888                 pci_write_config_dword(tp->pdev, 0xd8, 0xf5000);
4889         }
4890
4891         /* Re-enable indirect register accesses. */
4892         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
4893                                tp->misc_host_ctrl);
4894
4895         /* Set MAX PCI retry to zero. */
4896         val = (PCISTATE_ROM_ENABLE | PCISTATE_ROM_RETRY_ENABLE);
4897         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
4898             (tp->tg3_flags & TG3_FLAG_PCIX_MODE))
4899                 val |= PCISTATE_RETRY_SAME_DMA;
4900         pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, val);
4901
4902         pci_restore_state(tp->pdev);
4903
4904         /* Make sure PCI-X relaxed ordering bit is clear. */
4905         pci_read_config_dword(tp->pdev, TG3PCI_X_CAPS, &val);
4906         val &= ~PCIX_CAPS_RELAXED_ORDERING;
4907         pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);
4908
4909         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS) {
4910                 u32 val;
4911
4912                 /* Chip reset on 5780 will reset MSI enable bit,
4913                  * so need to restore it.
4914                  */
4915                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
4916                         u16 ctrl;
4917
4918                         pci_read_config_word(tp->pdev,
4919                                              tp->msi_cap + PCI_MSI_FLAGS,
4920                                              &ctrl);
4921                         pci_write_config_word(tp->pdev,
4922                                               tp->msi_cap + PCI_MSI_FLAGS,
4923                                               ctrl | PCI_MSI_FLAGS_ENABLE);
4924                         val = tr32(MSGINT_MODE);
4925                         tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);
4926                 }
4927
4928                 val = tr32(MEMARB_MODE);
4929                 tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
4930
4931         } else
4932                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
4933
4934         if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
4935                 tg3_stop_fw(tp);
4936                 tw32(0x5000, 0x400);
4937         }
4938
4939         tw32(GRC_MODE, tp->grc_mode);
4940
4941         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0) {
4942                 u32 val = tr32(0xc4);
4943
4944                 tw32(0xc4, val | (1 << 15));
4945         }
4946
4947         if ((tp->nic_sram_data_cfg & NIC_SRAM_DATA_CFG_MINI_PCI) != 0 &&
4948             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
4949                 tp->pci_clock_ctrl |= CLOCK_CTRL_CLKRUN_OENABLE;
4950                 if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A0)
4951                         tp->pci_clock_ctrl |= CLOCK_CTRL_FORCE_CLKRUN;
4952                 tw32(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
4953         }
4954
4955         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
4956                 tp->mac_mode = MAC_MODE_PORT_MODE_TBI;
4957                 tw32_f(MAC_MODE, tp->mac_mode);
4958         } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
4959                 tp->mac_mode = MAC_MODE_PORT_MODE_GMII;
4960                 tw32_f(MAC_MODE, tp->mac_mode);
4961         } else
4962                 tw32_f(MAC_MODE, 0);
4963         udelay(40);
4964
4965         err = tg3_poll_fw(tp);
4966         if (err)
4967                 return err;
4968
4969         if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
4970             tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
4971                 u32 val = tr32(0x7c00);
4972
4973                 tw32(0x7c00, val | (1 << 25));
4974         }
4975
4976         /* Reprobe ASF enable state.  */
4977         tp->tg3_flags &= ~TG3_FLAG_ENABLE_ASF;
4978         tp->tg3_flags2 &= ~TG3_FLG2_ASF_NEW_HANDSHAKE;
4979         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
4980         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
4981                 u32 nic_cfg;
4982
4983                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
4984                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
4985                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
4986                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
4987                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
4988                 }
4989         }
4990
4991         return 0;
4992 }
4993
4994 /* tp->lock is held. */
4995 static void tg3_stop_fw(struct tg3 *tp)
4996 {
4997         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
4998                 u32 val;
4999                 int i;
5000
5001                 tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_PAUSE_FW);
5002                 val = tr32(GRC_RX_CPU_EVENT);
5003                 val |= (1 << 14);
5004                 tw32(GRC_RX_CPU_EVENT, val);
5005
5006                 /* Wait for RX cpu to ACK the event.  */
5007                 for (i = 0; i < 100; i++) {
5008                         if (!(tr32(GRC_RX_CPU_EVENT) & (1 << 14)))
5009                                 break;
5010                         udelay(1);
5011                 }
5012         }
5013 }
5014
5015 /* tp->lock is held. */
5016 static int tg3_halt(struct tg3 *tp, int kind, int silent)
5017 {
5018         int err;
5019
5020         tg3_stop_fw(tp);
5021
5022         tg3_write_sig_pre_reset(tp, kind);
5023
5024         tg3_abort_hw(tp, silent);
5025         err = tg3_chip_reset(tp);
5026
5027         tg3_write_sig_legacy(tp, kind);
5028         tg3_write_sig_post_reset(tp, kind);
5029
5030         if (err)
5031                 return err;
5032
5033         return 0;
5034 }
5035
5036 #define TG3_FW_RELEASE_MAJOR    0x0
5037 #define TG3_FW_RELASE_MINOR     0x0
5038 #define TG3_FW_RELEASE_FIX      0x0
5039 #define TG3_FW_START_ADDR       0x08000000
5040 #define TG3_FW_TEXT_ADDR        0x08000000
5041 #define TG3_FW_TEXT_LEN         0x9c0
5042 #define TG3_FW_RODATA_ADDR      0x080009c0
5043 #define TG3_FW_RODATA_LEN       0x60
5044 #define TG3_FW_DATA_ADDR        0x08000a40
5045 #define TG3_FW_DATA_LEN         0x20
5046 #define TG3_FW_SBSS_ADDR        0x08000a60
5047 #define TG3_FW_SBSS_LEN         0xc
5048 #define TG3_FW_BSS_ADDR         0x08000a70
5049 #define TG3_FW_BSS_LEN          0x10
5050
5051 static const u32 tg3FwText[(TG3_FW_TEXT_LEN / sizeof(u32)) + 1] = {
5052         0x00000000, 0x10000003, 0x00000000, 0x0000000d, 0x0000000d, 0x3c1d0800,
5053         0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100000, 0x0e000018, 0x00000000,
5054         0x0000000d, 0x3c1d0800, 0x37bd3ffc, 0x03a0f021, 0x3c100800, 0x26100034,
5055         0x0e00021c, 0x00000000, 0x0000000d, 0x00000000, 0x00000000, 0x00000000,
5056         0x27bdffe0, 0x3c1cc000, 0xafbf0018, 0xaf80680c, 0x0e00004c, 0x241b2105,
5057         0x97850000, 0x97870002, 0x9782002c, 0x9783002e, 0x3c040800, 0x248409c0,
5058         0xafa00014, 0x00021400, 0x00621825, 0x00052c00, 0xafa30010, 0x8f860010,
5059         0x00e52825, 0x0e000060, 0x24070102, 0x3c02ac00, 0x34420100, 0x3c03ac01,
5060         0x34630100, 0xaf820490, 0x3c02ffff, 0xaf820494, 0xaf830498, 0xaf82049c,
5061         0x24020001, 0xaf825ce0, 0x0e00003f, 0xaf825d00, 0x0e000140, 0x00000000,
5062         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x2402ffff, 0xaf825404, 0x8f835400,
5063         0x34630400, 0xaf835400, 0xaf825404, 0x3c020800, 0x24420034, 0xaf82541c,
5064         0x03e00008, 0xaf805400, 0x00000000, 0x00000000, 0x3c020800, 0x34423000,
5065         0x3c030800, 0x34633000, 0x3c040800, 0x348437ff, 0x3c010800, 0xac220a64,
5066         0x24020040, 0x3c010800, 0xac220a68, 0x3c010800, 0xac200a60, 0xac600000,
5067         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5068         0x00804821, 0x8faa0010, 0x3c020800, 0x8c420a60, 0x3c040800, 0x8c840a68,
5069         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010800, 0xac230a60, 0x14400003,
5070         0x00004021, 0x3c010800, 0xac200a60, 0x3c020800, 0x8c420a60, 0x3c030800,
5071         0x8c630a64, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5072         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020800, 0x8c420a60,
5073         0x3c030800, 0x8c630a64, 0x8f84680c, 0x00021140, 0x00431021, 0xac440008,
5074         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5075         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5076         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5077         0, 0, 0, 0, 0, 0,
5078         0x02000008, 0x00000000, 0x0a0001e3, 0x3c0a0001, 0x0a0001e3, 0x3c0a0002,
5079         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5080         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5081         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5082         0x0a0001e3, 0x3c0a0007, 0x0a0001e3, 0x3c0a0008, 0x0a0001e3, 0x3c0a0009,
5083         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000b,
5084         0x0a0001e3, 0x3c0a000c, 0x0a0001e3, 0x3c0a000d, 0x0a0001e3, 0x00000000,
5085         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a000e, 0x0a0001e3, 0x00000000,
5086         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5087         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000, 0x0a0001e3, 0x00000000,
5088         0x0a0001e3, 0x00000000, 0x0a0001e3, 0x3c0a0013, 0x0a0001e3, 0x3c0a0014,
5089         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5090         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5091         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5092         0x27bdffe0, 0x00001821, 0x00001021, 0xafbf0018, 0xafb10014, 0xafb00010,
5093         0x3c010800, 0x00220821, 0xac200a70, 0x3c010800, 0x00220821, 0xac200a74,
5094         0x3c010800, 0x00220821, 0xac200a78, 0x24630001, 0x1860fff5, 0x2442000c,
5095         0x24110001, 0x8f906810, 0x32020004, 0x14400005, 0x24040001, 0x3c020800,
5096         0x8c420a78, 0x18400003, 0x00002021, 0x0e000182, 0x00000000, 0x32020001,
5097         0x10400003, 0x00000000, 0x0e000169, 0x00000000, 0x0a000153, 0xaf915028,
5098         0x8fbf0018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020, 0x3c050800,
5099         0x8ca50a70, 0x3c060800, 0x8cc60a80, 0x3c070800, 0x8ce70a78, 0x27bdffe0,
5100         0x3c040800, 0x248409d0, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014,
5101         0x0e00017b, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x24020001,
5102         0x8f836810, 0x00821004, 0x00021027, 0x00621824, 0x03e00008, 0xaf836810,
5103         0x27bdffd8, 0xafbf0024, 0x1080002e, 0xafb00020, 0x8f825cec, 0xafa20018,
5104         0x8f825cec, 0x3c100800, 0x26100a78, 0xafa2001c, 0x34028000, 0xaf825cec,
5105         0x8e020000, 0x18400016, 0x00000000, 0x3c020800, 0x94420a74, 0x8fa3001c,
5106         0x000221c0, 0xac830004, 0x8fa2001c, 0x3c010800, 0x0e000201, 0xac220a74,
5107         0x10400005, 0x00000000, 0x8e020000, 0x24420001, 0x0a0001df, 0xae020000,
5108         0x3c020800, 0x8c420a70, 0x00021c02, 0x000321c0, 0x0a0001c5, 0xafa2001c,
5109         0x0e000201, 0x00000000, 0x1040001f, 0x00000000, 0x8e020000, 0x8fa3001c,
5110         0x24420001, 0x3c010800, 0xac230a70, 0x3c010800, 0xac230a74, 0x0a0001df,
5111         0xae020000, 0x3c100800, 0x26100a78, 0x8e020000, 0x18400028, 0x00000000,
5112         0x0e000201, 0x00000000, 0x14400024, 0x00000000, 0x8e020000, 0x3c030800,
5113         0x8c630a70, 0x2442ffff, 0xafa3001c, 0x18400006, 0xae020000, 0x00031402,
5114         0x000221c0, 0x8c820004, 0x3c010800, 0xac220a70, 0x97a2001e, 0x2442ff00,
5115         0x2c420300, 0x1440000b, 0x24024000, 0x3c040800, 0x248409dc, 0xafa00010,
5116         0xafa00014, 0x8fa6001c, 0x24050008, 0x0e000060, 0x00003821, 0x0a0001df,
5117         0x00000000, 0xaf825cf8, 0x3c020800, 0x8c420a40, 0x8fa3001c, 0x24420001,
5118         0xaf835cf8, 0x3c010800, 0xac220a40, 0x8fbf0024, 0x8fb00020, 0x03e00008,
5119         0x27bd0028, 0x27bdffe0, 0x3c040800, 0x248409e8, 0x00002821, 0x00003021,
5120         0x00003821, 0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x8fbf0018,
5121         0x03e00008, 0x27bd0020, 0x8f82680c, 0x8f85680c, 0x00021827, 0x0003182b,
5122         0x00031823, 0x00431024, 0x00441021, 0x00a2282b, 0x10a00006, 0x00000000,
5123         0x00401821, 0x8f82680c, 0x0043102b, 0x1440fffd, 0x00000000, 0x03e00008,
5124         0x00000000, 0x3c040800, 0x8c840000, 0x3c030800, 0x8c630a40, 0x0064102b,
5125         0x54400002, 0x00831023, 0x00641023, 0x2c420008, 0x03e00008, 0x38420001,
5126         0x27bdffe0, 0x00802821, 0x3c040800, 0x24840a00, 0x00003021, 0x00003821,
5127         0xafbf0018, 0xafa00010, 0x0e000060, 0xafa00014, 0x0a000216, 0x00000000,
5128         0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000, 0x27bdffe0, 0x3c1cc000,
5129         0xafbf0018, 0x0e00004c, 0xaf80680c, 0x3c040800, 0x24840a10, 0x03802821,
5130         0x00003021, 0x00003821, 0xafa00010, 0x0e000060, 0xafa00014, 0x2402ffff,
5131         0xaf825404, 0x3c0200aa, 0x0e000234, 0xaf825434, 0x8fbf0018, 0x03e00008,
5132         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe8, 0xafb00010,
5133         0x24100001, 0xafbf0014, 0x3c01c003, 0xac200000, 0x8f826810, 0x30422000,
5134         0x10400003, 0x00000000, 0x0e000246, 0x00000000, 0x0a00023a, 0xaf905428,
5135         0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x27bdfff8, 0x8f845d0c,
5136         0x3c0200ff, 0x3c030800, 0x8c630a50, 0x3442fff8, 0x00821024, 0x1043001e,
5137         0x3c0500ff, 0x34a5fff8, 0x3c06c003, 0x3c074000, 0x00851824, 0x8c620010,
5138         0x3c010800, 0xac230a50, 0x30420008, 0x10400005, 0x00871025, 0x8cc20000,
5139         0x24420001, 0xacc20000, 0x00871025, 0xaf825d0c, 0x8fa20000, 0x24420001,
5140         0xafa20000, 0x8fa20000, 0x8fa20000, 0x24420001, 0xafa20000, 0x8fa20000,
5141         0x8f845d0c, 0x3c030800, 0x8c630a50, 0x00851024, 0x1443ffe8, 0x00851824,
5142         0x27bd0008, 0x03e00008, 0x00000000, 0x00000000, 0x00000000
5143 };
5144
5145 static const u32 tg3FwRodata[(TG3_FW_RODATA_LEN / sizeof(u32)) + 1] = {
5146         0x35373031, 0x726c7341, 0x00000000, 0x00000000, 0x53774576, 0x656e7430,
5147         0x00000000, 0x726c7045, 0x76656e74, 0x31000000, 0x556e6b6e, 0x45766e74,
5148         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5149         0x00000000, 0x00000000, 0x4d61696e, 0x43707542, 0x00000000, 0x00000000,
5150         0x00000000
5151 };
5152
5153 #if 0 /* All zeros, don't eat up space with it. */
5154 u32 tg3FwData[(TG3_FW_DATA_LEN / sizeof(u32)) + 1] = {
5155         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5156         0x00000000, 0x00000000, 0x00000000, 0x00000000
5157 };
5158 #endif
5159
5160 #define RX_CPU_SCRATCH_BASE     0x30000
5161 #define RX_CPU_SCRATCH_SIZE     0x04000
5162 #define TX_CPU_SCRATCH_BASE     0x34000
5163 #define TX_CPU_SCRATCH_SIZE     0x04000
5164
5165 /* tp->lock is held. */
5166 static int tg3_halt_cpu(struct tg3 *tp, u32 offset)
5167 {
5168         int i;
5169
5170         BUG_ON(offset == TX_CPU_BASE &&
5171             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS));
5172
5173         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
5174                 u32 val = tr32(GRC_VCPU_EXT_CTRL);
5175
5176                 tw32(GRC_VCPU_EXT_CTRL, val | GRC_VCPU_EXT_CTRL_HALT_CPU);
5177                 return 0;
5178         }
5179         if (offset == RX_CPU_BASE) {
5180                 for (i = 0; i < 10000; i++) {
5181                         tw32(offset + CPU_STATE, 0xffffffff);
5182                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5183                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5184                                 break;
5185                 }
5186
5187                 tw32(offset + CPU_STATE, 0xffffffff);
5188                 tw32_f(offset + CPU_MODE,  CPU_MODE_HALT);
5189                 udelay(10);
5190         } else {
5191                 for (i = 0; i < 10000; i++) {
5192                         tw32(offset + CPU_STATE, 0xffffffff);
5193                         tw32(offset + CPU_MODE,  CPU_MODE_HALT);
5194                         if (tr32(offset + CPU_MODE) & CPU_MODE_HALT)
5195                                 break;
5196                 }
5197         }
5198
5199         if (i >= 10000) {
5200                 printk(KERN_ERR PFX "tg3_reset_cpu timed out for %s, "
5201                        "and %s CPU\n",
5202                        tp->dev->name,
5203                        (offset == RX_CPU_BASE ? "RX" : "TX"));
5204                 return -ENODEV;
5205         }
5206
5207         /* Clear firmware's nvram arbitration. */
5208         if (tp->tg3_flags & TG3_FLAG_NVRAM)
5209                 tw32(NVRAM_SWARB, SWARB_REQ_CLR0);
5210         return 0;
5211 }
5212
5213 struct fw_info {
5214         unsigned int text_base;
5215         unsigned int text_len;
5216         const u32 *text_data;
5217         unsigned int rodata_base;
5218         unsigned int rodata_len;
5219         const u32 *rodata_data;
5220         unsigned int data_base;
5221         unsigned int data_len;
5222         const u32 *data_data;
5223 };
5224
5225 /* tp->lock is held. */
5226 static int tg3_load_firmware_cpu(struct tg3 *tp, u32 cpu_base, u32 cpu_scratch_base,
5227                                  int cpu_scratch_size, struct fw_info *info)
5228 {
5229         int err, lock_err, i;
5230         void (*write_op)(struct tg3 *, u32, u32);
5231
5232         if (cpu_base == TX_CPU_BASE &&
5233             (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
5234                 printk(KERN_ERR PFX "tg3_load_firmware_cpu: Trying to load "
5235                        "TX cpu firmware on %s which is 5705.\n",
5236                        tp->dev->name);
5237                 return -EINVAL;
5238         }
5239
5240         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
5241                 write_op = tg3_write_mem;
5242         else
5243                 write_op = tg3_write_indirect_reg32;
5244
5245         /* It is possible that bootcode is still loading at this point.
5246          * Get the nvram lock first before halting the cpu.
5247          */
5248         lock_err = tg3_nvram_lock(tp);
5249         err = tg3_halt_cpu(tp, cpu_base);
5250         if (!lock_err)
5251                 tg3_nvram_unlock(tp);
5252         if (err)
5253                 goto out;
5254
5255         for (i = 0; i < cpu_scratch_size; i += sizeof(u32))
5256                 write_op(tp, cpu_scratch_base + i, 0);
5257         tw32(cpu_base + CPU_STATE, 0xffffffff);
5258         tw32(cpu_base + CPU_MODE, tr32(cpu_base+CPU_MODE)|CPU_MODE_HALT);
5259         for (i = 0; i < (info->text_len / sizeof(u32)); i++)
5260                 write_op(tp, (cpu_scratch_base +
5261                               (info->text_base & 0xffff) +
5262                               (i * sizeof(u32))),
5263                          (info->text_data ?
5264                           info->text_data[i] : 0));
5265         for (i = 0; i < (info->rodata_len / sizeof(u32)); i++)
5266                 write_op(tp, (cpu_scratch_base +
5267                               (info->rodata_base & 0xffff) +
5268                               (i * sizeof(u32))),
5269                          (info->rodata_data ?
5270                           info->rodata_data[i] : 0));
5271         for (i = 0; i < (info->data_len / sizeof(u32)); i++)
5272                 write_op(tp, (cpu_scratch_base +
5273                               (info->data_base & 0xffff) +
5274                               (i * sizeof(u32))),
5275                          (info->data_data ?
5276                           info->data_data[i] : 0));
5277
5278         err = 0;
5279
5280 out:
5281         return err;
5282 }
5283
5284 /* tp->lock is held. */
5285 static int tg3_load_5701_a0_firmware_fix(struct tg3 *tp)
5286 {
5287         struct fw_info info;
5288         int err, i;
5289
5290         info.text_base = TG3_FW_TEXT_ADDR;
5291         info.text_len = TG3_FW_TEXT_LEN;
5292         info.text_data = &tg3FwText[0];
5293         info.rodata_base = TG3_FW_RODATA_ADDR;
5294         info.rodata_len = TG3_FW_RODATA_LEN;
5295         info.rodata_data = &tg3FwRodata[0];
5296         info.data_base = TG3_FW_DATA_ADDR;
5297         info.data_len = TG3_FW_DATA_LEN;
5298         info.data_data = NULL;
5299
5300         err = tg3_load_firmware_cpu(tp, RX_CPU_BASE,
5301                                     RX_CPU_SCRATCH_BASE, RX_CPU_SCRATCH_SIZE,
5302                                     &info);
5303         if (err)
5304                 return err;
5305
5306         err = tg3_load_firmware_cpu(tp, TX_CPU_BASE,
5307                                     TX_CPU_SCRATCH_BASE, TX_CPU_SCRATCH_SIZE,
5308                                     &info);
5309         if (err)
5310                 return err;
5311
5312         /* Now startup only the RX cpu. */
5313         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5314         tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5315
5316         for (i = 0; i < 5; i++) {
5317                 if (tr32(RX_CPU_BASE + CPU_PC) == TG3_FW_TEXT_ADDR)
5318                         break;
5319                 tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5320                 tw32(RX_CPU_BASE + CPU_MODE,  CPU_MODE_HALT);
5321                 tw32_f(RX_CPU_BASE + CPU_PC,    TG3_FW_TEXT_ADDR);
5322                 udelay(1000);
5323         }
5324         if (i >= 5) {
5325                 printk(KERN_ERR PFX "tg3_load_firmware fails for %s "
5326                        "to set RX CPU PC, is %08x should be %08x\n",
5327                        tp->dev->name, tr32(RX_CPU_BASE + CPU_PC),
5328                        TG3_FW_TEXT_ADDR);
5329                 return -ENODEV;
5330         }
5331         tw32(RX_CPU_BASE + CPU_STATE, 0xffffffff);
5332         tw32_f(RX_CPU_BASE + CPU_MODE,  0x00000000);
5333
5334         return 0;
5335 }
5336
5337
5338 #define TG3_TSO_FW_RELEASE_MAJOR        0x1
5339 #define TG3_TSO_FW_RELASE_MINOR         0x6
5340 #define TG3_TSO_FW_RELEASE_FIX          0x0
5341 #define TG3_TSO_FW_START_ADDR           0x08000000
5342 #define TG3_TSO_FW_TEXT_ADDR            0x08000000
5343 #define TG3_TSO_FW_TEXT_LEN             0x1aa0
5344 #define TG3_TSO_FW_RODATA_ADDR          0x08001aa0
5345 #define TG3_TSO_FW_RODATA_LEN           0x60
5346 #define TG3_TSO_FW_DATA_ADDR            0x08001b20
5347 #define TG3_TSO_FW_DATA_LEN             0x30
5348 #define TG3_TSO_FW_SBSS_ADDR            0x08001b50
5349 #define TG3_TSO_FW_SBSS_LEN             0x2c
5350 #define TG3_TSO_FW_BSS_ADDR             0x08001b80
5351 #define TG3_TSO_FW_BSS_LEN              0x894
5352
5353 static const u32 tg3TsoFwText[(TG3_TSO_FW_TEXT_LEN / 4) + 1] = {
5354         0x0e000003, 0x00000000, 0x08001b24, 0x00000000, 0x10000003, 0x00000000,
5355         0x0000000d, 0x0000000d, 0x3c1d0800, 0x37bd4000, 0x03a0f021, 0x3c100800,
5356         0x26100000, 0x0e000010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5357         0xafbf0018, 0x0e0005d8, 0x34840002, 0x0e000668, 0x00000000, 0x3c030800,
5358         0x90631b68, 0x24020002, 0x3c040800, 0x24841aac, 0x14620003, 0x24050001,
5359         0x3c040800, 0x24841aa0, 0x24060006, 0x00003821, 0xafa00010, 0x0e00067c,
5360         0xafa00014, 0x8f625c50, 0x34420001, 0xaf625c50, 0x8f625c90, 0x34420001,
5361         0xaf625c90, 0x2402ffff, 0x0e000034, 0xaf625404, 0x8fbf0018, 0x03e00008,
5362         0x27bd0020, 0x00000000, 0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c,
5363         0xafb20018, 0xafb10014, 0x0e00005b, 0xafb00010, 0x24120002, 0x24110001,
5364         0x8f706820, 0x32020100, 0x10400003, 0x00000000, 0x0e0000bb, 0x00000000,
5365         0x8f706820, 0x32022000, 0x10400004, 0x32020001, 0x0e0001f0, 0x24040001,
5366         0x32020001, 0x10400003, 0x00000000, 0x0e0000a3, 0x00000000, 0x3c020800,
5367         0x90421b98, 0x14520003, 0x00000000, 0x0e0004c0, 0x00000000, 0x0a00003c,
5368         0xaf715028, 0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008,
5369         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ac0, 0x00002821, 0x00003021,
5370         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x3c040800,
5371         0x248423d8, 0xa4800000, 0x3c010800, 0xa0201b98, 0x3c010800, 0xac201b9c,
5372         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5373         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bbc, 0x8f624434, 0x3c010800,
5374         0xac221b88, 0x8f624438, 0x3c010800, 0xac221b8c, 0x8f624410, 0xac80f7a8,
5375         0x3c010800, 0xac201b84, 0x3c010800, 0xac2023e0, 0x3c010800, 0xac2023c8,
5376         0x3c010800, 0xac2023cc, 0x3c010800, 0xac202400, 0x3c010800, 0xac221b90,
5377         0x8f620068, 0x24030007, 0x00021702, 0x10430005, 0x00000000, 0x8f620068,
5378         0x00021702, 0x14400004, 0x24020001, 0x3c010800, 0x0a000097, 0xac20240c,
5379         0xac820034, 0x3c040800, 0x24841acc, 0x3c050800, 0x8ca5240c, 0x00003021,
5380         0x00003821, 0xafa00010, 0x0e00067c, 0xafa00014, 0x8fbf0018, 0x03e00008,
5381         0x27bd0020, 0x27bdffe0, 0x3c040800, 0x24841ad8, 0x00002821, 0x00003021,
5382         0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014, 0x0e00005b,
5383         0x00000000, 0x0e0000b4, 0x00002021, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5384         0x24020001, 0x8f636820, 0x00821004, 0x00021027, 0x00621824, 0x03e00008,
5385         0xaf636820, 0x27bdffd0, 0xafbf002c, 0xafb60028, 0xafb50024, 0xafb40020,
5386         0xafb3001c, 0xafb20018, 0xafb10014, 0xafb00010, 0x8f675c5c, 0x3c030800,
5387         0x24631bbc, 0x8c620000, 0x14470005, 0x3c0200ff, 0x3c020800, 0x90421b98,
5388         0x14400119, 0x3c0200ff, 0x3442fff8, 0x00e28824, 0xac670000, 0x00111902,
5389         0x306300ff, 0x30e20003, 0x000211c0, 0x00622825, 0x00a04021, 0x00071602,
5390         0x3c030800, 0x90631b98, 0x3044000f, 0x14600036, 0x00804821, 0x24020001,
5391         0x3c010800, 0xa0221b98, 0x00051100, 0x00821025, 0x3c010800, 0xac201b9c,
5392         0x3c010800, 0xac201ba0, 0x3c010800, 0xac201ba4, 0x3c010800, 0xac201bac,
5393         0x3c010800, 0xac201bb8, 0x3c010800, 0xac201bb0, 0x3c010800, 0xac201bb4,
5394         0x3c010800, 0xa42223d8, 0x9622000c, 0x30437fff, 0x3c010800, 0xa4222410,
5395         0x30428000, 0x3c010800, 0xa4231bc6, 0x10400005, 0x24020001, 0x3c010800,
5396         0xac2223f4, 0x0a000102, 0x2406003e, 0x24060036, 0x3c010800, 0xac2023f4,
5397         0x9622000a, 0x3c030800, 0x94631bc6, 0x3c010800, 0xac2023f0, 0x3c010800,
5398         0xac2023f8, 0x00021302, 0x00021080, 0x00c21021, 0x00621821, 0x3c010800,
5399         0xa42223d0, 0x3c010800, 0x0a000115, 0xa4231b96, 0x9622000c, 0x3c010800,
5400         0xa42223ec, 0x3c040800, 0x24841b9c, 0x8c820000, 0x00021100, 0x3c010800,
5401         0x00220821, 0xac311bc8, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5402         0xac271bcc, 0x8c820000, 0x25030001, 0x306601ff, 0x00021100, 0x3c010800,
5403         0x00220821, 0xac261bd0, 0x8c820000, 0x00021100, 0x3c010800, 0x00220821,
5404         0xac291bd4, 0x96230008, 0x3c020800, 0x8c421bac, 0x00432821, 0x3c010800,
5405         0xac251bac, 0x9622000a, 0x30420004, 0x14400018, 0x00061100, 0x8f630c14,
5406         0x3063000f, 0x2c620002, 0x1440000b, 0x3c02c000, 0x8f630c14, 0x3c020800,
5407         0x8c421b40, 0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002,
5408         0x1040fff7, 0x3c02c000, 0x00e21825, 0xaf635c5c, 0x8f625c50, 0x30420002,
5409         0x10400014, 0x00000000, 0x0a000147, 0x00000000, 0x3c030800, 0x8c631b80,
5410         0x3c040800, 0x94841b94, 0x01221025, 0x3c010800, 0xa42223da, 0x24020001,
5411         0x3c010800, 0xac221bb8, 0x24630001, 0x0085202a, 0x3c010800, 0x10800003,
5412         0xac231b80, 0x3c010800, 0xa4251b94, 0x3c060800, 0x24c61b9c, 0x8cc20000,
5413         0x24420001, 0xacc20000, 0x28420080, 0x14400005, 0x00000000, 0x0e000656,
5414         0x24040002, 0x0a0001e6, 0x00000000, 0x3c020800, 0x8c421bb8, 0x10400078,
5415         0x24020001, 0x3c050800, 0x90a51b98, 0x14a20072, 0x00000000, 0x3c150800,
5416         0x96b51b96, 0x3c040800, 0x8c841bac, 0x32a3ffff, 0x0083102a, 0x1440006c,
5417         0x00000000, 0x14830003, 0x00000000, 0x3c010800, 0xac2523f0, 0x1060005c,
5418         0x00009021, 0x24d60004, 0x0060a021, 0x24d30014, 0x8ec20000, 0x00028100,
5419         0x3c110800, 0x02308821, 0x0e000625, 0x8e311bc8, 0x00402821, 0x10a00054,
5420         0x00000000, 0x9628000a, 0x31020040, 0x10400005, 0x2407180c, 0x8e22000c,
5421         0x2407188c, 0x00021400, 0xaca20018, 0x3c030800, 0x00701821, 0x8c631bd0,
5422         0x3c020800, 0x00501021, 0x8c421bd4, 0x00031d00, 0x00021400, 0x00621825,
5423         0xaca30014, 0x8ec30004, 0x96220008, 0x00432023, 0x3242ffff, 0x3083ffff,
5424         0x00431021, 0x0282102a, 0x14400002, 0x02b23023, 0x00803021, 0x8e620000,
5425         0x30c4ffff, 0x00441021, 0xae620000, 0x8e220000, 0xaca20000, 0x8e220004,
5426         0x8e63fff4, 0x00431021, 0xaca20004, 0xa4a6000e, 0x8e62fff4, 0x00441021,
5427         0xae62fff4, 0x96230008, 0x0043102a, 0x14400005, 0x02469021, 0x8e62fff0,
5428         0xae60fff4, 0x24420001, 0xae62fff0, 0xaca00008, 0x3242ffff, 0x14540008,
5429         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x24020905, 0xa4a2000c,
5430         0x0a0001cb, 0x34e70020, 0xa4a2000c, 0x3c020800, 0x8c4223f0, 0x10400003,
5431         0x3c024b65, 0x0a0001d3, 0x34427654, 0x3c02b49a, 0x344289ab, 0xaca2001c,
5432         0x30e2ffff, 0xaca20010, 0x0e0005a2, 0x00a02021, 0x3242ffff, 0x0054102b,
5433         0x1440ffa9, 0x00000000, 0x24020002, 0x3c010800, 0x0a0001e6, 0xa0221b98,
5434         0x8ec2083c, 0x24420001, 0x0a0001e6, 0xaec2083c, 0x0e0004c0, 0x00000000,
5435         0x8fbf002c, 0x8fb60028, 0x8fb50024, 0x8fb40020, 0x8fb3001c, 0x8fb20018,
5436         0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0030, 0x27bdffd0, 0xafbf0028,
5437         0xafb30024, 0xafb20020, 0xafb1001c, 0xafb00018, 0x8f725c9c, 0x3c0200ff,
5438         0x3442fff8, 0x3c070800, 0x24e71bb4, 0x02428824, 0x9623000e, 0x8ce20000,
5439         0x00431021, 0xace20000, 0x8e220010, 0x30420020, 0x14400011, 0x00809821,
5440         0x0e00063b, 0x02202021, 0x3c02c000, 0x02421825, 0xaf635c9c, 0x8f625c90,
5441         0x30420002, 0x1040011e, 0x00000000, 0xaf635c9c, 0x8f625c90, 0x30420002,
5442         0x10400119, 0x00000000, 0x0a00020d, 0x00000000, 0x8e240008, 0x8e230014,
5443         0x00041402, 0x000231c0, 0x00031502, 0x304201ff, 0x2442ffff, 0x3042007f,
5444         0x00031942, 0x30637800, 0x00021100, 0x24424000, 0x00624821, 0x9522000a,
5445         0x3084ffff, 0x30420008, 0x104000b0, 0x000429c0, 0x3c020800, 0x8c422400,
5446         0x14400024, 0x24c50008, 0x94c20014, 0x3c010800, 0xa42223d0, 0x8cc40010,
5447         0x00041402, 0x3c010800, 0xa42223d2, 0x3c010800, 0xa42423d4, 0x94c2000e,
5448         0x3083ffff, 0x00431023, 0x3c010800, 0xac222408, 0x94c2001a, 0x3c010800,
5449         0xac262400, 0x3c010800, 0xac322404, 0x3c010800, 0xac2223fc, 0x3c02c000,
5450         0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e5, 0x00000000,
5451         0xaf635c9c, 0x8f625c90, 0x30420002, 0x104000e0, 0x00000000, 0x0a000246,
5452         0x00000000, 0x94c2000e, 0x3c030800, 0x946323d4, 0x00434023, 0x3103ffff,
5453         0x2c620008, 0x1040001c, 0x00000000, 0x94c20014, 0x24420028, 0x00a22821,
5454         0x00031042, 0x1840000b, 0x00002021, 0x24e60848, 0x00403821, 0x94a30000,
5455         0x8cc20000, 0x24840001, 0x00431021, 0xacc20000, 0x0087102a, 0x1440fff9,
5456         0x24a50002, 0x31020001, 0x1040001f, 0x3c024000, 0x3c040800, 0x248423fc,
5457         0xa0a00001, 0x94a30000, 0x8c820000, 0x00431021, 0x0a000285, 0xac820000,
5458         0x8f626800, 0x3c030010, 0x00431024, 0x10400009, 0x00000000, 0x94c2001a,
5459         0x3c030800, 0x8c6323fc, 0x00431021, 0x3c010800, 0xac2223fc, 0x0a000286,
5460         0x3c024000, 0x94c2001a, 0x94c4001c, 0x3c030800, 0x8c6323fc, 0x00441023,
5461         0x00621821, 0x3c010800, 0xac2323fc, 0x3c024000, 0x02421825, 0xaf635c9c,
5462         0x8f625c90, 0x30420002, 0x1440fffc, 0x00000000, 0x9522000a, 0x30420010,
5463         0x1040009b, 0x00000000, 0x3c030800, 0x946323d4, 0x3c070800, 0x24e72400,
5464         0x8ce40000, 0x8f626800, 0x24630030, 0x00832821, 0x3c030010, 0x00431024,
5465         0x1440000a, 0x00000000, 0x94a20004, 0x3c040800, 0x8c842408, 0x3c030800,
5466         0x8c6323fc, 0x00441023, 0x00621821, 0x3c010800, 0xac2323fc, 0x3c040800,
5467         0x8c8423fc, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402, 0x00822021,
5468         0x00041027, 0xa4a20006, 0x3c030800, 0x8c632404, 0x3c0200ff, 0x3442fff8,
5469         0x00628824, 0x96220008, 0x24050001, 0x24034000, 0x000231c0, 0x00801021,
5470         0xa4c2001a, 0xa4c0001c, 0xace00000, 0x3c010800, 0xac251b60, 0xaf635cb8,
5471         0x8f625cb0, 0x30420002, 0x10400003, 0x00000000, 0x3c010800, 0xac201b60,
5472         0x8e220008, 0xaf625cb8, 0x8f625cb0, 0x30420002, 0x10400003, 0x00000000,
5473         0x3c010800, 0xac201b60, 0x3c020800, 0x8c421b60, 0x1040ffec, 0x00000000,
5474         0x3c040800, 0x0e00063b, 0x8c842404, 0x0a00032a, 0x00000000, 0x3c030800,
5475         0x90631b98, 0x24020002, 0x14620003, 0x3c034b65, 0x0a0002e1, 0x00008021,
5476         0x8e22001c, 0x34637654, 0x10430002, 0x24100002, 0x24100001, 0x00c02021,
5477         0x0e000350, 0x02003021, 0x24020003, 0x3c010800, 0xa0221b98, 0x24020002,
5478         0x1202000a, 0x24020001, 0x3c030800, 0x8c6323f0, 0x10620006, 0x00000000,
5479         0x3c020800, 0x944223d8, 0x00021400, 0x0a00031f, 0xae220014, 0x3c040800,
5480         0x248423da, 0x94820000, 0x00021400, 0xae220014, 0x3c020800, 0x8c421bbc,
5481         0x3c03c000, 0x3c010800, 0xa0201b98, 0x00431025, 0xaf625c5c, 0x8f625c50,
5482         0x30420002, 0x10400009, 0x00000000, 0x2484f7e2, 0x8c820000, 0x00431025,
5483         0xaf625c5c, 0x8f625c50, 0x30420002, 0x1440fffa, 0x00000000, 0x3c020800,
5484         0x24421b84, 0x8c430000, 0x24630001, 0xac430000, 0x8f630c14, 0x3063000f,
5485         0x2c620002, 0x1440000c, 0x3c024000, 0x8f630c14, 0x3c020800, 0x8c421b40,
5486         0x3063000f, 0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7,
5487         0x00000000, 0x3c024000, 0x02421825, 0xaf635c9c, 0x8f625c90, 0x30420002,
5488         0x1440fffc, 0x00000000, 0x12600003, 0x00000000, 0x0e0004c0, 0x00000000,
5489         0x8fbf0028, 0x8fb30024, 0x8fb20020, 0x8fb1001c, 0x8fb00018, 0x03e00008,
5490         0x27bd0030, 0x8f634450, 0x3c040800, 0x24841b88, 0x8c820000, 0x00031c02,
5491         0x0043102b, 0x14400007, 0x3c038000, 0x8c840004, 0x8f624450, 0x00021c02,
5492         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5493         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3c024000,
5494         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00000000,
5495         0x03e00008, 0x00000000, 0x27bdffe0, 0x00805821, 0x14c00011, 0x256e0008,
5496         0x3c020800, 0x8c4223f4, 0x10400007, 0x24020016, 0x3c010800, 0xa42223d2,
5497         0x2402002a, 0x3c010800, 0x0a000364, 0xa42223d4, 0x8d670010, 0x00071402,
5498         0x3c010800, 0xa42223d2, 0x3c010800, 0xa42723d4, 0x3c040800, 0x948423d4,
5499         0x3c030800, 0x946323d2, 0x95cf0006, 0x3c020800, 0x944223d0, 0x00832023,
5500         0x01e2c023, 0x3065ffff, 0x24a20028, 0x01c24821, 0x3082ffff, 0x14c0001a,
5501         0x01226021, 0x9582000c, 0x3042003f, 0x3c010800, 0xa42223d6, 0x95820004,
5502         0x95830006, 0x3c010800, 0xac2023e4, 0x3c010800, 0xac2023e8, 0x00021400,
5503         0x00431025, 0x3c010800, 0xac221bc0, 0x95220004, 0x3c010800, 0xa4221bc4,
5504         0x95230002, 0x01e51023, 0x0043102a, 0x10400010, 0x24020001, 0x3c010800,
5505         0x0a000398, 0xac2223f8, 0x3c030800, 0x8c6323e8, 0x3c020800, 0x94421bc4,
5506         0x00431021, 0xa5220004, 0x3c020800, 0x94421bc0, 0xa5820004, 0x3c020800,
5507         0x8c421bc0, 0xa5820006, 0x3c020800, 0x8c4223f0, 0x3c0d0800, 0x8dad23e4,
5508         0x3c0a0800, 0x144000e5, 0x8d4a23e8, 0x3c020800, 0x94421bc4, 0x004a1821,
5509         0x3063ffff, 0x0062182b, 0x24020002, 0x10c2000d, 0x01435023, 0x3c020800,
5510         0x944223d6, 0x30420009, 0x10400008, 0x00000000, 0x9582000c, 0x3042fff6,
5511         0xa582000c, 0x3c020800, 0x944223d6, 0x30420009, 0x01a26823, 0x3c020800,
5512         0x8c4223f8, 0x1040004a, 0x01203821, 0x3c020800, 0x944223d2, 0x00004021,
5513         0xa520000a, 0x01e21023, 0xa5220002, 0x3082ffff, 0x00021042, 0x18400008,
5514         0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021, 0x0103102a,
5515         0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061402,
5516         0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021, 0x2527000c,
5517         0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004, 0x1440fffb,
5518         0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023, 0x01803821,
5519         0x3082ffff, 0xa4e00010, 0x00621821, 0x00021042, 0x18400010, 0x00c33021,
5520         0x00404821, 0x94e20000, 0x24e70002, 0x00c23021, 0x30e2007f, 0x14400006,
5521         0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80, 0x00625824, 0x25670008,
5522         0x0109102a, 0x1440fff3, 0x00000000, 0x30820001, 0x10400005, 0x00061c02,
5523         0xa0e00001, 0x94e20000, 0x00c23021, 0x00061c02, 0x30c2ffff, 0x00623021,
5524         0x00061402, 0x00c23021, 0x0a00047d, 0x30c6ffff, 0x24020002, 0x14c20081,
5525         0x00000000, 0x3c020800, 0x8c42240c, 0x14400007, 0x00000000, 0x3c020800,
5526         0x944223d2, 0x95230002, 0x01e21023, 0x10620077, 0x00000000, 0x3c020800,
5527         0x944223d2, 0x01e21023, 0xa5220002, 0x3c020800, 0x8c42240c, 0x1040001a,
5528         0x31e3ffff, 0x8dc70010, 0x3c020800, 0x94421b96, 0x00e04021, 0x00072c02,
5529         0x00aa2021, 0x00431023, 0x00823823, 0x00072402, 0x30e2ffff, 0x00823821,
5530         0x00071027, 0xa522000a, 0x3102ffff, 0x3c040800, 0x948423d4, 0x00453023,
5531         0x00e02821, 0x00641823, 0x006d1821, 0x00c33021, 0x00061c02, 0x30c2ffff,
5532         0x0a00047d, 0x00623021, 0x01203821, 0x00004021, 0x3082ffff, 0x00021042,
5533         0x18400008, 0x00003021, 0x00401821, 0x94e20000, 0x25080001, 0x00c23021,
5534         0x0103102a, 0x1440fffb, 0x24e70002, 0x00061c02, 0x30c2ffff, 0x00623021,
5535         0x00061402, 0x00c23021, 0x00c02821, 0x00061027, 0xa522000a, 0x00003021,
5536         0x2527000c, 0x00004021, 0x94e20000, 0x25080001, 0x00c23021, 0x2d020004,
5537         0x1440fffb, 0x24e70002, 0x95220002, 0x00004021, 0x91230009, 0x00442023,
5538         0x01803821, 0x3082ffff, 0xa4e00010, 0x3c040800, 0x948423d4, 0x00621821,
5539         0x00c33021, 0x00061c02, 0x30c2ffff, 0x00623021, 0x00061c02, 0x3c020800,
5540         0x944223d0, 0x00c34821, 0x00441023, 0x00021fc2, 0x00431021, 0x00021043,
5541         0x18400010, 0x00003021, 0x00402021, 0x94e20000, 0x24e70002, 0x00c23021,
5542         0x30e2007f, 0x14400006, 0x25080001, 0x8d630000, 0x3c02007f, 0x3442ff80,
5543         0x00625824, 0x25670008, 0x0104102a, 0x1440fff3, 0x00000000, 0x3c020800,
5544         0x944223ec, 0x00c23021, 0x3122ffff, 0x00c23021, 0x00061c02, 0x30c2ffff,
5545         0x00623021, 0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010,
5546         0xadc00014, 0x0a00049d, 0xadc00000, 0x8dc70010, 0x00e04021, 0x11400007,
5547         0x00072c02, 0x00aa3021, 0x00061402, 0x30c3ffff, 0x00433021, 0x00061402,
5548         0x00c22821, 0x00051027, 0xa522000a, 0x3c030800, 0x946323d4, 0x3102ffff,
5549         0x01e21021, 0x00433023, 0x00cd3021, 0x00061c02, 0x30c2ffff, 0x00623021,
5550         0x00061402, 0x00c23021, 0x00c04021, 0x00061027, 0xa5820010, 0x3102ffff,
5551         0x00051c00, 0x00431025, 0xadc20010, 0x3c020800, 0x8c4223f4, 0x10400005,
5552         0x2de205eb, 0x14400002, 0x25e2fff2, 0x34028870, 0xa5c20034, 0x3c030800,
5553         0x246323e8, 0x8c620000, 0x24420001, 0xac620000, 0x3c040800, 0x8c8423e4,
5554         0x3c020800, 0x8c421bc0, 0x3303ffff, 0x00832021, 0x00431821, 0x0062102b,
5555         0x3c010800, 0xac2423e4, 0x10400003, 0x2482ffff, 0x3c010800, 0xac2223e4,
5556         0x3c010800, 0xac231bc0, 0x03e00008, 0x27bd0020, 0x27bdffb8, 0x3c050800,
5557         0x24a51b96, 0xafbf0044, 0xafbe0040, 0xafb7003c, 0xafb60038, 0xafb50034,
5558         0xafb40030, 0xafb3002c, 0xafb20028, 0xafb10024, 0xafb00020, 0x94a90000,
5559         0x3c020800, 0x944223d0, 0x3c030800, 0x8c631bb0, 0x3c040800, 0x8c841bac,
5560         0x01221023, 0x0064182a, 0xa7a9001e, 0x106000be, 0xa7a20016, 0x24be0022,
5561         0x97b6001e, 0x24b3001a, 0x24b70016, 0x8fc20000, 0x14400008, 0x00000000,
5562         0x8fc2fff8, 0x97a30016, 0x8fc4fff4, 0x00431021, 0x0082202a, 0x148000b0,
5563         0x00000000, 0x97d50818, 0x32a2ffff, 0x104000a3, 0x00009021, 0x0040a021,
5564         0x00008821, 0x0e000625, 0x00000000, 0x00403021, 0x14c00007, 0x00000000,
5565         0x3c020800, 0x8c4223dc, 0x24420001, 0x3c010800, 0x0a000596, 0xac2223dc,
5566         0x3c100800, 0x02118021, 0x8e101bc8, 0x9608000a, 0x31020040, 0x10400005,
5567         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x31020080,
5568         0x54400001, 0x34e70010, 0x3c020800, 0x00511021, 0x8c421bd0, 0x3c030800,
5569         0x00711821, 0x8c631bd4, 0x00021500, 0x00031c00, 0x00431025, 0xacc20014,
5570         0x96040008, 0x3242ffff, 0x00821021, 0x0282102a, 0x14400002, 0x02b22823,
5571         0x00802821, 0x8e020000, 0x02459021, 0xacc20000, 0x8e020004, 0x00c02021,
5572         0x26310010, 0xac820004, 0x30e2ffff, 0xac800008, 0xa485000e, 0xac820010,
5573         0x24020305, 0x0e0005a2, 0xa482000c, 0x3242ffff, 0x0054102b, 0x1440ffc5,
5574         0x3242ffff, 0x0a00058e, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5575         0x10400067, 0x00000000, 0x8e62fff0, 0x00028900, 0x3c100800, 0x02118021,
5576         0x0e000625, 0x8e101bc8, 0x00403021, 0x14c00005, 0x00000000, 0x8e62082c,
5577         0x24420001, 0x0a000596, 0xae62082c, 0x9608000a, 0x31020040, 0x10400005,
5578         0x2407180c, 0x8e02000c, 0x2407188c, 0x00021400, 0xacc20018, 0x3c020800,
5579         0x00511021, 0x8c421bd0, 0x3c030800, 0x00711821, 0x8c631bd4, 0x00021500,
5580         0x00031c00, 0x00431025, 0xacc20014, 0x8e63fff4, 0x96020008, 0x00432023,
5581         0x3242ffff, 0x3083ffff, 0x00431021, 0x02c2102a, 0x10400003, 0x00802821,
5582         0x97a9001e, 0x01322823, 0x8e620000, 0x30a4ffff, 0x00441021, 0xae620000,
5583         0xa4c5000e, 0x8e020000, 0xacc20000, 0x8e020004, 0x8e63fff4, 0x00431021,
5584         0xacc20004, 0x8e63fff4, 0x96020008, 0x00641821, 0x0062102a, 0x14400006,
5585         0x02459021, 0x8e62fff0, 0xae60fff4, 0x24420001, 0x0a000571, 0xae62fff0,
5586         0xae63fff4, 0xacc00008, 0x3242ffff, 0x10560003, 0x31020004, 0x10400006,
5587         0x24020305, 0x31020080, 0x54400001, 0x34e70010, 0x34e70020, 0x24020905,
5588         0xa4c2000c, 0x8ee30000, 0x8ee20004, 0x14620007, 0x3c02b49a, 0x8ee20860,
5589         0x54400001, 0x34e70400, 0x3c024b65, 0x0a000588, 0x34427654, 0x344289ab,
5590         0xacc2001c, 0x30e2ffff, 0xacc20010, 0x0e0005a2, 0x00c02021, 0x3242ffff,
5591         0x0056102b, 0x1440ff9b, 0x00000000, 0x8e620000, 0x8e63fffc, 0x0043102a,
5592         0x1440ff48, 0x00000000, 0x8fbf0044, 0x8fbe0040, 0x8fb7003c, 0x8fb60038,
5593         0x8fb50034, 0x8fb40030, 0x8fb3002c, 0x8fb20028, 0x8fb10024, 0x8fb00020,
5594         0x03e00008, 0x27bd0048, 0x27bdffe8, 0xafbf0014, 0xafb00010, 0x8f624450,
5595         0x8f634410, 0x0a0005b1, 0x00808021, 0x8f626820, 0x30422000, 0x10400003,
5596         0x00000000, 0x0e0001f0, 0x00002021, 0x8f624450, 0x8f634410, 0x3042ffff,
5597         0x0043102b, 0x1440fff5, 0x00000000, 0x8f630c14, 0x3063000f, 0x2c620002,
5598         0x1440000b, 0x00000000, 0x8f630c14, 0x3c020800, 0x8c421b40, 0x3063000f,
5599         0x24420001, 0x3c010800, 0xac221b40, 0x2c620002, 0x1040fff7, 0x00000000,
5600         0xaf705c18, 0x8f625c10, 0x30420002, 0x10400009, 0x00000000, 0x8f626820,
5601         0x30422000, 0x1040fff8, 0x00000000, 0x0e0001f0, 0x00002021, 0x0a0005c4,
5602         0x00000000, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000,
5603         0x00000000, 0x00000000, 0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010,
5604         0xaf60680c, 0x8f626804, 0x34420082, 0xaf626804, 0x8f634000, 0x24020b50,
5605         0x3c010800, 0xac221b54, 0x24020b78, 0x3c010800, 0xac221b64, 0x34630002,
5606         0xaf634000, 0x0e000605, 0x00808021, 0x3c010800, 0xa0221b68, 0x304200ff,
5607         0x24030002, 0x14430005, 0x00000000, 0x3c020800, 0x8c421b54, 0x0a0005f8,
5608         0xac5000c0, 0x3c020800, 0x8c421b54, 0xac5000bc, 0x8f624434, 0x8f634438,
5609         0x8f644410, 0x3c010800, 0xac221b5c, 0x3c010800, 0xac231b6c, 0x3c010800,
5610         0xac241b58, 0x8fbf0014, 0x8fb00010, 0x03e00008, 0x27bd0018, 0x3c040800,
5611         0x8c870000, 0x3c03aa55, 0x3463aa55, 0x3c06c003, 0xac830000, 0x8cc20000,
5612         0x14430007, 0x24050002, 0x3c0355aa, 0x346355aa, 0xac830000, 0x8cc20000,
5613         0x50430001, 0x24050001, 0x3c020800, 0xac470000, 0x03e00008, 0x00a01021,
5614         0x27bdfff8, 0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe,
5615         0x00000000, 0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008,
5616         0x27bd0008, 0x8f634450, 0x3c020800, 0x8c421b5c, 0x00031c02, 0x0043102b,
5617         0x14400008, 0x3c038000, 0x3c040800, 0x8c841b6c, 0x8f624450, 0x00021c02,
5618         0x0083102b, 0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024,
5619         0x1440fffd, 0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff,
5620         0x2442e000, 0x2c422001, 0x14400003, 0x3c024000, 0x0a000648, 0x2402ffff,
5621         0x00822025, 0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021,
5622         0x03e00008, 0x00000000, 0x8f624450, 0x3c030800, 0x8c631b58, 0x0a000651,
5623         0x3042ffff, 0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000,
5624         0x03e00008, 0x00000000, 0x27bdffe0, 0x00802821, 0x3c040800, 0x24841af0,
5625         0x00003021, 0x00003821, 0xafbf0018, 0xafa00010, 0x0e00067c, 0xafa00014,
5626         0x0a000660, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x00000000,
5627         0x00000000, 0x00000000, 0x3c020800, 0x34423000, 0x3c030800, 0x34633000,
5628         0x3c040800, 0x348437ff, 0x3c010800, 0xac221b74, 0x24020040, 0x3c010800,
5629         0xac221b78, 0x3c010800, 0xac201b70, 0xac600000, 0x24630004, 0x0083102b,
5630         0x5040fffd, 0xac600000, 0x03e00008, 0x00000000, 0x00804821, 0x8faa0010,
5631         0x3c020800, 0x8c421b70, 0x3c040800, 0x8c841b78, 0x8fab0014, 0x24430001,
5632         0x0044102b, 0x3c010800, 0xac231b70, 0x14400003, 0x00004021, 0x3c010800,
5633         0xac201b70, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74, 0x91240000,
5634         0x00021140, 0x00431021, 0x00481021, 0x25080001, 0xa0440000, 0x29020008,
5635         0x1440fff4, 0x25290001, 0x3c020800, 0x8c421b70, 0x3c030800, 0x8c631b74,
5636         0x8f64680c, 0x00021140, 0x00431021, 0xac440008, 0xac45000c, 0xac460010,
5637         0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c, 0x00000000, 0x00000000,
5638 };
5639
5640 static const u32 tg3TsoFwRodata[] = {
5641         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5642         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x496e0000, 0x73746b6f,
5643         0x66662a2a, 0x00000000, 0x53774576, 0x656e7430, 0x00000000, 0x00000000,
5644         0x00000000, 0x00000000, 0x66617461, 0x6c457272, 0x00000000, 0x00000000,
5645         0x00000000,
5646 };
5647
5648 static const u32 tg3TsoFwData[] = {
5649         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x362e3000, 0x00000000,
5650         0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
5651         0x00000000,
5652 };
5653
5654 /* 5705 needs a special version of the TSO firmware.  */
5655 #define TG3_TSO5_FW_RELEASE_MAJOR       0x1
5656 #define TG3_TSO5_FW_RELASE_MINOR        0x2
5657 #define TG3_TSO5_FW_RELEASE_FIX         0x0
5658 #define TG3_TSO5_FW_START_ADDR          0x00010000
5659 #define TG3_TSO5_FW_TEXT_ADDR           0x00010000
5660 #define TG3_TSO5_FW_TEXT_LEN            0xe90
5661 #define TG3_TSO5_FW_RODATA_ADDR         0x00010e90
5662 #define TG3_TSO5_FW_RODATA_LEN          0x50
5663 #define TG3_TSO5_FW_DATA_ADDR           0x00010f00
5664 #define TG3_TSO5_FW_DATA_LEN            0x20
5665 #define TG3_TSO5_FW_SBSS_ADDR           0x00010f20
5666 #define TG3_TSO5_FW_SBSS_LEN            0x28
5667 #define TG3_TSO5_FW_BSS_ADDR            0x00010f50
5668 #define TG3_TSO5_FW_BSS_LEN             0x88
5669
5670 static const u32 tg3Tso5FwText[(TG3_TSO5_FW_TEXT_LEN / 4) + 1] = {
5671         0x0c004003, 0x00000000, 0x00010f04, 0x00000000, 0x10000003, 0x00000000,
5672         0x0000000d, 0x0000000d, 0x3c1d0001, 0x37bde000, 0x03a0f021, 0x3c100001,
5673         0x26100000, 0x0c004010, 0x00000000, 0x0000000d, 0x27bdffe0, 0x3c04fefe,
5674         0xafbf0018, 0x0c0042e8, 0x34840002, 0x0c004364, 0x00000000, 0x3c030001,
5675         0x90630f34, 0x24020002, 0x3c040001, 0x24840e9c, 0x14620003, 0x24050001,
5676         0x3c040001, 0x24840e90, 0x24060002, 0x00003821, 0xafa00010, 0x0c004378,
5677         0xafa00014, 0x0c00402c, 0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5678         0x00000000, 0x00000000, 0x27bdffe0, 0xafbf001c, 0xafb20018, 0xafb10014,
5679         0x0c0042d4, 0xafb00010, 0x3c128000, 0x24110001, 0x8f706810, 0x32020400,
5680         0x10400007, 0x00000000, 0x8f641008, 0x00921024, 0x14400003, 0x00000000,
5681         0x0c004064, 0x00000000, 0x3c020001, 0x90420f56, 0x10510003, 0x32020200,
5682         0x1040fff1, 0x00000000, 0x0c0041b4, 0x00000000, 0x08004034, 0x00000000,
5683         0x8fbf001c, 0x8fb20018, 0x8fb10014, 0x8fb00010, 0x03e00008, 0x27bd0020,
5684         0x27bdffe0, 0x3c040001, 0x24840eb0, 0x00002821, 0x00003021, 0x00003821,
5685         0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0000d021, 0x24020130,
5686         0xaf625000, 0x3c010001, 0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018,
5687         0x03e00008, 0x27bd0020, 0x00000000, 0x00000000, 0x3c030001, 0x24630f60,
5688         0x90620000, 0x27bdfff0, 0x14400003, 0x0080c021, 0x08004073, 0x00004821,
5689         0x3c022000, 0x03021024, 0x10400003, 0x24090002, 0x08004073, 0xa0600000,
5690         0x24090001, 0x00181040, 0x30431f80, 0x346f8008, 0x1520004b, 0x25eb0028,
5691         0x3c040001, 0x00832021, 0x8c848010, 0x3c050001, 0x24a50f7a, 0x00041402,
5692         0xa0a20000, 0x3c010001, 0xa0240f7b, 0x3c020001, 0x00431021, 0x94428014,
5693         0x3c010001, 0xa0220f7c, 0x3c0c0001, 0x01836021, 0x8d8c8018, 0x304200ff,
5694         0x24420008, 0x000220c3, 0x24020001, 0x3c010001, 0xa0220f60, 0x0124102b,
5695         0x1040000c, 0x00003821, 0x24a6000e, 0x01602821, 0x8ca20000, 0x8ca30004,
5696         0x24a50008, 0x24e70001, 0xacc20000, 0xacc30004, 0x00e4102b, 0x1440fff8,
5697         0x24c60008, 0x00003821, 0x3c080001, 0x25080f7b, 0x91060000, 0x3c020001,
5698         0x90420f7c, 0x2503000d, 0x00c32821, 0x00461023, 0x00021fc2, 0x00431021,
5699         0x00021043, 0x1840000c, 0x00002021, 0x91020001, 0x00461023, 0x00021fc2,
5700         0x00431021, 0x00021843, 0x94a20000, 0x24e70001, 0x00822021, 0x00e3102a,
5701         0x1440fffb, 0x24a50002, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5702         0x00822021, 0x3c02ffff, 0x01821024, 0x3083ffff, 0x00431025, 0x3c010001,
5703         0x080040fa, 0xac220f80, 0x3c050001, 0x24a50f7c, 0x90a20000, 0x3c0c0001,
5704         0x01836021, 0x8d8c8018, 0x000220c2, 0x1080000e, 0x00003821, 0x01603021,
5705         0x24a5000c, 0x8ca20000, 0x8ca30004, 0x24a50008, 0x24e70001, 0xacc20000,
5706         0xacc30004, 0x00e4102b, 0x1440fff8, 0x24c60008, 0x3c050001, 0x24a50f7c,
5707         0x90a20000, 0x30430007, 0x24020004, 0x10620011, 0x28620005, 0x10400005,
5708         0x24020002, 0x10620008, 0x000710c0, 0x080040fa, 0x00000000, 0x24020006,
5709         0x1062000e, 0x000710c0, 0x080040fa, 0x00000000, 0x00a21821, 0x9463000c,
5710         0x004b1021, 0x080040fa, 0xa4430000, 0x000710c0, 0x00a21821, 0x8c63000c,
5711         0x004b1021, 0x080040fa, 0xac430000, 0x00a21821, 0x8c63000c, 0x004b2021,
5712         0x00a21021, 0xac830000, 0x94420010, 0xa4820004, 0x95e70006, 0x3c020001,
5713         0x90420f7c, 0x3c030001, 0x90630f7a, 0x00e2c823, 0x3c020001, 0x90420f7b,
5714         0x24630028, 0x01e34021, 0x24420028, 0x15200012, 0x01e23021, 0x94c2000c,
5715         0x3c010001, 0xa4220f78, 0x94c20004, 0x94c30006, 0x3c010001, 0xa4200f76,
5716         0x3c010001, 0xa4200f72, 0x00021400, 0x00431025, 0x3c010001, 0xac220f6c,
5717         0x95020004, 0x3c010001, 0x08004124, 0xa4220f70, 0x3c020001, 0x94420f70,
5718         0x3c030001, 0x94630f72, 0x00431021, 0xa5020004, 0x3c020001, 0x94420f6c,
5719         0xa4c20004, 0x3c020001, 0x8c420f6c, 0xa4c20006, 0x3c040001, 0x94840f72,
5720         0x3c020001, 0x94420f70, 0x3c0a0001, 0x954a0f76, 0x00441821, 0x3063ffff,
5721         0x0062182a, 0x24020002, 0x1122000b, 0x00832023, 0x3c030001, 0x94630f78,
5722         0x30620009, 0x10400006, 0x3062fff6, 0xa4c2000c, 0x3c020001, 0x94420f78,
5723         0x30420009, 0x01425023, 0x24020001, 0x1122001b, 0x29220002, 0x50400005,
5724         0x24020002, 0x11200007, 0x31a2ffff, 0x08004197, 0x00000000, 0x1122001d,
5725         0x24020016, 0x08004197, 0x31a2ffff, 0x3c0e0001, 0x95ce0f80, 0x10800005,
5726         0x01806821, 0x01c42021, 0x00041c02, 0x3082ffff, 0x00627021, 0x000e1027,
5727         0xa502000a, 0x3c030001, 0x90630f7b, 0x31a2ffff, 0x00e21021, 0x0800418d,
5728         0x00432023, 0x3c020001, 0x94420f80, 0x00442021, 0x00041c02, 0x3082ffff,
5729         0x00622021, 0x00807021, 0x00041027, 0x08004185, 0xa502000a, 0x3c050001,
5730         0x24a50f7a, 0x90a30000, 0x14620002, 0x24e2fff2, 0xa5e20034, 0x90a20000,
5731         0x00e21023, 0xa5020002, 0x3c030001, 0x94630f80, 0x3c020001, 0x94420f5a,
5732         0x30e5ffff, 0x00641821, 0x00451023, 0x00622023, 0x00041c02, 0x3082ffff,
5733         0x00622021, 0x00041027, 0xa502000a, 0x3c030001, 0x90630f7c, 0x24620001,
5734         0x14a20005, 0x00807021, 0x01631021, 0x90420000, 0x08004185, 0x00026200,
5735         0x24620002, 0x14a20003, 0x306200fe, 0x004b1021, 0x944c0000, 0x3c020001,
5736         0x94420f82, 0x3183ffff, 0x3c040001, 0x90840f7b, 0x00431021, 0x00e21021,
5737         0x00442023, 0x008a2021, 0x00041c02, 0x3082ffff, 0x00622021, 0x00041402,
5738         0x00822021, 0x00806821, 0x00041027, 0xa4c20010, 0x31a2ffff, 0x000e1c00,
5739         0x00431025, 0x3c040001, 0x24840f72, 0xade20010, 0x94820000, 0x3c050001,
5740         0x94a50f76, 0x3c030001, 0x8c630f6c, 0x24420001, 0x00b92821, 0xa4820000,
5741         0x3322ffff, 0x00622021, 0x0083182b, 0x3c010001, 0xa4250f76, 0x10600003,
5742         0x24a2ffff, 0x3c010001, 0xa4220f76, 0x3c024000, 0x03021025, 0x3c010001,
5743         0xac240f6c, 0xaf621008, 0x03e00008, 0x27bd0010, 0x3c030001, 0x90630f56,
5744         0x27bdffe8, 0x24020001, 0xafbf0014, 0x10620026, 0xafb00010, 0x8f620cf4,
5745         0x2442ffff, 0x3042007f, 0x00021100, 0x8c434000, 0x3c010001, 0xac230f64,
5746         0x8c434008, 0x24444000, 0x8c5c4004, 0x30620040, 0x14400002, 0x24020088,
5747         0x24020008, 0x3c010001, 0xa4220f68, 0x30620004, 0x10400005, 0x24020001,
5748         0x3c010001, 0xa0220f57, 0x080041d5, 0x00031402, 0x3c010001, 0xa0200f57,
5749         0x00031402, 0x3c010001, 0xa4220f54, 0x9483000c, 0x24020001, 0x3c010001,
5750         0xa4200f50, 0x3c010001, 0xa0220f56, 0x3c010001, 0xa4230f62, 0x24020001,
5751         0x1342001e, 0x00000000, 0x13400005, 0x24020003, 0x13420067, 0x00000000,
5752         0x080042cf, 0x00000000, 0x3c020001, 0x94420f62, 0x241a0001, 0x3c010001,
5753         0xa4200f5e, 0x3c010001, 0xa4200f52, 0x304407ff, 0x00021bc2, 0x00031823,
5754         0x3063003e, 0x34630036, 0x00021242, 0x3042003c, 0x00621821, 0x3c010001,
5755         0xa4240f58, 0x00832021, 0x24630030, 0x3c010001, 0xa4240f5a, 0x3c010001,
5756         0xa4230f5c, 0x3c060001, 0x24c60f52, 0x94c50000, 0x94c30002, 0x3c040001,
5757         0x94840f5a, 0x00651021, 0x0044102a, 0x10400013, 0x3c108000, 0x00a31021,
5758         0xa4c20000, 0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008,
5759         0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4,
5760         0x00501024, 0x104000b7, 0x00000000, 0x0800420f, 0x00000000, 0x3c030001,
5761         0x94630f50, 0x00851023, 0xa4c40000, 0x00621821, 0x3042ffff, 0x3c010001,
5762         0xa4230f50, 0xaf620ce8, 0x3c020001, 0x94420f68, 0x34420024, 0xaf620cec,
5763         0x94c30002, 0x3c020001, 0x94420f50, 0x14620012, 0x3c028000, 0x3c108000,
5764         0x3c02a000, 0xaf620cf4, 0x3c010001, 0xa0200f56, 0x8f641008, 0x00901024,
5765         0x14400003, 0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024,
5766         0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003, 0xaf620cf4, 0x3c108000,
5767         0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064, 0x00000000,
5768         0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x080042cf, 0x241a0003,
5769         0x3c070001, 0x24e70f50, 0x94e20000, 0x03821021, 0xaf620ce0, 0x3c020001,
5770         0x8c420f64, 0xaf620ce4, 0x3c050001, 0x94a50f54, 0x94e30000, 0x3c040001,
5771         0x94840f58, 0x3c020001, 0x94420f5e, 0x00a32823, 0x00822023, 0x30a6ffff,
5772         0x3083ffff, 0x00c3102b, 0x14400043, 0x00000000, 0x3c020001, 0x94420f5c,
5773         0x00021400, 0x00621025, 0xaf620ce8, 0x94e20000, 0x3c030001, 0x94630f54,
5774         0x00441021, 0xa4e20000, 0x3042ffff, 0x14430021, 0x3c020008, 0x3c020001,
5775         0x90420f57, 0x10400006, 0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624,
5776         0x0800427c, 0x0000d021, 0x3c020001, 0x94420f68, 0x3c030008, 0x34630624,
5777         0x00431025, 0xaf620cec, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5778         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5779         0x00000000, 0x8f620cf4, 0x00501024, 0x10400015, 0x00000000, 0x08004283,
5780         0x00000000, 0x3c030001, 0x94630f68, 0x34420624, 0x3c108000, 0x00621825,
5781         0x3c028000, 0xaf630cec, 0xaf620cf4, 0x8f641008, 0x00901024, 0x14400003,
5782         0x00000000, 0x0c004064, 0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7,
5783         0x00000000, 0x3c010001, 0x080042cf, 0xa4200f5e, 0x3c020001, 0x94420f5c,
5784         0x00021400, 0x00c21025, 0xaf620ce8, 0x3c020001, 0x90420f57, 0x10400009,
5785         0x3c03000c, 0x3c020001, 0x94420f68, 0x34630624, 0x0000d021, 0x00431025,
5786         0xaf620cec, 0x080042c1, 0x3c108000, 0x3c020001, 0x94420f68, 0x3c030008,
5787         0x34630604, 0x00431025, 0xaf620cec, 0x3c020001, 0x94420f5e, 0x00451021,
5788         0x3c010001, 0xa4220f5e, 0x3c108000, 0x3c02a000, 0xaf620cf4, 0x3c010001,
5789         0xa0200f56, 0x8f641008, 0x00901024, 0x14400003, 0x00000000, 0x0c004064,
5790         0x00000000, 0x8f620cf4, 0x00501024, 0x1440fff7, 0x00000000, 0x8fbf0014,
5791         0x8fb00010, 0x03e00008, 0x27bd0018, 0x00000000, 0x27bdffe0, 0x3c040001,
5792         0x24840ec0, 0x00002821, 0x00003021, 0x00003821, 0xafbf0018, 0xafa00010,
5793         0x0c004378, 0xafa00014, 0x0000d021, 0x24020130, 0xaf625000, 0x3c010001,
5794         0xa4200f50, 0x3c010001, 0xa0200f57, 0x8fbf0018, 0x03e00008, 0x27bd0020,
5795         0x27bdffe8, 0x3c1bc000, 0xafbf0014, 0xafb00010, 0xaf60680c, 0x8f626804,
5796         0x34420082, 0xaf626804, 0x8f634000, 0x24020b50, 0x3c010001, 0xac220f20,
5797         0x24020b78, 0x3c010001, 0xac220f30, 0x34630002, 0xaf634000, 0x0c004315,
5798         0x00808021, 0x3c010001, 0xa0220f34, 0x304200ff, 0x24030002, 0x14430005,
5799         0x00000000, 0x3c020001, 0x8c420f20, 0x08004308, 0xac5000c0, 0x3c020001,
5800         0x8c420f20, 0xac5000bc, 0x8f624434, 0x8f634438, 0x8f644410, 0x3c010001,
5801         0xac220f28, 0x3c010001, 0xac230f38, 0x3c010001, 0xac240f24, 0x8fbf0014,
5802         0x8fb00010, 0x03e00008, 0x27bd0018, 0x03e00008, 0x24020001, 0x27bdfff8,
5803         0x18800009, 0x00002821, 0x8f63680c, 0x8f62680c, 0x1043fffe, 0x00000000,
5804         0x24a50001, 0x00a4102a, 0x1440fff9, 0x00000000, 0x03e00008, 0x27bd0008,
5805         0x8f634450, 0x3c020001, 0x8c420f28, 0x00031c02, 0x0043102b, 0x14400008,
5806         0x3c038000, 0x3c040001, 0x8c840f38, 0x8f624450, 0x00021c02, 0x0083102b,
5807         0x1040fffc, 0x3c038000, 0xaf634444, 0x8f624444, 0x00431024, 0x1440fffd,
5808         0x00000000, 0x8f624448, 0x03e00008, 0x3042ffff, 0x3082ffff, 0x2442e000,
5809         0x2c422001, 0x14400003, 0x3c024000, 0x08004347, 0x2402ffff, 0x00822025,
5810         0xaf645c38, 0x8f625c30, 0x30420002, 0x1440fffc, 0x00001021, 0x03e00008,
5811         0x00000000, 0x8f624450, 0x3c030001, 0x8c630f24, 0x08004350, 0x3042ffff,
5812         0x8f624450, 0x3042ffff, 0x0043102b, 0x1440fffc, 0x00000000, 0x03e00008,
5813         0x00000000, 0x27bdffe0, 0x00802821, 0x3c040001, 0x24840ed0, 0x00003021,
5814         0x00003821, 0xafbf0018, 0xafa00010, 0x0c004378, 0xafa00014, 0x0800435f,
5815         0x00000000, 0x8fbf0018, 0x03e00008, 0x27bd0020, 0x3c020001, 0x3442d600,
5816         0x3c030001, 0x3463d600, 0x3c040001, 0x3484ddff, 0x3c010001, 0xac220f40,
5817         0x24020040, 0x3c010001, 0xac220f44, 0x3c010001, 0xac200f3c, 0xac600000,
5818         0x24630004, 0x0083102b, 0x5040fffd, 0xac600000, 0x03e00008, 0x00000000,
5819         0x00804821, 0x8faa0010, 0x3c020001, 0x8c420f3c, 0x3c040001, 0x8c840f44,
5820         0x8fab0014, 0x24430001, 0x0044102b, 0x3c010001, 0xac230f3c, 0x14400003,
5821         0x00004021, 0x3c010001, 0xac200f3c, 0x3c020001, 0x8c420f3c, 0x3c030001,
5822         0x8c630f40, 0x91240000, 0x00021140, 0x00431021, 0x00481021, 0x25080001,
5823         0xa0440000, 0x29020008, 0x1440fff4, 0x25290001, 0x3c020001, 0x8c420f3c,
5824         0x3c030001, 0x8c630f40, 0x8f64680c, 0x00021140, 0x00431021, 0xac440008,
5825         0xac45000c, 0xac460010, 0xac470014, 0xac4a0018, 0x03e00008, 0xac4b001c,
5826         0x00000000, 0x00000000, 0x00000000,
5827 };
5828
5829 static const u32 tg3Tso5FwRodata[(TG3_TSO5_FW_RODATA_LEN / 4) + 1] = {
5830         0x4d61696e, 0x43707542, 0x00000000, 0x4d61696e, 0x43707541, 0x00000000,
5831         0x00000000, 0x00000000, 0x73746b6f, 0x66666c64, 0x00000000, 0x00000000,
5832         0x73746b6f, 0x66666c64, 0x00000000, 0x00000000, 0x66617461, 0x6c457272,
5833         0x00000000, 0x00000000, 0x00000000,
5834 };
5835
5836 static const u32 tg3Tso5FwData[(TG3_TSO5_FW_DATA_LEN / 4) + 1] = {
5837         0x00000000, 0x73746b6f, 0x66666c64, 0x5f76312e, 0x322e3000, 0x00000000,
5838         0x00000000, 0x00000000, 0x00000000,
5839 };
5840
5841 /* tp->lock is held. */
5842 static int tg3_load_tso_firmware(struct tg3 *tp)
5843 {
5844         struct fw_info info;
5845         unsigned long cpu_base, cpu_scratch_base, cpu_scratch_size;
5846         int err, i;
5847
5848         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
5849                 return 0;
5850
5851         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
5852                 info.text_base = TG3_TSO5_FW_TEXT_ADDR;
5853                 info.text_len = TG3_TSO5_FW_TEXT_LEN;
5854                 info.text_data = &tg3Tso5FwText[0];
5855                 info.rodata_base = TG3_TSO5_FW_RODATA_ADDR;
5856                 info.rodata_len = TG3_TSO5_FW_RODATA_LEN;
5857                 info.rodata_data = &tg3Tso5FwRodata[0];
5858                 info.data_base = TG3_TSO5_FW_DATA_ADDR;
5859                 info.data_len = TG3_TSO5_FW_DATA_LEN;
5860                 info.data_data = &tg3Tso5FwData[0];
5861                 cpu_base = RX_CPU_BASE;
5862                 cpu_scratch_base = NIC_SRAM_MBUF_POOL_BASE5705;
5863                 cpu_scratch_size = (info.text_len +
5864                                     info.rodata_len +
5865                                     info.data_len +
5866                                     TG3_TSO5_FW_SBSS_LEN +
5867                                     TG3_TSO5_FW_BSS_LEN);
5868         } else {
5869                 info.text_base = TG3_TSO_FW_TEXT_ADDR;
5870                 info.text_len = TG3_TSO_FW_TEXT_LEN;
5871                 info.text_data = &tg3TsoFwText[0];
5872                 info.rodata_base = TG3_TSO_FW_RODATA_ADDR;
5873                 info.rodata_len = TG3_TSO_FW_RODATA_LEN;
5874                 info.rodata_data = &tg3TsoFwRodata[0];
5875                 info.data_base = TG3_TSO_FW_DATA_ADDR;
5876                 info.data_len = TG3_TSO_FW_DATA_LEN;
5877                 info.data_data = &tg3TsoFwData[0];
5878                 cpu_base = TX_CPU_BASE;
5879                 cpu_scratch_base = TX_CPU_SCRATCH_BASE;
5880                 cpu_scratch_size = TX_CPU_SCRATCH_SIZE;
5881         }
5882
5883         err = tg3_load_firmware_cpu(tp, cpu_base,
5884                                     cpu_scratch_base, cpu_scratch_size,
5885                                     &info);
5886         if (err)
5887                 return err;
5888
5889         /* Now startup the cpu. */
5890         tw32(cpu_base + CPU_STATE, 0xffffffff);
5891         tw32_f(cpu_base + CPU_PC,    info.text_base);
5892
5893         for (i = 0; i < 5; i++) {
5894                 if (tr32(cpu_base + CPU_PC) == info.text_base)
5895                         break;
5896                 tw32(cpu_base + CPU_STATE, 0xffffffff);
5897                 tw32(cpu_base + CPU_MODE,  CPU_MODE_HALT);
5898                 tw32_f(cpu_base + CPU_PC,    info.text_base);
5899                 udelay(1000);
5900         }
5901         if (i >= 5) {
5902                 printk(KERN_ERR PFX "tg3_load_tso_firmware fails for %s "
5903                        "to set CPU PC, is %08x should be %08x\n",
5904                        tp->dev->name, tr32(cpu_base + CPU_PC),
5905                        info.text_base);
5906                 return -ENODEV;
5907         }
5908         tw32(cpu_base + CPU_STATE, 0xffffffff);
5909         tw32_f(cpu_base + CPU_MODE,  0x00000000);
5910         return 0;
5911 }
5912
5913
5914 /* tp->lock is held. */
5915 static void __tg3_set_mac_addr(struct tg3 *tp)
5916 {
5917         u32 addr_high, addr_low;
5918         int i;
5919
5920         addr_high = ((tp->dev->dev_addr[0] << 8) |
5921                      tp->dev->dev_addr[1]);
5922         addr_low = ((tp->dev->dev_addr[2] << 24) |
5923                     (tp->dev->dev_addr[3] << 16) |
5924                     (tp->dev->dev_addr[4] <<  8) |
5925                     (tp->dev->dev_addr[5] <<  0));
5926         for (i = 0; i < 4; i++) {
5927                 tw32(MAC_ADDR_0_HIGH + (i * 8), addr_high);
5928                 tw32(MAC_ADDR_0_LOW + (i * 8), addr_low);
5929         }
5930
5931         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
5932             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
5933                 for (i = 0; i < 12; i++) {
5934                         tw32(MAC_EXTADDR_0_HIGH + (i * 8), addr_high);
5935                         tw32(MAC_EXTADDR_0_LOW + (i * 8), addr_low);
5936                 }
5937         }
5938
5939         addr_high = (tp->dev->dev_addr[0] +
5940                      tp->dev->dev_addr[1] +
5941                      tp->dev->dev_addr[2] +
5942                      tp->dev->dev_addr[3] +
5943                      tp->dev->dev_addr[4] +
5944                      tp->dev->dev_addr[5]) &
5945                 TX_BACKOFF_SEED_MASK;
5946         tw32(MAC_TX_BACKOFF_SEED, addr_high);
5947 }
5948
5949 static int tg3_set_mac_addr(struct net_device *dev, void *p)
5950 {
5951         struct tg3 *tp = netdev_priv(dev);
5952         struct sockaddr *addr = p;
5953         int err = 0;
5954
5955         if (!is_valid_ether_addr(addr->sa_data))
5956                 return -EINVAL;
5957
5958         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
5959
5960         if (!netif_running(dev))
5961                 return 0;
5962
5963         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
5964                 /* Reset chip so that ASF can re-init any MAC addresses it
5965                  * needs.
5966                  */
5967                 tg3_netif_stop(tp);
5968                 tg3_full_lock(tp, 1);
5969
5970                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
5971                 err = tg3_restart_hw(tp, 0);
5972                 if (!err)
5973                         tg3_netif_start(tp);
5974                 tg3_full_unlock(tp);
5975         } else {
5976                 spin_lock_bh(&tp->lock);
5977                 __tg3_set_mac_addr(tp);
5978                 spin_unlock_bh(&tp->lock);
5979         }
5980
5981         return err;
5982 }
5983
5984 /* tp->lock is held. */
5985 static void tg3_set_bdinfo(struct tg3 *tp, u32 bdinfo_addr,
5986                            dma_addr_t mapping, u32 maxlen_flags,
5987                            u32 nic_addr)
5988 {
5989         tg3_write_mem(tp,
5990                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH),
5991                       ((u64) mapping >> 32));
5992         tg3_write_mem(tp,
5993                       (bdinfo_addr + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW),
5994                       ((u64) mapping & 0xffffffff));
5995         tg3_write_mem(tp,
5996                       (bdinfo_addr + TG3_BDINFO_MAXLEN_FLAGS),
5997                        maxlen_flags);
5998
5999         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6000                 tg3_write_mem(tp,
6001                               (bdinfo_addr + TG3_BDINFO_NIC_ADDR),
6002                               nic_addr);
6003 }
6004
6005 static void __tg3_set_rx_mode(struct net_device *);
6006 static void __tg3_set_coalesce(struct tg3 *tp, struct ethtool_coalesce *ec)
6007 {
6008         tw32(HOSTCC_RXCOL_TICKS, ec->rx_coalesce_usecs);
6009         tw32(HOSTCC_TXCOL_TICKS, ec->tx_coalesce_usecs);
6010         tw32(HOSTCC_RXMAX_FRAMES, ec->rx_max_coalesced_frames);
6011         tw32(HOSTCC_TXMAX_FRAMES, ec->tx_max_coalesced_frames);
6012         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6013                 tw32(HOSTCC_RXCOAL_TICK_INT, ec->rx_coalesce_usecs_irq);
6014                 tw32(HOSTCC_TXCOAL_TICK_INT, ec->tx_coalesce_usecs_irq);
6015         }
6016         tw32(HOSTCC_RXCOAL_MAXF_INT, ec->rx_max_coalesced_frames_irq);
6017         tw32(HOSTCC_TXCOAL_MAXF_INT, ec->tx_max_coalesced_frames_irq);
6018         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6019                 u32 val = ec->stats_block_coalesce_usecs;
6020
6021                 if (!netif_carrier_ok(tp->dev))
6022                         val = 0;
6023
6024                 tw32(HOSTCC_STAT_COAL_TICKS, val);
6025         }
6026 }
6027
6028 /* tp->lock is held. */
6029 static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
6030 {
6031         u32 val, rdmac_mode;
6032         int i, err, limit;
6033
6034         tg3_disable_ints(tp);
6035
6036         tg3_stop_fw(tp);
6037
6038         tg3_write_sig_pre_reset(tp, RESET_KIND_INIT);
6039
6040         if (tp->tg3_flags & TG3_FLAG_INIT_COMPLETE) {
6041                 tg3_abort_hw(tp, 1);
6042         }
6043
6044         if (reset_phy)
6045                 tg3_phy_reset(tp);
6046
6047         err = tg3_chip_reset(tp);
6048         if (err)
6049                 return err;
6050
6051         tg3_write_sig_legacy(tp, RESET_KIND_INIT);
6052
6053         /* This works around an issue with Athlon chipsets on
6054          * B3 tigon3 silicon.  This bit has no effect on any
6055          * other revision.  But do not set this on PCI Express
6056          * chips.
6057          */
6058         if (!(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
6059                 tp->pci_clock_ctrl |= CLOCK_CTRL_DELAY_PCI_GRANT;
6060         tw32_f(TG3PCI_CLOCK_CTRL, tp->pci_clock_ctrl);
6061
6062         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0 &&
6063             (tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
6064                 val = tr32(TG3PCI_PCISTATE);
6065                 val |= PCISTATE_RETRY_SAME_DMA;
6066                 tw32(TG3PCI_PCISTATE, val);
6067         }
6068
6069         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_BX) {
6070                 /* Enable some hw fixes.  */
6071                 val = tr32(TG3PCI_MSI_DATA);
6072                 val |= (1 << 26) | (1 << 28) | (1 << 29);
6073                 tw32(TG3PCI_MSI_DATA, val);
6074         }
6075
6076         /* Descriptor ring init may make accesses to the
6077          * NIC SRAM area to setup the TX descriptors, so we
6078          * can only do this after the hardware has been
6079          * successfully reset.
6080          */
6081         err = tg3_init_rings(tp);
6082         if (err)
6083                 return err;
6084
6085         /* This value is determined during the probe time DMA
6086          * engine test, tg3_test_dma.
6087          */
6088         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
6089
6090         tp->grc_mode &= ~(GRC_MODE_HOST_SENDBDS |
6091                           GRC_MODE_4X_NIC_SEND_RINGS |
6092                           GRC_MODE_NO_TX_PHDR_CSUM |
6093                           GRC_MODE_NO_RX_PHDR_CSUM);
6094         tp->grc_mode |= GRC_MODE_HOST_SENDBDS;
6095
6096         /* Pseudo-header checksum is done by hardware logic and not
6097          * the offload processers, so make the chip do the pseudo-
6098          * header checksums on receive.  For transmit it is more
6099          * convenient to do the pseudo-header checksum in software
6100          * as Linux does that on transmit for us in all cases.
6101          */
6102         tp->grc_mode |= GRC_MODE_NO_TX_PHDR_CSUM;
6103
6104         tw32(GRC_MODE,
6105              tp->grc_mode |
6106              (GRC_MODE_IRQ_ON_MAC_ATTN | GRC_MODE_HOST_STACKUP));
6107
6108         /* Setup the timer prescalar register.  Clock is always 66Mhz. */
6109         val = tr32(GRC_MISC_CFG);
6110         val &= ~0xff;
6111         val |= (65 << GRC_MISC_CFG_PRESCALAR_SHIFT);
6112         tw32(GRC_MISC_CFG, val);
6113
6114         /* Initialize MBUF/DESC pool. */
6115         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6116                 /* Do nothing.  */
6117         } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
6118                 tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
6119                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
6120                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE64);
6121                 else
6122                         tw32(BUFMGR_MB_POOL_SIZE, NIC_SRAM_MBUF_POOL_SIZE96);
6123                 tw32(BUFMGR_DMA_DESC_POOL_ADDR, NIC_SRAM_DMA_DESC_POOL_BASE);
6124                 tw32(BUFMGR_DMA_DESC_POOL_SIZE, NIC_SRAM_DMA_DESC_POOL_SIZE);
6125         }
6126         else if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6127                 int fw_len;
6128
6129                 fw_len = (TG3_TSO5_FW_TEXT_LEN +
6130                           TG3_TSO5_FW_RODATA_LEN +
6131                           TG3_TSO5_FW_DATA_LEN +
6132                           TG3_TSO5_FW_SBSS_LEN +
6133                           TG3_TSO5_FW_BSS_LEN);
6134                 fw_len = (fw_len + (0x80 - 1)) & ~(0x80 - 1);
6135                 tw32(BUFMGR_MB_POOL_ADDR,
6136                      NIC_SRAM_MBUF_POOL_BASE5705 + fw_len);
6137                 tw32(BUFMGR_MB_POOL_SIZE,
6138                      NIC_SRAM_MBUF_POOL_SIZE5705 - fw_len - 0xa00);
6139         }
6140
6141         if (tp->dev->mtu <= ETH_DATA_LEN) {
6142                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6143                      tp->bufmgr_config.mbuf_read_dma_low_water);
6144                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6145                      tp->bufmgr_config.mbuf_mac_rx_low_water);
6146                 tw32(BUFMGR_MB_HIGH_WATER,
6147                      tp->bufmgr_config.mbuf_high_water);
6148         } else {
6149                 tw32(BUFMGR_MB_RDMA_LOW_WATER,
6150                      tp->bufmgr_config.mbuf_read_dma_low_water_jumbo);
6151                 tw32(BUFMGR_MB_MACRX_LOW_WATER,
6152                      tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo);
6153                 tw32(BUFMGR_MB_HIGH_WATER,
6154                      tp->bufmgr_config.mbuf_high_water_jumbo);
6155         }
6156         tw32(BUFMGR_DMA_LOW_WATER,
6157              tp->bufmgr_config.dma_low_water);
6158         tw32(BUFMGR_DMA_HIGH_WATER,
6159              tp->bufmgr_config.dma_high_water);
6160
6161         tw32(BUFMGR_MODE, BUFMGR_MODE_ENABLE | BUFMGR_MODE_ATTN_ENABLE);
6162         for (i = 0; i < 2000; i++) {
6163                 if (tr32(BUFMGR_MODE) & BUFMGR_MODE_ENABLE)
6164                         break;
6165                 udelay(10);
6166         }
6167         if (i >= 2000) {
6168                 printk(KERN_ERR PFX "tg3_reset_hw cannot enable BUFMGR for %s.\n",
6169                        tp->dev->name);
6170                 return -ENODEV;
6171         }
6172
6173         /* Setup replenish threshold. */
6174         val = tp->rx_pending / 8;
6175         if (val == 0)
6176                 val = 1;
6177         else if (val > tp->rx_std_max_post)
6178                 val = tp->rx_std_max_post;
6179         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
6180                 if (tp->pci_chip_rev_id == CHIPREV_ID_5906_A1)
6181                         tw32(ISO_PKT_TX, (tr32(ISO_PKT_TX) & ~0x3) | 0x2);
6182
6183                 if (val > (TG3_RX_INTERNAL_RING_SZ_5906 / 2))
6184                         val = TG3_RX_INTERNAL_RING_SZ_5906 / 2;
6185         }
6186
6187         tw32(RCVBDI_STD_THRESH, val);
6188
6189         /* Initialize TG3_BDINFO's at:
6190          *  RCVDBDI_STD_BD:     standard eth size rx ring
6191          *  RCVDBDI_JUMBO_BD:   jumbo frame rx ring
6192          *  RCVDBDI_MINI_BD:    small frame rx ring (??? does not work)
6193          *
6194          * like so:
6195          *  TG3_BDINFO_HOST_ADDR:       high/low parts of DMA address of ring
6196          *  TG3_BDINFO_MAXLEN_FLAGS:    (rx max buffer size << 16) |
6197          *                              ring attribute flags
6198          *  TG3_BDINFO_NIC_ADDR:        location of descriptors in nic SRAM
6199          *
6200          * Standard receive ring @ NIC_SRAM_RX_BUFFER_DESC, 512 entries.
6201          * Jumbo receive ring @ NIC_SRAM_RX_JUMBO_BUFFER_DESC, 256 entries.
6202          *
6203          * The size of each ring is fixed in the firmware, but the location is
6204          * configurable.
6205          */
6206         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6207              ((u64) tp->rx_std_mapping >> 32));
6208         tw32(RCVDBDI_STD_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6209              ((u64) tp->rx_std_mapping & 0xffffffff));
6210         tw32(RCVDBDI_STD_BD + TG3_BDINFO_NIC_ADDR,
6211              NIC_SRAM_RX_BUFFER_DESC);
6212
6213         /* Don't even try to program the JUMBO/MINI buffer descriptor
6214          * configs on 5705.
6215          */
6216         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
6217                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6218                      RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT);
6219         } else {
6220                 tw32(RCVDBDI_STD_BD + TG3_BDINFO_MAXLEN_FLAGS,
6221                      RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6222
6223                 tw32(RCVDBDI_MINI_BD + TG3_BDINFO_MAXLEN_FLAGS,
6224                      BDINFO_FLAGS_DISABLED);
6225
6226                 /* Setup replenish threshold. */
6227                 tw32(RCVBDI_JUMBO_THRESH, tp->rx_jumbo_pending / 8);
6228
6229                 if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) {
6230                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_HIGH,
6231                              ((u64) tp->rx_jumbo_mapping >> 32));
6232                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_HOST_ADDR + TG3_64BIT_REG_LOW,
6233                              ((u64) tp->rx_jumbo_mapping & 0xffffffff));
6234                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6235                              RX_JUMBO_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT);
6236                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_NIC_ADDR,
6237                              NIC_SRAM_RX_JUMBO_BUFFER_DESC);
6238                 } else {
6239                         tw32(RCVDBDI_JUMBO_BD + TG3_BDINFO_MAXLEN_FLAGS,
6240                              BDINFO_FLAGS_DISABLED);
6241                 }
6242
6243         }
6244
6245         /* There is only one send ring on 5705/5750, no need to explicitly
6246          * disable the others.
6247          */
6248         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6249                 /* Clear out send RCB ring in SRAM. */
6250                 for (i = NIC_SRAM_SEND_RCB; i < NIC_SRAM_RCV_RET_RCB; i += TG3_BDINFO_SIZE)
6251                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6252                                       BDINFO_FLAGS_DISABLED);
6253         }
6254
6255         tp->tx_prod = 0;
6256         tp->tx_cons = 0;
6257         tw32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6258         tw32_tx_mbox(MAILBOX_SNDNIC_PROD_IDX_0 + TG3_64BIT_REG_LOW, 0);
6259
6260         tg3_set_bdinfo(tp, NIC_SRAM_SEND_RCB,
6261                        tp->tx_desc_mapping,
6262                        (TG3_TX_RING_SIZE <<
6263                         BDINFO_FLAGS_MAXLEN_SHIFT),
6264                        NIC_SRAM_TX_BUFFER_DESC);
6265
6266         /* There is only one receive return ring on 5705/5750, no need
6267          * to explicitly disable the others.
6268          */
6269         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6270                 for (i = NIC_SRAM_RCV_RET_RCB; i < NIC_SRAM_STATS_BLK;
6271                      i += TG3_BDINFO_SIZE) {
6272                         tg3_write_mem(tp, i + TG3_BDINFO_MAXLEN_FLAGS,
6273                                       BDINFO_FLAGS_DISABLED);
6274                 }
6275         }
6276
6277         tp->rx_rcb_ptr = 0;
6278         tw32_rx_mbox(MAILBOX_RCVRET_CON_IDX_0 + TG3_64BIT_REG_LOW, 0);
6279
6280         tg3_set_bdinfo(tp, NIC_SRAM_RCV_RET_RCB,
6281                        tp->rx_rcb_mapping,
6282                        (TG3_RX_RCB_RING_SIZE(tp) <<
6283                         BDINFO_FLAGS_MAXLEN_SHIFT),
6284                        0);
6285
6286         tp->rx_std_ptr = tp->rx_pending;
6287         tw32_rx_mbox(MAILBOX_RCV_STD_PROD_IDX + TG3_64BIT_REG_LOW,
6288                      tp->rx_std_ptr);
6289
6290         tp->rx_jumbo_ptr = (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE) ?
6291                                                 tp->rx_jumbo_pending : 0;
6292         tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
6293                      tp->rx_jumbo_ptr);
6294
6295         /* Initialize MAC address and backoff seed. */
6296         __tg3_set_mac_addr(tp);
6297
6298         /* MTU + ethernet header + FCS + optional VLAN tag */
6299         tw32(MAC_RX_MTU_SIZE, tp->dev->mtu + ETH_HLEN + 8);
6300
6301         /* The slot time is changed by tg3_setup_phy if we
6302          * run at gigabit with half duplex.
6303          */
6304         tw32(MAC_TX_LENGTHS,
6305              (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
6306              (6 << TX_LENGTHS_IPG_SHIFT) |
6307              (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
6308
6309         /* Receive rules. */
6310         tw32(MAC_RCV_RULE_CFG, RCV_RULE_CFG_DEFAULT_CLASS);
6311         tw32(RCVLPC_CONFIG, 0x0181);
6312
6313         /* Calculate RDMAC_MODE setting early, we need it to determine
6314          * the RCVLPC_STATE_ENABLE mask.
6315          */
6316         rdmac_mode = (RDMAC_MODE_ENABLE | RDMAC_MODE_TGTABORT_ENAB |
6317                       RDMAC_MODE_MSTABORT_ENAB | RDMAC_MODE_PARITYERR_ENAB |
6318                       RDMAC_MODE_ADDROFLOW_ENAB | RDMAC_MODE_FIFOOFLOW_ENAB |
6319                       RDMAC_MODE_FIFOURUN_ENAB | RDMAC_MODE_FIFOOREAD_ENAB |
6320                       RDMAC_MODE_LNGREAD_ENAB);
6321         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6322                 rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
6323
6324         /* If statement applies to 5705 and 5750 PCI devices only */
6325         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6326              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6327             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
6328                 if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
6329                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6330                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6331                         rdmac_mode |= RDMAC_MODE_FIFO_SIZE_128;
6332                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6333                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788)) {
6334                         rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6335                 }
6336         }
6337
6338         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)
6339                 rdmac_mode |= RDMAC_MODE_FIFO_LONG_BURST;
6340
6341         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6342                 rdmac_mode |= (1 << 27);
6343
6344         /* Receive/send statistics. */
6345         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
6346                 val = tr32(RCVLPC_STATS_ENABLE);
6347                 val &= ~RCVLPC_STATSENAB_DACK_FIX;
6348                 tw32(RCVLPC_STATS_ENABLE, val);
6349         } else if ((rdmac_mode & RDMAC_MODE_FIFO_SIZE_128) &&
6350                    (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
6351                 val = tr32(RCVLPC_STATS_ENABLE);
6352                 val &= ~RCVLPC_STATSENAB_LNGBRST_RFIX;
6353                 tw32(RCVLPC_STATS_ENABLE, val);
6354         } else {
6355                 tw32(RCVLPC_STATS_ENABLE, 0xffffff);
6356         }
6357         tw32(RCVLPC_STATSCTRL, RCVLPC_STATSCTRL_ENABLE);
6358         tw32(SNDDATAI_STATSENAB, 0xffffff);
6359         tw32(SNDDATAI_STATSCTRL,
6360              (SNDDATAI_SCTRL_ENABLE |
6361               SNDDATAI_SCTRL_FASTUPD));
6362
6363         /* Setup host coalescing engine. */
6364         tw32(HOSTCC_MODE, 0);
6365         for (i = 0; i < 2000; i++) {
6366                 if (!(tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE))
6367                         break;
6368                 udelay(10);
6369         }
6370
6371         __tg3_set_coalesce(tp, &tp->coal);
6372
6373         /* set status block DMA address */
6374         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6375              ((u64) tp->status_mapping >> 32));
6376         tw32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6377              ((u64) tp->status_mapping & 0xffffffff));
6378
6379         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6380                 /* Status/statistics block address.  See tg3_timer,
6381                  * the tg3_periodic_fetch_stats call there, and
6382                  * tg3_get_stats to see how this works for 5705/5750 chips.
6383                  */
6384                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH,
6385                      ((u64) tp->stats_mapping >> 32));
6386                 tw32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW,
6387                      ((u64) tp->stats_mapping & 0xffffffff));
6388                 tw32(HOSTCC_STATS_BLK_NIC_ADDR, NIC_SRAM_STATS_BLK);
6389                 tw32(HOSTCC_STATUS_BLK_NIC_ADDR, NIC_SRAM_STATUS_BLK);
6390         }
6391
6392         tw32(HOSTCC_MODE, HOSTCC_MODE_ENABLE | tp->coalesce_mode);
6393
6394         tw32(RCVCC_MODE, RCVCC_MODE_ENABLE | RCVCC_MODE_ATTN_ENABLE);
6395         tw32(RCVLPC_MODE, RCVLPC_MODE_ENABLE);
6396         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6397                 tw32(RCVLSC_MODE, RCVLSC_MODE_ENABLE | RCVLSC_MODE_ATTN_ENABLE);
6398
6399         /* Clear statistics/status block in chip, and status block in ram. */
6400         for (i = NIC_SRAM_STATS_BLK;
6401              i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
6402              i += sizeof(u32)) {
6403                 tg3_write_mem(tp, i, 0);
6404                 udelay(40);
6405         }
6406         memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
6407
6408         if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
6409                 tp->tg3_flags2 &= ~TG3_FLG2_PARALLEL_DETECT;
6410                 /* reset to prevent losing 1st rx packet intermittently */
6411                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6412                 udelay(10);
6413         }
6414
6415         tp->mac_mode = MAC_MODE_TXSTAT_ENABLE | MAC_MODE_RXSTAT_ENABLE |
6416                 MAC_MODE_TDE_ENABLE | MAC_MODE_RDE_ENABLE | MAC_MODE_FHDE_ENABLE;
6417         tw32_f(MAC_MODE, tp->mac_mode | MAC_MODE_RXSTAT_CLEAR | MAC_MODE_TXSTAT_CLEAR);
6418         udelay(40);
6419
6420         /* tp->grc_local_ctrl is partially set up during tg3_get_invariants().
6421          * If TG3_FLG2_IS_NIC is zero, we should read the
6422          * register to preserve the GPIO settings for LOMs. The GPIOs,
6423          * whether used as inputs or outputs, are set by boot code after
6424          * reset.
6425          */
6426         if (!(tp->tg3_flags2 & TG3_FLG2_IS_NIC)) {
6427                 u32 gpio_mask;
6428
6429                 gpio_mask = GRC_LCLCTRL_GPIO_OE0 | GRC_LCLCTRL_GPIO_OE1 |
6430                             GRC_LCLCTRL_GPIO_OE2 | GRC_LCLCTRL_GPIO_OUTPUT0 |
6431                             GRC_LCLCTRL_GPIO_OUTPUT1 | GRC_LCLCTRL_GPIO_OUTPUT2;
6432
6433                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
6434                         gpio_mask |= GRC_LCLCTRL_GPIO_OE3 |
6435                                      GRC_LCLCTRL_GPIO_OUTPUT3;
6436
6437                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6438                         gpio_mask |= GRC_LCLCTRL_GPIO_UART_SEL;
6439
6440                 tp->grc_local_ctrl |= tr32(GRC_LOCAL_CTRL) & gpio_mask;
6441
6442                 /* GPIO1 must be driven high for eeprom write protect */
6443                 if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT)
6444                         tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
6445                                                GRC_LCLCTRL_GPIO_OUTPUT1);
6446         }
6447         tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6448         udelay(100);
6449
6450         tw32_mailbox_f(MAILBOX_INTERRUPT_0 + TG3_64BIT_REG_LOW, 0);
6451         tp->last_tag = 0;
6452
6453         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
6454                 tw32_f(DMAC_MODE, DMAC_MODE_ENABLE);
6455                 udelay(40);
6456         }
6457
6458         val = (WDMAC_MODE_ENABLE | WDMAC_MODE_TGTABORT_ENAB |
6459                WDMAC_MODE_MSTABORT_ENAB | WDMAC_MODE_PARITYERR_ENAB |
6460                WDMAC_MODE_ADDROFLOW_ENAB | WDMAC_MODE_FIFOOFLOW_ENAB |
6461                WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
6462                WDMAC_MODE_LNGREAD_ENAB);
6463
6464         /* If statement applies to 5705 and 5750 PCI devices only */
6465         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
6466              tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
6467             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
6468                 if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
6469                     (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
6470                      tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
6471                         /* nothing */
6472                 } else if (!(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH) &&
6473                            !(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
6474                            !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
6475                         val |= WDMAC_MODE_RX_ACCEL;
6476                 }
6477         }
6478
6479         /* Enable host coalescing bug fix */
6480         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755) ||
6481             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787))
6482                 val |= (1 << 29);
6483
6484         tw32_f(WDMAC_MODE, val);
6485         udelay(40);
6486
6487         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0) {
6488                 val = tr32(TG3PCI_X_CAPS);
6489                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703) {
6490                         val &= ~PCIX_CAPS_BURST_MASK;
6491                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6492                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
6493                         val &= ~(PCIX_CAPS_SPLIT_MASK | PCIX_CAPS_BURST_MASK);
6494                         val |= (PCIX_CAPS_MAX_BURST_CPIOB << PCIX_CAPS_BURST_SHIFT);
6495                         if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
6496                                 val |= (tp->split_mode_max_reqs <<
6497                                         PCIX_CAPS_SPLIT_SHIFT);
6498                 }
6499                 tw32(TG3PCI_X_CAPS, val);
6500         }
6501
6502         tw32_f(RDMAC_MODE, rdmac_mode);
6503         udelay(40);
6504
6505         tw32(RCVDCC_MODE, RCVDCC_MODE_ENABLE | RCVDCC_MODE_ATTN_ENABLE);
6506         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
6507                 tw32(MBFREE_MODE, MBFREE_MODE_ENABLE);
6508         tw32(SNDDATAC_MODE, SNDDATAC_MODE_ENABLE);
6509         tw32(SNDBDC_MODE, SNDBDC_MODE_ENABLE | SNDBDC_MODE_ATTN_ENABLE);
6510         tw32(RCVBDI_MODE, RCVBDI_MODE_ENABLE | RCVBDI_MODE_RCB_ATTN_ENAB);
6511         tw32(RCVDBDI_MODE, RCVDBDI_MODE_ENABLE | RCVDBDI_MODE_INV_RING_SZ);
6512         tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE);
6513         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO)
6514                 tw32(SNDDATAI_MODE, SNDDATAI_MODE_ENABLE | 0x8);
6515         tw32(SNDBDI_MODE, SNDBDI_MODE_ENABLE | SNDBDI_MODE_ATTN_ENABLE);
6516         tw32(SNDBDS_MODE, SNDBDS_MODE_ENABLE | SNDBDS_MODE_ATTN_ENABLE);
6517
6518         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0) {
6519                 err = tg3_load_5701_a0_firmware_fix(tp);
6520                 if (err)
6521                         return err;
6522         }
6523
6524         if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) {
6525                 err = tg3_load_tso_firmware(tp);
6526                 if (err)
6527                         return err;
6528         }
6529
6530         tp->tx_mode = TX_MODE_ENABLE;
6531         tw32_f(MAC_TX_MODE, tp->tx_mode);
6532         udelay(100);
6533
6534         tp->rx_mode = RX_MODE_ENABLE;
6535         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
6536                 tp->rx_mode |= RX_MODE_IPV6_CSUM_ENABLE;
6537
6538         tw32_f(MAC_RX_MODE, tp->rx_mode);
6539         udelay(10);
6540
6541         if (tp->link_config.phy_is_low_power) {
6542                 tp->link_config.phy_is_low_power = 0;
6543                 tp->link_config.speed = tp->link_config.orig_speed;
6544                 tp->link_config.duplex = tp->link_config.orig_duplex;
6545                 tp->link_config.autoneg = tp->link_config.orig_autoneg;
6546         }
6547
6548         tp->mi_mode = MAC_MI_MODE_BASE;
6549         tw32_f(MAC_MI_MODE, tp->mi_mode);
6550         udelay(80);
6551
6552         tw32(MAC_LED_CTRL, tp->led_ctrl);
6553
6554         tw32(MAC_MI_STAT, MAC_MI_STAT_LNKSTAT_ATTN_ENAB);
6555         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6556                 tw32_f(MAC_RX_MODE, RX_MODE_RESET);
6557                 udelay(10);
6558         }
6559         tw32_f(MAC_RX_MODE, tp->rx_mode);
6560         udelay(10);
6561
6562         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
6563                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) &&
6564                         !(tp->tg3_flags2 & TG3_FLG2_SERDES_PREEMPHASIS)) {
6565                         /* Set drive transmission level to 1.2V  */
6566                         /* only if the signal pre-emphasis bit is not set  */
6567                         val = tr32(MAC_SERDES_CFG);
6568                         val &= 0xfffff000;
6569                         val |= 0x880;
6570                         tw32(MAC_SERDES_CFG, val);
6571                 }
6572                 if (tp->pci_chip_rev_id == CHIPREV_ID_5703_A1)
6573                         tw32(MAC_SERDES_CFG, 0x616000);
6574         }
6575
6576         /* Prevent chip from dropping frames when flow control
6577          * is enabled.
6578          */
6579         tw32_f(MAC_LOW_WMARK_MAX_RX_FRAME, 2);
6580
6581         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
6582             (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
6583                 /* Use hardware link auto-negotiation */
6584                 tp->tg3_flags2 |= TG3_FLG2_HW_AUTONEG;
6585         }
6586
6587         if ((tp->tg3_flags2 & TG3_FLG2_MII_SERDES) &&
6588             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
6589                 u32 tmp;
6590
6591                 tmp = tr32(SERDES_RX_CTRL);
6592                 tw32(SERDES_RX_CTRL, tmp | SERDES_RX_SIG_DETECT);
6593                 tp->grc_local_ctrl &= ~GRC_LCLCTRL_USE_EXT_SIG_DETECT;
6594                 tp->grc_local_ctrl |= GRC_LCLCTRL_USE_SIG_DETECT;
6595                 tw32(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
6596         }
6597
6598         err = tg3_setup_phy(tp, 0);
6599         if (err)
6600                 return err;
6601
6602         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
6603             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906) {
6604                 u32 tmp;
6605
6606                 /* Clear CRC stats. */
6607                 if (!tg3_readphy(tp, MII_TG3_TEST1, &tmp)) {
6608                         tg3_writephy(tp, MII_TG3_TEST1,
6609                                      tmp | MII_TG3_TEST1_CRC_EN);
6610                         tg3_readphy(tp, 0x14, &tmp);
6611                 }
6612         }
6613
6614         __tg3_set_rx_mode(tp->dev);
6615
6616         /* Initialize receive rules. */
6617         tw32(MAC_RCV_RULE_0,  0xc2000000 & RCV_RULE_DISABLE_MASK);
6618         tw32(MAC_RCV_VALUE_0, 0xffffffff & RCV_RULE_DISABLE_MASK);
6619         tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);
6620         tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);
6621
6622         if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
6623             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
6624                 limit = 8;
6625         else
6626                 limit = 16;
6627         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF)
6628                 limit -= 4;
6629         switch (limit) {
6630         case 16:
6631                 tw32(MAC_RCV_RULE_15,  0); tw32(MAC_RCV_VALUE_15,  0);
6632         case 15:
6633                 tw32(MAC_RCV_RULE_14,  0); tw32(MAC_RCV_VALUE_14,  0);
6634         case 14:
6635                 tw32(MAC_RCV_RULE_13,  0); tw32(MAC_RCV_VALUE_13,  0);
6636         case 13:
6637                 tw32(MAC_RCV_RULE_12,  0); tw32(MAC_RCV_VALUE_12,  0);
6638         case 12:
6639                 tw32(MAC_RCV_RULE_11,  0); tw32(MAC_RCV_VALUE_11,  0);
6640         case 11:
6641                 tw32(MAC_RCV_RULE_10,  0); tw32(MAC_RCV_VALUE_10,  0);
6642         case 10:
6643                 tw32(MAC_RCV_RULE_9,  0); tw32(MAC_RCV_VALUE_9,  0);
6644         case 9:
6645                 tw32(MAC_RCV_RULE_8,  0); tw32(MAC_RCV_VALUE_8,  0);
6646         case 8:
6647                 tw32(MAC_RCV_RULE_7,  0); tw32(MAC_RCV_VALUE_7,  0);
6648         case 7:
6649                 tw32(MAC_RCV_RULE_6,  0); tw32(MAC_RCV_VALUE_6,  0);
6650         case 6:
6651                 tw32(MAC_RCV_RULE_5,  0); tw32(MAC_RCV_VALUE_5,  0);
6652         case 5:
6653                 tw32(MAC_RCV_RULE_4,  0); tw32(MAC_RCV_VALUE_4,  0);
6654         case 4:
6655                 /* tw32(MAC_RCV_RULE_3,  0); tw32(MAC_RCV_VALUE_3,  0); */
6656         case 3:
6657                 /* tw32(MAC_RCV_RULE_2,  0); tw32(MAC_RCV_VALUE_2,  0); */
6658         case 2:
6659         case 1:
6660
6661         default:
6662                 break;
6663         };
6664
6665         tg3_write_sig_post_reset(tp, RESET_KIND_INIT);
6666
6667         return 0;
6668 }
6669
6670 /* Called at device open time to get the chip ready for
6671  * packet processing.  Invoked with tp->lock held.
6672  */
6673 static int tg3_init_hw(struct tg3 *tp, int reset_phy)
6674 {
6675         int err;
6676
6677         /* Force the chip into D0. */
6678         err = tg3_set_power_state(tp, PCI_D0);
6679         if (err)
6680                 goto out;
6681
6682         tg3_switch_clocks(tp);
6683
6684         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
6685
6686         err = tg3_reset_hw(tp, reset_phy);
6687
6688 out:
6689         return err;
6690 }
6691
6692 #define TG3_STAT_ADD32(PSTAT, REG) \
6693 do {    u32 __val = tr32(REG); \
6694         (PSTAT)->low += __val; \
6695         if ((PSTAT)->low < __val) \
6696                 (PSTAT)->high += 1; \
6697 } while (0)
6698
6699 static void tg3_periodic_fetch_stats(struct tg3 *tp)
6700 {
6701         struct tg3_hw_stats *sp = tp->hw_stats;
6702
6703         if (!netif_carrier_ok(tp->dev))
6704                 return;
6705
6706         TG3_STAT_ADD32(&sp->tx_octets, MAC_TX_STATS_OCTETS);
6707         TG3_STAT_ADD32(&sp->tx_collisions, MAC_TX_STATS_COLLISIONS);
6708         TG3_STAT_ADD32(&sp->tx_xon_sent, MAC_TX_STATS_XON_SENT);
6709         TG3_STAT_ADD32(&sp->tx_xoff_sent, MAC_TX_STATS_XOFF_SENT);
6710         TG3_STAT_ADD32(&sp->tx_mac_errors, MAC_TX_STATS_MAC_ERRORS);
6711         TG3_STAT_ADD32(&sp->tx_single_collisions, MAC_TX_STATS_SINGLE_COLLISIONS);
6712         TG3_STAT_ADD32(&sp->tx_mult_collisions, MAC_TX_STATS_MULT_COLLISIONS);
6713         TG3_STAT_ADD32(&sp->tx_deferred, MAC_TX_STATS_DEFERRED);
6714         TG3_STAT_ADD32(&sp->tx_excessive_collisions, MAC_TX_STATS_EXCESSIVE_COL);
6715         TG3_STAT_ADD32(&sp->tx_late_collisions, MAC_TX_STATS_LATE_COL);
6716         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
6717         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
6718         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
6719
6720         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
6721         TG3_STAT_ADD32(&sp->rx_fragments, MAC_RX_STATS_FRAGMENTS);
6722         TG3_STAT_ADD32(&sp->rx_ucast_packets, MAC_RX_STATS_UCAST);
6723         TG3_STAT_ADD32(&sp->rx_mcast_packets, MAC_RX_STATS_MCAST);
6724         TG3_STAT_ADD32(&sp->rx_bcast_packets, MAC_RX_STATS_BCAST);
6725         TG3_STAT_ADD32(&sp->rx_fcs_errors, MAC_RX_STATS_FCS_ERRORS);
6726         TG3_STAT_ADD32(&sp->rx_align_errors, MAC_RX_STATS_ALIGN_ERRORS);
6727         TG3_STAT_ADD32(&sp->rx_xon_pause_rcvd, MAC_RX_STATS_XON_PAUSE_RECVD);
6728         TG3_STAT_ADD32(&sp->rx_xoff_pause_rcvd, MAC_RX_STATS_XOFF_PAUSE_RECVD);
6729         TG3_STAT_ADD32(&sp->rx_mac_ctrl_rcvd, MAC_RX_STATS_MAC_CTRL_RECVD);
6730         TG3_STAT_ADD32(&sp->rx_xoff_entered, MAC_RX_STATS_XOFF_ENTERED);
6731         TG3_STAT_ADD32(&sp->rx_frame_too_long_errors, MAC_RX_STATS_FRAME_TOO_LONG);
6732         TG3_STAT_ADD32(&sp->rx_jabbers, MAC_RX_STATS_JABBERS);
6733         TG3_STAT_ADD32(&sp->rx_undersize_packets, MAC_RX_STATS_UNDERSIZE);
6734
6735         TG3_STAT_ADD32(&sp->rxbds_empty, RCVLPC_NO_RCV_BD_CNT);
6736         TG3_STAT_ADD32(&sp->rx_discards, RCVLPC_IN_DISCARDS_CNT);
6737         TG3_STAT_ADD32(&sp->rx_errors, RCVLPC_IN_ERRORS_CNT);
6738 }
6739
6740 static void tg3_timer(unsigned long __opaque)
6741 {
6742         struct tg3 *tp = (struct tg3 *) __opaque;
6743
6744         if (tp->irq_sync)
6745                 goto restart_timer;
6746
6747         spin_lock(&tp->lock);
6748
6749         if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
6750                 /* All of this garbage is because when using non-tagged
6751                  * IRQ status the mailbox/status_block protocol the chip
6752                  * uses with the cpu is race prone.
6753                  */
6754                 if (tp->hw_status->status & SD_STATUS_UPDATED) {
6755                         tw32(GRC_LOCAL_CTRL,
6756                              tp->grc_local_ctrl | GRC_LCLCTRL_SETINT);
6757                 } else {
6758                         tw32(HOSTCC_MODE, tp->coalesce_mode |
6759                              (HOSTCC_MODE_ENABLE | HOSTCC_MODE_NOW));
6760                 }
6761
6762                 if (!(tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
6763                         tp->tg3_flags2 |= TG3_FLG2_RESTART_TIMER;
6764                         spin_unlock(&tp->lock);
6765                         schedule_work(&tp->reset_task);
6766                         return;
6767                 }
6768         }
6769
6770         /* This part only runs once per second. */
6771         if (!--tp->timer_counter) {
6772                 if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
6773                         tg3_periodic_fetch_stats(tp);
6774
6775                 if (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) {
6776                         u32 mac_stat;
6777                         int phy_event;
6778
6779                         mac_stat = tr32(MAC_STATUS);
6780
6781                         phy_event = 0;
6782                         if (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) {
6783                                 if (mac_stat & MAC_STATUS_MI_INTERRUPT)
6784                                         phy_event = 1;
6785                         } else if (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)
6786                                 phy_event = 1;
6787
6788                         if (phy_event)
6789                                 tg3_setup_phy(tp, 0);
6790                 } else if (tp->tg3_flags & TG3_FLAG_POLL_SERDES) {
6791                         u32 mac_stat = tr32(MAC_STATUS);
6792                         int need_setup = 0;
6793
6794                         if (netif_carrier_ok(tp->dev) &&
6795                             (mac_stat & MAC_STATUS_LNKSTATE_CHANGED)) {
6796                                 need_setup = 1;
6797                         }
6798                         if (! netif_carrier_ok(tp->dev) &&
6799                             (mac_stat & (MAC_STATUS_PCS_SYNCED |
6800                                          MAC_STATUS_SIGNAL_DET))) {
6801                                 need_setup = 1;
6802                         }
6803                         if (need_setup) {
6804                                 if (!tp->serdes_counter) {
6805                                         tw32_f(MAC_MODE,
6806                                              (tp->mac_mode &
6807                                               ~MAC_MODE_PORT_MODE_MASK));
6808                                         udelay(40);
6809                                         tw32_f(MAC_MODE, tp->mac_mode);
6810                                         udelay(40);
6811                                 }
6812                                 tg3_setup_phy(tp, 0);
6813                         }
6814                 } else if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
6815                         tg3_serdes_parallel_detect(tp);
6816
6817                 tp->timer_counter = tp->timer_multiplier;
6818         }
6819
6820         /* Heartbeat is only sent once every 2 seconds.
6821          *
6822          * The heartbeat is to tell the ASF firmware that the host
6823          * driver is still alive.  In the event that the OS crashes,
6824          * ASF needs to reset the hardware to free up the FIFO space
6825          * that may be filled with rx packets destined for the host.
6826          * If the FIFO is full, ASF will no longer function properly.
6827          *
6828          * Unintended resets have been reported on real time kernels
6829          * where the timer doesn't run on time.  Netpoll will also have
6830          * same problem.
6831          *
6832          * The new FWCMD_NICDRV_ALIVE3 command tells the ASF firmware
6833          * to check the ring condition when the heartbeat is expiring
6834          * before doing the reset.  This will prevent most unintended
6835          * resets.
6836          */
6837         if (!--tp->asf_counter) {
6838                 if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
6839                         u32 val;
6840
6841                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX,
6842                                       FWCMD_NICDRV_ALIVE3);
6843                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 4);
6844                         /* 5 seconds timeout */
6845                         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, 5);
6846                         val = tr32(GRC_RX_CPU_EVENT);
6847                         val |= (1 << 14);
6848                         tw32(GRC_RX_CPU_EVENT, val);
6849                 }
6850                 tp->asf_counter = tp->asf_multiplier;
6851         }
6852
6853         spin_unlock(&tp->lock);
6854
6855 restart_timer:
6856         tp->timer.expires = jiffies + tp->timer_offset;
6857         add_timer(&tp->timer);
6858 }
6859
6860 static int tg3_request_irq(struct tg3 *tp)
6861 {
6862         irq_handler_t fn;
6863         unsigned long flags;
6864         struct net_device *dev = tp->dev;
6865
6866         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
6867                 fn = tg3_msi;
6868                 if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)
6869                         fn = tg3_msi_1shot;
6870                 flags = IRQF_SAMPLE_RANDOM;
6871         } else {
6872                 fn = tg3_interrupt;
6873                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
6874                         fn = tg3_interrupt_tagged;
6875                 flags = IRQF_SHARED | IRQF_SAMPLE_RANDOM;
6876         }
6877         return (request_irq(tp->pdev->irq, fn, flags, dev->name, dev));
6878 }
6879
6880 static int tg3_test_interrupt(struct tg3 *tp)
6881 {
6882         struct net_device *dev = tp->dev;
6883         int err, i, intr_ok = 0;
6884
6885         if (!netif_running(dev))
6886                 return -ENODEV;
6887
6888         tg3_disable_ints(tp);
6889
6890         free_irq(tp->pdev->irq, dev);
6891
6892         err = request_irq(tp->pdev->irq, tg3_test_isr,
6893                           IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
6894         if (err)
6895                 return err;
6896
6897         tp->hw_status->status &= ~SD_STATUS_UPDATED;
6898         tg3_enable_ints(tp);
6899
6900         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
6901                HOSTCC_MODE_NOW);
6902
6903         for (i = 0; i < 5; i++) {
6904                 u32 int_mbox, misc_host_ctrl;
6905
6906                 int_mbox = tr32_mailbox(MAILBOX_INTERRUPT_0 +
6907                                         TG3_64BIT_REG_LOW);
6908                 misc_host_ctrl = tr32(TG3PCI_MISC_HOST_CTRL);
6909
6910                 if ((int_mbox != 0) ||
6911                     (misc_host_ctrl & MISC_HOST_CTRL_MASK_PCI_INT)) {
6912                         intr_ok = 1;
6913                         break;
6914                 }
6915
6916                 msleep(10);
6917         }
6918
6919         tg3_disable_ints(tp);
6920
6921         free_irq(tp->pdev->irq, dev);
6922
6923         err = tg3_request_irq(tp);
6924
6925         if (err)
6926                 return err;
6927
6928         if (intr_ok)
6929                 return 0;
6930
6931         return -EIO;
6932 }
6933
6934 /* Returns 0 if MSI test succeeds or MSI test fails and INTx mode is
6935  * successfully restored
6936  */
6937 static int tg3_test_msi(struct tg3 *tp)
6938 {
6939         struct net_device *dev = tp->dev;
6940         int err;
6941         u16 pci_cmd;
6942
6943         if (!(tp->tg3_flags2 & TG3_FLG2_USING_MSI))
6944                 return 0;
6945
6946         /* Turn off SERR reporting in case MSI terminates with Master
6947          * Abort.
6948          */
6949         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
6950         pci_write_config_word(tp->pdev, PCI_COMMAND,
6951                               pci_cmd & ~PCI_COMMAND_SERR);
6952
6953         err = tg3_test_interrupt(tp);
6954
6955         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
6956
6957         if (!err)
6958                 return 0;
6959
6960         /* other failures */
6961         if (err != -EIO)
6962                 return err;
6963
6964         /* MSI test failed, go back to INTx mode */
6965         printk(KERN_WARNING PFX "%s: No interrupt was generated using MSI, "
6966                "switching to INTx mode. Please report this failure to "
6967                "the PCI maintainer and include system chipset information.\n",
6968                        tp->dev->name);
6969
6970         free_irq(tp->pdev->irq, dev);
6971         pci_disable_msi(tp->pdev);
6972
6973         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
6974
6975         err = tg3_request_irq(tp);
6976         if (err)
6977                 return err;
6978
6979         /* Need to reset the chip because the MSI cycle may have terminated
6980          * with Master Abort.
6981          */
6982         tg3_full_lock(tp, 1);
6983
6984         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
6985         err = tg3_init_hw(tp, 1);
6986
6987         tg3_full_unlock(tp);
6988
6989         if (err)
6990                 free_irq(tp->pdev->irq, dev);
6991
6992         return err;
6993 }
6994
6995 static int tg3_open(struct net_device *dev)
6996 {
6997         struct tg3 *tp = netdev_priv(dev);
6998         int err;
6999
7000         netif_carrier_off(tp->dev);
7001
7002         tg3_full_lock(tp, 0);
7003
7004         err = tg3_set_power_state(tp, PCI_D0);
7005         if (err) {
7006                 tg3_full_unlock(tp);
7007                 return err;
7008         }
7009
7010         tg3_disable_ints(tp);
7011         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
7012
7013         tg3_full_unlock(tp);
7014
7015         /* The placement of this call is tied
7016          * to the setup and use of Host TX descriptors.
7017          */
7018         err = tg3_alloc_consistent(tp);
7019         if (err)
7020                 return err;
7021
7022         if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
7023             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_AX) &&
7024             (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5750_BX) &&
7025             !((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) &&
7026               (tp->pdev_peer == tp->pdev))) {
7027                 /* All MSI supporting chips should support tagged
7028                  * status.  Assert that this is the case.
7029                  */
7030                 if (!(tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)) {
7031                         printk(KERN_WARNING PFX "%s: MSI without TAGGED? "
7032                                "Not using MSI.\n", tp->dev->name);
7033                 } else if (pci_enable_msi(tp->pdev) == 0) {
7034                         u32 msi_mode;
7035
7036                         msi_mode = tr32(MSGINT_MODE);
7037                         tw32(MSGINT_MODE, msi_mode | MSGINT_MODE_ENABLE);
7038                         tp->tg3_flags2 |= TG3_FLG2_USING_MSI;
7039                 }
7040         }
7041         err = tg3_request_irq(tp);
7042
7043         if (err) {
7044                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7045                         pci_disable_msi(tp->pdev);
7046                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7047                 }
7048                 tg3_free_consistent(tp);
7049                 return err;
7050         }
7051
7052         tg3_full_lock(tp, 0);
7053
7054         err = tg3_init_hw(tp, 1);
7055         if (err) {
7056                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7057                 tg3_free_rings(tp);
7058         } else {
7059                 if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS)
7060                         tp->timer_offset = HZ;
7061                 else
7062                         tp->timer_offset = HZ / 10;
7063
7064                 BUG_ON(tp->timer_offset > HZ);
7065                 tp->timer_counter = tp->timer_multiplier =
7066                         (HZ / tp->timer_offset);
7067                 tp->asf_counter = tp->asf_multiplier =
7068                         ((HZ / tp->timer_offset) * 2);
7069
7070                 init_timer(&tp->timer);
7071                 tp->timer.expires = jiffies + tp->timer_offset;
7072                 tp->timer.data = (unsigned long) tp;
7073                 tp->timer.function = tg3_timer;
7074         }
7075
7076         tg3_full_unlock(tp);
7077
7078         if (err) {
7079                 free_irq(tp->pdev->irq, dev);
7080                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7081                         pci_disable_msi(tp->pdev);
7082                         tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7083                 }
7084                 tg3_free_consistent(tp);
7085                 return err;
7086         }
7087
7088         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7089                 err = tg3_test_msi(tp);
7090
7091                 if (err) {
7092                         tg3_full_lock(tp, 0);
7093
7094                         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7095                                 pci_disable_msi(tp->pdev);
7096                                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7097                         }
7098                         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7099                         tg3_free_rings(tp);
7100                         tg3_free_consistent(tp);
7101
7102                         tg3_full_unlock(tp);
7103
7104                         return err;
7105                 }
7106
7107                 if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7108                         if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
7109                                 u32 val = tr32(PCIE_TRANSACTION_CFG);
7110
7111                                 tw32(PCIE_TRANSACTION_CFG,
7112                                      val | PCIE_TRANS_CFG_1SHOT_MSI);
7113                         }
7114                 }
7115         }
7116
7117         tg3_full_lock(tp, 0);
7118
7119         add_timer(&tp->timer);
7120         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
7121         tg3_enable_ints(tp);
7122
7123         tg3_full_unlock(tp);
7124
7125         netif_start_queue(dev);
7126
7127         return 0;
7128 }
7129
7130 #if 0
7131 /*static*/ void tg3_dump_state(struct tg3 *tp)
7132 {
7133         u32 val32, val32_2, val32_3, val32_4, val32_5;
7134         u16 val16;
7135         int i;
7136
7137         pci_read_config_word(tp->pdev, PCI_STATUS, &val16);
7138         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE, &val32);
7139         printk("DEBUG: PCI status [%04x] TG3PCI state[%08x]\n",
7140                val16, val32);
7141
7142         /* MAC block */
7143         printk("DEBUG: MAC_MODE[%08x] MAC_STATUS[%08x]\n",
7144                tr32(MAC_MODE), tr32(MAC_STATUS));
7145         printk("       MAC_EVENT[%08x] MAC_LED_CTRL[%08x]\n",
7146                tr32(MAC_EVENT), tr32(MAC_LED_CTRL));
7147         printk("DEBUG: MAC_TX_MODE[%08x] MAC_TX_STATUS[%08x]\n",
7148                tr32(MAC_TX_MODE), tr32(MAC_TX_STATUS));
7149         printk("       MAC_RX_MODE[%08x] MAC_RX_STATUS[%08x]\n",
7150                tr32(MAC_RX_MODE), tr32(MAC_RX_STATUS));
7151
7152         /* Send data initiator control block */
7153         printk("DEBUG: SNDDATAI_MODE[%08x] SNDDATAI_STATUS[%08x]\n",
7154                tr32(SNDDATAI_MODE), tr32(SNDDATAI_STATUS));
7155         printk("       SNDDATAI_STATSCTRL[%08x]\n",
7156                tr32(SNDDATAI_STATSCTRL));
7157
7158         /* Send data completion control block */
7159         printk("DEBUG: SNDDATAC_MODE[%08x]\n", tr32(SNDDATAC_MODE));
7160
7161         /* Send BD ring selector block */
7162         printk("DEBUG: SNDBDS_MODE[%08x] SNDBDS_STATUS[%08x]\n",
7163                tr32(SNDBDS_MODE), tr32(SNDBDS_STATUS));
7164
7165         /* Send BD initiator control block */
7166         printk("DEBUG: SNDBDI_MODE[%08x] SNDBDI_STATUS[%08x]\n",
7167                tr32(SNDBDI_MODE), tr32(SNDBDI_STATUS));
7168
7169         /* Send BD completion control block */
7170         printk("DEBUG: SNDBDC_MODE[%08x]\n", tr32(SNDBDC_MODE));
7171
7172         /* Receive list placement control block */
7173         printk("DEBUG: RCVLPC_MODE[%08x] RCVLPC_STATUS[%08x]\n",
7174                tr32(RCVLPC_MODE), tr32(RCVLPC_STATUS));
7175         printk("       RCVLPC_STATSCTRL[%08x]\n",
7176                tr32(RCVLPC_STATSCTRL));
7177
7178         /* Receive data and receive BD initiator control block */
7179         printk("DEBUG: RCVDBDI_MODE[%08x] RCVDBDI_STATUS[%08x]\n",
7180                tr32(RCVDBDI_MODE), tr32(RCVDBDI_STATUS));
7181
7182         /* Receive data completion control block */
7183         printk("DEBUG: RCVDCC_MODE[%08x]\n",
7184                tr32(RCVDCC_MODE));
7185
7186         /* Receive BD initiator control block */
7187         printk("DEBUG: RCVBDI_MODE[%08x] RCVBDI_STATUS[%08x]\n",
7188                tr32(RCVBDI_MODE), tr32(RCVBDI_STATUS));
7189
7190         /* Receive BD completion control block */
7191         printk("DEBUG: RCVCC_MODE[%08x] RCVCC_STATUS[%08x]\n",
7192                tr32(RCVCC_MODE), tr32(RCVCC_STATUS));
7193
7194         /* Receive list selector control block */
7195         printk("DEBUG: RCVLSC_MODE[%08x] RCVLSC_STATUS[%08x]\n",
7196                tr32(RCVLSC_MODE), tr32(RCVLSC_STATUS));
7197
7198         /* Mbuf cluster free block */
7199         printk("DEBUG: MBFREE_MODE[%08x] MBFREE_STATUS[%08x]\n",
7200                tr32(MBFREE_MODE), tr32(MBFREE_STATUS));
7201
7202         /* Host coalescing control block */
7203         printk("DEBUG: HOSTCC_MODE[%08x] HOSTCC_STATUS[%08x]\n",
7204                tr32(HOSTCC_MODE), tr32(HOSTCC_STATUS));
7205         printk("DEBUG: HOSTCC_STATS_BLK_HOST_ADDR[%08x%08x]\n",
7206                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7207                tr32(HOSTCC_STATS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7208         printk("DEBUG: HOSTCC_STATUS_BLK_HOST_ADDR[%08x%08x]\n",
7209                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_HIGH),
7210                tr32(HOSTCC_STATUS_BLK_HOST_ADDR + TG3_64BIT_REG_LOW));
7211         printk("DEBUG: HOSTCC_STATS_BLK_NIC_ADDR[%08x]\n",
7212                tr32(HOSTCC_STATS_BLK_NIC_ADDR));
7213         printk("DEBUG: HOSTCC_STATUS_BLK_NIC_ADDR[%08x]\n",
7214                tr32(HOSTCC_STATUS_BLK_NIC_ADDR));
7215
7216         /* Memory arbiter control block */
7217         printk("DEBUG: MEMARB_MODE[%08x] MEMARB_STATUS[%08x]\n",
7218                tr32(MEMARB_MODE), tr32(MEMARB_STATUS));
7219
7220         /* Buffer manager control block */
7221         printk("DEBUG: BUFMGR_MODE[%08x] BUFMGR_STATUS[%08x]\n",
7222                tr32(BUFMGR_MODE), tr32(BUFMGR_STATUS));
7223         printk("DEBUG: BUFMGR_MB_POOL_ADDR[%08x] BUFMGR_MB_POOL_SIZE[%08x]\n",
7224                tr32(BUFMGR_MB_POOL_ADDR), tr32(BUFMGR_MB_POOL_SIZE));
7225         printk("DEBUG: BUFMGR_DMA_DESC_POOL_ADDR[%08x] "
7226                "BUFMGR_DMA_DESC_POOL_SIZE[%08x]\n",
7227                tr32(BUFMGR_DMA_DESC_POOL_ADDR),
7228                tr32(BUFMGR_DMA_DESC_POOL_SIZE));
7229
7230         /* Read DMA control block */
7231         printk("DEBUG: RDMAC_MODE[%08x] RDMAC_STATUS[%08x]\n",
7232                tr32(RDMAC_MODE), tr32(RDMAC_STATUS));
7233
7234         /* Write DMA control block */
7235         printk("DEBUG: WDMAC_MODE[%08x] WDMAC_STATUS[%08x]\n",
7236                tr32(WDMAC_MODE), tr32(WDMAC_STATUS));
7237
7238         /* DMA completion block */
7239         printk("DEBUG: DMAC_MODE[%08x]\n",
7240                tr32(DMAC_MODE));
7241
7242         /* GRC block */
7243         printk("DEBUG: GRC_MODE[%08x] GRC_MISC_CFG[%08x]\n",
7244                tr32(GRC_MODE), tr32(GRC_MISC_CFG));
7245         printk("DEBUG: GRC_LOCAL_CTRL[%08x]\n",
7246                tr32(GRC_LOCAL_CTRL));
7247
7248         /* TG3_BDINFOs */
7249         printk("DEBUG: RCVDBDI_JUMBO_BD[%08x%08x:%08x:%08x]\n",
7250                tr32(RCVDBDI_JUMBO_BD + 0x0),
7251                tr32(RCVDBDI_JUMBO_BD + 0x4),
7252                tr32(RCVDBDI_JUMBO_BD + 0x8),
7253                tr32(RCVDBDI_JUMBO_BD + 0xc));
7254         printk("DEBUG: RCVDBDI_STD_BD[%08x%08x:%08x:%08x]\n",
7255                tr32(RCVDBDI_STD_BD + 0x0),
7256                tr32(RCVDBDI_STD_BD + 0x4),
7257                tr32(RCVDBDI_STD_BD + 0x8),
7258                tr32(RCVDBDI_STD_BD + 0xc));
7259         printk("DEBUG: RCVDBDI_MINI_BD[%08x%08x:%08x:%08x]\n",
7260                tr32(RCVDBDI_MINI_BD + 0x0),
7261                tr32(RCVDBDI_MINI_BD + 0x4),
7262                tr32(RCVDBDI_MINI_BD + 0x8),
7263                tr32(RCVDBDI_MINI_BD + 0xc));
7264
7265         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x0, &val32);
7266         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x4, &val32_2);
7267         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0x8, &val32_3);
7268         tg3_read_mem(tp, NIC_SRAM_SEND_RCB + 0xc, &val32_4);
7269         printk("DEBUG: SRAM_SEND_RCB_0[%08x%08x:%08x:%08x]\n",
7270                val32, val32_2, val32_3, val32_4);
7271
7272         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x0, &val32);
7273         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x4, &val32_2);
7274         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0x8, &val32_3);
7275         tg3_read_mem(tp, NIC_SRAM_RCV_RET_RCB + 0xc, &val32_4);
7276         printk("DEBUG: SRAM_RCV_RET_RCB_0[%08x%08x:%08x:%08x]\n",
7277                val32, val32_2, val32_3, val32_4);
7278
7279         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x0, &val32);
7280         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x4, &val32_2);
7281         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x8, &val32_3);
7282         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0xc, &val32_4);
7283         tg3_read_mem(tp, NIC_SRAM_STATUS_BLK + 0x10, &val32_5);
7284         printk("DEBUG: SRAM_STATUS_BLK[%08x:%08x:%08x:%08x:%08x]\n",
7285                val32, val32_2, val32_3, val32_4, val32_5);
7286
7287         /* SW status block */
7288         printk("DEBUG: Host status block [%08x:%08x:(%04x:%04x:%04x):(%04x:%04x)]\n",
7289                tp->hw_status->status,
7290                tp->hw_status->status_tag,
7291                tp->hw_status->rx_jumbo_consumer,
7292                tp->hw_status->rx_consumer,
7293                tp->hw_status->rx_mini_consumer,
7294                tp->hw_status->idx[0].rx_producer,
7295                tp->hw_status->idx[0].tx_consumer);
7296
7297         /* SW statistics block */
7298         printk("DEBUG: Host statistics block [%08x:%08x:%08x:%08x]\n",
7299                ((u32 *)tp->hw_stats)[0],
7300                ((u32 *)tp->hw_stats)[1],
7301                ((u32 *)tp->hw_stats)[2],
7302                ((u32 *)tp->hw_stats)[3]);
7303
7304         /* Mailboxes */
7305         printk("DEBUG: SNDHOST_PROD[%08x%08x] SNDNIC_PROD[%08x%08x]\n",
7306                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x0),
7307                tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + 0x4),
7308                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x0),
7309                tr32_mailbox(MAILBOX_SNDNIC_PROD_IDX_0 + 0x4));
7310
7311         /* NIC side send descriptors. */
7312         for (i = 0; i < 6; i++) {
7313                 unsigned long txd;
7314
7315                 txd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_TX_BUFFER_DESC
7316                         + (i * sizeof(struct tg3_tx_buffer_desc));
7317                 printk("DEBUG: NIC TXD(%d)[%08x:%08x:%08x:%08x]\n",
7318                        i,
7319                        readl(txd + 0x0), readl(txd + 0x4),
7320                        readl(txd + 0x8), readl(txd + 0xc));
7321         }
7322
7323         /* NIC side RX descriptors. */
7324         for (i = 0; i < 6; i++) {
7325                 unsigned long rxd;
7326
7327                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_BUFFER_DESC
7328                         + (i * sizeof(struct tg3_rx_buffer_desc));
7329                 printk("DEBUG: NIC RXD_STD(%d)[0][%08x:%08x:%08x:%08x]\n",
7330                        i,
7331                        readl(rxd + 0x0), readl(rxd + 0x4),
7332                        readl(rxd + 0x8), readl(rxd + 0xc));
7333                 rxd += (4 * sizeof(u32));
7334                 printk("DEBUG: NIC RXD_STD(%d)[1][%08x:%08x:%08x:%08x]\n",
7335                        i,
7336                        readl(rxd + 0x0), readl(rxd + 0x4),
7337                        readl(rxd + 0x8), readl(rxd + 0xc));
7338         }
7339
7340         for (i = 0; i < 6; i++) {
7341                 unsigned long rxd;
7342
7343                 rxd = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_RX_JUMBO_BUFFER_DESC
7344                         + (i * sizeof(struct tg3_rx_buffer_desc));
7345                 printk("DEBUG: NIC RXD_JUMBO(%d)[0][%08x:%08x:%08x:%08x]\n",
7346                        i,
7347                        readl(rxd + 0x0), readl(rxd + 0x4),
7348                        readl(rxd + 0x8), readl(rxd + 0xc));
7349                 rxd += (4 * sizeof(u32));
7350                 printk("DEBUG: NIC RXD_JUMBO(%d)[1][%08x:%08x:%08x:%08x]\n",
7351                        i,
7352                        readl(rxd + 0x0), readl(rxd + 0x4),
7353                        readl(rxd + 0x8), readl(rxd + 0xc));
7354         }
7355 }
7356 #endif
7357
7358 static struct net_device_stats *tg3_get_stats(struct net_device *);
7359 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *);
7360
7361 static int tg3_close(struct net_device *dev)
7362 {
7363         struct tg3 *tp = netdev_priv(dev);
7364
7365         /* Calling flush_scheduled_work() may deadlock because
7366          * linkwatch_event() may be on the workqueue and it will try to get
7367          * the rtnl_lock which we are holding.
7368          */
7369         while (tp->tg3_flags & TG3_FLAG_IN_RESET_TASK)
7370                 msleep(1);
7371
7372         netif_stop_queue(dev);
7373
7374         del_timer_sync(&tp->timer);
7375
7376         tg3_full_lock(tp, 1);
7377 #if 0
7378         tg3_dump_state(tp);
7379 #endif
7380
7381         tg3_disable_ints(tp);
7382
7383         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
7384         tg3_free_rings(tp);
7385         tp->tg3_flags &=
7386                 ~(TG3_FLAG_INIT_COMPLETE |
7387                   TG3_FLAG_GOT_SERDES_FLOWCTL);
7388
7389         tg3_full_unlock(tp);
7390
7391         free_irq(tp->pdev->irq, dev);
7392         if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
7393                 pci_disable_msi(tp->pdev);
7394                 tp->tg3_flags2 &= ~TG3_FLG2_USING_MSI;
7395         }
7396
7397         memcpy(&tp->net_stats_prev, tg3_get_stats(tp->dev),
7398                sizeof(tp->net_stats_prev));
7399         memcpy(&tp->estats_prev, tg3_get_estats(tp),
7400                sizeof(tp->estats_prev));
7401
7402         tg3_free_consistent(tp);
7403
7404         tg3_set_power_state(tp, PCI_D3hot);
7405
7406         netif_carrier_off(tp->dev);
7407
7408         return 0;
7409 }
7410
7411 static inline unsigned long get_stat64(tg3_stat64_t *val)
7412 {
7413         unsigned long ret;
7414
7415 #if (BITS_PER_LONG == 32)
7416         ret = val->low;
7417 #else
7418         ret = ((u64)val->high << 32) | ((u64)val->low);
7419 #endif
7420         return ret;
7421 }
7422
7423 static unsigned long calc_crc_errors(struct tg3 *tp)
7424 {
7425         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7426
7427         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) &&
7428             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
7429              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)) {
7430                 u32 val;
7431
7432                 spin_lock_bh(&tp->lock);
7433                 if (!tg3_readphy(tp, MII_TG3_TEST1, &val)) {
7434                         tg3_writephy(tp, MII_TG3_TEST1,
7435                                      val | MII_TG3_TEST1_CRC_EN);
7436                         tg3_readphy(tp, 0x14, &val);
7437                 } else
7438                         val = 0;
7439                 spin_unlock_bh(&tp->lock);
7440
7441                 tp->phy_crc_errors += val;
7442
7443                 return tp->phy_crc_errors;
7444         }
7445
7446         return get_stat64(&hw_stats->rx_fcs_errors);
7447 }
7448
7449 #define ESTAT_ADD(member) \
7450         estats->member =        old_estats->member + \
7451                                 get_stat64(&hw_stats->member)
7452
7453 static struct tg3_ethtool_stats *tg3_get_estats(struct tg3 *tp)
7454 {
7455         struct tg3_ethtool_stats *estats = &tp->estats;
7456         struct tg3_ethtool_stats *old_estats = &tp->estats_prev;
7457         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7458
7459         if (!hw_stats)
7460                 return old_estats;
7461
7462         ESTAT_ADD(rx_octets);
7463         ESTAT_ADD(rx_fragments);
7464         ESTAT_ADD(rx_ucast_packets);
7465         ESTAT_ADD(rx_mcast_packets);
7466         ESTAT_ADD(rx_bcast_packets);
7467         ESTAT_ADD(rx_fcs_errors);
7468         ESTAT_ADD(rx_align_errors);
7469         ESTAT_ADD(rx_xon_pause_rcvd);
7470         ESTAT_ADD(rx_xoff_pause_rcvd);
7471         ESTAT_ADD(rx_mac_ctrl_rcvd);
7472         ESTAT_ADD(rx_xoff_entered);
7473         ESTAT_ADD(rx_frame_too_long_errors);
7474         ESTAT_ADD(rx_jabbers);
7475         ESTAT_ADD(rx_undersize_packets);
7476         ESTAT_ADD(rx_in_length_errors);
7477         ESTAT_ADD(rx_out_length_errors);
7478         ESTAT_ADD(rx_64_or_less_octet_packets);
7479         ESTAT_ADD(rx_65_to_127_octet_packets);
7480         ESTAT_ADD(rx_128_to_255_octet_packets);
7481         ESTAT_ADD(rx_256_to_511_octet_packets);
7482         ESTAT_ADD(rx_512_to_1023_octet_packets);
7483         ESTAT_ADD(rx_1024_to_1522_octet_packets);
7484         ESTAT_ADD(rx_1523_to_2047_octet_packets);
7485         ESTAT_ADD(rx_2048_to_4095_octet_packets);
7486         ESTAT_ADD(rx_4096_to_8191_octet_packets);
7487         ESTAT_ADD(rx_8192_to_9022_octet_packets);
7488
7489         ESTAT_ADD(tx_octets);
7490         ESTAT_ADD(tx_collisions);
7491         ESTAT_ADD(tx_xon_sent);
7492         ESTAT_ADD(tx_xoff_sent);
7493         ESTAT_ADD(tx_flow_control);
7494         ESTAT_ADD(tx_mac_errors);
7495         ESTAT_ADD(tx_single_collisions);
7496         ESTAT_ADD(tx_mult_collisions);
7497         ESTAT_ADD(tx_deferred);
7498         ESTAT_ADD(tx_excessive_collisions);
7499         ESTAT_ADD(tx_late_collisions);
7500         ESTAT_ADD(tx_collide_2times);
7501         ESTAT_ADD(tx_collide_3times);
7502         ESTAT_ADD(tx_collide_4times);
7503         ESTAT_ADD(tx_collide_5times);
7504         ESTAT_ADD(tx_collide_6times);
7505         ESTAT_ADD(tx_collide_7times);
7506         ESTAT_ADD(tx_collide_8times);
7507         ESTAT_ADD(tx_collide_9times);
7508         ESTAT_ADD(tx_collide_10times);
7509         ESTAT_ADD(tx_collide_11times);
7510         ESTAT_ADD(tx_collide_12times);
7511         ESTAT_ADD(tx_collide_13times);
7512         ESTAT_ADD(tx_collide_14times);
7513         ESTAT_ADD(tx_collide_15times);
7514         ESTAT_ADD(tx_ucast_packets);
7515         ESTAT_ADD(tx_mcast_packets);
7516         ESTAT_ADD(tx_bcast_packets);
7517         ESTAT_ADD(tx_carrier_sense_errors);
7518         ESTAT_ADD(tx_discards);
7519         ESTAT_ADD(tx_errors);
7520
7521         ESTAT_ADD(dma_writeq_full);
7522         ESTAT_ADD(dma_write_prioq_full);
7523         ESTAT_ADD(rxbds_empty);
7524         ESTAT_ADD(rx_discards);
7525         ESTAT_ADD(rx_errors);
7526         ESTAT_ADD(rx_threshold_hit);
7527
7528         ESTAT_ADD(dma_readq_full);
7529         ESTAT_ADD(dma_read_prioq_full);
7530         ESTAT_ADD(tx_comp_queue_full);
7531
7532         ESTAT_ADD(ring_set_send_prod_index);
7533         ESTAT_ADD(ring_status_update);
7534         ESTAT_ADD(nic_irqs);
7535         ESTAT_ADD(nic_avoided_irqs);
7536         ESTAT_ADD(nic_tx_threshold_hit);
7537
7538         return estats;
7539 }
7540
7541 static struct net_device_stats *tg3_get_stats(struct net_device *dev)
7542 {
7543         struct tg3 *tp = netdev_priv(dev);
7544         struct net_device_stats *stats = &tp->net_stats;
7545         struct net_device_stats *old_stats = &tp->net_stats_prev;
7546         struct tg3_hw_stats *hw_stats = tp->hw_stats;
7547
7548         if (!hw_stats)
7549                 return old_stats;
7550
7551         stats->rx_packets = old_stats->rx_packets +
7552                 get_stat64(&hw_stats->rx_ucast_packets) +
7553                 get_stat64(&hw_stats->rx_mcast_packets) +
7554                 get_stat64(&hw_stats->rx_bcast_packets);
7555
7556         stats->tx_packets = old_stats->tx_packets +
7557                 get_stat64(&hw_stats->tx_ucast_packets) +
7558                 get_stat64(&hw_stats->tx_mcast_packets) +
7559                 get_stat64(&hw_stats->tx_bcast_packets);
7560
7561         stats->rx_bytes = old_stats->rx_bytes +
7562                 get_stat64(&hw_stats->rx_octets);
7563         stats->tx_bytes = old_stats->tx_bytes +
7564                 get_stat64(&hw_stats->tx_octets);
7565
7566         stats->rx_errors = old_stats->rx_errors +
7567                 get_stat64(&hw_stats->rx_errors);
7568         stats->tx_errors = old_stats->tx_errors +
7569                 get_stat64(&hw_stats->tx_errors) +
7570                 get_stat64(&hw_stats->tx_mac_errors) +
7571                 get_stat64(&hw_stats->tx_carrier_sense_errors) +
7572                 get_stat64(&hw_stats->tx_discards);
7573
7574         stats->multicast = old_stats->multicast +
7575                 get_stat64(&hw_stats->rx_mcast_packets);
7576         stats->collisions = old_stats->collisions +
7577                 get_stat64(&hw_stats->tx_collisions);
7578
7579         stats->rx_length_errors = old_stats->rx_length_errors +
7580                 get_stat64(&hw_stats->rx_frame_too_long_errors) +
7581                 get_stat64(&hw_stats->rx_undersize_packets);
7582
7583         stats->rx_over_errors = old_stats->rx_over_errors +
7584                 get_stat64(&hw_stats->rxbds_empty);
7585         stats->rx_frame_errors = old_stats->rx_frame_errors +
7586                 get_stat64(&hw_stats->rx_align_errors);
7587         stats->tx_aborted_errors = old_stats->tx_aborted_errors +
7588                 get_stat64(&hw_stats->tx_discards);
7589         stats->tx_carrier_errors = old_stats->tx_carrier_errors +
7590                 get_stat64(&hw_stats->tx_carrier_sense_errors);
7591
7592         stats->rx_crc_errors = old_stats->rx_crc_errors +
7593                 calc_crc_errors(tp);
7594
7595         stats->rx_missed_errors = old_stats->rx_missed_errors +
7596                 get_stat64(&hw_stats->rx_discards);
7597
7598         return stats;
7599 }
7600
7601 static inline u32 calc_crc(unsigned char *buf, int len)
7602 {
7603         u32 reg;
7604         u32 tmp;
7605         int j, k;
7606
7607         reg = 0xffffffff;
7608
7609         for (j = 0; j < len; j++) {
7610                 reg ^= buf[j];
7611
7612                 for (k = 0; k < 8; k++) {
7613                         tmp = reg & 0x01;
7614
7615                         reg >>= 1;
7616
7617                         if (tmp) {
7618                                 reg ^= 0xedb88320;
7619                         }
7620                 }
7621         }
7622
7623         return ~reg;
7624 }
7625
7626 static void tg3_set_multi(struct tg3 *tp, unsigned int accept_all)
7627 {
7628         /* accept or reject all multicast frames */
7629         tw32(MAC_HASH_REG_0, accept_all ? 0xffffffff : 0);
7630         tw32(MAC_HASH_REG_1, accept_all ? 0xffffffff : 0);
7631         tw32(MAC_HASH_REG_2, accept_all ? 0xffffffff : 0);
7632         tw32(MAC_HASH_REG_3, accept_all ? 0xffffffff : 0);
7633 }
7634
7635 static void __tg3_set_rx_mode(struct net_device *dev)
7636 {
7637         struct tg3 *tp = netdev_priv(dev);
7638         u32 rx_mode;
7639
7640         rx_mode = tp->rx_mode & ~(RX_MODE_PROMISC |
7641                                   RX_MODE_KEEP_VLAN_TAG);
7642
7643         /* When ASF is in use, we always keep the RX_MODE_KEEP_VLAN_TAG
7644          * flag clear.
7645          */
7646 #if TG3_VLAN_TAG_USED
7647         if (!tp->vlgrp &&
7648             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7649                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7650 #else
7651         /* By definition, VLAN is disabled always in this
7652          * case.
7653          */
7654         if (!(tp->tg3_flags & TG3_FLAG_ENABLE_ASF))
7655                 rx_mode |= RX_MODE_KEEP_VLAN_TAG;
7656 #endif
7657
7658         if (dev->flags & IFF_PROMISC) {
7659                 /* Promiscuous mode. */
7660                 rx_mode |= RX_MODE_PROMISC;
7661         } else if (dev->flags & IFF_ALLMULTI) {
7662                 /* Accept all multicast. */
7663                 tg3_set_multi (tp, 1);
7664         } else if (dev->mc_count < 1) {
7665                 /* Reject all multicast. */
7666                 tg3_set_multi (tp, 0);
7667         } else {
7668                 /* Accept one or more multicast(s). */
7669                 struct dev_mc_list *mclist;
7670                 unsigned int i;
7671                 u32 mc_filter[4] = { 0, };
7672                 u32 regidx;
7673                 u32 bit;
7674                 u32 crc;
7675
7676                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
7677                      i++, mclist = mclist->next) {
7678
7679                         crc = calc_crc (mclist->dmi_addr, ETH_ALEN);
7680                         bit = ~crc & 0x7f;
7681                         regidx = (bit & 0x60) >> 5;
7682                         bit &= 0x1f;
7683                         mc_filter[regidx] |= (1 << bit);
7684                 }
7685
7686                 tw32(MAC_HASH_REG_0, mc_filter[0]);
7687                 tw32(MAC_HASH_REG_1, mc_filter[1]);
7688                 tw32(MAC_HASH_REG_2, mc_filter[2]);
7689                 tw32(MAC_HASH_REG_3, mc_filter[3]);
7690         }
7691
7692         if (rx_mode != tp->rx_mode) {
7693                 tp->rx_mode = rx_mode;
7694                 tw32_f(MAC_RX_MODE, rx_mode);
7695                 udelay(10);
7696         }
7697 }
7698
7699 static void tg3_set_rx_mode(struct net_device *dev)
7700 {
7701         struct tg3 *tp = netdev_priv(dev);
7702
7703         if (!netif_running(dev))
7704                 return;
7705
7706         tg3_full_lock(tp, 0);
7707         __tg3_set_rx_mode(dev);
7708         tg3_full_unlock(tp);
7709 }
7710
7711 #define TG3_REGDUMP_LEN         (32 * 1024)
7712
7713 static int tg3_get_regs_len(struct net_device *dev)
7714 {
7715         return TG3_REGDUMP_LEN;
7716 }
7717
7718 static void tg3_get_regs(struct net_device *dev,
7719                 struct ethtool_regs *regs, void *_p)
7720 {
7721         u32 *p = _p;
7722         struct tg3 *tp = netdev_priv(dev);
7723         u8 *orig_p = _p;
7724         int i;
7725
7726         regs->version = 0;
7727
7728         memset(p, 0, TG3_REGDUMP_LEN);
7729
7730         if (tp->link_config.phy_is_low_power)
7731                 return;
7732
7733         tg3_full_lock(tp, 0);
7734
7735 #define __GET_REG32(reg)        (*(p)++ = tr32(reg))
7736 #define GET_REG32_LOOP(base,len)                \
7737 do {    p = (u32 *)(orig_p + (base));           \
7738         for (i = 0; i < len; i += 4)            \
7739                 __GET_REG32((base) + i);        \
7740 } while (0)
7741 #define GET_REG32_1(reg)                        \
7742 do {    p = (u32 *)(orig_p + (reg));            \
7743         __GET_REG32((reg));                     \
7744 } while (0)
7745
7746         GET_REG32_LOOP(TG3PCI_VENDOR, 0xb0);
7747         GET_REG32_LOOP(MAILBOX_INTERRUPT_0, 0x200);
7748         GET_REG32_LOOP(MAC_MODE, 0x4f0);
7749         GET_REG32_LOOP(SNDDATAI_MODE, 0xe0);
7750         GET_REG32_1(SNDDATAC_MODE);
7751         GET_REG32_LOOP(SNDBDS_MODE, 0x80);
7752         GET_REG32_LOOP(SNDBDI_MODE, 0x48);
7753         GET_REG32_1(SNDBDC_MODE);
7754         GET_REG32_LOOP(RCVLPC_MODE, 0x20);
7755         GET_REG32_LOOP(RCVLPC_SELLST_BASE, 0x15c);
7756         GET_REG32_LOOP(RCVDBDI_MODE, 0x0c);
7757         GET_REG32_LOOP(RCVDBDI_JUMBO_BD, 0x3c);
7758         GET_REG32_LOOP(RCVDBDI_BD_PROD_IDX_0, 0x44);
7759         GET_REG32_1(RCVDCC_MODE);
7760         GET_REG32_LOOP(RCVBDI_MODE, 0x20);
7761         GET_REG32_LOOP(RCVCC_MODE, 0x14);
7762         GET_REG32_LOOP(RCVLSC_MODE, 0x08);
7763         GET_REG32_1(MBFREE_MODE);
7764         GET_REG32_LOOP(HOSTCC_MODE, 0x100);
7765         GET_REG32_LOOP(MEMARB_MODE, 0x10);
7766         GET_REG32_LOOP(BUFMGR_MODE, 0x58);
7767         GET_REG32_LOOP(RDMAC_MODE, 0x08);
7768         GET_REG32_LOOP(WDMAC_MODE, 0x08);
7769         GET_REG32_1(RX_CPU_MODE);
7770         GET_REG32_1(RX_CPU_STATE);
7771         GET_REG32_1(RX_CPU_PGMCTR);
7772         GET_REG32_1(RX_CPU_HWBKPT);
7773         GET_REG32_1(TX_CPU_MODE);
7774         GET_REG32_1(TX_CPU_STATE);
7775         GET_REG32_1(TX_CPU_PGMCTR);
7776         GET_REG32_LOOP(GRCMBOX_INTERRUPT_0, 0x110);
7777         GET_REG32_LOOP(FTQ_RESET, 0x120);
7778         GET_REG32_LOOP(MSGINT_MODE, 0x0c);
7779         GET_REG32_1(DMAC_MODE);
7780         GET_REG32_LOOP(GRC_MODE, 0x4c);
7781         if (tp->tg3_flags & TG3_FLAG_NVRAM)
7782                 GET_REG32_LOOP(NVRAM_CMD, 0x24);
7783
7784 #undef __GET_REG32
7785 #undef GET_REG32_LOOP
7786 #undef GET_REG32_1
7787
7788         tg3_full_unlock(tp);
7789 }
7790
7791 static int tg3_get_eeprom_len(struct net_device *dev)
7792 {
7793         struct tg3 *tp = netdev_priv(dev);
7794
7795         return tp->nvram_size;
7796 }
7797
7798 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val);
7799 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val);
7800
7801 static int tg3_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7802 {
7803         struct tg3 *tp = netdev_priv(dev);
7804         int ret;
7805         u8  *pd;
7806         u32 i, offset, len, val, b_offset, b_count;
7807
7808         if (tp->link_config.phy_is_low_power)
7809                 return -EAGAIN;
7810
7811         offset = eeprom->offset;
7812         len = eeprom->len;
7813         eeprom->len = 0;
7814
7815         eeprom->magic = TG3_EEPROM_MAGIC;
7816
7817         if (offset & 3) {
7818                 /* adjustments to start on required 4 byte boundary */
7819                 b_offset = offset & 3;
7820                 b_count = 4 - b_offset;
7821                 if (b_count > len) {
7822                         /* i.e. offset=1 len=2 */
7823                         b_count = len;
7824                 }
7825                 ret = tg3_nvram_read(tp, offset-b_offset, &val);
7826                 if (ret)
7827                         return ret;
7828                 val = cpu_to_le32(val);
7829                 memcpy(data, ((char*)&val) + b_offset, b_count);
7830                 len -= b_count;
7831                 offset += b_count;
7832                 eeprom->len += b_count;
7833         }
7834
7835         /* read bytes upto the last 4 byte boundary */
7836         pd = &data[eeprom->len];
7837         for (i = 0; i < (len - (len & 3)); i += 4) {
7838                 ret = tg3_nvram_read(tp, offset + i, &val);
7839                 if (ret) {
7840                         eeprom->len += i;
7841                         return ret;
7842                 }
7843                 val = cpu_to_le32(val);
7844                 memcpy(pd + i, &val, 4);
7845         }
7846         eeprom->len += i;
7847
7848         if (len & 3) {
7849                 /* read last bytes not ending on 4 byte boundary */
7850                 pd = &data[eeprom->len];
7851                 b_count = len & 3;
7852                 b_offset = offset + len - b_count;
7853                 ret = tg3_nvram_read(tp, b_offset, &val);
7854                 if (ret)
7855                         return ret;
7856                 val = cpu_to_le32(val);
7857                 memcpy(pd, ((char*)&val), b_count);
7858                 eeprom->len += b_count;
7859         }
7860         return 0;
7861 }
7862
7863 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf);
7864
7865 static int tg3_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom, u8 *data)
7866 {
7867         struct tg3 *tp = netdev_priv(dev);
7868         int ret;
7869         u32 offset, len, b_offset, odd_len, start, end;
7870         u8 *buf;
7871
7872         if (tp->link_config.phy_is_low_power)
7873                 return -EAGAIN;
7874
7875         if (eeprom->magic != TG3_EEPROM_MAGIC)
7876                 return -EINVAL;
7877
7878         offset = eeprom->offset;
7879         len = eeprom->len;
7880
7881         if ((b_offset = (offset & 3))) {
7882                 /* adjustments to start on required 4 byte boundary */
7883                 ret = tg3_nvram_read(tp, offset-b_offset, &start);
7884                 if (ret)
7885                         return ret;
7886                 start = cpu_to_le32(start);
7887                 len += b_offset;
7888                 offset &= ~3;
7889                 if (len < 4)
7890                         len = 4;
7891         }
7892
7893         odd_len = 0;
7894         if (len & 3) {
7895                 /* adjustments to end on required 4 byte boundary */
7896                 odd_len = 1;
7897                 len = (len + 3) & ~3;
7898                 ret = tg3_nvram_read(tp, offset+len-4, &end);
7899                 if (ret)
7900                         return ret;
7901                 end = cpu_to_le32(end);
7902         }
7903
7904         buf = data;
7905         if (b_offset || odd_len) {
7906                 buf = kmalloc(len, GFP_KERNEL);
7907                 if (buf == 0)
7908                         return -ENOMEM;
7909                 if (b_offset)
7910                         memcpy(buf, &start, 4);
7911                 if (odd_len)
7912                         memcpy(buf+len-4, &end, 4);
7913                 memcpy(buf + b_offset, data, eeprom->len);
7914         }
7915
7916         ret = tg3_nvram_write_block(tp, offset, len, buf);
7917
7918         if (buf != data)
7919                 kfree(buf);
7920
7921         return ret;
7922 }
7923
7924 static int tg3_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7925 {
7926         struct tg3 *tp = netdev_priv(dev);
7927
7928         cmd->supported = (SUPPORTED_Autoneg);
7929
7930         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
7931                 cmd->supported |= (SUPPORTED_1000baseT_Half |
7932                                    SUPPORTED_1000baseT_Full);
7933
7934         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)) {
7935                 cmd->supported |= (SUPPORTED_100baseT_Half |
7936                                   SUPPORTED_100baseT_Full |
7937                                   SUPPORTED_10baseT_Half |
7938                                   SUPPORTED_10baseT_Full |
7939                                   SUPPORTED_MII);
7940                 cmd->port = PORT_TP;
7941         } else {
7942                 cmd->supported |= SUPPORTED_FIBRE;
7943                 cmd->port = PORT_FIBRE;
7944         }
7945
7946         cmd->advertising = tp->link_config.advertising;
7947         if (netif_running(dev)) {
7948                 cmd->speed = tp->link_config.active_speed;
7949                 cmd->duplex = tp->link_config.active_duplex;
7950         }
7951         cmd->phy_address = PHY_ADDR;
7952         cmd->transceiver = 0;
7953         cmd->autoneg = tp->link_config.autoneg;
7954         cmd->maxtxpkt = 0;
7955         cmd->maxrxpkt = 0;
7956         return 0;
7957 }
7958
7959 static int tg3_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
7960 {
7961         struct tg3 *tp = netdev_priv(dev);
7962
7963         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) {
7964                 /* These are the only valid advertisement bits allowed.  */
7965                 if (cmd->autoneg == AUTONEG_ENABLE &&
7966                     (cmd->advertising & ~(ADVERTISED_1000baseT_Half |
7967                                           ADVERTISED_1000baseT_Full |
7968                                           ADVERTISED_Autoneg |
7969                                           ADVERTISED_FIBRE)))
7970                         return -EINVAL;
7971                 /* Fiber can only do SPEED_1000.  */
7972                 else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7973                          (cmd->speed != SPEED_1000))
7974                         return -EINVAL;
7975         /* Copper cannot force SPEED_1000.  */
7976         } else if ((cmd->autoneg != AUTONEG_ENABLE) &&
7977                    (cmd->speed == SPEED_1000))
7978                 return -EINVAL;
7979         else if ((cmd->speed == SPEED_1000) &&
7980                  (tp->tg3_flags2 & TG3_FLAG_10_100_ONLY))
7981                 return -EINVAL;
7982
7983         tg3_full_lock(tp, 0);
7984
7985         tp->link_config.autoneg = cmd->autoneg;
7986         if (cmd->autoneg == AUTONEG_ENABLE) {
7987                 tp->link_config.advertising = cmd->advertising;
7988                 tp->link_config.speed = SPEED_INVALID;
7989                 tp->link_config.duplex = DUPLEX_INVALID;
7990         } else {
7991                 tp->link_config.advertising = 0;
7992                 tp->link_config.speed = cmd->speed;
7993                 tp->link_config.duplex = cmd->duplex;
7994         }
7995
7996         tp->link_config.orig_speed = tp->link_config.speed;
7997         tp->link_config.orig_duplex = tp->link_config.duplex;
7998         tp->link_config.orig_autoneg = tp->link_config.autoneg;
7999
8000         if (netif_running(dev))
8001                 tg3_setup_phy(tp, 1);
8002
8003         tg3_full_unlock(tp);
8004
8005         return 0;
8006 }
8007
8008 static void tg3_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
8009 {
8010         struct tg3 *tp = netdev_priv(dev);
8011
8012         strcpy(info->driver, DRV_MODULE_NAME);
8013         strcpy(info->version, DRV_MODULE_VERSION);
8014         strcpy(info->fw_version, tp->fw_ver);
8015         strcpy(info->bus_info, pci_name(tp->pdev));
8016 }
8017
8018 static void tg3_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8019 {
8020         struct tg3 *tp = netdev_priv(dev);
8021
8022         wol->supported = WAKE_MAGIC;
8023         wol->wolopts = 0;
8024         if (tp->tg3_flags & TG3_FLAG_WOL_ENABLE)
8025                 wol->wolopts = WAKE_MAGIC;
8026         memset(&wol->sopass, 0, sizeof(wol->sopass));
8027 }
8028
8029 static int tg3_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
8030 {
8031         struct tg3 *tp = netdev_priv(dev);
8032
8033         if (wol->wolopts & ~WAKE_MAGIC)
8034                 return -EINVAL;
8035         if ((wol->wolopts & WAKE_MAGIC) &&
8036             tp->tg3_flags2 & TG3_FLG2_ANY_SERDES &&
8037             !(tp->tg3_flags & TG3_FLAG_SERDES_WOL_CAP))
8038                 return -EINVAL;
8039
8040         spin_lock_bh(&tp->lock);
8041         if (wol->wolopts & WAKE_MAGIC)
8042                 tp->tg3_flags |= TG3_FLAG_WOL_ENABLE;
8043         else
8044                 tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
8045         spin_unlock_bh(&tp->lock);
8046
8047         return 0;
8048 }
8049
8050 static u32 tg3_get_msglevel(struct net_device *dev)
8051 {
8052         struct tg3 *tp = netdev_priv(dev);
8053         return tp->msg_enable;
8054 }
8055
8056 static void tg3_set_msglevel(struct net_device *dev, u32 value)
8057 {
8058         struct tg3 *tp = netdev_priv(dev);
8059         tp->msg_enable = value;
8060 }
8061
8062 static int tg3_set_tso(struct net_device *dev, u32 value)
8063 {
8064         struct tg3 *tp = netdev_priv(dev);
8065
8066         if (!(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE)) {
8067                 if (value)
8068                         return -EINVAL;
8069                 return 0;
8070         }
8071         if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
8072             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)) {
8073                 if (value)
8074                         dev->features |= NETIF_F_TSO6;
8075                 else
8076                         dev->features &= ~NETIF_F_TSO6;
8077         }
8078         return ethtool_op_set_tso(dev, value);
8079 }
8080
8081 static int tg3_nway_reset(struct net_device *dev)
8082 {
8083         struct tg3 *tp = netdev_priv(dev);
8084         u32 bmcr;
8085         int r;
8086
8087         if (!netif_running(dev))
8088                 return -EAGAIN;
8089
8090         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
8091                 return -EINVAL;
8092
8093         spin_lock_bh(&tp->lock);
8094         r = -EINVAL;
8095         tg3_readphy(tp, MII_BMCR, &bmcr);
8096         if (!tg3_readphy(tp, MII_BMCR, &bmcr) &&
8097             ((bmcr & BMCR_ANENABLE) ||
8098              (tp->tg3_flags2 & TG3_FLG2_PARALLEL_DETECT))) {
8099                 tg3_writephy(tp, MII_BMCR, bmcr | BMCR_ANRESTART |
8100                                            BMCR_ANENABLE);
8101                 r = 0;
8102         }
8103         spin_unlock_bh(&tp->lock);
8104
8105         return r;
8106 }
8107
8108 static void tg3_get_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8109 {
8110         struct tg3 *tp = netdev_priv(dev);
8111
8112         ering->rx_max_pending = TG3_RX_RING_SIZE - 1;
8113         ering->rx_mini_max_pending = 0;
8114         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8115                 ering->rx_jumbo_max_pending = TG3_RX_JUMBO_RING_SIZE - 1;
8116         else
8117                 ering->rx_jumbo_max_pending = 0;
8118
8119         ering->tx_max_pending = TG3_TX_RING_SIZE - 1;
8120
8121         ering->rx_pending = tp->rx_pending;
8122         ering->rx_mini_pending = 0;
8123         if (tp->tg3_flags & TG3_FLAG_JUMBO_RING_ENABLE)
8124                 ering->rx_jumbo_pending = tp->rx_jumbo_pending;
8125         else
8126                 ering->rx_jumbo_pending = 0;
8127
8128         ering->tx_pending = tp->tx_pending;
8129 }
8130
8131 static int tg3_set_ringparam(struct net_device *dev, struct ethtool_ringparam *ering)
8132 {
8133         struct tg3 *tp = netdev_priv(dev);
8134         int irq_sync = 0, err = 0;
8135
8136         if ((ering->rx_pending > TG3_RX_RING_SIZE - 1) ||
8137             (ering->rx_jumbo_pending > TG3_RX_JUMBO_RING_SIZE - 1) ||
8138             (ering->tx_pending > TG3_TX_RING_SIZE - 1) ||
8139             (ering->tx_pending <= MAX_SKB_FRAGS) ||
8140             ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_1_BUG) &&
8141              (ering->tx_pending <= (MAX_SKB_FRAGS * 3))))
8142                 return -EINVAL;
8143
8144         if (netif_running(dev)) {
8145                 tg3_netif_stop(tp);
8146                 irq_sync = 1;
8147         }
8148
8149         tg3_full_lock(tp, irq_sync);
8150
8151         tp->rx_pending = ering->rx_pending;
8152
8153         if ((tp->tg3_flags2 & TG3_FLG2_MAX_RXPEND_64) &&
8154             tp->rx_pending > 63)
8155                 tp->rx_pending = 63;
8156         tp->rx_jumbo_pending = ering->rx_jumbo_pending;
8157         tp->tx_pending = ering->tx_pending;
8158
8159         if (netif_running(dev)) {
8160                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8161                 err = tg3_restart_hw(tp, 1);
8162                 if (!err)
8163                         tg3_netif_start(tp);
8164         }
8165
8166         tg3_full_unlock(tp);
8167
8168         return err;
8169 }
8170
8171 static void tg3_get_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8172 {
8173         struct tg3 *tp = netdev_priv(dev);
8174
8175         epause->autoneg = (tp->tg3_flags & TG3_FLAG_PAUSE_AUTONEG) != 0;
8176         epause->rx_pause = (tp->tg3_flags & TG3_FLAG_RX_PAUSE) != 0;
8177         epause->tx_pause = (tp->tg3_flags & TG3_FLAG_TX_PAUSE) != 0;
8178 }
8179
8180 static int tg3_set_pauseparam(struct net_device *dev, struct ethtool_pauseparam *epause)
8181 {
8182         struct tg3 *tp = netdev_priv(dev);
8183         int irq_sync = 0, err = 0;
8184
8185         if (netif_running(dev)) {
8186                 tg3_netif_stop(tp);
8187                 irq_sync = 1;
8188         }
8189
8190         tg3_full_lock(tp, irq_sync);
8191
8192         if (epause->autoneg)
8193                 tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
8194         else
8195                 tp->tg3_flags &= ~TG3_FLAG_PAUSE_AUTONEG;
8196         if (epause->rx_pause)
8197                 tp->tg3_flags |= TG3_FLAG_RX_PAUSE;
8198         else
8199                 tp->tg3_flags &= ~TG3_FLAG_RX_PAUSE;
8200         if (epause->tx_pause)
8201                 tp->tg3_flags |= TG3_FLAG_TX_PAUSE;
8202         else
8203                 tp->tg3_flags &= ~TG3_FLAG_TX_PAUSE;
8204
8205         if (netif_running(dev)) {
8206                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
8207                 err = tg3_restart_hw(tp, 1);
8208                 if (!err)
8209                         tg3_netif_start(tp);
8210         }
8211
8212         tg3_full_unlock(tp);
8213
8214         return err;
8215 }
8216
8217 static u32 tg3_get_rx_csum(struct net_device *dev)
8218 {
8219         struct tg3 *tp = netdev_priv(dev);
8220         return (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0;
8221 }
8222
8223 static int tg3_set_rx_csum(struct net_device *dev, u32 data)
8224 {
8225         struct tg3 *tp = netdev_priv(dev);
8226
8227         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8228                 if (data != 0)
8229                         return -EINVAL;
8230                 return 0;
8231         }
8232
8233         spin_lock_bh(&tp->lock);
8234         if (data)
8235                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
8236         else
8237                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
8238         spin_unlock_bh(&tp->lock);
8239
8240         return 0;
8241 }
8242
8243 static int tg3_set_tx_csum(struct net_device *dev, u32 data)
8244 {
8245         struct tg3 *tp = netdev_priv(dev);
8246
8247         if (tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) {
8248                 if (data != 0)
8249                         return -EINVAL;
8250                 return 0;
8251         }
8252
8253         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8254             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8255                 ethtool_op_set_tx_hw_csum(dev, data);
8256         else
8257                 ethtool_op_set_tx_csum(dev, data);
8258
8259         return 0;
8260 }
8261
8262 static int tg3_get_stats_count (struct net_device *dev)
8263 {
8264         return TG3_NUM_STATS;
8265 }
8266
8267 static int tg3_get_test_count (struct net_device *dev)
8268 {
8269         return TG3_NUM_TEST;
8270 }
8271
8272 static void tg3_get_strings (struct net_device *dev, u32 stringset, u8 *buf)
8273 {
8274         switch (stringset) {
8275         case ETH_SS_STATS:
8276                 memcpy(buf, &ethtool_stats_keys, sizeof(ethtool_stats_keys));
8277                 break;
8278         case ETH_SS_TEST:
8279                 memcpy(buf, &ethtool_test_keys, sizeof(ethtool_test_keys));
8280                 break;
8281         default:
8282                 WARN_ON(1);     /* we need a WARN() */
8283                 break;
8284         }
8285 }
8286
8287 static int tg3_phys_id(struct net_device *dev, u32 data)
8288 {
8289         struct tg3 *tp = netdev_priv(dev);
8290         int i;
8291
8292         if (!netif_running(tp->dev))
8293                 return -EAGAIN;
8294
8295         if (data == 0)
8296                 data = 2;
8297
8298         for (i = 0; i < (data * 2); i++) {
8299                 if ((i % 2) == 0)
8300                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8301                                            LED_CTRL_1000MBPS_ON |
8302                                            LED_CTRL_100MBPS_ON |
8303                                            LED_CTRL_10MBPS_ON |
8304                                            LED_CTRL_TRAFFIC_OVERRIDE |
8305                                            LED_CTRL_TRAFFIC_BLINK |
8306                                            LED_CTRL_TRAFFIC_LED);
8307
8308                 else
8309                         tw32(MAC_LED_CTRL, LED_CTRL_LNKLED_OVERRIDE |
8310                                            LED_CTRL_TRAFFIC_OVERRIDE);
8311
8312                 if (msleep_interruptible(500))
8313                         break;
8314         }
8315         tw32(MAC_LED_CTRL, tp->led_ctrl);
8316         return 0;
8317 }
8318
8319 static void tg3_get_ethtool_stats (struct net_device *dev,
8320                                    struct ethtool_stats *estats, u64 *tmp_stats)
8321 {
8322         struct tg3 *tp = netdev_priv(dev);
8323         memcpy(tmp_stats, tg3_get_estats(tp), sizeof(tp->estats));
8324 }
8325
8326 #define NVRAM_TEST_SIZE 0x100
8327 #define NVRAM_SELFBOOT_FORMAT1_SIZE 0x14
8328 #define NVRAM_SELFBOOT_HW_SIZE 0x20
8329 #define NVRAM_SELFBOOT_DATA_SIZE 0x1c
8330
8331 static int tg3_test_nvram(struct tg3 *tp)
8332 {
8333         u32 *buf, csum, magic;
8334         int i, j, err = 0, size;
8335
8336         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
8337                 return -EIO;
8338
8339         if (magic == TG3_EEPROM_MAGIC)
8340                 size = NVRAM_TEST_SIZE;
8341         else if ((magic & TG3_EEPROM_MAGIC_FW_MSK) == TG3_EEPROM_MAGIC_FW) {
8342                 if ((magic & 0xe00000) == 0x200000)
8343                         size = NVRAM_SELFBOOT_FORMAT1_SIZE;
8344                 else
8345                         return 0;
8346         } else if ((magic & TG3_EEPROM_MAGIC_HW_MSK) == TG3_EEPROM_MAGIC_HW)
8347                 size = NVRAM_SELFBOOT_HW_SIZE;
8348         else
8349                 return -EIO;
8350
8351         buf = kmalloc(size, GFP_KERNEL);
8352         if (buf == NULL)
8353                 return -ENOMEM;
8354
8355         err = -EIO;
8356         for (i = 0, j = 0; i < size; i += 4, j++) {
8357                 u32 val;
8358
8359                 if ((err = tg3_nvram_read(tp, i, &val)) != 0)
8360                         break;
8361                 buf[j] = cpu_to_le32(val);
8362         }
8363         if (i < size)
8364                 goto out;
8365
8366         /* Selfboot format */
8367         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_FW_MSK) ==
8368             TG3_EEPROM_MAGIC_FW) {
8369                 u8 *buf8 = (u8 *) buf, csum8 = 0;
8370
8371                 for (i = 0; i < size; i++)
8372                         csum8 += buf8[i];
8373
8374                 if (csum8 == 0) {
8375                         err = 0;
8376                         goto out;
8377                 }
8378
8379                 err = -EIO;
8380                 goto out;
8381         }
8382
8383         if ((cpu_to_be32(buf[0]) & TG3_EEPROM_MAGIC_HW_MSK) ==
8384             TG3_EEPROM_MAGIC_HW) {
8385                 u8 data[NVRAM_SELFBOOT_DATA_SIZE];
8386                 u8 parity[NVRAM_SELFBOOT_DATA_SIZE];
8387                 u8 *buf8 = (u8 *) buf;
8388                 int j, k;
8389
8390                 /* Separate the parity bits and the data bytes.  */
8391                 for (i = 0, j = 0, k = 0; i < NVRAM_SELFBOOT_HW_SIZE; i++) {
8392                         if ((i == 0) || (i == 8)) {
8393                                 int l;
8394                                 u8 msk;
8395
8396                                 for (l = 0, msk = 0x80; l < 7; l++, msk >>= 1)
8397                                         parity[k++] = buf8[i] & msk;
8398                                 i++;
8399                         }
8400                         else if (i == 16) {
8401                                 int l;
8402                                 u8 msk;
8403
8404                                 for (l = 0, msk = 0x20; l < 6; l++, msk >>= 1)
8405                                         parity[k++] = buf8[i] & msk;
8406                                 i++;
8407
8408                                 for (l = 0, msk = 0x80; l < 8; l++, msk >>= 1)
8409                                         parity[k++] = buf8[i] & msk;
8410                                 i++;
8411                         }
8412                         data[j++] = buf8[i];
8413                 }
8414
8415                 err = -EIO;
8416                 for (i = 0; i < NVRAM_SELFBOOT_DATA_SIZE; i++) {
8417                         u8 hw8 = hweight8(data[i]);
8418
8419                         if ((hw8 & 0x1) && parity[i])
8420                                 goto out;
8421                         else if (!(hw8 & 0x1) && !parity[i])
8422                                 goto out;
8423                 }
8424                 err = 0;
8425                 goto out;
8426         }
8427
8428         /* Bootstrap checksum at offset 0x10 */
8429         csum = calc_crc((unsigned char *) buf, 0x10);
8430         if(csum != cpu_to_le32(buf[0x10/4]))
8431                 goto out;
8432
8433         /* Manufacturing block starts at offset 0x74, checksum at 0xfc */
8434         csum = calc_crc((unsigned char *) &buf[0x74/4], 0x88);
8435         if (csum != cpu_to_le32(buf[0xfc/4]))
8436                  goto out;
8437
8438         err = 0;
8439
8440 out:
8441         kfree(buf);
8442         return err;
8443 }
8444
8445 #define TG3_SERDES_TIMEOUT_SEC  2
8446 #define TG3_COPPER_TIMEOUT_SEC  6
8447
8448 static int tg3_test_link(struct tg3 *tp)
8449 {
8450         int i, max;
8451
8452         if (!netif_running(tp->dev))
8453                 return -ENODEV;
8454
8455         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
8456                 max = TG3_SERDES_TIMEOUT_SEC;
8457         else
8458                 max = TG3_COPPER_TIMEOUT_SEC;
8459
8460         for (i = 0; i < max; i++) {
8461                 if (netif_carrier_ok(tp->dev))
8462                         return 0;
8463
8464                 if (msleep_interruptible(1000))
8465                         break;
8466         }
8467
8468         return -EIO;
8469 }
8470
8471 /* Only test the commonly used registers */
8472 static int tg3_test_registers(struct tg3 *tp)
8473 {
8474         int i, is_5705, is_5750;
8475         u32 offset, read_mask, write_mask, val, save_val, read_val;
8476         static struct {
8477                 u16 offset;
8478                 u16 flags;
8479 #define TG3_FL_5705     0x1
8480 #define TG3_FL_NOT_5705 0x2
8481 #define TG3_FL_NOT_5788 0x4
8482 #define TG3_FL_NOT_5750 0x8
8483                 u32 read_mask;
8484                 u32 write_mask;
8485         } reg_tbl[] = {
8486                 /* MAC Control Registers */
8487                 { MAC_MODE, TG3_FL_NOT_5705,
8488                         0x00000000, 0x00ef6f8c },
8489                 { MAC_MODE, TG3_FL_5705,
8490                         0x00000000, 0x01ef6b8c },
8491                 { MAC_STATUS, TG3_FL_NOT_5705,
8492                         0x03800107, 0x00000000 },
8493                 { MAC_STATUS, TG3_FL_5705,
8494                         0x03800100, 0x00000000 },
8495                 { MAC_ADDR_0_HIGH, 0x0000,
8496                         0x00000000, 0x0000ffff },
8497                 { MAC_ADDR_0_LOW, 0x0000,
8498                         0x00000000, 0xffffffff },
8499                 { MAC_RX_MTU_SIZE, 0x0000,
8500                         0x00000000, 0x0000ffff },
8501                 { MAC_TX_MODE, 0x0000,
8502                         0x00000000, 0x00000070 },
8503                 { MAC_TX_LENGTHS, 0x0000,
8504                         0x00000000, 0x00003fff },
8505                 { MAC_RX_MODE, TG3_FL_NOT_5705,
8506                         0x00000000, 0x000007fc },
8507                 { MAC_RX_MODE, TG3_FL_5705,
8508                         0x00000000, 0x000007dc },
8509                 { MAC_HASH_REG_0, 0x0000,
8510                         0x00000000, 0xffffffff },
8511                 { MAC_HASH_REG_1, 0x0000,
8512                         0x00000000, 0xffffffff },
8513                 { MAC_HASH_REG_2, 0x0000,
8514                         0x00000000, 0xffffffff },
8515                 { MAC_HASH_REG_3, 0x0000,
8516                         0x00000000, 0xffffffff },
8517
8518                 /* Receive Data and Receive BD Initiator Control Registers. */
8519                 { RCVDBDI_JUMBO_BD+0, TG3_FL_NOT_5705,
8520                         0x00000000, 0xffffffff },
8521                 { RCVDBDI_JUMBO_BD+4, TG3_FL_NOT_5705,
8522                         0x00000000, 0xffffffff },
8523                 { RCVDBDI_JUMBO_BD+8, TG3_FL_NOT_5705,
8524                         0x00000000, 0x00000003 },
8525                 { RCVDBDI_JUMBO_BD+0xc, TG3_FL_NOT_5705,
8526                         0x00000000, 0xffffffff },
8527                 { RCVDBDI_STD_BD+0, 0x0000,
8528                         0x00000000, 0xffffffff },
8529                 { RCVDBDI_STD_BD+4, 0x0000,
8530                         0x00000000, 0xffffffff },
8531                 { RCVDBDI_STD_BD+8, 0x0000,
8532                         0x00000000, 0xffff0002 },
8533                 { RCVDBDI_STD_BD+0xc, 0x0000,
8534                         0x00000000, 0xffffffff },
8535
8536                 /* Receive BD Initiator Control Registers. */
8537                 { RCVBDI_STD_THRESH, TG3_FL_NOT_5705,
8538                         0x00000000, 0xffffffff },
8539                 { RCVBDI_STD_THRESH, TG3_FL_5705,
8540                         0x00000000, 0x000003ff },
8541                 { RCVBDI_JUMBO_THRESH, TG3_FL_NOT_5705,
8542                         0x00000000, 0xffffffff },
8543
8544                 /* Host Coalescing Control Registers. */
8545                 { HOSTCC_MODE, TG3_FL_NOT_5705,
8546                         0x00000000, 0x00000004 },
8547                 { HOSTCC_MODE, TG3_FL_5705,
8548                         0x00000000, 0x000000f6 },
8549                 { HOSTCC_RXCOL_TICKS, TG3_FL_NOT_5705,
8550                         0x00000000, 0xffffffff },
8551                 { HOSTCC_RXCOL_TICKS, TG3_FL_5705,
8552                         0x00000000, 0x000003ff },
8553                 { HOSTCC_TXCOL_TICKS, TG3_FL_NOT_5705,
8554                         0x00000000, 0xffffffff },
8555                 { HOSTCC_TXCOL_TICKS, TG3_FL_5705,
8556                         0x00000000, 0x000003ff },
8557                 { HOSTCC_RXMAX_FRAMES, TG3_FL_NOT_5705,
8558                         0x00000000, 0xffffffff },
8559                 { HOSTCC_RXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8560                         0x00000000, 0x000000ff },
8561                 { HOSTCC_TXMAX_FRAMES, TG3_FL_NOT_5705,
8562                         0x00000000, 0xffffffff },
8563                 { HOSTCC_TXMAX_FRAMES, TG3_FL_5705 | TG3_FL_NOT_5788,
8564                         0x00000000, 0x000000ff },
8565                 { HOSTCC_RXCOAL_TICK_INT, TG3_FL_NOT_5705,
8566                         0x00000000, 0xffffffff },
8567                 { HOSTCC_TXCOAL_TICK_INT, TG3_FL_NOT_5705,
8568                         0x00000000, 0xffffffff },
8569                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8570                         0x00000000, 0xffffffff },
8571                 { HOSTCC_RXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8572                         0x00000000, 0x000000ff },
8573                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_NOT_5705,
8574                         0x00000000, 0xffffffff },
8575                 { HOSTCC_TXCOAL_MAXF_INT, TG3_FL_5705 | TG3_FL_NOT_5788,
8576                         0x00000000, 0x000000ff },
8577                 { HOSTCC_STAT_COAL_TICKS, TG3_FL_NOT_5705,
8578                         0x00000000, 0xffffffff },
8579                 { HOSTCC_STATS_BLK_HOST_ADDR, TG3_FL_NOT_5705,
8580                         0x00000000, 0xffffffff },
8581                 { HOSTCC_STATS_BLK_HOST_ADDR+4, TG3_FL_NOT_5705,
8582                         0x00000000, 0xffffffff },
8583                 { HOSTCC_STATUS_BLK_HOST_ADDR, 0x0000,
8584                         0x00000000, 0xffffffff },
8585                 { HOSTCC_STATUS_BLK_HOST_ADDR+4, 0x0000,
8586                         0x00000000, 0xffffffff },
8587                 { HOSTCC_STATS_BLK_NIC_ADDR, 0x0000,
8588                         0xffffffff, 0x00000000 },
8589                 { HOSTCC_STATUS_BLK_NIC_ADDR, 0x0000,
8590                         0xffffffff, 0x00000000 },
8591
8592                 /* Buffer Manager Control Registers. */
8593                 { BUFMGR_MB_POOL_ADDR, TG3_FL_NOT_5750,
8594                         0x00000000, 0x007fff80 },
8595                 { BUFMGR_MB_POOL_SIZE, TG3_FL_NOT_5750,
8596                         0x00000000, 0x007fffff },
8597                 { BUFMGR_MB_RDMA_LOW_WATER, 0x0000,
8598                         0x00000000, 0x0000003f },
8599                 { BUFMGR_MB_MACRX_LOW_WATER, 0x0000,
8600                         0x00000000, 0x000001ff },
8601                 { BUFMGR_MB_HIGH_WATER, 0x0000,
8602                         0x00000000, 0x000001ff },
8603                 { BUFMGR_DMA_DESC_POOL_ADDR, TG3_FL_NOT_5705,
8604                         0xffffffff, 0x00000000 },
8605                 { BUFMGR_DMA_DESC_POOL_SIZE, TG3_FL_NOT_5705,
8606                         0xffffffff, 0x00000000 },
8607
8608                 /* Mailbox Registers */
8609                 { GRCMBOX_RCVSTD_PROD_IDX+4, 0x0000,
8610                         0x00000000, 0x000001ff },
8611                 { GRCMBOX_RCVJUMBO_PROD_IDX+4, TG3_FL_NOT_5705,
8612                         0x00000000, 0x000001ff },
8613                 { GRCMBOX_RCVRET_CON_IDX_0+4, 0x0000,
8614                         0x00000000, 0x000007ff },
8615                 { GRCMBOX_SNDHOST_PROD_IDX_0+4, 0x0000,
8616                         0x00000000, 0x000001ff },
8617
8618                 { 0xffff, 0x0000, 0x00000000, 0x00000000 },
8619         };
8620
8621         is_5705 = is_5750 = 0;
8622         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8623                 is_5705 = 1;
8624                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
8625                         is_5750 = 1;
8626         }
8627
8628         for (i = 0; reg_tbl[i].offset != 0xffff; i++) {
8629                 if (is_5705 && (reg_tbl[i].flags & TG3_FL_NOT_5705))
8630                         continue;
8631
8632                 if (!is_5705 && (reg_tbl[i].flags & TG3_FL_5705))
8633                         continue;
8634
8635                 if ((tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
8636                     (reg_tbl[i].flags & TG3_FL_NOT_5788))
8637                         continue;
8638
8639                 if (is_5750 && (reg_tbl[i].flags & TG3_FL_NOT_5750))
8640                         continue;
8641
8642                 offset = (u32) reg_tbl[i].offset;
8643                 read_mask = reg_tbl[i].read_mask;
8644                 write_mask = reg_tbl[i].write_mask;
8645
8646                 /* Save the original register content */
8647                 save_val = tr32(offset);
8648
8649                 /* Determine the read-only value. */
8650                 read_val = save_val & read_mask;
8651
8652                 /* Write zero to the register, then make sure the read-only bits
8653                  * are not changed and the read/write bits are all zeros.
8654                  */
8655                 tw32(offset, 0);
8656
8657                 val = tr32(offset);
8658
8659                 /* Test the read-only and read/write bits. */
8660                 if (((val & read_mask) != read_val) || (val & write_mask))
8661                         goto out;
8662
8663                 /* Write ones to all the bits defined by RdMask and WrMask, then
8664                  * make sure the read-only bits are not changed and the
8665                  * read/write bits are all ones.
8666                  */
8667                 tw32(offset, read_mask | write_mask);
8668
8669                 val = tr32(offset);
8670
8671                 /* Test the read-only bits. */
8672                 if ((val & read_mask) != read_val)
8673                         goto out;
8674
8675                 /* Test the read/write bits. */
8676                 if ((val & write_mask) != write_mask)
8677                         goto out;
8678
8679                 tw32(offset, save_val);
8680         }
8681
8682         return 0;
8683
8684 out:
8685         if (netif_msg_hw(tp))
8686                 printk(KERN_ERR PFX "Register test failed at offset %x\n",
8687                        offset);
8688         tw32(offset, save_val);
8689         return -EIO;
8690 }
8691
8692 static int tg3_do_mem_test(struct tg3 *tp, u32 offset, u32 len)
8693 {
8694         static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0xaa55a55a };
8695         int i;
8696         u32 j;
8697
8698         for (i = 0; i < sizeof(test_pattern)/sizeof(u32); i++) {
8699                 for (j = 0; j < len; j += 4) {
8700                         u32 val;
8701
8702                         tg3_write_mem(tp, offset + j, test_pattern[i]);
8703                         tg3_read_mem(tp, offset + j, &val);
8704                         if (val != test_pattern[i])
8705                                 return -EIO;
8706                 }
8707         }
8708         return 0;
8709 }
8710
8711 static int tg3_test_memory(struct tg3 *tp)
8712 {
8713         static struct mem_entry {
8714                 u32 offset;
8715                 u32 len;
8716         } mem_tbl_570x[] = {
8717                 { 0x00000000, 0x00b50},
8718                 { 0x00002000, 0x1c000},
8719                 { 0xffffffff, 0x00000}
8720         }, mem_tbl_5705[] = {
8721                 { 0x00000100, 0x0000c},
8722                 { 0x00000200, 0x00008},
8723                 { 0x00004000, 0x00800},
8724                 { 0x00006000, 0x01000},
8725                 { 0x00008000, 0x02000},
8726                 { 0x00010000, 0x0e000},
8727                 { 0xffffffff, 0x00000}
8728         }, mem_tbl_5755[] = {
8729                 { 0x00000200, 0x00008},
8730                 { 0x00004000, 0x00800},
8731                 { 0x00006000, 0x00800},
8732                 { 0x00008000, 0x02000},
8733                 { 0x00010000, 0x0c000},
8734                 { 0xffffffff, 0x00000}
8735         }, mem_tbl_5906[] = {
8736                 { 0x00000200, 0x00008},
8737                 { 0x00004000, 0x00400},
8738                 { 0x00006000, 0x00400},
8739                 { 0x00008000, 0x01000},
8740                 { 0x00010000, 0x01000},
8741                 { 0xffffffff, 0x00000}
8742         };
8743         struct mem_entry *mem_tbl;
8744         int err = 0;
8745         int i;
8746
8747         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
8748                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
8749                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
8750                         mem_tbl = mem_tbl_5755;
8751                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
8752                         mem_tbl = mem_tbl_5906;
8753                 else
8754                         mem_tbl = mem_tbl_5705;
8755         } else
8756                 mem_tbl = mem_tbl_570x;
8757
8758         for (i = 0; mem_tbl[i].offset != 0xffffffff; i++) {
8759                 if ((err = tg3_do_mem_test(tp, mem_tbl[i].offset,
8760                     mem_tbl[i].len)) != 0)
8761                         break;
8762         }
8763
8764         return err;
8765 }
8766
8767 #define TG3_MAC_LOOPBACK        0
8768 #define TG3_PHY_LOOPBACK        1
8769
8770 static int tg3_run_loopback(struct tg3 *tp, int loopback_mode)
8771 {
8772         u32 mac_mode, rx_start_idx, rx_idx, tx_idx, opaque_key;
8773         u32 desc_idx;
8774         struct sk_buff *skb, *rx_skb;
8775         u8 *tx_data;
8776         dma_addr_t map;
8777         int num_pkts, tx_len, rx_len, i, err;
8778         struct tg3_rx_buffer_desc *desc;
8779
8780         if (loopback_mode == TG3_MAC_LOOPBACK) {
8781                 /* HW errata - mac loopback fails in some cases on 5780.
8782                  * Normal traffic and PHY loopback are not affected by
8783                  * errata.
8784                  */
8785                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)
8786                         return 0;
8787
8788                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8789                            MAC_MODE_PORT_INT_LPBACK | MAC_MODE_LINK_POLARITY;
8790                 if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
8791                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8792                 else
8793                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8794                 tw32(MAC_MODE, mac_mode);
8795         } else if (loopback_mode == TG3_PHY_LOOPBACK) {
8796                 u32 val;
8797
8798                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8799                         u32 phytest;
8800
8801                         if (!tg3_readphy(tp, MII_TG3_EPHY_TEST, &phytest)) {
8802                                 u32 phy;
8803
8804                                 tg3_writephy(tp, MII_TG3_EPHY_TEST,
8805                                              phytest | MII_TG3_EPHY_SHADOW_EN);
8806                                 if (!tg3_readphy(tp, 0x1b, &phy))
8807                                         tg3_writephy(tp, 0x1b, phy & ~0x20);
8808                                 if (!tg3_readphy(tp, 0x10, &phy))
8809                                         tg3_writephy(tp, 0x10, phy & ~0x4000);
8810                                 tg3_writephy(tp, MII_TG3_EPHY_TEST, phytest);
8811                         }
8812                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED100;
8813                 } else
8814                         val = BMCR_LOOPBACK | BMCR_FULLDPLX | BMCR_SPEED1000;
8815
8816                 tg3_writephy(tp, MII_BMCR, val);
8817                 udelay(40);
8818
8819                 mac_mode = (tp->mac_mode & ~MAC_MODE_PORT_MODE_MASK) |
8820                            MAC_MODE_LINK_POLARITY;
8821                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
8822                         tg3_writephy(tp, MII_TG3_EPHY_PTEST, 0x1800);
8823                         mac_mode |= MAC_MODE_PORT_MODE_MII;
8824                 } else
8825                         mac_mode |= MAC_MODE_PORT_MODE_GMII;
8826
8827                 /* reset to prevent losing 1st rx packet intermittently */
8828                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES) {
8829                         tw32_f(MAC_RX_MODE, RX_MODE_RESET);
8830                         udelay(10);
8831                         tw32_f(MAC_RX_MODE, tp->rx_mode);
8832                 }
8833                 if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
8834                         mac_mode &= ~MAC_MODE_LINK_POLARITY;
8835                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
8836                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
8837                 }
8838                 tw32(MAC_MODE, mac_mode);
8839         }
8840         else
8841                 return -EINVAL;
8842
8843         err = -EIO;
8844
8845         tx_len = 1514;
8846         skb = netdev_alloc_skb(tp->dev, tx_len);
8847         if (!skb)
8848                 return -ENOMEM;
8849
8850         tx_data = skb_put(skb, tx_len);
8851         memcpy(tx_data, tp->dev->dev_addr, 6);
8852         memset(tx_data + 6, 0x0, 8);
8853
8854         tw32(MAC_RX_MTU_SIZE, tx_len + 4);
8855
8856         for (i = 14; i < tx_len; i++)
8857                 tx_data[i] = (u8) (i & 0xff);
8858
8859         map = pci_map_single(tp->pdev, skb->data, tx_len, PCI_DMA_TODEVICE);
8860
8861         tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8862              HOSTCC_MODE_NOW);
8863
8864         udelay(10);
8865
8866         rx_start_idx = tp->hw_status->idx[0].rx_producer;
8867
8868         num_pkts = 0;
8869
8870         tg3_set_txd(tp, tp->tx_prod, map, tx_len, 0, 1);
8871
8872         tp->tx_prod++;
8873         num_pkts++;
8874
8875         tw32_tx_mbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW,
8876                      tp->tx_prod);
8877         tr32_mailbox(MAILBOX_SNDHOST_PROD_IDX_0 + TG3_64BIT_REG_LOW);
8878
8879         udelay(10);
8880
8881         /* 250 usec to allow enough time on some 10/100 Mbps devices.  */
8882         for (i = 0; i < 25; i++) {
8883                 tw32_f(HOSTCC_MODE, tp->coalesce_mode | HOSTCC_MODE_ENABLE |
8884                        HOSTCC_MODE_NOW);
8885
8886                 udelay(10);
8887
8888                 tx_idx = tp->hw_status->idx[0].tx_consumer;
8889                 rx_idx = tp->hw_status->idx[0].rx_producer;
8890                 if ((tx_idx == tp->tx_prod) &&
8891                     (rx_idx == (rx_start_idx + num_pkts)))
8892                         break;
8893         }
8894
8895         pci_unmap_single(tp->pdev, map, tx_len, PCI_DMA_TODEVICE);
8896         dev_kfree_skb(skb);
8897
8898         if (tx_idx != tp->tx_prod)
8899                 goto out;
8900
8901         if (rx_idx != rx_start_idx + num_pkts)
8902                 goto out;
8903
8904         desc = &tp->rx_rcb[rx_start_idx];
8905         desc_idx = desc->opaque & RXD_OPAQUE_INDEX_MASK;
8906         opaque_key = desc->opaque & RXD_OPAQUE_RING_MASK;
8907         if (opaque_key != RXD_OPAQUE_RING_STD)
8908                 goto out;
8909
8910         if ((desc->err_vlan & RXD_ERR_MASK) != 0 &&
8911             (desc->err_vlan != RXD_ERR_ODD_NIBBLE_RCVD_MII))
8912                 goto out;
8913
8914         rx_len = ((desc->idx_len & RXD_LEN_MASK) >> RXD_LEN_SHIFT) - 4;
8915         if (rx_len != tx_len)
8916                 goto out;
8917
8918         rx_skb = tp->rx_std_buffers[desc_idx].skb;
8919
8920         map = pci_unmap_addr(&tp->rx_std_buffers[desc_idx], mapping);
8921         pci_dma_sync_single_for_cpu(tp->pdev, map, rx_len, PCI_DMA_FROMDEVICE);
8922
8923         for (i = 14; i < tx_len; i++) {
8924                 if (*(rx_skb->data + i) != (u8) (i & 0xff))
8925                         goto out;
8926         }
8927         err = 0;
8928
8929         /* tg3_free_rings will unmap and free the rx_skb */
8930 out:
8931         return err;
8932 }
8933
8934 #define TG3_MAC_LOOPBACK_FAILED         1
8935 #define TG3_PHY_LOOPBACK_FAILED         2
8936 #define TG3_LOOPBACK_FAILED             (TG3_MAC_LOOPBACK_FAILED |      \
8937                                          TG3_PHY_LOOPBACK_FAILED)
8938
8939 static int tg3_test_loopback(struct tg3 *tp)
8940 {
8941         int err = 0;
8942
8943         if (!netif_running(tp->dev))
8944                 return TG3_LOOPBACK_FAILED;
8945
8946         err = tg3_reset_hw(tp, 1);
8947         if (err)
8948                 return TG3_LOOPBACK_FAILED;
8949
8950         if (tg3_run_loopback(tp, TG3_MAC_LOOPBACK))
8951                 err |= TG3_MAC_LOOPBACK_FAILED;
8952         if (!(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
8953                 if (tg3_run_loopback(tp, TG3_PHY_LOOPBACK))
8954                         err |= TG3_PHY_LOOPBACK_FAILED;
8955         }
8956
8957         return err;
8958 }
8959
8960 static void tg3_self_test(struct net_device *dev, struct ethtool_test *etest,
8961                           u64 *data)
8962 {
8963         struct tg3 *tp = netdev_priv(dev);
8964
8965         if (tp->link_config.phy_is_low_power)
8966                 tg3_set_power_state(tp, PCI_D0);
8967
8968         memset(data, 0, sizeof(u64) * TG3_NUM_TEST);
8969
8970         if (tg3_test_nvram(tp) != 0) {
8971                 etest->flags |= ETH_TEST_FL_FAILED;
8972                 data[0] = 1;
8973         }
8974         if (tg3_test_link(tp) != 0) {
8975                 etest->flags |= ETH_TEST_FL_FAILED;
8976                 data[1] = 1;
8977         }
8978         if (etest->flags & ETH_TEST_FL_OFFLINE) {
8979                 int err, irq_sync = 0;
8980
8981                 if (netif_running(dev)) {
8982                         tg3_netif_stop(tp);
8983                         irq_sync = 1;
8984                 }
8985
8986                 tg3_full_lock(tp, irq_sync);
8987
8988                 tg3_halt(tp, RESET_KIND_SUSPEND, 1);
8989                 err = tg3_nvram_lock(tp);
8990                 tg3_halt_cpu(tp, RX_CPU_BASE);
8991                 if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
8992                         tg3_halt_cpu(tp, TX_CPU_BASE);
8993                 if (!err)
8994                         tg3_nvram_unlock(tp);
8995
8996                 if (tp->tg3_flags2 & TG3_FLG2_MII_SERDES)
8997                         tg3_phy_reset(tp);
8998
8999                 if (tg3_test_registers(tp) != 0) {
9000                         etest->flags |= ETH_TEST_FL_FAILED;
9001                         data[2] = 1;
9002                 }
9003                 if (tg3_test_memory(tp) != 0) {
9004                         etest->flags |= ETH_TEST_FL_FAILED;
9005                         data[3] = 1;
9006                 }
9007                 if ((data[4] = tg3_test_loopback(tp)) != 0)
9008                         etest->flags |= ETH_TEST_FL_FAILED;
9009
9010                 tg3_full_unlock(tp);
9011
9012                 if (tg3_test_interrupt(tp) != 0) {
9013                         etest->flags |= ETH_TEST_FL_FAILED;
9014                         data[5] = 1;
9015                 }
9016
9017                 tg3_full_lock(tp, 0);
9018
9019                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
9020                 if (netif_running(dev)) {
9021                         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
9022                         if (!tg3_restart_hw(tp, 1))
9023                                 tg3_netif_start(tp);
9024                 }
9025
9026                 tg3_full_unlock(tp);
9027         }
9028         if (tp->link_config.phy_is_low_power)
9029                 tg3_set_power_state(tp, PCI_D3hot);
9030
9031 }
9032
9033 static int tg3_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
9034 {
9035         struct mii_ioctl_data *data = if_mii(ifr);
9036         struct tg3 *tp = netdev_priv(dev);
9037         int err;
9038
9039         switch(cmd) {
9040         case SIOCGMIIPHY:
9041                 data->phy_id = PHY_ADDR;
9042
9043                 /* fallthru */
9044         case SIOCGMIIREG: {
9045                 u32 mii_regval;
9046
9047                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9048                         break;                  /* We have no PHY */
9049
9050                 if (tp->link_config.phy_is_low_power)
9051                         return -EAGAIN;
9052
9053                 spin_lock_bh(&tp->lock);
9054                 err = tg3_readphy(tp, data->reg_num & 0x1f, &mii_regval);
9055                 spin_unlock_bh(&tp->lock);
9056
9057                 data->val_out = mii_regval;
9058
9059                 return err;
9060         }
9061
9062         case SIOCSMIIREG:
9063                 if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
9064                         break;                  /* We have no PHY */
9065
9066                 if (!capable(CAP_NET_ADMIN))
9067                         return -EPERM;
9068
9069                 if (tp->link_config.phy_is_low_power)
9070                         return -EAGAIN;
9071
9072                 spin_lock_bh(&tp->lock);
9073                 err = tg3_writephy(tp, data->reg_num & 0x1f, data->val_in);
9074                 spin_unlock_bh(&tp->lock);
9075
9076                 return err;
9077
9078         default:
9079                 /* do nothing */
9080                 break;
9081         }
9082         return -EOPNOTSUPP;
9083 }
9084
9085 #if TG3_VLAN_TAG_USED
9086 static void tg3_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
9087 {
9088         struct tg3 *tp = netdev_priv(dev);
9089
9090         if (netif_running(dev))
9091                 tg3_netif_stop(tp);
9092
9093         tg3_full_lock(tp, 0);
9094
9095         tp->vlgrp = grp;
9096
9097         /* Update RX_MODE_KEEP_VLAN_TAG bit in RX_MODE register. */
9098         __tg3_set_rx_mode(dev);
9099
9100         tg3_full_unlock(tp);
9101
9102         if (netif_running(dev))
9103                 tg3_netif_start(tp);
9104 }
9105
9106 static void tg3_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
9107 {
9108         struct tg3 *tp = netdev_priv(dev);
9109
9110         if (netif_running(dev))
9111                 tg3_netif_stop(tp);
9112
9113         tg3_full_lock(tp, 0);
9114         if (tp->vlgrp)
9115                 tp->vlgrp->vlan_devices[vid] = NULL;
9116         tg3_full_unlock(tp);
9117
9118         if (netif_running(dev))
9119                 tg3_netif_start(tp);
9120 }
9121 #endif
9122
9123 static int tg3_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9124 {
9125         struct tg3 *tp = netdev_priv(dev);
9126
9127         memcpy(ec, &tp->coal, sizeof(*ec));
9128         return 0;
9129 }
9130
9131 static int tg3_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
9132 {
9133         struct tg3 *tp = netdev_priv(dev);
9134         u32 max_rxcoal_tick_int = 0, max_txcoal_tick_int = 0;
9135         u32 max_stat_coal_ticks = 0, min_stat_coal_ticks = 0;
9136
9137         if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
9138                 max_rxcoal_tick_int = MAX_RXCOAL_TICK_INT;
9139                 max_txcoal_tick_int = MAX_TXCOAL_TICK_INT;
9140                 max_stat_coal_ticks = MAX_STAT_COAL_TICKS;
9141                 min_stat_coal_ticks = MIN_STAT_COAL_TICKS;
9142         }
9143
9144         if ((ec->rx_coalesce_usecs > MAX_RXCOL_TICKS) ||
9145             (ec->tx_coalesce_usecs > MAX_TXCOL_TICKS) ||
9146             (ec->rx_max_coalesced_frames > MAX_RXMAX_FRAMES) ||
9147             (ec->tx_max_coalesced_frames > MAX_TXMAX_FRAMES) ||
9148             (ec->rx_coalesce_usecs_irq > max_rxcoal_tick_int) ||
9149             (ec->tx_coalesce_usecs_irq > max_txcoal_tick_int) ||
9150             (ec->rx_max_coalesced_frames_irq > MAX_RXCOAL_MAXF_INT) ||
9151             (ec->tx_max_coalesced_frames_irq > MAX_TXCOAL_MAXF_INT) ||
9152             (ec->stats_block_coalesce_usecs > max_stat_coal_ticks) ||
9153             (ec->stats_block_coalesce_usecs < min_stat_coal_ticks))
9154                 return -EINVAL;
9155
9156         /* No rx interrupts will be generated if both are zero */
9157         if ((ec->rx_coalesce_usecs == 0) &&
9158             (ec->rx_max_coalesced_frames == 0))
9159                 return -EINVAL;
9160
9161         /* No tx interrupts will be generated if both are zero */
9162         if ((ec->tx_coalesce_usecs == 0) &&
9163             (ec->tx_max_coalesced_frames == 0))
9164                 return -EINVAL;
9165
9166         /* Only copy relevant parameters, ignore all others. */
9167         tp->coal.rx_coalesce_usecs = ec->rx_coalesce_usecs;
9168         tp->coal.tx_coalesce_usecs = ec->tx_coalesce_usecs;
9169         tp->coal.rx_max_coalesced_frames = ec->rx_max_coalesced_frames;
9170         tp->coal.tx_max_coalesced_frames = ec->tx_max_coalesced_frames;
9171         tp->coal.rx_coalesce_usecs_irq = ec->rx_coalesce_usecs_irq;
9172         tp->coal.tx_coalesce_usecs_irq = ec->tx_coalesce_usecs_irq;
9173         tp->coal.rx_max_coalesced_frames_irq = ec->rx_max_coalesced_frames_irq;
9174         tp->coal.tx_max_coalesced_frames_irq = ec->tx_max_coalesced_frames_irq;
9175         tp->coal.stats_block_coalesce_usecs = ec->stats_block_coalesce_usecs;
9176
9177         if (netif_running(dev)) {
9178                 tg3_full_lock(tp, 0);
9179                 __tg3_set_coalesce(tp, &tp->coal);
9180                 tg3_full_unlock(tp);
9181         }
9182         return 0;
9183 }
9184
9185 static const struct ethtool_ops tg3_ethtool_ops = {
9186         .get_settings           = tg3_get_settings,
9187         .set_settings           = tg3_set_settings,
9188         .get_drvinfo            = tg3_get_drvinfo,
9189         .get_regs_len           = tg3_get_regs_len,
9190         .get_regs               = tg3_get_regs,
9191         .get_wol                = tg3_get_wol,
9192         .set_wol                = tg3_set_wol,
9193         .get_msglevel           = tg3_get_msglevel,
9194         .set_msglevel           = tg3_set_msglevel,
9195         .nway_reset             = tg3_nway_reset,
9196         .get_link               = ethtool_op_get_link,
9197         .get_eeprom_len         = tg3_get_eeprom_len,
9198         .get_eeprom             = tg3_get_eeprom,
9199         .set_eeprom             = tg3_set_eeprom,
9200         .get_ringparam          = tg3_get_ringparam,
9201         .set_ringparam          = tg3_set_ringparam,
9202         .get_pauseparam         = tg3_get_pauseparam,
9203         .set_pauseparam         = tg3_set_pauseparam,
9204         .get_rx_csum            = tg3_get_rx_csum,
9205         .set_rx_csum            = tg3_set_rx_csum,
9206         .get_tx_csum            = ethtool_op_get_tx_csum,
9207         .set_tx_csum            = tg3_set_tx_csum,
9208         .get_sg                 = ethtool_op_get_sg,
9209         .set_sg                 = ethtool_op_set_sg,
9210         .get_tso                = ethtool_op_get_tso,
9211         .set_tso                = tg3_set_tso,
9212         .self_test_count        = tg3_get_test_count,
9213         .self_test              = tg3_self_test,
9214         .get_strings            = tg3_get_strings,
9215         .phys_id                = tg3_phys_id,
9216         .get_stats_count        = tg3_get_stats_count,
9217         .get_ethtool_stats      = tg3_get_ethtool_stats,
9218         .get_coalesce           = tg3_get_coalesce,
9219         .set_coalesce           = tg3_set_coalesce,
9220         .get_perm_addr          = ethtool_op_get_perm_addr,
9221 };
9222
9223 static void __devinit tg3_get_eeprom_size(struct tg3 *tp)
9224 {
9225         u32 cursize, val, magic;
9226
9227         tp->nvram_size = EEPROM_CHIP_SIZE;
9228
9229         if (tg3_nvram_read_swab(tp, 0, &magic) != 0)
9230                 return;
9231
9232         if ((magic != TG3_EEPROM_MAGIC) &&
9233             ((magic & TG3_EEPROM_MAGIC_FW_MSK) != TG3_EEPROM_MAGIC_FW) &&
9234             ((magic & TG3_EEPROM_MAGIC_HW_MSK) != TG3_EEPROM_MAGIC_HW))
9235                 return;
9236
9237         /*
9238          * Size the chip by reading offsets at increasing powers of two.
9239          * When we encounter our validation signature, we know the addressing
9240          * has wrapped around, and thus have our chip size.
9241          */
9242         cursize = 0x10;
9243
9244         while (cursize < tp->nvram_size) {
9245                 if (tg3_nvram_read_swab(tp, cursize, &val) != 0)
9246                         return;
9247
9248                 if (val == magic)
9249                         break;
9250
9251                 cursize <<= 1;
9252         }
9253
9254         tp->nvram_size = cursize;
9255 }
9256
9257 static void __devinit tg3_get_nvram_size(struct tg3 *tp)
9258 {
9259         u32 val;
9260
9261         if (tg3_nvram_read_swab(tp, 0, &val) != 0)
9262                 return;
9263
9264         /* Selfboot format */
9265         if (val != TG3_EEPROM_MAGIC) {
9266                 tg3_get_eeprom_size(tp);
9267                 return;
9268         }
9269
9270         if (tg3_nvram_read(tp, 0xf0, &val) == 0) {
9271                 if (val != 0) {
9272                         tp->nvram_size = (val >> 16) * 1024;
9273                         return;
9274                 }
9275         }
9276         tp->nvram_size = 0x20000;
9277 }
9278
9279 static void __devinit tg3_get_nvram_info(struct tg3 *tp)
9280 {
9281         u32 nvcfg1;
9282
9283         nvcfg1 = tr32(NVRAM_CFG1);
9284         if (nvcfg1 & NVRAM_CFG1_FLASHIF_ENAB) {
9285                 tp->tg3_flags2 |= TG3_FLG2_FLASH;
9286         }
9287         else {
9288                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9289                 tw32(NVRAM_CFG1, nvcfg1);
9290         }
9291
9292         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
9293             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
9294                 switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
9295                         case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
9296                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9297                                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9298                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9299                                 break;
9300                         case FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED:
9301                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9302                                 tp->nvram_pagesize = ATMEL_AT25F512_PAGE_SIZE;
9303                                 break;
9304                         case FLASH_VENDOR_ATMEL_EEPROM:
9305                                 tp->nvram_jedecnum = JEDEC_ATMEL;
9306                                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9307                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9308                                 break;
9309                         case FLASH_VENDOR_ST:
9310                                 tp->nvram_jedecnum = JEDEC_ST;
9311                                 tp->nvram_pagesize = ST_M45PEX0_PAGE_SIZE;
9312                                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9313                                 break;
9314                         case FLASH_VENDOR_SAIFUN:
9315                                 tp->nvram_jedecnum = JEDEC_SAIFUN;
9316                                 tp->nvram_pagesize = SAIFUN_SA25F0XX_PAGE_SIZE;
9317                                 break;
9318                         case FLASH_VENDOR_SST_SMALL:
9319                         case FLASH_VENDOR_SST_LARGE:
9320                                 tp->nvram_jedecnum = JEDEC_SST;
9321                                 tp->nvram_pagesize = SST_25VF0X0_PAGE_SIZE;
9322                                 break;
9323                 }
9324         }
9325         else {
9326                 tp->nvram_jedecnum = JEDEC_ATMEL;
9327                 tp->nvram_pagesize = ATMEL_AT45DB0X1B_PAGE_SIZE;
9328                 tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9329         }
9330 }
9331
9332 static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
9333 {
9334         u32 nvcfg1;
9335
9336         nvcfg1 = tr32(NVRAM_CFG1);
9337
9338         /* NVRAM protection for TPM */
9339         if (nvcfg1 & (1 << 27))
9340                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9341
9342         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9343                 case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
9344                 case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
9345                         tp->nvram_jedecnum = JEDEC_ATMEL;
9346                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9347                         break;
9348                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9349                         tp->nvram_jedecnum = JEDEC_ATMEL;
9350                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9351                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9352                         break;
9353                 case FLASH_5752VENDOR_ST_M45PE10:
9354                 case FLASH_5752VENDOR_ST_M45PE20:
9355                 case FLASH_5752VENDOR_ST_M45PE40:
9356                         tp->nvram_jedecnum = JEDEC_ST;
9357                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9358                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9359                         break;
9360         }
9361
9362         if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
9363                 switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
9364                         case FLASH_5752PAGE_SIZE_256:
9365                                 tp->nvram_pagesize = 256;
9366                                 break;
9367                         case FLASH_5752PAGE_SIZE_512:
9368                                 tp->nvram_pagesize = 512;
9369                                 break;
9370                         case FLASH_5752PAGE_SIZE_1K:
9371                                 tp->nvram_pagesize = 1024;
9372                                 break;
9373                         case FLASH_5752PAGE_SIZE_2K:
9374                                 tp->nvram_pagesize = 2048;
9375                                 break;
9376                         case FLASH_5752PAGE_SIZE_4K:
9377                                 tp->nvram_pagesize = 4096;
9378                                 break;
9379                         case FLASH_5752PAGE_SIZE_264:
9380                                 tp->nvram_pagesize = 264;
9381                                 break;
9382                 }
9383         }
9384         else {
9385                 /* For eeprom, set pagesize to maximum eeprom size */
9386                 tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9387
9388                 nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9389                 tw32(NVRAM_CFG1, nvcfg1);
9390         }
9391 }
9392
9393 static void __devinit tg3_get_5755_nvram_info(struct tg3 *tp)
9394 {
9395         u32 nvcfg1;
9396
9397         nvcfg1 = tr32(NVRAM_CFG1);
9398
9399         /* NVRAM protection for TPM */
9400         if (nvcfg1 & (1 << 27))
9401                 tp->tg3_flags2 |= TG3_FLG2_PROTECTED_NVRAM;
9402
9403         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9404                 case FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ:
9405                 case FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ:
9406                         tp->nvram_jedecnum = JEDEC_ATMEL;
9407                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9408                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9409
9410                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9411                         tw32(NVRAM_CFG1, nvcfg1);
9412                         break;
9413                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9414                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9415                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9416                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9417                 case FLASH_5755VENDOR_ATMEL_FLASH_4:
9418                         tp->nvram_jedecnum = JEDEC_ATMEL;
9419                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9420                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9421                         tp->nvram_pagesize = 264;
9422                         break;
9423                 case FLASH_5752VENDOR_ST_M45PE10:
9424                 case FLASH_5752VENDOR_ST_M45PE20:
9425                 case FLASH_5752VENDOR_ST_M45PE40:
9426                         tp->nvram_jedecnum = JEDEC_ST;
9427                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9428                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9429                         tp->nvram_pagesize = 256;
9430                         break;
9431         }
9432 }
9433
9434 static void __devinit tg3_get_5787_nvram_info(struct tg3 *tp)
9435 {
9436         u32 nvcfg1;
9437
9438         nvcfg1 = tr32(NVRAM_CFG1);
9439
9440         switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
9441                 case FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ:
9442                 case FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ:
9443                 case FLASH_5787VENDOR_MICRO_EEPROM_64KHZ:
9444                 case FLASH_5787VENDOR_MICRO_EEPROM_376KHZ:
9445                         tp->nvram_jedecnum = JEDEC_ATMEL;
9446                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9447                         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9448
9449                         nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
9450                         tw32(NVRAM_CFG1, nvcfg1);
9451                         break;
9452                 case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
9453                 case FLASH_5755VENDOR_ATMEL_FLASH_1:
9454                 case FLASH_5755VENDOR_ATMEL_FLASH_2:
9455                 case FLASH_5755VENDOR_ATMEL_FLASH_3:
9456                         tp->nvram_jedecnum = JEDEC_ATMEL;
9457                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9458                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9459                         tp->nvram_pagesize = 264;
9460                         break;
9461                 case FLASH_5752VENDOR_ST_M45PE10:
9462                 case FLASH_5752VENDOR_ST_M45PE20:
9463                 case FLASH_5752VENDOR_ST_M45PE40:
9464                         tp->nvram_jedecnum = JEDEC_ST;
9465                         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9466                         tp->tg3_flags2 |= TG3_FLG2_FLASH;
9467                         tp->nvram_pagesize = 256;
9468                         break;
9469         }
9470 }
9471
9472 static void __devinit tg3_get_5906_nvram_info(struct tg3 *tp)
9473 {
9474         tp->nvram_jedecnum = JEDEC_ATMEL;
9475         tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
9476         tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
9477 }
9478
9479 /* Chips other than 5700/5701 use the NVRAM for fetching info. */
9480 static void __devinit tg3_nvram_init(struct tg3 *tp)
9481 {
9482         tw32_f(GRC_EEPROM_ADDR,
9483              (EEPROM_ADDR_FSM_RESET |
9484               (EEPROM_DEFAULT_CLOCK_PERIOD <<
9485                EEPROM_ADDR_CLKPERD_SHIFT)));
9486
9487         msleep(1);
9488
9489         /* Enable seeprom accesses. */
9490         tw32_f(GRC_LOCAL_CTRL,
9491              tr32(GRC_LOCAL_CTRL) | GRC_LCLCTRL_AUTO_SEEPROM);
9492         udelay(100);
9493
9494         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
9495             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
9496                 tp->tg3_flags |= TG3_FLAG_NVRAM;
9497
9498                 if (tg3_nvram_lock(tp)) {
9499                         printk(KERN_WARNING PFX "%s: Cannot get nvarm lock, "
9500                                "tg3_nvram_init failed.\n", tp->dev->name);
9501                         return;
9502                 }
9503                 tg3_enable_nvram_access(tp);
9504
9505                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
9506                         tg3_get_5752_nvram_info(tp);
9507                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
9508                         tg3_get_5755_nvram_info(tp);
9509                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
9510                         tg3_get_5787_nvram_info(tp);
9511                 else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
9512                         tg3_get_5906_nvram_info(tp);
9513                 else
9514                         tg3_get_nvram_info(tp);
9515
9516                 tg3_get_nvram_size(tp);
9517
9518                 tg3_disable_nvram_access(tp);
9519                 tg3_nvram_unlock(tp);
9520
9521         } else {
9522                 tp->tg3_flags &= ~(TG3_FLAG_NVRAM | TG3_FLAG_NVRAM_BUFFERED);
9523
9524                 tg3_get_eeprom_size(tp);
9525         }
9526 }
9527
9528 static int tg3_nvram_read_using_eeprom(struct tg3 *tp,
9529                                         u32 offset, u32 *val)
9530 {
9531         u32 tmp;
9532         int i;
9533
9534         if (offset > EEPROM_ADDR_ADDR_MASK ||
9535             (offset % 4) != 0)
9536                 return -EINVAL;
9537
9538         tmp = tr32(GRC_EEPROM_ADDR) & ~(EEPROM_ADDR_ADDR_MASK |
9539                                         EEPROM_ADDR_DEVID_MASK |
9540                                         EEPROM_ADDR_READ);
9541         tw32(GRC_EEPROM_ADDR,
9542              tmp |
9543              (0 << EEPROM_ADDR_DEVID_SHIFT) |
9544              ((offset << EEPROM_ADDR_ADDR_SHIFT) &
9545               EEPROM_ADDR_ADDR_MASK) |
9546              EEPROM_ADDR_READ | EEPROM_ADDR_START);
9547
9548         for (i = 0; i < 1000; i++) {
9549                 tmp = tr32(GRC_EEPROM_ADDR);
9550
9551                 if (tmp & EEPROM_ADDR_COMPLETE)
9552                         break;
9553                 msleep(1);
9554         }
9555         if (!(tmp & EEPROM_ADDR_COMPLETE))
9556                 return -EBUSY;
9557
9558         *val = tr32(GRC_EEPROM_DATA);
9559         return 0;
9560 }
9561
9562 #define NVRAM_CMD_TIMEOUT 10000
9563
9564 static int tg3_nvram_exec_cmd(struct tg3 *tp, u32 nvram_cmd)
9565 {
9566         int i;
9567
9568         tw32(NVRAM_CMD, nvram_cmd);
9569         for (i = 0; i < NVRAM_CMD_TIMEOUT; i++) {
9570                 udelay(10);
9571                 if (tr32(NVRAM_CMD) & NVRAM_CMD_DONE) {
9572                         udelay(10);
9573                         break;
9574                 }
9575         }
9576         if (i == NVRAM_CMD_TIMEOUT) {
9577                 return -EBUSY;
9578         }
9579         return 0;
9580 }
9581
9582 static u32 tg3_nvram_phys_addr(struct tg3 *tp, u32 addr)
9583 {
9584         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9585             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9586             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9587             (tp->nvram_jedecnum == JEDEC_ATMEL))
9588
9589                 addr = ((addr / tp->nvram_pagesize) <<
9590                         ATMEL_AT45DB0X1B_PAGE_POS) +
9591                        (addr % tp->nvram_pagesize);
9592
9593         return addr;
9594 }
9595
9596 static u32 tg3_nvram_logical_addr(struct tg3 *tp, u32 addr)
9597 {
9598         if ((tp->tg3_flags & TG3_FLAG_NVRAM) &&
9599             (tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) &&
9600             (tp->tg3_flags2 & TG3_FLG2_FLASH) &&
9601             (tp->nvram_jedecnum == JEDEC_ATMEL))
9602
9603                 addr = ((addr >> ATMEL_AT45DB0X1B_PAGE_POS) *
9604                         tp->nvram_pagesize) +
9605                        (addr & ((1 << ATMEL_AT45DB0X1B_PAGE_POS) - 1));
9606
9607         return addr;
9608 }
9609
9610 static int tg3_nvram_read(struct tg3 *tp, u32 offset, u32 *val)
9611 {
9612         int ret;
9613
9614         if (!(tp->tg3_flags & TG3_FLAG_NVRAM))
9615                 return tg3_nvram_read_using_eeprom(tp, offset, val);
9616
9617         offset = tg3_nvram_phys_addr(tp, offset);
9618
9619         if (offset > NVRAM_ADDR_MSK)
9620                 return -EINVAL;
9621
9622         ret = tg3_nvram_lock(tp);
9623         if (ret)
9624                 return ret;
9625
9626         tg3_enable_nvram_access(tp);
9627
9628         tw32(NVRAM_ADDR, offset);
9629         ret = tg3_nvram_exec_cmd(tp, NVRAM_CMD_RD | NVRAM_CMD_GO |
9630                 NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_DONE);
9631
9632         if (ret == 0)
9633                 *val = swab32(tr32(NVRAM_RDDATA));
9634
9635         tg3_disable_nvram_access(tp);
9636
9637         tg3_nvram_unlock(tp);
9638
9639         return ret;
9640 }
9641
9642 static int tg3_nvram_read_swab(struct tg3 *tp, u32 offset, u32 *val)
9643 {
9644         int err;
9645         u32 tmp;
9646
9647         err = tg3_nvram_read(tp, offset, &tmp);
9648         *val = swab32(tmp);
9649         return err;
9650 }
9651
9652 static int tg3_nvram_write_block_using_eeprom(struct tg3 *tp,
9653                                     u32 offset, u32 len, u8 *buf)
9654 {
9655         int i, j, rc = 0;
9656         u32 val;
9657
9658         for (i = 0; i < len; i += 4) {
9659                 u32 addr, data;
9660
9661                 addr = offset + i;
9662
9663                 memcpy(&data, buf + i, 4);
9664
9665                 tw32(GRC_EEPROM_DATA, cpu_to_le32(data));
9666
9667                 val = tr32(GRC_EEPROM_ADDR);
9668                 tw32(GRC_EEPROM_ADDR, val | EEPROM_ADDR_COMPLETE);
9669
9670                 val &= ~(EEPROM_ADDR_ADDR_MASK | EEPROM_ADDR_DEVID_MASK |
9671                         EEPROM_ADDR_READ);
9672                 tw32(GRC_EEPROM_ADDR, val |
9673                         (0 << EEPROM_ADDR_DEVID_SHIFT) |
9674                         (addr & EEPROM_ADDR_ADDR_MASK) |
9675                         EEPROM_ADDR_START |
9676                         EEPROM_ADDR_WRITE);
9677
9678                 for (j = 0; j < 1000; j++) {
9679                         val = tr32(GRC_EEPROM_ADDR);
9680
9681                         if (val & EEPROM_ADDR_COMPLETE)
9682                                 break;
9683                         msleep(1);
9684                 }
9685                 if (!(val & EEPROM_ADDR_COMPLETE)) {
9686                         rc = -EBUSY;
9687                         break;
9688                 }
9689         }
9690
9691         return rc;
9692 }
9693
9694 /* offset and length are dword aligned */
9695 static int tg3_nvram_write_block_unbuffered(struct tg3 *tp, u32 offset, u32 len,
9696                 u8 *buf)
9697 {
9698         int ret = 0;
9699         u32 pagesize = tp->nvram_pagesize;
9700         u32 pagemask = pagesize - 1;
9701         u32 nvram_cmd;
9702         u8 *tmp;
9703
9704         tmp = kmalloc(pagesize, GFP_KERNEL);
9705         if (tmp == NULL)
9706                 return -ENOMEM;
9707
9708         while (len) {
9709                 int j;
9710                 u32 phy_addr, page_off, size;
9711
9712                 phy_addr = offset & ~pagemask;
9713
9714                 for (j = 0; j < pagesize; j += 4) {
9715                         if ((ret = tg3_nvram_read(tp, phy_addr + j,
9716                                                 (u32 *) (tmp + j))))
9717                                 break;
9718                 }
9719                 if (ret)
9720                         break;
9721
9722                 page_off = offset & pagemask;
9723                 size = pagesize;
9724                 if (len < size)
9725                         size = len;
9726
9727                 len -= size;
9728
9729                 memcpy(tmp + page_off, buf, size);
9730
9731                 offset = offset + (pagesize - page_off);
9732
9733                 tg3_enable_nvram_access(tp);
9734
9735                 /*
9736                  * Before we can erase the flash page, we need
9737                  * to issue a special "write enable" command.
9738                  */
9739                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9740
9741                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9742                         break;
9743
9744                 /* Erase the target page */
9745                 tw32(NVRAM_ADDR, phy_addr);
9746
9747                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR |
9748                         NVRAM_CMD_FIRST | NVRAM_CMD_LAST | NVRAM_CMD_ERASE;
9749
9750                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9751                         break;
9752
9753                 /* Issue another write enable to start the write. */
9754                 nvram_cmd = NVRAM_CMD_WREN | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9755
9756                 if (tg3_nvram_exec_cmd(tp, nvram_cmd))
9757                         break;
9758
9759                 for (j = 0; j < pagesize; j += 4) {
9760                         u32 data;
9761
9762                         data = *((u32 *) (tmp + j));
9763                         tw32(NVRAM_WRDATA, cpu_to_be32(data));
9764
9765                         tw32(NVRAM_ADDR, phy_addr + j);
9766
9767                         nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE |
9768                                 NVRAM_CMD_WR;
9769
9770                         if (j == 0)
9771                                 nvram_cmd |= NVRAM_CMD_FIRST;
9772                         else if (j == (pagesize - 4))
9773                                 nvram_cmd |= NVRAM_CMD_LAST;
9774
9775                         if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9776                                 break;
9777                 }
9778                 if (ret)
9779                         break;
9780         }
9781
9782         nvram_cmd = NVRAM_CMD_WRDI | NVRAM_CMD_GO | NVRAM_CMD_DONE;
9783         tg3_nvram_exec_cmd(tp, nvram_cmd);
9784
9785         kfree(tmp);
9786
9787         return ret;
9788 }
9789
9790 /* offset and length are dword aligned */
9791 static int tg3_nvram_write_block_buffered(struct tg3 *tp, u32 offset, u32 len,
9792                 u8 *buf)
9793 {
9794         int i, ret = 0;
9795
9796         for (i = 0; i < len; i += 4, offset += 4) {
9797                 u32 data, page_off, phy_addr, nvram_cmd;
9798
9799                 memcpy(&data, buf + i, 4);
9800                 tw32(NVRAM_WRDATA, cpu_to_be32(data));
9801
9802                 page_off = offset % tp->nvram_pagesize;
9803
9804                 phy_addr = tg3_nvram_phys_addr(tp, offset);
9805
9806                 tw32(NVRAM_ADDR, phy_addr);
9807
9808                 nvram_cmd = NVRAM_CMD_GO | NVRAM_CMD_DONE | NVRAM_CMD_WR;
9809
9810                 if ((page_off == 0) || (i == 0))
9811                         nvram_cmd |= NVRAM_CMD_FIRST;
9812                 if (page_off == (tp->nvram_pagesize - 4))
9813                         nvram_cmd |= NVRAM_CMD_LAST;
9814
9815                 if (i == (len - 4))
9816                         nvram_cmd |= NVRAM_CMD_LAST;
9817
9818                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) &&
9819                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755) &&
9820                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787) &&
9821                     (tp->nvram_jedecnum == JEDEC_ST) &&
9822                     (nvram_cmd & NVRAM_CMD_FIRST)) {
9823
9824                         if ((ret = tg3_nvram_exec_cmd(tp,
9825                                 NVRAM_CMD_WREN | NVRAM_CMD_GO |
9826                                 NVRAM_CMD_DONE)))
9827
9828                                 break;
9829                 }
9830                 if (!(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9831                         /* We always do complete word writes to eeprom. */
9832                         nvram_cmd |= (NVRAM_CMD_FIRST | NVRAM_CMD_LAST);
9833                 }
9834
9835                 if ((ret = tg3_nvram_exec_cmd(tp, nvram_cmd)))
9836                         break;
9837         }
9838         return ret;
9839 }
9840
9841 /* offset and length are dword aligned */
9842 static int tg3_nvram_write_block(struct tg3 *tp, u32 offset, u32 len, u8 *buf)
9843 {
9844         int ret;
9845
9846         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9847                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl &
9848                        ~GRC_LCLCTRL_GPIO_OUTPUT1);
9849                 udelay(40);
9850         }
9851
9852         if (!(tp->tg3_flags & TG3_FLAG_NVRAM)) {
9853                 ret = tg3_nvram_write_block_using_eeprom(tp, offset, len, buf);
9854         }
9855         else {
9856                 u32 grc_mode;
9857
9858                 ret = tg3_nvram_lock(tp);
9859                 if (ret)
9860                         return ret;
9861
9862                 tg3_enable_nvram_access(tp);
9863                 if ((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&
9864                     !(tp->tg3_flags2 & TG3_FLG2_PROTECTED_NVRAM))
9865                         tw32(NVRAM_WRITE1, 0x406);
9866
9867                 grc_mode = tr32(GRC_MODE);
9868                 tw32(GRC_MODE, grc_mode | GRC_MODE_NVRAM_WR_ENABLE);
9869
9870                 if ((tp->tg3_flags & TG3_FLAG_NVRAM_BUFFERED) ||
9871                         !(tp->tg3_flags2 & TG3_FLG2_FLASH)) {
9872
9873                         ret = tg3_nvram_write_block_buffered(tp, offset, len,
9874                                 buf);
9875                 }
9876                 else {
9877                         ret = tg3_nvram_write_block_unbuffered(tp, offset, len,
9878                                 buf);
9879                 }
9880
9881                 grc_mode = tr32(GRC_MODE);
9882                 tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
9883
9884                 tg3_disable_nvram_access(tp);
9885                 tg3_nvram_unlock(tp);
9886         }
9887
9888         if (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT) {
9889                 tw32_f(GRC_LOCAL_CTRL, tp->grc_local_ctrl);
9890                 udelay(40);
9891         }
9892
9893         return ret;
9894 }
9895
9896 struct subsys_tbl_ent {
9897         u16 subsys_vendor, subsys_devid;
9898         u32 phy_id;
9899 };
9900
9901 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
9902         /* Broadcom boards. */
9903         { PCI_VENDOR_ID_BROADCOM, 0x1644, PHY_ID_BCM5401 }, /* BCM95700A6 */
9904         { PCI_VENDOR_ID_BROADCOM, 0x0001, PHY_ID_BCM5701 }, /* BCM95701A5 */
9905         { PCI_VENDOR_ID_BROADCOM, 0x0002, PHY_ID_BCM8002 }, /* BCM95700T6 */
9906         { PCI_VENDOR_ID_BROADCOM, 0x0003, 0 },              /* BCM95700A9 */
9907         { PCI_VENDOR_ID_BROADCOM, 0x0005, PHY_ID_BCM5701 }, /* BCM95701T1 */
9908         { PCI_VENDOR_ID_BROADCOM, 0x0006, PHY_ID_BCM5701 }, /* BCM95701T8 */
9909         { PCI_VENDOR_ID_BROADCOM, 0x0007, 0 },              /* BCM95701A7 */
9910         { PCI_VENDOR_ID_BROADCOM, 0x0008, PHY_ID_BCM5701 }, /* BCM95701A10 */
9911         { PCI_VENDOR_ID_BROADCOM, 0x8008, PHY_ID_BCM5701 }, /* BCM95701A12 */
9912         { PCI_VENDOR_ID_BROADCOM, 0x0009, PHY_ID_BCM5703 }, /* BCM95703Ax1 */
9913         { PCI_VENDOR_ID_BROADCOM, 0x8009, PHY_ID_BCM5703 }, /* BCM95703Ax2 */
9914
9915         /* 3com boards. */
9916         { PCI_VENDOR_ID_3COM, 0x1000, PHY_ID_BCM5401 }, /* 3C996T */
9917         { PCI_VENDOR_ID_3COM, 0x1006, PHY_ID_BCM5701 }, /* 3C996BT */
9918         { PCI_VENDOR_ID_3COM, 0x1004, 0 },              /* 3C996SX */
9919         { PCI_VENDOR_ID_3COM, 0x1007, PHY_ID_BCM5701 }, /* 3C1000T */
9920         { PCI_VENDOR_ID_3COM, 0x1008, PHY_ID_BCM5701 }, /* 3C940BR01 */
9921
9922         /* DELL boards. */
9923         { PCI_VENDOR_ID_DELL, 0x00d1, PHY_ID_BCM5401 }, /* VIPER */
9924         { PCI_VENDOR_ID_DELL, 0x0106, PHY_ID_BCM5401 }, /* JAGUAR */
9925         { PCI_VENDOR_ID_DELL, 0x0109, PHY_ID_BCM5411 }, /* MERLOT */
9926         { PCI_VENDOR_ID_DELL, 0x010a, PHY_ID_BCM5411 }, /* SLIM_MERLOT */
9927
9928         /* Compaq boards. */
9929         { PCI_VENDOR_ID_COMPAQ, 0x007c, PHY_ID_BCM5701 }, /* BANSHEE */
9930         { PCI_VENDOR_ID_COMPAQ, 0x009a, PHY_ID_BCM5701 }, /* BANSHEE_2 */
9931         { PCI_VENDOR_ID_COMPAQ, 0x007d, 0 },              /* CHANGELING */
9932         { PCI_VENDOR_ID_COMPAQ, 0x0085, PHY_ID_BCM5701 }, /* NC7780 */
9933         { PCI_VENDOR_ID_COMPAQ, 0x0099, PHY_ID_BCM5701 }, /* NC7780_2 */
9934
9935         /* IBM boards. */
9936         { PCI_VENDOR_ID_IBM, 0x0281, 0 } /* IBM??? */
9937 };
9938
9939 static inline struct subsys_tbl_ent *lookup_by_subsys(struct tg3 *tp)
9940 {
9941         int i;
9942
9943         for (i = 0; i < ARRAY_SIZE(subsys_id_to_phy_id); i++) {
9944                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
9945                      tp->pdev->subsystem_vendor) &&
9946                     (subsys_id_to_phy_id[i].subsys_devid ==
9947                      tp->pdev->subsystem_device))
9948                         return &subsys_id_to_phy_id[i];
9949         }
9950         return NULL;
9951 }
9952
9953 static void __devinit tg3_get_eeprom_hw_cfg(struct tg3 *tp)
9954 {
9955         u32 val;
9956         u16 pmcsr;
9957
9958         /* On some early chips the SRAM cannot be accessed in D3hot state,
9959          * so need make sure we're in D0.
9960          */
9961         pci_read_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, &pmcsr);
9962         pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
9963         pci_write_config_word(tp->pdev, tp->pm_cap + PCI_PM_CTRL, pmcsr);
9964         msleep(1);
9965
9966         /* Make sure register accesses (indirect or otherwise)
9967          * will function correctly.
9968          */
9969         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
9970                                tp->misc_host_ctrl);
9971
9972         /* The memory arbiter has to be enabled in order for SRAM accesses
9973          * to succeed.  Normally on powerup the tg3 chip firmware will make
9974          * sure it is enabled, but other entities such as system netboot
9975          * code might disable it.
9976          */
9977         val = tr32(MEMARB_MODE);
9978         tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);
9979
9980         tp->phy_id = PHY_ID_INVALID;
9981         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
9982
9983         /* Assume an onboard device by default.  */
9984         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
9985
9986         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
9987                 if (!(tr32(PCIE_TRANSACTION_CFG) & PCIE_TRANS_CFG_LOM)) {
9988                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
9989                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
9990                 }
9991                 return;
9992         }
9993
9994         tg3_read_mem(tp, NIC_SRAM_DATA_SIG, &val);
9995         if (val == NIC_SRAM_DATA_SIG_MAGIC) {
9996                 u32 nic_cfg, led_cfg;
9997                 u32 nic_phy_id, ver, cfg2 = 0, eeprom_phy_id;
9998                 int eeprom_phy_serdes = 0;
9999
10000                 tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
10001                 tp->nic_sram_data_cfg = nic_cfg;
10002
10003                 tg3_read_mem(tp, NIC_SRAM_DATA_VER, &ver);
10004                 ver >>= NIC_SRAM_DATA_VER_SHIFT;
10005                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700) &&
10006                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) &&
10007                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5703) &&
10008                     (ver > 0) && (ver < 0x100))
10009                         tg3_read_mem(tp, NIC_SRAM_DATA_CFG_2, &cfg2);
10010
10011                 if ((nic_cfg & NIC_SRAM_DATA_CFG_PHY_TYPE_MASK) ==
10012                     NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER)
10013                         eeprom_phy_serdes = 1;
10014
10015                 tg3_read_mem(tp, NIC_SRAM_DATA_PHY_ID, &nic_phy_id);
10016                 if (nic_phy_id != 0) {
10017                         u32 id1 = nic_phy_id & NIC_SRAM_DATA_PHY_ID1_MASK;
10018                         u32 id2 = nic_phy_id & NIC_SRAM_DATA_PHY_ID2_MASK;
10019
10020                         eeprom_phy_id  = (id1 >> 16) << 10;
10021                         eeprom_phy_id |= (id2 & 0xfc00) << 16;
10022                         eeprom_phy_id |= (id2 & 0x03ff) <<  0;
10023                 } else
10024                         eeprom_phy_id = 0;
10025
10026                 tp->phy_id = eeprom_phy_id;
10027                 if (eeprom_phy_serdes) {
10028                         if (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)
10029                                 tp->tg3_flags2 |= TG3_FLG2_MII_SERDES;
10030                         else
10031                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10032                 }
10033
10034                 if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10035                         led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
10036                                     SHASTA_EXT_LED_MODE_MASK);
10037                 else
10038                         led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
10039
10040                 switch (led_cfg) {
10041                 default:
10042                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_1:
10043                         tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10044                         break;
10045
10046                 case NIC_SRAM_DATA_CFG_LED_MODE_PHY_2:
10047                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10048                         break;
10049
10050                 case NIC_SRAM_DATA_CFG_LED_MODE_MAC:
10051                         tp->led_ctrl = LED_CTRL_MODE_MAC;
10052
10053                         /* Default to PHY_1_MODE if 0 (MAC_MODE) is
10054                          * read on some older 5700/5701 bootcode.
10055                          */
10056                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10057                             ASIC_REV_5700 ||
10058                             GET_ASIC_REV(tp->pci_chip_rev_id) ==
10059                             ASIC_REV_5701)
10060                                 tp->led_ctrl = LED_CTRL_MODE_PHY_1;
10061
10062                         break;
10063
10064                 case SHASTA_EXT_LED_SHARED:
10065                         tp->led_ctrl = LED_CTRL_MODE_SHARED;
10066                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
10067                             tp->pci_chip_rev_id != CHIPREV_ID_5750_A1)
10068                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10069                                                  LED_CTRL_MODE_PHY_2);
10070                         break;
10071
10072                 case SHASTA_EXT_LED_MAC:
10073                         tp->led_ctrl = LED_CTRL_MODE_SHASTA_MAC;
10074                         break;
10075
10076                 case SHASTA_EXT_LED_COMBO:
10077                         tp->led_ctrl = LED_CTRL_MODE_COMBO;
10078                         if (tp->pci_chip_rev_id != CHIPREV_ID_5750_A0)
10079                                 tp->led_ctrl |= (LED_CTRL_MODE_PHY_1 |
10080                                                  LED_CTRL_MODE_PHY_2);
10081                         break;
10082
10083                 };
10084
10085                 if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10086                      GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) &&
10087                     tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL)
10088                         tp->led_ctrl = LED_CTRL_MODE_PHY_2;
10089
10090                 if (nic_cfg & NIC_SRAM_DATA_CFG_EEPROM_WP) {
10091                         tp->tg3_flags |= TG3_FLAG_EEPROM_WRITE_PROT;
10092                         if ((tp->pdev->subsystem_vendor ==
10093                              PCI_VENDOR_ID_ARIMA) &&
10094                             (tp->pdev->subsystem_device == 0x205a ||
10095                              tp->pdev->subsystem_device == 0x2063))
10096                                 tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10097                 } else {
10098                         tp->tg3_flags &= ~TG3_FLAG_EEPROM_WRITE_PROT;
10099                         tp->tg3_flags2 |= TG3_FLG2_IS_NIC;
10100                 }
10101
10102                 if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
10103                         tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
10104                         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
10105                                 tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
10106                 }
10107                 if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
10108                         tp->tg3_flags |= TG3_FLAG_SERDES_WOL_CAP;
10109
10110                 if (cfg2 & (1 << 17))
10111                         tp->tg3_flags2 |= TG3_FLG2_CAPACITIVE_COUPLING;
10112
10113                 /* serdes signal pre-emphasis in register 0x590 set by */
10114                 /* bootcode if bit 18 is set */
10115                 if (cfg2 & (1 << 18))
10116                         tp->tg3_flags2 |= TG3_FLG2_SERDES_PREEMPHASIS;
10117         }
10118 }
10119
10120 static int __devinit tg3_phy_probe(struct tg3 *tp)
10121 {
10122         u32 hw_phy_id_1, hw_phy_id_2;
10123         u32 hw_phy_id, hw_phy_id_masked;
10124         int err;
10125
10126         /* Reading the PHY ID register can conflict with ASF
10127          * firwmare access to the PHY hardware.
10128          */
10129         err = 0;
10130         if (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) {
10131                 hw_phy_id = hw_phy_id_masked = PHY_ID_INVALID;
10132         } else {
10133                 /* Now read the physical PHY_ID from the chip and verify
10134                  * that it is sane.  If it doesn't look good, we fall back
10135                  * to either the hard-coded table based PHY_ID and failing
10136                  * that the value found in the eeprom area.
10137                  */
10138                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
10139                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
10140
10141                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
10142                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
10143                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
10144
10145                 hw_phy_id_masked = hw_phy_id & PHY_ID_MASK;
10146         }
10147
10148         if (!err && KNOWN_PHY_ID(hw_phy_id_masked)) {
10149                 tp->phy_id = hw_phy_id;
10150                 if (hw_phy_id_masked == PHY_ID_BCM8002)
10151                         tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10152                 else
10153                         tp->tg3_flags2 &= ~TG3_FLG2_PHY_SERDES;
10154         } else {
10155                 if (tp->phy_id != PHY_ID_INVALID) {
10156                         /* Do nothing, phy ID already set up in
10157                          * tg3_get_eeprom_hw_cfg().
10158                          */
10159                 } else {
10160                         struct subsys_tbl_ent *p;
10161
10162                         /* No eeprom signature?  Try the hardcoded
10163                          * subsys device table.
10164                          */
10165                         p = lookup_by_subsys(tp);
10166                         if (!p)
10167                                 return -ENODEV;
10168
10169                         tp->phy_id = p->phy_id;
10170                         if (!tp->phy_id ||
10171                             tp->phy_id == PHY_ID_BCM8002)
10172                                 tp->tg3_flags2 |= TG3_FLG2_PHY_SERDES;
10173                 }
10174         }
10175
10176         if (!(tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) &&
10177             !(tp->tg3_flags & TG3_FLAG_ENABLE_ASF)) {
10178                 u32 bmsr, adv_reg, tg3_ctrl, mask;
10179
10180                 tg3_readphy(tp, MII_BMSR, &bmsr);
10181                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
10182                     (bmsr & BMSR_LSTATUS))
10183                         goto skip_phy_reset;
10184
10185                 err = tg3_phy_reset(tp);
10186                 if (err)
10187                         return err;
10188
10189                 adv_reg = (ADVERTISE_10HALF | ADVERTISE_10FULL |
10190                            ADVERTISE_100HALF | ADVERTISE_100FULL |
10191                            ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
10192                 tg3_ctrl = 0;
10193                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY)) {
10194                         tg3_ctrl = (MII_TG3_CTRL_ADV_1000_HALF |
10195                                     MII_TG3_CTRL_ADV_1000_FULL);
10196                         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10197                             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
10198                                 tg3_ctrl |= (MII_TG3_CTRL_AS_MASTER |
10199                                              MII_TG3_CTRL_ENABLE_AS_MASTER);
10200                 }
10201
10202                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
10203                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
10204                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
10205                 if (!tg3_copper_is_advertising_all(tp, mask)) {
10206                         tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10207
10208                         if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10209                                 tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10210
10211                         tg3_writephy(tp, MII_BMCR,
10212                                      BMCR_ANENABLE | BMCR_ANRESTART);
10213                 }
10214                 tg3_phy_set_wirespeed(tp);
10215
10216                 tg3_writephy(tp, MII_ADVERTISE, adv_reg);
10217                 if (!(tp->tg3_flags & TG3_FLAG_10_100_ONLY))
10218                         tg3_writephy(tp, MII_TG3_CTRL, tg3_ctrl);
10219         }
10220
10221 skip_phy_reset:
10222         if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
10223                 err = tg3_init_5401phy_dsp(tp);
10224                 if (err)
10225                         return err;
10226         }
10227
10228         if (!err && ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401)) {
10229                 err = tg3_init_5401phy_dsp(tp);
10230         }
10231
10232         if (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES)
10233                 tp->link_config.advertising =
10234                         (ADVERTISED_1000baseT_Half |
10235                          ADVERTISED_1000baseT_Full |
10236                          ADVERTISED_Autoneg |
10237                          ADVERTISED_FIBRE);
10238         if (tp->tg3_flags & TG3_FLAG_10_100_ONLY)
10239                 tp->link_config.advertising &=
10240                         ~(ADVERTISED_1000baseT_Half |
10241                           ADVERTISED_1000baseT_Full);
10242
10243         return err;
10244 }
10245
10246 static void __devinit tg3_read_partno(struct tg3 *tp)
10247 {
10248         unsigned char vpd_data[256];
10249         unsigned int i;
10250         u32 magic;
10251
10252         if (tg3_nvram_read_swab(tp, 0x0, &magic))
10253                 goto out_not_found;
10254
10255         if (magic == TG3_EEPROM_MAGIC) {
10256                 for (i = 0; i < 256; i += 4) {
10257                         u32 tmp;
10258
10259                         if (tg3_nvram_read(tp, 0x100 + i, &tmp))
10260                                 goto out_not_found;
10261
10262                         vpd_data[i + 0] = ((tmp >>  0) & 0xff);
10263                         vpd_data[i + 1] = ((tmp >>  8) & 0xff);
10264                         vpd_data[i + 2] = ((tmp >> 16) & 0xff);
10265                         vpd_data[i + 3] = ((tmp >> 24) & 0xff);
10266                 }
10267         } else {
10268                 int vpd_cap;
10269
10270                 vpd_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_VPD);
10271                 for (i = 0; i < 256; i += 4) {
10272                         u32 tmp, j = 0;
10273                         u16 tmp16;
10274
10275                         pci_write_config_word(tp->pdev, vpd_cap + PCI_VPD_ADDR,
10276                                               i);
10277                         while (j++ < 100) {
10278                                 pci_read_config_word(tp->pdev, vpd_cap +
10279                                                      PCI_VPD_ADDR, &tmp16);
10280                                 if (tmp16 & 0x8000)
10281                                         break;
10282                                 msleep(1);
10283                         }
10284                         if (!(tmp16 & 0x8000))
10285                                 goto out_not_found;
10286
10287                         pci_read_config_dword(tp->pdev, vpd_cap + PCI_VPD_DATA,
10288                                               &tmp);
10289                         tmp = cpu_to_le32(tmp);
10290                         memcpy(&vpd_data[i], &tmp, 4);
10291                 }
10292         }
10293
10294         /* Now parse and find the part number. */
10295         for (i = 0; i < 254; ) {
10296                 unsigned char val = vpd_data[i];
10297                 unsigned int block_end;
10298
10299                 if (val == 0x82 || val == 0x91) {
10300                         i = (i + 3 +
10301                              (vpd_data[i + 1] +
10302                               (vpd_data[i + 2] << 8)));
10303                         continue;
10304                 }
10305
10306                 if (val != 0x90)
10307                         goto out_not_found;
10308
10309                 block_end = (i + 3 +
10310                              (vpd_data[i + 1] +
10311                               (vpd_data[i + 2] << 8)));
10312                 i += 3;
10313
10314                 if (block_end > 256)
10315                         goto out_not_found;
10316
10317                 while (i < (block_end - 2)) {
10318                         if (vpd_data[i + 0] == 'P' &&
10319                             vpd_data[i + 1] == 'N') {
10320                                 int partno_len = vpd_data[i + 2];
10321
10322                                 i += 3;
10323                                 if (partno_len > 24 || (partno_len + i) > 256)
10324                                         goto out_not_found;
10325
10326                                 memcpy(tp->board_part_number,
10327                                        &vpd_data[i], partno_len);
10328
10329                                 /* Success. */
10330                                 return;
10331                         }
10332                         i += 3 + vpd_data[i + 2];
10333                 }
10334
10335                 /* Part number not found. */
10336                 goto out_not_found;
10337         }
10338
10339 out_not_found:
10340         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10341                 strcpy(tp->board_part_number, "BCM95906");
10342         else
10343                 strcpy(tp->board_part_number, "none");
10344 }
10345
10346 static void __devinit tg3_read_fw_ver(struct tg3 *tp)
10347 {
10348         u32 val, offset, start;
10349
10350         if (tg3_nvram_read_swab(tp, 0, &val))
10351                 return;
10352
10353         if (val != TG3_EEPROM_MAGIC)
10354                 return;
10355
10356         if (tg3_nvram_read_swab(tp, 0xc, &offset) ||
10357             tg3_nvram_read_swab(tp, 0x4, &start))
10358                 return;
10359
10360         offset = tg3_nvram_logical_addr(tp, offset);
10361         if (tg3_nvram_read_swab(tp, offset, &val))
10362                 return;
10363
10364         if ((val & 0xfc000000) == 0x0c000000) {
10365                 u32 ver_offset, addr;
10366                 int i;
10367
10368                 if (tg3_nvram_read_swab(tp, offset + 4, &val) ||
10369                     tg3_nvram_read_swab(tp, offset + 8, &ver_offset))
10370                         return;
10371
10372                 if (val != 0)
10373                         return;
10374
10375                 addr = offset + ver_offset - start;
10376                 for (i = 0; i < 16; i += 4) {
10377                         if (tg3_nvram_read(tp, addr + i, &val))
10378                                 return;
10379
10380                         val = cpu_to_le32(val);
10381                         memcpy(tp->fw_ver + i, &val, 4);
10382                 }
10383         }
10384 }
10385
10386 static int __devinit tg3_get_invariants(struct tg3 *tp)
10387 {
10388         static struct pci_device_id write_reorder_chipsets[] = {
10389                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10390                              PCI_DEVICE_ID_AMD_FE_GATE_700C) },
10391                 { PCI_DEVICE(PCI_VENDOR_ID_AMD,
10392                              PCI_DEVICE_ID_AMD_8131_BRIDGE) },
10393                 { PCI_DEVICE(PCI_VENDOR_ID_VIA,
10394                              PCI_DEVICE_ID_VIA_8385_0) },
10395                 { },
10396         };
10397         u32 misc_ctrl_reg;
10398         u32 cacheline_sz_reg;
10399         u32 pci_state_reg, grc_misc_cfg;
10400         u32 val;
10401         u16 pci_cmd;
10402         int err, pcie_cap;
10403
10404         /* Force memory write invalidate off.  If we leave it on,
10405          * then on 5700_BX chips we have to enable a workaround.
10406          * The workaround is to set the TG3PCI_DMA_RW_CTRL boundary
10407          * to match the cacheline size.  The Broadcom driver have this
10408          * workaround but turns MWI off all the times so never uses
10409          * it.  This seems to suggest that the workaround is insufficient.
10410          */
10411         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10412         pci_cmd &= ~PCI_COMMAND_INVALIDATE;
10413         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10414
10415         /* It is absolutely critical that TG3PCI_MISC_HOST_CTRL
10416          * has the register indirect write enable bit set before
10417          * we try to access any of the MMIO registers.  It is also
10418          * critical that the PCI-X hw workaround situation is decided
10419          * before that as well.
10420          */
10421         pci_read_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10422                               &misc_ctrl_reg);
10423
10424         tp->pci_chip_rev_id = (misc_ctrl_reg >>
10425                                MISC_HOST_CTRL_CHIPREV_SHIFT);
10426
10427         /* Wrong chip ID in 5752 A0. This code can be removed later
10428          * as A0 is not in production.
10429          */
10430         if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)
10431                 tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;
10432
10433         /* If we have 5702/03 A1 or A2 on certain ICH chipsets,
10434          * we need to disable memory and use config. cycles
10435          * only to access all registers. The 5702/03 chips
10436          * can mistakenly decode the special cycles from the
10437          * ICH chipsets as memory write cycles, causing corruption
10438          * of register and memory space. Only certain ICH bridges
10439          * will drive special cycles with non-zero data during the
10440          * address phase which can fall within the 5703's address
10441          * range. This is not an ICH bug as the PCI spec allows
10442          * non-zero address during special cycles. However, only
10443          * these ICH bridges are known to drive non-zero addresses
10444          * during special cycles.
10445          *
10446          * Since special cycles do not cross PCI bridges, we only
10447          * enable this workaround if the 5703 is on the secondary
10448          * bus of these ICH bridges.
10449          */
10450         if ((tp->pci_chip_rev_id == CHIPREV_ID_5703_A1) ||
10451             (tp->pci_chip_rev_id == CHIPREV_ID_5703_A2)) {
10452                 static struct tg3_dev_id {
10453                         u32     vendor;
10454                         u32     device;
10455                         u32     rev;
10456                 } ich_chipsets[] = {
10457                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_8,
10458                           PCI_ANY_ID },
10459                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_8,
10460                           PCI_ANY_ID },
10461                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_11,
10462                           0xa },
10463                         { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_6,
10464                           PCI_ANY_ID },
10465                         { },
10466                 };
10467                 struct tg3_dev_id *pci_id = &ich_chipsets[0];
10468                 struct pci_dev *bridge = NULL;
10469
10470                 while (pci_id->vendor != 0) {
10471                         bridge = pci_get_device(pci_id->vendor, pci_id->device,
10472                                                 bridge);
10473                         if (!bridge) {
10474                                 pci_id++;
10475                                 continue;
10476                         }
10477                         if (pci_id->rev != PCI_ANY_ID) {
10478                                 u8 rev;
10479
10480                                 pci_read_config_byte(bridge, PCI_REVISION_ID,
10481                                                      &rev);
10482                                 if (rev > pci_id->rev)
10483                                         continue;
10484                         }
10485                         if (bridge->subordinate &&
10486                             (bridge->subordinate->number ==
10487                              tp->pdev->bus->number)) {
10488
10489                                 tp->tg3_flags2 |= TG3_FLG2_ICH_WORKAROUND;
10490                                 pci_dev_put(bridge);
10491                                 break;
10492                         }
10493                 }
10494         }
10495
10496         /* The EPB bridge inside 5714, 5715, and 5780 cannot support
10497          * DMA addresses > 40-bit. This bridge may have other additional
10498          * 57xx devices behind it in some 4-port NIC designs for example.
10499          * Any tg3 device found behind the bridge will also need the 40-bit
10500          * DMA workaround.
10501          */
10502         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780 ||
10503             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
10504                 tp->tg3_flags2 |= TG3_FLG2_5780_CLASS;
10505                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10506                 tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);
10507         }
10508         else {
10509                 struct pci_dev *bridge = NULL;
10510
10511                 do {
10512                         bridge = pci_get_device(PCI_VENDOR_ID_SERVERWORKS,
10513                                                 PCI_DEVICE_ID_SERVERWORKS_EPB,
10514                                                 bridge);
10515                         if (bridge && bridge->subordinate &&
10516                             (bridge->subordinate->number <=
10517                              tp->pdev->bus->number) &&
10518                             (bridge->subordinate->subordinate >=
10519                              tp->pdev->bus->number)) {
10520                                 tp->tg3_flags |= TG3_FLAG_40BIT_DMA_BUG;
10521                                 pci_dev_put(bridge);
10522                                 break;
10523                         }
10524                 } while (bridge);
10525         }
10526
10527         /* Initialize misc host control in PCI block. */
10528         tp->misc_host_ctrl |= (misc_ctrl_reg &
10529                                MISC_HOST_CTRL_CHIPREV);
10530         pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10531                                tp->misc_host_ctrl);
10532
10533         pci_read_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10534                               &cacheline_sz_reg);
10535
10536         tp->pci_cacheline_sz = (cacheline_sz_reg >>  0) & 0xff;
10537         tp->pci_lat_timer    = (cacheline_sz_reg >>  8) & 0xff;
10538         tp->pci_hdr_type     = (cacheline_sz_reg >> 16) & 0xff;
10539         tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;
10540
10541         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10542             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10543             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10544             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10545             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
10546             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10547                 tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
10548
10549         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
10550             (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
10551                 tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
10552
10553         if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
10554                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10555                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10556                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10557                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_2;
10558                         tp->tg3_flags2 |= TG3_FLG2_1SHOT_MSI;
10559                 } else {
10560                         tp->tg3_flags2 |= TG3_FLG2_HW_TSO_1 |
10561                                           TG3_FLG2_HW_TSO_1_BUG;
10562                         if (GET_ASIC_REV(tp->pci_chip_rev_id) ==
10563                                 ASIC_REV_5750 &&
10564                             tp->pci_chip_rev_id >= CHIPREV_ID_5750_C2)
10565                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_1_BUG;
10566                 }
10567         }
10568
10569         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
10570             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
10571             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752 &&
10572             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5755 &&
10573             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5787 &&
10574             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10575                 tp->tg3_flags2 |= TG3_FLG2_JUMBO_CAPABLE;
10576
10577         pcie_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_EXP);
10578         if (pcie_cap != 0) {
10579                 tp->tg3_flags2 |= TG3_FLG2_PCI_EXPRESS;
10580                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10581                         u16 lnkctl;
10582
10583                         pci_read_config_word(tp->pdev,
10584                                              pcie_cap + PCI_EXP_LNKCTL,
10585                                              &lnkctl);
10586                         if (lnkctl & PCI_EXP_LNKCTL_CLKREQ_EN)
10587                                 tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
10588                 }
10589         }
10590
10591         /* If we have an AMD 762 or VIA K8T800 chipset, write
10592          * reordering to the mailbox registers done by the host
10593          * controller can cause major troubles.  We read back from
10594          * every mailbox register write to force the writes to be
10595          * posted to the chip in order.
10596          */
10597         if (pci_dev_present(write_reorder_chipsets) &&
10598             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
10599                 tp->tg3_flags |= TG3_FLAG_MBOX_WRITE_REORDER;
10600
10601         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10602             tp->pci_lat_timer < 64) {
10603                 tp->pci_lat_timer = 64;
10604
10605                 cacheline_sz_reg  = ((tp->pci_cacheline_sz & 0xff) <<  0);
10606                 cacheline_sz_reg |= ((tp->pci_lat_timer    & 0xff) <<  8);
10607                 cacheline_sz_reg |= ((tp->pci_hdr_type     & 0xff) << 16);
10608                 cacheline_sz_reg |= ((tp->pci_bist         & 0xff) << 24);
10609
10610                 pci_write_config_dword(tp->pdev, TG3PCI_CACHELINESZ,
10611                                        cacheline_sz_reg);
10612         }
10613
10614         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10615                               &pci_state_reg);
10616
10617         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0) {
10618                 tp->tg3_flags |= TG3_FLAG_PCIX_MODE;
10619
10620                 /* If this is a 5700 BX chipset, and we are in PCI-X
10621                  * mode, enable register write workaround.
10622                  *
10623                  * The workaround is to use indirect register accesses
10624                  * for all chip writes not to mailbox registers.
10625                  */
10626                 if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX) {
10627                         u32 pm_reg;
10628                         u16 pci_cmd;
10629
10630                         tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10631
10632                         /* The chip can have it's power management PCI config
10633                          * space registers clobbered due to this bug.
10634                          * So explicitly force the chip into D0 here.
10635                          */
10636                         pci_read_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10637                                               &pm_reg);
10638                         pm_reg &= ~PCI_PM_CTRL_STATE_MASK;
10639                         pm_reg |= PCI_PM_CTRL_PME_ENABLE | 0 /* D0 */;
10640                         pci_write_config_dword(tp->pdev, TG3PCI_PM_CTRL_STAT,
10641                                                pm_reg);
10642
10643                         /* Also, force SERR#/PERR# in PCI command. */
10644                         pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10645                         pci_cmd |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
10646                         pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10647                 }
10648         }
10649
10650         /* 5700 BX chips need to have their TX producer index mailboxes
10651          * written twice to workaround a bug.
10652          */
10653         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5700_BX)
10654                 tp->tg3_flags |= TG3_FLAG_TXD_MBOX_HWBUG;
10655
10656         /* Back to back register writes can cause problems on this chip,
10657          * the workaround is to read back all reg writes except those to
10658          * mailbox regs.  See tg3_write_indirect_reg32().
10659          *
10660          * PCI Express 5750_A0 rev chips need this workaround too.
10661          */
10662         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
10663             ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
10664              tp->pci_chip_rev_id == CHIPREV_ID_5750_A0))
10665                 tp->tg3_flags |= TG3_FLAG_5701_REG_WRITE_BUG;
10666
10667         if ((pci_state_reg & PCISTATE_BUS_SPEED_HIGH) != 0)
10668                 tp->tg3_flags |= TG3_FLAG_PCI_HIGH_SPEED;
10669         if ((pci_state_reg & PCISTATE_BUS_32BIT) != 0)
10670                 tp->tg3_flags |= TG3_FLAG_PCI_32BIT;
10671
10672         /* Chip-specific fixup from Broadcom driver */
10673         if ((tp->pci_chip_rev_id == CHIPREV_ID_5704_A0) &&
10674             (!(pci_state_reg & PCISTATE_RETRY_SAME_DMA))) {
10675                 pci_state_reg |= PCISTATE_RETRY_SAME_DMA;
10676                 pci_write_config_dword(tp->pdev, TG3PCI_PCISTATE, pci_state_reg);
10677         }
10678
10679         /* Default fast path register access methods */
10680         tp->read32 = tg3_read32;
10681         tp->write32 = tg3_write32;
10682         tp->read32_mbox = tg3_read32;
10683         tp->write32_mbox = tg3_write32;
10684         tp->write32_tx_mbox = tg3_write32;
10685         tp->write32_rx_mbox = tg3_write32;
10686
10687         /* Various workaround register access methods */
10688         if (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG)
10689                 tp->write32 = tg3_write_indirect_reg32;
10690         else if (tp->tg3_flags & TG3_FLAG_5701_REG_WRITE_BUG)
10691                 tp->write32 = tg3_write_flush_reg32;
10692
10693         if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
10694             (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
10695                 tp->write32_tx_mbox = tg3_write32_tx_mbox;
10696                 if (tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)
10697                         tp->write32_rx_mbox = tg3_write_flush_reg32;
10698         }
10699
10700         if (tp->tg3_flags2 & TG3_FLG2_ICH_WORKAROUND) {
10701                 tp->read32 = tg3_read_indirect_reg32;
10702                 tp->write32 = tg3_write_indirect_reg32;
10703                 tp->read32_mbox = tg3_read_indirect_mbox;
10704                 tp->write32_mbox = tg3_write_indirect_mbox;
10705                 tp->write32_tx_mbox = tg3_write_indirect_mbox;
10706                 tp->write32_rx_mbox = tg3_write_indirect_mbox;
10707
10708                 iounmap(tp->regs);
10709                 tp->regs = NULL;
10710
10711                 pci_read_config_word(tp->pdev, PCI_COMMAND, &pci_cmd);
10712                 pci_cmd &= ~PCI_COMMAND_MEMORY;
10713                 pci_write_config_word(tp->pdev, PCI_COMMAND, pci_cmd);
10714         }
10715         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
10716                 tp->read32_mbox = tg3_read32_mbox_5906;
10717                 tp->write32_mbox = tg3_write32_mbox_5906;
10718                 tp->write32_tx_mbox = tg3_write32_mbox_5906;
10719                 tp->write32_rx_mbox = tg3_write32_mbox_5906;
10720         }
10721
10722         if (tp->write32 == tg3_write_indirect_reg32 ||
10723             ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
10724              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10725               GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701)))
10726                 tp->tg3_flags |= TG3_FLAG_SRAM_USE_CONFIG;
10727
10728         /* Get eeprom hw config before calling tg3_set_power_state().
10729          * In particular, the TG3_FLG2_IS_NIC flag must be
10730          * determined before calling tg3_set_power_state() so that
10731          * we know whether or not to switch out of Vaux power.
10732          * When the flag is set, it means that GPIO1 is used for eeprom
10733          * write protect and also implies that it is a LOM where GPIOs
10734          * are not used to switch power.
10735          */
10736         tg3_get_eeprom_hw_cfg(tp);
10737
10738         /* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
10739          * GPIO1 driven high will bring 5700's external PHY out of reset.
10740          * It is also used as eeprom write protect on LOMs.
10741          */
10742         tp->grc_local_ctrl = GRC_LCLCTRL_INT_ON_ATTN | GRC_LCLCTRL_AUTO_SEEPROM;
10743         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10744             (tp->tg3_flags & TG3_FLAG_EEPROM_WRITE_PROT))
10745                 tp->grc_local_ctrl |= (GRC_LCLCTRL_GPIO_OE1 |
10746                                        GRC_LCLCTRL_GPIO_OUTPUT1);
10747         /* Unused GPIO3 must be driven as output on 5752 because there
10748          * are no pull-up resistors on unused GPIO pins.
10749          */
10750         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
10751                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_OE3;
10752
10753         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10754                 tp->grc_local_ctrl |= GRC_LCLCTRL_GPIO_UART_SEL;
10755
10756         /* Force the chip into D0. */
10757         err = tg3_set_power_state(tp, PCI_D0);
10758         if (err) {
10759                 printk(KERN_ERR PFX "(%s) transition to D0 failed\n",
10760                        pci_name(tp->pdev));
10761                 return err;
10762         }
10763
10764         /* 5700 B0 chips do not support checksumming correctly due
10765          * to hardware bugs.
10766          */
10767         if (tp->pci_chip_rev_id == CHIPREV_ID_5700_B0)
10768                 tp->tg3_flags |= TG3_FLAG_BROKEN_CHECKSUMS;
10769
10770         /* Derive initial jumbo mode from MTU assigned in
10771          * ether_setup() via the alloc_etherdev() call
10772          */
10773         if (tp->dev->mtu > ETH_DATA_LEN &&
10774             !(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
10775                 tp->tg3_flags |= TG3_FLAG_JUMBO_RING_ENABLE;
10776
10777         /* Determine WakeOnLan speed to use. */
10778         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
10779             tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
10780             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0 ||
10781             tp->pci_chip_rev_id == CHIPREV_ID_5701_B2) {
10782                 tp->tg3_flags &= ~(TG3_FLAG_WOL_SPEED_100MB);
10783         } else {
10784                 tp->tg3_flags |= TG3_FLAG_WOL_SPEED_100MB;
10785         }
10786
10787         /* A few boards don't want Ethernet@WireSpeed phy feature */
10788         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) ||
10789             ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
10790              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) &&
10791              (tp->pci_chip_rev_id != CHIPREV_ID_5705_A1)) ||
10792             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) ||
10793             (tp->tg3_flags2 & TG3_FLG2_ANY_SERDES))
10794                 tp->tg3_flags2 |= TG3_FLG2_NO_ETH_WIRE_SPEED;
10795
10796         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5703_AX ||
10797             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5704_AX)
10798                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADC_BUG;
10799         if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
10800                 tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
10801
10802         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
10803                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10804                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787) {
10805                         if (tp->pdev->device != PCI_DEVICE_ID_TIGON3_5756 &&
10806                             tp->pdev->device != PCI_DEVICE_ID_TIGON3_5722)
10807                                 tp->tg3_flags2 |= TG3_FLG2_PHY_JITTER_BUG;
10808                         if (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5755M)
10809                                 tp->tg3_flags2 |= TG3_FLG2_PHY_ADJUST_TRIM;
10810                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906)
10811                         tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
10812         }
10813
10814         tp->coalesce_mode = 0;
10815         if (GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_AX &&
10816             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5700_BX)
10817                 tp->coalesce_mode |= HOSTCC_MODE_32BYTE;
10818
10819         /* Initialize MAC MI mode, polling disabled. */
10820         tw32_f(MAC_MI_MODE, tp->mi_mode);
10821         udelay(80);
10822
10823         /* Initialize data/descriptor byte/word swapping. */
10824         val = tr32(GRC_MODE);
10825         val &= GRC_MODE_HOST_STACKUP;
10826         tw32(GRC_MODE, val | tp->grc_mode);
10827
10828         tg3_switch_clocks(tp);
10829
10830         /* Clear this out for sanity. */
10831         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
10832
10833         pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
10834                               &pci_state_reg);
10835         if ((pci_state_reg & PCISTATE_CONV_PCI_MODE) == 0 &&
10836             (tp->tg3_flags & TG3_FLAG_PCIX_TARGET_HWBUG) == 0) {
10837                 u32 chiprevid = GET_CHIP_REV_ID(tp->misc_host_ctrl);
10838
10839                 if (chiprevid == CHIPREV_ID_5701_A0 ||
10840                     chiprevid == CHIPREV_ID_5701_B0 ||
10841                     chiprevid == CHIPREV_ID_5701_B2 ||
10842                     chiprevid == CHIPREV_ID_5701_B5) {
10843                         void __iomem *sram_base;
10844
10845                         /* Write some dummy words into the SRAM status block
10846                          * area, see if it reads back correctly.  If the return
10847                          * value is bad, force enable the PCIX workaround.
10848                          */
10849                         sram_base = tp->regs + NIC_SRAM_WIN_BASE + NIC_SRAM_STATS_BLK;
10850
10851                         writel(0x00000000, sram_base);
10852                         writel(0x00000000, sram_base + 4);
10853                         writel(0xffffffff, sram_base + 4);
10854                         if (readl(sram_base) != 0x00000000)
10855                                 tp->tg3_flags |= TG3_FLAG_PCIX_TARGET_HWBUG;
10856                 }
10857         }
10858
10859         udelay(50);
10860         tg3_nvram_init(tp);
10861
10862         grc_misc_cfg = tr32(GRC_MISC_CFG);
10863         grc_misc_cfg &= GRC_MISC_CFG_BOARD_ID_MASK;
10864
10865         /* Broadcom's driver says that CIOBE multisplit has a bug */
10866 #if 0
10867         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&
10868             grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5704CIOBE) {
10869                 tp->tg3_flags |= TG3_FLAG_SPLIT_MODE;
10870                 tp->split_mode_max_reqs = SPLIT_MODE_5704_MAX_REQ;
10871         }
10872 #endif
10873         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10874             (grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788 ||
10875              grc_misc_cfg == GRC_MISC_CFG_BOARD_ID_5788M))
10876                 tp->tg3_flags2 |= TG3_FLG2_IS_5788;
10877
10878         if (!(tp->tg3_flags2 & TG3_FLG2_IS_5788) &&
10879             (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700))
10880                 tp->tg3_flags |= TG3_FLAG_TAGGED_STATUS;
10881         if (tp->tg3_flags & TG3_FLAG_TAGGED_STATUS) {
10882                 tp->coalesce_mode |= (HOSTCC_MODE_CLRTICK_RXBD |
10883                                       HOSTCC_MODE_CLRTICK_TXBD);
10884
10885                 tp->misc_host_ctrl |= MISC_HOST_CTRL_TAGGED_STATUS;
10886                 pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
10887                                        tp->misc_host_ctrl);
10888         }
10889
10890         /* these are limited to 10/100 only */
10891         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 &&
10892              (grc_misc_cfg == 0x8000 || grc_misc_cfg == 0x4000)) ||
10893             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
10894              tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10895              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901 ||
10896               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5901_2 ||
10897               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5705F)) ||
10898             (tp->pdev->vendor == PCI_VENDOR_ID_BROADCOM &&
10899              (tp->pdev->device == PCI_DEVICE_ID_TIGON3_5751F ||
10900               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5753F ||
10901               tp->pdev->device == PCI_DEVICE_ID_TIGON3_5787F)) ||
10902             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10903                 tp->tg3_flags |= TG3_FLAG_10_100_ONLY;
10904
10905         err = tg3_phy_probe(tp);
10906         if (err) {
10907                 printk(KERN_ERR PFX "(%s) phy probe failed, err %d\n",
10908                        pci_name(tp->pdev), err);
10909                 /* ... but do not return immediately ... */
10910         }
10911
10912         tg3_read_partno(tp);
10913         tg3_read_fw_ver(tp);
10914
10915         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES) {
10916                 tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10917         } else {
10918                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10919                         tp->tg3_flags |= TG3_FLAG_USE_MI_INTERRUPT;
10920                 else
10921                         tp->tg3_flags &= ~TG3_FLAG_USE_MI_INTERRUPT;
10922         }
10923
10924         /* 5700 {AX,BX} chips have a broken status block link
10925          * change bit implementation, so we must use the
10926          * status register in those cases.
10927          */
10928         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700)
10929                 tp->tg3_flags |= TG3_FLAG_USE_LINKCHG_REG;
10930         else
10931                 tp->tg3_flags &= ~TG3_FLAG_USE_LINKCHG_REG;
10932
10933         /* The led_ctrl is set during tg3_phy_probe, here we might
10934          * have to force the link status polling mechanism based
10935          * upon subsystem IDs.
10936          */
10937         if (tp->pdev->subsystem_vendor == PCI_VENDOR_ID_DELL &&
10938             !(tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)) {
10939                 tp->tg3_flags |= (TG3_FLAG_USE_MI_INTERRUPT |
10940                                   TG3_FLAG_USE_LINKCHG_REG);
10941         }
10942
10943         /* For all SERDES we poll the MAC status register. */
10944         if (tp->tg3_flags2 & TG3_FLG2_PHY_SERDES)
10945                 tp->tg3_flags |= TG3_FLAG_POLL_SERDES;
10946         else
10947                 tp->tg3_flags &= ~TG3_FLAG_POLL_SERDES;
10948
10949         /* All chips before 5787 can get confused if TX buffers
10950          * straddle the 4GB address boundary in some cases.
10951          */
10952         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
10953             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
10954             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
10955                 tp->dev->hard_start_xmit = tg3_start_xmit;
10956         else
10957                 tp->dev->hard_start_xmit = tg3_start_xmit_dma_bug;
10958
10959         tp->rx_offset = 2;
10960         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 &&
10961             (tp->tg3_flags & TG3_FLAG_PCIX_MODE) != 0)
10962                 tp->rx_offset = 0;
10963
10964         tp->rx_std_max_post = TG3_RX_RING_SIZE;
10965
10966         /* Increment the rx prod index on the rx std ring by at most
10967          * 8 for these chips to workaround hw errata.
10968          */
10969         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
10970             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||
10971             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
10972                 tp->rx_std_max_post = 8;
10973
10974         /* By default, disable wake-on-lan.  User can change this
10975          * using ETHTOOL_SWOL.
10976          */
10977         tp->tg3_flags &= ~TG3_FLAG_WOL_ENABLE;
10978
10979         return err;
10980 }
10981
10982 #ifdef CONFIG_SPARC64
10983 static int __devinit tg3_get_macaddr_sparc(struct tg3 *tp)
10984 {
10985         struct net_device *dev = tp->dev;
10986         struct pci_dev *pdev = tp->pdev;
10987         struct pcidev_cookie *pcp = pdev->sysdata;
10988
10989         if (pcp != NULL) {
10990                 unsigned char *addr;
10991                 int len;
10992
10993                 addr = of_get_property(pcp->prom_node, "local-mac-address",
10994                                         &len);
10995                 if (addr && len == 6) {
10996                         memcpy(dev->dev_addr, addr, 6);
10997                         memcpy(dev->perm_addr, dev->dev_addr, 6);
10998                         return 0;
10999                 }
11000         }
11001         return -ENODEV;
11002 }
11003
11004 static int __devinit tg3_get_default_macaddr_sparc(struct tg3 *tp)
11005 {
11006         struct net_device *dev = tp->dev;
11007
11008         memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
11009         memcpy(dev->perm_addr, idprom->id_ethaddr, 6);
11010         return 0;
11011 }
11012 #endif
11013
11014 static int __devinit tg3_get_device_address(struct tg3 *tp)
11015 {
11016         struct net_device *dev = tp->dev;
11017         u32 hi, lo, mac_offset;
11018         int addr_ok = 0;
11019
11020 #ifdef CONFIG_SPARC64
11021         if (!tg3_get_macaddr_sparc(tp))
11022                 return 0;
11023 #endif
11024
11025         mac_offset = 0x7c;
11026         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11027             (tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) {
11028                 if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)
11029                         mac_offset = 0xcc;
11030                 if (tg3_nvram_lock(tp))
11031                         tw32_f(NVRAM_CMD, NVRAM_CMD_RESET);
11032                 else
11033                         tg3_nvram_unlock(tp);
11034         }
11035         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906)
11036                 mac_offset = 0x10;
11037
11038         /* First try to get it from MAC address mailbox. */
11039         tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_HIGH_MBOX, &hi);
11040         if ((hi >> 16) == 0x484b) {
11041                 dev->dev_addr[0] = (hi >>  8) & 0xff;
11042                 dev->dev_addr[1] = (hi >>  0) & 0xff;
11043
11044                 tg3_read_mem(tp, NIC_SRAM_MAC_ADDR_LOW_MBOX, &lo);
11045                 dev->dev_addr[2] = (lo >> 24) & 0xff;
11046                 dev->dev_addr[3] = (lo >> 16) & 0xff;
11047                 dev->dev_addr[4] = (lo >>  8) & 0xff;
11048                 dev->dev_addr[5] = (lo >>  0) & 0xff;
11049
11050                 /* Some old bootcode may report a 0 MAC address in SRAM */
11051                 addr_ok = is_valid_ether_addr(&dev->dev_addr[0]);
11052         }
11053         if (!addr_ok) {
11054                 /* Next, try NVRAM. */
11055                 if (!tg3_nvram_read(tp, mac_offset + 0, &hi) &&
11056                     !tg3_nvram_read(tp, mac_offset + 4, &lo)) {
11057                         dev->dev_addr[0] = ((hi >> 16) & 0xff);
11058                         dev->dev_addr[1] = ((hi >> 24) & 0xff);
11059                         dev->dev_addr[2] = ((lo >>  0) & 0xff);
11060                         dev->dev_addr[3] = ((lo >>  8) & 0xff);
11061                         dev->dev_addr[4] = ((lo >> 16) & 0xff);
11062                         dev->dev_addr[5] = ((lo >> 24) & 0xff);
11063                 }
11064                 /* Finally just fetch it out of the MAC control regs. */
11065                 else {
11066                         hi = tr32(MAC_ADDR_0_HIGH);
11067                         lo = tr32(MAC_ADDR_0_LOW);
11068
11069                         dev->dev_addr[5] = lo & 0xff;
11070                         dev->dev_addr[4] = (lo >> 8) & 0xff;
11071                         dev->dev_addr[3] = (lo >> 16) & 0xff;
11072                         dev->dev_addr[2] = (lo >> 24) & 0xff;
11073                         dev->dev_addr[1] = hi & 0xff;
11074                         dev->dev_addr[0] = (hi >> 8) & 0xff;
11075                 }
11076         }
11077
11078         if (!is_valid_ether_addr(&dev->dev_addr[0])) {
11079 #ifdef CONFIG_SPARC64
11080                 if (!tg3_get_default_macaddr_sparc(tp))
11081                         return 0;
11082 #endif
11083                 return -EINVAL;
11084         }
11085         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
11086         return 0;
11087 }
11088
11089 #define BOUNDARY_SINGLE_CACHELINE       1
11090 #define BOUNDARY_MULTI_CACHELINE        2
11091
11092 static u32 __devinit tg3_calc_dma_bndry(struct tg3 *tp, u32 val)
11093 {
11094         int cacheline_size;
11095         u8 byte;
11096         int goal;
11097
11098         pci_read_config_byte(tp->pdev, PCI_CACHE_LINE_SIZE, &byte);
11099         if (byte == 0)
11100                 cacheline_size = 1024;
11101         else
11102                 cacheline_size = (int) byte * 4;
11103
11104         /* On 5703 and later chips, the boundary bits have no
11105          * effect.
11106          */
11107         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11108             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701 &&
11109             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS))
11110                 goto out;
11111
11112 #if defined(CONFIG_PPC64) || defined(CONFIG_IA64) || defined(CONFIG_PARISC)
11113         goal = BOUNDARY_MULTI_CACHELINE;
11114 #else
11115 #if defined(CONFIG_SPARC64) || defined(CONFIG_ALPHA)
11116         goal = BOUNDARY_SINGLE_CACHELINE;
11117 #else
11118         goal = 0;
11119 #endif
11120 #endif
11121
11122         if (!goal)
11123                 goto out;
11124
11125         /* PCI controllers on most RISC systems tend to disconnect
11126          * when a device tries to burst across a cache-line boundary.
11127          * Therefore, letting tg3 do so just wastes PCI bandwidth.
11128          *
11129          * Unfortunately, for PCI-E there are only limited
11130          * write-side controls for this, and thus for reads
11131          * we will still get the disconnects.  We'll also waste
11132          * these PCI cycles for both read and write for chips
11133          * other than 5700 and 5701 which do not implement the
11134          * boundary bits.
11135          */
11136         if ((tp->tg3_flags & TG3_FLAG_PCIX_MODE) &&
11137             !(tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS)) {
11138                 switch (cacheline_size) {
11139                 case 16:
11140                 case 32:
11141                 case 64:
11142                 case 128:
11143                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11144                                 val |= (DMA_RWCTRL_READ_BNDRY_128_PCIX |
11145                                         DMA_RWCTRL_WRITE_BNDRY_128_PCIX);
11146                         } else {
11147                                 val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11148                                         DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11149                         }
11150                         break;
11151
11152                 case 256:
11153                         val |= (DMA_RWCTRL_READ_BNDRY_256_PCIX |
11154                                 DMA_RWCTRL_WRITE_BNDRY_256_PCIX);
11155                         break;
11156
11157                 default:
11158                         val |= (DMA_RWCTRL_READ_BNDRY_384_PCIX |
11159                                 DMA_RWCTRL_WRITE_BNDRY_384_PCIX);
11160                         break;
11161                 };
11162         } else if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11163                 switch (cacheline_size) {
11164                 case 16:
11165                 case 32:
11166                 case 64:
11167                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11168                                 val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11169                                 val |= DMA_RWCTRL_WRITE_BNDRY_64_PCIE;
11170                                 break;
11171                         }
11172                         /* fallthrough */
11173                 case 128:
11174                 default:
11175                         val &= ~DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE;
11176                         val |= DMA_RWCTRL_WRITE_BNDRY_128_PCIE;
11177                         break;
11178                 };
11179         } else {
11180                 switch (cacheline_size) {
11181                 case 16:
11182                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11183                                 val |= (DMA_RWCTRL_READ_BNDRY_16 |
11184                                         DMA_RWCTRL_WRITE_BNDRY_16);
11185                                 break;
11186                         }
11187                         /* fallthrough */
11188                 case 32:
11189                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11190                                 val |= (DMA_RWCTRL_READ_BNDRY_32 |
11191                                         DMA_RWCTRL_WRITE_BNDRY_32);
11192                                 break;
11193                         }
11194                         /* fallthrough */
11195                 case 64:
11196                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11197                                 val |= (DMA_RWCTRL_READ_BNDRY_64 |
11198                                         DMA_RWCTRL_WRITE_BNDRY_64);
11199                                 break;
11200                         }
11201                         /* fallthrough */
11202                 case 128:
11203                         if (goal == BOUNDARY_SINGLE_CACHELINE) {
11204                                 val |= (DMA_RWCTRL_READ_BNDRY_128 |
11205                                         DMA_RWCTRL_WRITE_BNDRY_128);
11206                                 break;
11207                         }
11208                         /* fallthrough */
11209                 case 256:
11210                         val |= (DMA_RWCTRL_READ_BNDRY_256 |
11211                                 DMA_RWCTRL_WRITE_BNDRY_256);
11212                         break;
11213                 case 512:
11214                         val |= (DMA_RWCTRL_READ_BNDRY_512 |
11215                                 DMA_RWCTRL_WRITE_BNDRY_512);
11216                         break;
11217                 case 1024:
11218                 default:
11219                         val |= (DMA_RWCTRL_READ_BNDRY_1024 |
11220                                 DMA_RWCTRL_WRITE_BNDRY_1024);
11221                         break;
11222                 };
11223         }
11224
11225 out:
11226         return val;
11227 }
11228
11229 static int __devinit tg3_do_test_dma(struct tg3 *tp, u32 *buf, dma_addr_t buf_dma, int size, int to_device)
11230 {
11231         struct tg3_internal_buffer_desc test_desc;
11232         u32 sram_dma_descs;
11233         int i, ret;
11234
11235         sram_dma_descs = NIC_SRAM_DMA_DESC_POOL_BASE;
11236
11237         tw32(FTQ_RCVBD_COMP_FIFO_ENQDEQ, 0);
11238         tw32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ, 0);
11239         tw32(RDMAC_STATUS, 0);
11240         tw32(WDMAC_STATUS, 0);
11241
11242         tw32(BUFMGR_MODE, 0);
11243         tw32(FTQ_RESET, 0);
11244
11245         test_desc.addr_hi = ((u64) buf_dma) >> 32;
11246         test_desc.addr_lo = buf_dma & 0xffffffff;
11247         test_desc.nic_mbuf = 0x00002100;
11248         test_desc.len = size;
11249
11250         /*
11251          * HP ZX1 was seeing test failures for 5701 cards running at 33Mhz
11252          * the *second* time the tg3 driver was getting loaded after an
11253          * initial scan.
11254          *
11255          * Broadcom tells me:
11256          *   ...the DMA engine is connected to the GRC block and a DMA
11257          *   reset may affect the GRC block in some unpredictable way...
11258          *   The behavior of resets to individual blocks has not been tested.
11259          *
11260          * Broadcom noted the GRC reset will also reset all sub-components.
11261          */
11262         if (to_device) {
11263                 test_desc.cqid_sqid = (13 << 8) | 2;
11264
11265                 tw32_f(RDMAC_MODE, RDMAC_MODE_ENABLE);
11266                 udelay(40);
11267         } else {
11268                 test_desc.cqid_sqid = (16 << 8) | 7;
11269
11270                 tw32_f(WDMAC_MODE, WDMAC_MODE_ENABLE);
11271                 udelay(40);
11272         }
11273         test_desc.flags = 0x00000005;
11274
11275         for (i = 0; i < (sizeof(test_desc) / sizeof(u32)); i++) {
11276                 u32 val;
11277
11278                 val = *(((u32 *)&test_desc) + i);
11279                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR,
11280                                        sram_dma_descs + (i * sizeof(u32)));
11281                 pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_DATA, val);
11282         }
11283         pci_write_config_dword(tp->pdev, TG3PCI_MEM_WIN_BASE_ADDR, 0);
11284
11285         if (to_device) {
11286                 tw32(FTQ_DMA_HIGH_READ_FIFO_ENQDEQ, sram_dma_descs);
11287         } else {
11288                 tw32(FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ, sram_dma_descs);
11289         }
11290
11291         ret = -ENODEV;
11292         for (i = 0; i < 40; i++) {
11293                 u32 val;
11294
11295                 if (to_device)
11296                         val = tr32(FTQ_RCVBD_COMP_FIFO_ENQDEQ);
11297                 else
11298                         val = tr32(FTQ_RCVDATA_COMP_FIFO_ENQDEQ);
11299                 if ((val & 0xffff) == sram_dma_descs) {
11300                         ret = 0;
11301                         break;
11302                 }
11303
11304                 udelay(100);
11305         }
11306
11307         return ret;
11308 }
11309
11310 #define TEST_BUFFER_SIZE        0x2000
11311
11312 static int __devinit tg3_test_dma(struct tg3 *tp)
11313 {
11314         dma_addr_t buf_dma;
11315         u32 *buf, saved_dma_rwctrl;
11316         int ret;
11317
11318         buf = pci_alloc_consistent(tp->pdev, TEST_BUFFER_SIZE, &buf_dma);
11319         if (!buf) {
11320                 ret = -ENOMEM;
11321                 goto out_nofree;
11322         }
11323
11324         tp->dma_rwctrl = ((0x7 << DMA_RWCTRL_PCI_WRITE_CMD_SHIFT) |
11325                           (0x6 << DMA_RWCTRL_PCI_READ_CMD_SHIFT));
11326
11327         tp->dma_rwctrl = tg3_calc_dma_bndry(tp, tp->dma_rwctrl);
11328
11329         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11330                 /* DMA read watermark not used on PCIE */
11331                 tp->dma_rwctrl |= 0x00180000;
11332         } else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
11333                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
11334                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
11335                         tp->dma_rwctrl |= 0x003f0000;
11336                 else
11337                         tp->dma_rwctrl |= 0x003f000f;
11338         } else {
11339                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11340                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) {
11341                         u32 ccval = (tr32(TG3PCI_CLOCK_CTRL) & 0x1f);
11342                         u32 read_water = 0x7;
11343
11344                         /* If the 5704 is behind the EPB bridge, we can
11345                          * do the less restrictive ONE_DMA workaround for
11346                          * better performance.
11347                          */
11348                         if ((tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) &&
11349                             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11350                                 tp->dma_rwctrl |= 0x8000;
11351                         else if (ccval == 0x6 || ccval == 0x7)
11352                                 tp->dma_rwctrl |= DMA_RWCTRL_ONE_DMA;
11353
11354                         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703)
11355                                 read_water = 4;
11356                         /* Set bit 23 to enable PCIX hw bug fix */
11357                         tp->dma_rwctrl |=
11358                                 (read_water << DMA_RWCTRL_READ_WATER_SHIFT) |
11359                                 (0x3 << DMA_RWCTRL_WRITE_WATER_SHIFT) |
11360                                 (1 << 23);
11361                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {
11362                         /* 5780 always in PCIX mode */
11363                         tp->dma_rwctrl |= 0x00144000;
11364                 } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714) {
11365                         /* 5714 always in PCIX mode */
11366                         tp->dma_rwctrl |= 0x00148000;
11367                 } else {
11368                         tp->dma_rwctrl |= 0x001b000f;
11369                 }
11370         }
11371
11372         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
11373             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704)
11374                 tp->dma_rwctrl &= 0xfffffff0;
11375
11376         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11377             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
11378                 /* Remove this if it causes problems for some boards. */
11379                 tp->dma_rwctrl |= DMA_RWCTRL_USE_MEM_READ_MULT;
11380
11381                 /* On 5700/5701 chips, we need to set this bit.
11382                  * Otherwise the chip will issue cacheline transactions
11383                  * to streamable DMA memory with not all the byte
11384                  * enables turned on.  This is an error on several
11385                  * RISC PCI controllers, in particular sparc64.
11386                  *
11387                  * On 5703/5704 chips, this bit has been reassigned
11388                  * a different meaning.  In particular, it is used
11389                  * on those chips to enable a PCI-X workaround.
11390                  */
11391                 tp->dma_rwctrl |= DMA_RWCTRL_ASSERT_ALL_BE;
11392         }
11393
11394         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11395
11396 #if 0
11397         /* Unneeded, already done by tg3_get_invariants.  */
11398         tg3_switch_clocks(tp);
11399 #endif
11400
11401         ret = 0;
11402         if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5700 &&
11403             GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701)
11404                 goto out;
11405
11406         /* It is best to perform DMA test with maximum write burst size
11407          * to expose the 5700/5701 write DMA bug.
11408          */
11409         saved_dma_rwctrl = tp->dma_rwctrl;
11410         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11411         tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11412
11413         while (1) {
11414                 u32 *p = buf, i;
11415
11416                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++)
11417                         p[i] = i;
11418
11419                 /* Send the buffer to the chip. */
11420                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 1);
11421                 if (ret) {
11422                         printk(KERN_ERR "tg3_test_dma() Write the buffer failed %d\n", ret);
11423                         break;
11424                 }
11425
11426 #if 0
11427                 /* validate data reached card RAM correctly. */
11428                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11429                         u32 val;
11430                         tg3_read_mem(tp, 0x2100 + (i*4), &val);
11431                         if (le32_to_cpu(val) != p[i]) {
11432                                 printk(KERN_ERR "  tg3_test_dma()  Card buffer corrupted on write! (%d != %d)\n", val, i);
11433                                 /* ret = -ENODEV here? */
11434                         }
11435                         p[i] = 0;
11436                 }
11437 #endif
11438                 /* Now read it back. */
11439                 ret = tg3_do_test_dma(tp, buf, buf_dma, TEST_BUFFER_SIZE, 0);
11440                 if (ret) {
11441                         printk(KERN_ERR "tg3_test_dma() Read the buffer failed %d\n", ret);
11442
11443                         break;
11444                 }
11445
11446                 /* Verify it. */
11447                 for (i = 0; i < TEST_BUFFER_SIZE / sizeof(u32); i++) {
11448                         if (p[i] == i)
11449                                 continue;
11450
11451                         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11452                             DMA_RWCTRL_WRITE_BNDRY_16) {
11453                                 tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11454                                 tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11455                                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11456                                 break;
11457                         } else {
11458                                 printk(KERN_ERR "tg3_test_dma() buffer corrupted on read back! (%d != %d)\n", p[i], i);
11459                                 ret = -ENODEV;
11460                                 goto out;
11461                         }
11462                 }
11463
11464                 if (i == (TEST_BUFFER_SIZE / sizeof(u32))) {
11465                         /* Success. */
11466                         ret = 0;
11467                         break;
11468                 }
11469         }
11470         if ((tp->dma_rwctrl & DMA_RWCTRL_WRITE_BNDRY_MASK) !=
11471             DMA_RWCTRL_WRITE_BNDRY_16) {
11472                 static struct pci_device_id dma_wait_state_chipsets[] = {
11473                         { PCI_DEVICE(PCI_VENDOR_ID_APPLE,
11474                                      PCI_DEVICE_ID_APPLE_UNI_N_PCI15) },
11475                         { },
11476                 };
11477
11478                 /* DMA test passed without adjusting DMA boundary,
11479                  * now look for chipsets that are known to expose the
11480                  * DMA bug without failing the test.
11481                  */
11482                 if (pci_dev_present(dma_wait_state_chipsets)) {
11483                         tp->dma_rwctrl &= ~DMA_RWCTRL_WRITE_BNDRY_MASK;
11484                         tp->dma_rwctrl |= DMA_RWCTRL_WRITE_BNDRY_16;
11485                 }
11486                 else
11487                         /* Safe to use the calculated DMA boundary. */
11488                         tp->dma_rwctrl = saved_dma_rwctrl;
11489
11490                 tw32(TG3PCI_DMA_RW_CTRL, tp->dma_rwctrl);
11491         }
11492
11493 out:
11494         pci_free_consistent(tp->pdev, TEST_BUFFER_SIZE, buf, buf_dma);
11495 out_nofree:
11496         return ret;
11497 }
11498
11499 static void __devinit tg3_init_link_config(struct tg3 *tp)
11500 {
11501         tp->link_config.advertising =
11502                 (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
11503                  ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
11504                  ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full |
11505                  ADVERTISED_Autoneg | ADVERTISED_MII);
11506         tp->link_config.speed = SPEED_INVALID;
11507         tp->link_config.duplex = DUPLEX_INVALID;
11508         tp->link_config.autoneg = AUTONEG_ENABLE;
11509         tp->link_config.active_speed = SPEED_INVALID;
11510         tp->link_config.active_duplex = DUPLEX_INVALID;
11511         tp->link_config.phy_is_low_power = 0;
11512         tp->link_config.orig_speed = SPEED_INVALID;
11513         tp->link_config.orig_duplex = DUPLEX_INVALID;
11514         tp->link_config.orig_autoneg = AUTONEG_INVALID;
11515 }
11516
11517 static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
11518 {
11519         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11520                 tp->bufmgr_config.mbuf_read_dma_low_water =
11521                         DEFAULT_MB_RDMA_LOW_WATER_5705;
11522                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11523                         DEFAULT_MB_MACRX_LOW_WATER_5705;
11524                 tp->bufmgr_config.mbuf_high_water =
11525                         DEFAULT_MB_HIGH_WATER_5705;
11526                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
11527                         tp->bufmgr_config.mbuf_mac_rx_low_water =
11528                                 DEFAULT_MB_MACRX_LOW_WATER_5906;
11529                         tp->bufmgr_config.mbuf_high_water =
11530                                 DEFAULT_MB_HIGH_WATER_5906;
11531                 }
11532
11533                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11534                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780;
11535                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11536                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780;
11537                 tp->bufmgr_config.mbuf_high_water_jumbo =
11538                         DEFAULT_MB_HIGH_WATER_JUMBO_5780;
11539         } else {
11540                 tp->bufmgr_config.mbuf_read_dma_low_water =
11541                         DEFAULT_MB_RDMA_LOW_WATER;
11542                 tp->bufmgr_config.mbuf_mac_rx_low_water =
11543                         DEFAULT_MB_MACRX_LOW_WATER;
11544                 tp->bufmgr_config.mbuf_high_water =
11545                         DEFAULT_MB_HIGH_WATER;
11546
11547                 tp->bufmgr_config.mbuf_read_dma_low_water_jumbo =
11548                         DEFAULT_MB_RDMA_LOW_WATER_JUMBO;
11549                 tp->bufmgr_config.mbuf_mac_rx_low_water_jumbo =
11550                         DEFAULT_MB_MACRX_LOW_WATER_JUMBO;
11551                 tp->bufmgr_config.mbuf_high_water_jumbo =
11552                         DEFAULT_MB_HIGH_WATER_JUMBO;
11553         }
11554
11555         tp->bufmgr_config.dma_low_water = DEFAULT_DMA_LOW_WATER;
11556         tp->bufmgr_config.dma_high_water = DEFAULT_DMA_HIGH_WATER;
11557 }
11558
11559 static char * __devinit tg3_phy_string(struct tg3 *tp)
11560 {
11561         switch (tp->phy_id & PHY_ID_MASK) {
11562         case PHY_ID_BCM5400:    return "5400";
11563         case PHY_ID_BCM5401:    return "5401";
11564         case PHY_ID_BCM5411:    return "5411";
11565         case PHY_ID_BCM5701:    return "5701";
11566         case PHY_ID_BCM5703:    return "5703";
11567         case PHY_ID_BCM5704:    return "5704";
11568         case PHY_ID_BCM5705:    return "5705";
11569         case PHY_ID_BCM5750:    return "5750";
11570         case PHY_ID_BCM5752:    return "5752";
11571         case PHY_ID_BCM5714:    return "5714";
11572         case PHY_ID_BCM5780:    return "5780";
11573         case PHY_ID_BCM5755:    return "5755";
11574         case PHY_ID_BCM5787:    return "5787";
11575         case PHY_ID_BCM5756:    return "5722/5756";
11576         case PHY_ID_BCM5906:    return "5906";
11577         case PHY_ID_BCM8002:    return "8002/serdes";
11578         case 0:                 return "serdes";
11579         default:                return "unknown";
11580         };
11581 }
11582
11583 static char * __devinit tg3_bus_string(struct tg3 *tp, char *str)
11584 {
11585         if (tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) {
11586                 strcpy(str, "PCI Express");
11587                 return str;
11588         } else if (tp->tg3_flags & TG3_FLAG_PCIX_MODE) {
11589                 u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL) & 0x1f;
11590
11591                 strcpy(str, "PCIX:");
11592
11593                 if ((clock_ctrl == 7) ||
11594                     ((tr32(GRC_MISC_CFG) & GRC_MISC_CFG_BOARD_ID_MASK) ==
11595                      GRC_MISC_CFG_BOARD_ID_5704CIOBE))
11596                         strcat(str, "133MHz");
11597                 else if (clock_ctrl == 0)
11598                         strcat(str, "33MHz");
11599                 else if (clock_ctrl == 2)
11600                         strcat(str, "50MHz");
11601                 else if (clock_ctrl == 4)
11602                         strcat(str, "66MHz");
11603                 else if (clock_ctrl == 6)
11604                         strcat(str, "100MHz");
11605         } else {
11606                 strcpy(str, "PCI:");
11607                 if (tp->tg3_flags & TG3_FLAG_PCI_HIGH_SPEED)
11608                         strcat(str, "66MHz");
11609                 else
11610                         strcat(str, "33MHz");
11611         }
11612         if (tp->tg3_flags & TG3_FLAG_PCI_32BIT)
11613                 strcat(str, ":32-bit");
11614         else
11615                 strcat(str, ":64-bit");
11616         return str;
11617 }
11618
11619 static struct pci_dev * __devinit tg3_find_peer(struct tg3 *tp)
11620 {
11621         struct pci_dev *peer;
11622         unsigned int func, devnr = tp->pdev->devfn & ~7;
11623
11624         for (func = 0; func < 8; func++) {
11625                 peer = pci_get_slot(tp->pdev->bus, devnr | func);
11626                 if (peer && peer != tp->pdev)
11627                         break;
11628                 pci_dev_put(peer);
11629         }
11630         /* 5704 can be configured in single-port mode, set peer to
11631          * tp->pdev in that case.
11632          */
11633         if (!peer) {
11634                 peer = tp->pdev;
11635                 return peer;
11636         }
11637
11638         /*
11639          * We don't need to keep the refcount elevated; there's no way
11640          * to remove one half of this device without removing the other
11641          */
11642         pci_dev_put(peer);
11643
11644         return peer;
11645 }
11646
11647 static void __devinit tg3_init_coal(struct tg3 *tp)
11648 {
11649         struct ethtool_coalesce *ec = &tp->coal;
11650
11651         memset(ec, 0, sizeof(*ec));
11652         ec->cmd = ETHTOOL_GCOALESCE;
11653         ec->rx_coalesce_usecs = LOW_RXCOL_TICKS;
11654         ec->tx_coalesce_usecs = LOW_TXCOL_TICKS;
11655         ec->rx_max_coalesced_frames = LOW_RXMAX_FRAMES;
11656         ec->tx_max_coalesced_frames = LOW_TXMAX_FRAMES;
11657         ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT;
11658         ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT;
11659         ec->rx_max_coalesced_frames_irq = DEFAULT_RXCOAL_MAXF_INT;
11660         ec->tx_max_coalesced_frames_irq = DEFAULT_TXCOAL_MAXF_INT;
11661         ec->stats_block_coalesce_usecs = DEFAULT_STAT_COAL_TICKS;
11662
11663         if (tp->coalesce_mode & (HOSTCC_MODE_CLRTICK_RXBD |
11664                                  HOSTCC_MODE_CLRTICK_TXBD)) {
11665                 ec->rx_coalesce_usecs = LOW_RXCOL_TICKS_CLRTCKS;
11666                 ec->rx_coalesce_usecs_irq = DEFAULT_RXCOAL_TICK_INT_CLRTCKS;
11667                 ec->tx_coalesce_usecs = LOW_TXCOL_TICKS_CLRTCKS;
11668                 ec->tx_coalesce_usecs_irq = DEFAULT_TXCOAL_TICK_INT_CLRTCKS;
11669         }
11670
11671         if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
11672                 ec->rx_coalesce_usecs_irq = 0;
11673                 ec->tx_coalesce_usecs_irq = 0;
11674                 ec->stats_block_coalesce_usecs = 0;
11675         }
11676 }
11677
11678 static int __devinit tg3_init_one(struct pci_dev *pdev,
11679                                   const struct pci_device_id *ent)
11680 {
11681         static int tg3_version_printed = 0;
11682         unsigned long tg3reg_base, tg3reg_len;
11683         struct net_device *dev;
11684         struct tg3 *tp;
11685         int i, err, pm_cap;
11686         char str[40];
11687         u64 dma_mask, persist_dma_mask;
11688
11689         if (tg3_version_printed++ == 0)
11690                 printk(KERN_INFO "%s", version);
11691
11692         err = pci_enable_device(pdev);
11693         if (err) {
11694                 printk(KERN_ERR PFX "Cannot enable PCI device, "
11695                        "aborting.\n");
11696                 return err;
11697         }
11698
11699         if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
11700                 printk(KERN_ERR PFX "Cannot find proper PCI device "
11701                        "base address, aborting.\n");
11702                 err = -ENODEV;
11703                 goto err_out_disable_pdev;
11704         }
11705
11706         err = pci_request_regions(pdev, DRV_MODULE_NAME);
11707         if (err) {
11708                 printk(KERN_ERR PFX "Cannot obtain PCI resources, "
11709                        "aborting.\n");
11710                 goto err_out_disable_pdev;
11711         }
11712
11713         pci_set_master(pdev);
11714
11715         /* Find power-management capability. */
11716         pm_cap = pci_find_capability(pdev, PCI_CAP_ID_PM);
11717         if (pm_cap == 0) {
11718                 printk(KERN_ERR PFX "Cannot find PowerManagement capability, "
11719                        "aborting.\n");
11720                 err = -EIO;
11721                 goto err_out_free_res;
11722         }
11723
11724         tg3reg_base = pci_resource_start(pdev, 0);
11725         tg3reg_len = pci_resource_len(pdev, 0);
11726
11727         dev = alloc_etherdev(sizeof(*tp));
11728         if (!dev) {
11729                 printk(KERN_ERR PFX "Etherdev alloc failed, aborting.\n");
11730                 err = -ENOMEM;
11731                 goto err_out_free_res;
11732         }
11733
11734         SET_MODULE_OWNER(dev);
11735         SET_NETDEV_DEV(dev, &pdev->dev);
11736
11737 #if TG3_VLAN_TAG_USED
11738         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
11739         dev->vlan_rx_register = tg3_vlan_rx_register;
11740         dev->vlan_rx_kill_vid = tg3_vlan_rx_kill_vid;
11741 #endif
11742
11743         tp = netdev_priv(dev);
11744         tp->pdev = pdev;
11745         tp->dev = dev;
11746         tp->pm_cap = pm_cap;
11747         tp->mac_mode = TG3_DEF_MAC_MODE;
11748         tp->rx_mode = TG3_DEF_RX_MODE;
11749         tp->tx_mode = TG3_DEF_TX_MODE;
11750         tp->mi_mode = MAC_MI_MODE_BASE;
11751         if (tg3_debug > 0)
11752                 tp->msg_enable = tg3_debug;
11753         else
11754                 tp->msg_enable = TG3_DEF_MSG_ENABLE;
11755
11756         /* The word/byte swap controls here control register access byte
11757          * swapping.  DMA data byte swapping is controlled in the GRC_MODE
11758          * setting below.
11759          */
11760         tp->misc_host_ctrl =
11761                 MISC_HOST_CTRL_MASK_PCI_INT |
11762                 MISC_HOST_CTRL_WORD_SWAP |
11763                 MISC_HOST_CTRL_INDIR_ACCESS |
11764                 MISC_HOST_CTRL_PCISTATE_RW;
11765
11766         /* The NONFRM (non-frame) byte/word swap controls take effect
11767          * on descriptor entries, anything which isn't packet data.
11768          *
11769          * The StrongARM chips on the board (one for tx, one for rx)
11770          * are running in big-endian mode.
11771          */
11772         tp->grc_mode = (GRC_MODE_WSWAP_DATA | GRC_MODE_BSWAP_DATA |
11773                         GRC_MODE_WSWAP_NONFRM_DATA);
11774 #ifdef __BIG_ENDIAN
11775         tp->grc_mode |= GRC_MODE_BSWAP_NONFRM_DATA;
11776 #endif
11777         spin_lock_init(&tp->lock);
11778         spin_lock_init(&tp->indirect_lock);
11779         INIT_WORK(&tp->reset_task, tg3_reset_task);
11780
11781         tp->regs = ioremap_nocache(tg3reg_base, tg3reg_len);
11782         if (tp->regs == 0UL) {
11783                 printk(KERN_ERR PFX "Cannot map device registers, "
11784                        "aborting.\n");
11785                 err = -ENOMEM;
11786                 goto err_out_free_dev;
11787         }
11788
11789         tg3_init_link_config(tp);
11790
11791         tp->rx_pending = TG3_DEF_RX_RING_PENDING;
11792         tp->rx_jumbo_pending = TG3_DEF_RX_JUMBO_RING_PENDING;
11793         tp->tx_pending = TG3_DEF_TX_RING_PENDING;
11794
11795         dev->open = tg3_open;
11796         dev->stop = tg3_close;
11797         dev->get_stats = tg3_get_stats;
11798         dev->set_multicast_list = tg3_set_rx_mode;
11799         dev->set_mac_address = tg3_set_mac_addr;
11800         dev->do_ioctl = tg3_ioctl;
11801         dev->tx_timeout = tg3_tx_timeout;
11802         dev->poll = tg3_poll;
11803         dev->ethtool_ops = &tg3_ethtool_ops;
11804         dev->weight = 64;
11805         dev->watchdog_timeo = TG3_TX_TIMEOUT;
11806         dev->change_mtu = tg3_change_mtu;
11807         dev->irq = pdev->irq;
11808 #ifdef CONFIG_NET_POLL_CONTROLLER
11809         dev->poll_controller = tg3_poll_controller;
11810 #endif
11811
11812         err = tg3_get_invariants(tp);
11813         if (err) {
11814                 printk(KERN_ERR PFX "Problem fetching invariants of chip, "
11815                        "aborting.\n");
11816                 goto err_out_iounmap;
11817         }
11818
11819         /* The EPB bridge inside 5714, 5715, and 5780 and any
11820          * device behind the EPB cannot support DMA addresses > 40-bit.
11821          * On 64-bit systems with IOMMU, use 40-bit dma_mask.
11822          * On 64-bit systems without IOMMU, use 64-bit dma_mask and
11823          * do DMA address check in tg3_start_xmit().
11824          */
11825         if (tp->tg3_flags2 & TG3_FLG2_IS_5788)
11826                 persist_dma_mask = dma_mask = DMA_32BIT_MASK;
11827         else if (tp->tg3_flags & TG3_FLAG_40BIT_DMA_BUG) {
11828                 persist_dma_mask = dma_mask = DMA_40BIT_MASK;
11829 #ifdef CONFIG_HIGHMEM
11830                 dma_mask = DMA_64BIT_MASK;
11831 #endif
11832         } else
11833                 persist_dma_mask = dma_mask = DMA_64BIT_MASK;
11834
11835         /* Configure DMA attributes. */
11836         if (dma_mask > DMA_32BIT_MASK) {
11837                 err = pci_set_dma_mask(pdev, dma_mask);
11838                 if (!err) {
11839                         dev->features |= NETIF_F_HIGHDMA;
11840                         err = pci_set_consistent_dma_mask(pdev,
11841                                                           persist_dma_mask);
11842                         if (err < 0) {
11843                                 printk(KERN_ERR PFX "Unable to obtain 64 bit "
11844                                        "DMA for consistent allocations\n");
11845                                 goto err_out_iounmap;
11846                         }
11847                 }
11848         }
11849         if (err || dma_mask == DMA_32BIT_MASK) {
11850                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
11851                 if (err) {
11852                         printk(KERN_ERR PFX "No usable DMA configuration, "
11853                                "aborting.\n");
11854                         goto err_out_iounmap;
11855                 }
11856         }
11857
11858         tg3_init_bufmgr_config(tp);
11859
11860         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11861                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11862         }
11863         else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
11864             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701 ||
11865             tp->pci_chip_rev_id == CHIPREV_ID_5705_A0 ||
11866             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906 ||
11867             (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0) {
11868                 tp->tg3_flags2 &= ~TG3_FLG2_TSO_CAPABLE;
11869         } else {
11870                 tp->tg3_flags2 |= TG3_FLG2_TSO_CAPABLE;
11871         }
11872
11873         /* TSO is on by default on chips that support hardware TSO.
11874          * Firmware TSO on older chips gives lower performance, so it
11875          * is off by default, but can be enabled using ethtool.
11876          */
11877         if (tp->tg3_flags2 & TG3_FLG2_HW_TSO) {
11878                 dev->features |= NETIF_F_TSO;
11879                 if ((tp->tg3_flags2 & TG3_FLG2_HW_TSO_2) &&
11880                     (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5906))
11881                         dev->features |= NETIF_F_TSO6;
11882         }
11883
11884
11885         if (tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 &&
11886             !(tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) &&
11887             !(tr32(TG3PCI_PCISTATE) & PCISTATE_BUS_SPEED_HIGH)) {
11888                 tp->tg3_flags2 |= TG3_FLG2_MAX_RXPEND_64;
11889                 tp->rx_pending = 63;
11890         }
11891
11892         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
11893             (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
11894                 tp->pdev_peer = tg3_find_peer(tp);
11895
11896         err = tg3_get_device_address(tp);
11897         if (err) {
11898                 printk(KERN_ERR PFX "Could not obtain valid ethernet address, "
11899                        "aborting.\n");
11900                 goto err_out_iounmap;
11901         }
11902
11903         /*
11904          * Reset chip in case UNDI or EFI driver did not shutdown
11905          * DMA self test will enable WDMAC and we'll see (spurious)
11906          * pending DMA on the PCI bus at that point.
11907          */
11908         if ((tr32(HOSTCC_MODE) & HOSTCC_MODE_ENABLE) ||
11909             (tr32(WDMAC_MODE) & WDMAC_MODE_ENABLE)) {
11910                 pci_save_state(tp->pdev);
11911                 tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);
11912                 tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
11913         }
11914
11915         err = tg3_test_dma(tp);
11916         if (err) {
11917                 printk(KERN_ERR PFX "DMA engine test failed, aborting.\n");
11918                 goto err_out_iounmap;
11919         }
11920
11921         /* Tigon3 can do ipv4 only... and some chips have buggy
11922          * checksumming.
11923          */
11924         if ((tp->tg3_flags & TG3_FLAG_BROKEN_CHECKSUMS) == 0) {
11925                 if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
11926                     GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787)
11927                         dev->features |= NETIF_F_HW_CSUM;
11928                 else
11929                         dev->features |= NETIF_F_IP_CSUM;
11930                 dev->features |= NETIF_F_SG;
11931                 tp->tg3_flags |= TG3_FLAG_RX_CHECKSUMS;
11932         } else
11933                 tp->tg3_flags &= ~TG3_FLAG_RX_CHECKSUMS;
11934
11935         /* flow control autonegotiation is default behavior */
11936         tp->tg3_flags |= TG3_FLAG_PAUSE_AUTONEG;
11937
11938         tg3_init_coal(tp);
11939
11940         /* Now that we have fully setup the chip, save away a snapshot
11941          * of the PCI config space.  We need to restore this after
11942          * GRC_MISC_CFG core clock resets and some resume events.
11943          */
11944         pci_save_state(tp->pdev);
11945
11946         pci_set_drvdata(pdev, dev);
11947
11948         err = register_netdev(dev);
11949         if (err) {
11950                 printk(KERN_ERR PFX "Cannot register net device, "
11951                        "aborting.\n");
11952                 goto err_out_iounmap;
11953         }
11954
11955         printk(KERN_INFO "%s: Tigon3 [partno(%s) rev %04x PHY(%s)] (%s) %s Ethernet ",
11956                dev->name,
11957                tp->board_part_number,
11958                tp->pci_chip_rev_id,
11959                tg3_phy_string(tp),
11960                tg3_bus_string(tp, str),
11961                ((tp->tg3_flags & TG3_FLAG_10_100_ONLY) ? "10/100Base-TX" :
11962                 ((tp->tg3_flags2 & TG3_FLG2_ANY_SERDES) ? "1000Base-SX" :
11963                  "10/100/1000Base-T")));
11964
11965         for (i = 0; i < 6; i++)
11966                 printk("%2.2x%c", dev->dev_addr[i],
11967                        i == 5 ? '\n' : ':');
11968
11969         printk(KERN_INFO "%s: RXcsums[%d] LinkChgREG[%d] "
11970                "MIirq[%d] ASF[%d] Split[%d] WireSpeed[%d] "
11971                "TSOcap[%d] \n",
11972                dev->name,
11973                (tp->tg3_flags & TG3_FLAG_RX_CHECKSUMS) != 0,
11974                (tp->tg3_flags & TG3_FLAG_USE_LINKCHG_REG) != 0,
11975                (tp->tg3_flags & TG3_FLAG_USE_MI_INTERRUPT) != 0,
11976                (tp->tg3_flags & TG3_FLAG_ENABLE_ASF) != 0,
11977                (tp->tg3_flags & TG3_FLAG_SPLIT_MODE) != 0,
11978                (tp->tg3_flags2 & TG3_FLG2_NO_ETH_WIRE_SPEED) == 0,
11979                (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE) != 0);
11980         printk(KERN_INFO "%s: dma_rwctrl[%08x] dma_mask[%d-bit]\n",
11981                dev->name, tp->dma_rwctrl,
11982                (pdev->dma_mask == DMA_32BIT_MASK) ? 32 :
11983                 (((u64) pdev->dma_mask == DMA_40BIT_MASK) ? 40 : 64));
11984
11985         return 0;
11986
11987 err_out_iounmap:
11988         if (tp->regs) {
11989                 iounmap(tp->regs);
11990                 tp->regs = NULL;
11991         }
11992
11993 err_out_free_dev:
11994         free_netdev(dev);
11995
11996 err_out_free_res:
11997         pci_release_regions(pdev);
11998
11999 err_out_disable_pdev:
12000         pci_disable_device(pdev);
12001         pci_set_drvdata(pdev, NULL);
12002         return err;
12003 }
12004
12005 static void __devexit tg3_remove_one(struct pci_dev *pdev)
12006 {
12007         struct net_device *dev = pci_get_drvdata(pdev);
12008
12009         if (dev) {
12010                 struct tg3 *tp = netdev_priv(dev);
12011
12012                 flush_scheduled_work();
12013                 unregister_netdev(dev);
12014                 if (tp->regs) {
12015                         iounmap(tp->regs);
12016                         tp->regs = NULL;
12017                 }
12018                 free_netdev(dev);
12019                 pci_release_regions(pdev);
12020                 pci_disable_device(pdev);
12021                 pci_set_drvdata(pdev, NULL);
12022         }
12023 }
12024
12025 static int tg3_suspend(struct pci_dev *pdev, pm_message_t state)
12026 {
12027         struct net_device *dev = pci_get_drvdata(pdev);
12028         struct tg3 *tp = netdev_priv(dev);
12029         int err;
12030
12031         if (!netif_running(dev))
12032                 return 0;
12033
12034         flush_scheduled_work();
12035         tg3_netif_stop(tp);
12036
12037         del_timer_sync(&tp->timer);
12038
12039         tg3_full_lock(tp, 1);
12040         tg3_disable_ints(tp);
12041         tg3_full_unlock(tp);
12042
12043         netif_device_detach(dev);
12044
12045         tg3_full_lock(tp, 0);
12046         tg3_halt(tp, RESET_KIND_SHUTDOWN, 1);
12047         tp->tg3_flags &= ~TG3_FLAG_INIT_COMPLETE;
12048         tg3_full_unlock(tp);
12049
12050         /* Save MSI address and data for resume.  */
12051         pci_save_state(pdev);
12052
12053         err = tg3_set_power_state(tp, pci_choose_state(pdev, state));
12054         if (err) {
12055                 tg3_full_lock(tp, 0);
12056
12057                 tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12058                 if (tg3_restart_hw(tp, 1))
12059                         goto out;
12060
12061                 tp->timer.expires = jiffies + tp->timer_offset;
12062                 add_timer(&tp->timer);
12063
12064                 netif_device_attach(dev);
12065                 tg3_netif_start(tp);
12066
12067 out:
12068                 tg3_full_unlock(tp);
12069         }
12070
12071         return err;
12072 }
12073
12074 static int tg3_resume(struct pci_dev *pdev)
12075 {
12076         struct net_device *dev = pci_get_drvdata(pdev);
12077         struct tg3 *tp = netdev_priv(dev);
12078         int err;
12079
12080         if (!netif_running(dev))
12081                 return 0;
12082
12083         pci_restore_state(tp->pdev);
12084
12085         err = tg3_set_power_state(tp, PCI_D0);
12086         if (err)
12087                 return err;
12088
12089         netif_device_attach(dev);
12090
12091         tg3_full_lock(tp, 0);
12092
12093         tp->tg3_flags |= TG3_FLAG_INIT_COMPLETE;
12094         err = tg3_restart_hw(tp, 1);
12095         if (err)
12096                 goto out;
12097
12098         tp->timer.expires = jiffies + tp->timer_offset;
12099         add_timer(&tp->timer);
12100
12101         tg3_netif_start(tp);
12102
12103 out:
12104         tg3_full_unlock(tp);
12105
12106         return err;
12107 }
12108
12109 static struct pci_driver tg3_driver = {
12110         .name           = DRV_MODULE_NAME,
12111         .id_table       = tg3_pci_tbl,
12112         .probe          = tg3_init_one,
12113         .remove         = __devexit_p(tg3_remove_one),
12114         .suspend        = tg3_suspend,
12115         .resume         = tg3_resume
12116 };
12117
12118 static int __init tg3_init(void)
12119 {
12120         return pci_register_driver(&tg3_driver);
12121 }
12122
12123 static void __exit tg3_cleanup(void)
12124 {
12125         pci_unregister_driver(&tg3_driver);
12126 }
12127
12128 module_init(tg3_init);
12129 module_exit(tg3_cleanup);