1 /* sunhme.c: Sparc HME/BigMac 10/100baseT half/full duplex auto switching,
2 * auto carrier detecting ethernet driver. Also known as the
3 * "Happy Meal Ethernet" found on SunSwift SBUS cards.
5 * Copyright (C) 1996, 1998, 1999, 2002, 2003,
6 * 2006, 2008 David S. Miller (davem@davemloft.net)
9 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
10 * - port to non-sparc architectures. Tested only on x86 and
11 * only currently works with QFE PCI cards.
12 * - ability to specify the MAC address at module load time by passing this
13 * argument : macaddr=0x00,0x10,0x20,0x30,0x40,0x50
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/types.h>
19 #include <linux/fcntl.h>
20 #include <linux/interrupt.h>
21 #include <linux/ioport.h>
23 #include <linux/slab.h>
24 #include <linux/string.h>
25 #include <linux/delay.h>
26 #include <linux/init.h>
27 #include <linux/ethtool.h>
28 #include <linux/mii.h>
29 #include <linux/crc32.h>
30 #include <linux/random.h>
31 #include <linux/errno.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/skbuff.h>
36 #include <linux/bitops.h>
37 #include <linux/dma-mapping.h>
39 #include <asm/system.h>
42 #include <asm/byteorder.h>
46 #include <linux/of_device.h>
47 #include <asm/idprom.h>
48 #include <asm/openprom.h>
49 #include <asm/oplib.h>
51 #include <asm/auxio.h>
53 #include <asm/uaccess.h>
55 #include <asm/pgtable.h>
59 #include <linux/pci.h>
64 #define DRV_NAME "sunhme"
65 #define DRV_VERSION "3.10"
66 #define DRV_RELDATE "August 26, 2008"
67 #define DRV_AUTHOR "David S. Miller (davem@davemloft.net)"
69 static char version[] =
70 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
72 MODULE_VERSION(DRV_VERSION);
73 MODULE_AUTHOR(DRV_AUTHOR);
74 MODULE_DESCRIPTION("Sun HappyMealEthernet(HME) 10/100baseT ethernet driver");
75 MODULE_LICENSE("GPL");
77 static int macaddr[6];
79 /* accept MAC address of the form macaddr=0x08,0x00,0x20,0x30,0x40,0x50 */
80 module_param_array(macaddr, int, NULL, 0);
81 MODULE_PARM_DESC(macaddr, "Happy Meal MAC address to set");
84 static struct quattro *qfe_sbus_list;
88 static struct quattro *qfe_pci_list;
98 struct hme_tx_logent {
102 #define TXLOG_ACTION_IRQ 0x01
103 #define TXLOG_ACTION_TXMIT 0x02
104 #define TXLOG_ACTION_TBUSY 0x04
105 #define TXLOG_ACTION_NBUFS 0x08
108 #define TX_LOG_LEN 128
109 static struct hme_tx_logent tx_log[TX_LOG_LEN];
110 static int txlog_cur_entry;
111 static __inline__ void tx_add_log(struct happy_meal *hp, unsigned int a, unsigned int s)
113 struct hme_tx_logent *tlp;
116 local_irq_save(flags);
117 tlp = &tx_log[txlog_cur_entry];
118 tlp->tstamp = (unsigned int)jiffies;
119 tlp->tx_new = hp->tx_new;
120 tlp->tx_old = hp->tx_old;
123 txlog_cur_entry = (txlog_cur_entry + 1) & (TX_LOG_LEN - 1);
124 local_irq_restore(flags);
126 static __inline__ void tx_dump_log(void)
130 this = txlog_cur_entry;
131 for (i = 0; i < TX_LOG_LEN; i++) {
132 printk("TXLOG[%d]: j[%08x] tx[N(%d)O(%d)] action[%08x] stat[%08x]\n", i,
134 tx_log[this].tx_new, tx_log[this].tx_old,
135 tx_log[this].action, tx_log[this].status);
136 this = (this + 1) & (TX_LOG_LEN - 1);
139 static __inline__ void tx_dump_ring(struct happy_meal *hp)
141 struct hmeal_init_block *hb = hp->happy_block;
142 struct happy_meal_txd *tp = &hb->happy_meal_txd[0];
145 for (i = 0; i < TX_RING_SIZE; i+=4) {
146 printk("TXD[%d..%d]: [%08x:%08x] [%08x:%08x] [%08x:%08x] [%08x:%08x]\n",
148 le32_to_cpu(tp[i].tx_flags), le32_to_cpu(tp[i].tx_addr),
149 le32_to_cpu(tp[i + 1].tx_flags), le32_to_cpu(tp[i + 1].tx_addr),
150 le32_to_cpu(tp[i + 2].tx_flags), le32_to_cpu(tp[i + 2].tx_addr),
151 le32_to_cpu(tp[i + 3].tx_flags), le32_to_cpu(tp[i + 3].tx_addr));
155 #define tx_add_log(hp, a, s) do { } while(0)
156 #define tx_dump_log() do { } while(0)
157 #define tx_dump_ring(hp) do { } while(0)
161 #define HMD(x) printk x
166 /* #define AUTO_SWITCH_DEBUG */
168 #ifdef AUTO_SWITCH_DEBUG
169 #define ASD(x) printk x
174 #define DEFAULT_IPG0 16 /* For lance-mode only */
175 #define DEFAULT_IPG1 8 /* For all modes */
176 #define DEFAULT_IPG2 4 /* For all modes */
177 #define DEFAULT_JAMSIZE 4 /* Toe jam */
179 /* NOTE: In the descriptor writes one _must_ write the address
180 * member _first_. The card must not be allowed to see
181 * the updated descriptor flags until the address is
182 * correct. I've added a write memory barrier between
183 * the two stores so that I can sleep well at night... -DaveM
186 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
187 static void sbus_hme_write32(void __iomem *reg, u32 val)
189 sbus_writel(val, reg);
192 static u32 sbus_hme_read32(void __iomem *reg)
194 return sbus_readl(reg);
197 static void sbus_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
199 rxd->rx_addr = (__force hme32)addr;
201 rxd->rx_flags = (__force hme32)flags;
204 static void sbus_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
206 txd->tx_addr = (__force hme32)addr;
208 txd->tx_flags = (__force hme32)flags;
211 static u32 sbus_hme_read_desc32(hme32 *p)
213 return (__force u32)*p;
216 static void pci_hme_write32(void __iomem *reg, u32 val)
221 static u32 pci_hme_read32(void __iomem *reg)
226 static void pci_hme_write_rxd(struct happy_meal_rxd *rxd, u32 flags, u32 addr)
228 rxd->rx_addr = (__force hme32)cpu_to_le32(addr);
230 rxd->rx_flags = (__force hme32)cpu_to_le32(flags);
233 static void pci_hme_write_txd(struct happy_meal_txd *txd, u32 flags, u32 addr)
235 txd->tx_addr = (__force hme32)cpu_to_le32(addr);
237 txd->tx_flags = (__force hme32)cpu_to_le32(flags);
240 static u32 pci_hme_read_desc32(hme32 *p)
242 return le32_to_cpup((__le32 *)p);
245 #define hme_write32(__hp, __reg, __val) \
246 ((__hp)->write32((__reg), (__val)))
247 #define hme_read32(__hp, __reg) \
248 ((__hp)->read32(__reg))
249 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
250 ((__hp)->write_rxd((__rxd), (__flags), (__addr)))
251 #define hme_write_txd(__hp, __txd, __flags, __addr) \
252 ((__hp)->write_txd((__txd), (__flags), (__addr)))
253 #define hme_read_desc32(__hp, __p) \
254 ((__hp)->read_desc32(__p))
255 #define hme_dma_map(__hp, __ptr, __size, __dir) \
256 ((__hp)->dma_map((__hp)->dma_dev, (__ptr), (__size), (__dir)))
257 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
258 ((__hp)->dma_unmap((__hp)->dma_dev, (__addr), (__size), (__dir)))
259 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
260 ((__hp)->dma_sync_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir)))
261 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
262 ((__hp)->dma_sync_for_device((__hp)->dma_dev, (__addr), (__size), (__dir)))
265 /* SBUS only compilation */
266 #define hme_write32(__hp, __reg, __val) \
267 sbus_writel((__val), (__reg))
268 #define hme_read32(__hp, __reg) \
270 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
271 do { (__rxd)->rx_addr = (__force hme32)(u32)(__addr); \
273 (__rxd)->rx_flags = (__force hme32)(u32)(__flags); \
275 #define hme_write_txd(__hp, __txd, __flags, __addr) \
276 do { (__txd)->tx_addr = (__force hme32)(u32)(__addr); \
278 (__txd)->tx_flags = (__force hme32)(u32)(__flags); \
280 #define hme_read_desc32(__hp, __p) ((__force u32)(hme32)*(__p))
281 #define hme_dma_map(__hp, __ptr, __size, __dir) \
282 dma_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
283 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
284 dma_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
285 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
286 dma_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
287 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
288 dma_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
290 /* PCI only compilation */
291 #define hme_write32(__hp, __reg, __val) \
292 writel((__val), (__reg))
293 #define hme_read32(__hp, __reg) \
295 #define hme_write_rxd(__hp, __rxd, __flags, __addr) \
296 do { (__rxd)->rx_addr = (__force hme32)cpu_to_le32(__addr); \
298 (__rxd)->rx_flags = (__force hme32)cpu_to_le32(__flags); \
300 #define hme_write_txd(__hp, __txd, __flags, __addr) \
301 do { (__txd)->tx_addr = (__force hme32)cpu_to_le32(__addr); \
303 (__txd)->tx_flags = (__force hme32)cpu_to_le32(__flags); \
305 static inline u32 hme_read_desc32(struct happy_meal *hp, hme32 *p)
307 return le32_to_cpup((__le32 *)p);
309 #define hme_dma_map(__hp, __ptr, __size, __dir) \
310 pci_map_single((__hp)->dma_dev, (__ptr), (__size), (__dir))
311 #define hme_dma_unmap(__hp, __addr, __size, __dir) \
312 pci_unmap_single((__hp)->dma_dev, (__addr), (__size), (__dir))
313 #define hme_dma_sync_for_cpu(__hp, __addr, __size, __dir) \
314 pci_dma_sync_single_for_cpu((__hp)->dma_dev, (__addr), (__size), (__dir))
315 #define hme_dma_sync_for_device(__hp, __addr, __size, __dir) \
316 pci_dma_sync_single_for_device((__hp)->dma_dev, (__addr), (__size), (__dir))
321 /* Oh yes, the MIF BitBang is mighty fun to program. BitBucket is more like it. */
322 static void BB_PUT_BIT(struct happy_meal *hp, void __iomem *tregs, int bit)
324 hme_write32(hp, tregs + TCVR_BBDATA, bit);
325 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
326 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
330 static u32 BB_GET_BIT(struct happy_meal *hp, void __iomem *tregs, int internal)
334 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
335 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
336 ret = hme_read32(hp, tregs + TCVR_CFG);
338 ret &= TCV_CFG_MDIO0;
340 ret &= TCV_CFG_MDIO1;
346 static u32 BB_GET_BIT2(struct happy_meal *hp, void __iomem *tregs, int internal)
350 hme_write32(hp, tregs + TCVR_BBCLOCK, 0);
352 retval = hme_read32(hp, tregs + TCVR_CFG);
354 retval &= TCV_CFG_MDIO0;
356 retval &= TCV_CFG_MDIO1;
357 hme_write32(hp, tregs + TCVR_BBCLOCK, 1);
362 #define TCVR_FAILURE 0x80000000 /* Impossible MIF read value */
364 static int happy_meal_bb_read(struct happy_meal *hp,
365 void __iomem *tregs, int reg)
371 ASD(("happy_meal_bb_read: reg=%d ", reg));
373 /* Enable the MIF BitBang outputs. */
374 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
376 /* Force BitBang into the idle state. */
377 for (i = 0; i < 32; i++)
378 BB_PUT_BIT(hp, tregs, 1);
380 /* Give it the read sequence. */
381 BB_PUT_BIT(hp, tregs, 0);
382 BB_PUT_BIT(hp, tregs, 1);
383 BB_PUT_BIT(hp, tregs, 1);
384 BB_PUT_BIT(hp, tregs, 0);
386 /* Give it the PHY address. */
387 tmp = hp->paddr & 0xff;
388 for (i = 4; i >= 0; i--)
389 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
391 /* Tell it what register we want to read. */
393 for (i = 4; i >= 0; i--)
394 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
396 /* Close down the MIF BitBang outputs. */
397 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
399 /* Now read in the value. */
400 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
401 for (i = 15; i >= 0; i--)
402 retval |= BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
403 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
404 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
405 (void) BB_GET_BIT2(hp, tregs, (hp->tcvr_type == internal));
406 ASD(("value=%x\n", retval));
410 static void happy_meal_bb_write(struct happy_meal *hp,
411 void __iomem *tregs, int reg,
412 unsigned short value)
417 ASD(("happy_meal_bb_write: reg=%d value=%x\n", reg, value));
419 /* Enable the MIF BitBang outputs. */
420 hme_write32(hp, tregs + TCVR_BBOENAB, 1);
422 /* Force BitBang into the idle state. */
423 for (i = 0; i < 32; i++)
424 BB_PUT_BIT(hp, tregs, 1);
426 /* Give it write sequence. */
427 BB_PUT_BIT(hp, tregs, 0);
428 BB_PUT_BIT(hp, tregs, 1);
429 BB_PUT_BIT(hp, tregs, 0);
430 BB_PUT_BIT(hp, tregs, 1);
432 /* Give it the PHY address. */
433 tmp = (hp->paddr & 0xff);
434 for (i = 4; i >= 0; i--)
435 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
437 /* Tell it what register we will be writing. */
439 for (i = 4; i >= 0; i--)
440 BB_PUT_BIT(hp, tregs, ((tmp >> i) & 1));
442 /* Tell it to become ready for the bits. */
443 BB_PUT_BIT(hp, tregs, 1);
444 BB_PUT_BIT(hp, tregs, 0);
446 for (i = 15; i >= 0; i--)
447 BB_PUT_BIT(hp, tregs, ((value >> i) & 1));
449 /* Close down the MIF BitBang outputs. */
450 hme_write32(hp, tregs + TCVR_BBOENAB, 0);
453 #define TCVR_READ_TRIES 16
455 static int happy_meal_tcvr_read(struct happy_meal *hp,
456 void __iomem *tregs, int reg)
458 int tries = TCVR_READ_TRIES;
461 ASD(("happy_meal_tcvr_read: reg=0x%02x ", reg));
462 if (hp->tcvr_type == none) {
463 ASD(("no transceiver, value=TCVR_FAILURE\n"));
467 if (!(hp->happy_flags & HFLAG_FENABLE)) {
468 ASD(("doing bit bang\n"));
469 return happy_meal_bb_read(hp, tregs, reg);
472 hme_write32(hp, tregs + TCVR_FRAME,
473 (FRAME_READ | (hp->paddr << 23) | ((reg & 0xff) << 18)));
474 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
477 printk(KERN_ERR "happy meal: Aieee, transceiver MIF read bolixed\n");
480 retval = hme_read32(hp, tregs + TCVR_FRAME) & 0xffff;
481 ASD(("value=%04x\n", retval));
485 #define TCVR_WRITE_TRIES 16
487 static void happy_meal_tcvr_write(struct happy_meal *hp,
488 void __iomem *tregs, int reg,
489 unsigned short value)
491 int tries = TCVR_WRITE_TRIES;
493 ASD(("happy_meal_tcvr_write: reg=0x%02x value=%04x\n", reg, value));
495 /* Welcome to Sun Microsystems, can I take your order please? */
496 if (!(hp->happy_flags & HFLAG_FENABLE)) {
497 happy_meal_bb_write(hp, tregs, reg, value);
501 /* Would you like fries with that? */
502 hme_write32(hp, tregs + TCVR_FRAME,
503 (FRAME_WRITE | (hp->paddr << 23) |
504 ((reg & 0xff) << 18) | (value & 0xffff)));
505 while (!(hme_read32(hp, tregs + TCVR_FRAME) & 0x10000) && --tries)
510 printk(KERN_ERR "happy meal: Aieee, transceiver MIF write bolixed\n");
512 /* Fifty-two cents is your change, have a nice day. */
515 /* Auto negotiation. The scheme is very simple. We have a timer routine
516 * that keeps watching the auto negotiation process as it progresses.
517 * The DP83840 is first told to start doing it's thing, we set up the time
518 * and place the timer state machine in it's initial state.
520 * Here the timer peeks at the DP83840 status registers at each click to see
521 * if the auto negotiation has completed, we assume here that the DP83840 PHY
522 * will time out at some point and just tell us what (didn't) happen. For
523 * complete coverage we only allow so many of the ticks at this level to run,
524 * when this has expired we print a warning message and try another strategy.
525 * This "other" strategy is to force the interface into various speed/duplex
526 * configurations and we stop when we see a link-up condition before the
527 * maximum number of "peek" ticks have occurred.
529 * Once a valid link status has been detected we configure the BigMAC and
530 * the rest of the Happy Meal to speak the most efficient protocol we could
531 * get a clean link for. The priority for link configurations, highest first
533 * 100 Base-T Full Duplex
534 * 100 Base-T Half Duplex
535 * 10 Base-T Full Duplex
536 * 10 Base-T Half Duplex
538 * We start a new timer now, after a successful auto negotiation status has
539 * been detected. This timer just waits for the link-up bit to get set in
540 * the BMCR of the DP83840. When this occurs we print a kernel log message
541 * describing the link type in use and the fact that it is up.
543 * If a fatal error of some sort is signalled and detected in the interrupt
544 * service routine, and the chip is reset, or the link is ifconfig'd down
545 * and then back up, this entire process repeats itself all over again.
547 static int try_next_permutation(struct happy_meal *hp, void __iomem *tregs)
549 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
551 /* Downgrade from full to half duplex. Only possible
554 if (hp->sw_bmcr & BMCR_FULLDPLX) {
555 hp->sw_bmcr &= ~(BMCR_FULLDPLX);
556 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
560 /* Downgrade from 100 to 10. */
561 if (hp->sw_bmcr & BMCR_SPEED100) {
562 hp->sw_bmcr &= ~(BMCR_SPEED100);
563 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
567 /* We've tried everything. */
571 static void display_link_mode(struct happy_meal *hp, void __iomem *tregs)
573 printk(KERN_INFO "%s: Link is up using ", hp->dev->name);
574 if (hp->tcvr_type == external)
578 printk("transceiver at ");
579 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
580 if (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) {
581 if (hp->sw_lpa & LPA_100FULL)
582 printk("100Mb/s, Full Duplex.\n");
584 printk("100Mb/s, Half Duplex.\n");
586 if (hp->sw_lpa & LPA_10FULL)
587 printk("10Mb/s, Full Duplex.\n");
589 printk("10Mb/s, Half Duplex.\n");
593 static void display_forced_link_mode(struct happy_meal *hp, void __iomem *tregs)
595 printk(KERN_INFO "%s: Link has been forced up using ", hp->dev->name);
596 if (hp->tcvr_type == external)
600 printk("transceiver at ");
601 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
602 if (hp->sw_bmcr & BMCR_SPEED100)
606 if (hp->sw_bmcr & BMCR_FULLDPLX)
607 printk("Full Duplex.\n");
609 printk("Half Duplex.\n");
612 static int set_happy_link_modes(struct happy_meal *hp, void __iomem *tregs)
616 /* All we care about is making sure the bigmac tx_cfg has a
617 * proper duplex setting.
619 if (hp->timer_state == arbwait) {
620 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
621 if (!(hp->sw_lpa & (LPA_10HALF | LPA_10FULL | LPA_100HALF | LPA_100FULL)))
623 if (hp->sw_lpa & LPA_100FULL)
625 else if (hp->sw_lpa & LPA_100HALF)
627 else if (hp->sw_lpa & LPA_10FULL)
632 /* Forcing a link mode. */
633 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
634 if (hp->sw_bmcr & BMCR_FULLDPLX)
640 /* Before changing other bits in the tx_cfg register, and in
641 * general any of other the TX config registers too, you
644 * 2) Poll with reads until that bit reads back as zero
645 * 3) Make TX configuration changes
646 * 4) Set Enable once more
648 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
649 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
650 ~(BIGMAC_TXCFG_ENABLE));
651 while (hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) & BIGMAC_TXCFG_ENABLE)
654 hp->happy_flags |= HFLAG_FULL;
655 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
656 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
657 BIGMAC_TXCFG_FULLDPLX);
659 hp->happy_flags &= ~(HFLAG_FULL);
660 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
661 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) &
662 ~(BIGMAC_TXCFG_FULLDPLX));
664 hme_write32(hp, hp->bigmacregs + BMAC_TXCFG,
665 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG) |
666 BIGMAC_TXCFG_ENABLE);
672 static int happy_meal_init(struct happy_meal *hp);
674 static int is_lucent_phy(struct happy_meal *hp)
676 void __iomem *tregs = hp->tcvregs;
677 unsigned short mr2, mr3;
680 mr2 = happy_meal_tcvr_read(hp, tregs, 2);
681 mr3 = happy_meal_tcvr_read(hp, tregs, 3);
682 if ((mr2 & 0xffff) == 0x0180 &&
683 ((mr3 & 0xffff) >> 10) == 0x1d)
689 static void happy_meal_timer(unsigned long data)
691 struct happy_meal *hp = (struct happy_meal *) data;
692 void __iomem *tregs = hp->tcvregs;
693 int restart_timer = 0;
695 spin_lock_irq(&hp->happy_lock);
698 switch(hp->timer_state) {
700 /* Only allow for 5 ticks, thats 10 seconds and much too
701 * long to wait for arbitration to complete.
703 if (hp->timer_ticks >= 10) {
704 /* Enter force mode. */
706 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
707 printk(KERN_NOTICE "%s: Auto-Negotiation unsuccessful, trying force link mode\n",
709 hp->sw_bmcr = BMCR_SPEED100;
710 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
712 if (!is_lucent_phy(hp)) {
713 /* OK, seems we need do disable the transceiver for the first
714 * tick to make sure we get an accurate link state at the
717 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
718 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
719 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG, hp->sw_csconfig);
721 hp->timer_state = ltrywait;
725 /* Anything interesting happen? */
726 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
727 if (hp->sw_bmsr & BMSR_ANEGCOMPLETE) {
730 /* Just what we've been waiting for... */
731 ret = set_happy_link_modes(hp, tregs);
733 /* Ooops, something bad happened, go to force
736 * XXX Broken hubs which don't support 802.3u
737 * XXX auto-negotiation make this happen as well.
742 /* Success, at least so far, advance our state engine. */
743 hp->timer_state = lupwait;
752 /* Auto negotiation was successful and we are awaiting a
753 * link up status. I have decided to let this timer run
754 * forever until some sort of error is signalled, reporting
755 * a message to the user at 10 second intervals.
757 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
758 if (hp->sw_bmsr & BMSR_LSTATUS) {
759 /* Wheee, it's up, display the link mode in use and put
760 * the timer to sleep.
762 display_link_mode(hp, tregs);
763 hp->timer_state = asleep;
766 if (hp->timer_ticks >= 10) {
767 printk(KERN_NOTICE "%s: Auto negotiation successful, link still "
768 "not completely up.\n", hp->dev->name);
778 /* Making the timeout here too long can make it take
779 * annoyingly long to attempt all of the link mode
780 * permutations, but then again this is essentially
781 * error recovery code for the most part.
783 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
784 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs, DP83840_CSCONFIG);
785 if (hp->timer_ticks == 1) {
786 if (!is_lucent_phy(hp)) {
787 /* Re-enable transceiver, we'll re-enable the transceiver next
788 * tick, then check link state on the following tick.
790 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
791 happy_meal_tcvr_write(hp, tregs,
792 DP83840_CSCONFIG, hp->sw_csconfig);
797 if (hp->timer_ticks == 2) {
798 if (!is_lucent_phy(hp)) {
799 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
800 happy_meal_tcvr_write(hp, tregs,
801 DP83840_CSCONFIG, hp->sw_csconfig);
806 if (hp->sw_bmsr & BMSR_LSTATUS) {
807 /* Force mode selection success. */
808 display_forced_link_mode(hp, tregs);
809 set_happy_link_modes(hp, tregs); /* XXX error? then what? */
810 hp->timer_state = asleep;
813 if (hp->timer_ticks >= 4) { /* 6 seconds or so... */
816 ret = try_next_permutation(hp, tregs);
818 /* Aieee, tried them all, reset the
819 * chip and try all over again.
822 /* Let the user know... */
823 printk(KERN_NOTICE "%s: Link down, cable problem?\n",
826 ret = happy_meal_init(hp);
829 printk(KERN_ERR "%s: Error, cannot re-init the "
830 "Happy Meal.\n", hp->dev->name);
834 if (!is_lucent_phy(hp)) {
835 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
837 hp->sw_csconfig |= CSCONFIG_TCVDISAB;
838 happy_meal_tcvr_write(hp, tregs,
839 DP83840_CSCONFIG, hp->sw_csconfig);
851 /* Can't happens.... */
852 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
856 hp->timer_state = asleep; /* foo on you */
861 hp->happy_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
862 add_timer(&hp->happy_timer);
866 spin_unlock_irq(&hp->happy_lock);
869 #define TX_RESET_TRIES 32
870 #define RX_RESET_TRIES 32
872 /* hp->happy_lock must be held */
873 static void happy_meal_tx_reset(struct happy_meal *hp, void __iomem *bregs)
875 int tries = TX_RESET_TRIES;
877 HMD(("happy_meal_tx_reset: reset, "));
879 /* Would you like to try our SMCC Delux? */
880 hme_write32(hp, bregs + BMAC_TXSWRESET, 0);
881 while ((hme_read32(hp, bregs + BMAC_TXSWRESET) & 1) && --tries)
884 /* Lettuce, tomato, buggy hardware (no extra charge)? */
886 printk(KERN_ERR "happy meal: Transceiver BigMac ATTACK!");
892 /* hp->happy_lock must be held */
893 static void happy_meal_rx_reset(struct happy_meal *hp, void __iomem *bregs)
895 int tries = RX_RESET_TRIES;
897 HMD(("happy_meal_rx_reset: reset, "));
899 /* We have a special on GNU/Viking hardware bugs today. */
900 hme_write32(hp, bregs + BMAC_RXSWRESET, 0);
901 while ((hme_read32(hp, bregs + BMAC_RXSWRESET) & 1) && --tries)
904 /* Will that be all? */
906 printk(KERN_ERR "happy meal: Receiver BigMac ATTACK!");
908 /* Don't forget your vik_1137125_wa. Have a nice day. */
912 #define STOP_TRIES 16
914 /* hp->happy_lock must be held */
915 static void happy_meal_stop(struct happy_meal *hp, void __iomem *gregs)
917 int tries = STOP_TRIES;
919 HMD(("happy_meal_stop: reset, "));
921 /* We're consolidating our STB products, it's your lucky day. */
922 hme_write32(hp, gregs + GREG_SWRESET, GREG_RESET_ALL);
923 while (hme_read32(hp, gregs + GREG_SWRESET) && --tries)
926 /* Come back next week when we are "Sun Microelectronics". */
928 printk(KERN_ERR "happy meal: Fry guys.");
930 /* Remember: "Different name, same old buggy as shit hardware." */
934 /* hp->happy_lock must be held */
935 static void happy_meal_get_counters(struct happy_meal *hp, void __iomem *bregs)
937 struct net_device_stats *stats = &hp->net_stats;
939 stats->rx_crc_errors += hme_read32(hp, bregs + BMAC_RCRCECTR);
940 hme_write32(hp, bregs + BMAC_RCRCECTR, 0);
942 stats->rx_frame_errors += hme_read32(hp, bregs + BMAC_UNALECTR);
943 hme_write32(hp, bregs + BMAC_UNALECTR, 0);
945 stats->rx_length_errors += hme_read32(hp, bregs + BMAC_GLECTR);
946 hme_write32(hp, bregs + BMAC_GLECTR, 0);
948 stats->tx_aborted_errors += hme_read32(hp, bregs + BMAC_EXCTR);
951 (hme_read32(hp, bregs + BMAC_EXCTR) +
952 hme_read32(hp, bregs + BMAC_LTCTR));
953 hme_write32(hp, bregs + BMAC_EXCTR, 0);
954 hme_write32(hp, bregs + BMAC_LTCTR, 0);
957 /* hp->happy_lock must be held */
958 static void happy_meal_poll_stop(struct happy_meal *hp, void __iomem *tregs)
960 ASD(("happy_meal_poll_stop: "));
962 /* If polling disabled or not polling already, nothing to do. */
963 if ((hp->happy_flags & (HFLAG_POLLENABLE | HFLAG_POLL)) !=
964 (HFLAG_POLLENABLE | HFLAG_POLL)) {
965 HMD(("not polling, return\n"));
969 /* Shut up the MIF. */
970 ASD(("were polling, mif ints off, "));
971 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
973 /* Turn off polling. */
974 ASD(("polling off, "));
975 hme_write32(hp, tregs + TCVR_CFG,
976 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_PENABLE));
978 /* We are no longer polling. */
979 hp->happy_flags &= ~(HFLAG_POLL);
981 /* Let the bits set. */
986 /* Only Sun can take such nice parts and fuck up the programming interface
987 * like this. Good job guys...
989 #define TCVR_RESET_TRIES 16 /* It should reset quickly */
990 #define TCVR_UNISOLATE_TRIES 32 /* Dis-isolation can take longer. */
992 /* hp->happy_lock must be held */
993 static int happy_meal_tcvr_reset(struct happy_meal *hp, void __iomem *tregs)
996 int result, tries = TCVR_RESET_TRIES;
998 tconfig = hme_read32(hp, tregs + TCVR_CFG);
999 ASD(("happy_meal_tcvr_reset: tcfg<%08lx> ", tconfig));
1000 if (hp->tcvr_type == external) {
1002 hme_write32(hp, tregs + TCVR_CFG, tconfig & ~(TCV_CFG_PSELECT));
1003 hp->tcvr_type = internal;
1004 hp->paddr = TCV_PADDR_ITX;
1006 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1007 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1008 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1009 if (result == TCVR_FAILURE) {
1010 ASD(("phyread_fail>\n"));
1013 ASD(("phyread_ok,PSELECT>"));
1014 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1015 hp->tcvr_type = external;
1016 hp->paddr = TCV_PADDR_ETX;
1018 if (tconfig & TCV_CFG_MDIO1) {
1019 ASD(("internal<PSELECT,"));
1020 hme_write32(hp, tregs + TCVR_CFG, (tconfig | TCV_CFG_PSELECT));
1022 happy_meal_tcvr_write(hp, tregs, MII_BMCR,
1023 (BMCR_LOOPBACK|BMCR_PDOWN|BMCR_ISOLATE));
1024 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1025 if (result == TCVR_FAILURE) {
1026 ASD(("phyread_fail>\n"));
1029 ASD(("phyread_ok,~PSELECT>"));
1030 hme_write32(hp, tregs + TCVR_CFG, (tconfig & ~(TCV_CFG_PSELECT)));
1031 hp->tcvr_type = internal;
1032 hp->paddr = TCV_PADDR_ITX;
1036 ASD(("BMCR_RESET "));
1037 happy_meal_tcvr_write(hp, tregs, MII_BMCR, BMCR_RESET);
1040 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1041 if (result == TCVR_FAILURE)
1043 hp->sw_bmcr = result;
1044 if (!(result & BMCR_RESET))
1049 ASD(("BMCR RESET FAILED!\n"));
1052 ASD(("RESET_OK\n"));
1054 /* Get fresh copies of the PHY registers. */
1055 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1056 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1057 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1058 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1061 hp->sw_bmcr &= ~(BMCR_ISOLATE);
1062 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1064 tries = TCVR_UNISOLATE_TRIES;
1066 result = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1067 if (result == TCVR_FAILURE)
1069 if (!(result & BMCR_ISOLATE))
1074 ASD((" FAILED!\n"));
1077 ASD((" SUCCESS and CSCONFIG_DFBYPASS\n"));
1078 if (!is_lucent_phy(hp)) {
1079 result = happy_meal_tcvr_read(hp, tregs,
1081 happy_meal_tcvr_write(hp, tregs,
1082 DP83840_CSCONFIG, (result | CSCONFIG_DFBYPASS));
1087 /* Figure out whether we have an internal or external transceiver.
1089 * hp->happy_lock must be held
1091 static void happy_meal_transceiver_check(struct happy_meal *hp, void __iomem *tregs)
1093 unsigned long tconfig = hme_read32(hp, tregs + TCVR_CFG);
1095 ASD(("happy_meal_transceiver_check: tcfg=%08lx ", tconfig));
1096 if (hp->happy_flags & HFLAG_POLL) {
1097 /* If we are polling, we must stop to get the transceiver type. */
1098 ASD(("<polling> "));
1099 if (hp->tcvr_type == internal) {
1100 if (tconfig & TCV_CFG_MDIO1) {
1101 ASD(("<internal> <poll stop> "));
1102 happy_meal_poll_stop(hp, tregs);
1103 hp->paddr = TCV_PADDR_ETX;
1104 hp->tcvr_type = external;
1105 ASD(("<external>\n"));
1106 tconfig &= ~(TCV_CFG_PENABLE);
1107 tconfig |= TCV_CFG_PSELECT;
1108 hme_write32(hp, tregs + TCVR_CFG, tconfig);
1111 if (hp->tcvr_type == external) {
1112 ASD(("<external> "));
1113 if (!(hme_read32(hp, tregs + TCVR_STATUS) >> 16)) {
1114 ASD(("<poll stop> "));
1115 happy_meal_poll_stop(hp, tregs);
1116 hp->paddr = TCV_PADDR_ITX;
1117 hp->tcvr_type = internal;
1118 ASD(("<internal>\n"));
1119 hme_write32(hp, tregs + TCVR_CFG,
1120 hme_read32(hp, tregs + TCVR_CFG) &
1121 ~(TCV_CFG_PSELECT));
1129 u32 reread = hme_read32(hp, tregs + TCVR_CFG);
1131 /* Else we can just work off of the MDIO bits. */
1132 ASD(("<not polling> "));
1133 if (reread & TCV_CFG_MDIO1) {
1134 hme_write32(hp, tregs + TCVR_CFG, tconfig | TCV_CFG_PSELECT);
1135 hp->paddr = TCV_PADDR_ETX;
1136 hp->tcvr_type = external;
1137 ASD(("<external>\n"));
1139 if (reread & TCV_CFG_MDIO0) {
1140 hme_write32(hp, tregs + TCVR_CFG,
1141 tconfig & ~(TCV_CFG_PSELECT));
1142 hp->paddr = TCV_PADDR_ITX;
1143 hp->tcvr_type = internal;
1144 ASD(("<internal>\n"));
1146 printk(KERN_ERR "happy meal: Transceiver and a coke please.");
1147 hp->tcvr_type = none; /* Grrr... */
1154 /* The receive ring buffers are a bit tricky to get right. Here goes...
1156 * The buffers we dma into must be 64 byte aligned. So we use a special
1157 * alloc_skb() routine for the happy meal to allocate 64 bytes more than
1160 * We use skb_reserve() to align the data block we get in the skb. We
1161 * also program the etxregs->cfg register to use an offset of 2. This
1162 * imperical constant plus the ethernet header size will always leave
1163 * us with a nicely aligned ip header once we pass things up to the
1166 * The numbers work out to:
1168 * Max ethernet frame size 1518
1169 * Ethernet header size 14
1170 * Happy Meal base offset 2
1172 * Say a skb data area is at 0xf001b010, and its size alloced is
1173 * (ETH_FRAME_LEN + 64 + 2) = (1514 + 64 + 2) = 1580 bytes.
1175 * First our alloc_skb() routine aligns the data base to a 64 byte
1176 * boundary. We now have 0xf001b040 as our skb data address. We
1177 * plug this into the receive descriptor address.
1179 * Next, we skb_reserve() 2 bytes to account for the Happy Meal offset.
1180 * So now the data we will end up looking at starts at 0xf001b042. When
1181 * the packet arrives, we will check out the size received and subtract
1182 * this from the skb->length. Then we just pass the packet up to the
1183 * protocols as is, and allocate a new skb to replace this slot we have
1184 * just received from.
1186 * The ethernet layer will strip the ether header from the front of the
1187 * skb we just sent to it, this leaves us with the ip header sitting
1188 * nicely aligned at 0xf001b050. Also, for tcp and udp packets the
1189 * Happy Meal has even checksummed the tcp/udp data for us. The 16
1190 * bit checksum is obtained from the low bits of the receive descriptor
1193 * skb->csum = rxd->rx_flags & 0xffff;
1194 * skb->ip_summed = CHECKSUM_COMPLETE;
1196 * before sending off the skb to the protocols, and we are good as gold.
1198 static void happy_meal_clean_rings(struct happy_meal *hp)
1202 for (i = 0; i < RX_RING_SIZE; i++) {
1203 if (hp->rx_skbs[i] != NULL) {
1204 struct sk_buff *skb = hp->rx_skbs[i];
1205 struct happy_meal_rxd *rxd;
1208 rxd = &hp->happy_block->happy_meal_rxd[i];
1209 dma_addr = hme_read_desc32(hp, &rxd->rx_addr);
1210 dma_unmap_single(hp->dma_dev, dma_addr,
1211 RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
1212 dev_kfree_skb_any(skb);
1213 hp->rx_skbs[i] = NULL;
1217 for (i = 0; i < TX_RING_SIZE; i++) {
1218 if (hp->tx_skbs[i] != NULL) {
1219 struct sk_buff *skb = hp->tx_skbs[i];
1220 struct happy_meal_txd *txd;
1224 hp->tx_skbs[i] = NULL;
1226 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1227 txd = &hp->happy_block->happy_meal_txd[i];
1228 dma_addr = hme_read_desc32(hp, &txd->tx_addr);
1229 dma_unmap_single(hp->dma_dev, dma_addr,
1230 (hme_read_desc32(hp, &txd->tx_flags)
1234 if (frag != skb_shinfo(skb)->nr_frags)
1238 dev_kfree_skb_any(skb);
1243 /* hp->happy_lock must be held */
1244 static void happy_meal_init_rings(struct happy_meal *hp)
1246 struct hmeal_init_block *hb = hp->happy_block;
1247 struct net_device *dev = hp->dev;
1250 HMD(("happy_meal_init_rings: counters to zero, "));
1251 hp->rx_new = hp->rx_old = hp->tx_new = hp->tx_old = 0;
1253 /* Free any skippy bufs left around in the rings. */
1255 happy_meal_clean_rings(hp);
1257 /* Now get new skippy bufs for the receive ring. */
1258 HMD(("init rxring, "));
1259 for (i = 0; i < RX_RING_SIZE; i++) {
1260 struct sk_buff *skb;
1262 skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
1264 hme_write_rxd(hp, &hb->happy_meal_rxd[i], 0, 0);
1267 hp->rx_skbs[i] = skb;
1270 /* Because we reserve afterwards. */
1271 skb_put(skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
1272 hme_write_rxd(hp, &hb->happy_meal_rxd[i],
1273 (RXFLAG_OWN | ((RX_BUF_ALLOC_SIZE - RX_OFFSET) << 16)),
1274 dma_map_single(hp->dma_dev, skb->data, RX_BUF_ALLOC_SIZE,
1276 skb_reserve(skb, RX_OFFSET);
1279 HMD(("init txring, "));
1280 for (i = 0; i < TX_RING_SIZE; i++)
1281 hme_write_txd(hp, &hb->happy_meal_txd[i], 0, 0);
1286 /* hp->happy_lock must be held */
1287 static void happy_meal_begin_auto_negotiation(struct happy_meal *hp,
1288 void __iomem *tregs,
1289 struct ethtool_cmd *ep)
1293 /* Read all of the registers we are interested in now. */
1294 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1295 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1296 hp->sw_physid1 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID1);
1297 hp->sw_physid2 = happy_meal_tcvr_read(hp, tregs, MII_PHYSID2);
1299 /* XXX Check BMSR_ANEGCAPABLE, should not be necessary though. */
1301 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1302 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1303 /* Advertise everything we can support. */
1304 if (hp->sw_bmsr & BMSR_10HALF)
1305 hp->sw_advertise |= (ADVERTISE_10HALF);
1307 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1309 if (hp->sw_bmsr & BMSR_10FULL)
1310 hp->sw_advertise |= (ADVERTISE_10FULL);
1312 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1313 if (hp->sw_bmsr & BMSR_100HALF)
1314 hp->sw_advertise |= (ADVERTISE_100HALF);
1316 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1317 if (hp->sw_bmsr & BMSR_100FULL)
1318 hp->sw_advertise |= (ADVERTISE_100FULL);
1320 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1321 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1323 /* XXX Currently no Happy Meal cards I know off support 100BaseT4,
1324 * XXX and this is because the DP83840 does not support it, changes
1325 * XXX would need to be made to the tx/rx logic in the driver as well
1326 * XXX so I completely skip checking for it in the BMSR for now.
1329 #ifdef AUTO_SWITCH_DEBUG
1330 ASD(("%s: Advertising [ ", hp->dev->name));
1331 if (hp->sw_advertise & ADVERTISE_10HALF)
1333 if (hp->sw_advertise & ADVERTISE_10FULL)
1335 if (hp->sw_advertise & ADVERTISE_100HALF)
1337 if (hp->sw_advertise & ADVERTISE_100FULL)
1341 /* Enable Auto-Negotiation, this is usually on already... */
1342 hp->sw_bmcr |= BMCR_ANENABLE;
1343 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1345 /* Restart it to make sure it is going. */
1346 hp->sw_bmcr |= BMCR_ANRESTART;
1347 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1349 /* BMCR_ANRESTART self clears when the process has begun. */
1351 timeout = 64; /* More than enough. */
1353 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1354 if (!(hp->sw_bmcr & BMCR_ANRESTART))
1355 break; /* got it. */
1359 printk(KERN_ERR "%s: Happy Meal would not start auto negotiation "
1360 "BMCR=0x%04x\n", hp->dev->name, hp->sw_bmcr);
1361 printk(KERN_NOTICE "%s: Performing force link detection.\n",
1365 hp->timer_state = arbwait;
1369 /* Force the link up, trying first a particular mode.
1370 * Either we are here at the request of ethtool or
1371 * because the Happy Meal would not start to autoneg.
1374 /* Disable auto-negotiation in BMCR, enable the duplex and
1375 * speed setting, init the timer state machine, and fire it off.
1377 if (ep == NULL || ep->autoneg == AUTONEG_ENABLE) {
1378 hp->sw_bmcr = BMCR_SPEED100;
1380 if (ep->speed == SPEED_100)
1381 hp->sw_bmcr = BMCR_SPEED100;
1384 if (ep->duplex == DUPLEX_FULL)
1385 hp->sw_bmcr |= BMCR_FULLDPLX;
1387 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1389 if (!is_lucent_phy(hp)) {
1390 /* OK, seems we need do disable the transceiver for the first
1391 * tick to make sure we get an accurate link state at the
1394 hp->sw_csconfig = happy_meal_tcvr_read(hp, tregs,
1396 hp->sw_csconfig &= ~(CSCONFIG_TCVDISAB);
1397 happy_meal_tcvr_write(hp, tregs, DP83840_CSCONFIG,
1400 hp->timer_state = ltrywait;
1403 hp->timer_ticks = 0;
1404 hp->happy_timer.expires = jiffies + (12 * HZ)/10; /* 1.2 sec. */
1405 hp->happy_timer.data = (unsigned long) hp;
1406 hp->happy_timer.function = &happy_meal_timer;
1407 add_timer(&hp->happy_timer);
1410 /* hp->happy_lock must be held */
1411 static int happy_meal_init(struct happy_meal *hp)
1413 void __iomem *gregs = hp->gregs;
1414 void __iomem *etxregs = hp->etxregs;
1415 void __iomem *erxregs = hp->erxregs;
1416 void __iomem *bregs = hp->bigmacregs;
1417 void __iomem *tregs = hp->tcvregs;
1419 unsigned char *e = &hp->dev->dev_addr[0];
1421 /* If auto-negotiation timer is running, kill it. */
1422 del_timer(&hp->happy_timer);
1424 HMD(("happy_meal_init: happy_flags[%08x] ",
1426 if (!(hp->happy_flags & HFLAG_INIT)) {
1427 HMD(("set HFLAG_INIT, "));
1428 hp->happy_flags |= HFLAG_INIT;
1429 happy_meal_get_counters(hp, bregs);
1433 HMD(("to happy_meal_poll_stop\n"));
1434 happy_meal_poll_stop(hp, tregs);
1436 /* Stop transmitter and receiver. */
1437 HMD(("happy_meal_init: to happy_meal_stop\n"));
1438 happy_meal_stop(hp, gregs);
1440 /* Alloc and reset the tx/rx descriptor chains. */
1441 HMD(("happy_meal_init: to happy_meal_init_rings\n"));
1442 happy_meal_init_rings(hp);
1444 /* Shut up the MIF. */
1445 HMD(("happy_meal_init: Disable all MIF irqs (old[%08x]), ",
1446 hme_read32(hp, tregs + TCVR_IMASK)));
1447 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1449 /* See if we can enable the MIF frame on this card to speak to the DP83840. */
1450 if (hp->happy_flags & HFLAG_FENABLE) {
1451 HMD(("use frame old[%08x], ",
1452 hme_read32(hp, tregs + TCVR_CFG)));
1453 hme_write32(hp, tregs + TCVR_CFG,
1454 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1456 HMD(("use bitbang old[%08x], ",
1457 hme_read32(hp, tregs + TCVR_CFG)));
1458 hme_write32(hp, tregs + TCVR_CFG,
1459 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1462 /* Check the state of the transceiver. */
1463 HMD(("to happy_meal_transceiver_check\n"));
1464 happy_meal_transceiver_check(hp, tregs);
1466 /* Put the Big Mac into a sane state. */
1467 HMD(("happy_meal_init: "));
1468 switch(hp->tcvr_type) {
1470 /* Cannot operate if we don't know the transceiver type! */
1471 HMD(("AAIEEE no transceiver type, EAGAIN"));
1475 /* Using the MII buffers. */
1476 HMD(("internal, using MII, "));
1477 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1481 /* Not using the MII, disable it. */
1482 HMD(("external, disable MII, "));
1483 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1487 if (happy_meal_tcvr_reset(hp, tregs))
1490 /* Reset the Happy Meal Big Mac transceiver and the receiver. */
1491 HMD(("tx/rx reset, "));
1492 happy_meal_tx_reset(hp, bregs);
1493 happy_meal_rx_reset(hp, bregs);
1495 /* Set jam size and inter-packet gaps to reasonable defaults. */
1496 HMD(("jsize/ipg1/ipg2, "));
1497 hme_write32(hp, bregs + BMAC_JSIZE, DEFAULT_JAMSIZE);
1498 hme_write32(hp, bregs + BMAC_IGAP1, DEFAULT_IPG1);
1499 hme_write32(hp, bregs + BMAC_IGAP2, DEFAULT_IPG2);
1501 /* Load up the MAC address and random seed. */
1502 HMD(("rseed/macaddr, "));
1504 /* The docs recommend to use the 10LSB of our MAC here. */
1505 hme_write32(hp, bregs + BMAC_RSEED, ((e[5] | e[4]<<8)&0x3ff));
1507 hme_write32(hp, bregs + BMAC_MACADDR2, ((e[4] << 8) | e[5]));
1508 hme_write32(hp, bregs + BMAC_MACADDR1, ((e[2] << 8) | e[3]));
1509 hme_write32(hp, bregs + BMAC_MACADDR0, ((e[0] << 8) | e[1]));
1512 if ((hp->dev->flags & IFF_ALLMULTI) ||
1513 (hp->dev->mc_count > 64)) {
1514 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
1515 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
1516 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
1517 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
1518 } else if ((hp->dev->flags & IFF_PROMISC) == 0) {
1520 struct dev_mc_list *dmi = hp->dev->mc_list;
1525 for (i = 0; i < 4; i++)
1528 for (i = 0; i < hp->dev->mc_count; i++) {
1529 addrs = dmi->dmi_addr;
1535 crc = ether_crc_le(6, addrs);
1537 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1539 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
1540 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
1541 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
1542 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
1544 hme_write32(hp, bregs + BMAC_HTABLE3, 0);
1545 hme_write32(hp, bregs + BMAC_HTABLE2, 0);
1546 hme_write32(hp, bregs + BMAC_HTABLE1, 0);
1547 hme_write32(hp, bregs + BMAC_HTABLE0, 0);
1550 /* Set the RX and TX ring ptrs. */
1551 HMD(("ring ptrs rxr[%08x] txr[%08x]\n",
1552 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)),
1553 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0))));
1554 hme_write32(hp, erxregs + ERX_RING,
1555 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)));
1556 hme_write32(hp, etxregs + ETX_RING,
1557 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_txd, 0)));
1559 /* Parity issues in the ERX unit of some HME revisions can cause some
1560 * registers to not be written unless their parity is even. Detect such
1561 * lost writes and simply rewrite with a low bit set (which will be ignored
1562 * since the rxring needs to be 2K aligned).
1564 if (hme_read32(hp, erxregs + ERX_RING) !=
1565 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0)))
1566 hme_write32(hp, erxregs + ERX_RING,
1567 ((__u32)hp->hblock_dvma + hblock_offset(happy_meal_rxd, 0))
1570 /* Set the supported burst sizes. */
1571 HMD(("happy_meal_init: old[%08x] bursts<",
1572 hme_read32(hp, gregs + GREG_CFG)));
1574 #ifndef CONFIG_SPARC
1575 /* It is always PCI and can handle 64byte bursts. */
1576 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST64);
1578 if ((hp->happy_bursts & DMA_BURST64) &&
1579 ((hp->happy_flags & HFLAG_PCI) != 0
1581 || sbus_can_burst64()
1584 u32 gcfg = GREG_CFG_BURST64;
1586 /* I have no idea if I should set the extended
1587 * transfer mode bit for Cheerio, so for now I
1591 if ((hp->happy_flags & HFLAG_PCI) == 0) {
1592 struct of_device *op = hp->happy_dev;
1593 if (sbus_can_dma_64bit()) {
1594 sbus_set_sbus64(&op->dev,
1596 gcfg |= GREG_CFG_64BIT;
1602 hme_write32(hp, gregs + GREG_CFG, gcfg);
1603 } else if (hp->happy_bursts & DMA_BURST32) {
1605 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST32);
1606 } else if (hp->happy_bursts & DMA_BURST16) {
1608 hme_write32(hp, gregs + GREG_CFG, GREG_CFG_BURST16);
1611 hme_write32(hp, gregs + GREG_CFG, 0);
1613 #endif /* CONFIG_SPARC */
1615 /* Turn off interrupts we do not want to hear. */
1616 HMD((", enable global interrupts, "));
1617 hme_write32(hp, gregs + GREG_IMASK,
1618 (GREG_IMASK_GOTFRAME | GREG_IMASK_RCNTEXP |
1619 GREG_IMASK_SENTFRAME | GREG_IMASK_TXPERR));
1621 /* Set the transmit ring buffer size. */
1622 HMD(("tx rsize=%d oreg[%08x], ", (int)TX_RING_SIZE,
1623 hme_read32(hp, etxregs + ETX_RSIZE)));
1624 hme_write32(hp, etxregs + ETX_RSIZE, (TX_RING_SIZE >> ETX_RSIZE_SHIFT) - 1);
1626 /* Enable transmitter DVMA. */
1627 HMD(("tx dma enable old[%08x], ",
1628 hme_read32(hp, etxregs + ETX_CFG)));
1629 hme_write32(hp, etxregs + ETX_CFG,
1630 hme_read32(hp, etxregs + ETX_CFG) | ETX_CFG_DMAENABLE);
1632 /* This chip really rots, for the receiver sometimes when you
1633 * write to its control registers not all the bits get there
1634 * properly. I cannot think of a sane way to provide complete
1635 * coverage for this hardware bug yet.
1637 HMD(("erx regs bug old[%08x]\n",
1638 hme_read32(hp, erxregs + ERX_CFG)));
1639 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1640 regtmp = hme_read32(hp, erxregs + ERX_CFG);
1641 hme_write32(hp, erxregs + ERX_CFG, ERX_CFG_DEFAULT(RX_OFFSET));
1642 if (hme_read32(hp, erxregs + ERX_CFG) != ERX_CFG_DEFAULT(RX_OFFSET)) {
1643 printk(KERN_ERR "happy meal: Eieee, rx config register gets greasy fries.\n");
1644 printk(KERN_ERR "happy meal: Trying to set %08x, reread gives %08x\n",
1645 ERX_CFG_DEFAULT(RX_OFFSET), regtmp);
1646 /* XXX Should return failure here... */
1649 /* Enable Big Mac hash table filter. */
1650 HMD(("happy_meal_init: enable hash rx_cfg_old[%08x], ",
1651 hme_read32(hp, bregs + BMAC_RXCFG)));
1652 rxcfg = BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_REJME;
1653 if (hp->dev->flags & IFF_PROMISC)
1654 rxcfg |= BIGMAC_RXCFG_PMISC;
1655 hme_write32(hp, bregs + BMAC_RXCFG, rxcfg);
1657 /* Let the bits settle in the chip. */
1660 /* Ok, configure the Big Mac transmitter. */
1661 HMD(("BIGMAC init, "));
1663 if (hp->happy_flags & HFLAG_FULL)
1664 regtmp |= BIGMAC_TXCFG_FULLDPLX;
1666 /* Don't turn on the "don't give up" bit for now. It could cause hme
1667 * to deadlock with the PHY if a Jabber occurs.
1669 hme_write32(hp, bregs + BMAC_TXCFG, regtmp /*| BIGMAC_TXCFG_DGIVEUP*/);
1671 /* Give up after 16 TX attempts. */
1672 hme_write32(hp, bregs + BMAC_ALIMIT, 16);
1674 /* Enable the output drivers no matter what. */
1675 regtmp = BIGMAC_XCFG_ODENABLE;
1677 /* If card can do lance mode, enable it. */
1678 if (hp->happy_flags & HFLAG_LANCE)
1679 regtmp |= (DEFAULT_IPG0 << 5) | BIGMAC_XCFG_LANCE;
1681 /* Disable the MII buffers if using external transceiver. */
1682 if (hp->tcvr_type == external)
1683 regtmp |= BIGMAC_XCFG_MIIDISAB;
1685 HMD(("XIF config old[%08x], ",
1686 hme_read32(hp, bregs + BMAC_XIFCFG)));
1687 hme_write32(hp, bregs + BMAC_XIFCFG, regtmp);
1689 /* Start things up. */
1690 HMD(("tx old[%08x] and rx [%08x] ON!\n",
1691 hme_read32(hp, bregs + BMAC_TXCFG),
1692 hme_read32(hp, bregs + BMAC_RXCFG)));
1694 /* Set larger TX/RX size to allow for 802.1q */
1695 hme_write32(hp, bregs + BMAC_TXMAX, ETH_FRAME_LEN + 8);
1696 hme_write32(hp, bregs + BMAC_RXMAX, ETH_FRAME_LEN + 8);
1698 hme_write32(hp, bregs + BMAC_TXCFG,
1699 hme_read32(hp, bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE);
1700 hme_write32(hp, bregs + BMAC_RXCFG,
1701 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE);
1703 /* Get the autonegotiation started, and the watch timer ticking. */
1704 happy_meal_begin_auto_negotiation(hp, tregs, NULL);
1710 /* hp->happy_lock must be held */
1711 static void happy_meal_set_initial_advertisement(struct happy_meal *hp)
1713 void __iomem *tregs = hp->tcvregs;
1714 void __iomem *bregs = hp->bigmacregs;
1715 void __iomem *gregs = hp->gregs;
1717 happy_meal_stop(hp, gregs);
1718 hme_write32(hp, tregs + TCVR_IMASK, 0xffff);
1719 if (hp->happy_flags & HFLAG_FENABLE)
1720 hme_write32(hp, tregs + TCVR_CFG,
1721 hme_read32(hp, tregs + TCVR_CFG) & ~(TCV_CFG_BENABLE));
1723 hme_write32(hp, tregs + TCVR_CFG,
1724 hme_read32(hp, tregs + TCVR_CFG) | TCV_CFG_BENABLE);
1725 happy_meal_transceiver_check(hp, tregs);
1726 switch(hp->tcvr_type) {
1730 hme_write32(hp, bregs + BMAC_XIFCFG, 0);
1733 hme_write32(hp, bregs + BMAC_XIFCFG, BIGMAC_XCFG_MIIDISAB);
1736 if (happy_meal_tcvr_reset(hp, tregs))
1739 /* Latch PHY registers as of now. */
1740 hp->sw_bmsr = happy_meal_tcvr_read(hp, tregs, MII_BMSR);
1741 hp->sw_advertise = happy_meal_tcvr_read(hp, tregs, MII_ADVERTISE);
1743 /* Advertise everything we can support. */
1744 if (hp->sw_bmsr & BMSR_10HALF)
1745 hp->sw_advertise |= (ADVERTISE_10HALF);
1747 hp->sw_advertise &= ~(ADVERTISE_10HALF);
1749 if (hp->sw_bmsr & BMSR_10FULL)
1750 hp->sw_advertise |= (ADVERTISE_10FULL);
1752 hp->sw_advertise &= ~(ADVERTISE_10FULL);
1753 if (hp->sw_bmsr & BMSR_100HALF)
1754 hp->sw_advertise |= (ADVERTISE_100HALF);
1756 hp->sw_advertise &= ~(ADVERTISE_100HALF);
1757 if (hp->sw_bmsr & BMSR_100FULL)
1758 hp->sw_advertise |= (ADVERTISE_100FULL);
1760 hp->sw_advertise &= ~(ADVERTISE_100FULL);
1762 /* Update the PHY advertisement register. */
1763 happy_meal_tcvr_write(hp, tregs, MII_ADVERTISE, hp->sw_advertise);
1766 /* Once status is latched (by happy_meal_interrupt) it is cleared by
1767 * the hardware, so we cannot re-read it and get a correct value.
1769 * hp->happy_lock must be held
1771 static int happy_meal_is_not_so_happy(struct happy_meal *hp, u32 status)
1775 /* Only print messages for non-counter related interrupts. */
1776 if (status & (GREG_STAT_STSTERR | GREG_STAT_TFIFO_UND |
1777 GREG_STAT_MAXPKTERR | GREG_STAT_RXERR |
1778 GREG_STAT_RXPERR | GREG_STAT_RXTERR | GREG_STAT_EOPERR |
1779 GREG_STAT_MIFIRQ | GREG_STAT_TXEACK | GREG_STAT_TXLERR |
1780 GREG_STAT_TXPERR | GREG_STAT_TXTERR | GREG_STAT_SLVERR |
1782 printk(KERN_ERR "%s: Error interrupt for happy meal, status = %08x\n",
1783 hp->dev->name, status);
1785 if (status & GREG_STAT_RFIFOVF) {
1786 /* Receive FIFO overflow is harmless and the hardware will take
1787 care of it, just some packets are lost. Who cares. */
1788 printk(KERN_DEBUG "%s: Happy Meal receive FIFO overflow.\n", hp->dev->name);
1791 if (status & GREG_STAT_STSTERR) {
1792 /* BigMAC SQE link test failed. */
1793 printk(KERN_ERR "%s: Happy Meal BigMAC SQE test failed.\n", hp->dev->name);
1797 if (status & GREG_STAT_TFIFO_UND) {
1798 /* Transmit FIFO underrun, again DMA error likely. */
1799 printk(KERN_ERR "%s: Happy Meal transmitter FIFO underrun, DMA error.\n",
1804 if (status & GREG_STAT_MAXPKTERR) {
1805 /* Driver error, tried to transmit something larger
1806 * than ethernet max mtu.
1808 printk(KERN_ERR "%s: Happy Meal MAX Packet size error.\n", hp->dev->name);
1812 if (status & GREG_STAT_NORXD) {
1813 /* This is harmless, it just means the system is
1814 * quite loaded and the incoming packet rate was
1815 * faster than the interrupt handler could keep up
1818 printk(KERN_INFO "%s: Happy Meal out of receive "
1819 "descriptors, packet dropped.\n",
1823 if (status & (GREG_STAT_RXERR|GREG_STAT_RXPERR|GREG_STAT_RXTERR)) {
1824 /* All sorts of DMA receive errors. */
1825 printk(KERN_ERR "%s: Happy Meal rx DMA errors [ ", hp->dev->name);
1826 if (status & GREG_STAT_RXERR)
1827 printk("GenericError ");
1828 if (status & GREG_STAT_RXPERR)
1829 printk("ParityError ");
1830 if (status & GREG_STAT_RXTERR)
1831 printk("RxTagBotch ");
1836 if (status & GREG_STAT_EOPERR) {
1837 /* Driver bug, didn't set EOP bit in tx descriptor given
1838 * to the happy meal.
1840 printk(KERN_ERR "%s: EOP not set in happy meal transmit descriptor!\n",
1845 if (status & GREG_STAT_MIFIRQ) {
1846 /* MIF signalled an interrupt, were we polling it? */
1847 printk(KERN_ERR "%s: Happy Meal MIF interrupt.\n", hp->dev->name);
1851 (GREG_STAT_TXEACK|GREG_STAT_TXLERR|GREG_STAT_TXPERR|GREG_STAT_TXTERR)) {
1852 /* All sorts of transmit DMA errors. */
1853 printk(KERN_ERR "%s: Happy Meal tx DMA errors [ ", hp->dev->name);
1854 if (status & GREG_STAT_TXEACK)
1855 printk("GenericError ");
1856 if (status & GREG_STAT_TXLERR)
1857 printk("LateError ");
1858 if (status & GREG_STAT_TXPERR)
1859 printk("ParityErro ");
1860 if (status & GREG_STAT_TXTERR)
1861 printk("TagBotch ");
1866 if (status & (GREG_STAT_SLVERR|GREG_STAT_SLVPERR)) {
1867 /* Bus or parity error when cpu accessed happy meal registers
1868 * or it's internal FIFO's. Should never see this.
1870 printk(KERN_ERR "%s: Happy Meal register access SBUS slave (%s) error.\n",
1872 (status & GREG_STAT_SLVPERR) ? "parity" : "generic");
1877 printk(KERN_NOTICE "%s: Resetting...\n", hp->dev->name);
1878 happy_meal_init(hp);
1884 /* hp->happy_lock must be held */
1885 static void happy_meal_mif_interrupt(struct happy_meal *hp)
1887 void __iomem *tregs = hp->tcvregs;
1889 printk(KERN_INFO "%s: Link status change.\n", hp->dev->name);
1890 hp->sw_bmcr = happy_meal_tcvr_read(hp, tregs, MII_BMCR);
1891 hp->sw_lpa = happy_meal_tcvr_read(hp, tregs, MII_LPA);
1893 /* Use the fastest transmission protocol possible. */
1894 if (hp->sw_lpa & LPA_100FULL) {
1895 printk(KERN_INFO "%s: Switching to 100Mbps at full duplex.", hp->dev->name);
1896 hp->sw_bmcr |= (BMCR_FULLDPLX | BMCR_SPEED100);
1897 } else if (hp->sw_lpa & LPA_100HALF) {
1898 printk(KERN_INFO "%s: Switching to 100MBps at half duplex.", hp->dev->name);
1899 hp->sw_bmcr |= BMCR_SPEED100;
1900 } else if (hp->sw_lpa & LPA_10FULL) {
1901 printk(KERN_INFO "%s: Switching to 10MBps at full duplex.", hp->dev->name);
1902 hp->sw_bmcr |= BMCR_FULLDPLX;
1904 printk(KERN_INFO "%s: Using 10Mbps at half duplex.", hp->dev->name);
1906 happy_meal_tcvr_write(hp, tregs, MII_BMCR, hp->sw_bmcr);
1908 /* Finally stop polling and shut up the MIF. */
1909 happy_meal_poll_stop(hp, tregs);
1913 #define TXD(x) printk x
1918 /* hp->happy_lock must be held */
1919 static void happy_meal_tx(struct happy_meal *hp)
1921 struct happy_meal_txd *txbase = &hp->happy_block->happy_meal_txd[0];
1922 struct happy_meal_txd *this;
1923 struct net_device *dev = hp->dev;
1928 while (elem != hp->tx_new) {
1929 struct sk_buff *skb;
1930 u32 flags, dma_addr, dma_len;
1933 TXD(("[%d]", elem));
1934 this = &txbase[elem];
1935 flags = hme_read_desc32(hp, &this->tx_flags);
1936 if (flags & TXFLAG_OWN)
1938 skb = hp->tx_skbs[elem];
1939 if (skb_shinfo(skb)->nr_frags) {
1942 last = elem + skb_shinfo(skb)->nr_frags;
1943 last &= (TX_RING_SIZE - 1);
1944 flags = hme_read_desc32(hp, &txbase[last].tx_flags);
1945 if (flags & TXFLAG_OWN)
1948 hp->tx_skbs[elem] = NULL;
1949 hp->net_stats.tx_bytes += skb->len;
1951 for (frag = 0; frag <= skb_shinfo(skb)->nr_frags; frag++) {
1952 dma_addr = hme_read_desc32(hp, &this->tx_addr);
1953 dma_len = hme_read_desc32(hp, &this->tx_flags);
1955 dma_len &= TXFLAG_SIZE;
1956 dma_unmap_single(hp->dma_dev, dma_addr, dma_len, DMA_TO_DEVICE);
1958 elem = NEXT_TX(elem);
1959 this = &txbase[elem];
1962 dev_kfree_skb_irq(skb);
1963 hp->net_stats.tx_packets++;
1968 if (netif_queue_stopped(dev) &&
1969 TX_BUFFS_AVAIL(hp) > (MAX_SKB_FRAGS + 1))
1970 netif_wake_queue(dev);
1974 #define RXD(x) printk x
1979 /* Originally I used to handle the allocation failure by just giving back just
1980 * that one ring buffer to the happy meal. Problem is that usually when that
1981 * condition is triggered, the happy meal expects you to do something reasonable
1982 * with all of the packets it has DMA'd in. So now I just drop the entire
1983 * ring when we cannot get a new skb and give them all back to the happy meal,
1984 * maybe things will be "happier" now.
1986 * hp->happy_lock must be held
1988 static void happy_meal_rx(struct happy_meal *hp, struct net_device *dev)
1990 struct happy_meal_rxd *rxbase = &hp->happy_block->happy_meal_rxd[0];
1991 struct happy_meal_rxd *this;
1992 int elem = hp->rx_new, drops = 0;
1996 this = &rxbase[elem];
1997 while (!((flags = hme_read_desc32(hp, &this->rx_flags)) & RXFLAG_OWN)) {
1998 struct sk_buff *skb;
1999 int len = flags >> 16;
2000 u16 csum = flags & RXFLAG_CSUM;
2001 u32 dma_addr = hme_read_desc32(hp, &this->rx_addr);
2003 RXD(("[%d ", elem));
2005 /* Check for errors. */
2006 if ((len < ETH_ZLEN) || (flags & RXFLAG_OVERFLOW)) {
2007 RXD(("ERR(%08x)]", flags));
2008 hp->net_stats.rx_errors++;
2010 hp->net_stats.rx_length_errors++;
2011 if (len & (RXFLAG_OVERFLOW >> 16)) {
2012 hp->net_stats.rx_over_errors++;
2013 hp->net_stats.rx_fifo_errors++;
2016 /* Return it to the Happy meal. */
2018 hp->net_stats.rx_dropped++;
2019 hme_write_rxd(hp, this,
2020 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2024 skb = hp->rx_skbs[elem];
2025 if (len > RX_COPY_THRESHOLD) {
2026 struct sk_buff *new_skb;
2028 /* Now refill the entry, if we can. */
2029 new_skb = happy_meal_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
2030 if (new_skb == NULL) {
2034 dma_unmap_single(hp->dma_dev, dma_addr, RX_BUF_ALLOC_SIZE, DMA_FROM_DEVICE);
2035 hp->rx_skbs[elem] = new_skb;
2037 skb_put(new_skb, (ETH_FRAME_LEN + RX_OFFSET + 4));
2038 hme_write_rxd(hp, this,
2039 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2040 dma_map_single(hp->dma_dev, new_skb->data, RX_BUF_ALLOC_SIZE,
2042 skb_reserve(new_skb, RX_OFFSET);
2044 /* Trim the original skb for the netif. */
2047 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
2049 if (copy_skb == NULL) {
2054 skb_reserve(copy_skb, 2);
2055 skb_put(copy_skb, len);
2056 dma_sync_single_for_cpu(hp->dma_dev, dma_addr, len, DMA_FROM_DEVICE);
2057 skb_copy_from_linear_data(skb, copy_skb->data, len);
2058 dma_sync_single_for_device(hp->dma_dev, dma_addr, len, DMA_FROM_DEVICE);
2059 /* Reuse original ring buffer. */
2060 hme_write_rxd(hp, this,
2061 (RXFLAG_OWN|((RX_BUF_ALLOC_SIZE-RX_OFFSET)<<16)),
2067 /* This card is _fucking_ hot... */
2068 skb->csum = csum_unfold(~(__force __sum16)htons(csum));
2069 skb->ip_summed = CHECKSUM_COMPLETE;
2071 RXD(("len=%d csum=%4x]", len, csum));
2072 skb->protocol = eth_type_trans(skb, dev);
2075 dev->last_rx = jiffies;
2076 hp->net_stats.rx_packets++;
2077 hp->net_stats.rx_bytes += len;
2079 elem = NEXT_RX(elem);
2080 this = &rxbase[elem];
2084 printk(KERN_INFO "%s: Memory squeeze, deferring packet.\n", hp->dev->name);
2088 static irqreturn_t happy_meal_interrupt(int irq, void *dev_id)
2090 struct net_device *dev = dev_id;
2091 struct happy_meal *hp = netdev_priv(dev);
2092 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2094 HMD(("happy_meal_interrupt: status=%08x ", happy_status));
2096 spin_lock(&hp->happy_lock);
2098 if (happy_status & GREG_STAT_ERRORS) {
2100 if (happy_meal_is_not_so_happy(hp, /* un- */ happy_status))
2104 if (happy_status & GREG_STAT_MIFIRQ) {
2106 happy_meal_mif_interrupt(hp);
2109 if (happy_status & GREG_STAT_TXALL) {
2114 if (happy_status & GREG_STAT_RXTOHOST) {
2116 happy_meal_rx(hp, dev);
2121 spin_unlock(&hp->happy_lock);
2127 static irqreturn_t quattro_sbus_interrupt(int irq, void *cookie)
2129 struct quattro *qp = (struct quattro *) cookie;
2132 for (i = 0; i < 4; i++) {
2133 struct net_device *dev = qp->happy_meals[i];
2134 struct happy_meal *hp = dev->priv;
2135 u32 happy_status = hme_read32(hp, hp->gregs + GREG_STAT);
2137 HMD(("quattro_interrupt: status=%08x ", happy_status));
2139 if (!(happy_status & (GREG_STAT_ERRORS |
2142 GREG_STAT_RXTOHOST)))
2145 spin_lock(&hp->happy_lock);
2147 if (happy_status & GREG_STAT_ERRORS) {
2149 if (happy_meal_is_not_so_happy(hp, happy_status))
2153 if (happy_status & GREG_STAT_MIFIRQ) {
2155 happy_meal_mif_interrupt(hp);
2158 if (happy_status & GREG_STAT_TXALL) {
2163 if (happy_status & GREG_STAT_RXTOHOST) {
2165 happy_meal_rx(hp, dev);
2169 spin_unlock(&hp->happy_lock);
2177 static int happy_meal_open(struct net_device *dev)
2179 struct happy_meal *hp = dev->priv;
2182 HMD(("happy_meal_open: "));
2184 /* On SBUS Quattro QFE cards, all hme interrupts are concentrated
2185 * into a single source which we register handling at probe time.
2187 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO) {
2188 if (request_irq(dev->irq, &happy_meal_interrupt,
2189 IRQF_SHARED, dev->name, (void *)dev)) {
2191 printk(KERN_ERR "happy_meal(SBUS): Can't order irq %d to go.\n",
2198 HMD(("to happy_meal_init\n"));
2200 spin_lock_irq(&hp->happy_lock);
2201 res = happy_meal_init(hp);
2202 spin_unlock_irq(&hp->happy_lock);
2204 if (res && ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO))
2205 free_irq(dev->irq, dev);
2209 static int happy_meal_close(struct net_device *dev)
2211 struct happy_meal *hp = dev->priv;
2213 spin_lock_irq(&hp->happy_lock);
2214 happy_meal_stop(hp, hp->gregs);
2215 happy_meal_clean_rings(hp);
2217 /* If auto-negotiation timer is running, kill it. */
2218 del_timer(&hp->happy_timer);
2220 spin_unlock_irq(&hp->happy_lock);
2222 /* On Quattro QFE cards, all hme interrupts are concentrated
2223 * into a single source which we register handling at probe
2224 * time and never unregister.
2226 if ((hp->happy_flags & (HFLAG_QUATTRO|HFLAG_PCI)) != HFLAG_QUATTRO)
2227 free_irq(dev->irq, dev);
2233 #define SXD(x) printk x
2238 static void happy_meal_tx_timeout(struct net_device *dev)
2240 struct happy_meal *hp = dev->priv;
2242 printk (KERN_ERR "%s: transmit timed out, resetting\n", dev->name);
2244 printk (KERN_ERR "%s: Happy Status %08x TX[%08x:%08x]\n", dev->name,
2245 hme_read32(hp, hp->gregs + GREG_STAT),
2246 hme_read32(hp, hp->etxregs + ETX_CFG),
2247 hme_read32(hp, hp->bigmacregs + BMAC_TXCFG));
2249 spin_lock_irq(&hp->happy_lock);
2250 happy_meal_init(hp);
2251 spin_unlock_irq(&hp->happy_lock);
2253 netif_wake_queue(dev);
2256 static int happy_meal_start_xmit(struct sk_buff *skb, struct net_device *dev)
2258 struct happy_meal *hp = dev->priv;
2262 tx_flags = TXFLAG_OWN;
2263 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2264 const u32 csum_start_off = skb_transport_offset(skb);
2265 const u32 csum_stuff_off = csum_start_off + skb->csum_offset;
2267 tx_flags = (TXFLAG_OWN | TXFLAG_CSENABLE |
2268 ((csum_start_off << 14) & TXFLAG_CSBUFBEGIN) |
2269 ((csum_stuff_off << 20) & TXFLAG_CSLOCATION));
2272 spin_lock_irq(&hp->happy_lock);
2274 if (TX_BUFFS_AVAIL(hp) <= (skb_shinfo(skb)->nr_frags + 1)) {
2275 netif_stop_queue(dev);
2276 spin_unlock_irq(&hp->happy_lock);
2277 printk(KERN_ERR "%s: BUG! Tx Ring full when queue awake!\n",
2283 SXD(("SX<l[%d]e[%d]>", len, entry));
2284 hp->tx_skbs[entry] = skb;
2286 if (skb_shinfo(skb)->nr_frags == 0) {
2290 mapping = dma_map_single(hp->dma_dev, skb->data, len, DMA_TO_DEVICE);
2291 tx_flags |= (TXFLAG_SOP | TXFLAG_EOP);
2292 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2293 (tx_flags | (len & TXFLAG_SIZE)),
2295 entry = NEXT_TX(entry);
2297 u32 first_len, first_mapping;
2298 int frag, first_entry = entry;
2300 /* We must give this initial chunk to the device last.
2301 * Otherwise we could race with the device.
2303 first_len = skb_headlen(skb);
2304 first_mapping = dma_map_single(hp->dma_dev, skb->data, first_len,
2306 entry = NEXT_TX(entry);
2308 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
2309 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
2310 u32 len, mapping, this_txflags;
2312 len = this_frag->size;
2313 mapping = dma_map_page(hp->dma_dev, this_frag->page,
2314 this_frag->page_offset, len,
2316 this_txflags = tx_flags;
2317 if (frag == skb_shinfo(skb)->nr_frags - 1)
2318 this_txflags |= TXFLAG_EOP;
2319 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[entry],
2320 (this_txflags | (len & TXFLAG_SIZE)),
2322 entry = NEXT_TX(entry);
2324 hme_write_txd(hp, &hp->happy_block->happy_meal_txd[first_entry],
2325 (tx_flags | TXFLAG_SOP | (first_len & TXFLAG_SIZE)),
2331 if (TX_BUFFS_AVAIL(hp) <= (MAX_SKB_FRAGS + 1))
2332 netif_stop_queue(dev);
2335 hme_write32(hp, hp->etxregs + ETX_PENDING, ETX_TP_DMAWAKEUP);
2337 spin_unlock_irq(&hp->happy_lock);
2339 dev->trans_start = jiffies;
2341 tx_add_log(hp, TXLOG_ACTION_TXMIT, 0);
2345 static struct net_device_stats *happy_meal_get_stats(struct net_device *dev)
2347 struct happy_meal *hp = dev->priv;
2349 spin_lock_irq(&hp->happy_lock);
2350 happy_meal_get_counters(hp, hp->bigmacregs);
2351 spin_unlock_irq(&hp->happy_lock);
2353 return &hp->net_stats;
2356 static void happy_meal_set_multicast(struct net_device *dev)
2358 struct happy_meal *hp = dev->priv;
2359 void __iomem *bregs = hp->bigmacregs;
2360 struct dev_mc_list *dmi = dev->mc_list;
2365 spin_lock_irq(&hp->happy_lock);
2367 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
2368 hme_write32(hp, bregs + BMAC_HTABLE0, 0xffff);
2369 hme_write32(hp, bregs + BMAC_HTABLE1, 0xffff);
2370 hme_write32(hp, bregs + BMAC_HTABLE2, 0xffff);
2371 hme_write32(hp, bregs + BMAC_HTABLE3, 0xffff);
2372 } else if (dev->flags & IFF_PROMISC) {
2373 hme_write32(hp, bregs + BMAC_RXCFG,
2374 hme_read32(hp, bregs + BMAC_RXCFG) | BIGMAC_RXCFG_PMISC);
2378 for (i = 0; i < 4; i++)
2381 for (i = 0; i < dev->mc_count; i++) {
2382 addrs = dmi->dmi_addr;
2388 crc = ether_crc_le(6, addrs);
2390 hash_table[crc >> 4] |= 1 << (crc & 0xf);
2392 hme_write32(hp, bregs + BMAC_HTABLE0, hash_table[0]);
2393 hme_write32(hp, bregs + BMAC_HTABLE1, hash_table[1]);
2394 hme_write32(hp, bregs + BMAC_HTABLE2, hash_table[2]);
2395 hme_write32(hp, bregs + BMAC_HTABLE3, hash_table[3]);
2398 spin_unlock_irq(&hp->happy_lock);
2401 /* Ethtool support... */
2402 static int hme_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2404 struct happy_meal *hp = dev->priv;
2407 (SUPPORTED_10baseT_Half | SUPPORTED_10baseT_Full |
2408 SUPPORTED_100baseT_Half | SUPPORTED_100baseT_Full |
2409 SUPPORTED_Autoneg | SUPPORTED_TP | SUPPORTED_MII);
2411 /* XXX hardcoded stuff for now */
2412 cmd->port = PORT_TP; /* XXX no MII support */
2413 cmd->transceiver = XCVR_INTERNAL; /* XXX no external xcvr support */
2414 cmd->phy_address = 0; /* XXX fixed PHYAD */
2416 /* Record PHY settings. */
2417 spin_lock_irq(&hp->happy_lock);
2418 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2419 hp->sw_lpa = happy_meal_tcvr_read(hp, hp->tcvregs, MII_LPA);
2420 spin_unlock_irq(&hp->happy_lock);
2422 if (hp->sw_bmcr & BMCR_ANENABLE) {
2423 cmd->autoneg = AUTONEG_ENABLE;
2425 (hp->sw_lpa & (LPA_100HALF | LPA_100FULL)) ?
2426 SPEED_100 : SPEED_10;
2427 if (cmd->speed == SPEED_100)
2429 (hp->sw_lpa & (LPA_100FULL)) ?
2430 DUPLEX_FULL : DUPLEX_HALF;
2433 (hp->sw_lpa & (LPA_10FULL)) ?
2434 DUPLEX_FULL : DUPLEX_HALF;
2436 cmd->autoneg = AUTONEG_DISABLE;
2438 (hp->sw_bmcr & BMCR_SPEED100) ?
2439 SPEED_100 : SPEED_10;
2441 (hp->sw_bmcr & BMCR_FULLDPLX) ?
2442 DUPLEX_FULL : DUPLEX_HALF;
2447 static int hme_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
2449 struct happy_meal *hp = dev->priv;
2451 /* Verify the settings we care about. */
2452 if (cmd->autoneg != AUTONEG_ENABLE &&
2453 cmd->autoneg != AUTONEG_DISABLE)
2455 if (cmd->autoneg == AUTONEG_DISABLE &&
2456 ((cmd->speed != SPEED_100 &&
2457 cmd->speed != SPEED_10) ||
2458 (cmd->duplex != DUPLEX_HALF &&
2459 cmd->duplex != DUPLEX_FULL)))
2462 /* Ok, do it to it. */
2463 spin_lock_irq(&hp->happy_lock);
2464 del_timer(&hp->happy_timer);
2465 happy_meal_begin_auto_negotiation(hp, hp->tcvregs, cmd);
2466 spin_unlock_irq(&hp->happy_lock);
2471 static void hme_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
2473 struct happy_meal *hp = dev->priv;
2475 strcpy(info->driver, "sunhme");
2476 strcpy(info->version, "2.02");
2477 if (hp->happy_flags & HFLAG_PCI) {
2478 struct pci_dev *pdev = hp->happy_dev;
2479 strcpy(info->bus_info, pci_name(pdev));
2483 const struct linux_prom_registers *regs;
2484 struct of_device *op = hp->happy_dev;
2485 regs = of_get_property(op->node, "regs", NULL);
2487 sprintf(info->bus_info, "SBUS:%d",
2493 static u32 hme_get_link(struct net_device *dev)
2495 struct happy_meal *hp = dev->priv;
2497 spin_lock_irq(&hp->happy_lock);
2498 hp->sw_bmcr = happy_meal_tcvr_read(hp, hp->tcvregs, MII_BMCR);
2499 spin_unlock_irq(&hp->happy_lock);
2501 return (hp->sw_bmsr & BMSR_LSTATUS);
2504 static const struct ethtool_ops hme_ethtool_ops = {
2505 .get_settings = hme_get_settings,
2506 .set_settings = hme_set_settings,
2507 .get_drvinfo = hme_get_drvinfo,
2508 .get_link = hme_get_link,
2511 static int hme_version_printed;
2514 /* Given a happy meal sbus device, find it's quattro parent.
2515 * If none exist, allocate and return a new one.
2517 * Return NULL on failure.
2519 static struct quattro * __devinit quattro_sbus_find(struct of_device *child)
2521 struct device *parent = child->dev.parent;
2522 struct of_device *op;
2525 op = to_of_device(parent);
2526 qp = dev_get_drvdata(&op->dev);
2530 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2534 for (i = 0; i < 4; i++)
2535 qp->happy_meals[i] = NULL;
2537 qp->quattro_dev = child;
2538 qp->next = qfe_sbus_list;
2541 dev_set_drvdata(&op->dev, qp);
2546 /* After all quattro cards have been probed, we call these functions
2547 * to register the IRQ handlers.
2549 static void __init quattro_sbus_register_irqs(void)
2553 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2554 struct of_device *op = qp->quattro_dev;
2557 err = request_irq(op->irqs[0],
2558 quattro_sbus_interrupt,
2559 IRQF_SHARED, "Quattro",
2562 printk(KERN_ERR "Quattro: Fatal IRQ registery error %d.\n", err);
2563 panic("QFE request irq");
2568 static void quattro_sbus_free_irqs(void)
2572 for (qp = qfe_sbus_list; qp != NULL; qp = qp->next) {
2573 struct of_device *op = qp->quattro_dev;
2575 free_irq(op->irqs[0], qp);
2578 #endif /* CONFIG_SBUS */
2581 static struct quattro * __devinit quattro_pci_find(struct pci_dev *pdev)
2583 struct pci_dev *bdev = pdev->bus->self;
2586 if (!bdev) return NULL;
2587 for (qp = qfe_pci_list; qp != NULL; qp = qp->next) {
2588 struct pci_dev *qpdev = qp->quattro_dev;
2593 qp = kmalloc(sizeof(struct quattro), GFP_KERNEL);
2597 for (i = 0; i < 4; i++)
2598 qp->happy_meals[i] = NULL;
2600 qp->quattro_dev = bdev;
2601 qp->next = qfe_pci_list;
2604 /* No range tricks necessary on PCI. */
2609 #endif /* CONFIG_PCI */
2612 static int __devinit happy_meal_sbus_probe_one(struct of_device *op, int is_qfe)
2614 struct device_node *dp = op->node, *sbus_dp;
2615 struct quattro *qp = NULL;
2616 struct happy_meal *hp;
2617 struct net_device *dev;
2618 int i, qfe_slot = -1;
2620 DECLARE_MAC_BUF(mac);
2623 qp = quattro_sbus_find(op);
2626 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2627 if (qp->happy_meals[qfe_slot] == NULL)
2634 dev = alloc_etherdev(sizeof(struct happy_meal));
2637 SET_NETDEV_DEV(dev, &op->dev);
2639 if (hme_version_printed++ == 0)
2640 printk(KERN_INFO "%s", version);
2642 /* If user did not specify a MAC address specifically, use
2643 * the Quattro local-mac-address property...
2645 for (i = 0; i < 6; i++) {
2646 if (macaddr[i] != 0)
2649 if (i < 6) { /* a mac address was given */
2650 for (i = 0; i < 6; i++)
2651 dev->dev_addr[i] = macaddr[i];
2654 const unsigned char *addr;
2657 addr = of_get_property(dp, "local-mac-address", &len);
2659 if (qfe_slot != -1 && addr && len == 6)
2660 memcpy(dev->dev_addr, addr, 6);
2662 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
2665 hp = netdev_priv(dev);
2668 hp->dma_dev = &op->dev;
2670 spin_lock_init(&hp->happy_lock);
2674 hp->qfe_parent = qp;
2675 hp->qfe_ent = qfe_slot;
2676 qp->happy_meals[qfe_slot] = dev;
2679 hp->gregs = of_ioremap(&op->resource[0], 0,
2680 GREG_REG_SIZE, "HME Global Regs");
2682 printk(KERN_ERR "happymeal: Cannot map global registers.\n");
2683 goto err_out_free_netdev;
2686 hp->etxregs = of_ioremap(&op->resource[1], 0,
2687 ETX_REG_SIZE, "HME TX Regs");
2689 printk(KERN_ERR "happymeal: Cannot map MAC TX registers.\n");
2690 goto err_out_iounmap;
2693 hp->erxregs = of_ioremap(&op->resource[2], 0,
2694 ERX_REG_SIZE, "HME RX Regs");
2696 printk(KERN_ERR "happymeal: Cannot map MAC RX registers.\n");
2697 goto err_out_iounmap;
2700 hp->bigmacregs = of_ioremap(&op->resource[3], 0,
2701 BMAC_REG_SIZE, "HME BIGMAC Regs");
2702 if (!hp->bigmacregs) {
2703 printk(KERN_ERR "happymeal: Cannot map BIGMAC registers.\n");
2704 goto err_out_iounmap;
2707 hp->tcvregs = of_ioremap(&op->resource[4], 0,
2708 TCVR_REG_SIZE, "HME Tranceiver Regs");
2710 printk(KERN_ERR "happymeal: Cannot map TCVR registers.\n");
2711 goto err_out_iounmap;
2714 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
2715 if (hp->hm_revision == 0xff)
2716 hp->hm_revision = 0xa0;
2718 /* Now enable the feature flags we can. */
2719 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
2720 hp->happy_flags = HFLAG_20_21;
2721 else if (hp->hm_revision != 0xa0)
2722 hp->happy_flags = HFLAG_NOT_A0;
2725 hp->happy_flags |= HFLAG_QUATTRO;
2727 sbus_dp = to_of_device(op->dev.parent)->node;
2729 sbus_dp = to_of_device(op->dev.parent->parent)->node;
2731 /* Get the supported DVMA burst sizes from our Happy SBUS. */
2732 hp->happy_bursts = of_getintprop_default(sbus_dp,
2733 "burst-sizes", 0x00);
2735 hp->happy_block = dma_alloc_coherent(hp->dma_dev,
2740 if (!hp->happy_block) {
2741 printk(KERN_ERR "happymeal: Cannot allocate descriptors.\n");
2742 goto err_out_iounmap;
2745 /* Force check of the link first time we are brought up. */
2748 /* Force timer state to 'asleep' with count of zero. */
2749 hp->timer_state = asleep;
2750 hp->timer_ticks = 0;
2752 init_timer(&hp->happy_timer);
2755 dev->open = &happy_meal_open;
2756 dev->stop = &happy_meal_close;
2757 dev->hard_start_xmit = &happy_meal_start_xmit;
2758 dev->get_stats = &happy_meal_get_stats;
2759 dev->set_multicast_list = &happy_meal_set_multicast;
2760 dev->tx_timeout = &happy_meal_tx_timeout;
2761 dev->watchdog_timeo = 5*HZ;
2762 dev->ethtool_ops = &hme_ethtool_ops;
2764 /* Happy Meal can do it all... */
2765 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
2767 dev->irq = op->irqs[0];
2769 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
2770 /* Hook up SBUS register/descriptor accessors. */
2771 hp->read_desc32 = sbus_hme_read_desc32;
2772 hp->write_txd = sbus_hme_write_txd;
2773 hp->write_rxd = sbus_hme_write_rxd;
2774 hp->read32 = sbus_hme_read32;
2775 hp->write32 = sbus_hme_write32;
2778 /* Grrr, Happy Meal comes up by default not advertising
2779 * full duplex 100baseT capabilities, fix this.
2781 spin_lock_irq(&hp->happy_lock);
2782 happy_meal_set_initial_advertisement(hp);
2783 spin_unlock_irq(&hp->happy_lock);
2785 if (register_netdev(hp->dev)) {
2786 printk(KERN_ERR "happymeal: Cannot register net device, "
2788 goto err_out_free_coherent;
2791 dev_set_drvdata(&op->dev, hp);
2794 printk(KERN_INFO "%s: Quattro HME slot %d (SBUS) 10/100baseT Ethernet ",
2795 dev->name, qfe_slot);
2797 printk(KERN_INFO "%s: HAPPY MEAL (SBUS) 10/100baseT Ethernet ",
2800 printk("%s\n", print_mac(mac, dev->dev_addr));
2804 err_out_free_coherent:
2805 dma_free_coherent(hp->dma_dev,
2812 of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
2814 of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
2816 of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
2818 of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
2820 of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
2822 err_out_free_netdev:
2831 #ifndef CONFIG_SPARC
2832 static int is_quattro_p(struct pci_dev *pdev)
2834 struct pci_dev *busdev = pdev->bus->self;
2835 struct list_head *tmp;
2838 if (busdev == NULL ||
2839 busdev->vendor != PCI_VENDOR_ID_DEC ||
2840 busdev->device != PCI_DEVICE_ID_DEC_21153)
2844 tmp = pdev->bus->devices.next;
2845 while (tmp != &pdev->bus->devices) {
2846 struct pci_dev *this_pdev = pci_dev_b(tmp);
2848 if (this_pdev->vendor == PCI_VENDOR_ID_SUN &&
2849 this_pdev->device == PCI_DEVICE_ID_SUN_HAPPYMEAL)
2861 /* Fetch MAC address from vital product data of PCI ROM. */
2862 static int find_eth_addr_in_vpd(void __iomem *rom_base, int len, int index, unsigned char *dev_addr)
2866 for (this_offset = 0x20; this_offset < len; this_offset++) {
2867 void __iomem *p = rom_base + this_offset;
2869 if (readb(p + 0) != 0x90 ||
2870 readb(p + 1) != 0x00 ||
2871 readb(p + 2) != 0x09 ||
2872 readb(p + 3) != 0x4e ||
2873 readb(p + 4) != 0x41 ||
2874 readb(p + 5) != 0x06)
2883 for (i = 0; i < 6; i++)
2884 dev_addr[i] = readb(p + i);
2892 static void get_hme_mac_nonsparc(struct pci_dev *pdev, unsigned char *dev_addr)
2895 void __iomem *p = pci_map_rom(pdev, &size);
2901 if (is_quattro_p(pdev))
2902 index = PCI_SLOT(pdev->devfn);
2904 found = readb(p) == 0x55 &&
2905 readb(p + 1) == 0xaa &&
2906 find_eth_addr_in_vpd(p, (64 * 1024), index, dev_addr);
2907 pci_unmap_rom(pdev, p);
2912 /* Sun MAC prefix then 3 random bytes. */
2916 get_random_bytes(&dev_addr[3], 3);
2919 #endif /* !(CONFIG_SPARC) */
2921 static int __devinit happy_meal_pci_probe(struct pci_dev *pdev,
2922 const struct pci_device_id *ent)
2924 struct quattro *qp = NULL;
2926 struct device_node *dp;
2928 struct happy_meal *hp;
2929 struct net_device *dev;
2930 void __iomem *hpreg_base;
2931 unsigned long hpreg_res;
2932 int i, qfe_slot = -1;
2935 DECLARE_MAC_BUF(mac);
2937 /* Now make sure pci_dev cookie is there. */
2939 dp = pci_device_to_OF_node(pdev);
2940 strcpy(prom_name, dp->name);
2942 if (is_quattro_p(pdev))
2943 strcpy(prom_name, "SUNW,qfe");
2945 strcpy(prom_name, "SUNW,hme");
2950 if (pci_enable_device(pdev))
2952 pci_set_master(pdev);
2954 if (!strcmp(prom_name, "SUNW,qfe") || !strcmp(prom_name, "qfe")) {
2955 qp = quattro_pci_find(pdev);
2958 for (qfe_slot = 0; qfe_slot < 4; qfe_slot++)
2959 if (qp->happy_meals[qfe_slot] == NULL)
2965 dev = alloc_etherdev(sizeof(struct happy_meal));
2969 SET_NETDEV_DEV(dev, &pdev->dev);
2971 if (hme_version_printed++ == 0)
2972 printk(KERN_INFO "%s", version);
2974 dev->base_addr = (long) pdev;
2976 hp = (struct happy_meal *)dev->priv;
2977 memset(hp, 0, sizeof(*hp));
2979 hp->happy_dev = pdev;
2980 hp->dma_dev = &pdev->dev;
2982 spin_lock_init(&hp->happy_lock);
2985 hp->qfe_parent = qp;
2986 hp->qfe_ent = qfe_slot;
2987 qp->happy_meals[qfe_slot] = dev;
2990 hpreg_res = pci_resource_start(pdev, 0);
2992 if ((pci_resource_flags(pdev, 0) & IORESOURCE_IO) != 0) {
2993 printk(KERN_ERR "happymeal(PCI): Cannot find proper PCI device base address.\n");
2994 goto err_out_clear_quattro;
2996 if (pci_request_regions(pdev, DRV_NAME)) {
2997 printk(KERN_ERR "happymeal(PCI): Cannot obtain PCI resources, "
2999 goto err_out_clear_quattro;
3002 if ((hpreg_base = ioremap(hpreg_res, 0x8000)) == NULL) {
3003 printk(KERN_ERR "happymeal(PCI): Unable to remap card memory.\n");
3004 goto err_out_free_res;
3007 for (i = 0; i < 6; i++) {
3008 if (macaddr[i] != 0)
3011 if (i < 6) { /* a mac address was given */
3012 for (i = 0; i < 6; i++)
3013 dev->dev_addr[i] = macaddr[i];
3017 const unsigned char *addr;
3020 if (qfe_slot != -1 &&
3021 (addr = of_get_property(dp,
3022 "local-mac-address", &len)) != NULL
3024 memcpy(dev->dev_addr, addr, 6);
3026 memcpy(dev->dev_addr, idprom->id_ethaddr, 6);
3029 get_hme_mac_nonsparc(pdev, &dev->dev_addr[0]);
3033 /* Layout registers. */
3034 hp->gregs = (hpreg_base + 0x0000UL);
3035 hp->etxregs = (hpreg_base + 0x2000UL);
3036 hp->erxregs = (hpreg_base + 0x4000UL);
3037 hp->bigmacregs = (hpreg_base + 0x6000UL);
3038 hp->tcvregs = (hpreg_base + 0x7000UL);
3041 hp->hm_revision = of_getintprop_default(dp, "hm-rev", 0xff);
3042 if (hp->hm_revision == 0xff)
3043 hp->hm_revision = 0xc0 | (pdev->revision & 0x0f);
3045 /* works with this on non-sparc hosts */
3046 hp->hm_revision = 0x20;
3049 /* Now enable the feature flags we can. */
3050 if (hp->hm_revision == 0x20 || hp->hm_revision == 0x21)
3051 hp->happy_flags = HFLAG_20_21;
3052 else if (hp->hm_revision != 0xa0 && hp->hm_revision != 0xc0)
3053 hp->happy_flags = HFLAG_NOT_A0;
3056 hp->happy_flags |= HFLAG_QUATTRO;
3058 /* And of course, indicate this is PCI. */
3059 hp->happy_flags |= HFLAG_PCI;
3062 /* Assume PCI happy meals can handle all burst sizes. */
3063 hp->happy_bursts = DMA_BURSTBITS;
3066 hp->happy_block = (struct hmeal_init_block *)
3067 dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &hp->hblock_dvma, GFP_KERNEL);
3070 if (!hp->happy_block) {
3071 printk(KERN_ERR "happymeal(PCI): Cannot get hme init block.\n");
3072 goto err_out_iounmap;
3076 hp->timer_state = asleep;
3077 hp->timer_ticks = 0;
3079 init_timer(&hp->happy_timer);
3082 dev->open = &happy_meal_open;
3083 dev->stop = &happy_meal_close;
3084 dev->hard_start_xmit = &happy_meal_start_xmit;
3085 dev->get_stats = &happy_meal_get_stats;
3086 dev->set_multicast_list = &happy_meal_set_multicast;
3087 dev->tx_timeout = &happy_meal_tx_timeout;
3088 dev->watchdog_timeo = 5*HZ;
3089 dev->ethtool_ops = &hme_ethtool_ops;
3090 dev->irq = pdev->irq;
3093 /* Happy Meal can do it all... */
3094 dev->features |= NETIF_F_SG | NETIF_F_HW_CSUM;
3096 #if defined(CONFIG_SBUS) && defined(CONFIG_PCI)
3097 /* Hook up PCI register/descriptor accessors. */
3098 hp->read_desc32 = pci_hme_read_desc32;
3099 hp->write_txd = pci_hme_write_txd;
3100 hp->write_rxd = pci_hme_write_rxd;
3101 hp->read32 = pci_hme_read32;
3102 hp->write32 = pci_hme_write32;
3105 /* Grrr, Happy Meal comes up by default not advertising
3106 * full duplex 100baseT capabilities, fix this.
3108 spin_lock_irq(&hp->happy_lock);
3109 happy_meal_set_initial_advertisement(hp);
3110 spin_unlock_irq(&hp->happy_lock);
3112 if (register_netdev(hp->dev)) {
3113 printk(KERN_ERR "happymeal(PCI): Cannot register net device, "
3115 goto err_out_iounmap;
3118 dev_set_drvdata(&pdev->dev, hp);
3121 struct pci_dev *qpdev = qp->quattro_dev;
3124 if (!strncmp(dev->name, "eth", 3)) {
3125 int i = simple_strtoul(dev->name + 3, NULL, 10);
3126 sprintf(prom_name, "-%d", i + 3);
3128 printk(KERN_INFO "%s%s: Quattro HME (PCI/CheerIO) 10/100baseT Ethernet ", dev->name, prom_name);
3129 if (qpdev->vendor == PCI_VENDOR_ID_DEC &&
3130 qpdev->device == PCI_DEVICE_ID_DEC_21153)
3131 printk("DEC 21153 PCI Bridge\n");
3133 printk("unknown bridge %04x.%04x\n",
3134 qpdev->vendor, qpdev->device);
3138 printk(KERN_INFO "%s: Quattro HME slot %d (PCI/CheerIO) 10/100baseT Ethernet ",
3139 dev->name, qfe_slot);
3141 printk(KERN_INFO "%s: HAPPY MEAL (PCI/CheerIO) 10/100BaseT Ethernet ",
3144 printk("%s\n", print_mac(mac, dev->dev_addr));
3152 pci_release_regions(pdev);
3154 err_out_clear_quattro:
3156 qp->happy_meals[qfe_slot] = NULL;
3164 static void __devexit happy_meal_pci_remove(struct pci_dev *pdev)
3166 struct happy_meal *hp = dev_get_drvdata(&pdev->dev);
3167 struct net_device *net_dev = hp->dev;
3169 unregister_netdev(net_dev);
3171 dma_free_coherent(hp->dma_dev, PAGE_SIZE,
3172 hp->happy_block, hp->hblock_dvma);
3174 pci_release_regions(hp->happy_dev);
3176 free_netdev(net_dev);
3178 dev_set_drvdata(&pdev->dev, NULL);
3181 static struct pci_device_id happymeal_pci_ids[] = {
3182 { PCI_DEVICE(PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_HAPPYMEAL) },
3183 { } /* Terminating entry */
3186 MODULE_DEVICE_TABLE(pci, happymeal_pci_ids);
3188 static struct pci_driver hme_pci_driver = {
3190 .id_table = happymeal_pci_ids,
3191 .probe = happy_meal_pci_probe,
3192 .remove = __devexit_p(happy_meal_pci_remove),
3195 static int __init happy_meal_pci_init(void)
3197 return pci_register_driver(&hme_pci_driver);
3200 static void happy_meal_pci_exit(void)
3202 pci_unregister_driver(&hme_pci_driver);
3204 while (qfe_pci_list) {
3205 struct quattro *qfe = qfe_pci_list;
3206 struct quattro *next = qfe->next;
3210 qfe_pci_list = next;
3217 static int __devinit hme_sbus_probe(struct of_device *op, const struct of_device_id *match)
3219 struct device_node *dp = op->node;
3220 const char *model = of_get_property(dp, "model", NULL);
3221 int is_qfe = (match->data != NULL);
3223 if (!is_qfe && model && !strcmp(model, "SUNW,sbus-qfe"))
3226 return happy_meal_sbus_probe_one(op, is_qfe);
3229 static int __devexit hme_sbus_remove(struct of_device *op)
3231 struct happy_meal *hp = dev_get_drvdata(&op->dev);
3232 struct net_device *net_dev = hp->dev;
3234 unregister_netdev(net_dev);
3236 /* XXX qfe parent interrupt... */
3238 of_iounmap(&op->resource[0], hp->gregs, GREG_REG_SIZE);
3239 of_iounmap(&op->resource[1], hp->etxregs, ETX_REG_SIZE);
3240 of_iounmap(&op->resource[2], hp->erxregs, ERX_REG_SIZE);
3241 of_iounmap(&op->resource[3], hp->bigmacregs, BMAC_REG_SIZE);
3242 of_iounmap(&op->resource[4], hp->tcvregs, TCVR_REG_SIZE);
3243 dma_free_coherent(hp->dma_dev,
3248 free_netdev(net_dev);
3250 dev_set_drvdata(&op->dev, NULL);
3255 static const struct of_device_id hme_sbus_match[] = {
3270 MODULE_DEVICE_TABLE(of, hme_sbus_match);
3272 static struct of_platform_driver hme_sbus_driver = {
3274 .match_table = hme_sbus_match,
3275 .probe = hme_sbus_probe,
3276 .remove = __devexit_p(hme_sbus_remove),
3279 static int __init happy_meal_sbus_init(void)
3283 err = of_register_driver(&hme_sbus_driver, &of_bus_type);
3285 quattro_sbus_register_irqs();
3290 static void happy_meal_sbus_exit(void)
3292 of_unregister_driver(&hme_sbus_driver);
3293 quattro_sbus_free_irqs();
3295 while (qfe_sbus_list) {
3296 struct quattro *qfe = qfe_sbus_list;
3297 struct quattro *next = qfe->next;
3301 qfe_sbus_list = next;
3306 static int __init happy_meal_probe(void)
3311 err = happy_meal_sbus_init();
3315 err = happy_meal_pci_init();
3318 happy_meal_sbus_exit();
3327 static void __exit happy_meal_exit(void)
3330 happy_meal_sbus_exit();
3333 happy_meal_pci_exit();
3337 module_init(happy_meal_probe);
3338 module_exit(happy_meal_exit);