1 #ifndef __SUNGEM_PHY_H__
2 #define __SUNGEM_PHY_H__
6 /* Operations supported by any kind of PHY */
9 int (*init)(struct mii_phy *phy);
10 int (*suspend)(struct mii_phy *phy);
11 int (*setup_aneg)(struct mii_phy *phy, u32 advertise);
12 int (*setup_forced)(struct mii_phy *phy, int speed, int fd);
13 int (*poll_link)(struct mii_phy *phy);
14 int (*read_link)(struct mii_phy *phy);
15 int (*enable_fiber)(struct mii_phy *phy);
18 /* Structure used to statically define an mii/gii based PHY */
21 u32 phy_id; /* Concatenated ID1 << 16 | ID2 */
22 u32 phy_id_mask; /* Significant bits */
23 u32 features; /* Ethtool SUPPORTED_* defines */
24 int magic_aneg; /* Autoneg does all speed test for us */
26 const struct mii_phy_ops* ops;
29 /* An instance of a PHY, partially borrowed from mii_if_info */
32 struct mii_phy_def* def;
36 /* 1: autoneg enabled, 0: disabled */
39 /* forced speed & duplex (no autoneg)
40 * partner speed & duplex & pause (autoneg)
46 /* Provided by host chip */
47 struct net_device *dev;
48 int (*mdio_read) (struct net_device *dev, int mii_id, int reg);
49 void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val);
53 /* Pass in a struct mii_phy with dev, mdio_read and mdio_write
54 * filled, the remaining fields will be filled on return
56 extern int mii_phy_probe(struct mii_phy *phy, int mii_id);
59 /* MII definitions missing from mii.h */
61 #define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */
62 #define LPA_PAUSE 0x0400
64 /* More PHY registers (model specific) */
66 /* MII BCM5201 MULTIPHY interrupt register */
67 #define MII_BCM5201_INTERRUPT 0x1A
68 #define MII_BCM5201_INTERRUPT_INTENABLE 0x4000
70 #define MII_BCM5201_AUXMODE2 0x1B
71 #define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008
73 #define MII_BCM5201_MULTIPHY 0x1E
75 /* MII BCM5201 MULTIPHY register bits */
76 #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002
77 #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008
79 /* MII BCM5221 Additional registers */
80 #define MII_BCM5221_TEST 0x1f
81 #define MII_BCM5221_TEST_ENABLE_SHADOWS 0x0080
82 #define MII_BCM5221_SHDOW_AUX_STAT2 0x1b
83 #define MII_BCM5221_SHDOW_AUX_STAT2_APD 0x0020
84 #define MII_BCM5221_SHDOW_AUX_MODE4 0x1a
85 #define MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE 0x0001
86 #define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004
88 /* MII BCM5400 1000-BASET Control register */
89 #define MII_BCM5400_GB_CONTROL 0x09
90 #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200
92 /* MII BCM5400 AUXCONTROL register */
93 #define MII_BCM5400_AUXCONTROL 0x18
94 #define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004
96 /* MII BCM5400 AUXSTATUS register */
97 #define MII_BCM5400_AUXSTATUS 0x19
98 #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700
99 #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8
101 /* 1000BT control (Marvell & BCM54xx at least) */
102 #define MII_1000BASETCONTROL 0x09
103 #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
104 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
106 /* Marvell 88E1011 PHY control */
107 #define MII_M1011_PHY_SPEC_CONTROL 0x10
108 #define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20
109 #define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40
111 /* Marvell 88E1011 PHY status */
112 #define MII_M1011_PHY_SPEC_STATUS 0x11
113 #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
114 #define MII_M1011_PHY_SPEC_STATUS_100 0x4000
115 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
116 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
117 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
119 #endif /* __SUNGEM_PHY_H__ */