1 #ifndef __SUNGEM_PHY_H__
2 #define __SUNGEM_PHY_H__
6 /* Operations supported by any kind of PHY */
9 int (*init)(struct mii_phy *phy);
10 int (*suspend)(struct mii_phy *phy);
11 int (*setup_aneg)(struct mii_phy *phy, u32 advertise);
12 int (*setup_forced)(struct mii_phy *phy, int speed, int fd);
13 int (*poll_link)(struct mii_phy *phy);
14 int (*read_link)(struct mii_phy *phy);
17 /* Structure used to statically define an mii/gii based PHY */
20 u32 phy_id; /* Concatenated ID1 << 16 | ID2 */
21 u32 phy_id_mask; /* Significant bits */
22 u32 features; /* Ethtool SUPPORTED_* defines */
23 int magic_aneg; /* Autoneg does all speed test for us */
25 const struct mii_phy_ops* ops;
28 /* An instance of a PHY, partially borrowed from mii_if_info */
31 struct mii_phy_def* def;
35 /* 1: autoneg enabled, 0: disabled */
38 /* forced speed & duplex (no autoneg)
39 * partner speed & duplex & pause (autoneg)
45 /* Provided by host chip */
46 struct net_device *dev;
47 int (*mdio_read) (struct net_device *dev, int mii_id, int reg);
48 void (*mdio_write) (struct net_device *dev, int mii_id, int reg, int val);
52 /* Pass in a struct mii_phy with dev, mdio_read and mdio_write
53 * filled, the remaining fields will be filled on return
55 extern int mii_phy_probe(struct mii_phy *phy, int mii_id);
58 /* MII definitions missing from mii.h */
60 #define BMCR_SPD2 0x0040 /* Gigabit enable (bcm54xx) */
61 #define LPA_PAUSE 0x0400
63 /* More PHY registers (model specific) */
65 /* MII BCM5201 MULTIPHY interrupt register */
66 #define MII_BCM5201_INTERRUPT 0x1A
67 #define MII_BCM5201_INTERRUPT_INTENABLE 0x4000
69 #define MII_BCM5201_AUXMODE2 0x1B
70 #define MII_BCM5201_AUXMODE2_LOWPOWER 0x0008
72 #define MII_BCM5201_MULTIPHY 0x1E
74 /* MII BCM5201 MULTIPHY register bits */
75 #define MII_BCM5201_MULTIPHY_SERIALMODE 0x0002
76 #define MII_BCM5201_MULTIPHY_SUPERISOLATE 0x0008
78 /* MII BCM5221 Additional registers */
79 #define MII_BCM5221_TEST 0x1f
80 #define MII_BCM5221_TEST_ENABLE_SHADOWS 0x0080
81 #define MII_BCM5221_SHDOW_AUX_STAT2 0x1b
82 #define MII_BCM5221_SHDOW_AUX_STAT2_APD 0x0020
83 #define MII_BCM5221_SHDOW_AUX_MODE4 0x1a
84 #define MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE 0x0001
85 #define MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR 0x0004
87 /* MII BCM5400 1000-BASET Control register */
88 #define MII_BCM5400_GB_CONTROL 0x09
89 #define MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP 0x0200
91 /* MII BCM5400 AUXCONTROL register */
92 #define MII_BCM5400_AUXCONTROL 0x18
93 #define MII_BCM5400_AUXCONTROL_PWR10BASET 0x0004
95 /* MII BCM5400 AUXSTATUS register */
96 #define MII_BCM5400_AUXSTATUS 0x19
97 #define MII_BCM5400_AUXSTATUS_LINKMODE_MASK 0x0700
98 #define MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT 8
100 /* 1000BT control (Marvell & BCM54xx at least) */
101 #define MII_1000BASETCONTROL 0x09
102 #define MII_1000BASETCONTROL_FULLDUPLEXCAP 0x0200
103 #define MII_1000BASETCONTROL_HALFDUPLEXCAP 0x0100
105 /* Marvell 88E1011 PHY control */
106 #define MII_M1011_PHY_SPEC_CONTROL 0x10
107 #define MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX 0x20
108 #define MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX 0x40
110 /* Marvell 88E1011 PHY status */
111 #define MII_M1011_PHY_SPEC_STATUS 0x11
112 #define MII_M1011_PHY_SPEC_STATUS_1000 0x8000
113 #define MII_M1011_PHY_SPEC_STATUS_100 0x4000
114 #define MII_M1011_PHY_SPEC_STATUS_SPD_MASK 0xc000
115 #define MII_M1011_PHY_SPEC_STATUS_FULLDUPLEX 0x2000
116 #define MII_M1011_PHY_SPEC_STATUS_RESOLVED 0x0800
118 #endif /* __SUNGEM_PHY_H__ */