1 /* sundance.c: A Linux device driver for the Sundance ST201 "Alta". */
3 Written 1999-2000 by Donald Becker.
5 This software may be used and distributed according to the terms of
6 the GNU General Public License (GPL), incorporated herein by reference.
7 Drivers based on or derived from this code fall under the GPL and must
8 retain the authorship, copyright and license notice. This file is not
9 a complete program and may only be used when the entire operating
10 system is licensed under the GPL.
12 The author may be reached as becker@scyld.com, or C/O
13 Scyld Computing Corporation
14 410 Severn Ave., Suite 210
17 Support and updates available at
18 http://www.scyld.com/network/sundance.html
19 [link no longer provides useful info -jgarzik]
20 Archives of the mailing list are still available at
21 http://www.beowulf.org/pipermail/netdrivers/
25 #define DRV_NAME "sundance"
26 #define DRV_VERSION "1.2"
27 #define DRV_RELDATE "11-Sep-2006"
30 /* The user-configurable values.
31 These may be modified when a driver module is loaded.*/
32 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
33 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
34 Typical is a 64 element hash table based on the Ethernet CRC. */
35 static const int multicast_filter_limit = 32;
37 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
38 Setting to > 1518 effectively disables this feature.
39 This chip can receive into offset buffers, so the Alpha does not
41 static int rx_copybreak;
42 static int flowctrl=1;
44 /* media[] specifies the media type the NIC operates at.
45 autosense Autosensing active media.
46 10mbps_hd 10Mbps half duplex.
47 10mbps_fd 10Mbps full duplex.
48 100mbps_hd 100Mbps half duplex.
49 100mbps_fd 100Mbps full duplex.
50 0 Autosensing active media.
53 3 100Mbps half duplex.
54 4 100Mbps full duplex.
57 static char *media[MAX_UNITS];
60 /* Operational parameters that are set at compile time. */
62 /* Keep the ring sizes a power of two for compile efficiency.
63 The compiler will convert <unsigned>'%'<2^N> into a bit mask.
64 Making the Tx ring too large decreases the effectiveness of channel
65 bonding and packet priority, and more than 128 requires modifying the
67 Large receive rings merely waste memory. */
68 #define TX_RING_SIZE 32
69 #define TX_QUEUE_LEN (TX_RING_SIZE - 1) /* Limit ring entries actually used. */
70 #define RX_RING_SIZE 64
72 #define TX_TOTAL_SIZE TX_RING_SIZE*sizeof(struct netdev_desc)
73 #define RX_TOTAL_SIZE RX_RING_SIZE*sizeof(struct netdev_desc)
75 /* Operational parameters that usually are not changed. */
76 /* Time in jiffies before concluding the transmitter is hung. */
77 #define TX_TIMEOUT (4*HZ)
78 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
80 /* Include files, designed to support most kernel versions 2.0.0 and later. */
81 #include <linux/module.h>
82 #include <linux/kernel.h>
83 #include <linux/string.h>
84 #include <linux/timer.h>
85 #include <linux/errno.h>
86 #include <linux/ioport.h>
87 #include <linux/slab.h>
88 #include <linux/interrupt.h>
89 #include <linux/pci.h>
90 #include <linux/netdevice.h>
91 #include <linux/etherdevice.h>
92 #include <linux/skbuff.h>
93 #include <linux/init.h>
94 #include <linux/bitops.h>
95 #include <asm/uaccess.h>
96 #include <asm/processor.h> /* Processor type for cache alignment. */
98 #include <linux/delay.h>
99 #include <linux/spinlock.h>
100 #ifndef _COMPAT_WITH_OLD_KERNEL
101 #include <linux/crc32.h>
102 #include <linux/ethtool.h>
103 #include <linux/mii.h>
111 /* These identify the driver base version and may not be removed. */
112 static char version[] =
113 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " Written by Donald Becker\n";
115 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
116 MODULE_DESCRIPTION("Sundance Alta Ethernet driver");
117 MODULE_LICENSE("GPL");
119 module_param(debug, int, 0);
120 module_param(rx_copybreak, int, 0);
121 module_param_array(media, charp, NULL, 0);
122 module_param(flowctrl, int, 0);
123 MODULE_PARM_DESC(debug, "Sundance Alta debug level (0-5)");
124 MODULE_PARM_DESC(rx_copybreak, "Sundance Alta copy breakpoint for copy-only-tiny-frames");
125 MODULE_PARM_DESC(flowctrl, "Sundance Alta flow control [0|1]");
130 I. Board Compatibility
132 This driver is designed for the Sundance Technologies "Alta" ST201 chip.
134 II. Board-specific settings
136 III. Driver operation
140 This driver uses two statically allocated fixed-size descriptor lists
141 formed into rings by a branch from the final descriptor to the beginning of
142 the list. The ring sizes are set at compile time by RX/TX_RING_SIZE.
143 Some chips explicitly use only 2^N sized rings, while others use a
144 'next descriptor' pointer that the driver forms into rings.
146 IIIb/c. Transmit/Receive Structure
148 This driver uses a zero-copy receive and transmit scheme.
149 The driver allocates full frame size skbuffs for the Rx ring buffers at
150 open() time and passes the skb->data field to the chip as receive data
151 buffers. When an incoming frame is less than RX_COPYBREAK bytes long,
152 a fresh skbuff is allocated and the frame is copied to the new skbuff.
153 When the incoming frame is larger, the skbuff is passed directly up the
154 protocol stack. Buffers consumed this way are replaced by newly allocated
155 skbuffs in a later phase of receives.
157 The RX_COPYBREAK value is chosen to trade-off the memory wasted by
158 using a full-sized skbuff for small frames vs. the copying costs of larger
159 frames. New boards are typically used in generously configured machines
160 and the underfilled buffers have negligible impact compared to the benefit of
161 a single allocation size, so the default value of zero results in never
162 copying packets. When copying is done, the cost is usually mitigated by using
163 a combined copy/checksum routine. Copying also preloads the cache, which is
164 most useful with small frames.
166 A subtle aspect of the operation is that the IP header at offset 14 in an
167 ethernet frame isn't longword aligned for further processing.
168 Unaligned buffers are permitted by the Sundance hardware, so
169 frames are received into the skbuff at an offset of "+2", 16-byte aligning
172 IIId. Synchronization
174 The driver runs as two independent, single-threaded flows of control. One
175 is the send-packet routine, which enforces single-threaded use by the
176 dev->tbusy flag. The other thread is the interrupt handler, which is single
177 threaded by the hardware and interrupt handling software.
179 The send packet thread has partial control over the Tx ring and 'dev->tbusy'
180 flag. It sets the tbusy flag whenever it's queuing a Tx packet. If the next
181 queue slot is empty, it clears the tbusy flag when finished otherwise it sets
182 the 'lp->tx_full' flag.
184 The interrupt handler has exclusive control over the Rx ring and records stats
185 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
186 empty by incrementing the dirty_tx mark. Iff the 'lp->tx_full' flag is set, it
187 clears both the tx_full and tbusy flags.
193 The Sundance ST201 datasheet, preliminary version.
194 The Kendin KS8723 datasheet, preliminary version.
195 The ICplus IP100 datasheet, preliminary version.
196 http://www.scyld.com/expert/100mbps.html
197 http://www.scyld.com/expert/NWay.html
203 /* Work-around for Kendin chip bugs. */
204 #ifndef CONFIG_SUNDANCE_MMIO
208 static const struct pci_device_id sundance_pci_tbl[] = {
209 { 0x1186, 0x1002, 0x1186, 0x1002, 0, 0, 0 },
210 { 0x1186, 0x1002, 0x1186, 0x1003, 0, 0, 1 },
211 { 0x1186, 0x1002, 0x1186, 0x1012, 0, 0, 2 },
212 { 0x1186, 0x1002, 0x1186, 0x1040, 0, 0, 3 },
213 { 0x1186, 0x1002, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
214 { 0x13F0, 0x0201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
215 { 0x13F0, 0x0200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 6 },
218 MODULE_DEVICE_TABLE(pci, sundance_pci_tbl);
227 static const struct pci_id_info pci_id_tbl[] __devinitdata = {
228 {"D-Link DFE-550TX FAST Ethernet Adapter"},
229 {"D-Link DFE-550FX 100Mbps Fiber-optics Adapter"},
230 {"D-Link DFE-580TX 4 port Server Adapter"},
231 {"D-Link DFE-530TXS FAST Ethernet Adapter"},
232 {"D-Link DL10050-based FAST Ethernet Adapter"},
233 {"Sundance Technology Alta"},
234 {"IC Plus Corporation IP100A FAST Ethernet Adapter"},
235 { } /* terminate list. */
238 /* This driver was written to use PCI memory space, however x86-oriented
239 hardware often uses I/O space accesses. */
241 /* Offsets to the device registers.
242 Unlike software-only systems, device drivers interact with complex hardware.
243 It's not useful to define symbolic names for every register bit in the
244 device. The name can only partially document the semantics and make
245 the driver longer and more difficult to read.
246 In general, only the important configuration values or bits changed
247 multiple times should be defined symbolically.
252 TxDMABurstThresh = 0x08,
253 TxDMAUrgentThresh = 0x09,
254 TxDMAPollPeriod = 0x0a,
259 RxDMABurstThresh = 0x14,
260 RxDMAUrgentThresh = 0x15,
261 RxDMAPollPeriod = 0x16,
280 MulticastFilter0 = 0x60,
281 MulticastFilter1 = 0x64,
288 StatsCarrierError = 0x74,
289 StatsLateColl = 0x75,
290 StatsMultiColl = 0x76,
294 StatsTxXSDefer = 0x7a,
300 /* Aliased and bogus values! */
303 enum ASICCtrl_HiWord_bit {
304 GlobalReset = 0x0001,
309 NetworkReset = 0x0020,
314 /* Bits in the interrupt status/mask registers. */
315 enum intr_status_bits {
316 IntrSummary=0x0001, IntrPCIErr=0x0002, IntrMACCtrl=0x0008,
317 IntrTxDone=0x0004, IntrRxDone=0x0010, IntrRxStart=0x0020,
319 StatsMax=0x0080, LinkChange=0x0100,
320 IntrTxDMADone=0x0200, IntrRxDMADone=0x0400,
323 /* Bits in the RxMode register. */
325 AcceptAllIPMulti=0x20, AcceptMultiHash=0x10, AcceptAll=0x08,
326 AcceptBroadcast=0x04, AcceptMulticast=0x02, AcceptMyPhys=0x01,
328 /* Bits in MACCtrl. */
329 enum mac_ctrl0_bits {
330 EnbFullDuplex=0x20, EnbRcvLargeFrame=0x40,
331 EnbFlowCtrl=0x100, EnbPassRxCRC=0x200,
333 enum mac_ctrl1_bits {
334 StatsEnable=0x0020, StatsDisable=0x0040, StatsEnabled=0x0080,
335 TxEnable=0x0100, TxDisable=0x0200, TxEnabled=0x0400,
336 RxEnable=0x0800, RxDisable=0x1000, RxEnabled=0x2000,
339 /* The Rx and Tx buffer descriptors. */
340 /* Note that using only 32 bit fields simplifies conversion to big-endian
345 struct desc_frag { __le32 addr, length; } frag[1];
348 /* Bits in netdev_desc.status */
349 enum desc_status_bits {
351 DescEndPacket=0x4000,
355 DescIntrOnDMADone=0x80000000,
356 DisableAlign = 0x00000001,
359 #define PRIV_ALIGN 15 /* Required alignment mask */
360 /* Use __attribute__((aligned (L1_CACHE_BYTES))) to maintain alignment
361 within the structure. */
363 struct netdev_private {
364 /* Descriptor rings first for alignment. */
365 struct netdev_desc *rx_ring;
366 struct netdev_desc *tx_ring;
367 struct sk_buff* rx_skbuff[RX_RING_SIZE];
368 struct sk_buff* tx_skbuff[TX_RING_SIZE];
369 dma_addr_t tx_ring_dma;
370 dma_addr_t rx_ring_dma;
371 struct net_device_stats stats;
372 struct timer_list timer; /* Media monitoring timer. */
373 /* Frequently used values: keep some adjacent for cache effect. */
375 spinlock_t rx_lock; /* Group with Tx control cache line. */
378 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
379 unsigned int rx_buf_sz; /* Based on MTU+slack. */
380 struct netdev_desc *last_tx; /* Last Tx descriptor used. */
381 unsigned int cur_tx, dirty_tx;
382 /* These values are keep track of the transceiver/media in use. */
383 unsigned int flowctrl:1;
384 unsigned int default_port:4; /* Last dev->if_port value. */
385 unsigned int an_enable:1;
387 struct tasklet_struct rx_tasklet;
388 struct tasklet_struct tx_tasklet;
391 /* Multicast and receive mode. */
392 spinlock_t mcastlock; /* SMP lock multicast updates. */
394 /* MII transceiver section. */
395 struct mii_if_info mii_if;
396 int mii_preamble_required;
397 unsigned char phys[MII_CNT]; /* MII device addresses, only first one used. */
398 struct pci_dev *pci_dev;
402 /* The station address location in the EEPROM. */
403 #define EEPROM_SA_OFFSET 0x10
404 #define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \
405 IntrDrvRqst | IntrTxDone | StatsMax | \
408 static int change_mtu(struct net_device *dev, int new_mtu);
409 static int eeprom_read(void __iomem *ioaddr, int location);
410 static int mdio_read(struct net_device *dev, int phy_id, int location);
411 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
412 static int mdio_wait_link(struct net_device *dev, int wait);
413 static int netdev_open(struct net_device *dev);
414 static void check_duplex(struct net_device *dev);
415 static void netdev_timer(unsigned long data);
416 static void tx_timeout(struct net_device *dev);
417 static void init_ring(struct net_device *dev);
418 static int start_tx(struct sk_buff *skb, struct net_device *dev);
419 static int reset_tx (struct net_device *dev);
420 static irqreturn_t intr_handler(int irq, void *dev_instance);
421 static void rx_poll(unsigned long data);
422 static void tx_poll(unsigned long data);
423 static void refill_rx (struct net_device *dev);
424 static void netdev_error(struct net_device *dev, int intr_status);
425 static void netdev_error(struct net_device *dev, int intr_status);
426 static void set_rx_mode(struct net_device *dev);
427 static int __set_mac_addr(struct net_device *dev);
428 static struct net_device_stats *get_stats(struct net_device *dev);
429 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
430 static int netdev_close(struct net_device *dev);
431 static const struct ethtool_ops ethtool_ops;
433 static void sundance_reset(struct net_device *dev, unsigned long reset_cmd)
435 struct netdev_private *np = netdev_priv(dev);
436 void __iomem *ioaddr = np->base + ASICCtrl;
439 /* ST201 documentation states ASICCtrl is a 32bit register */
440 iowrite32 (reset_cmd | ioread32 (ioaddr), ioaddr);
441 /* ST201 documentation states reset can take up to 1 ms */
443 while (ioread32 (ioaddr) & (ResetBusy << 16)) {
444 if (--countdown == 0) {
445 printk(KERN_WARNING "%s : reset not completed !!\n", dev->name);
452 static int __devinit sundance_probe1 (struct pci_dev *pdev,
453 const struct pci_device_id *ent)
455 struct net_device *dev;
456 struct netdev_private *np;
458 int chip_idx = ent->driver_data;
461 void __iomem *ioaddr;
470 int phy, phy_end, phy_idx = 0;
472 /* when built into the kernel, we only print version if device is found */
474 static int printed_version;
475 if (!printed_version++)
479 if (pci_enable_device(pdev))
481 pci_set_master(pdev);
485 dev = alloc_etherdev(sizeof(*np));
488 SET_NETDEV_DEV(dev, &pdev->dev);
490 if (pci_request_regions(pdev, DRV_NAME))
493 ioaddr = pci_iomap(pdev, bar, netdev_io_size);
497 for (i = 0; i < 3; i++)
498 ((__le16 *)dev->dev_addr)[i] =
499 cpu_to_le16(eeprom_read(ioaddr, i + EEPROM_SA_OFFSET));
500 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
502 dev->base_addr = (unsigned long)ioaddr;
505 np = netdev_priv(dev);
508 np->chip_id = chip_idx;
509 np->msg_enable = (1 << debug) - 1;
510 spin_lock_init(&np->lock);
511 tasklet_init(&np->rx_tasklet, rx_poll, (unsigned long)dev);
512 tasklet_init(&np->tx_tasklet, tx_poll, (unsigned long)dev);
514 ring_space = pci_alloc_consistent(pdev, TX_TOTAL_SIZE, &ring_dma);
516 goto err_out_cleardev;
517 np->tx_ring = (struct netdev_desc *)ring_space;
518 np->tx_ring_dma = ring_dma;
520 ring_space = pci_alloc_consistent(pdev, RX_TOTAL_SIZE, &ring_dma);
522 goto err_out_unmap_tx;
523 np->rx_ring = (struct netdev_desc *)ring_space;
524 np->rx_ring_dma = ring_dma;
526 np->mii_if.dev = dev;
527 np->mii_if.mdio_read = mdio_read;
528 np->mii_if.mdio_write = mdio_write;
529 np->mii_if.phy_id_mask = 0x1f;
530 np->mii_if.reg_num_mask = 0x1f;
532 /* The chip-specific entries in the device structure. */
533 dev->open = &netdev_open;
534 dev->hard_start_xmit = &start_tx;
535 dev->stop = &netdev_close;
536 dev->get_stats = &get_stats;
537 dev->set_multicast_list = &set_rx_mode;
538 dev->do_ioctl = &netdev_ioctl;
539 SET_ETHTOOL_OPS(dev, ðtool_ops);
540 dev->tx_timeout = &tx_timeout;
541 dev->watchdog_timeo = TX_TIMEOUT;
542 dev->change_mtu = &change_mtu;
543 pci_set_drvdata(pdev, dev);
545 i = register_netdev(dev);
547 goto err_out_unmap_rx;
549 printk(KERN_INFO "%s: %s at %p, %pM, IRQ %d.\n",
550 dev->name, pci_id_tbl[chip_idx].name, ioaddr,
553 np->phys[0] = 1; /* Default setting */
554 np->mii_preamble_required++;
557 * It seems some phys doesn't deal well with address 0 being accessed
560 if (sundance_pci_tbl[np->chip_id].device == 0x0200) {
565 phy_end = 32; /* wraps to zero, due to 'phy & 0x1f' */
567 for (; phy <= phy_end && phy_idx < MII_CNT; phy++) {
568 int phyx = phy & 0x1f;
569 int mii_status = mdio_read(dev, phyx, MII_BMSR);
570 if (mii_status != 0xffff && mii_status != 0x0000) {
571 np->phys[phy_idx++] = phyx;
572 np->mii_if.advertising = mdio_read(dev, phyx, MII_ADVERTISE);
573 if ((mii_status & 0x0040) == 0)
574 np->mii_preamble_required++;
575 printk(KERN_INFO "%s: MII PHY found at address %d, status "
576 "0x%4.4x advertising %4.4x.\n",
577 dev->name, phyx, mii_status, np->mii_if.advertising);
580 np->mii_preamble_required--;
583 printk(KERN_INFO "%s: No MII transceiver found, aborting. ASIC status %x\n",
584 dev->name, ioread32(ioaddr + ASICCtrl));
585 goto err_out_unregister;
588 np->mii_if.phy_id = np->phys[0];
590 /* Parse override configuration */
592 if (card_idx < MAX_UNITS) {
593 if (media[card_idx] != NULL) {
595 if (strcmp (media[card_idx], "100mbps_fd") == 0 ||
596 strcmp (media[card_idx], "4") == 0) {
598 np->mii_if.full_duplex = 1;
599 } else if (strcmp (media[card_idx], "100mbps_hd") == 0
600 || strcmp (media[card_idx], "3") == 0) {
602 np->mii_if.full_duplex = 0;
603 } else if (strcmp (media[card_idx], "10mbps_fd") == 0 ||
604 strcmp (media[card_idx], "2") == 0) {
606 np->mii_if.full_duplex = 1;
607 } else if (strcmp (media[card_idx], "10mbps_hd") == 0 ||
608 strcmp (media[card_idx], "1") == 0) {
610 np->mii_if.full_duplex = 0;
620 if (ioread32 (ioaddr + ASICCtrl) & 0x80) {
621 /* Default 100Mbps Full */
624 np->mii_if.full_duplex = 1;
629 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_RESET);
631 /* If flow control enabled, we need to advertise it.*/
633 mdio_write (dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising | 0x0400);
634 mdio_write (dev, np->phys[0], MII_BMCR, BMCR_ANENABLE|BMCR_ANRESTART);
635 /* Force media type */
636 if (!np->an_enable) {
638 mii_ctl |= (np->speed == 100) ? BMCR_SPEED100 : 0;
639 mii_ctl |= (np->mii_if.full_duplex) ? BMCR_FULLDPLX : 0;
640 mdio_write (dev, np->phys[0], MII_BMCR, mii_ctl);
641 printk (KERN_INFO "Override speed=%d, %s duplex\n",
642 np->speed, np->mii_if.full_duplex ? "Full" : "Half");
646 /* Perhaps move the reset here? */
647 /* Reset the chip to erase previous misconfiguration. */
648 if (netif_msg_hw(np))
649 printk("ASIC Control is %x.\n", ioread32(ioaddr + ASICCtrl));
650 sundance_reset(dev, 0x00ff << 16);
651 if (netif_msg_hw(np))
652 printk("ASIC Control is now %x.\n", ioread32(ioaddr + ASICCtrl));
658 unregister_netdev(dev);
660 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring, np->rx_ring_dma);
662 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring, np->tx_ring_dma);
664 pci_set_drvdata(pdev, NULL);
665 pci_iounmap(pdev, ioaddr);
667 pci_release_regions(pdev);
673 static int change_mtu(struct net_device *dev, int new_mtu)
675 if ((new_mtu < 68) || (new_mtu > 8191)) /* Set by RxDMAFrameLen */
677 if (netif_running(dev))
683 #define eeprom_delay(ee_addr) ioread32(ee_addr)
684 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */
685 static int __devinit eeprom_read(void __iomem *ioaddr, int location)
687 int boguscnt = 10000; /* Typical 1900 ticks. */
688 iowrite16(0x0200 | (location & 0xff), ioaddr + EECtrl);
690 eeprom_delay(ioaddr + EECtrl);
691 if (! (ioread16(ioaddr + EECtrl) & 0x8000)) {
692 return ioread16(ioaddr + EEData);
694 } while (--boguscnt > 0);
698 /* MII transceiver control section.
699 Read and write the MII registers using software-generated serial
700 MDIO protocol. See the MII specifications or DP83840A data sheet
703 The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
704 met by back-to-back 33Mhz PCI cycles. */
705 #define mdio_delay() ioread8(mdio_addr)
708 MDIO_ShiftClk=0x0001, MDIO_Data=0x0002, MDIO_EnbOutput=0x0004,
710 #define MDIO_EnbIn (0)
711 #define MDIO_WRITE0 (MDIO_EnbOutput)
712 #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
714 /* Generate the preamble required for initial synchronization and
715 a few older transceivers. */
716 static void mdio_sync(void __iomem *mdio_addr)
720 /* Establish sync by sending at least 32 logic ones. */
721 while (--bits >= 0) {
722 iowrite8(MDIO_WRITE1, mdio_addr);
724 iowrite8(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
729 static int mdio_read(struct net_device *dev, int phy_id, int location)
731 struct netdev_private *np = netdev_priv(dev);
732 void __iomem *mdio_addr = np->base + MIICtrl;
733 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
736 if (np->mii_preamble_required)
737 mdio_sync(mdio_addr);
739 /* Shift the read command bits out. */
740 for (i = 15; i >= 0; i--) {
741 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
743 iowrite8(dataval, mdio_addr);
745 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
748 /* Read the two transition, 16 data, and wire-idle bits. */
749 for (i = 19; i > 0; i--) {
750 iowrite8(MDIO_EnbIn, mdio_addr);
752 retval = (retval << 1) | ((ioread8(mdio_addr) & MDIO_Data) ? 1 : 0);
753 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
756 return (retval>>1) & 0xffff;
759 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
761 struct netdev_private *np = netdev_priv(dev);
762 void __iomem *mdio_addr = np->base + MIICtrl;
763 int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
766 if (np->mii_preamble_required)
767 mdio_sync(mdio_addr);
769 /* Shift the command bits out. */
770 for (i = 31; i >= 0; i--) {
771 int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
773 iowrite8(dataval, mdio_addr);
775 iowrite8(dataval | MDIO_ShiftClk, mdio_addr);
778 /* Clear out extra bits. */
779 for (i = 2; i > 0; i--) {
780 iowrite8(MDIO_EnbIn, mdio_addr);
782 iowrite8(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
788 static int mdio_wait_link(struct net_device *dev, int wait)
792 struct netdev_private *np;
794 np = netdev_priv(dev);
795 phy_id = np->phys[0];
798 bmsr = mdio_read(dev, phy_id, MII_BMSR);
802 } while (--wait > 0);
806 static int netdev_open(struct net_device *dev)
808 struct netdev_private *np = netdev_priv(dev);
809 void __iomem *ioaddr = np->base;
813 /* Do we need to reset the chip??? */
815 i = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
819 if (netif_msg_ifup(np))
820 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
821 dev->name, dev->irq);
824 iowrite32(np->rx_ring_dma, ioaddr + RxListPtr);
825 /* The Tx list pointer is written as packets are queued. */
827 /* Initialize other registers. */
829 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
830 iowrite16(dev->mtu + 18, ioaddr + MaxFrameSize);
832 iowrite16(dev->mtu + 14, ioaddr + MaxFrameSize);
835 iowrite32(ioread32(ioaddr + ASICCtrl) | 0x0C, ioaddr + ASICCtrl);
837 /* Configure the PCI bus bursts and FIFO thresholds. */
839 if (dev->if_port == 0)
840 dev->if_port = np->default_port;
842 spin_lock_init(&np->mcastlock);
845 iowrite16(0, ioaddr + IntrEnable);
846 iowrite16(0, ioaddr + DownCounter);
847 /* Set the chip to poll every N*320nsec. */
848 iowrite8(100, ioaddr + RxDMAPollPeriod);
849 iowrite8(127, ioaddr + TxDMAPollPeriod);
850 /* Fix DFE-580TX packet drop issue */
851 if (np->pci_dev->revision >= 0x14)
852 iowrite8(0x01, ioaddr + DebugCtrl1);
853 netif_start_queue(dev);
855 spin_lock_irqsave(&np->lock, flags);
857 spin_unlock_irqrestore(&np->lock, flags);
859 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
861 if (netif_msg_ifup(np))
862 printk(KERN_DEBUG "%s: Done netdev_open(), status: Rx %x Tx %x "
863 "MAC Control %x, %4.4x %4.4x.\n",
864 dev->name, ioread32(ioaddr + RxStatus), ioread8(ioaddr + TxStatus),
865 ioread32(ioaddr + MACCtrl0),
866 ioread16(ioaddr + MACCtrl1), ioread16(ioaddr + MACCtrl0));
868 /* Set the timer to check for link beat. */
869 init_timer(&np->timer);
870 np->timer.expires = jiffies + 3*HZ;
871 np->timer.data = (unsigned long)dev;
872 np->timer.function = &netdev_timer; /* timer handler */
873 add_timer(&np->timer);
875 /* Enable interrupts by setting the interrupt mask. */
876 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
881 static void check_duplex(struct net_device *dev)
883 struct netdev_private *np = netdev_priv(dev);
884 void __iomem *ioaddr = np->base;
885 int mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
886 int negotiated = mii_lpa & np->mii_if.advertising;
890 if (!np->an_enable || mii_lpa == 0xffff) {
891 if (np->mii_if.full_duplex)
892 iowrite16 (ioread16 (ioaddr + MACCtrl0) | EnbFullDuplex,
897 /* Autonegotiation */
898 duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
899 if (np->mii_if.full_duplex != duplex) {
900 np->mii_if.full_duplex = duplex;
901 if (netif_msg_link(np))
902 printk(KERN_INFO "%s: Setting %s-duplex based on MII #%d "
903 "negotiated capability %4.4x.\n", dev->name,
904 duplex ? "full" : "half", np->phys[0], negotiated);
905 iowrite16(ioread16(ioaddr + MACCtrl0) | duplex ? 0x20 : 0, ioaddr + MACCtrl0);
909 static void netdev_timer(unsigned long data)
911 struct net_device *dev = (struct net_device *)data;
912 struct netdev_private *np = netdev_priv(dev);
913 void __iomem *ioaddr = np->base;
914 int next_tick = 10*HZ;
916 if (netif_msg_timer(np)) {
917 printk(KERN_DEBUG "%s: Media selection timer tick, intr status %4.4x, "
919 dev->name, ioread16(ioaddr + IntrEnable),
920 ioread8(ioaddr + TxStatus), ioread32(ioaddr + RxStatus));
923 np->timer.expires = jiffies + next_tick;
924 add_timer(&np->timer);
927 static void tx_timeout(struct net_device *dev)
929 struct netdev_private *np = netdev_priv(dev);
930 void __iomem *ioaddr = np->base;
933 netif_stop_queue(dev);
934 tasklet_disable(&np->tx_tasklet);
935 iowrite16(0, ioaddr + IntrEnable);
936 printk(KERN_WARNING "%s: Transmit timed out, TxStatus %2.2x "
938 " resetting...\n", dev->name, ioread8(ioaddr + TxStatus),
939 ioread8(ioaddr + TxFrameId));
943 for (i=0; i<TX_RING_SIZE; i++) {
944 printk(KERN_DEBUG "%02x %08llx %08x %08x(%02x) %08x %08x\n", i,
945 (unsigned long long)(np->tx_ring_dma + i*sizeof(*np->tx_ring)),
946 le32_to_cpu(np->tx_ring[i].next_desc),
947 le32_to_cpu(np->tx_ring[i].status),
948 (le32_to_cpu(np->tx_ring[i].status) >> 2) & 0xff,
949 le32_to_cpu(np->tx_ring[i].frag[0].addr),
950 le32_to_cpu(np->tx_ring[i].frag[0].length));
952 printk(KERN_DEBUG "TxListPtr=%08x netif_queue_stopped=%d\n",
953 ioread32(np->base + TxListPtr),
954 netif_queue_stopped(dev));
955 printk(KERN_DEBUG "cur_tx=%d(%02x) dirty_tx=%d(%02x)\n",
956 np->cur_tx, np->cur_tx % TX_RING_SIZE,
957 np->dirty_tx, np->dirty_tx % TX_RING_SIZE);
958 printk(KERN_DEBUG "cur_rx=%d dirty_rx=%d\n", np->cur_rx, np->dirty_rx);
959 printk(KERN_DEBUG "cur_task=%d\n", np->cur_task);
961 spin_lock_irqsave(&np->lock, flag);
963 /* Stop and restart the chip's Tx processes . */
965 spin_unlock_irqrestore(&np->lock, flag);
969 dev->trans_start = jiffies;
970 np->stats.tx_errors++;
971 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
972 netif_wake_queue(dev);
974 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
975 tasklet_enable(&np->tx_tasklet);
979 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
980 static void init_ring(struct net_device *dev)
982 struct netdev_private *np = netdev_priv(dev);
985 np->cur_rx = np->cur_tx = 0;
986 np->dirty_rx = np->dirty_tx = 0;
989 np->rx_buf_sz = (dev->mtu <= 1520 ? PKT_BUF_SZ : dev->mtu + 16);
991 /* Initialize all Rx descriptors. */
992 for (i = 0; i < RX_RING_SIZE; i++) {
993 np->rx_ring[i].next_desc = cpu_to_le32(np->rx_ring_dma +
994 ((i+1)%RX_RING_SIZE)*sizeof(*np->rx_ring));
995 np->rx_ring[i].status = 0;
996 np->rx_ring[i].frag[0].length = 0;
997 np->rx_skbuff[i] = NULL;
1000 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1001 for (i = 0; i < RX_RING_SIZE; i++) {
1002 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1003 np->rx_skbuff[i] = skb;
1006 skb->dev = dev; /* Mark as being used by this device. */
1007 skb_reserve(skb, 2); /* 16 byte align the IP header. */
1008 np->rx_ring[i].frag[0].addr = cpu_to_le32(
1009 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz,
1010 PCI_DMA_FROMDEVICE));
1011 np->rx_ring[i].frag[0].length = cpu_to_le32(np->rx_buf_sz | LastFrag);
1013 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1015 for (i = 0; i < TX_RING_SIZE; i++) {
1016 np->tx_skbuff[i] = NULL;
1017 np->tx_ring[i].status = 0;
1022 static void tx_poll (unsigned long data)
1024 struct net_device *dev = (struct net_device *)data;
1025 struct netdev_private *np = netdev_priv(dev);
1026 unsigned head = np->cur_task % TX_RING_SIZE;
1027 struct netdev_desc *txdesc =
1028 &np->tx_ring[(np->cur_tx - 1) % TX_RING_SIZE];
1030 /* Chain the next pointer */
1031 for (; np->cur_tx - np->cur_task > 0; np->cur_task++) {
1032 int entry = np->cur_task % TX_RING_SIZE;
1033 txdesc = &np->tx_ring[entry];
1035 np->last_tx->next_desc = cpu_to_le32(np->tx_ring_dma +
1036 entry*sizeof(struct netdev_desc));
1038 np->last_tx = txdesc;
1040 /* Indicate the latest descriptor of tx ring */
1041 txdesc->status |= cpu_to_le32(DescIntrOnTx);
1043 if (ioread32 (np->base + TxListPtr) == 0)
1044 iowrite32 (np->tx_ring_dma + head * sizeof(struct netdev_desc),
1045 np->base + TxListPtr);
1050 start_tx (struct sk_buff *skb, struct net_device *dev)
1052 struct netdev_private *np = netdev_priv(dev);
1053 struct netdev_desc *txdesc;
1056 /* Calculate the next Tx descriptor entry. */
1057 entry = np->cur_tx % TX_RING_SIZE;
1058 np->tx_skbuff[entry] = skb;
1059 txdesc = &np->tx_ring[entry];
1061 txdesc->next_desc = 0;
1062 txdesc->status = cpu_to_le32 ((entry << 2) | DisableAlign);
1063 txdesc->frag[0].addr = cpu_to_le32 (pci_map_single (np->pci_dev, skb->data,
1066 txdesc->frag[0].length = cpu_to_le32 (skb->len | LastFrag);
1068 /* Increment cur_tx before tasklet_schedule() */
1071 /* Schedule a tx_poll() task */
1072 tasklet_schedule(&np->tx_tasklet);
1074 /* On some architectures: explicitly flush cache lines here. */
1075 if (np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 1
1076 && !netif_queue_stopped(dev)) {
1079 netif_stop_queue (dev);
1081 dev->trans_start = jiffies;
1082 if (netif_msg_tx_queued(np)) {
1084 "%s: Transmit frame #%d queued in slot %d.\n",
1085 dev->name, np->cur_tx, entry);
1090 /* Reset hardware tx and free all of tx buffers */
1092 reset_tx (struct net_device *dev)
1094 struct netdev_private *np = netdev_priv(dev);
1095 void __iomem *ioaddr = np->base;
1096 struct sk_buff *skb;
1098 int irq = in_interrupt();
1100 /* Reset tx logic, TxListPtr will be cleaned */
1101 iowrite16 (TxDisable, ioaddr + MACCtrl1);
1102 sundance_reset(dev, (NetworkReset|FIFOReset|DMAReset|TxReset) << 16);
1104 /* free all tx skbuff */
1105 for (i = 0; i < TX_RING_SIZE; i++) {
1106 np->tx_ring[i].next_desc = 0;
1108 skb = np->tx_skbuff[i];
1110 pci_unmap_single(np->pci_dev,
1111 le32_to_cpu(np->tx_ring[i].frag[0].addr),
1112 skb->len, PCI_DMA_TODEVICE);
1114 dev_kfree_skb_irq (skb);
1116 dev_kfree_skb (skb);
1117 np->tx_skbuff[i] = NULL;
1118 np->stats.tx_dropped++;
1121 np->cur_tx = np->dirty_tx = 0;
1125 iowrite8(127, ioaddr + TxDMAPollPeriod);
1127 iowrite16 (StatsEnable | RxEnable | TxEnable, ioaddr + MACCtrl1);
1131 /* The interrupt handler cleans up after the Tx thread,
1132 and schedule a Rx thread work */
1133 static irqreturn_t intr_handler(int irq, void *dev_instance)
1135 struct net_device *dev = (struct net_device *)dev_instance;
1136 struct netdev_private *np = netdev_priv(dev);
1137 void __iomem *ioaddr = np->base;
1146 int intr_status = ioread16(ioaddr + IntrStatus);
1147 iowrite16(intr_status, ioaddr + IntrStatus);
1149 if (netif_msg_intr(np))
1150 printk(KERN_DEBUG "%s: Interrupt, status %4.4x.\n",
1151 dev->name, intr_status);
1153 if (!(intr_status & DEFAULT_INTR))
1158 if (intr_status & (IntrRxDMADone)) {
1159 iowrite16(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
1160 ioaddr + IntrEnable);
1162 np->budget = RX_BUDGET;
1163 tasklet_schedule(&np->rx_tasklet);
1165 if (intr_status & (IntrTxDone | IntrDrvRqst)) {
1166 tx_status = ioread16 (ioaddr + TxStatus);
1167 for (tx_cnt=32; tx_status & 0x80; --tx_cnt) {
1168 if (netif_msg_tx_done(np))
1170 ("%s: Transmit status is %2.2x.\n",
1171 dev->name, tx_status);
1172 if (tx_status & 0x1e) {
1173 if (netif_msg_tx_err(np))
1174 printk("%s: Transmit error status %4.4x.\n",
1175 dev->name, tx_status);
1176 np->stats.tx_errors++;
1177 if (tx_status & 0x10)
1178 np->stats.tx_fifo_errors++;
1179 if (tx_status & 0x08)
1180 np->stats.collisions++;
1181 if (tx_status & 0x04)
1182 np->stats.tx_fifo_errors++;
1183 if (tx_status & 0x02)
1184 np->stats.tx_window_errors++;
1187 ** This reset has been verified on
1188 ** DFE-580TX boards ! phdm@macqel.be.
1190 if (tx_status & 0x10) { /* TxUnderrun */
1191 /* Restart Tx FIFO and transmitter */
1192 sundance_reset(dev, (NetworkReset|FIFOReset|TxReset) << 16);
1193 /* No need to reset the Tx pointer here */
1195 /* Restart the Tx. Need to make sure tx enabled */
1198 iowrite16(ioread16(ioaddr + MACCtrl1) | TxEnable, ioaddr + MACCtrl1);
1199 if (ioread16(ioaddr + MACCtrl1) & TxEnabled)
1204 /* Yup, this is a documentation bug. It cost me *hours*. */
1205 iowrite16 (0, ioaddr + TxStatus);
1207 iowrite32(5000, ioaddr + DownCounter);
1210 tx_status = ioread16 (ioaddr + TxStatus);
1212 hw_frame_id = (tx_status >> 8) & 0xff;
1214 hw_frame_id = ioread8(ioaddr + TxFrameId);
1217 if (np->pci_dev->revision >= 0x14) {
1218 spin_lock(&np->lock);
1219 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1220 int entry = np->dirty_tx % TX_RING_SIZE;
1221 struct sk_buff *skb;
1223 sw_frame_id = (le32_to_cpu(
1224 np->tx_ring[entry].status) >> 2) & 0xff;
1225 if (sw_frame_id == hw_frame_id &&
1226 !(le32_to_cpu(np->tx_ring[entry].status)
1229 if (sw_frame_id == (hw_frame_id + 1) %
1232 skb = np->tx_skbuff[entry];
1233 /* Free the original skb. */
1234 pci_unmap_single(np->pci_dev,
1235 le32_to_cpu(np->tx_ring[entry].frag[0].addr),
1236 skb->len, PCI_DMA_TODEVICE);
1237 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1238 np->tx_skbuff[entry] = NULL;
1239 np->tx_ring[entry].frag[0].addr = 0;
1240 np->tx_ring[entry].frag[0].length = 0;
1242 spin_unlock(&np->lock);
1244 spin_lock(&np->lock);
1245 for (; np->cur_tx - np->dirty_tx > 0; np->dirty_tx++) {
1246 int entry = np->dirty_tx % TX_RING_SIZE;
1247 struct sk_buff *skb;
1248 if (!(le32_to_cpu(np->tx_ring[entry].status)
1251 skb = np->tx_skbuff[entry];
1252 /* Free the original skb. */
1253 pci_unmap_single(np->pci_dev,
1254 le32_to_cpu(np->tx_ring[entry].frag[0].addr),
1255 skb->len, PCI_DMA_TODEVICE);
1256 dev_kfree_skb_irq (np->tx_skbuff[entry]);
1257 np->tx_skbuff[entry] = NULL;
1258 np->tx_ring[entry].frag[0].addr = 0;
1259 np->tx_ring[entry].frag[0].length = 0;
1261 spin_unlock(&np->lock);
1264 if (netif_queue_stopped(dev) &&
1265 np->cur_tx - np->dirty_tx < TX_QUEUE_LEN - 4) {
1266 /* The ring is no longer full, clear busy flag. */
1267 netif_wake_queue (dev);
1269 /* Abnormal error summary/uncommon events handlers. */
1270 if (intr_status & (IntrPCIErr | LinkChange | StatsMax))
1271 netdev_error(dev, intr_status);
1273 if (netif_msg_intr(np))
1274 printk(KERN_DEBUG "%s: exiting interrupt, status=%#4.4x.\n",
1275 dev->name, ioread16(ioaddr + IntrStatus));
1276 return IRQ_RETVAL(handled);
1279 static void rx_poll(unsigned long data)
1281 struct net_device *dev = (struct net_device *)data;
1282 struct netdev_private *np = netdev_priv(dev);
1283 int entry = np->cur_rx % RX_RING_SIZE;
1284 int boguscnt = np->budget;
1285 void __iomem *ioaddr = np->base;
1288 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1290 struct netdev_desc *desc = &(np->rx_ring[entry]);
1291 u32 frame_status = le32_to_cpu(desc->status);
1294 if (--boguscnt < 0) {
1297 if (!(frame_status & DescOwn))
1299 pkt_len = frame_status & 0x1fff; /* Chip omits the CRC. */
1300 if (netif_msg_rx_status(np))
1301 printk(KERN_DEBUG " netdev_rx() status was %8.8x.\n",
1303 if (frame_status & 0x001f4000) {
1304 /* There was a error. */
1305 if (netif_msg_rx_err(np))
1306 printk(KERN_DEBUG " netdev_rx() Rx error was %8.8x.\n",
1308 np->stats.rx_errors++;
1309 if (frame_status & 0x00100000) np->stats.rx_length_errors++;
1310 if (frame_status & 0x00010000) np->stats.rx_fifo_errors++;
1311 if (frame_status & 0x00060000) np->stats.rx_frame_errors++;
1312 if (frame_status & 0x00080000) np->stats.rx_crc_errors++;
1313 if (frame_status & 0x00100000) {
1314 printk(KERN_WARNING "%s: Oversized Ethernet frame,"
1316 dev->name, frame_status);
1319 struct sk_buff *skb;
1320 #ifndef final_version
1321 if (netif_msg_rx_status(np))
1322 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d"
1323 ", bogus_cnt %d.\n",
1326 /* Check if the packet is long enough to accept without copying
1327 to a minimally-sized skbuff. */
1328 if (pkt_len < rx_copybreak
1329 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1330 skb_reserve(skb, 2); /* 16 byte align the IP header */
1331 pci_dma_sync_single_for_cpu(np->pci_dev,
1332 le32_to_cpu(desc->frag[0].addr),
1334 PCI_DMA_FROMDEVICE);
1336 skb_copy_to_linear_data(skb, np->rx_skbuff[entry]->data, pkt_len);
1337 pci_dma_sync_single_for_device(np->pci_dev,
1338 le32_to_cpu(desc->frag[0].addr),
1340 PCI_DMA_FROMDEVICE);
1341 skb_put(skb, pkt_len);
1343 pci_unmap_single(np->pci_dev,
1344 le32_to_cpu(desc->frag[0].addr),
1346 PCI_DMA_FROMDEVICE);
1347 skb_put(skb = np->rx_skbuff[entry], pkt_len);
1348 np->rx_skbuff[entry] = NULL;
1350 skb->protocol = eth_type_trans(skb, dev);
1351 /* Note: checksum -> skb->ip_summed = CHECKSUM_UNNECESSARY; */
1353 dev->last_rx = jiffies;
1355 entry = (entry + 1) % RX_RING_SIZE;
1360 np->budget -= received;
1361 iowrite16(DEFAULT_INTR, ioaddr + IntrEnable);
1369 np->budget -= received;
1370 if (np->budget <= 0)
1371 np->budget = RX_BUDGET;
1372 tasklet_schedule(&np->rx_tasklet);
1376 static void refill_rx (struct net_device *dev)
1378 struct netdev_private *np = netdev_priv(dev);
1382 /* Refill the Rx ring buffers. */
1383 for (;(np->cur_rx - np->dirty_rx + RX_RING_SIZE) % RX_RING_SIZE > 0;
1384 np->dirty_rx = (np->dirty_rx + 1) % RX_RING_SIZE) {
1385 struct sk_buff *skb;
1386 entry = np->dirty_rx % RX_RING_SIZE;
1387 if (np->rx_skbuff[entry] == NULL) {
1388 skb = dev_alloc_skb(np->rx_buf_sz);
1389 np->rx_skbuff[entry] = skb;
1391 break; /* Better luck next round. */
1392 skb->dev = dev; /* Mark as being used by this device. */
1393 skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
1394 np->rx_ring[entry].frag[0].addr = cpu_to_le32(
1395 pci_map_single(np->pci_dev, skb->data,
1396 np->rx_buf_sz, PCI_DMA_FROMDEVICE));
1398 /* Perhaps we need not reset this field. */
1399 np->rx_ring[entry].frag[0].length =
1400 cpu_to_le32(np->rx_buf_sz | LastFrag);
1401 np->rx_ring[entry].status = 0;
1406 static void netdev_error(struct net_device *dev, int intr_status)
1408 struct netdev_private *np = netdev_priv(dev);
1409 void __iomem *ioaddr = np->base;
1410 u16 mii_ctl, mii_advertise, mii_lpa;
1413 if (intr_status & LinkChange) {
1414 if (mdio_wait_link(dev, 10) == 0) {
1415 printk(KERN_INFO "%s: Link up\n", dev->name);
1416 if (np->an_enable) {
1417 mii_advertise = mdio_read(dev, np->phys[0],
1419 mii_lpa = mdio_read(dev, np->phys[0], MII_LPA);
1420 mii_advertise &= mii_lpa;
1421 printk(KERN_INFO "%s: Link changed: ",
1423 if (mii_advertise & ADVERTISE_100FULL) {
1425 printk("100Mbps, full duplex\n");
1426 } else if (mii_advertise & ADVERTISE_100HALF) {
1428 printk("100Mbps, half duplex\n");
1429 } else if (mii_advertise & ADVERTISE_10FULL) {
1431 printk("10Mbps, full duplex\n");
1432 } else if (mii_advertise & ADVERTISE_10HALF) {
1434 printk("10Mbps, half duplex\n");
1439 mii_ctl = mdio_read(dev, np->phys[0], MII_BMCR);
1440 speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10;
1442 printk(KERN_INFO "%s: Link changed: %dMbps ,",
1444 printk("%s duplex.\n",
1445 (mii_ctl & BMCR_FULLDPLX) ?
1449 if (np->flowctrl && np->mii_if.full_duplex) {
1450 iowrite16(ioread16(ioaddr + MulticastFilter1+2) | 0x0200,
1451 ioaddr + MulticastFilter1+2);
1452 iowrite16(ioread16(ioaddr + MACCtrl0) | EnbFlowCtrl,
1455 netif_carrier_on(dev);
1457 printk(KERN_INFO "%s: Link down\n", dev->name);
1458 netif_carrier_off(dev);
1461 if (intr_status & StatsMax) {
1464 if (intr_status & IntrPCIErr) {
1465 printk(KERN_ERR "%s: Something Wicked happened! %4.4x.\n",
1466 dev->name, intr_status);
1467 /* We must do a global reset of DMA to continue. */
1471 static struct net_device_stats *get_stats(struct net_device *dev)
1473 struct netdev_private *np = netdev_priv(dev);
1474 void __iomem *ioaddr = np->base;
1477 /* We should lock this segment of code for SMP eventually, although
1478 the vulnerability window is very small and statistics are
1480 /* The chip only need report frame silently dropped. */
1481 np->stats.rx_missed_errors += ioread8(ioaddr + RxMissed);
1482 np->stats.tx_packets += ioread16(ioaddr + TxFramesOK);
1483 np->stats.rx_packets += ioread16(ioaddr + RxFramesOK);
1484 np->stats.collisions += ioread8(ioaddr + StatsLateColl);
1485 np->stats.collisions += ioread8(ioaddr + StatsMultiColl);
1486 np->stats.collisions += ioread8(ioaddr + StatsOneColl);
1487 np->stats.tx_carrier_errors += ioread8(ioaddr + StatsCarrierError);
1488 ioread8(ioaddr + StatsTxDefer);
1489 for (i = StatsTxDefer; i <= StatsMcastRx; i++)
1490 ioread8(ioaddr + i);
1491 np->stats.tx_bytes += ioread16(ioaddr + TxOctetsLow);
1492 np->stats.tx_bytes += ioread16(ioaddr + TxOctetsHigh) << 16;
1493 np->stats.rx_bytes += ioread16(ioaddr + RxOctetsLow);
1494 np->stats.rx_bytes += ioread16(ioaddr + RxOctetsHigh) << 16;
1499 static void set_rx_mode(struct net_device *dev)
1501 struct netdev_private *np = netdev_priv(dev);
1502 void __iomem *ioaddr = np->base;
1503 u16 mc_filter[4]; /* Multicast hash filter */
1507 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1508 memset(mc_filter, 0xff, sizeof(mc_filter));
1509 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptAll | AcceptMyPhys;
1510 } else if ((dev->mc_count > multicast_filter_limit)
1511 || (dev->flags & IFF_ALLMULTI)) {
1512 /* Too many to match, or accept all multicasts. */
1513 memset(mc_filter, 0xff, sizeof(mc_filter));
1514 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
1515 } else if (dev->mc_count) {
1516 struct dev_mc_list *mclist;
1520 memset (mc_filter, 0, sizeof (mc_filter));
1521 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1522 i++, mclist = mclist->next) {
1523 crc = ether_crc_le (ETH_ALEN, mclist->dmi_addr);
1524 for (index=0, bit=0; bit < 6; bit++, crc <<= 1)
1525 if (crc & 0x80000000) index |= 1 << bit;
1526 mc_filter[index/16] |= (1 << (index % 16));
1528 rx_mode = AcceptBroadcast | AcceptMultiHash | AcceptMyPhys;
1530 iowrite8(AcceptBroadcast | AcceptMyPhys, ioaddr + RxMode);
1533 if (np->mii_if.full_duplex && np->flowctrl)
1534 mc_filter[3] |= 0x0200;
1536 for (i = 0; i < 4; i++)
1537 iowrite16(mc_filter[i], ioaddr + MulticastFilter0 + i*2);
1538 iowrite8(rx_mode, ioaddr + RxMode);
1541 static int __set_mac_addr(struct net_device *dev)
1543 struct netdev_private *np = netdev_priv(dev);
1546 addr16 = (dev->dev_addr[0] | (dev->dev_addr[1] << 8));
1547 iowrite16(addr16, np->base + StationAddr);
1548 addr16 = (dev->dev_addr[2] | (dev->dev_addr[3] << 8));
1549 iowrite16(addr16, np->base + StationAddr+2);
1550 addr16 = (dev->dev_addr[4] | (dev->dev_addr[5] << 8));
1551 iowrite16(addr16, np->base + StationAddr+4);
1555 static int check_if_running(struct net_device *dev)
1557 if (!netif_running(dev))
1562 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1564 struct netdev_private *np = netdev_priv(dev);
1565 strcpy(info->driver, DRV_NAME);
1566 strcpy(info->version, DRV_VERSION);
1567 strcpy(info->bus_info, pci_name(np->pci_dev));
1570 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1572 struct netdev_private *np = netdev_priv(dev);
1573 spin_lock_irq(&np->lock);
1574 mii_ethtool_gset(&np->mii_if, ecmd);
1575 spin_unlock_irq(&np->lock);
1579 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1581 struct netdev_private *np = netdev_priv(dev);
1583 spin_lock_irq(&np->lock);
1584 res = mii_ethtool_sset(&np->mii_if, ecmd);
1585 spin_unlock_irq(&np->lock);
1589 static int nway_reset(struct net_device *dev)
1591 struct netdev_private *np = netdev_priv(dev);
1592 return mii_nway_restart(&np->mii_if);
1595 static u32 get_link(struct net_device *dev)
1597 struct netdev_private *np = netdev_priv(dev);
1598 return mii_link_ok(&np->mii_if);
1601 static u32 get_msglevel(struct net_device *dev)
1603 struct netdev_private *np = netdev_priv(dev);
1604 return np->msg_enable;
1607 static void set_msglevel(struct net_device *dev, u32 val)
1609 struct netdev_private *np = netdev_priv(dev);
1610 np->msg_enable = val;
1613 static const struct ethtool_ops ethtool_ops = {
1614 .begin = check_if_running,
1615 .get_drvinfo = get_drvinfo,
1616 .get_settings = get_settings,
1617 .set_settings = set_settings,
1618 .nway_reset = nway_reset,
1619 .get_link = get_link,
1620 .get_msglevel = get_msglevel,
1621 .set_msglevel = set_msglevel,
1624 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1626 struct netdev_private *np = netdev_priv(dev);
1629 if (!netif_running(dev))
1632 spin_lock_irq(&np->lock);
1633 rc = generic_mii_ioctl(&np->mii_if, if_mii(rq), cmd, NULL);
1634 spin_unlock_irq(&np->lock);
1639 static int netdev_close(struct net_device *dev)
1641 struct netdev_private *np = netdev_priv(dev);
1642 void __iomem *ioaddr = np->base;
1643 struct sk_buff *skb;
1646 /* Wait and kill tasklet */
1647 tasklet_kill(&np->rx_tasklet);
1648 tasklet_kill(&np->tx_tasklet);
1654 netif_stop_queue(dev);
1656 if (netif_msg_ifdown(np)) {
1657 printk(KERN_DEBUG "%s: Shutting down ethercard, status was Tx %2.2x "
1658 "Rx %4.4x Int %2.2x.\n",
1659 dev->name, ioread8(ioaddr + TxStatus),
1660 ioread32(ioaddr + RxStatus), ioread16(ioaddr + IntrStatus));
1661 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1662 dev->name, np->cur_tx, np->dirty_tx, np->cur_rx, np->dirty_rx);
1665 /* Disable interrupts by clearing the interrupt mask. */
1666 iowrite16(0x0000, ioaddr + IntrEnable);
1668 /* Disable Rx and Tx DMA for safely release resource */
1669 iowrite32(0x500, ioaddr + DMACtrl);
1671 /* Stop the chip's Tx and Rx processes. */
1672 iowrite16(TxDisable | RxDisable | StatsDisable, ioaddr + MACCtrl1);
1674 for (i = 2000; i > 0; i--) {
1675 if ((ioread32(ioaddr + DMACtrl) & 0xc000) == 0)
1680 iowrite16(GlobalReset | DMAReset | FIFOReset | NetworkReset,
1681 ioaddr +ASICCtrl + 2);
1683 for (i = 2000; i > 0; i--) {
1684 if ((ioread16(ioaddr + ASICCtrl +2) & ResetBusy) == 0)
1690 if (netif_msg_hw(np)) {
1691 printk("\n"KERN_DEBUG" Tx ring at %8.8x:\n",
1692 (int)(np->tx_ring_dma));
1693 for (i = 0; i < TX_RING_SIZE; i++)
1694 printk(" #%d desc. %4.4x %8.8x %8.8x.\n",
1695 i, np->tx_ring[i].status, np->tx_ring[i].frag[0].addr,
1696 np->tx_ring[i].frag[0].length);
1697 printk("\n"KERN_DEBUG " Rx ring %8.8x:\n",
1698 (int)(np->rx_ring_dma));
1699 for (i = 0; i < /*RX_RING_SIZE*/4 ; i++) {
1700 printk(KERN_DEBUG " #%d desc. %4.4x %4.4x %8.8x\n",
1701 i, np->rx_ring[i].status, np->rx_ring[i].frag[0].addr,
1702 np->rx_ring[i].frag[0].length);
1705 #endif /* __i386__ debugging only */
1707 free_irq(dev->irq, dev);
1709 del_timer_sync(&np->timer);
1711 /* Free all the skbuffs in the Rx queue. */
1712 for (i = 0; i < RX_RING_SIZE; i++) {
1713 np->rx_ring[i].status = 0;
1714 skb = np->rx_skbuff[i];
1716 pci_unmap_single(np->pci_dev,
1717 le32_to_cpu(np->rx_ring[i].frag[0].addr),
1718 np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1720 np->rx_skbuff[i] = NULL;
1722 np->rx_ring[i].frag[0].addr = cpu_to_le32(0xBADF00D0); /* poison */
1724 for (i = 0; i < TX_RING_SIZE; i++) {
1725 np->tx_ring[i].next_desc = 0;
1726 skb = np->tx_skbuff[i];
1728 pci_unmap_single(np->pci_dev,
1729 le32_to_cpu(np->tx_ring[i].frag[0].addr),
1730 skb->len, PCI_DMA_TODEVICE);
1732 np->tx_skbuff[i] = NULL;
1739 static void __devexit sundance_remove1 (struct pci_dev *pdev)
1741 struct net_device *dev = pci_get_drvdata(pdev);
1744 struct netdev_private *np = netdev_priv(dev);
1746 unregister_netdev(dev);
1747 pci_free_consistent(pdev, RX_TOTAL_SIZE, np->rx_ring,
1749 pci_free_consistent(pdev, TX_TOTAL_SIZE, np->tx_ring,
1751 pci_iounmap(pdev, np->base);
1752 pci_release_regions(pdev);
1754 pci_set_drvdata(pdev, NULL);
1758 static struct pci_driver sundance_driver = {
1760 .id_table = sundance_pci_tbl,
1761 .probe = sundance_probe1,
1762 .remove = __devexit_p(sundance_remove1),
1765 static int __init sundance_init(void)
1767 /* when a module, this is printed whether or not devices are found in probe */
1771 return pci_register_driver(&sundance_driver);
1774 static void __exit sundance_exit(void)
1776 pci_unregister_driver(&sundance_driver);
1779 module_init(sundance_init);
1780 module_exit(sundance_exit);