1 /* $Id: sunbmac.c,v 1.30 2002/01/15 06:48:55 davem Exp $
2 * sunbmac.c: Driver for Sparc BigMAC 100baseT ethernet adapters.
4 * Copyright (C) 1997, 1998, 1999, 2003 David S. Miller (davem@redhat.com)
7 #include <linux/module.h>
9 #include <linux/kernel.h>
10 #include <linux/types.h>
11 #include <linux/fcntl.h>
12 #include <linux/interrupt.h>
13 #include <linux/ioport.h>
15 #include <linux/slab.h>
16 #include <linux/string.h>
17 #include <linux/delay.h>
18 #include <linux/init.h>
19 #include <linux/crc32.h>
20 #include <linux/errno.h>
21 #include <linux/ethtool.h>
22 #include <linux/netdevice.h>
23 #include <linux/etherdevice.h>
24 #include <linux/skbuff.h>
25 #include <linux/bitops.h>
27 #include <asm/auxio.h>
28 #include <asm/byteorder.h>
30 #include <asm/idprom.h>
32 #include <asm/openprom.h>
33 #include <asm/oplib.h>
34 #include <asm/pgtable.h>
36 #include <asm/system.h>
40 #define DRV_NAME "sunbmac"
41 #define DRV_VERSION "2.0"
42 #define DRV_RELDATE "11/24/03"
43 #define DRV_AUTHOR "David S. Miller (davem@redhat.com)"
45 static char version[] __initdata =
46 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " " DRV_AUTHOR "\n";
48 MODULE_VERSION(DRV_VERSION);
49 MODULE_AUTHOR(DRV_AUTHOR);
50 MODULE_DESCRIPTION("Sun BigMAC 100baseT ethernet driver");
51 MODULE_LICENSE("GPL");
58 #define DP(x) printk x
64 #define DTX(x) printk x
70 #define DIRQ(x) printk x
75 #define DEFAULT_JAMSIZE 4 /* Toe jam */
77 #define QEC_RESET_TRIES 200
79 static int qec_global_reset(void __iomem *gregs)
81 int tries = QEC_RESET_TRIES;
83 sbus_writel(GLOB_CTRL_RESET, gregs + GLOB_CTRL);
85 if (sbus_readl(gregs + GLOB_CTRL) & GLOB_CTRL_RESET) {
93 printk(KERN_ERR "BigMAC: Cannot reset the QEC.\n");
97 static void qec_init(struct bigmac *bp)
99 void __iomem *gregs = bp->gregs;
100 struct sbus_dev *qec_sdev = bp->qec_sdev;
101 u8 bsizes = bp->bigmac_bursts;
104 /* 64byte bursts do not work at the moment, do
105 * not even try to enable them. -DaveM
107 if (bsizes & DMA_BURST32)
108 regval = GLOB_CTRL_B32;
110 regval = GLOB_CTRL_B16;
111 sbus_writel(regval | GLOB_CTRL_BMODE, gregs + GLOB_CTRL);
112 sbus_writel(GLOB_PSIZE_2048, gregs + GLOB_PSIZE);
114 /* All of memsize is given to bigmac. */
115 sbus_writel(qec_sdev->reg_addrs[1].reg_size,
118 /* Half to the transmitter, half to the receiver. */
119 sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
121 sbus_writel(qec_sdev->reg_addrs[1].reg_size >> 1,
125 #define TX_RESET_TRIES 32
126 #define RX_RESET_TRIES 32
128 static void bigmac_tx_reset(void __iomem *bregs)
130 int tries = TX_RESET_TRIES;
132 sbus_writel(0, bregs + BMAC_TXCFG);
134 /* The fifo threshold bit is read-only and does
137 while ((sbus_readl(bregs + BMAC_TXCFG) & ~(BIGMAC_TXCFG_FIFO)) != 0 &&
142 printk(KERN_ERR "BIGMAC: Transmitter will not reset.\n");
143 printk(KERN_ERR "BIGMAC: tx_cfg is %08x\n",
144 sbus_readl(bregs + BMAC_TXCFG));
148 static void bigmac_rx_reset(void __iomem *bregs)
150 int tries = RX_RESET_TRIES;
152 sbus_writel(0, bregs + BMAC_RXCFG);
153 while (sbus_readl(bregs + BMAC_RXCFG) && --tries)
157 printk(KERN_ERR "BIGMAC: Receiver will not reset.\n");
158 printk(KERN_ERR "BIGMAC: rx_cfg is %08x\n",
159 sbus_readl(bregs + BMAC_RXCFG));
163 /* Reset the transmitter and receiver. */
164 static void bigmac_stop(struct bigmac *bp)
166 bigmac_tx_reset(bp->bregs);
167 bigmac_rx_reset(bp->bregs);
170 static void bigmac_get_counters(struct bigmac *bp, void __iomem *bregs)
172 struct net_device_stats *stats = &bp->enet_stats;
174 stats->rx_crc_errors += sbus_readl(bregs + BMAC_RCRCECTR);
175 sbus_writel(0, bregs + BMAC_RCRCECTR);
177 stats->rx_frame_errors += sbus_readl(bregs + BMAC_UNALECTR);
178 sbus_writel(0, bregs + BMAC_UNALECTR);
180 stats->rx_length_errors += sbus_readl(bregs + BMAC_GLECTR);
181 sbus_writel(0, bregs + BMAC_GLECTR);
183 stats->tx_aborted_errors += sbus_readl(bregs + BMAC_EXCTR);
186 (sbus_readl(bregs + BMAC_EXCTR) +
187 sbus_readl(bregs + BMAC_LTCTR));
188 sbus_writel(0, bregs + BMAC_EXCTR);
189 sbus_writel(0, bregs + BMAC_LTCTR);
192 static void bigmac_clean_rings(struct bigmac *bp)
196 for (i = 0; i < RX_RING_SIZE; i++) {
197 if (bp->rx_skbs[i] != NULL) {
198 dev_kfree_skb_any(bp->rx_skbs[i]);
199 bp->rx_skbs[i] = NULL;
203 for (i = 0; i < TX_RING_SIZE; i++) {
204 if (bp->tx_skbs[i] != NULL) {
205 dev_kfree_skb_any(bp->tx_skbs[i]);
206 bp->tx_skbs[i] = NULL;
211 static void bigmac_init_rings(struct bigmac *bp, int from_irq)
213 struct bmac_init_block *bb = bp->bmac_block;
214 struct net_device *dev = bp->dev;
216 gfp_t gfp_flags = GFP_KERNEL;
218 if (from_irq || in_interrupt())
219 gfp_flags = GFP_ATOMIC;
221 bp->rx_new = bp->rx_old = bp->tx_new = bp->tx_old = 0;
223 /* Free any skippy bufs left around in the rings. */
224 bigmac_clean_rings(bp);
226 /* Now get new skbufs for the receive ring. */
227 for (i = 0; i < RX_RING_SIZE; i++) {
230 skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, gfp_flags);
234 bp->rx_skbs[i] = skb;
237 /* Because we reserve afterwards. */
238 skb_put(skb, ETH_FRAME_LEN);
239 skb_reserve(skb, 34);
241 bb->be_rxd[i].rx_addr =
242 sbus_map_single(bp->bigmac_sdev, skb->data,
243 RX_BUF_ALLOC_SIZE - 34,
244 SBUS_DMA_FROMDEVICE);
245 bb->be_rxd[i].rx_flags =
246 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
249 for (i = 0; i < TX_RING_SIZE; i++)
250 bb->be_txd[i].tx_flags = bb->be_txd[i].tx_addr = 0;
253 #define MGMT_CLKON (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB|MGMT_PAL_DCLOCK)
254 #define MGMT_CLKOFF (MGMT_PAL_INT_MDIO|MGMT_PAL_EXT_MDIO|MGMT_PAL_OENAB)
256 static void idle_transceiver(void __iomem *tregs)
261 sbus_writel(MGMT_CLKOFF, tregs + TCVR_MPAL);
262 sbus_readl(tregs + TCVR_MPAL);
263 sbus_writel(MGMT_CLKON, tregs + TCVR_MPAL);
264 sbus_readl(tregs + TCVR_MPAL);
268 static void write_tcvr_bit(struct bigmac *bp, void __iomem *tregs, int bit)
270 if (bp->tcvr_type == internal) {
271 bit = (bit & 1) << 3;
272 sbus_writel(bit | (MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO),
274 sbus_readl(tregs + TCVR_MPAL);
275 sbus_writel(bit | MGMT_PAL_OENAB | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
277 sbus_readl(tregs + TCVR_MPAL);
278 } else if (bp->tcvr_type == external) {
279 bit = (bit & 1) << 2;
280 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB,
282 sbus_readl(tregs + TCVR_MPAL);
283 sbus_writel(bit | MGMT_PAL_INT_MDIO | MGMT_PAL_OENAB | MGMT_PAL_DCLOCK,
285 sbus_readl(tregs + TCVR_MPAL);
287 printk(KERN_ERR "write_tcvr_bit: No transceiver type known!\n");
291 static int read_tcvr_bit(struct bigmac *bp, void __iomem *tregs)
295 if (bp->tcvr_type == internal) {
296 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
297 sbus_readl(tregs + TCVR_MPAL);
298 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
300 sbus_readl(tregs + TCVR_MPAL);
301 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
302 } else if (bp->tcvr_type == external) {
303 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
304 sbus_readl(tregs + TCVR_MPAL);
305 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
306 sbus_readl(tregs + TCVR_MPAL);
307 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
309 printk(KERN_ERR "read_tcvr_bit: No transceiver type known!\n");
314 static int read_tcvr_bit2(struct bigmac *bp, void __iomem *tregs)
318 if (bp->tcvr_type == internal) {
319 sbus_writel(MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
320 sbus_readl(tregs + TCVR_MPAL);
321 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_INT_MDIO) >> 3;
322 sbus_writel(MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
323 sbus_readl(tregs + TCVR_MPAL);
324 } else if (bp->tcvr_type == external) {
325 sbus_writel(MGMT_PAL_INT_MDIO, tregs + TCVR_MPAL);
326 sbus_readl(tregs + TCVR_MPAL);
327 retval = (sbus_readl(tregs + TCVR_MPAL) & MGMT_PAL_EXT_MDIO) >> 2;
328 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_DCLOCK, tregs + TCVR_MPAL);
329 sbus_readl(tregs + TCVR_MPAL);
331 printk(KERN_ERR "read_tcvr_bit2: No transceiver type known!\n");
336 static void put_tcvr_byte(struct bigmac *bp,
343 write_tcvr_bit(bp, tregs, ((byte >> shift) & 1));
345 } while (shift >= 0);
348 static void bigmac_tcvr_write(struct bigmac *bp, void __iomem *tregs,
349 int reg, unsigned short val)
355 switch(bp->tcvr_type) {
361 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
365 idle_transceiver(tregs);
366 write_tcvr_bit(bp, tregs, 0);
367 write_tcvr_bit(bp, tregs, 1);
368 write_tcvr_bit(bp, tregs, 0);
369 write_tcvr_bit(bp, tregs, 1);
371 put_tcvr_byte(bp, tregs,
372 ((bp->tcvr_type == internal) ?
373 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
375 put_tcvr_byte(bp, tregs, reg);
377 write_tcvr_bit(bp, tregs, 1);
378 write_tcvr_bit(bp, tregs, 0);
382 write_tcvr_bit(bp, tregs, (val >> shift) & 1);
384 } while (shift >= 0);
387 static unsigned short bigmac_tcvr_read(struct bigmac *bp,
391 unsigned short retval = 0;
394 switch(bp->tcvr_type) {
400 printk(KERN_ERR "bigmac_tcvr_read: Whoops, no known transceiver type.\n");
404 idle_transceiver(tregs);
405 write_tcvr_bit(bp, tregs, 0);
406 write_tcvr_bit(bp, tregs, 1);
407 write_tcvr_bit(bp, tregs, 1);
408 write_tcvr_bit(bp, tregs, 0);
410 put_tcvr_byte(bp, tregs,
411 ((bp->tcvr_type == internal) ?
412 BIGMAC_PHY_INTERNAL : BIGMAC_PHY_EXTERNAL));
414 put_tcvr_byte(bp, tregs, reg);
416 if (bp->tcvr_type == external) {
419 (void) read_tcvr_bit2(bp, tregs);
420 (void) read_tcvr_bit2(bp, tregs);
425 tmp = read_tcvr_bit2(bp, tregs);
426 retval |= ((tmp & 1) << shift);
428 } while (shift >= 0);
430 (void) read_tcvr_bit2(bp, tregs);
431 (void) read_tcvr_bit2(bp, tregs);
432 (void) read_tcvr_bit2(bp, tregs);
436 (void) read_tcvr_bit(bp, tregs);
437 (void) read_tcvr_bit(bp, tregs);
442 tmp = read_tcvr_bit(bp, tregs);
443 retval |= ((tmp & 1) << shift);
445 } while (shift >= 0);
447 (void) read_tcvr_bit(bp, tregs);
448 (void) read_tcvr_bit(bp, tregs);
449 (void) read_tcvr_bit(bp, tregs);
454 static void bigmac_tcvr_init(struct bigmac *bp)
456 void __iomem *tregs = bp->tregs;
459 idle_transceiver(tregs);
460 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO | MGMT_PAL_DCLOCK,
462 sbus_readl(tregs + TCVR_MPAL);
464 /* Only the bit for the present transceiver (internal or
465 * external) will stick, set them both and see what stays.
467 sbus_writel(MGMT_PAL_INT_MDIO | MGMT_PAL_EXT_MDIO, tregs + TCVR_MPAL);
468 sbus_readl(tregs + TCVR_MPAL);
471 mpal = sbus_readl(tregs + TCVR_MPAL);
472 if (mpal & MGMT_PAL_EXT_MDIO) {
473 bp->tcvr_type = external;
474 sbus_writel(~(TCVR_PAL_EXTLBACK | TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
476 sbus_readl(tregs + TCVR_TPAL);
477 } else if (mpal & MGMT_PAL_INT_MDIO) {
478 bp->tcvr_type = internal;
479 sbus_writel(~(TCVR_PAL_SERIAL | TCVR_PAL_EXTLBACK |
480 TCVR_PAL_MSENSE | TCVR_PAL_LTENABLE),
482 sbus_readl(tregs + TCVR_TPAL);
484 printk(KERN_ERR "BIGMAC: AIEEE, neither internal nor "
485 "external MDIO available!\n");
486 printk(KERN_ERR "BIGMAC: mgmt_pal[%08x] tcvr_pal[%08x]\n",
487 sbus_readl(tregs + TCVR_MPAL),
488 sbus_readl(tregs + TCVR_TPAL));
492 static int bigmac_init_hw(struct bigmac *, int);
494 static int try_next_permutation(struct bigmac *bp, void __iomem *tregs)
496 if (bp->sw_bmcr & BMCR_SPEED100) {
500 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
501 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
502 bp->sw_bmcr = (BMCR_RESET);
503 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
507 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
508 if ((bp->sw_bmcr & BMCR_RESET) == 0)
513 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
515 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
517 /* Now we try 10baseT. */
518 bp->sw_bmcr &= ~(BMCR_SPEED100);
519 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
523 /* We've tried them all. */
527 static void bigmac_timer(unsigned long data)
529 struct bigmac *bp = (struct bigmac *) data;
530 void __iomem *tregs = bp->tregs;
531 int restart_timer = 0;
534 if (bp->timer_state == ltrywait) {
535 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
536 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
537 if (bp->sw_bmsr & BMSR_LSTATUS) {
538 printk(KERN_INFO "%s: Link is now up at %s.\n",
540 (bp->sw_bmcr & BMCR_SPEED100) ?
541 "100baseT" : "10baseT");
542 bp->timer_state = asleep;
545 if (bp->timer_ticks >= 4) {
548 ret = try_next_permutation(bp, tregs);
550 printk(KERN_ERR "%s: Link down, cable problem?\n",
552 ret = bigmac_init_hw(bp, 0);
554 printk(KERN_ERR "%s: Error, cannot re-init the "
555 "BigMAC.\n", bp->dev->name);
566 /* Can't happens.... */
567 printk(KERN_ERR "%s: Aieee, link timer is asleep but we got one anyways!\n",
571 bp->timer_state = asleep; /* foo on you */
574 if (restart_timer != 0) {
575 bp->bigmac_timer.expires = jiffies + ((12 * HZ)/10); /* 1.2 sec. */
576 add_timer(&bp->bigmac_timer);
580 /* Well, really we just force the chip into 100baseT then
581 * 10baseT, each time checking for a link status.
583 static void bigmac_begin_auto_negotiation(struct bigmac *bp)
585 void __iomem *tregs = bp->tregs;
588 /* Grab new software copies of PHY registers. */
589 bp->sw_bmsr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMSR);
590 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
593 bp->sw_bmcr = (BMCR_ISOLATE | BMCR_PDOWN | BMCR_LOOPBACK);
594 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
595 bp->sw_bmcr = (BMCR_RESET);
596 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
600 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
601 if ((bp->sw_bmcr & BMCR_RESET) == 0)
606 printk(KERN_ERR "%s: PHY reset failed.\n", bp->dev->name);
608 bp->sw_bmcr = bigmac_tcvr_read(bp, tregs, BIGMAC_BMCR);
610 /* First we try 100baseT. */
611 bp->sw_bmcr |= BMCR_SPEED100;
612 bigmac_tcvr_write(bp, tregs, BIGMAC_BMCR, bp->sw_bmcr);
614 bp->timer_state = ltrywait;
616 bp->bigmac_timer.expires = jiffies + (12 * HZ) / 10;
617 bp->bigmac_timer.data = (unsigned long) bp;
618 bp->bigmac_timer.function = &bigmac_timer;
619 add_timer(&bp->bigmac_timer);
622 static int bigmac_init_hw(struct bigmac *bp, int from_irq)
624 void __iomem *gregs = bp->gregs;
625 void __iomem *cregs = bp->creg;
626 void __iomem *bregs = bp->bregs;
627 unsigned char *e = &bp->dev->dev_addr[0];
629 /* Latch current counters into statistics. */
630 bigmac_get_counters(bp, bregs);
633 qec_global_reset(gregs);
638 /* Alloc and reset the tx/rx descriptor chains. */
639 bigmac_init_rings(bp, from_irq);
641 /* Initialize the PHY. */
642 bigmac_tcvr_init(bp);
644 /* Stop transmitter and receiver. */
647 /* Set hardware ethernet address. */
648 sbus_writel(((e[4] << 8) | e[5]), bregs + BMAC_MACADDR2);
649 sbus_writel(((e[2] << 8) | e[3]), bregs + BMAC_MACADDR1);
650 sbus_writel(((e[0] << 8) | e[1]), bregs + BMAC_MACADDR0);
652 /* Clear the hash table until mc upload occurs. */
653 sbus_writel(0, bregs + BMAC_HTABLE3);
654 sbus_writel(0, bregs + BMAC_HTABLE2);
655 sbus_writel(0, bregs + BMAC_HTABLE1);
656 sbus_writel(0, bregs + BMAC_HTABLE0);
658 /* Enable Big Mac hash table filter. */
659 sbus_writel(BIGMAC_RXCFG_HENABLE | BIGMAC_RXCFG_FIFO,
663 /* Ok, configure the Big Mac transmitter. */
664 sbus_writel(BIGMAC_TXCFG_FIFO, bregs + BMAC_TXCFG);
666 /* The HME docs recommend to use the 10LSB of our MAC here. */
667 sbus_writel(((e[5] | e[4] << 8) & 0x3ff),
670 /* Enable the output drivers no matter what. */
671 sbus_writel(BIGMAC_XCFG_ODENABLE | BIGMAC_XCFG_RESV,
672 bregs + BMAC_XIFCFG);
674 /* Tell the QEC where the ring descriptors are. */
675 sbus_writel(bp->bblock_dvma + bib_offset(be_rxd, 0),
677 sbus_writel(bp->bblock_dvma + bib_offset(be_txd, 0),
680 /* Setup the FIFO pointers into QEC local memory. */
681 sbus_writel(0, cregs + CREG_RXRBUFPTR);
682 sbus_writel(0, cregs + CREG_RXWBUFPTR);
683 sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
684 cregs + CREG_TXRBUFPTR);
685 sbus_writel(sbus_readl(gregs + GLOB_RSIZE),
686 cregs + CREG_TXWBUFPTR);
688 /* Tell bigmac what interrupts we don't want to hear about. */
689 sbus_writel(BIGMAC_IMASK_GOTFRAME | BIGMAC_IMASK_SENTFRAME,
692 /* Enable the various other irq's. */
693 sbus_writel(0, cregs + CREG_RIMASK);
694 sbus_writel(0, cregs + CREG_TIMASK);
695 sbus_writel(0, cregs + CREG_QMASK);
696 sbus_writel(0, cregs + CREG_BMASK);
698 /* Set jam size to a reasonable default. */
699 sbus_writel(DEFAULT_JAMSIZE, bregs + BMAC_JSIZE);
701 /* Clear collision counter. */
702 sbus_writel(0, cregs + CREG_CCNT);
704 /* Enable transmitter and receiver. */
705 sbus_writel(sbus_readl(bregs + BMAC_TXCFG) | BIGMAC_TXCFG_ENABLE,
707 sbus_writel(sbus_readl(bregs + BMAC_RXCFG) | BIGMAC_RXCFG_ENABLE,
710 /* Ok, start detecting link speed/duplex. */
711 bigmac_begin_auto_negotiation(bp);
717 /* Error interrupts get sent here. */
718 static void bigmac_is_medium_rare(struct bigmac *bp, u32 qec_status, u32 bmac_status)
720 printk(KERN_ERR "bigmac_is_medium_rare: ");
721 if (qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) {
722 if (qec_status & GLOB_STAT_ER)
723 printk("QEC_ERROR, ");
724 if (qec_status & GLOB_STAT_BM)
725 printk("QEC_BMAC_ERROR, ");
727 if (bmac_status & CREG_STAT_ERRORS) {
728 if (bmac_status & CREG_STAT_BERROR)
729 printk("BMAC_ERROR, ");
730 if (bmac_status & CREG_STAT_TXDERROR)
731 printk("TXD_ERROR, ");
732 if (bmac_status & CREG_STAT_TXLERR)
733 printk("TX_LATE_ERROR, ");
734 if (bmac_status & CREG_STAT_TXPERR)
735 printk("TX_PARITY_ERROR, ");
736 if (bmac_status & CREG_STAT_TXSERR)
737 printk("TX_SBUS_ERROR, ");
739 if (bmac_status & CREG_STAT_RXDROP)
740 printk("RX_DROP_ERROR, ");
742 if (bmac_status & CREG_STAT_RXSMALL)
743 printk("RX_SMALL_ERROR, ");
744 if (bmac_status & CREG_STAT_RXLERR)
745 printk("RX_LATE_ERROR, ");
746 if (bmac_status & CREG_STAT_RXPERR)
747 printk("RX_PARITY_ERROR, ");
748 if (bmac_status & CREG_STAT_RXSERR)
749 printk("RX_SBUS_ERROR, ");
753 bigmac_init_hw(bp, 1);
756 /* BigMAC transmit complete service routines. */
757 static void bigmac_tx(struct bigmac *bp)
759 struct be_txd *txbase = &bp->bmac_block->be_txd[0];
760 struct net_device *dev = bp->dev;
763 spin_lock(&bp->lock);
766 DTX(("bigmac_tx: tx_old[%d] ", elem));
767 while (elem != bp->tx_new) {
769 struct be_txd *this = &txbase[elem];
771 DTX(("this(%p) [flags(%08x)addr(%08x)]",
772 this, this->tx_flags, this->tx_addr));
774 if (this->tx_flags & TXD_OWN)
776 skb = bp->tx_skbs[elem];
777 bp->enet_stats.tx_packets++;
778 bp->enet_stats.tx_bytes += skb->len;
779 sbus_unmap_single(bp->bigmac_sdev,
780 this->tx_addr, skb->len,
783 DTX(("skb(%p) ", skb));
784 bp->tx_skbs[elem] = NULL;
785 dev_kfree_skb_irq(skb);
787 elem = NEXT_TX(elem);
789 DTX((" DONE, tx_old=%d\n", elem));
792 if (netif_queue_stopped(dev) &&
793 TX_BUFFS_AVAIL(bp) > 0)
794 netif_wake_queue(bp->dev);
796 spin_unlock(&bp->lock);
799 /* BigMAC receive complete service routines. */
800 static void bigmac_rx(struct bigmac *bp)
802 struct be_rxd *rxbase = &bp->bmac_block->be_rxd[0];
804 int elem = bp->rx_new, drops = 0;
807 this = &rxbase[elem];
808 while (!((flags = this->rx_flags) & RXD_OWN)) {
810 int len = (flags & RXD_LENGTH); /* FCS not included */
812 /* Check for errors. */
813 if (len < ETH_ZLEN) {
814 bp->enet_stats.rx_errors++;
815 bp->enet_stats.rx_length_errors++;
818 /* Return it to the BigMAC. */
819 bp->enet_stats.rx_dropped++;
821 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
824 skb = bp->rx_skbs[elem];
825 if (len > RX_COPY_THRESHOLD) {
826 struct sk_buff *new_skb;
828 /* Now refill the entry, if we can. */
829 new_skb = big_mac_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
830 if (new_skb == NULL) {
834 sbus_unmap_single(bp->bigmac_sdev,
836 RX_BUF_ALLOC_SIZE - 34,
837 SBUS_DMA_FROMDEVICE);
838 bp->rx_skbs[elem] = new_skb;
839 new_skb->dev = bp->dev;
840 skb_put(new_skb, ETH_FRAME_LEN);
841 skb_reserve(new_skb, 34);
842 this->rx_addr = sbus_map_single(bp->bigmac_sdev,
844 RX_BUF_ALLOC_SIZE - 34,
845 SBUS_DMA_FROMDEVICE);
847 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
849 /* Trim the original skb for the netif. */
852 struct sk_buff *copy_skb = dev_alloc_skb(len + 2);
854 if (copy_skb == NULL) {
858 copy_skb->dev = bp->dev;
859 skb_reserve(copy_skb, 2);
860 skb_put(copy_skb, len);
861 sbus_dma_sync_single_for_cpu(bp->bigmac_sdev,
863 SBUS_DMA_FROMDEVICE);
864 eth_copy_and_sum(copy_skb, (unsigned char *)skb->data, len, 0);
865 sbus_dma_sync_single_for_device(bp->bigmac_sdev,
867 SBUS_DMA_FROMDEVICE);
869 /* Reuse original ring buffer. */
871 (RXD_OWN | ((RX_BUF_ALLOC_SIZE - 34) & RXD_LENGTH));
876 /* No checksums done by the BigMAC ;-( */
877 skb->protocol = eth_type_trans(skb, bp->dev);
879 bp->dev->last_rx = jiffies;
880 bp->enet_stats.rx_packets++;
881 bp->enet_stats.rx_bytes += len;
883 elem = NEXT_RX(elem);
884 this = &rxbase[elem];
888 printk(KERN_NOTICE "%s: Memory squeeze, deferring packet.\n", bp->dev->name);
891 static irqreturn_t bigmac_interrupt(int irq, void *dev_id, struct pt_regs *regs)
893 struct bigmac *bp = (struct bigmac *) dev_id;
894 u32 qec_status, bmac_status;
896 DIRQ(("bigmac_interrupt: "));
898 /* Latch status registers now. */
899 bmac_status = sbus_readl(bp->creg + CREG_STAT);
900 qec_status = sbus_readl(bp->gregs + GLOB_STAT);
902 DIRQ(("qec_status=%08x bmac_status=%08x\n", qec_status, bmac_status));
903 if ((qec_status & (GLOB_STAT_ER | GLOB_STAT_BM)) ||
904 (bmac_status & CREG_STAT_ERRORS))
905 bigmac_is_medium_rare(bp, qec_status, bmac_status);
907 if (bmac_status & CREG_STAT_TXIRQ)
910 if (bmac_status & CREG_STAT_RXIRQ)
916 static int bigmac_open(struct net_device *dev)
918 struct bigmac *bp = (struct bigmac *) dev->priv;
921 ret = request_irq(dev->irq, &bigmac_interrupt, IRQF_SHARED, dev->name, bp);
923 printk(KERN_ERR "BIGMAC: Can't order irq %d to go.\n", dev->irq);
926 init_timer(&bp->bigmac_timer);
927 ret = bigmac_init_hw(bp, 0);
929 free_irq(dev->irq, bp);
933 static int bigmac_close(struct net_device *dev)
935 struct bigmac *bp = (struct bigmac *) dev->priv;
937 del_timer(&bp->bigmac_timer);
938 bp->timer_state = asleep;
942 bigmac_clean_rings(bp);
943 free_irq(dev->irq, bp);
947 static void bigmac_tx_timeout(struct net_device *dev)
949 struct bigmac *bp = (struct bigmac *) dev->priv;
951 bigmac_init_hw(bp, 0);
952 netif_wake_queue(dev);
955 /* Put a packet on the wire. */
956 static int bigmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
958 struct bigmac *bp = (struct bigmac *) dev->priv;
963 mapping = sbus_map_single(bp->bigmac_sdev, skb->data, len, SBUS_DMA_TODEVICE);
965 /* Avoid a race... */
966 spin_lock_irq(&bp->lock);
968 DTX(("bigmac_start_xmit: len(%d) entry(%d)\n", len, entry));
969 bp->bmac_block->be_txd[entry].tx_flags = TXD_UPDATE;
970 bp->tx_skbs[entry] = skb;
971 bp->bmac_block->be_txd[entry].tx_addr = mapping;
972 bp->bmac_block->be_txd[entry].tx_flags =
973 (TXD_OWN | TXD_SOP | TXD_EOP | (len & TXD_LENGTH));
974 bp->tx_new = NEXT_TX(entry);
975 if (TX_BUFFS_AVAIL(bp) <= 0)
976 netif_stop_queue(dev);
977 spin_unlock_irq(&bp->lock);
980 sbus_writel(CREG_CTRL_TWAKEUP, bp->creg + CREG_CTRL);
983 dev->trans_start = jiffies;
988 static struct net_device_stats *bigmac_get_stats(struct net_device *dev)
990 struct bigmac *bp = (struct bigmac *) dev->priv;
992 bigmac_get_counters(bp, bp->bregs);
993 return &bp->enet_stats;
996 static void bigmac_set_multicast(struct net_device *dev)
998 struct bigmac *bp = (struct bigmac *) dev->priv;
999 void __iomem *bregs = bp->bregs;
1000 struct dev_mc_list *dmi = dev->mc_list;
1005 /* Disable the receiver. The bit self-clears when
1006 * the operation is complete.
1008 tmp = sbus_readl(bregs + BMAC_RXCFG);
1009 tmp &= ~(BIGMAC_RXCFG_ENABLE);
1010 sbus_writel(tmp, bregs + BMAC_RXCFG);
1011 while ((sbus_readl(bregs + BMAC_RXCFG) & BIGMAC_RXCFG_ENABLE) != 0)
1014 if ((dev->flags & IFF_ALLMULTI) || (dev->mc_count > 64)) {
1015 sbus_writel(0xffff, bregs + BMAC_HTABLE0);
1016 sbus_writel(0xffff, bregs + BMAC_HTABLE1);
1017 sbus_writel(0xffff, bregs + BMAC_HTABLE2);
1018 sbus_writel(0xffff, bregs + BMAC_HTABLE3);
1019 } else if (dev->flags & IFF_PROMISC) {
1020 tmp = sbus_readl(bregs + BMAC_RXCFG);
1021 tmp |= BIGMAC_RXCFG_PMISC;
1022 sbus_writel(tmp, bregs + BMAC_RXCFG);
1026 for (i = 0; i < 4; i++)
1029 for (i = 0; i < dev->mc_count; i++) {
1030 addrs = dmi->dmi_addr;
1036 crc = ether_crc_le(6, addrs);
1038 hash_table[crc >> 4] |= 1 << (crc & 0xf);
1040 sbus_writel(hash_table[0], bregs + BMAC_HTABLE0);
1041 sbus_writel(hash_table[1], bregs + BMAC_HTABLE1);
1042 sbus_writel(hash_table[2], bregs + BMAC_HTABLE2);
1043 sbus_writel(hash_table[3], bregs + BMAC_HTABLE3);
1046 /* Re-enable the receiver. */
1047 tmp = sbus_readl(bregs + BMAC_RXCFG);
1048 tmp |= BIGMAC_RXCFG_ENABLE;
1049 sbus_writel(tmp, bregs + BMAC_RXCFG);
1052 /* Ethtool support... */
1053 static void bigmac_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1055 struct bigmac *bp = dev->priv;
1057 strcpy(info->driver, "sunbmac");
1058 strcpy(info->version, "2.0");
1059 sprintf(info->bus_info, "SBUS:%d",
1060 bp->qec_sdev->slot);
1063 static u32 bigmac_get_link(struct net_device *dev)
1065 struct bigmac *bp = dev->priv;
1067 spin_lock_irq(&bp->lock);
1068 bp->sw_bmsr = bigmac_tcvr_read(bp, bp->tregs, BIGMAC_BMSR);
1069 spin_unlock_irq(&bp->lock);
1071 return (bp->sw_bmsr & BMSR_LSTATUS);
1074 static struct ethtool_ops bigmac_ethtool_ops = {
1075 .get_drvinfo = bigmac_get_drvinfo,
1076 .get_link = bigmac_get_link,
1079 static int __init bigmac_ether_init(struct sbus_dev *qec_sdev)
1081 struct net_device *dev;
1082 static int version_printed;
1084 u8 bsizes, bsizes_more;
1087 /* Get a new device struct for this interface. */
1088 dev = alloc_etherdev(sizeof(struct bigmac));
1091 SET_MODULE_OWNER(dev);
1093 if (version_printed++ == 0)
1094 printk(KERN_INFO "%s", version);
1096 dev->base_addr = (long) qec_sdev;
1097 for (i = 0; i < 6; i++)
1098 dev->dev_addr[i] = idprom->id_ethaddr[i];
1100 /* Setup softc, with backpointers to QEC and BigMAC SBUS device structs. */
1102 bp->qec_sdev = qec_sdev;
1103 bp->bigmac_sdev = qec_sdev->child;
1105 SET_NETDEV_DEV(dev, &bp->bigmac_sdev->ofdev.dev);
1107 spin_lock_init(&bp->lock);
1109 /* Verify the registers we expect, are actually there. */
1110 if ((bp->bigmac_sdev->num_registers != 3) ||
1111 (bp->qec_sdev->num_registers != 2)) {
1112 printk(KERN_ERR "BIGMAC: Device does not have 2 and 3 regs, it has %d and %d.\n",
1113 bp->qec_sdev->num_registers,
1114 bp->bigmac_sdev->num_registers);
1115 printk(KERN_ERR "BIGMAC: Would you like that for here or to go?\n");
1116 goto fail_and_cleanup;
1119 /* Map in QEC global control registers. */
1120 bp->gregs = sbus_ioremap(&bp->qec_sdev->resource[0], 0,
1121 GLOB_REG_SIZE, "BigMAC QEC GLobal Regs");
1123 printk(KERN_ERR "BIGMAC: Cannot map QEC global registers.\n");
1124 goto fail_and_cleanup;
1127 /* Make sure QEC is in BigMAC mode. */
1128 if ((sbus_readl(bp->gregs + GLOB_CTRL) & 0xf0000000) != GLOB_CTRL_BMODE) {
1129 printk(KERN_ERR "BigMAC: AIEEE, QEC is not in BigMAC mode!\n");
1130 goto fail_and_cleanup;
1133 /* Reset the QEC. */
1134 if (qec_global_reset(bp->gregs))
1135 goto fail_and_cleanup;
1137 /* Get supported SBUS burst sizes. */
1138 bsizes = prom_getintdefault(bp->qec_sdev->prom_node,
1142 bsizes_more = prom_getintdefault(bp->qec_sdev->bus->prom_node,
1147 if (bsizes_more != 0xff)
1148 bsizes &= bsizes_more;
1149 if (bsizes == 0xff || (bsizes & DMA_BURST16) == 0 ||
1150 (bsizes & DMA_BURST32) == 0)
1151 bsizes = (DMA_BURST32 - 1);
1152 bp->bigmac_bursts = bsizes;
1154 /* Perform QEC initialization. */
1157 /* Map in the BigMAC channel registers. */
1158 bp->creg = sbus_ioremap(&bp->bigmac_sdev->resource[0], 0,
1159 CREG_REG_SIZE, "BigMAC QEC Channel Regs");
1161 printk(KERN_ERR "BIGMAC: Cannot map QEC channel registers.\n");
1162 goto fail_and_cleanup;
1165 /* Map in the BigMAC control registers. */
1166 bp->bregs = sbus_ioremap(&bp->bigmac_sdev->resource[1], 0,
1167 BMAC_REG_SIZE, "BigMAC Primary Regs");
1169 printk(KERN_ERR "BIGMAC: Cannot map BigMAC primary registers.\n");
1170 goto fail_and_cleanup;
1173 /* Map in the BigMAC transceiver registers, this is how you poke at
1176 bp->tregs = sbus_ioremap(&bp->bigmac_sdev->resource[2], 0,
1177 TCVR_REG_SIZE, "BigMAC Transceiver Regs");
1179 printk(KERN_ERR "BIGMAC: Cannot map BigMAC transceiver registers.\n");
1180 goto fail_and_cleanup;
1183 /* Stop the BigMAC. */
1186 /* Allocate transmit/receive descriptor DVMA block. */
1187 bp->bmac_block = sbus_alloc_consistent(bp->bigmac_sdev,
1190 if (bp->bmac_block == NULL || bp->bblock_dvma == 0) {
1191 printk(KERN_ERR "BIGMAC: Cannot allocate consistent DMA.\n");
1192 goto fail_and_cleanup;
1195 /* Get the board revision of this BigMAC. */
1196 bp->board_rev = prom_getintdefault(bp->bigmac_sdev->prom_node,
1197 "board-version", 1);
1199 /* Init auto-negotiation timer state. */
1200 init_timer(&bp->bigmac_timer);
1201 bp->timer_state = asleep;
1202 bp->timer_ticks = 0;
1204 /* Backlink to generic net device struct. */
1207 /* Set links to our BigMAC open and close routines. */
1208 dev->open = &bigmac_open;
1209 dev->stop = &bigmac_close;
1210 dev->hard_start_xmit = &bigmac_start_xmit;
1211 dev->ethtool_ops = &bigmac_ethtool_ops;
1213 /* Set links to BigMAC statistic and multi-cast loading code. */
1214 dev->get_stats = &bigmac_get_stats;
1215 dev->set_multicast_list = &bigmac_set_multicast;
1217 dev->tx_timeout = &bigmac_tx_timeout;
1218 dev->watchdog_timeo = 5*HZ;
1220 /* Finish net device registration. */
1221 dev->irq = bp->bigmac_sdev->irqs[0];
1224 if (register_netdev(dev)) {
1225 printk(KERN_ERR "BIGMAC: Cannot register device.\n");
1226 goto fail_and_cleanup;
1229 dev_set_drvdata(&bp->bigmac_sdev->ofdev.dev, bp);
1231 printk(KERN_INFO "%s: BigMAC 100baseT Ethernet ", dev->name);
1232 for (i = 0; i < 6; i++)
1233 printk("%2.2x%c", dev->dev_addr[i],
1234 i == 5 ? ' ' : ':');
1240 /* Something went wrong, undo whatever we did so far. */
1241 /* Free register mappings if any. */
1243 sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1245 sbus_iounmap(bp->creg, CREG_REG_SIZE);
1247 sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1249 sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1252 sbus_free_consistent(bp->bigmac_sdev,
1257 /* This also frees the co-located 'dev->priv' */
1262 /* QEC can be the parent of either QuadEthernet or
1263 * a BigMAC. We want the latter.
1265 static int __devinit bigmac_sbus_probe(struct of_device *dev, const struct of_device_id *match)
1267 struct sbus_dev *sdev = to_sbus_device(&dev->dev);
1268 struct device_node *dp = dev->node;
1270 if (!strcmp(dp->name, "be"))
1271 sdev = sdev->parent;
1273 return bigmac_ether_init(sdev);
1276 static int __devexit bigmac_sbus_remove(struct of_device *dev)
1278 struct bigmac *bp = dev_get_drvdata(&dev->dev);
1279 struct net_device *net_dev = bp->dev;
1281 unregister_netdevice(net_dev);
1283 sbus_iounmap(bp->gregs, GLOB_REG_SIZE);
1284 sbus_iounmap(bp->creg, CREG_REG_SIZE);
1285 sbus_iounmap(bp->bregs, BMAC_REG_SIZE);
1286 sbus_iounmap(bp->tregs, TCVR_REG_SIZE);
1287 sbus_free_consistent(bp->bigmac_sdev,
1292 free_netdev(net_dev);
1294 dev_set_drvdata(&dev->dev, NULL);
1299 static struct of_device_id bigmac_sbus_match[] = {
1309 MODULE_DEVICE_TABLE(of, bigmac_sbus_match);
1311 static struct of_platform_driver bigmac_sbus_driver = {
1313 .match_table = bigmac_sbus_match,
1314 .probe = bigmac_sbus_probe,
1315 .remove = __devexit_p(bigmac_sbus_remove),
1318 static int __init bigmac_init(void)
1320 return of_register_driver(&bigmac_sbus_driver, &sbus_bus_type);
1323 static void __exit bigmac_exit(void)
1325 of_unregister_driver(&bigmac_sbus_driver);
1328 module_init(bigmac_init);
1329 module_exit(bigmac_exit);