1 /* starfire.c: Linux device driver for the Adaptec Starfire network adapter. */
3 Written 1998-2000 by Donald Becker.
5 Current maintainer is Ion Badulescu <ionut ta badula tod org>. Please
6 send all bug reports to me, and not to Donald Becker, as this code
7 has been heavily modified from Donald's original version.
9 This software may be used and distributed according to the terms of
10 the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on or derived from this code fall under the GPL and must
12 retain the authorship, copyright and license notice. This file is not
13 a complete program and may only be used when the entire operating
14 system is licensed under the GPL.
16 The information below comes from Donald Becker's original driver:
18 The author may be reached as becker@scyld.com, or C/O
19 Scyld Computing Corporation
20 410 Severn Ave., Suite 210
23 Support and updates available at
24 http://www.scyld.com/network/starfire.html
25 [link no longer provides useful info -jgarzik]
29 #define DRV_NAME "starfire"
30 #define DRV_VERSION "2.0"
31 #define DRV_RELDATE "June 27, 2006"
33 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/pci.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/init.h>
39 #include <linux/delay.h>
40 #include <linux/crc32.h>
41 #include <linux/ethtool.h>
42 #include <linux/mii.h>
43 #include <linux/if_vlan.h>
45 #include <asm/processor.h> /* Processor type for cache alignment. */
46 #include <asm/uaccess.h>
49 #include "starfire_firmware.h"
51 * The current frame processor firmware fails to checksum a fragment
52 * of length 1. If and when this is fixed, the #define below can be removed.
54 #define HAS_BROKEN_FIRMWARE
57 * If using the broken firmware, data must be padded to the next 32-bit boundary.
59 #ifdef HAS_BROKEN_FIRMWARE
60 #define PADDING_MASK 3
64 * Define this if using the driver with the zero-copy patch
68 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
72 #ifndef CONFIG_ADAPTEC_STARFIRE_NAPI
73 #undef HAVE_NETDEV_POLL
76 /* The user-configurable values.
77 These may be modified when a driver module is loaded.*/
79 /* Used for tuning interrupt latency vs. overhead. */
80 static int intr_latency;
81 static int small_frames;
83 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
84 static int max_interrupt_work = 20;
86 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
87 The Starfire has a 512 element hash table based on the Ethernet CRC. */
88 static const int multicast_filter_limit = 512;
89 /* Whether to do TCP/UDP checksums in hardware */
90 static int enable_hw_cksum = 1;
92 #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
94 * Set the copy breakpoint for the copy-only-tiny-frames scheme.
95 * Setting to > 1518 effectively disables this feature.
98 * The ia64 doesn't allow for unaligned loads even of integers being
99 * misaligned on a 2 byte boundary. Thus always force copying of
100 * packets as the starfire doesn't allow for misaligned DMAs ;-(
103 * The Alpha and the Sparc don't like unaligned loads, either. On Sparc64,
104 * at least, having unaligned frames leads to a rather serious performance
107 #if defined(__ia64__) || defined(__alpha__) || defined(__sparc__)
108 static int rx_copybreak = PKT_BUF_SZ;
110 static int rx_copybreak /* = 0 */;
113 /* PCI DMA burst size -- on sparc64 we want to force it to 64 bytes, on the others the default of 128 is fine. */
115 #define DMA_BURST_SIZE 64
117 #define DMA_BURST_SIZE 128
120 /* Used to pass the media type, etc.
121 Both 'options[]' and 'full_duplex[]' exist for driver interoperability.
122 The media type is usually passed in 'options[]'.
123 These variables are deprecated, use ethtool instead. -Ion
125 #define MAX_UNITS 8 /* More are supported, limit only on options */
126 static int options[MAX_UNITS] = {0, };
127 static int full_duplex[MAX_UNITS] = {0, };
129 /* Operational parameters that are set at compile time. */
131 /* The "native" ring sizes are either 256 or 2048.
132 However in some modes a descriptor may be marked to wrap the ring earlier.
134 #define RX_RING_SIZE 256
135 #define TX_RING_SIZE 32
136 /* The completion queues are fixed at 1024 entries i.e. 4K or 8KB. */
137 #define DONE_Q_SIZE 1024
138 /* All queues must be aligned on a 256-byte boundary */
139 #define QUEUE_ALIGN 256
141 #if RX_RING_SIZE > 256
142 #define RX_Q_ENTRIES Rx2048QEntries
144 #define RX_Q_ENTRIES Rx256QEntries
147 /* Operational parameters that usually are not changed. */
148 /* Time in jiffies before concluding the transmitter is hung. */
149 #define TX_TIMEOUT (2 * HZ)
153 * We need a much better method to determine if dma_addr_t is 64-bit.
155 #if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR))
156 /* 64-bit dma_addr_t */
157 #define ADDR_64BITS /* This chip uses 64 bit addresses. */
158 #define netdrv_addr_t u64
159 #define cpu_to_dma(x) cpu_to_le64(x)
160 #define dma_to_cpu(x) le64_to_cpu(x)
161 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
162 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr64bit
163 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr64bit
164 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
165 #define RX_DESC_ADDR_SIZE RxDescAddr64bit
166 #else /* 32-bit dma_addr_t */
167 #define netdrv_addr_t u32
168 #define cpu_to_dma(x) cpu_to_le32(x)
169 #define dma_to_cpu(x) le32_to_cpu(x)
170 #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
171 #define TX_DESC_Q_ADDR_SIZE TxDescQAddr32bit
172 #define RX_COMPL_Q_ADDR_SIZE RxComplQAddr32bit
173 #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr32bit
174 #define RX_DESC_ADDR_SIZE RxDescAddr32bit
177 #define skb_first_frag_len(skb) skb_headlen(skb)
178 #define skb_num_frags(skb) (skb_shinfo(skb)->nr_frags + 1)
180 #ifdef HAVE_NETDEV_POLL
181 #define init_poll(dev) \
183 dev->poll = &netdev_poll; \
184 dev->weight = max_interrupt_work; \
186 #define netdev_rx(dev, ioaddr) \
189 if (netif_rx_schedule_prep(dev)) { \
190 __netif_rx_schedule(dev); \
191 intr_enable = readl(ioaddr + IntrEnable); \
192 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \
193 writel(intr_enable, ioaddr + IntrEnable); \
194 readl(ioaddr + IntrEnable); /* flush PCI posting buffers */ \
196 /* Paranoia check */ \
197 intr_enable = readl(ioaddr + IntrEnable); \
198 if (intr_enable & (IntrRxDone | IntrRxEmpty)) { \
199 printk(KERN_INFO "%s: interrupt while in polling mode!\n", dev->name); \
200 intr_enable &= ~(IntrRxDone | IntrRxEmpty); \
201 writel(intr_enable, ioaddr + IntrEnable); \
205 #define netdev_receive_skb(skb) netif_receive_skb(skb)
206 #define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_receive_skb(skb, vlgrp, vlid)
207 static int netdev_poll(struct net_device *dev, int *budget);
208 #else /* not HAVE_NETDEV_POLL */
209 #define init_poll(dev)
210 #define netdev_receive_skb(skb) netif_rx(skb)
211 #define vlan_netdev_receive_skb(skb, vlgrp, vlid) vlan_hwaccel_rx(skb, vlgrp, vlid)
212 #define netdev_rx(dev, ioaddr) \
214 int quota = np->dirty_rx + RX_RING_SIZE - np->cur_rx; \
215 __netdev_rx(dev, "a);\
217 #endif /* not HAVE_NETDEV_POLL */
218 /* end of compatibility code */
221 /* These identify the driver base version and may not be removed. */
222 static const char version[] __devinitdata =
223 KERN_INFO "starfire.c:v1.03 7/26/2000 Written by Donald Becker <becker@scyld.com>\n"
224 KERN_INFO " (unofficial 2.2/2.4 kernel port, version " DRV_VERSION ", " DRV_RELDATE ")\n";
226 MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
227 MODULE_DESCRIPTION("Adaptec Starfire Ethernet driver");
228 MODULE_LICENSE("GPL");
229 MODULE_VERSION(DRV_VERSION);
231 module_param(max_interrupt_work, int, 0);
232 module_param(mtu, int, 0);
233 module_param(debug, int, 0);
234 module_param(rx_copybreak, int, 0);
235 module_param(intr_latency, int, 0);
236 module_param(small_frames, int, 0);
237 module_param_array(options, int, NULL, 0);
238 module_param_array(full_duplex, int, NULL, 0);
239 module_param(enable_hw_cksum, int, 0);
240 MODULE_PARM_DESC(max_interrupt_work, "Maximum events handled per interrupt");
241 MODULE_PARM_DESC(mtu, "MTU (all boards)");
242 MODULE_PARM_DESC(debug, "Debug level (0-6)");
243 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
244 MODULE_PARM_DESC(intr_latency, "Maximum interrupt latency, in microseconds");
245 MODULE_PARM_DESC(small_frames, "Maximum size of receive frames that bypass interrupt latency (0,64,128,256,512)");
246 MODULE_PARM_DESC(options, "Deprecated: Bits 0-3: media type, bit 17: full duplex");
247 MODULE_PARM_DESC(full_duplex, "Deprecated: Forced full-duplex setting (0/1)");
248 MODULE_PARM_DESC(enable_hw_cksum, "Enable/disable hardware cksum support (0/1)");
253 I. Board Compatibility
255 This driver is for the Adaptec 6915 "Starfire" 64 bit PCI Ethernet adapter.
257 II. Board-specific settings
259 III. Driver operation
263 The Starfire hardware uses multiple fixed-size descriptor queues/rings. The
264 ring sizes are set fixed by the hardware, but may optionally be wrapped
265 earlier by the END bit in the descriptor.
266 This driver uses that hardware queue size for the Rx ring, where a large
267 number of entries has no ill effect beyond increases the potential backlog.
268 The Tx ring is wrapped with the END bit, since a large hardware Tx queue
269 disables the queue layer priority ordering and we have no mechanism to
270 utilize the hardware two-level priority queue. When modifying the
271 RX/TX_RING_SIZE pay close attention to page sizes and the ring-empty warning
274 IIIb/c. Transmit/Receive Structure
276 See the Adaptec manual for the many possible structures, and options for
277 each structure. There are far too many to document all of them here.
279 For transmit this driver uses type 0/1 transmit descriptors (depending
280 on the 32/64 bitness of the architecture), and relies on automatic
281 minimum-length padding. It does not use the completion queue
282 consumer index, but instead checks for non-zero status entries.
284 For receive this driver uses type 2/3 receive descriptors. The driver
285 allocates full frame size skbuffs for the Rx ring buffers, so all frames
286 should fit in a single descriptor. The driver does not use the completion
287 queue consumer index, but instead checks for non-zero status entries.
289 When an incoming frame is less than RX_COPYBREAK bytes long, a fresh skbuff
290 is allocated and the frame is copied to the new skbuff. When the incoming
291 frame is larger, the skbuff is passed directly up the protocol stack.
292 Buffers consumed this way are replaced by newly allocated skbuffs in a later
295 A notable aspect of operation is that unaligned buffers are not permitted by
296 the Starfire hardware. Thus the IP header at offset 14 in an ethernet frame
297 isn't longword aligned, which may cause problems on some machine
298 e.g. Alphas and IA64. For these architectures, the driver is forced to copy
299 the frame into a new skbuff unconditionally. Copied frames are put into the
300 skbuff at an offset of "+2", thus 16-byte aligning the IP header.
302 IIId. Synchronization
304 The driver runs as two independent, single-threaded flows of control. One
305 is the send-packet routine, which enforces single-threaded use by the
306 dev->tbusy flag. The other thread is the interrupt handler, which is single
307 threaded by the hardware and interrupt handling software.
309 The send packet thread has partial control over the Tx ring and the netif_queue
310 status. If the number of free Tx slots in the ring falls below a certain number
311 (currently hardcoded to 4), it signals the upper layer to stop the queue.
313 The interrupt handler has exclusive control over the Rx ring and records stats
314 from the Tx ring. After reaping the stats, it marks the Tx queue entry as
315 empty by incrementing the dirty_tx mark. Iff the netif_queue is stopped and the
316 number of free Tx slow is above the threshold, it signals the upper layer to
323 The Adaptec Starfire manuals, available only from Adaptec.
324 http://www.scyld.com/expert/100mbps.html
325 http://www.scyld.com/expert/NWay.html
329 - StopOnPerr is broken, don't enable
330 - Hardware ethernet padding exposes random data, perform software padding
331 instead (unverified -- works correctly for all the hardware I have)
337 enum chip_capability_flags {CanHaveMII=1, };
343 static struct pci_device_id starfire_pci_tbl[] = {
344 { 0x9004, 0x6915, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_6915 },
347 MODULE_DEVICE_TABLE(pci, starfire_pci_tbl);
349 /* A chip capabilities table, matching the CH_xxx entries in xxx_pci_tbl[] above. */
350 static const struct chip_info {
353 } netdrv_tbl[] __devinitdata = {
354 { "Adaptec Starfire 6915", CanHaveMII },
358 /* Offsets to the device registers.
359 Unlike software-only systems, device drivers interact with complex hardware.
360 It's not useful to define symbolic names for every register bit in the
361 device. The name can only partially document the semantics and make
362 the driver longer and more difficult to read.
363 In general, only the important configuration values or bits changed
364 multiple times should be defined symbolically.
366 enum register_offsets {
367 PCIDeviceConfig=0x50040, GenCtrl=0x50070, IntrTimerCtrl=0x50074,
368 IntrClear=0x50080, IntrStatus=0x50084, IntrEnable=0x50088,
369 MIICtrl=0x52000, TxStationAddr=0x50120, EEPROMCtrl=0x51000,
370 GPIOCtrl=0x5008C, TxDescCtrl=0x50090,
371 TxRingPtr=0x50098, HiPriTxRingPtr=0x50094, /* Low and High priority. */
372 TxRingHiAddr=0x5009C, /* 64 bit address extension. */
373 TxProducerIdx=0x500A0, TxConsumerIdx=0x500A4,
375 CompletionHiAddr=0x500B4, TxCompletionAddr=0x500B8,
376 RxCompletionAddr=0x500BC, RxCompletionQ2Addr=0x500C0,
377 CompletionQConsumerIdx=0x500C4, RxDMACtrl=0x500D0,
378 RxDescQCtrl=0x500D4, RxDescQHiAddr=0x500DC, RxDescQAddr=0x500E0,
379 RxDescQIdx=0x500E8, RxDMAStatus=0x500F0, RxFilterMode=0x500F4,
380 TxMode=0x55000, VlanType=0x55064,
381 PerfFilterTable=0x56000, HashTable=0x56100,
382 TxGfpMem=0x58000, RxGfpMem=0x5a000,
386 * Bits in the interrupt status/mask registers.
387 * Warning: setting Intr[Ab]NormalSummary in the IntrEnable register
388 * enables all the interrupt sources that are or'ed into those status bits.
390 enum intr_status_bits {
391 IntrLinkChange=0xf0000000, IntrStatsMax=0x08000000,
392 IntrAbnormalSummary=0x02000000, IntrGeneralTimer=0x01000000,
393 IntrSoftware=0x800000, IntrRxComplQ1Low=0x400000,
394 IntrTxComplQLow=0x200000, IntrPCI=0x100000,
395 IntrDMAErr=0x080000, IntrTxDataLow=0x040000,
396 IntrRxComplQ2Low=0x020000, IntrRxDescQ1Low=0x010000,
397 IntrNormalSummary=0x8000, IntrTxDone=0x4000,
398 IntrTxDMADone=0x2000, IntrTxEmpty=0x1000,
399 IntrEarlyRxQ2=0x0800, IntrEarlyRxQ1=0x0400,
400 IntrRxQ2Done=0x0200, IntrRxQ1Done=0x0100,
401 IntrRxGFPDead=0x80, IntrRxDescQ2Low=0x40,
402 IntrNoTxCsum=0x20, IntrTxBadID=0x10,
403 IntrHiPriTxBadID=0x08, IntrRxGfp=0x04,
404 IntrTxGfp=0x02, IntrPCIPad=0x01,
406 IntrRxDone=IntrRxQ2Done | IntrRxQ1Done,
407 IntrRxEmpty=IntrRxDescQ1Low | IntrRxDescQ2Low,
408 IntrNormalMask=0xff00, IntrAbnormalMask=0x3ff00fe,
411 /* Bits in the RxFilterMode register. */
413 AcceptBroadcast=0x04, AcceptAllMulticast=0x02, AcceptAll=0x01,
414 AcceptMulticast=0x10, PerfectFilter=0x40, HashFilter=0x30,
415 PerfectFilterVlan=0x80, MinVLANPrio=0xE000, VlanMode=0x0200,
419 /* Bits in the TxMode register */
421 MiiSoftReset=0x8000, MIILoopback=0x4000,
422 TxFlowEnable=0x0800, RxFlowEnable=0x0400,
423 PadEnable=0x04, FullDuplex=0x02, HugeFrame=0x01,
426 /* Bits in the TxDescCtrl register. */
428 TxDescSpaceUnlim=0x00, TxDescSpace32=0x10, TxDescSpace64=0x20,
429 TxDescSpace128=0x30, TxDescSpace256=0x40,
430 TxDescType0=0x00, TxDescType1=0x01, TxDescType2=0x02,
431 TxDescType3=0x03, TxDescType4=0x04,
432 TxNoDMACompletion=0x08,
433 TxDescQAddr64bit=0x80, TxDescQAddr32bit=0,
434 TxHiPriFIFOThreshShift=24, TxPadLenShift=16,
435 TxDMABurstSizeShift=8,
438 /* Bits in the RxDescQCtrl register. */
440 RxBufferLenShift=16, RxMinDescrThreshShift=0,
441 RxPrefetchMode=0x8000, RxVariableQ=0x2000,
442 Rx2048QEntries=0x4000, Rx256QEntries=0,
443 RxDescAddr64bit=0x1000, RxDescAddr32bit=0,
444 RxDescQAddr64bit=0x0100, RxDescQAddr32bit=0,
445 RxDescSpace4=0x000, RxDescSpace8=0x100,
446 RxDescSpace16=0x200, RxDescSpace32=0x300,
447 RxDescSpace64=0x400, RxDescSpace128=0x500,
451 /* Bits in the RxDMACtrl register. */
452 enum rx_dmactrl_bits {
453 RxReportBadFrames=0x80000000, RxDMAShortFrames=0x40000000,
454 RxDMABadFrames=0x20000000, RxDMACrcErrorFrames=0x10000000,
455 RxDMAControlFrame=0x08000000, RxDMAPauseFrame=0x04000000,
456 RxChecksumIgnore=0, RxChecksumRejectTCPUDP=0x02000000,
457 RxChecksumRejectTCPOnly=0x01000000,
458 RxCompletionQ2Enable=0x800000,
459 RxDMAQ2Disable=0, RxDMAQ2FPOnly=0x100000,
460 RxDMAQ2SmallPkt=0x200000, RxDMAQ2HighPrio=0x300000,
461 RxDMAQ2NonIP=0x400000,
462 RxUseBackupQueue=0x080000, RxDMACRC=0x040000,
463 RxEarlyIntThreshShift=12, RxHighPrioThreshShift=8,
467 /* Bits in the RxCompletionAddr register */
469 RxComplQAddr64bit=0x80, RxComplQAddr32bit=0,
470 RxComplProducerWrEn=0x40,
471 RxComplType0=0x00, RxComplType1=0x10,
472 RxComplType2=0x20, RxComplType3=0x30,
473 RxComplThreshShift=0,
476 /* Bits in the TxCompletionAddr register */
478 TxComplQAddr64bit=0x80, TxComplQAddr32bit=0,
479 TxComplProducerWrEn=0x40,
480 TxComplIntrStatus=0x20,
481 CommonQueueMode=0x10,
482 TxComplThreshShift=0,
485 /* Bits in the GenCtrl register */
487 RxEnable=0x05, TxEnable=0x0a,
488 RxGFPEnable=0x10, TxGFPEnable=0x20,
491 /* Bits in the IntrTimerCtrl register */
492 enum intr_ctrl_bits {
493 Timer10X=0x800, EnableIntrMasking=0x60, SmallFrameBypass=0x100,
494 SmallFrame64=0, SmallFrame128=0x200, SmallFrame256=0x400, SmallFrame512=0x600,
495 IntrLatencyMask=0x1f,
498 /* The Rx and Tx buffer descriptors. */
499 struct starfire_rx_desc {
503 RxDescValid=1, RxDescEndRing=2,
506 /* Completion queue entry. */
507 struct short_rx_done_desc {
508 u32 status; /* Low 16 bits is length. */
510 struct basic_rx_done_desc {
511 u32 status; /* Low 16 bits is length. */
515 struct csum_rx_done_desc {
516 u32 status; /* Low 16 bits is length. */
517 u16 csum; /* Partial checksum */
520 struct full_rx_done_desc {
521 u32 status; /* Low 16 bits is length. */
525 u16 csum; /* partial checksum */
528 /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
530 typedef struct full_rx_done_desc rx_done_desc;
531 #define RxComplType RxComplType3
532 #else /* not VLAN_SUPPORT */
533 typedef struct csum_rx_done_desc rx_done_desc;
534 #define RxComplType RxComplType2
535 #endif /* not VLAN_SUPPORT */
538 RxOK=0x20000000, RxFIFOErr=0x10000000, RxBufQ2=0x08000000,
541 /* Type 1 Tx descriptor. */
542 struct starfire_tx_desc_1 {
543 u32 status; /* Upper bits are status, lower 16 length. */
547 /* Type 2 Tx descriptor. */
548 struct starfire_tx_desc_2 {
549 u32 status; /* Upper bits are status, lower 16 length. */
555 typedef struct starfire_tx_desc_2 starfire_tx_desc;
556 #define TX_DESC_TYPE TxDescType2
557 #else /* not ADDR_64BITS */
558 typedef struct starfire_tx_desc_1 starfire_tx_desc;
559 #define TX_DESC_TYPE TxDescType1
560 #endif /* not ADDR_64BITS */
561 #define TX_DESC_SPACING TxDescSpaceUnlim
565 TxCRCEn=0x01000000, TxDescIntr=0x08000000,
566 TxRingWrap=0x04000000, TxCalTCP=0x02000000,
568 struct tx_done_desc {
569 u32 status; /* timestamp, index. */
571 u32 intrstatus; /* interrupt status */
575 struct rx_ring_info {
579 struct tx_ring_info {
582 unsigned int used_slots;
586 struct netdev_private {
587 /* Descriptor rings first for alignment. */
588 struct starfire_rx_desc *rx_ring;
589 starfire_tx_desc *tx_ring;
590 dma_addr_t rx_ring_dma;
591 dma_addr_t tx_ring_dma;
592 /* The addresses of rx/tx-in-place skbuffs. */
593 struct rx_ring_info rx_info[RX_RING_SIZE];
594 struct tx_ring_info tx_info[TX_RING_SIZE];
595 /* Pointers to completion queues (full pages). */
596 rx_done_desc *rx_done_q;
597 dma_addr_t rx_done_q_dma;
598 unsigned int rx_done;
599 struct tx_done_desc *tx_done_q;
600 dma_addr_t tx_done_q_dma;
601 unsigned int tx_done;
602 struct net_device_stats stats;
603 struct pci_dev *pci_dev;
605 struct vlan_group *vlgrp;
608 dma_addr_t queue_mem_dma;
609 size_t queue_mem_size;
611 /* Frequently used values: keep some adjacent for cache effect. */
613 unsigned int cur_rx, dirty_rx; /* Producer/consumer ring indices */
614 unsigned int cur_tx, dirty_tx, reap_tx;
615 unsigned int rx_buf_sz; /* Based on MTU+slack. */
616 /* These values keep track of the transceiver/media in use. */
617 int speed100; /* Set if speed == 100MBit. */
621 /* MII transceiver section. */
622 struct mii_if_info mii_if; /* MII lib hooks/info */
623 int phy_cnt; /* MII device addresses. */
624 unsigned char phys[PHY_CNT]; /* MII device addresses. */
629 static int mdio_read(struct net_device *dev, int phy_id, int location);
630 static void mdio_write(struct net_device *dev, int phy_id, int location, int value);
631 static int netdev_open(struct net_device *dev);
632 static void check_duplex(struct net_device *dev);
633 static void tx_timeout(struct net_device *dev);
634 static void init_ring(struct net_device *dev);
635 static int start_tx(struct sk_buff *skb, struct net_device *dev);
636 static irqreturn_t intr_handler(int irq, void *dev_instance);
637 static void netdev_error(struct net_device *dev, int intr_status);
638 static int __netdev_rx(struct net_device *dev, int *quota);
639 static void refill_rx_ring(struct net_device *dev);
640 static void netdev_error(struct net_device *dev, int intr_status);
641 static void set_rx_mode(struct net_device *dev);
642 static struct net_device_stats *get_stats(struct net_device *dev);
643 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
644 static int netdev_close(struct net_device *dev);
645 static void netdev_media_change(struct net_device *dev);
646 static const struct ethtool_ops ethtool_ops;
650 static void netdev_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
652 struct netdev_private *np = netdev_priv(dev);
654 spin_lock(&np->lock);
656 printk("%s: Setting vlgrp to %p\n", dev->name, grp);
659 spin_unlock(&np->lock);
662 static void netdev_vlan_rx_add_vid(struct net_device *dev, unsigned short vid)
664 struct netdev_private *np = netdev_priv(dev);
666 spin_lock(&np->lock);
668 printk("%s: Adding vlanid %d to vlan filter\n", dev->name, vid);
670 spin_unlock(&np->lock);
673 static void netdev_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
675 struct netdev_private *np = netdev_priv(dev);
677 spin_lock(&np->lock);
679 printk("%s: removing vlanid %d from vlan filter\n", dev->name, vid);
680 vlan_group_set_device(np->vlgrp, vid, NULL);
682 spin_unlock(&np->lock);
684 #endif /* VLAN_SUPPORT */
687 static int __devinit starfire_init_one(struct pci_dev *pdev,
688 const struct pci_device_id *ent)
690 struct netdev_private *np;
691 int i, irq, option, chip_idx = ent->driver_data;
692 struct net_device *dev;
693 static int card_idx = -1;
696 int drv_flags, io_size;
699 /* when built into the kernel, we only print version if device is found */
701 static int printed_version;
702 if (!printed_version++)
708 if (pci_enable_device (pdev))
711 ioaddr = pci_resource_start(pdev, 0);
712 io_size = pci_resource_len(pdev, 0);
713 if (!ioaddr || ((pci_resource_flags(pdev, 0) & IORESOURCE_MEM) == 0)) {
714 printk(KERN_ERR DRV_NAME " %d: no PCI MEM resources, aborting\n", card_idx);
718 dev = alloc_etherdev(sizeof(*np));
720 printk(KERN_ERR DRV_NAME " %d: cannot alloc etherdev, aborting\n", card_idx);
723 SET_MODULE_OWNER(dev);
724 SET_NETDEV_DEV(dev, &pdev->dev);
728 if (pci_request_regions (pdev, DRV_NAME)) {
729 printk(KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", card_idx);
730 goto err_out_free_netdev;
733 base = ioremap(ioaddr, io_size);
735 printk(KERN_ERR DRV_NAME " %d: cannot remap %#x @ %#lx, aborting\n",
736 card_idx, io_size, ioaddr);
737 goto err_out_free_res;
740 pci_set_master(pdev);
742 /* enable MWI -- it vastly improves Rx performance on sparc64 */
743 pci_try_set_mwi(pdev);
746 /* Starfire can do TCP/UDP checksumming */
748 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
749 #endif /* ZEROCOPY */
751 dev->features |= NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER;
752 dev->vlan_rx_register = netdev_vlan_rx_register;
753 dev->vlan_rx_add_vid = netdev_vlan_rx_add_vid;
754 dev->vlan_rx_kill_vid = netdev_vlan_rx_kill_vid;
755 #endif /* VLAN_RX_KILL_VID */
757 dev->features |= NETIF_F_HIGHDMA;
758 #endif /* ADDR_64BITS */
760 /* Serial EEPROM reads are hidden by the hardware. */
761 for (i = 0; i < 6; i++)
762 dev->dev_addr[i] = readb(base + EEPROMCtrl + 20 - i);
764 #if ! defined(final_version) /* Dump the EEPROM contents during development. */
766 for (i = 0; i < 0x20; i++)
768 (unsigned int)readb(base + EEPROMCtrl + i),
769 i % 16 != 15 ? " " : "\n");
772 /* Issue soft reset */
773 writel(MiiSoftReset, base + TxMode);
775 writel(0, base + TxMode);
777 /* Reset the chip to erase previous misconfiguration. */
778 writel(1, base + PCIDeviceConfig);
780 while (--boguscnt > 0) {
782 if ((readl(base + PCIDeviceConfig) & 1) == 0)
786 printk("%s: chipset reset never completed!\n", dev->name);
787 /* wait a little longer */
790 dev->base_addr = (unsigned long)base;
793 np = netdev_priv(dev);
795 spin_lock_init(&np->lock);
796 pci_set_drvdata(pdev, dev);
800 np->mii_if.dev = dev;
801 np->mii_if.mdio_read = mdio_read;
802 np->mii_if.mdio_write = mdio_write;
803 np->mii_if.phy_id_mask = 0x1f;
804 np->mii_if.reg_num_mask = 0x1f;
806 drv_flags = netdrv_tbl[chip_idx].drv_flags;
808 option = card_idx < MAX_UNITS ? options[card_idx] : 0;
810 option = dev->mem_start;
812 /* The lower four bits are the media type. */
814 np->mii_if.full_duplex = 1;
816 if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0)
817 np->mii_if.full_duplex = 1;
819 if (np->mii_if.full_duplex)
820 np->mii_if.force_media = 1;
822 np->mii_if.force_media = 0;
825 /* timer resolution is 128 * 0.8us */
826 np->intr_timer_ctrl = (((intr_latency * 10) / 1024) & IntrLatencyMask) |
827 Timer10X | EnableIntrMasking;
829 if (small_frames > 0) {
830 np->intr_timer_ctrl |= SmallFrameBypass;
831 switch (small_frames) {
833 np->intr_timer_ctrl |= SmallFrame64;
836 np->intr_timer_ctrl |= SmallFrame128;
839 np->intr_timer_ctrl |= SmallFrame256;
842 np->intr_timer_ctrl |= SmallFrame512;
843 if (small_frames > 512)
844 printk("Adjusting small_frames down to 512\n");
849 /* The chip-specific entries in the device structure. */
850 dev->open = &netdev_open;
851 dev->hard_start_xmit = &start_tx;
852 dev->tx_timeout = tx_timeout;
853 dev->watchdog_timeo = TX_TIMEOUT;
855 dev->stop = &netdev_close;
856 dev->get_stats = &get_stats;
857 dev->set_multicast_list = &set_rx_mode;
858 dev->do_ioctl = &netdev_ioctl;
859 SET_ETHTOOL_OPS(dev, ðtool_ops);
864 if (register_netdev(dev))
865 goto err_out_cleardev;
867 printk(KERN_INFO "%s: %s at %p, ",
868 dev->name, netdrv_tbl[chip_idx].name, base);
869 for (i = 0; i < 5; i++)
870 printk("%2.2x:", dev->dev_addr[i]);
871 printk("%2.2x, IRQ %d.\n", dev->dev_addr[i], irq);
873 if (drv_flags & CanHaveMII) {
874 int phy, phy_idx = 0;
876 for (phy = 0; phy < 32 && phy_idx < PHY_CNT; phy++) {
877 mdio_write(dev, phy, MII_BMCR, BMCR_RESET);
880 while (--boguscnt > 0)
881 if ((mdio_read(dev, phy, MII_BMCR) & BMCR_RESET) == 0)
884 printk("%s: PHY#%d reset never completed!\n", dev->name, phy);
887 mii_status = mdio_read(dev, phy, MII_BMSR);
888 if (mii_status != 0) {
889 np->phys[phy_idx++] = phy;
890 np->mii_if.advertising = mdio_read(dev, phy, MII_ADVERTISE);
891 printk(KERN_INFO "%s: MII PHY found at address %d, status "
892 "%#4.4x advertising %#4.4x.\n",
893 dev->name, phy, mii_status, np->mii_if.advertising);
894 /* there can be only one PHY on-board */
898 np->phy_cnt = phy_idx;
900 np->mii_if.phy_id = np->phys[0];
902 memset(&np->mii_if, 0, sizeof(np->mii_if));
905 printk(KERN_INFO "%s: scatter-gather and hardware TCP cksumming %s.\n",
906 dev->name, enable_hw_cksum ? "enabled" : "disabled");
910 pci_set_drvdata(pdev, NULL);
913 pci_release_regions (pdev);
920 /* Read the MII Management Data I/O (MDIO) interfaces. */
921 static int mdio_read(struct net_device *dev, int phy_id, int location)
923 struct netdev_private *np = netdev_priv(dev);
924 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
925 int result, boguscnt=1000;
926 /* ??? Should we add a busy-wait here? */
928 result = readl(mdio_addr);
929 while ((result & 0xC0000000) != 0x80000000 && --boguscnt > 0);
932 if ((result & 0xffff) == 0xffff)
934 return result & 0xffff;
938 static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
940 struct netdev_private *np = netdev_priv(dev);
941 void __iomem *mdio_addr = np->base + MIICtrl + (phy_id<<7) + (location<<2);
942 writel(value, mdio_addr);
943 /* The busy-wait will occur before a read. */
947 static int netdev_open(struct net_device *dev)
949 struct netdev_private *np = netdev_priv(dev);
950 void __iomem *ioaddr = np->base;
952 size_t tx_done_q_size, rx_done_q_size, tx_ring_size, rx_ring_size;
954 /* Do we ever need to reset the chip??? */
956 retval = request_irq(dev->irq, &intr_handler, IRQF_SHARED, dev->name, dev);
960 /* Disable the Rx and Tx, and reset the chip. */
961 writel(0, ioaddr + GenCtrl);
962 writel(1, ioaddr + PCIDeviceConfig);
964 printk(KERN_DEBUG "%s: netdev_open() irq %d.\n",
965 dev->name, dev->irq);
967 /* Allocate the various queues. */
968 if (np->queue_mem == 0) {
969 tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
970 rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
971 tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
972 rx_ring_size = sizeof(struct starfire_rx_desc) * RX_RING_SIZE;
973 np->queue_mem_size = tx_done_q_size + rx_done_q_size + tx_ring_size + rx_ring_size;
974 np->queue_mem = pci_alloc_consistent(np->pci_dev, np->queue_mem_size, &np->queue_mem_dma);
975 if (np->queue_mem == NULL) {
976 free_irq(dev->irq, dev);
980 np->tx_done_q = np->queue_mem;
981 np->tx_done_q_dma = np->queue_mem_dma;
982 np->rx_done_q = (void *) np->tx_done_q + tx_done_q_size;
983 np->rx_done_q_dma = np->tx_done_q_dma + tx_done_q_size;
984 np->tx_ring = (void *) np->rx_done_q + rx_done_q_size;
985 np->tx_ring_dma = np->rx_done_q_dma + rx_done_q_size;
986 np->rx_ring = (void *) np->tx_ring + tx_ring_size;
987 np->rx_ring_dma = np->tx_ring_dma + tx_ring_size;
990 /* Start with no carrier, it gets adjusted later */
991 netif_carrier_off(dev);
993 /* Set the size of the Rx buffers. */
994 writel((np->rx_buf_sz << RxBufferLenShift) |
995 (0 << RxMinDescrThreshShift) |
996 RxPrefetchMode | RxVariableQ |
998 RX_DESC_Q_ADDR_SIZE | RX_DESC_ADDR_SIZE |
1000 ioaddr + RxDescQCtrl);
1002 /* Set up the Rx DMA controller. */
1003 writel(RxChecksumIgnore |
1004 (0 << RxEarlyIntThreshShift) |
1005 (6 << RxHighPrioThreshShift) |
1006 ((DMA_BURST_SIZE / 32) << RxBurstSizeShift),
1007 ioaddr + RxDMACtrl);
1009 /* Set Tx descriptor */
1010 writel((2 << TxHiPriFIFOThreshShift) |
1011 (0 << TxPadLenShift) |
1012 ((DMA_BURST_SIZE / 32) << TxDMABurstSizeShift) |
1013 TX_DESC_Q_ADDR_SIZE |
1014 TX_DESC_SPACING | TX_DESC_TYPE,
1015 ioaddr + TxDescCtrl);
1017 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + RxDescQHiAddr);
1018 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + TxRingHiAddr);
1019 writel( (np->queue_mem_dma >> 16) >> 16, ioaddr + CompletionHiAddr);
1020 writel(np->rx_ring_dma, ioaddr + RxDescQAddr);
1021 writel(np->tx_ring_dma, ioaddr + TxRingPtr);
1023 writel(np->tx_done_q_dma, ioaddr + TxCompletionAddr);
1024 writel(np->rx_done_q_dma |
1026 (0 << RxComplThreshShift),
1027 ioaddr + RxCompletionAddr);
1030 printk(KERN_DEBUG "%s: Filling in the station address.\n", dev->name);
1032 /* Fill both the Tx SA register and the Rx perfect filter. */
1033 for (i = 0; i < 6; i++)
1034 writeb(dev->dev_addr[i], ioaddr + TxStationAddr + 5 - i);
1035 /* The first entry is special because it bypasses the VLAN filter.
1037 writew(0, ioaddr + PerfFilterTable);
1038 writew(0, ioaddr + PerfFilterTable + 4);
1039 writew(0, ioaddr + PerfFilterTable + 8);
1040 for (i = 1; i < 16; i++) {
1041 u16 *eaddrs = (u16 *)dev->dev_addr;
1042 void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
1043 writew(cpu_to_be16(eaddrs[2]), setup_frm); setup_frm += 4;
1044 writew(cpu_to_be16(eaddrs[1]), setup_frm); setup_frm += 4;
1045 writew(cpu_to_be16(eaddrs[0]), setup_frm); setup_frm += 8;
1048 /* Initialize other registers. */
1049 /* Configure the PCI bus bursts and FIFO thresholds. */
1050 np->tx_mode = TxFlowEnable|RxFlowEnable|PadEnable; /* modified when link is up. */
1051 writel(MiiSoftReset | np->tx_mode, ioaddr + TxMode);
1053 writel(np->tx_mode, ioaddr + TxMode);
1054 np->tx_threshold = 4;
1055 writel(np->tx_threshold, ioaddr + TxThreshold);
1057 writel(np->intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1059 netif_start_queue(dev);
1062 printk(KERN_DEBUG "%s: Setting the Rx and Tx modes.\n", dev->name);
1065 np->mii_if.advertising = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1068 /* Enable GPIO interrupts on link change */
1069 writel(0x0f00ff00, ioaddr + GPIOCtrl);
1071 /* Set the interrupt mask */
1072 writel(IntrRxDone | IntrRxEmpty | IntrDMAErr |
1073 IntrTxDMADone | IntrStatsMax | IntrLinkChange |
1074 IntrRxGFPDead | IntrNoTxCsum | IntrTxBadID,
1075 ioaddr + IntrEnable);
1076 /* Enable PCI interrupts. */
1077 writel(0x00800000 | readl(ioaddr + PCIDeviceConfig),
1078 ioaddr + PCIDeviceConfig);
1081 /* Set VLAN type to 802.1q */
1082 writel(ETH_P_8021Q, ioaddr + VlanType);
1083 #endif /* VLAN_SUPPORT */
1085 /* Load Rx/Tx firmware into the frame processors */
1086 for (i = 0; i < FIRMWARE_RX_SIZE * 2; i++)
1087 writel(firmware_rx[i], ioaddr + RxGfpMem + i * 4);
1088 for (i = 0; i < FIRMWARE_TX_SIZE * 2; i++)
1089 writel(firmware_tx[i], ioaddr + TxGfpMem + i * 4);
1090 if (enable_hw_cksum)
1091 /* Enable the Rx and Tx units, and the Rx/Tx frame processors. */
1092 writel(TxEnable|TxGFPEnable|RxEnable|RxGFPEnable, ioaddr + GenCtrl);
1094 /* Enable the Rx and Tx units only. */
1095 writel(TxEnable|RxEnable, ioaddr + GenCtrl);
1098 printk(KERN_DEBUG "%s: Done netdev_open().\n",
1105 static void check_duplex(struct net_device *dev)
1107 struct netdev_private *np = netdev_priv(dev);
1109 int silly_count = 1000;
1111 mdio_write(dev, np->phys[0], MII_ADVERTISE, np->mii_if.advertising);
1112 mdio_write(dev, np->phys[0], MII_BMCR, BMCR_RESET);
1114 while (--silly_count && mdio_read(dev, np->phys[0], MII_BMCR) & BMCR_RESET)
1117 printk("%s: MII reset failed!\n", dev->name);
1121 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1123 if (!np->mii_if.force_media) {
1124 reg0 |= BMCR_ANENABLE | BMCR_ANRESTART;
1126 reg0 &= ~(BMCR_ANENABLE | BMCR_ANRESTART);
1128 reg0 |= BMCR_SPEED100;
1129 if (np->mii_if.full_duplex)
1130 reg0 |= BMCR_FULLDPLX;
1131 printk(KERN_DEBUG "%s: Link forced to %sMbit %s-duplex\n",
1133 np->speed100 ? "100" : "10",
1134 np->mii_if.full_duplex ? "full" : "half");
1136 mdio_write(dev, np->phys[0], MII_BMCR, reg0);
1140 static void tx_timeout(struct net_device *dev)
1142 struct netdev_private *np = netdev_priv(dev);
1143 void __iomem *ioaddr = np->base;
1146 printk(KERN_WARNING "%s: Transmit timed out, status %#8.8x, "
1147 "resetting...\n", dev->name, (int) readl(ioaddr + IntrStatus));
1149 /* Perhaps we should reinitialize the hardware here. */
1152 * Stop and restart the interface.
1153 * Cheat and increase the debug level temporarily.
1161 /* Trigger an immediate transmit demand. */
1163 dev->trans_start = jiffies;
1164 np->stats.tx_errors++;
1165 netif_wake_queue(dev);
1169 /* Initialize the Rx and Tx rings, along with various 'dev' bits. */
1170 static void init_ring(struct net_device *dev)
1172 struct netdev_private *np = netdev_priv(dev);
1175 np->cur_rx = np->cur_tx = np->reap_tx = 0;
1176 np->dirty_rx = np->dirty_tx = np->rx_done = np->tx_done = 0;
1178 np->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32);
1180 /* Fill in the Rx buffers. Handle allocation failure gracefully. */
1181 for (i = 0; i < RX_RING_SIZE; i++) {
1182 struct sk_buff *skb = dev_alloc_skb(np->rx_buf_sz);
1183 np->rx_info[i].skb = skb;
1186 np->rx_info[i].mapping = pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1187 skb->dev = dev; /* Mark as being used by this device. */
1188 /* Grrr, we cannot offset to correctly align the IP header. */
1189 np->rx_ring[i].rxaddr = cpu_to_dma(np->rx_info[i].mapping | RxDescValid);
1191 writew(i - 1, np->base + RxDescQIdx);
1192 np->dirty_rx = (unsigned int)(i - RX_RING_SIZE);
1194 /* Clear the remainder of the Rx buffer ring. */
1195 for ( ; i < RX_RING_SIZE; i++) {
1196 np->rx_ring[i].rxaddr = 0;
1197 np->rx_info[i].skb = NULL;
1198 np->rx_info[i].mapping = 0;
1200 /* Mark the last entry as wrapping the ring. */
1201 np->rx_ring[RX_RING_SIZE - 1].rxaddr |= cpu_to_dma(RxDescEndRing);
1203 /* Clear the completion rings. */
1204 for (i = 0; i < DONE_Q_SIZE; i++) {
1205 np->rx_done_q[i].status = 0;
1206 np->tx_done_q[i].status = 0;
1209 for (i = 0; i < TX_RING_SIZE; i++)
1210 memset(&np->tx_info[i], 0, sizeof(np->tx_info[i]));
1216 static int start_tx(struct sk_buff *skb, struct net_device *dev)
1218 struct netdev_private *np = netdev_priv(dev);
1224 * be cautious here, wrapping the queue has weird semantics
1225 * and we may not have enough slots even when it seems we do.
1227 if ((np->cur_tx - np->dirty_tx) + skb_num_frags(skb) * 2 > TX_RING_SIZE) {
1228 netif_stop_queue(dev);
1232 #if defined(ZEROCOPY) && defined(HAS_BROKEN_FIRMWARE)
1233 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1234 if (skb_padto(skb, (skb->len + PADDING_MASK) & ~PADDING_MASK))
1235 return NETDEV_TX_OK;
1237 #endif /* ZEROCOPY && HAS_BROKEN_FIRMWARE */
1239 entry = np->cur_tx % TX_RING_SIZE;
1240 for (i = 0; i < skb_num_frags(skb); i++) {
1245 np->tx_info[entry].skb = skb;
1247 if (entry >= TX_RING_SIZE - skb_num_frags(skb)) {
1248 status |= TxRingWrap;
1252 status |= TxDescIntr;
1255 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1257 np->stats.tx_compressed++;
1259 status |= skb_first_frag_len(skb) | (skb_num_frags(skb) << 16);
1261 np->tx_info[entry].mapping =
1262 pci_map_single(np->pci_dev, skb->data, skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1264 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[i - 1];
1265 status |= this_frag->size;
1266 np->tx_info[entry].mapping =
1267 pci_map_single(np->pci_dev, page_address(this_frag->page) + this_frag->page_offset, this_frag->size, PCI_DMA_TODEVICE);
1270 np->tx_ring[entry].addr = cpu_to_dma(np->tx_info[entry].mapping);
1271 np->tx_ring[entry].status = cpu_to_le32(status);
1273 printk(KERN_DEBUG "%s: Tx #%d/#%d slot %d status %#8.8x.\n",
1274 dev->name, np->cur_tx, np->dirty_tx,
1277 np->tx_info[entry].used_slots = TX_RING_SIZE - entry;
1278 np->cur_tx += np->tx_info[entry].used_slots;
1281 np->tx_info[entry].used_slots = 1;
1282 np->cur_tx += np->tx_info[entry].used_slots;
1285 /* scavenge the tx descriptors twice per TX_RING_SIZE */
1286 if (np->cur_tx % (TX_RING_SIZE / 2) == 0)
1290 /* Non-x86: explicitly flush descriptor cache lines here. */
1291 /* Ensure all descriptors are written back before the transmit is
1295 /* Update the producer index. */
1296 writel(entry * (sizeof(starfire_tx_desc) / 8), np->base + TxProducerIdx);
1298 /* 4 is arbitrary, but should be ok */
1299 if ((np->cur_tx - np->dirty_tx) + 4 > TX_RING_SIZE)
1300 netif_stop_queue(dev);
1302 dev->trans_start = jiffies;
1308 /* The interrupt handler does all of the Rx thread work and cleans up
1309 after the Tx thread. */
1310 static irqreturn_t intr_handler(int irq, void *dev_instance)
1312 struct net_device *dev = dev_instance;
1313 struct netdev_private *np = netdev_priv(dev);
1314 void __iomem *ioaddr = np->base;
1315 int boguscnt = max_interrupt_work;
1321 u32 intr_status = readl(ioaddr + IntrClear);
1324 printk(KERN_DEBUG "%s: Interrupt status %#8.8x.\n",
1325 dev->name, intr_status);
1327 if (intr_status == 0 || intr_status == (u32) -1)
1332 if (intr_status & (IntrRxDone | IntrRxEmpty))
1333 netdev_rx(dev, ioaddr);
1335 /* Scavenge the skbuff list based on the Tx-done queue.
1336 There are redundant checks here that may be cleaned up
1337 after the driver has proven to be reliable. */
1338 consumer = readl(ioaddr + TxConsumerIdx);
1340 printk(KERN_DEBUG "%s: Tx Consumer index is %d.\n",
1341 dev->name, consumer);
1343 while ((tx_status = le32_to_cpu(np->tx_done_q[np->tx_done].status)) != 0) {
1345 printk(KERN_DEBUG "%s: Tx completion #%d entry %d is %#8.8x.\n",
1346 dev->name, np->dirty_tx, np->tx_done, tx_status);
1347 if ((tx_status & 0xe0000000) == 0xa0000000) {
1348 np->stats.tx_packets++;
1349 } else if ((tx_status & 0xe0000000) == 0x80000000) {
1350 u16 entry = (tx_status & 0x7fff) / sizeof(starfire_tx_desc);
1351 struct sk_buff *skb = np->tx_info[entry].skb;
1352 np->tx_info[entry].skb = NULL;
1353 pci_unmap_single(np->pci_dev,
1354 np->tx_info[entry].mapping,
1355 skb_first_frag_len(skb),
1357 np->tx_info[entry].mapping = 0;
1358 np->dirty_tx += np->tx_info[entry].used_slots;
1359 entry = (entry + np->tx_info[entry].used_slots) % TX_RING_SIZE;
1362 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1363 pci_unmap_single(np->pci_dev,
1364 np->tx_info[entry].mapping,
1365 skb_shinfo(skb)->frags[i].size,
1372 dev_kfree_skb_irq(skb);
1374 np->tx_done_q[np->tx_done].status = 0;
1375 np->tx_done = (np->tx_done + 1) % DONE_Q_SIZE;
1377 writew(np->tx_done, ioaddr + CompletionQConsumerIdx + 2);
1379 if (netif_queue_stopped(dev) &&
1380 (np->cur_tx - np->dirty_tx + 4 < TX_RING_SIZE)) {
1381 /* The ring is no longer full, wake the queue. */
1382 netif_wake_queue(dev);
1385 /* Stats overflow */
1386 if (intr_status & IntrStatsMax)
1389 /* Media change interrupt. */
1390 if (intr_status & IntrLinkChange)
1391 netdev_media_change(dev);
1393 /* Abnormal error summary/uncommon events handlers. */
1394 if (intr_status & IntrAbnormalSummary)
1395 netdev_error(dev, intr_status);
1397 if (--boguscnt < 0) {
1399 printk(KERN_WARNING "%s: Too much work at interrupt, "
1401 dev->name, intr_status);
1407 printk(KERN_DEBUG "%s: exiting interrupt, status=%#8.8x.\n",
1408 dev->name, (int) readl(ioaddr + IntrStatus));
1409 return IRQ_RETVAL(handled);
1413 /* This routine is logically part of the interrupt/poll handler, but separated
1414 for clarity, code sharing between NAPI/non-NAPI, and better register allocation. */
1415 static int __netdev_rx(struct net_device *dev, int *quota)
1417 struct netdev_private *np = netdev_priv(dev);
1421 /* If EOP is set on the next entry, it's a new packet. Send it up. */
1422 while ((desc_status = le32_to_cpu(np->rx_done_q[np->rx_done].status)) != 0) {
1423 struct sk_buff *skb;
1426 rx_done_desc *desc = &np->rx_done_q[np->rx_done];
1429 printk(KERN_DEBUG " netdev_rx() status of %d was %#8.8x.\n", np->rx_done, desc_status);
1430 if (!(desc_status & RxOK)) {
1431 /* There was an error. */
1433 printk(KERN_DEBUG " netdev_rx() Rx error was %#8.8x.\n", desc_status);
1434 np->stats.rx_errors++;
1435 if (desc_status & RxFIFOErr)
1436 np->stats.rx_fifo_errors++;
1440 if (*quota <= 0) { /* out of rx quota */
1446 pkt_len = desc_status; /* Implicitly Truncate */
1447 entry = (desc_status >> 16) & 0x7ff;
1450 printk(KERN_DEBUG " netdev_rx() normal Rx pkt length %d, quota %d.\n", pkt_len, *quota);
1451 /* Check if the packet is long enough to accept without copying
1452 to a minimally-sized skbuff. */
1453 if (pkt_len < rx_copybreak
1454 && (skb = dev_alloc_skb(pkt_len + 2)) != NULL) {
1455 skb_reserve(skb, 2); /* 16 byte align the IP header */
1456 pci_dma_sync_single_for_cpu(np->pci_dev,
1457 np->rx_info[entry].mapping,
1458 pkt_len, PCI_DMA_FROMDEVICE);
1459 skb_copy_to_linear_data(skb, np->rx_info[entry].skb->data, pkt_len);
1460 pci_dma_sync_single_for_device(np->pci_dev,
1461 np->rx_info[entry].mapping,
1462 pkt_len, PCI_DMA_FROMDEVICE);
1463 skb_put(skb, pkt_len);
1465 pci_unmap_single(np->pci_dev, np->rx_info[entry].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1466 skb = np->rx_info[entry].skb;
1467 skb_put(skb, pkt_len);
1468 np->rx_info[entry].skb = NULL;
1469 np->rx_info[entry].mapping = 0;
1471 #ifndef final_version /* Remove after testing. */
1472 /* You will want this info for the initial debug. */
1474 printk(KERN_DEBUG " Rx data %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:"
1475 "%2.2x %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x %2.2x%2.2x.\n",
1476 skb->data[0], skb->data[1], skb->data[2], skb->data[3],
1477 skb->data[4], skb->data[5], skb->data[6], skb->data[7],
1478 skb->data[8], skb->data[9], skb->data[10],
1479 skb->data[11], skb->data[12], skb->data[13]);
1482 skb->protocol = eth_type_trans(skb, dev);
1485 printk(KERN_DEBUG " netdev_rx() status2 of %d was %#4.4x.\n", np->rx_done, le16_to_cpu(desc->status2));
1487 if (le16_to_cpu(desc->status2) & 0x0100) {
1488 skb->ip_summed = CHECKSUM_UNNECESSARY;
1489 np->stats.rx_compressed++;
1492 * This feature doesn't seem to be working, at least
1493 * with the two firmware versions I have. If the GFP sees
1494 * an IP fragment, it either ignores it completely, or reports
1495 * "bad checksum" on it.
1497 * Maybe I missed something -- corrections are welcome.
1498 * Until then, the printk stays. :-) -Ion
1500 else if (le16_to_cpu(desc->status2) & 0x0040) {
1501 skb->ip_summed = CHECKSUM_COMPLETE;
1502 skb->csum = le16_to_cpu(desc->csum);
1503 printk(KERN_DEBUG "%s: checksum_hw, status2 = %#x\n", dev->name, le16_to_cpu(desc->status2));
1506 if (np->vlgrp && le16_to_cpu(desc->status2) & 0x0200) {
1508 printk(KERN_DEBUG " netdev_rx() vlanid = %d\n", le16_to_cpu(desc->vlanid));
1509 /* vlan_netdev_receive_skb() expects a packet with the VLAN tag stripped out */
1510 vlan_netdev_receive_skb(skb, np->vlgrp, le16_to_cpu(desc->vlanid) & VLAN_VID_MASK);
1512 #endif /* VLAN_SUPPORT */
1513 netdev_receive_skb(skb);
1514 dev->last_rx = jiffies;
1515 np->stats.rx_packets++;
1520 np->rx_done = (np->rx_done + 1) % DONE_Q_SIZE;
1522 writew(np->rx_done, np->base + CompletionQConsumerIdx);
1525 refill_rx_ring(dev);
1527 printk(KERN_DEBUG " exiting netdev_rx(): %d, status of %d was %#8.8x.\n",
1528 retcode, np->rx_done, desc_status);
1533 #ifdef HAVE_NETDEV_POLL
1534 static int netdev_poll(struct net_device *dev, int *budget)
1537 struct netdev_private *np = netdev_priv(dev);
1538 void __iomem *ioaddr = np->base;
1539 int retcode = 0, quota = dev->quota;
1542 writel(IntrRxDone | IntrRxEmpty, ioaddr + IntrClear);
1544 retcode = __netdev_rx(dev, "a);
1545 *budget -= (dev->quota - quota);
1550 intr_status = readl(ioaddr + IntrStatus);
1551 } while (intr_status & (IntrRxDone | IntrRxEmpty));
1553 netif_rx_complete(dev);
1554 intr_status = readl(ioaddr + IntrEnable);
1555 intr_status |= IntrRxDone | IntrRxEmpty;
1556 writel(intr_status, ioaddr + IntrEnable);
1560 printk(KERN_DEBUG " exiting netdev_poll(): %d.\n", retcode);
1562 /* Restart Rx engine if stopped. */
1565 #endif /* HAVE_NETDEV_POLL */
1568 static void refill_rx_ring(struct net_device *dev)
1570 struct netdev_private *np = netdev_priv(dev);
1571 struct sk_buff *skb;
1574 /* Refill the Rx ring buffers. */
1575 for (; np->cur_rx - np->dirty_rx > 0; np->dirty_rx++) {
1576 entry = np->dirty_rx % RX_RING_SIZE;
1577 if (np->rx_info[entry].skb == NULL) {
1578 skb = dev_alloc_skb(np->rx_buf_sz);
1579 np->rx_info[entry].skb = skb;
1581 break; /* Better luck next round. */
1582 np->rx_info[entry].mapping =
1583 pci_map_single(np->pci_dev, skb->data, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1584 skb->dev = dev; /* Mark as being used by this device. */
1585 np->rx_ring[entry].rxaddr =
1586 cpu_to_dma(np->rx_info[entry].mapping | RxDescValid);
1588 if (entry == RX_RING_SIZE - 1)
1589 np->rx_ring[entry].rxaddr |= cpu_to_dma(RxDescEndRing);
1592 writew(entry, np->base + RxDescQIdx);
1596 static void netdev_media_change(struct net_device *dev)
1598 struct netdev_private *np = netdev_priv(dev);
1599 void __iomem *ioaddr = np->base;
1600 u16 reg0, reg1, reg4, reg5;
1602 u32 new_intr_timer_ctrl;
1604 /* reset status first */
1605 mdio_read(dev, np->phys[0], MII_BMCR);
1606 mdio_read(dev, np->phys[0], MII_BMSR);
1608 reg0 = mdio_read(dev, np->phys[0], MII_BMCR);
1609 reg1 = mdio_read(dev, np->phys[0], MII_BMSR);
1611 if (reg1 & BMSR_LSTATUS) {
1613 if (reg0 & BMCR_ANENABLE) {
1614 /* autonegotiation is enabled */
1615 reg4 = mdio_read(dev, np->phys[0], MII_ADVERTISE);
1616 reg5 = mdio_read(dev, np->phys[0], MII_LPA);
1617 if (reg4 & ADVERTISE_100FULL && reg5 & LPA_100FULL) {
1619 np->mii_if.full_duplex = 1;
1620 } else if (reg4 & ADVERTISE_100HALF && reg5 & LPA_100HALF) {
1622 np->mii_if.full_duplex = 0;
1623 } else if (reg4 & ADVERTISE_10FULL && reg5 & LPA_10FULL) {
1625 np->mii_if.full_duplex = 1;
1628 np->mii_if.full_duplex = 0;
1631 /* autonegotiation is disabled */
1632 if (reg0 & BMCR_SPEED100)
1636 if (reg0 & BMCR_FULLDPLX)
1637 np->mii_if.full_duplex = 1;
1639 np->mii_if.full_duplex = 0;
1641 netif_carrier_on(dev);
1642 printk(KERN_DEBUG "%s: Link is up, running at %sMbit %s-duplex\n",
1644 np->speed100 ? "100" : "10",
1645 np->mii_if.full_duplex ? "full" : "half");
1647 new_tx_mode = np->tx_mode & ~FullDuplex; /* duplex setting */
1648 if (np->mii_if.full_duplex)
1649 new_tx_mode |= FullDuplex;
1650 if (np->tx_mode != new_tx_mode) {
1651 np->tx_mode = new_tx_mode;
1652 writel(np->tx_mode | MiiSoftReset, ioaddr + TxMode);
1654 writel(np->tx_mode, ioaddr + TxMode);
1657 new_intr_timer_ctrl = np->intr_timer_ctrl & ~Timer10X;
1659 new_intr_timer_ctrl |= Timer10X;
1660 if (np->intr_timer_ctrl != new_intr_timer_ctrl) {
1661 np->intr_timer_ctrl = new_intr_timer_ctrl;
1662 writel(new_intr_timer_ctrl, ioaddr + IntrTimerCtrl);
1665 netif_carrier_off(dev);
1666 printk(KERN_DEBUG "%s: Link is down\n", dev->name);
1671 static void netdev_error(struct net_device *dev, int intr_status)
1673 struct netdev_private *np = netdev_priv(dev);
1675 /* Came close to underrunning the Tx FIFO, increase threshold. */
1676 if (intr_status & IntrTxDataLow) {
1677 if (np->tx_threshold <= PKT_BUF_SZ / 16) {
1678 writel(++np->tx_threshold, np->base + TxThreshold);
1679 printk(KERN_NOTICE "%s: PCI bus congestion, increasing Tx FIFO threshold to %d bytes\n",
1680 dev->name, np->tx_threshold * 16);
1682 printk(KERN_WARNING "%s: PCI Tx underflow -- adapter is probably malfunctioning\n", dev->name);
1684 if (intr_status & IntrRxGFPDead) {
1685 np->stats.rx_fifo_errors++;
1686 np->stats.rx_errors++;
1688 if (intr_status & (IntrNoTxCsum | IntrDMAErr)) {
1689 np->stats.tx_fifo_errors++;
1690 np->stats.tx_errors++;
1692 if ((intr_status & ~(IntrNormalMask | IntrAbnormalSummary | IntrLinkChange | IntrStatsMax | IntrTxDataLow | IntrRxGFPDead | IntrNoTxCsum | IntrPCIPad)) && debug)
1693 printk(KERN_ERR "%s: Something Wicked happened! %#8.8x.\n",
1694 dev->name, intr_status);
1698 static struct net_device_stats *get_stats(struct net_device *dev)
1700 struct netdev_private *np = netdev_priv(dev);
1701 void __iomem *ioaddr = np->base;
1703 /* This adapter architecture needs no SMP locks. */
1704 np->stats.tx_bytes = readl(ioaddr + 0x57010);
1705 np->stats.rx_bytes = readl(ioaddr + 0x57044);
1706 np->stats.tx_packets = readl(ioaddr + 0x57000);
1707 np->stats.tx_aborted_errors =
1708 readl(ioaddr + 0x57024) + readl(ioaddr + 0x57028);
1709 np->stats.tx_window_errors = readl(ioaddr + 0x57018);
1710 np->stats.collisions =
1711 readl(ioaddr + 0x57004) + readl(ioaddr + 0x57008);
1713 /* The chip only need report frame silently dropped. */
1714 np->stats.rx_dropped += readw(ioaddr + RxDMAStatus);
1715 writew(0, ioaddr + RxDMAStatus);
1716 np->stats.rx_crc_errors = readl(ioaddr + 0x5703C);
1717 np->stats.rx_frame_errors = readl(ioaddr + 0x57040);
1718 np->stats.rx_length_errors = readl(ioaddr + 0x57058);
1719 np->stats.rx_missed_errors = readl(ioaddr + 0x5707C);
1725 static void set_rx_mode(struct net_device *dev)
1727 struct netdev_private *np = netdev_priv(dev);
1728 void __iomem *ioaddr = np->base;
1729 u32 rx_mode = MinVLANPrio;
1730 struct dev_mc_list *mclist;
1734 rx_mode |= VlanMode;
1737 void __iomem *filter_addr = ioaddr + HashTable + 8;
1738 for (i = 0; i < VLAN_VID_MASK; i++) {
1739 if (vlan_group_get_device(np->vlgrp, i)) {
1740 if (vlan_count >= 32)
1742 writew(cpu_to_be16(i), filter_addr);
1747 if (i == VLAN_VID_MASK) {
1748 rx_mode |= PerfectFilterVlan;
1749 while (vlan_count < 32) {
1750 writew(0, filter_addr);
1756 #endif /* VLAN_SUPPORT */
1758 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */
1759 rx_mode |= AcceptAll;
1760 } else if ((dev->mc_count > multicast_filter_limit)
1761 || (dev->flags & IFF_ALLMULTI)) {
1762 /* Too many to match, or accept all multicasts. */
1763 rx_mode |= AcceptBroadcast|AcceptAllMulticast|PerfectFilter;
1764 } else if (dev->mc_count <= 14) {
1765 /* Use the 16 element perfect filter, skip first two entries. */
1766 void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1768 for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2;
1769 i++, mclist = mclist->next) {
1770 eaddrs = (u16 *)mclist->dmi_addr;
1771 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 4;
1772 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4;
1773 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 8;
1775 eaddrs = (u16 *)dev->dev_addr;
1777 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4;
1778 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4;
1779 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8;
1781 rx_mode |= AcceptBroadcast|PerfectFilter;
1783 /* Must use a multicast hash table. */
1784 void __iomem *filter_addr;
1786 u16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
1788 memset(mc_filter, 0, sizeof(mc_filter));
1789 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
1790 i++, mclist = mclist->next) {
1791 /* The chip uses the upper 9 CRC bits
1792 as index into the hash table */
1793 int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23;
1794 __u32 *fptr = (__u32 *) &mc_filter[(bit_nr >> 4) & ~1];
1796 *fptr |= cpu_to_le32(1 << (bit_nr & 31));
1798 /* Clear the perfect filter list, skip first two entries. */
1799 filter_addr = ioaddr + PerfFilterTable + 2 * 16;
1800 eaddrs = (u16 *)dev->dev_addr;
1801 for (i = 2; i < 16; i++) {
1802 writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4;
1803 writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4;
1804 writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8;
1806 for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
1807 writew(mc_filter[i], filter_addr);
1808 rx_mode |= AcceptBroadcast|PerfectFilter|HashFilter;
1810 writel(rx_mode, ioaddr + RxFilterMode);
1813 static int check_if_running(struct net_device *dev)
1815 if (!netif_running(dev))
1820 static void get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info)
1822 struct netdev_private *np = netdev_priv(dev);
1823 strcpy(info->driver, DRV_NAME);
1824 strcpy(info->version, DRV_VERSION);
1825 strcpy(info->bus_info, pci_name(np->pci_dev));
1828 static int get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1830 struct netdev_private *np = netdev_priv(dev);
1831 spin_lock_irq(&np->lock);
1832 mii_ethtool_gset(&np->mii_if, ecmd);
1833 spin_unlock_irq(&np->lock);
1837 static int set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
1839 struct netdev_private *np = netdev_priv(dev);
1841 spin_lock_irq(&np->lock);
1842 res = mii_ethtool_sset(&np->mii_if, ecmd);
1843 spin_unlock_irq(&np->lock);
1848 static int nway_reset(struct net_device *dev)
1850 struct netdev_private *np = netdev_priv(dev);
1851 return mii_nway_restart(&np->mii_if);
1854 static u32 get_link(struct net_device *dev)
1856 struct netdev_private *np = netdev_priv(dev);
1857 return mii_link_ok(&np->mii_if);
1860 static u32 get_msglevel(struct net_device *dev)
1865 static void set_msglevel(struct net_device *dev, u32 val)
1870 static const struct ethtool_ops ethtool_ops = {
1871 .begin = check_if_running,
1872 .get_drvinfo = get_drvinfo,
1873 .get_settings = get_settings,
1874 .set_settings = set_settings,
1875 .nway_reset = nway_reset,
1876 .get_link = get_link,
1877 .get_msglevel = get_msglevel,
1878 .set_msglevel = set_msglevel,
1881 static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1883 struct netdev_private *np = netdev_priv(dev);
1884 struct mii_ioctl_data *data = if_mii(rq);
1887 if (!netif_running(dev))
1890 spin_lock_irq(&np->lock);
1891 rc = generic_mii_ioctl(&np->mii_if, data, cmd, NULL);
1892 spin_unlock_irq(&np->lock);
1894 if ((cmd == SIOCSMIIREG) && (data->phy_id == np->phys[0]))
1900 static int netdev_close(struct net_device *dev)
1902 struct netdev_private *np = netdev_priv(dev);
1903 void __iomem *ioaddr = np->base;
1906 netif_stop_queue(dev);
1909 printk(KERN_DEBUG "%s: Shutting down ethercard, Intr status %#8.8x.\n",
1910 dev->name, (int) readl(ioaddr + IntrStatus));
1911 printk(KERN_DEBUG "%s: Queue pointers were Tx %d / %d, Rx %d / %d.\n",
1912 dev->name, np->cur_tx, np->dirty_tx,
1913 np->cur_rx, np->dirty_rx);
1916 /* Disable interrupts by clearing the interrupt mask. */
1917 writel(0, ioaddr + IntrEnable);
1919 /* Stop the chip's Tx and Rx processes. */
1920 writel(0, ioaddr + GenCtrl);
1921 readl(ioaddr + GenCtrl);
1924 printk(KERN_DEBUG" Tx ring at %#llx:\n",
1925 (long long) np->tx_ring_dma);
1926 for (i = 0; i < 8 /* TX_RING_SIZE is huge! */; i++)
1927 printk(KERN_DEBUG " #%d desc. %#8.8x %#llx -> %#8.8x.\n",
1928 i, le32_to_cpu(np->tx_ring[i].status),
1929 (long long) dma_to_cpu(np->tx_ring[i].addr),
1930 le32_to_cpu(np->tx_done_q[i].status));
1931 printk(KERN_DEBUG " Rx ring at %#llx -> %p:\n",
1932 (long long) np->rx_ring_dma, np->rx_done_q);
1934 for (i = 0; i < 8 /* RX_RING_SIZE */; i++) {
1935 printk(KERN_DEBUG " #%d desc. %#llx -> %#8.8x\n",
1936 i, (long long) dma_to_cpu(np->rx_ring[i].rxaddr), le32_to_cpu(np->rx_done_q[i].status));
1940 free_irq(dev->irq, dev);
1942 /* Free all the skbuffs in the Rx queue. */
1943 for (i = 0; i < RX_RING_SIZE; i++) {
1944 np->rx_ring[i].rxaddr = cpu_to_dma(0xBADF00D0); /* An invalid address. */
1945 if (np->rx_info[i].skb != NULL) {
1946 pci_unmap_single(np->pci_dev, np->rx_info[i].mapping, np->rx_buf_sz, PCI_DMA_FROMDEVICE);
1947 dev_kfree_skb(np->rx_info[i].skb);
1949 np->rx_info[i].skb = NULL;
1950 np->rx_info[i].mapping = 0;
1952 for (i = 0; i < TX_RING_SIZE; i++) {
1953 struct sk_buff *skb = np->tx_info[i].skb;
1956 pci_unmap_single(np->pci_dev,
1957 np->tx_info[i].mapping,
1958 skb_first_frag_len(skb), PCI_DMA_TODEVICE);
1959 np->tx_info[i].mapping = 0;
1961 np->tx_info[i].skb = NULL;
1968 static int starfire_suspend(struct pci_dev *pdev, pm_message_t state)
1970 struct net_device *dev = pci_get_drvdata(pdev);
1972 if (netif_running(dev)) {
1973 netif_device_detach(dev);
1977 pci_save_state(pdev);
1978 pci_set_power_state(pdev, pci_choose_state(pdev,state));
1983 static int starfire_resume(struct pci_dev *pdev)
1985 struct net_device *dev = pci_get_drvdata(pdev);
1987 pci_set_power_state(pdev, PCI_D0);
1988 pci_restore_state(pdev);
1990 if (netif_running(dev)) {
1992 netif_device_attach(dev);
1997 #endif /* CONFIG_PM */
2000 static void __devexit starfire_remove_one (struct pci_dev *pdev)
2002 struct net_device *dev = pci_get_drvdata(pdev);
2003 struct netdev_private *np = netdev_priv(dev);
2007 unregister_netdev(dev);
2010 pci_free_consistent(pdev, np->queue_mem_size, np->queue_mem, np->queue_mem_dma);
2013 /* XXX: add wakeup code -- requires firmware for MagicPacket */
2014 pci_set_power_state(pdev, PCI_D3hot); /* go to sleep in D3 mode */
2015 pci_disable_device(pdev);
2018 pci_release_regions(pdev);
2020 pci_set_drvdata(pdev, NULL);
2021 free_netdev(dev); /* Will also free np!! */
2025 static struct pci_driver starfire_driver = {
2027 .probe = starfire_init_one,
2028 .remove = __devexit_p(starfire_remove_one),
2030 .suspend = starfire_suspend,
2031 .resume = starfire_resume,
2032 #endif /* CONFIG_PM */
2033 .id_table = starfire_pci_tbl,
2037 static int __init starfire_init (void)
2039 /* when a module, this is printed whether or not devices are found in probe */
2042 #ifdef HAVE_NETDEV_POLL
2043 printk(KERN_INFO DRV_NAME ": polling (NAPI) enabled\n");
2045 printk(KERN_INFO DRV_NAME ": polling (NAPI) disabled\n");
2049 /* we can do this test only at run-time... sigh */
2050 if (sizeof(dma_addr_t) != sizeof(netdrv_addr_t)) {
2051 printk("This driver has dma_addr_t issues, please send email to maintainer\n");
2055 return pci_register_driver(&starfire_driver);
2059 static void __exit starfire_cleanup (void)
2061 pci_unregister_driver (&starfire_driver);
2065 module_init(starfire_init);
2066 module_exit(starfire_cleanup);