1 /*------------------------------------------------------------------------
2 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
4 . Copyright (C) 1996 by Erik Stahlman
5 . Copyright (C) 2001 Standard Microsystems Corporation
6 . Developed by Simple Network Magic Corporation
7 . Copyright (C) 2003 Monta Vista Software, Inc.
8 . Unified SMC91x driver by Nicolas Pitre
10 . This program is free software; you can redistribute it and/or modify
11 . it under the terms of the GNU General Public License as published by
12 . the Free Software Foundation; either version 2 of the License, or
13 . (at your option) any later version.
15 . This program is distributed in the hope that it will be useful,
16 . but WITHOUT ANY WARRANTY; without even the implied warranty of
17 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 . GNU General Public License for more details.
20 . You should have received a copy of the GNU General Public License
21 . along with this program; if not, write to the Free Software
22 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 . Information contained in this file was obtained from the LAN91C111
25 . manual from SMC. To get a copy, if you really want one, you can find
26 . information under www.smsc.com.
29 . Erik Stahlman <erik@vt.edu>
30 . Daris A Nevil <dnevil@snmc.com>
31 . Nicolas Pitre <nico@cam.org>
33 ---------------------------------------------------------------------------*/
37 #include <linux/smc91x.h>
40 * Define your architecture specific bus configuration parameters here.
43 #if defined(CONFIG_ARCH_LUBBOCK) ||\
44 defined(CONFIG_MACH_MAINSTONE) ||\
45 defined(CONFIG_MACH_ZYLONITE)
47 #include <asm/mach-types.h>
49 /* Now the bus width is specified in the platform data
50 * pretend here to support all I/O access types
52 #define SMC_CAN_USE_8BIT 1
53 #define SMC_CAN_USE_16BIT 1
54 #define SMC_CAN_USE_32BIT 1
57 #define SMC_IO_SHIFT (lp->io_shift)
59 #define SMC_inb(a, r) readb((a) + (r))
60 #define SMC_inw(a, r) readw((a) + (r))
61 #define SMC_inl(a, r) readl((a) + (r))
62 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
63 #define SMC_outl(v, a, r) writel(v, (a) + (r))
64 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
65 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
66 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
67 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
68 #define SMC_IRQ_FLAGS (-1) /* from resource */
70 /* We actually can't write halfwords properly if not word aligned */
71 static inline void SMC_outw(u16 val, void __iomem *ioaddr, int reg)
73 if (machine_is_mainstone() && reg & 2) {
74 unsigned int v = val << 16;
75 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
76 writel(v, ioaddr + (reg & ~2));
78 writew(val, ioaddr + reg);
82 #elif defined(CONFIG_BLACKFIN)
84 #define SMC_IRQ_FLAGS IRQF_TRIGGER_HIGH
85 #define RPC_LSA_DEFAULT RPC_LED_100_10
86 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
88 # if defined (CONFIG_BFIN561_EZKIT)
89 #define SMC_CAN_USE_8BIT 0
90 #define SMC_CAN_USE_16BIT 1
91 #define SMC_CAN_USE_32BIT 1
92 #define SMC_IO_SHIFT 0
94 #define SMC_USE_BFIN_DMA 0
97 #define SMC_inw(a, r) readw((a) + (r))
98 #define SMC_outw(v, a, r) writew(v, (a) + (r))
99 #define SMC_inl(a, r) readl((a) + (r))
100 #define SMC_outl(v, a, r) writel(v, (a) + (r))
101 #define SMC_outsl(a, r, p, l) outsl((unsigned long *)((a) + (r)), p, l)
102 #define SMC_insl(a, r, p, l) insl ((unsigned long *)((a) + (r)), p, l)
104 #define SMC_CAN_USE_8BIT 0
105 #define SMC_CAN_USE_16BIT 1
106 #define SMC_CAN_USE_32BIT 0
107 #define SMC_IO_SHIFT 0
109 #define SMC_USE_BFIN_DMA 0
112 #define SMC_inw(a, r) readw((a) + (r))
113 #define SMC_outw(v, a, r) writew(v, (a) + (r))
114 #define SMC_outsw(a, r, p, l) outsw((unsigned long *)((a) + (r)), p, l)
115 #define SMC_insw(a, r, p, l) insw ((unsigned long *)((a) + (r)), p, l)
117 /* check if the mac in reg is valid */
118 #define SMC_GET_MAC_ADDR(lp, addr) \
121 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
122 addr[0] = __v; addr[1] = __v >> 8; \
123 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
124 addr[2] = __v; addr[3] = __v >> 8; \
125 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
126 addr[4] = __v; addr[5] = __v >> 8; \
127 if (*(u32 *)(&addr[0]) == 0xFFFFFFFF) { \
128 random_ether_addr(addr); \
131 #elif defined(CONFIG_REDWOOD_5) || defined(CONFIG_REDWOOD_6)
133 /* We can only do 16-bit reads and writes in the static memory space. */
134 #define SMC_CAN_USE_8BIT 0
135 #define SMC_CAN_USE_16BIT 1
136 #define SMC_CAN_USE_32BIT 0
139 #define SMC_IO_SHIFT 0
141 #define SMC_inw(a, r) in_be16((volatile u16 *)((a) + (r)))
142 #define SMC_outw(v, a, r) out_be16((volatile u16 *)((a) + (r)), v)
143 #define SMC_insw(a, r, p, l) \
145 unsigned long __port = (a) + (r); \
146 u16 *__p = (u16 *)(p); \
148 insw(__port, __p, __l); \
150 *__p = swab16(*__p); \
155 #define SMC_outsw(a, r, p, l) \
157 unsigned long __port = (a) + (r); \
158 u16 *__p = (u16 *)(p); \
161 /* Believe it or not, the swab isn't needed. */ \
162 outw( /* swab16 */ (*__p++), __port); \
166 #define SMC_IRQ_FLAGS (0)
168 #elif defined(CONFIG_SA1100_PLEB)
169 /* We can only do 16-bit reads and writes in the static memory space. */
170 #define SMC_CAN_USE_8BIT 1
171 #define SMC_CAN_USE_16BIT 1
172 #define SMC_CAN_USE_32BIT 0
173 #define SMC_IO_SHIFT 0
176 #define SMC_inb(a, r) readb((a) + (r))
177 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
178 #define SMC_inw(a, r) readw((a) + (r))
179 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
180 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
181 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
182 #define SMC_outw(v, a, r) writew(v, (a) + (r))
183 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
185 #define SMC_IRQ_FLAGS (-1)
187 #elif defined(CONFIG_SA1100_ASSABET)
189 #include <asm/arch/neponset.h>
191 /* We can only do 8-bit reads and writes in the static memory space. */
192 #define SMC_CAN_USE_8BIT 1
193 #define SMC_CAN_USE_16BIT 0
194 #define SMC_CAN_USE_32BIT 0
197 /* The first two address lines aren't connected... */
198 #define SMC_IO_SHIFT 2
200 #define SMC_inb(a, r) readb((a) + (r))
201 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
202 #define SMC_insb(a, r, p, l) readsb((a) + (r), p, (l))
203 #define SMC_outsb(a, r, p, l) writesb((a) + (r), p, (l))
204 #define SMC_IRQ_FLAGS (-1) /* from resource */
206 #elif defined(CONFIG_MACH_LOGICPD_PXA270)
208 #define SMC_CAN_USE_8BIT 0
209 #define SMC_CAN_USE_16BIT 1
210 #define SMC_CAN_USE_32BIT 0
211 #define SMC_IO_SHIFT 0
214 #define SMC_inw(a, r) readw((a) + (r))
215 #define SMC_outw(v, a, r) writew(v, (a) + (r))
216 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
217 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
219 #elif defined(CONFIG_ARCH_INNOKOM) || \
220 defined(CONFIG_ARCH_PXA_IDP) || \
221 defined(CONFIG_ARCH_RAMSES) || \
222 defined(CONFIG_ARCH_PCM027)
224 #define SMC_CAN_USE_8BIT 1
225 #define SMC_CAN_USE_16BIT 1
226 #define SMC_CAN_USE_32BIT 1
227 #define SMC_IO_SHIFT 0
229 #define SMC_USE_PXA_DMA 1
231 #define SMC_inb(a, r) readb((a) + (r))
232 #define SMC_inw(a, r) readw((a) + (r))
233 #define SMC_inl(a, r) readl((a) + (r))
234 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
235 #define SMC_outl(v, a, r) writel(v, (a) + (r))
236 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
237 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
238 #define SMC_IRQ_FLAGS (-1) /* from resource */
240 /* We actually can't write halfwords properly if not word aligned */
242 SMC_outw(u16 val, void __iomem *ioaddr, int reg)
245 unsigned int v = val << 16;
246 v |= readl(ioaddr + (reg & ~2)) & 0xffff;
247 writel(v, ioaddr + (reg & ~2));
249 writew(val, ioaddr + reg);
253 #elif defined(CONFIG_ARCH_OMAP)
255 /* We can only do 16-bit reads and writes in the static memory space. */
256 #define SMC_CAN_USE_8BIT 0
257 #define SMC_CAN_USE_16BIT 1
258 #define SMC_CAN_USE_32BIT 0
259 #define SMC_IO_SHIFT 0
262 #define SMC_inw(a, r) readw((a) + (r))
263 #define SMC_outw(v, a, r) writew(v, (a) + (r))
264 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
265 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
266 #define SMC_IRQ_FLAGS (-1) /* from resource */
268 #elif defined(CONFIG_SH_SH4202_MICRODEV)
270 #define SMC_CAN_USE_8BIT 0
271 #define SMC_CAN_USE_16BIT 1
272 #define SMC_CAN_USE_32BIT 0
274 #define SMC_inb(a, r) inb((a) + (r) - 0xa0000000)
275 #define SMC_inw(a, r) inw((a) + (r) - 0xa0000000)
276 #define SMC_inl(a, r) inl((a) + (r) - 0xa0000000)
277 #define SMC_outb(v, a, r) outb(v, (a) + (r) - 0xa0000000)
278 #define SMC_outw(v, a, r) outw(v, (a) + (r) - 0xa0000000)
279 #define SMC_outl(v, a, r) outl(v, (a) + (r) - 0xa0000000)
280 #define SMC_insl(a, r, p, l) insl((a) + (r) - 0xa0000000, p, l)
281 #define SMC_outsl(a, r, p, l) outsl((a) + (r) - 0xa0000000, p, l)
282 #define SMC_insw(a, r, p, l) insw((a) + (r) - 0xa0000000, p, l)
283 #define SMC_outsw(a, r, p, l) outsw((a) + (r) - 0xa0000000, p, l)
285 #define SMC_IRQ_FLAGS (0)
287 #elif defined(CONFIG_ISA)
289 #define SMC_CAN_USE_8BIT 1
290 #define SMC_CAN_USE_16BIT 1
291 #define SMC_CAN_USE_32BIT 0
293 #define SMC_inb(a, r) inb((a) + (r))
294 #define SMC_inw(a, r) inw((a) + (r))
295 #define SMC_outb(v, a, r) outb(v, (a) + (r))
296 #define SMC_outw(v, a, r) outw(v, (a) + (r))
297 #define SMC_insw(a, r, p, l) insw((a) + (r), p, l)
298 #define SMC_outsw(a, r, p, l) outsw((a) + (r), p, l)
300 #elif defined(CONFIG_M32R)
302 #define SMC_CAN_USE_8BIT 0
303 #define SMC_CAN_USE_16BIT 1
304 #define SMC_CAN_USE_32BIT 0
306 #define SMC_inb(a, r) inb(((u32)a) + (r))
307 #define SMC_inw(a, r) inw(((u32)a) + (r))
308 #define SMC_outb(v, a, r) outb(v, ((u32)a) + (r))
309 #define SMC_outw(v, a, r) outw(v, ((u32)a) + (r))
310 #define SMC_insw(a, r, p, l) insw(((u32)a) + (r), p, l)
311 #define SMC_outsw(a, r, p, l) outsw(((u32)a) + (r), p, l)
313 #define SMC_IRQ_FLAGS (0)
315 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
316 #define RPC_LSB_DEFAULT RPC_LED_100_10
318 #elif defined(CONFIG_MACH_LPD79520) \
319 || defined(CONFIG_MACH_LPD7A400) \
320 || defined(CONFIG_MACH_LPD7A404)
322 /* The LPD7X_IOBARRIER is necessary to overcome a mismatch between the
323 * way that the CPU handles chip selects and the way that the SMC chip
324 * expects the chip select to operate. Refer to
325 * Documentation/arm/Sharp-LH/IOBarrier for details. The read from
326 * IOBARRIER is a byte, in order that we read the least-common
327 * denominator. It would be wasteful to read 32 bits from an 8-bit
330 * There is no explicit protection against interrupts intervening
331 * between the writew and the IOBARRIER. In SMC ISR there is a
332 * preamble that performs an IOBARRIER in the extremely unlikely event
333 * that the driver interrupts itself between a writew to the chip an
334 * the IOBARRIER that follows *and* the cache is large enough that the
335 * first off-chip access while handing the interrupt is to the SMC
336 * chip. Other devices in the same address space as the SMC chip must
337 * be aware of the potential for trouble and perform a similar
338 * IOBARRIER on entry to their ISR.
341 #include <asm/arch/constants.h> /* IOBARRIER_VIRT */
343 #define SMC_CAN_USE_8BIT 0
344 #define SMC_CAN_USE_16BIT 1
345 #define SMC_CAN_USE_32BIT 0
347 #define LPD7X_IOBARRIER readb (IOBARRIER_VIRT)
349 #define SMC_inw(a,r)\
350 ({ unsigned short v = readw ((void*) ((a) + (r))); LPD7X_IOBARRIER; v; })
351 #define SMC_outw(v,a,r) ({ writew ((v), (a) + (r)); LPD7X_IOBARRIER; })
353 #define SMC_insw LPD7_SMC_insw
354 static inline void LPD7_SMC_insw (unsigned char* a, int r,
355 unsigned char* p, int l)
357 unsigned short* ps = (unsigned short*) p;
359 *ps++ = readw (a + r);
364 #define SMC_outsw LPD7_SMC_outsw
365 static inline void LPD7_SMC_outsw (unsigned char* a, int r,
366 unsigned char* p, int l)
368 unsigned short* ps = (unsigned short*) p;
370 writew (*ps++, a + r);
375 #define SMC_INTERRUPT_PREAMBLE LPD7X_IOBARRIER
377 #define RPC_LSA_DEFAULT RPC_LED_TX_RX
378 #define RPC_LSB_DEFAULT RPC_LED_100_10
380 #elif defined(CONFIG_SOC_AU1X00)
384 /* We can only do 16-bit reads and writes in the static memory space. */
385 #define SMC_CAN_USE_8BIT 0
386 #define SMC_CAN_USE_16BIT 1
387 #define SMC_CAN_USE_32BIT 0
388 #define SMC_IO_SHIFT 0
391 #define SMC_inw(a, r) au_readw((unsigned long)((a) + (r)))
392 #define SMC_insw(a, r, p, l) \
394 unsigned long _a = (unsigned long)((a) + (r)); \
396 u16 *_p = (u16 *)(p); \
398 *_p++ = au_readw(_a); \
400 #define SMC_outw(v, a, r) au_writew(v, (unsigned long)((a) + (r)))
401 #define SMC_outsw(a, r, p, l) \
403 unsigned long _a = (unsigned long)((a) + (r)); \
405 const u16 *_p = (const u16 *)(p); \
407 au_writew(*_p++ , _a); \
410 #define SMC_IRQ_FLAGS (0)
412 #elif defined(CONFIG_ARCH_VERSATILE)
414 #define SMC_CAN_USE_8BIT 1
415 #define SMC_CAN_USE_16BIT 1
416 #define SMC_CAN_USE_32BIT 1
419 #define SMC_inb(a, r) readb((a) + (r))
420 #define SMC_inw(a, r) readw((a) + (r))
421 #define SMC_inl(a, r) readl((a) + (r))
422 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
423 #define SMC_outw(v, a, r) writew(v, (a) + (r))
424 #define SMC_outl(v, a, r) writel(v, (a) + (r))
425 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
426 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
427 #define SMC_IRQ_FLAGS (-1) /* from resource */
429 #elif defined(CONFIG_MN10300)
432 * MN10300/AM33 configuration
435 #include <asm/unit/smc91111.h>
440 * Default configuration
443 #define SMC_CAN_USE_8BIT 1
444 #define SMC_CAN_USE_16BIT 1
445 #define SMC_CAN_USE_32BIT 1
448 #define SMC_inb(a, r) readb((a) + (r))
449 #define SMC_inw(a, r) readw((a) + (r))
450 #define SMC_inl(a, r) readl((a) + (r))
451 #define SMC_outb(v, a, r) writeb(v, (a) + (r))
452 #define SMC_outw(v, a, r) writew(v, (a) + (r))
453 #define SMC_outl(v, a, r) writel(v, (a) + (r))
454 #define SMC_insw(a, r, p, l) readsw((a) + (r), p, l)
455 #define SMC_outsw(a, r, p, l) writesw((a) + (r), p, l)
456 #define SMC_insl(a, r, p, l) readsl((a) + (r), p, l)
457 #define SMC_outsl(a, r, p, l) writesl((a) + (r), p, l)
459 #define RPC_LSA_DEFAULT RPC_LED_100_10
460 #define RPC_LSB_DEFAULT RPC_LED_TX_RX
465 /* store this information for the driver.. */
468 * If I have to wait until memory is available to send a
469 * packet, I will store the skbuff here, until I get the
470 * desired memory. Then, I'll send it out and free it.
472 struct sk_buff *pending_tx_skb;
473 struct tasklet_struct tx_task;
475 /* version/revision of the SMC91x chip */
478 /* Contains the current active transmission mode */
481 /* Contains the current active receive mode */
484 /* Contains the current active receive/phy mode */
491 struct mii_if_info mii;
494 struct work_struct phy_configure;
495 struct net_device *dev;
500 #ifdef CONFIG_ARCH_PXA
501 /* DMA needs the physical address of the chip */
503 struct device *device;
506 void __iomem *datacs;
508 /* the low address lines on some platforms aren't connected... */
511 struct smc91x_platdata cfg;
514 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
515 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
516 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
518 #ifdef CONFIG_ARCH_PXA
520 * Let's use the DMA engine on the XScale PXA2xx for RX packets. This is
521 * always happening in irq context so no need to worry about races. TX is
522 * different and probably not worth it for that reason, and not as critical
523 * as RX which can overrun memory and lose packets.
525 #include <linux/dma-mapping.h>
527 #include <asm/arch/pxa-regs.h>
531 #define SMC_insl(a, r, p, l) \
532 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
534 smc_pxa_dma_insl(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
535 u_char *buf, int len)
537 u_long physaddr = lp->physaddr;
540 /* fallback if no DMA available */
541 if (dma == (unsigned char)-1) {
542 readsl(ioaddr + reg, buf, len);
546 /* 64 bit alignment is required for memory to memory DMA */
548 *((u32 *)buf) = SMC_inl(ioaddr, reg);
554 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
555 DCSR(dma) = DCSR_NODESC;
557 DSADR(dma) = physaddr + reg;
558 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
559 DCMD_WIDTH4 | (DCMD_LENGTH & len));
560 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
561 while (!(DCSR(dma) & DCSR_STOPSTATE))
564 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
570 #define SMC_insw(a, r, p, l) \
571 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
573 smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma,
574 u_char *buf, int len)
576 u_long physaddr = lp->physaddr;
579 /* fallback if no DMA available */
580 if (dma == (unsigned char)-1) {
581 readsw(ioaddr + reg, buf, len);
585 /* 64 bit alignment is required for memory to memory DMA */
586 while ((long)buf & 6) {
587 *((u16 *)buf) = SMC_inw(ioaddr, reg);
593 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE);
594 DCSR(dma) = DCSR_NODESC;
596 DSADR(dma) = physaddr + reg;
597 DCMD(dma) = (DCMD_INCTRGADDR | DCMD_BURST32 |
598 DCMD_WIDTH2 | (DCMD_LENGTH & len));
599 DCSR(dma) = DCSR_NODESC | DCSR_RUN;
600 while (!(DCSR(dma) & DCSR_STOPSTATE))
603 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE);
608 smc_pxa_dma_irq(int dma, void *dummy)
612 #endif /* CONFIG_ARCH_PXA */
616 * Everything a particular hardware setup needs should have been defined
617 * at this point. Add stubs for the undefined cases, mainly to avoid
618 * compilation warnings since they'll be optimized away, or to prevent buggy
622 #if ! SMC_CAN_USE_32BIT
623 #define SMC_inl(ioaddr, reg) ({ BUG(); 0; })
624 #define SMC_outl(x, ioaddr, reg) BUG()
625 #define SMC_insl(a, r, p, l) BUG()
626 #define SMC_outsl(a, r, p, l) BUG()
629 #if !defined(SMC_insl) || !defined(SMC_outsl)
630 #define SMC_insl(a, r, p, l) BUG()
631 #define SMC_outsl(a, r, p, l) BUG()
634 #if ! SMC_CAN_USE_16BIT
637 * Any 16-bit access is performed with two 8-bit accesses if the hardware
638 * can't do it directly. Most registers are 16-bit so those are mandatory.
640 #define SMC_outw(x, ioaddr, reg) \
642 unsigned int __val16 = (x); \
643 SMC_outb( __val16, ioaddr, reg ); \
644 SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\
646 #define SMC_inw(ioaddr, reg) \
648 unsigned int __val16; \
649 __val16 = SMC_inb( ioaddr, reg ); \
650 __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \
654 #define SMC_insw(a, r, p, l) BUG()
655 #define SMC_outsw(a, r, p, l) BUG()
659 #if !defined(SMC_insw) || !defined(SMC_outsw)
660 #define SMC_insw(a, r, p, l) BUG()
661 #define SMC_outsw(a, r, p, l) BUG()
664 #if ! SMC_CAN_USE_8BIT
665 #define SMC_inb(ioaddr, reg) ({ BUG(); 0; })
666 #define SMC_outb(x, ioaddr, reg) BUG()
667 #define SMC_insb(a, r, p, l) BUG()
668 #define SMC_outsb(a, r, p, l) BUG()
671 #if !defined(SMC_insb) || !defined(SMC_outsb)
672 #define SMC_insb(a, r, p, l) BUG()
673 #define SMC_outsb(a, r, p, l) BUG()
676 #ifndef SMC_CAN_USE_DATACS
677 #define SMC_CAN_USE_DATACS 0
681 #define SMC_IO_SHIFT 0
684 #ifndef SMC_IRQ_FLAGS
685 #define SMC_IRQ_FLAGS IRQF_TRIGGER_RISING
688 #ifndef SMC_INTERRUPT_PREAMBLE
689 #define SMC_INTERRUPT_PREAMBLE
693 /* Because of bank switching, the LAN91x uses only 16 I/O ports */
694 #define SMC_IO_EXTENT (16 << SMC_IO_SHIFT)
695 #define SMC_DATA_EXTENT (4)
698 . Bank Select Register:
700 . yyyy yyyy 0000 00xx
702 . yyyy yyyy = 0x33, for identification purposes.
704 #define BANK_SELECT (14 << SMC_IO_SHIFT)
707 // Transmit Control Register
709 #define TCR_REG(lp) SMC_REG(lp, 0x0000, 0)
710 #define TCR_ENABLE 0x0001 // When 1 we can transmit
711 #define TCR_LOOP 0x0002 // Controls output pin LBK
712 #define TCR_FORCOL 0x0004 // When 1 will force a collision
713 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
714 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
715 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
716 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
717 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
718 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
719 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
721 #define TCR_CLEAR 0 /* do NOTHING */
722 /* the default settings for the TCR register : */
723 #define TCR_DEFAULT (TCR_ENABLE | TCR_PAD_EN)
726 // EPH Status Register
728 #define EPH_STATUS_REG(lp) SMC_REG(lp, 0x0002, 0)
729 #define ES_TX_SUC 0x0001 // Last TX was successful
730 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
731 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
732 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
733 #define ES_16COL 0x0010 // 16 Collisions Reached
734 #define ES_SQET 0x0020 // Signal Quality Error Test
735 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
736 #define ES_TXDEFR 0x0080 // Transmit Deferred
737 #define ES_LATCOL 0x0200 // Late collision detected on last tx
738 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
739 #define ES_EXC_DEF 0x0800 // Excessive Deferral
740 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
741 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
742 #define ES_TXUNRN 0x8000 // Tx Underrun
745 // Receive Control Register
747 #define RCR_REG(lp) SMC_REG(lp, 0x0004, 0)
748 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
749 #define RCR_PRMS 0x0002 // Enable promiscuous mode
750 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
751 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
752 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
753 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
754 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
755 #define RCR_SOFTRST 0x8000 // resets the chip
757 /* the normal settings for the RCR register : */
758 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
759 #define RCR_CLEAR 0x0 // set it to a base state
764 #define COUNTER_REG(lp) SMC_REG(lp, 0x0006, 0)
767 // Memory Information Register
769 #define MIR_REG(lp) SMC_REG(lp, 0x0008, 0)
772 // Receive/Phy Control Register
774 #define RPC_REG(lp) SMC_REG(lp, 0x000A, 0)
775 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
776 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
777 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
778 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
779 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
780 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
781 #define RPC_LED_RES (0x01) // LED = Reserved
782 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
783 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
784 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
785 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
786 #define RPC_LED_TX (0x06) // LED = TX packet occurred
787 #define RPC_LED_RX (0x07) // LED = RX packet occurred
789 #ifndef RPC_LSA_DEFAULT
790 #define RPC_LSA_DEFAULT RPC_LED_100
792 #ifndef RPC_LSB_DEFAULT
793 #define RPC_LSB_DEFAULT RPC_LED_FD
796 #define RPC_DEFAULT (RPC_ANEG | (RPC_LSA_DEFAULT << RPC_LSXA_SHFT) | (RPC_LSB_DEFAULT << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
799 /* Bank 0 0x0C is reserved */
801 // Bank Select Register
803 #define BSR_REG 0x000E
808 #define CONFIG_REG(lp) SMC_REG(lp, 0x0000, 1)
809 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
810 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
811 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
812 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
814 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
815 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
818 // Base Address Register
820 #define BASE_REG(lp) SMC_REG(lp, 0x0002, 1)
823 // Individual Address Registers
825 #define ADDR0_REG(lp) SMC_REG(lp, 0x0004, 1)
826 #define ADDR1_REG(lp) SMC_REG(lp, 0x0006, 1)
827 #define ADDR2_REG(lp) SMC_REG(lp, 0x0008, 1)
830 // General Purpose Register
832 #define GP_REG(lp) SMC_REG(lp, 0x000A, 1)
837 #define CTL_REG(lp) SMC_REG(lp, 0x000C, 1)
838 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
839 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
840 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
841 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
842 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
843 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
844 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
845 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
848 // MMU Command Register
850 #define MMU_CMD_REG(lp) SMC_REG(lp, 0x0000, 2)
851 #define MC_BUSY 1 // When 1 the last release has not completed
852 #define MC_NOP (0<<5) // No Op
853 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
854 #define MC_RESET (2<<5) // Reset MMU to initial state
855 #define MC_REMOVE (3<<5) // Remove the current rx packet
856 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
857 #define MC_FREEPKT (5<<5) // Release packet in PNR register
858 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
859 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
862 // Packet Number Register
864 #define PN_REG(lp) SMC_REG(lp, 0x0002, 2)
867 // Allocation Result Register
869 #define AR_REG(lp) SMC_REG(lp, 0x0003, 2)
870 #define AR_FAILED 0x80 // Alocation Failed
873 // TX FIFO Ports Register
875 #define TXFIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
876 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
878 // RX FIFO Ports Register
880 #define RXFIFO_REG(lp) SMC_REG(lp, 0x0005, 2)
881 #define RXFIFO_REMPTY 0x80 // RX FIFO Empty
883 #define FIFO_REG(lp) SMC_REG(lp, 0x0004, 2)
887 #define PTR_REG(lp) SMC_REG(lp, 0x0006, 2)
888 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
889 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
890 #define PTR_READ 0x2000 // When 1 the operation is a read
895 #define DATA_REG(lp) SMC_REG(lp, 0x0008, 2)
898 // Interrupt Status/Acknowledge Register
900 #define INT_REG(lp) SMC_REG(lp, 0x000C, 2)
903 // Interrupt Mask Register
905 #define IM_REG(lp) SMC_REG(lp, 0x000D, 2)
906 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
907 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
908 #define IM_EPH_INT 0x20 // Set by Ethernet Protocol Handler section
909 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
910 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
911 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
912 #define IM_TX_INT 0x02 // Transmit Interrupt
913 #define IM_RCV_INT 0x01 // Receive Interrupt
916 // Multicast Table Registers
918 #define MCAST_REG1(lp) SMC_REG(lp, 0x0000, 3)
919 #define MCAST_REG2(lp) SMC_REG(lp, 0x0002, 3)
920 #define MCAST_REG3(lp) SMC_REG(lp, 0x0004, 3)
921 #define MCAST_REG4(lp) SMC_REG(lp, 0x0006, 3)
924 // Management Interface Register (MII)
926 #define MII_REG(lp) SMC_REG(lp, 0x0008, 3)
927 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
928 #define MII_MDOE 0x0008 // MII Output Enable
929 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
930 #define MII_MDI 0x0002 // MII Input, pin MDI
931 #define MII_MDO 0x0001 // MII Output, pin MDO
936 /* ( hi: chip id low: rev # ) */
937 #define REV_REG(lp) SMC_REG(lp, 0x000A, 3)
940 // Early RCV Register
942 /* this is NOT on SMC9192 */
943 #define ERCV_REG(lp) SMC_REG(lp, 0x000C, 3)
944 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
945 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
950 #define EXT_REG(lp) SMC_REG(lp, 0x0000, 7)
958 #define CHIP_91100FD 8
959 #define CHIP_91111FD 9
961 static const char * chip_ids[ 16 ] = {
963 /* 3 */ "SMC91C90/91C92",
968 /* 8 */ "SMC91C100FD",
969 /* 9 */ "SMC91C11xFD",
975 . Receive status bits
977 #define RS_ALGNERR 0x8000
978 #define RS_BRODCAST 0x4000
979 #define RS_BADCRC 0x2000
980 #define RS_ODDFRAME 0x1000
981 #define RS_TOOLONG 0x0800
982 #define RS_TOOSHORT 0x0400
983 #define RS_MULTICAST 0x0001
984 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
989 * LAN83C183 == LAN91C111 Internal PHY
991 #define PHY_LAN83C183 0x0016f840
992 #define PHY_LAN83C180 0x02821c50
995 * PHY Register Addresses (LAN91C111 Internal PHY)
997 * Generic PHY registers can be found in <linux/mii.h>
999 * These phy registers are specific to our on-board phy.
1002 // PHY Configuration Register 1
1003 #define PHY_CFG1_REG 0x10
1004 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
1005 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
1006 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
1007 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
1008 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
1009 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
1010 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
1011 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
1012 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
1013 #define PHY_CFG1_TLVL_MASK 0x003C
1014 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
1017 // PHY Configuration Register 2
1018 #define PHY_CFG2_REG 0x11
1019 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
1020 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
1021 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
1022 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
1024 // PHY Status Output (and Interrupt status) Register
1025 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
1026 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
1027 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
1028 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
1029 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
1030 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
1031 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
1032 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
1033 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
1034 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
1035 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
1037 // PHY Interrupt/Status Mask Register
1038 #define PHY_MASK_REG 0x13 // Interrupt Mask
1039 // Uses the same bit definitions as PHY_INT_REG
1043 * SMC91C96 ethernet config and status registers.
1044 * These are in the "attribute" space.
1047 #define ECOR_RESET 0x80
1048 #define ECOR_LEVEL_IRQ 0x40
1049 #define ECOR_WR_ATTRIB 0x04
1050 #define ECOR_ENABLE 0x01
1053 #define ECSR_IOIS8 0x20
1054 #define ECSR_PWRDWN 0x04
1055 #define ECSR_INT 0x02
1057 #define ATTRIB_SIZE ((64*1024) << SMC_IO_SHIFT)
1061 * Macros to abstract register access according to the data bus
1062 * capabilities. Please use those and not the in/out primitives.
1063 * Note: the following macros do *not* select the bank -- this must
1064 * be done separately as needed in the main code. The SMC_REG() macro
1065 * only uses the bank argument for debugging purposes (when enabled).
1067 * Note: despite inline functions being safer, everything leading to this
1068 * should preferably be macros to let BUG() display the line number in
1069 * the core source code since we're interested in the top call site
1070 * not in any inline function location.
1074 #define SMC_REG(lp, reg, bank) \
1076 int __b = SMC_CURRENT_BANK(lp); \
1077 if (unlikely((__b & ~0xf0) != (0x3300 | bank))) { \
1078 printk( "%s: bank reg screwed (0x%04x)\n", \
1082 reg<<SMC_IO_SHIFT; \
1085 #define SMC_REG(lp, reg, bank) (reg<<SMC_IO_SHIFT)
1089 * Hack Alert: Some setups just can't write 8 or 16 bits reliably when not
1090 * aligned to a 32 bit boundary. I tell you that does exist!
1091 * Fortunately the affected register accesses can be easily worked around
1092 * since we can write zeroes to the preceeding 16 bits without adverse
1093 * effects and use a 32-bit access.
1095 * Enforce it on any 32-bit capable setup for now.
1097 #define SMC_MUST_ALIGN_WRITE(lp) SMC_32BIT(lp)
1099 #define SMC_GET_PN(lp) \
1100 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, PN_REG(lp))) \
1101 : (SMC_inw(ioaddr, PN_REG(lp)) & 0xFF))
1103 #define SMC_SET_PN(lp, x) \
1105 if (SMC_MUST_ALIGN_WRITE(lp)) \
1106 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 0, 2)); \
1107 else if (SMC_8BIT(lp)) \
1108 SMC_outb(x, ioaddr, PN_REG(lp)); \
1110 SMC_outw(x, ioaddr, PN_REG(lp)); \
1113 #define SMC_GET_AR(lp) \
1114 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, AR_REG(lp))) \
1115 : (SMC_inw(ioaddr, PN_REG(lp)) >> 8))
1117 #define SMC_GET_TXFIFO(lp) \
1118 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, TXFIFO_REG(lp))) \
1119 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) & 0xFF))
1121 #define SMC_GET_RXFIFO(lp) \
1122 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, RXFIFO_REG(lp))) \
1123 : (SMC_inw(ioaddr, TXFIFO_REG(lp)) >> 8))
1125 #define SMC_GET_INT(lp) \
1126 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, INT_REG(lp))) \
1127 : (SMC_inw(ioaddr, INT_REG(lp)) & 0xFF))
1129 #define SMC_ACK_INT(lp, x) \
1132 SMC_outb(x, ioaddr, INT_REG(lp)); \
1134 unsigned long __flags; \
1136 local_irq_save(__flags); \
1137 __mask = SMC_inw(ioaddr, INT_REG(lp)) & ~0xff; \
1138 SMC_outw(__mask | (x), ioaddr, INT_REG(lp)); \
1139 local_irq_restore(__flags); \
1143 #define SMC_GET_INT_MASK(lp) \
1144 (SMC_8BIT(lp) ? (SMC_inb(ioaddr, IM_REG(lp))) \
1145 : (SMC_inw(ioaddr, INT_REG(lp)) >> 8))
1147 #define SMC_SET_INT_MASK(lp, x) \
1150 SMC_outb(x, ioaddr, IM_REG(lp)); \
1152 SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \
1155 #define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT)
1157 #define SMC_SELECT_BANK(lp, x) \
1159 if (SMC_MUST_ALIGN_WRITE(lp)) \
1160 SMC_outl((x)<<16, ioaddr, 12<<SMC_IO_SHIFT); \
1162 SMC_outw(x, ioaddr, BANK_SELECT); \
1165 #define SMC_GET_BASE(lp) SMC_inw(ioaddr, BASE_REG(lp))
1167 #define SMC_SET_BASE(lp, x) SMC_outw(x, ioaddr, BASE_REG(lp))
1169 #define SMC_GET_CONFIG(lp) SMC_inw(ioaddr, CONFIG_REG(lp))
1171 #define SMC_SET_CONFIG(lp, x) SMC_outw(x, ioaddr, CONFIG_REG(lp))
1173 #define SMC_GET_COUNTER(lp) SMC_inw(ioaddr, COUNTER_REG(lp))
1175 #define SMC_GET_CTL(lp) SMC_inw(ioaddr, CTL_REG(lp))
1177 #define SMC_SET_CTL(lp, x) SMC_outw(x, ioaddr, CTL_REG(lp))
1179 #define SMC_GET_MII(lp) SMC_inw(ioaddr, MII_REG(lp))
1181 #define SMC_SET_MII(lp, x) SMC_outw(x, ioaddr, MII_REG(lp))
1183 #define SMC_GET_MIR(lp) SMC_inw(ioaddr, MIR_REG(lp))
1185 #define SMC_SET_MIR(lp, x) SMC_outw(x, ioaddr, MIR_REG(lp))
1187 #define SMC_GET_MMU_CMD(lp) SMC_inw(ioaddr, MMU_CMD_REG(lp))
1189 #define SMC_SET_MMU_CMD(lp, x) SMC_outw(x, ioaddr, MMU_CMD_REG(lp))
1191 #define SMC_GET_FIFO(lp) SMC_inw(ioaddr, FIFO_REG(lp))
1193 #define SMC_GET_PTR(lp) SMC_inw(ioaddr, PTR_REG(lp))
1195 #define SMC_SET_PTR(lp, x) \
1197 if (SMC_MUST_ALIGN_WRITE(lp)) \
1198 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 4, 2)); \
1200 SMC_outw(x, ioaddr, PTR_REG(lp)); \
1203 #define SMC_GET_EPH_STATUS(lp) SMC_inw(ioaddr, EPH_STATUS_REG(lp))
1205 #define SMC_GET_RCR(lp) SMC_inw(ioaddr, RCR_REG(lp))
1207 #define SMC_SET_RCR(lp, x) SMC_outw(x, ioaddr, RCR_REG(lp))
1209 #define SMC_GET_REV(lp) SMC_inw(ioaddr, REV_REG(lp))
1211 #define SMC_GET_RPC(lp) SMC_inw(ioaddr, RPC_REG(lp))
1213 #define SMC_SET_RPC(lp, x) \
1215 if (SMC_MUST_ALIGN_WRITE(lp)) \
1216 SMC_outl((x)<<16, ioaddr, SMC_REG(lp, 8, 0)); \
1218 SMC_outw(x, ioaddr, RPC_REG(lp)); \
1221 #define SMC_GET_TCR(lp) SMC_inw(ioaddr, TCR_REG(lp))
1223 #define SMC_SET_TCR(lp, x) SMC_outw(x, ioaddr, TCR_REG(lp))
1225 #ifndef SMC_GET_MAC_ADDR
1226 #define SMC_GET_MAC_ADDR(lp, addr) \
1229 __v = SMC_inw(ioaddr, ADDR0_REG(lp)); \
1230 addr[0] = __v; addr[1] = __v >> 8; \
1231 __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \
1232 addr[2] = __v; addr[3] = __v >> 8; \
1233 __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \
1234 addr[4] = __v; addr[5] = __v >> 8; \
1238 #define SMC_SET_MAC_ADDR(lp, addr) \
1240 SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \
1241 SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \
1242 SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \
1245 #define SMC_SET_MCAST(lp, x) \
1247 const unsigned char *mt = (x); \
1248 SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \
1249 SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \
1250 SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \
1251 SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \
1254 #define SMC_PUT_PKT_HDR(lp, status, length) \
1256 if (SMC_32BIT(lp)) \
1257 SMC_outl((status) | (length)<<16, ioaddr, \
1260 SMC_outw(status, ioaddr, DATA_REG(lp)); \
1261 SMC_outw(length, ioaddr, DATA_REG(lp)); \
1265 #define SMC_GET_PKT_HDR(lp, status, length) \
1267 if (SMC_32BIT(lp)) { \
1268 unsigned int __val = SMC_inl(ioaddr, DATA_REG(lp)); \
1269 (status) = __val & 0xffff; \
1270 (length) = __val >> 16; \
1272 (status) = SMC_inw(ioaddr, DATA_REG(lp)); \
1273 (length) = SMC_inw(ioaddr, DATA_REG(lp)); \
1277 #define SMC_PUSH_DATA(lp, p, l) \
1279 if (SMC_32BIT(lp)) { \
1280 void *__ptr = (p); \
1282 void __iomem *__ioaddr = ioaddr; \
1283 if (__len >= 2 && (unsigned long)__ptr & 2) { \
1285 SMC_outw(*(u16 *)__ptr, ioaddr, \
1289 if (SMC_CAN_USE_DATACS && lp->datacs) \
1290 __ioaddr = lp->datacs; \
1291 SMC_outsl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1293 __ptr += (__len & ~3); \
1294 SMC_outw(*((u16 *)__ptr), ioaddr, \
1297 } else if (SMC_16BIT(lp)) \
1298 SMC_outsw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1299 else if (SMC_8BIT(lp)) \
1300 SMC_outsb(ioaddr, DATA_REG(lp), p, l); \
1303 #define SMC_PULL_DATA(lp, p, l) \
1305 if (SMC_32BIT(lp)) { \
1306 void *__ptr = (p); \
1308 void __iomem *__ioaddr = ioaddr; \
1309 if ((unsigned long)__ptr & 2) { \
1311 * We want 32bit alignment here. \
1312 * Since some buses perform a full \
1313 * 32bit fetch even for 16bit data \
1314 * we can't use SMC_inw() here. \
1315 * Back both source (on-chip) and \
1316 * destination pointers of 2 bytes. \
1317 * This is possible since the call to \
1318 * SMC_GET_PKT_HDR() already advanced \
1319 * the source pointer of 4 bytes, and \
1320 * the skb_reserve(skb, 2) advanced \
1321 * the destination pointer of 2 bytes. \
1326 2|PTR_READ|PTR_RCV|PTR_AUTOINC); \
1328 if (SMC_CAN_USE_DATACS && lp->datacs) \
1329 __ioaddr = lp->datacs; \
1331 SMC_insl(__ioaddr, DATA_REG(lp), __ptr, __len>>2); \
1332 } else if (SMC_16BIT(lp)) \
1333 SMC_insw(ioaddr, DATA_REG(lp), p, (l) >> 1); \
1334 else if (SMC_8BIT(lp)) \
1335 SMC_insb(ioaddr, DATA_REG(lp), p, l); \
1338 #endif /* _SMC91X_H_ */