2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27 #include <linux/crc32.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
36 #include <linux/slab.h>
38 #include <linux/tcp.h>
40 #include <linux/delay.h>
41 #include <linux/workqueue.h>
42 #include <linux/if_vlan.h>
43 #include <linux/prefetch.h>
44 #include <linux/debugfs.h>
45 #include <linux/mii.h>
49 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
50 #define SKY2_VLAN_TAG_USED 1
55 #define DRV_NAME "sky2"
56 #define DRV_VERSION "1.27"
59 * The Yukon II chipset takes 64 bit command blocks (called list elements)
60 * that are organized into three (receive, transmit, status) different rings
64 #define RX_LE_SIZE 1024
65 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
66 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
67 #define RX_DEF_PENDING RX_MAX_PENDING
69 /* This is the worst case number of transmit list elements for a single skb:
70 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
71 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
72 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
73 #define TX_MAX_PENDING 1024
74 #define TX_DEF_PENDING 127
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
82 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
84 static const u32 default_msg =
85 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
86 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
87 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
89 static int debug = -1; /* defaults above */
90 module_param(debug, int, 0);
91 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
93 static int copybreak __read_mostly = 128;
94 module_param(copybreak, int, 0);
95 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
97 static int disable_msi = 0;
98 module_param(disable_msi, int, 0);
99 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
101 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
102 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
105 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
146 MODULE_DEVICE_TABLE(pci, sky2_id_table);
148 /* Avoid conditionals by using array */
149 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
150 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
151 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
153 static void sky2_set_multicast(struct net_device *dev);
155 /* Access to PHY via serial interconnect */
156 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
160 gma_write16(hw, port, GM_SMI_DATA, val);
161 gma_write16(hw, port, GM_SMI_CTRL,
162 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164 for (i = 0; i < PHY_RETRIES; i++) {
165 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
169 if (!(ctrl & GM_SMI_CT_BUSY))
175 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
179 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
183 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
187 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
188 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
190 for (i = 0; i < PHY_RETRIES; i++) {
191 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
195 if (ctrl & GM_SMI_CT_RD_VAL) {
196 *val = gma_read16(hw, port, GM_SMI_DATA);
203 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
206 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
210 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
213 __gm_phy_read(hw, port, reg, &v);
218 static void sky2_power_on(struct sky2_hw *hw)
220 /* switch power to VCC (WA for VAUX problem) */
221 sky2_write8(hw, B0_POWER_CTRL,
222 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
224 /* disable Core Clock Division, */
225 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
227 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
228 /* enable bits are inverted */
229 sky2_write8(hw, B2_Y2_CLK_GATE,
230 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
231 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
232 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
234 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
236 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
239 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
241 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
242 /* set all bits to 0 except bits 15..12 and 8 */
243 reg &= P_ASPM_CONTROL_MSK;
244 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
246 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
247 /* set all bits to 0 except bits 28 & 27 */
248 reg &= P_CTL_TIM_VMAIN_AV_MSK;
249 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
251 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
253 sky2_write16(hw, B0_CTST, Y2_HW_WOL_ON);
255 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
256 reg = sky2_read32(hw, B2_GP_IO);
257 reg |= GLB_GPIO_STAT_RACE_DIS;
258 sky2_write32(hw, B2_GP_IO, reg);
260 sky2_read32(hw, B2_GP_IO);
263 /* Turn on "driver loaded" LED */
264 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
267 static void sky2_power_aux(struct sky2_hw *hw)
269 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
270 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
272 /* enable bits are inverted */
273 sky2_write8(hw, B2_Y2_CLK_GATE,
274 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
275 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
276 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
278 /* switch power to VAUX if supported and PME from D3cold */
279 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
280 pci_pme_capable(hw->pdev, PCI_D3cold))
281 sky2_write8(hw, B0_POWER_CTRL,
282 (PC_VAUX_ENA | PC_VCC_ENA |
283 PC_VAUX_ON | PC_VCC_OFF));
285 /* turn off "driver loaded LED" */
286 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
289 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
293 /* disable all GMAC IRQ's */
294 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
296 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
297 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
299 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
301 reg = gma_read16(hw, port, GM_RX_CTRL);
302 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
303 gma_write16(hw, port, GM_RX_CTRL, reg);
306 /* flow control to advertise bits */
307 static const u16 copper_fc_adv[] = {
309 [FC_TX] = PHY_M_AN_ASP,
310 [FC_RX] = PHY_M_AN_PC,
311 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
314 /* flow control to advertise bits when using 1000BaseX */
315 static const u16 fiber_fc_adv[] = {
316 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
317 [FC_TX] = PHY_M_P_ASYM_MD_X,
318 [FC_RX] = PHY_M_P_SYM_MD_X,
319 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
322 /* flow control to GMA disable bits */
323 static const u16 gm_fc_disable[] = {
324 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
325 [FC_TX] = GM_GPCR_FC_RX_DIS,
326 [FC_RX] = GM_GPCR_FC_TX_DIS,
331 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
333 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
334 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
336 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
337 !(hw->flags & SKY2_HW_NEWER_PHY)) {
338 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
340 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
342 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
344 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
345 if (hw->chip_id == CHIP_ID_YUKON_EC)
346 /* set downshift counter to 3x and enable downshift */
347 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
349 /* set master & slave downshift counter to 1x */
350 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
352 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
355 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
356 if (sky2_is_copper(hw)) {
357 if (!(hw->flags & SKY2_HW_GIGABIT)) {
358 /* enable automatic crossover */
359 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
361 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
362 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
365 /* Enable Class A driver for FE+ A0 */
366 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
367 spec |= PHY_M_FESC_SEL_CL_A;
368 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
371 /* disable energy detect */
372 ctrl &= ~PHY_M_PC_EN_DET_MSK;
374 /* enable automatic crossover */
375 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
377 /* downshift on PHY 88E1112 and 88E1149 is changed */
378 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
379 (hw->flags & SKY2_HW_NEWER_PHY)) {
380 /* set downshift counter to 3x and enable downshift */
381 ctrl &= ~PHY_M_PC_DSC_MSK;
382 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
386 /* workaround for deviation #4.88 (CRC errors) */
387 /* disable Automatic Crossover */
389 ctrl &= ~PHY_M_PC_MDIX_MSK;
392 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
394 /* special setup for PHY 88E1112 Fiber */
395 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
396 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
398 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
399 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
400 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
401 ctrl &= ~PHY_M_MAC_MD_MSK;
402 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
403 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
405 if (hw->pmd_type == 'P') {
406 /* select page 1 to access Fiber registers */
407 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
409 /* for SFP-module set SIGDET polarity to low */
410 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
411 ctrl |= PHY_M_FIB_SIGD_POL;
412 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
415 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
423 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
424 if (sky2_is_copper(hw)) {
425 if (sky2->advertising & ADVERTISED_1000baseT_Full)
426 ct1000 |= PHY_M_1000C_AFD;
427 if (sky2->advertising & ADVERTISED_1000baseT_Half)
428 ct1000 |= PHY_M_1000C_AHD;
429 if (sky2->advertising & ADVERTISED_100baseT_Full)
430 adv |= PHY_M_AN_100_FD;
431 if (sky2->advertising & ADVERTISED_100baseT_Half)
432 adv |= PHY_M_AN_100_HD;
433 if (sky2->advertising & ADVERTISED_10baseT_Full)
434 adv |= PHY_M_AN_10_FD;
435 if (sky2->advertising & ADVERTISED_10baseT_Half)
436 adv |= PHY_M_AN_10_HD;
438 } else { /* special defines for FIBER (88E1040S only) */
439 if (sky2->advertising & ADVERTISED_1000baseT_Full)
440 adv |= PHY_M_AN_1000X_AFD;
441 if (sky2->advertising & ADVERTISED_1000baseT_Half)
442 adv |= PHY_M_AN_1000X_AHD;
445 /* Restart Auto-negotiation */
446 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
448 /* forced speed/duplex settings */
449 ct1000 = PHY_M_1000C_MSE;
451 /* Disable auto update for duplex flow control and duplex */
452 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
454 switch (sky2->speed) {
456 ctrl |= PHY_CT_SP1000;
457 reg |= GM_GPCR_SPEED_1000;
460 ctrl |= PHY_CT_SP100;
461 reg |= GM_GPCR_SPEED_100;
465 if (sky2->duplex == DUPLEX_FULL) {
466 reg |= GM_GPCR_DUP_FULL;
467 ctrl |= PHY_CT_DUP_MD;
468 } else if (sky2->speed < SPEED_1000)
469 sky2->flow_mode = FC_NONE;
472 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
473 if (sky2_is_copper(hw))
474 adv |= copper_fc_adv[sky2->flow_mode];
476 adv |= fiber_fc_adv[sky2->flow_mode];
478 reg |= GM_GPCR_AU_FCT_DIS;
479 reg |= gm_fc_disable[sky2->flow_mode];
481 /* Forward pause packets to GMAC? */
482 if (sky2->flow_mode & FC_RX)
483 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
485 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
488 gma_write16(hw, port, GM_GP_CTRL, reg);
490 if (hw->flags & SKY2_HW_GIGABIT)
491 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
493 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
494 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
496 /* Setup Phy LED's */
497 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
500 switch (hw->chip_id) {
501 case CHIP_ID_YUKON_FE:
502 /* on 88E3082 these bits are at 11..9 (shifted left) */
503 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
505 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
507 /* delete ACT LED control bits */
508 ctrl &= ~PHY_M_FELP_LED1_MSK;
509 /* change ACT LED control to blink mode */
510 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
511 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
514 case CHIP_ID_YUKON_FE_P:
515 /* Enable Link Partner Next Page */
516 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
517 ctrl |= PHY_M_PC_ENA_LIP_NP;
519 /* disable Energy Detect and enable scrambler */
520 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
521 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
523 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
524 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
525 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
526 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
528 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
531 case CHIP_ID_YUKON_XL:
532 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
534 /* select page 3 to access LED control register */
535 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
537 /* set LED Function Control register */
538 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
539 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
540 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
541 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
542 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
544 /* set Polarity Control register */
545 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
546 (PHY_M_POLC_LS1_P_MIX(4) |
547 PHY_M_POLC_IS0_P_MIX(4) |
548 PHY_M_POLC_LOS_CTRL(2) |
549 PHY_M_POLC_INIT_CTRL(2) |
550 PHY_M_POLC_STA1_CTRL(2) |
551 PHY_M_POLC_STA0_CTRL(2)));
553 /* restore page register */
554 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
557 case CHIP_ID_YUKON_EC_U:
558 case CHIP_ID_YUKON_EX:
559 case CHIP_ID_YUKON_SUPR:
560 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
562 /* select page 3 to access LED control register */
563 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
565 /* set LED Function Control register */
566 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
567 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
568 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
569 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
570 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
572 /* set Blink Rate in LED Timer Control Register */
573 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
574 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
575 /* restore page register */
576 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
580 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
581 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
583 /* turn off the Rx LED (LED_RX) */
584 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
587 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
588 /* apply fixes in PHY AFE */
589 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
591 /* increase differential signal amplitude in 10BASE-T */
592 gm_phy_write(hw, port, 0x18, 0xaa99);
593 gm_phy_write(hw, port, 0x17, 0x2011);
595 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
596 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
597 gm_phy_write(hw, port, 0x18, 0xa204);
598 gm_phy_write(hw, port, 0x17, 0x2002);
601 /* set page register to 0 */
602 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
603 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
604 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
605 /* apply workaround for integrated resistors calibration */
606 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
607 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
608 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
609 /* apply fixes in PHY AFE */
610 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
612 /* apply RDAC termination workaround */
613 gm_phy_write(hw, port, 24, 0x2800);
614 gm_phy_write(hw, port, 23, 0x2001);
616 /* set page register back to 0 */
617 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
618 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
619 hw->chip_id < CHIP_ID_YUKON_SUPR) {
620 /* no effect on Yukon-XL */
621 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
623 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
624 sky2->speed == SPEED_100) {
625 /* turn on 100 Mbps LED (LED_LINK100) */
626 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
630 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
634 /* Enable phy interrupt on auto-negotiation complete (or link up) */
635 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
636 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
638 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
641 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
642 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
644 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
648 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
649 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
650 reg1 &= ~phy_power[port];
652 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > CHIP_REV_YU_XL_A1)
653 reg1 |= coma_mode[port];
655 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
656 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
657 sky2_pci_read32(hw, PCI_DEV_REG1);
659 if (hw->chip_id == CHIP_ID_YUKON_FE)
660 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
661 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
662 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
665 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
670 /* release GPHY Control reset */
671 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
673 /* release GMAC reset */
674 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
676 if (hw->flags & SKY2_HW_NEWER_PHY) {
677 /* select page 2 to access MAC control register */
678 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
680 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
681 /* allow GMII Power Down */
682 ctrl &= ~PHY_M_MAC_GMIF_PUP;
683 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
685 /* set page register back to 0 */
686 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
689 /* setup General Purpose Control Register */
690 gma_write16(hw, port, GM_GP_CTRL,
691 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
692 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
695 if (hw->chip_id != CHIP_ID_YUKON_EC) {
696 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
697 /* select page 2 to access MAC control register */
698 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
700 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
701 /* enable Power Down */
702 ctrl |= PHY_M_PC_POW_D_ENA;
703 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
705 /* set page register back to 0 */
706 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
709 /* set IEEE compatible Power Down Mode (dev. #4.99) */
710 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
713 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
714 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
715 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
716 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
717 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
720 /* Force a renegotiation */
721 static void sky2_phy_reinit(struct sky2_port *sky2)
723 spin_lock_bh(&sky2->phy_lock);
724 sky2_phy_init(sky2->hw, sky2->port);
725 spin_unlock_bh(&sky2->phy_lock);
728 /* Put device in state to listen for Wake On Lan */
729 static void sky2_wol_init(struct sky2_port *sky2)
731 struct sky2_hw *hw = sky2->hw;
732 unsigned port = sky2->port;
733 enum flow_control save_mode;
736 /* Bring hardware out of reset */
737 sky2_write16(hw, B0_CTST, CS_RST_CLR);
738 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
740 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
744 * sky2_reset will re-enable on resume
746 save_mode = sky2->flow_mode;
747 ctrl = sky2->advertising;
749 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
750 sky2->flow_mode = FC_NONE;
752 spin_lock_bh(&sky2->phy_lock);
753 sky2_phy_power_up(hw, port);
754 sky2_phy_init(hw, port);
755 spin_unlock_bh(&sky2->phy_lock);
757 sky2->flow_mode = save_mode;
758 sky2->advertising = ctrl;
760 /* Set GMAC to no flow control and auto update for speed/duplex */
761 gma_write16(hw, port, GM_GP_CTRL,
762 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
763 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
765 /* Set WOL address */
766 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
767 sky2->netdev->dev_addr, ETH_ALEN);
769 /* Turn on appropriate WOL control bits */
770 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
772 if (sky2->wol & WAKE_PHY)
773 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
775 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
777 if (sky2->wol & WAKE_MAGIC)
778 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
780 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
782 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
783 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
785 /* Disable PiG firmware */
786 sky2_write16(hw, B0_CTST, Y2_HW_WOL_OFF);
789 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
792 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
794 struct net_device *dev = hw->dev[port];
796 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
797 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
798 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
799 /* Yukon-Extreme B0 and further Extreme devices */
800 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
801 } else if (dev->mtu > ETH_DATA_LEN) {
802 /* set Tx GMAC FIFO Almost Empty Threshold */
803 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
804 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
806 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
808 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
811 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
813 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
817 const u8 *addr = hw->dev[port]->dev_addr;
819 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
820 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
822 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
824 if (hw->chip_id == CHIP_ID_YUKON_XL &&
825 hw->chip_rev == CHIP_REV_YU_XL_A0 &&
827 /* WA DEV_472 -- looks like crossed wires on port 2 */
828 /* clear GMAC 1 Control reset */
829 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
831 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
832 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
833 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
834 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
835 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
838 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
840 /* Enable Transmit FIFO Underrun */
841 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
843 spin_lock_bh(&sky2->phy_lock);
844 sky2_phy_power_up(hw, port);
845 sky2_phy_init(hw, port);
846 spin_unlock_bh(&sky2->phy_lock);
849 reg = gma_read16(hw, port, GM_PHY_ADDR);
850 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
852 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
853 gma_read16(hw, port, i);
854 gma_write16(hw, port, GM_PHY_ADDR, reg);
856 /* transmit control */
857 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
859 /* receive control reg: unicast + multicast + no FCS */
860 gma_write16(hw, port, GM_RX_CTRL,
861 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
863 /* transmit flow control */
864 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
866 /* transmit parameter */
867 gma_write16(hw, port, GM_TX_PARAM,
868 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
869 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
870 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
871 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
873 /* serial mode register */
874 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
875 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
877 if (hw->dev[port]->mtu > ETH_DATA_LEN)
878 reg |= GM_SMOD_JUMBO_ENA;
880 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
881 hw->chip_rev == CHIP_REV_YU_EC_U_B1)
882 reg |= GM_NEW_FLOW_CTRL;
884 gma_write16(hw, port, GM_SERIAL_MODE, reg);
886 /* virtual address for data */
887 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
889 /* physical address: used for pause frames */
890 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
892 /* ignore counter overflows */
893 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
894 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
895 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
897 /* Configure Rx MAC FIFO */
898 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
899 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
900 if (hw->chip_id == CHIP_ID_YUKON_EX ||
901 hw->chip_id == CHIP_ID_YUKON_FE_P)
902 rx_reg |= GMF_RX_OVER_ON;
904 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
906 if (hw->chip_id == CHIP_ID_YUKON_XL) {
907 /* Hardware errata - clear flush mask */
908 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
910 /* Flush Rx MAC FIFO on any flow control or error */
911 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
914 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
915 reg = RX_GMF_FL_THR_DEF + 1;
916 /* Another magic mystery workaround from sk98lin */
917 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
918 hw->chip_rev == CHIP_REV_YU_FE2_A0)
920 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
922 /* Configure Tx MAC FIFO */
923 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
924 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
926 /* On chips without ram buffer, pause is controled by MAC level */
927 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
928 /* Pause threshold is scaled by 8 in bytes */
929 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
930 hw->chip_rev == CHIP_REV_YU_FE2_A0)
934 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
935 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
937 sky2_set_tx_stfwd(hw, port);
940 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
941 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
942 /* disable dynamic watermark */
943 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
944 reg &= ~TX_DYN_WM_ENA;
945 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
949 /* Assign Ram Buffer allocation to queue */
950 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
954 /* convert from K bytes to qwords used for hw register */
957 end = start + space - 1;
959 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
960 sky2_write32(hw, RB_ADDR(q, RB_START), start);
961 sky2_write32(hw, RB_ADDR(q, RB_END), end);
962 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
963 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
965 if (q == Q_R1 || q == Q_R2) {
966 u32 tp = space - space/4;
968 /* On receive queue's set the thresholds
969 * give receiver priority when > 3/4 full
970 * send pause when down to 2K
972 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
973 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
976 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
977 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
979 /* Enable store & forward on Tx queue's because
980 * Tx FIFO is only 1K on Yukon
982 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
985 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
986 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
989 /* Setup Bus Memory Interface */
990 static void sky2_qset(struct sky2_hw *hw, u16 q)
992 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
993 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
994 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
995 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
998 /* Setup prefetch unit registers. This is the interface between
999 * hardware and driver list elements
1001 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1002 dma_addr_t addr, u32 last)
1004 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1005 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1006 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1007 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1008 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1009 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1011 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1014 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1016 struct sky2_tx_le *le = sky2->tx_le + *slot;
1018 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1023 static void tx_init(struct sky2_port *sky2)
1025 struct sky2_tx_le *le;
1027 sky2->tx_prod = sky2->tx_cons = 0;
1028 sky2->tx_tcpsum = 0;
1029 sky2->tx_last_mss = 0;
1031 le = get_tx_le(sky2, &sky2->tx_prod);
1033 le->opcode = OP_ADDR64 | HW_OWNER;
1034 sky2->tx_last_upper = 0;
1037 /* Update chip's next pointer */
1038 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1040 /* Make sure write' to descriptors are complete before we tell hardware */
1042 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1044 /* Synchronize I/O on since next processor may write to tail */
1049 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1051 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1052 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1057 static unsigned sky2_get_rx_threshold(struct sky2_port* sky2)
1061 /* Space needed for frame data + headers rounded up */
1062 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1064 /* Stopping point for hardware truncation */
1065 return (size - 8) / sizeof(u32);
1068 static unsigned sky2_get_rx_data_size(struct sky2_port* sky2)
1070 struct rx_ring_info *re;
1073 /* Space needed for frame data + headers rounded up */
1074 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1076 sky2->rx_nfrags = size >> PAGE_SHIFT;
1077 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1079 /* Compute residue after pages */
1080 size -= sky2->rx_nfrags << PAGE_SHIFT;
1082 /* Optimize to handle small packets and headers */
1083 if (size < copybreak)
1085 if (size < ETH_HLEN)
1091 /* Build description to hardware for one receive segment */
1092 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1093 dma_addr_t map, unsigned len)
1095 struct sky2_rx_le *le;
1097 if (sizeof(dma_addr_t) > sizeof(u32)) {
1098 le = sky2_next_rx(sky2);
1099 le->addr = cpu_to_le32(upper_32_bits(map));
1100 le->opcode = OP_ADDR64 | HW_OWNER;
1103 le = sky2_next_rx(sky2);
1104 le->addr = cpu_to_le32(lower_32_bits(map));
1105 le->length = cpu_to_le16(len);
1106 le->opcode = op | HW_OWNER;
1109 /* Build description to hardware for one possibly fragmented skb */
1110 static void sky2_rx_submit(struct sky2_port *sky2,
1111 const struct rx_ring_info *re)
1115 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1117 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1118 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1122 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1125 struct sk_buff *skb = re->skb;
1128 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1129 if (pci_dma_mapping_error(pdev, re->data_addr))
1132 dma_unmap_len_set(re, data_size, size);
1134 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1135 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1137 re->frag_addr[i] = pci_map_page(pdev, frag->page,
1140 PCI_DMA_FROMDEVICE);
1142 if (pci_dma_mapping_error(pdev, re->frag_addr[i]))
1143 goto map_page_error;
1149 pci_unmap_page(pdev, re->frag_addr[i],
1150 skb_shinfo(skb)->frags[i].size,
1151 PCI_DMA_FROMDEVICE);
1154 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1155 PCI_DMA_FROMDEVICE);
1158 if (net_ratelimit())
1159 dev_warn(&pdev->dev, "%s: rx mapping error\n",
1164 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1166 struct sk_buff *skb = re->skb;
1169 pci_unmap_single(pdev, re->data_addr, dma_unmap_len(re, data_size),
1170 PCI_DMA_FROMDEVICE);
1172 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1173 pci_unmap_page(pdev, re->frag_addr[i],
1174 skb_shinfo(skb)->frags[i].size,
1175 PCI_DMA_FROMDEVICE);
1178 /* Tell chip where to start receive checksum.
1179 * Actually has two checksums, but set both same to avoid possible byte
1182 static void rx_set_checksum(struct sky2_port *sky2)
1184 struct sky2_rx_le *le = sky2_next_rx(sky2);
1186 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1188 le->opcode = OP_TCPSTART | HW_OWNER;
1190 sky2_write32(sky2->hw,
1191 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1192 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1193 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1196 /* Enable/disable receive hash calculation (RSS) */
1197 static void rx_set_rss(struct net_device *dev)
1199 struct sky2_port *sky2 = netdev_priv(dev);
1200 struct sky2_hw *hw = sky2->hw;
1203 /* Supports IPv6 and other modes */
1204 if (hw->flags & SKY2_HW_NEW_LE) {
1206 sky2_write32(hw, SK_REG(sky2->port, RSS_CFG), HASH_ALL);
1209 /* Program RSS initial values */
1210 if (dev->features & NETIF_F_RXHASH) {
1213 get_random_bytes(key, nkeys * sizeof(u32));
1214 for (i = 0; i < nkeys; i++)
1215 sky2_write32(hw, SK_REG(sky2->port, RSS_KEY + i * 4),
1218 /* Need to turn on (undocumented) flag to make hashing work */
1219 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T),
1222 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1223 BMU_ENA_RX_RSS_HASH);
1225 sky2_write32(hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1226 BMU_DIS_RX_RSS_HASH);
1230 * The RX Stop command will not work for Yukon-2 if the BMU does not
1231 * reach the end of packet and since we can't make sure that we have
1232 * incoming data, we must reset the BMU while it is not doing a DMA
1233 * transfer. Since it is possible that the RX path is still active,
1234 * the RX RAM buffer will be stopped first, so any possible incoming
1235 * data will not trigger a DMA. After the RAM buffer is stopped, the
1236 * BMU is polled until any DMA in progress is ended and only then it
1239 static void sky2_rx_stop(struct sky2_port *sky2)
1241 struct sky2_hw *hw = sky2->hw;
1242 unsigned rxq = rxqaddr[sky2->port];
1245 /* disable the RAM Buffer receive queue */
1246 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1248 for (i = 0; i < 0xffff; i++)
1249 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1250 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1253 netdev_warn(sky2->netdev, "receiver stop failed\n");
1255 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1257 /* reset the Rx prefetch unit */
1258 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1262 /* Clean out receive buffer area, assumes receiver hardware stopped */
1263 static void sky2_rx_clean(struct sky2_port *sky2)
1267 memset(sky2->rx_le, 0, RX_LE_BYTES);
1268 for (i = 0; i < sky2->rx_pending; i++) {
1269 struct rx_ring_info *re = sky2->rx_ring + i;
1272 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1279 /* Basic MII support */
1280 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1282 struct mii_ioctl_data *data = if_mii(ifr);
1283 struct sky2_port *sky2 = netdev_priv(dev);
1284 struct sky2_hw *hw = sky2->hw;
1285 int err = -EOPNOTSUPP;
1287 if (!netif_running(dev))
1288 return -ENODEV; /* Phy still in reset */
1292 data->phy_id = PHY_ADDR_MARV;
1298 spin_lock_bh(&sky2->phy_lock);
1299 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1300 spin_unlock_bh(&sky2->phy_lock);
1302 data->val_out = val;
1307 spin_lock_bh(&sky2->phy_lock);
1308 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1310 spin_unlock_bh(&sky2->phy_lock);
1316 #ifdef SKY2_VLAN_TAG_USED
1317 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1320 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1322 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1325 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1327 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1332 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1334 struct sky2_port *sky2 = netdev_priv(dev);
1335 struct sky2_hw *hw = sky2->hw;
1336 u16 port = sky2->port;
1338 netif_tx_lock_bh(dev);
1339 napi_disable(&hw->napi);
1342 sky2_set_vlan_mode(hw, port, grp != NULL);
1344 sky2_read32(hw, B0_Y2_SP_LISR);
1345 napi_enable(&hw->napi);
1346 netif_tx_unlock_bh(dev);
1350 /* Amount of required worst case padding in rx buffer */
1351 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1353 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1357 * Allocate an skb for receiving. If the MTU is large enough
1358 * make the skb non-linear with a fragment list of pages.
1360 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1362 struct sk_buff *skb;
1365 skb = netdev_alloc_skb(sky2->netdev,
1366 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1370 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1371 unsigned char *start;
1373 * Workaround for a bug in FIFO that cause hang
1374 * if the FIFO if the receive buffer is not 64 byte aligned.
1375 * The buffer returned from netdev_alloc_skb is
1376 * aligned except if slab debugging is enabled.
1378 start = PTR_ALIGN(skb->data, 8);
1379 skb_reserve(skb, start - skb->data);
1381 skb_reserve(skb, NET_IP_ALIGN);
1383 for (i = 0; i < sky2->rx_nfrags; i++) {
1384 struct page *page = alloc_page(GFP_ATOMIC);
1388 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1398 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1400 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1403 static int sky2_alloc_rx_skbs(struct sky2_port *sky2)
1405 struct sky2_hw *hw = sky2->hw;
1408 sky2->rx_data_size = sky2_get_rx_data_size(sky2);
1411 for (i = 0; i < sky2->rx_pending; i++) {
1412 struct rx_ring_info *re = sky2->rx_ring + i;
1414 re->skb = sky2_rx_alloc(sky2);
1418 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1419 dev_kfree_skb(re->skb);
1428 * Setup receiver buffer pool.
1429 * Normal case this ends up creating one list element for skb
1430 * in the receive ring. Worst case if using large MTU and each
1431 * allocation falls on a different 64 bit region, that results
1432 * in 6 list elements per ring entry.
1433 * One element is used for checksum enable/disable, and one
1434 * extra to avoid wrap.
1436 static void sky2_rx_start(struct sky2_port *sky2)
1438 struct sky2_hw *hw = sky2->hw;
1439 struct rx_ring_info *re;
1440 unsigned rxq = rxqaddr[sky2->port];
1443 sky2->rx_put = sky2->rx_next = 0;
1446 /* On PCI express lowering the watermark gives better performance */
1447 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1448 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1450 /* These chips have no ram buffer?
1451 * MAC Rx RAM Read is controlled by hardware */
1452 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1453 hw->chip_rev > CHIP_REV_YU_EC_U_A0)
1454 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1456 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1458 if (!(hw->flags & SKY2_HW_NEW_LE))
1459 rx_set_checksum(sky2);
1461 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
1462 rx_set_rss(sky2->netdev);
1464 /* submit Rx ring */
1465 for (i = 0; i < sky2->rx_pending; i++) {
1466 re = sky2->rx_ring + i;
1467 sky2_rx_submit(sky2, re);
1471 * The receiver hangs if it receives frames larger than the
1472 * packet buffer. As a workaround, truncate oversize frames, but
1473 * the register is limited to 9 bits, so if you do frames > 2052
1474 * you better get the MTU right!
1476 thresh = sky2_get_rx_threshold(sky2);
1478 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1480 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1481 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1484 /* Tell chip about available buffers */
1485 sky2_rx_update(sky2, rxq);
1487 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1488 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1490 * Disable flushing of non ASF packets;
1491 * must be done after initializing the BMUs;
1492 * drivers without ASF support should do this too, otherwise
1493 * it may happen that they cannot run on ASF devices;
1494 * remember that the MAC FIFO isn't reset during initialization.
1496 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1499 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1500 /* Enable RX Home Address & Routing Header checksum fix */
1501 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1502 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1504 /* Enable TX Home Address & Routing Header checksum fix */
1505 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1506 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1510 static int sky2_alloc_buffers(struct sky2_port *sky2)
1512 struct sky2_hw *hw = sky2->hw;
1514 /* must be power of 2 */
1515 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1516 sky2->tx_ring_size *
1517 sizeof(struct sky2_tx_le),
1522 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1527 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1531 memset(sky2->rx_le, 0, RX_LE_BYTES);
1533 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1538 return sky2_alloc_rx_skbs(sky2);
1543 static void sky2_free_buffers(struct sky2_port *sky2)
1545 struct sky2_hw *hw = sky2->hw;
1547 sky2_rx_clean(sky2);
1550 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1551 sky2->rx_le, sky2->rx_le_map);
1555 pci_free_consistent(hw->pdev,
1556 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1557 sky2->tx_le, sky2->tx_le_map);
1560 kfree(sky2->tx_ring);
1561 kfree(sky2->rx_ring);
1563 sky2->tx_ring = NULL;
1564 sky2->rx_ring = NULL;
1567 static void sky2_hw_up(struct sky2_port *sky2)
1569 struct sky2_hw *hw = sky2->hw;
1570 unsigned port = sky2->port;
1573 struct net_device *otherdev = hw->dev[sky2->port^1];
1578 * On dual port PCI-X card, there is an problem where status
1579 * can be received out of order due to split transactions
1581 if (otherdev && netif_running(otherdev) &&
1582 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1585 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1586 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1587 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1590 sky2_mac_init(hw, port);
1592 /* Register is number of 4K blocks on internal RAM buffer. */
1593 ramsize = sky2_read8(hw, B2_E_0) * 4;
1597 netdev_dbg(sky2->netdev, "ram buffer %dK\n", ramsize);
1599 rxspace = ramsize / 2;
1601 rxspace = 8 + (2*(ramsize - 16))/3;
1603 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1604 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1606 /* Make sure SyncQ is disabled */
1607 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1611 sky2_qset(hw, txqaddr[port]);
1613 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1614 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1615 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1617 /* Set almost empty threshold */
1618 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1619 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1620 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1622 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1623 sky2->tx_ring_size - 1);
1625 #ifdef SKY2_VLAN_TAG_USED
1626 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1629 sky2_rx_start(sky2);
1632 /* Bring up network interface. */
1633 static int sky2_up(struct net_device *dev)
1635 struct sky2_port *sky2 = netdev_priv(dev);
1636 struct sky2_hw *hw = sky2->hw;
1637 unsigned port = sky2->port;
1641 netif_carrier_off(dev);
1643 err = sky2_alloc_buffers(sky2);
1649 /* Enable interrupts from phy/mac for port */
1650 imask = sky2_read32(hw, B0_IMSK);
1651 imask |= portirq_msk[port];
1652 sky2_write32(hw, B0_IMSK, imask);
1653 sky2_read32(hw, B0_IMSK);
1655 netif_info(sky2, ifup, dev, "enabling interface\n");
1660 sky2_free_buffers(sky2);
1664 /* Modular subtraction in ring */
1665 static inline int tx_inuse(const struct sky2_port *sky2)
1667 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1670 /* Number of list elements available for next tx */
1671 static inline int tx_avail(const struct sky2_port *sky2)
1673 return sky2->tx_pending - tx_inuse(sky2);
1676 /* Estimate of number of transmit list elements required */
1677 static unsigned tx_le_req(const struct sk_buff *skb)
1681 count = (skb_shinfo(skb)->nr_frags + 1)
1682 * (sizeof(dma_addr_t) / sizeof(u32));
1684 if (skb_is_gso(skb))
1686 else if (sizeof(dma_addr_t) == sizeof(u32))
1687 ++count; /* possible vlan */
1689 if (skb->ip_summed == CHECKSUM_PARTIAL)
1695 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1697 if (re->flags & TX_MAP_SINGLE)
1698 pci_unmap_single(pdev, dma_unmap_addr(re, mapaddr),
1699 dma_unmap_len(re, maplen),
1701 else if (re->flags & TX_MAP_PAGE)
1702 pci_unmap_page(pdev, dma_unmap_addr(re, mapaddr),
1703 dma_unmap_len(re, maplen),
1709 * Put one packet in ring for transmit.
1710 * A single packet can generate multiple list elements, and
1711 * the number of ring elements will probably be less than the number
1712 * of list elements used.
1714 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1715 struct net_device *dev)
1717 struct sky2_port *sky2 = netdev_priv(dev);
1718 struct sky2_hw *hw = sky2->hw;
1719 struct sky2_tx_le *le = NULL;
1720 struct tx_ring_info *re;
1728 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1729 return NETDEV_TX_BUSY;
1731 len = skb_headlen(skb);
1732 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1734 if (pci_dma_mapping_error(hw->pdev, mapping))
1737 slot = sky2->tx_prod;
1738 netif_printk(sky2, tx_queued, KERN_DEBUG, dev,
1739 "tx queued, slot %u, len %d\n", slot, skb->len);
1741 /* Send high bits if needed */
1742 upper = upper_32_bits(mapping);
1743 if (upper != sky2->tx_last_upper) {
1744 le = get_tx_le(sky2, &slot);
1745 le->addr = cpu_to_le32(upper);
1746 sky2->tx_last_upper = upper;
1747 le->opcode = OP_ADDR64 | HW_OWNER;
1750 /* Check for TCP Segmentation Offload */
1751 mss = skb_shinfo(skb)->gso_size;
1754 if (!(hw->flags & SKY2_HW_NEW_LE))
1755 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1757 if (mss != sky2->tx_last_mss) {
1758 le = get_tx_le(sky2, &slot);
1759 le->addr = cpu_to_le32(mss);
1761 if (hw->flags & SKY2_HW_NEW_LE)
1762 le->opcode = OP_MSS | HW_OWNER;
1764 le->opcode = OP_LRGLEN | HW_OWNER;
1765 sky2->tx_last_mss = mss;
1770 #ifdef SKY2_VLAN_TAG_USED
1771 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1772 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1774 le = get_tx_le(sky2, &slot);
1776 le->opcode = OP_VLAN|HW_OWNER;
1778 le->opcode |= OP_VLAN;
1779 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1784 /* Handle TCP checksum offload */
1785 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1786 /* On Yukon EX (some versions) encoding change. */
1787 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1788 ctrl |= CALSUM; /* auto checksum */
1790 const unsigned offset = skb_transport_offset(skb);
1793 tcpsum = offset << 16; /* sum start */
1794 tcpsum |= offset + skb->csum_offset; /* sum write */
1796 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1797 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1800 if (tcpsum != sky2->tx_tcpsum) {
1801 sky2->tx_tcpsum = tcpsum;
1803 le = get_tx_le(sky2, &slot);
1804 le->addr = cpu_to_le32(tcpsum);
1805 le->length = 0; /* initial checksum value */
1806 le->ctrl = 1; /* one packet */
1807 le->opcode = OP_TCPLISW | HW_OWNER;
1812 re = sky2->tx_ring + slot;
1813 re->flags = TX_MAP_SINGLE;
1814 dma_unmap_addr_set(re, mapaddr, mapping);
1815 dma_unmap_len_set(re, maplen, len);
1817 le = get_tx_le(sky2, &slot);
1818 le->addr = cpu_to_le32(lower_32_bits(mapping));
1819 le->length = cpu_to_le16(len);
1821 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1824 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1825 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1827 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1828 frag->size, PCI_DMA_TODEVICE);
1830 if (pci_dma_mapping_error(hw->pdev, mapping))
1831 goto mapping_unwind;
1833 upper = upper_32_bits(mapping);
1834 if (upper != sky2->tx_last_upper) {
1835 le = get_tx_le(sky2, &slot);
1836 le->addr = cpu_to_le32(upper);
1837 sky2->tx_last_upper = upper;
1838 le->opcode = OP_ADDR64 | HW_OWNER;
1841 re = sky2->tx_ring + slot;
1842 re->flags = TX_MAP_PAGE;
1843 dma_unmap_addr_set(re, mapaddr, mapping);
1844 dma_unmap_len_set(re, maplen, frag->size);
1846 le = get_tx_le(sky2, &slot);
1847 le->addr = cpu_to_le32(lower_32_bits(mapping));
1848 le->length = cpu_to_le16(frag->size);
1850 le->opcode = OP_BUFFER | HW_OWNER;
1856 sky2->tx_prod = slot;
1858 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1859 netif_stop_queue(dev);
1861 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1863 return NETDEV_TX_OK;
1866 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1867 re = sky2->tx_ring + i;
1869 sky2_tx_unmap(hw->pdev, re);
1873 if (net_ratelimit())
1874 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1876 return NETDEV_TX_OK;
1880 * Free ring elements from starting at tx_cons until "done"
1883 * 1. The hardware will tell us about partial completion of multi-part
1884 * buffers so make sure not to free skb to early.
1885 * 2. This may run in parallel start_xmit because the it only
1886 * looks at the tail of the queue of FIFO (tx_cons), not
1887 * the head (tx_prod)
1889 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1891 struct net_device *dev = sky2->netdev;
1894 BUG_ON(done >= sky2->tx_ring_size);
1896 for (idx = sky2->tx_cons; idx != done;
1897 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1898 struct tx_ring_info *re = sky2->tx_ring + idx;
1899 struct sk_buff *skb = re->skb;
1901 sky2_tx_unmap(sky2->hw->pdev, re);
1904 netif_printk(sky2, tx_done, KERN_DEBUG, dev,
1905 "tx done %u\n", idx);
1907 dev->stats.tx_packets++;
1908 dev->stats.tx_bytes += skb->len;
1911 dev_kfree_skb_any(skb);
1913 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1917 sky2->tx_cons = idx;
1921 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1923 /* Disable Force Sync bit and Enable Alloc bit */
1924 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1925 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1927 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1928 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1929 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1931 /* Reset the PCI FIFO of the async Tx queue */
1932 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1933 BMU_RST_SET | BMU_FIFO_RST);
1935 /* Reset the Tx prefetch units */
1936 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1939 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1940 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1943 static void sky2_hw_down(struct sky2_port *sky2)
1945 struct sky2_hw *hw = sky2->hw;
1946 unsigned port = sky2->port;
1949 /* Force flow control off */
1950 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1952 /* Stop transmitter */
1953 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1954 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1956 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1957 RB_RST_SET | RB_DIS_OP_MD);
1959 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1960 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1961 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1963 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1965 /* Workaround shared GMAC reset */
1966 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1967 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1968 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1970 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1972 /* Force any delayed status interrrupt and NAPI */
1973 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1974 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1975 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1976 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1980 spin_lock_bh(&sky2->phy_lock);
1981 sky2_phy_power_down(hw, port);
1982 spin_unlock_bh(&sky2->phy_lock);
1984 sky2_tx_reset(hw, port);
1986 /* Free any pending frames stuck in HW queue */
1987 sky2_tx_complete(sky2, sky2->tx_prod);
1990 /* Network shutdown */
1991 static int sky2_down(struct net_device *dev)
1993 struct sky2_port *sky2 = netdev_priv(dev);
1994 struct sky2_hw *hw = sky2->hw;
1996 /* Never really got started! */
2000 netif_info(sky2, ifdown, dev, "disabling interface\n");
2002 /* Disable port IRQ */
2003 sky2_write32(hw, B0_IMSK,
2004 sky2_read32(hw, B0_IMSK) & ~portirq_msk[sky2->port]);
2005 sky2_read32(hw, B0_IMSK);
2007 synchronize_irq(hw->pdev->irq);
2008 napi_synchronize(&hw->napi);
2012 sky2_free_buffers(sky2);
2017 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
2019 if (hw->flags & SKY2_HW_FIBRE_PHY)
2022 if (!(hw->flags & SKY2_HW_GIGABIT)) {
2023 if (aux & PHY_M_PS_SPEED_100)
2029 switch (aux & PHY_M_PS_SPEED_MSK) {
2030 case PHY_M_PS_SPEED_1000:
2032 case PHY_M_PS_SPEED_100:
2039 static void sky2_link_up(struct sky2_port *sky2)
2041 struct sky2_hw *hw = sky2->hw;
2042 unsigned port = sky2->port;
2044 static const char *fc_name[] = {
2052 reg = gma_read16(hw, port, GM_GP_CTRL);
2053 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2054 gma_write16(hw, port, GM_GP_CTRL, reg);
2056 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
2058 netif_carrier_on(sky2->netdev);
2060 mod_timer(&hw->watchdog_timer, jiffies + 1);
2062 /* Turn on link LED */
2063 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
2064 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
2066 netif_info(sky2, link, sky2->netdev,
2067 "Link is up at %d Mbps, %s duplex, flow control %s\n",
2069 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2070 fc_name[sky2->flow_status]);
2073 static void sky2_link_down(struct sky2_port *sky2)
2075 struct sky2_hw *hw = sky2->hw;
2076 unsigned port = sky2->port;
2079 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2081 reg = gma_read16(hw, port, GM_GP_CTRL);
2082 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2083 gma_write16(hw, port, GM_GP_CTRL, reg);
2085 netif_carrier_off(sky2->netdev);
2087 /* Turn off link LED */
2088 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2090 netif_info(sky2, link, sky2->netdev, "Link is down\n");
2092 sky2_phy_init(hw, port);
2095 static enum flow_control sky2_flow(int rx, int tx)
2098 return tx ? FC_BOTH : FC_RX;
2100 return tx ? FC_TX : FC_NONE;
2103 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2105 struct sky2_hw *hw = sky2->hw;
2106 unsigned port = sky2->port;
2109 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2110 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2111 if (lpa & PHY_M_AN_RF) {
2112 netdev_err(sky2->netdev, "remote fault\n");
2116 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2117 netdev_err(sky2->netdev, "speed/duplex mismatch\n");
2121 sky2->speed = sky2_phy_speed(hw, aux);
2122 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2124 /* Since the pause result bits seem to in different positions on
2125 * different chips. look at registers.
2127 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2128 /* Shift for bits in fiber PHY */
2129 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2130 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2132 if (advert & ADVERTISE_1000XPAUSE)
2133 advert |= ADVERTISE_PAUSE_CAP;
2134 if (advert & ADVERTISE_1000XPSE_ASYM)
2135 advert |= ADVERTISE_PAUSE_ASYM;
2136 if (lpa & LPA_1000XPAUSE)
2137 lpa |= LPA_PAUSE_CAP;
2138 if (lpa & LPA_1000XPAUSE_ASYM)
2139 lpa |= LPA_PAUSE_ASYM;
2142 sky2->flow_status = FC_NONE;
2143 if (advert & ADVERTISE_PAUSE_CAP) {
2144 if (lpa & LPA_PAUSE_CAP)
2145 sky2->flow_status = FC_BOTH;
2146 else if (advert & ADVERTISE_PAUSE_ASYM)
2147 sky2->flow_status = FC_RX;
2148 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2149 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2150 sky2->flow_status = FC_TX;
2153 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2154 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2155 sky2->flow_status = FC_NONE;
2157 if (sky2->flow_status & FC_TX)
2158 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2160 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2165 /* Interrupt from PHY */
2166 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2168 struct net_device *dev = hw->dev[port];
2169 struct sky2_port *sky2 = netdev_priv(dev);
2170 u16 istatus, phystat;
2172 if (!netif_running(dev))
2175 spin_lock(&sky2->phy_lock);
2176 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2177 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2179 netif_info(sky2, intr, sky2->netdev, "phy interrupt status 0x%x 0x%x\n",
2182 if (istatus & PHY_M_IS_AN_COMPL) {
2183 if (sky2_autoneg_done(sky2, phystat) == 0 &&
2184 !netif_carrier_ok(dev))
2189 if (istatus & PHY_M_IS_LSP_CHANGE)
2190 sky2->speed = sky2_phy_speed(hw, phystat);
2192 if (istatus & PHY_M_IS_DUP_CHANGE)
2194 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2196 if (istatus & PHY_M_IS_LST_CHANGE) {
2197 if (phystat & PHY_M_PS_LINK_UP)
2200 sky2_link_down(sky2);
2203 spin_unlock(&sky2->phy_lock);
2206 /* Special quick link interrupt (Yukon-2 Optima only) */
2207 static void sky2_qlink_intr(struct sky2_hw *hw)
2209 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2214 imask = sky2_read32(hw, B0_IMSK);
2215 imask &= ~Y2_IS_PHY_QLNK;
2216 sky2_write32(hw, B0_IMSK, imask);
2218 /* reset PHY Link Detect */
2219 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2220 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2221 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2222 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2227 /* Transmit timeout is only called if we are running, carrier is up
2228 * and tx queue is full (stopped).
2230 static void sky2_tx_timeout(struct net_device *dev)
2232 struct sky2_port *sky2 = netdev_priv(dev);
2233 struct sky2_hw *hw = sky2->hw;
2235 netif_err(sky2, timer, dev, "tx timeout\n");
2237 netdev_printk(KERN_DEBUG, dev, "transmit ring %u .. %u report=%u done=%u\n",
2238 sky2->tx_cons, sky2->tx_prod,
2239 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2240 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2242 /* can't restart safely under softirq */
2243 schedule_work(&hw->restart_work);
2246 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2248 struct sky2_port *sky2 = netdev_priv(dev);
2249 struct sky2_hw *hw = sky2->hw;
2250 unsigned port = sky2->port;
2255 /* MTU size outside the spec */
2256 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2259 /* MTU > 1500 on yukon FE and FE+ not allowed */
2260 if (new_mtu > ETH_DATA_LEN &&
2261 (hw->chip_id == CHIP_ID_YUKON_FE ||
2262 hw->chip_id == CHIP_ID_YUKON_FE_P))
2265 /* TSO, etc on Yukon Ultra and MTU > 1500 not supported */
2266 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U)
2267 dev->features &= ~(NETIF_F_TSO|NETIF_F_SG|NETIF_F_ALL_CSUM);
2269 if (!netif_running(dev)) {
2274 imask = sky2_read32(hw, B0_IMSK);
2275 sky2_write32(hw, B0_IMSK, 0);
2277 dev->trans_start = jiffies; /* prevent tx timeout */
2278 netif_stop_queue(dev);
2279 napi_disable(&hw->napi);
2281 synchronize_irq(hw->pdev->irq);
2283 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2284 sky2_set_tx_stfwd(hw, port);
2286 ctl = gma_read16(hw, port, GM_GP_CTRL);
2287 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2289 sky2_rx_clean(sky2);
2293 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2294 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2296 if (dev->mtu > ETH_DATA_LEN)
2297 mode |= GM_SMOD_JUMBO_ENA;
2299 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2301 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2303 err = sky2_alloc_rx_skbs(sky2);
2305 sky2_rx_start(sky2);
2307 sky2_rx_clean(sky2);
2308 sky2_write32(hw, B0_IMSK, imask);
2310 sky2_read32(hw, B0_Y2_SP_LISR);
2311 napi_enable(&hw->napi);
2316 gma_write16(hw, port, GM_GP_CTRL, ctl);
2318 netif_wake_queue(dev);
2324 /* For small just reuse existing skb for next receive */
2325 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2326 const struct rx_ring_info *re,
2329 struct sk_buff *skb;
2331 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2333 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2334 length, PCI_DMA_FROMDEVICE);
2335 skb_copy_from_linear_data(re->skb, skb->data, length);
2336 skb->ip_summed = re->skb->ip_summed;
2337 skb->csum = re->skb->csum;
2338 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2339 length, PCI_DMA_FROMDEVICE);
2340 re->skb->ip_summed = CHECKSUM_NONE;
2341 skb_put(skb, length);
2346 /* Adjust length of skb with fragments to match received data */
2347 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2348 unsigned int length)
2353 /* put header into skb */
2354 size = min(length, hdr_space);
2359 num_frags = skb_shinfo(skb)->nr_frags;
2360 for (i = 0; i < num_frags; i++) {
2361 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2364 /* don't need this page */
2365 __free_page(frag->page);
2366 --skb_shinfo(skb)->nr_frags;
2368 size = min(length, (unsigned) PAGE_SIZE);
2371 skb->data_len += size;
2372 skb->truesize += size;
2379 /* Normal packet - take skb from ring element and put in a new one */
2380 static struct sk_buff *receive_new(struct sky2_port *sky2,
2381 struct rx_ring_info *re,
2382 unsigned int length)
2384 struct sk_buff *skb;
2385 struct rx_ring_info nre;
2386 unsigned hdr_space = sky2->rx_data_size;
2388 nre.skb = sky2_rx_alloc(sky2);
2389 if (unlikely(!nre.skb))
2392 if (sky2_rx_map_skb(sky2->hw->pdev, &nre, hdr_space))
2396 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2397 prefetch(skb->data);
2400 if (skb_shinfo(skb)->nr_frags)
2401 skb_put_frags(skb, hdr_space, length);
2403 skb_put(skb, length);
2407 dev_kfree_skb(nre.skb);
2413 * Receive one packet.
2414 * For larger packets, get new buffer.
2416 static struct sk_buff *sky2_receive(struct net_device *dev,
2417 u16 length, u32 status)
2419 struct sky2_port *sky2 = netdev_priv(dev);
2420 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2421 struct sk_buff *skb = NULL;
2422 u16 count = (status & GMR_FS_LEN) >> 16;
2424 #ifdef SKY2_VLAN_TAG_USED
2425 /* Account for vlan tag */
2426 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2430 netif_printk(sky2, rx_status, KERN_DEBUG, dev,
2431 "rx slot %u status 0x%x len %d\n",
2432 sky2->rx_next, status, length);
2434 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2435 prefetch(sky2->rx_ring + sky2->rx_next);
2437 /* This chip has hardware problems that generates bogus status.
2438 * So do only marginal checking and expect higher level protocols
2439 * to handle crap frames.
2441 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2442 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2446 if (status & GMR_FS_ANY_ERR)
2449 if (!(status & GMR_FS_RX_OK))
2452 /* if length reported by DMA does not match PHY, packet was truncated */
2453 if (length != count)
2457 if (length < copybreak)
2458 skb = receive_copy(sky2, re, length);
2460 skb = receive_new(sky2, re, length);
2462 dev->stats.rx_dropped += (skb == NULL);
2465 sky2_rx_submit(sky2, re);
2470 /* Truncation of overlength packets
2471 causes PHY length to not match MAC length */
2472 ++dev->stats.rx_length_errors;
2473 if (net_ratelimit())
2474 netif_info(sky2, rx_err, dev,
2475 "rx length error: status %#x length %d\n",
2480 ++dev->stats.rx_errors;
2481 if (status & GMR_FS_RX_FF_OV) {
2482 dev->stats.rx_over_errors++;
2486 if (net_ratelimit())
2487 netif_info(sky2, rx_err, dev,
2488 "rx error, status 0x%x length %d\n", status, length);
2490 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2491 dev->stats.rx_length_errors++;
2492 if (status & GMR_FS_FRAGMENT)
2493 dev->stats.rx_frame_errors++;
2494 if (status & GMR_FS_CRC_ERR)
2495 dev->stats.rx_crc_errors++;
2500 /* Transmit complete */
2501 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2503 struct sky2_port *sky2 = netdev_priv(dev);
2505 if (netif_running(dev)) {
2506 sky2_tx_complete(sky2, last);
2508 /* Wake unless it's detached, and called e.g. from sky2_down() */
2509 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
2510 netif_wake_queue(dev);
2514 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2515 u32 status, struct sk_buff *skb)
2517 #ifdef SKY2_VLAN_TAG_USED
2518 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2519 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2520 if (skb->ip_summed == CHECKSUM_NONE)
2521 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2523 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2528 if (skb->ip_summed == CHECKSUM_NONE)
2529 netif_receive_skb(skb);
2531 napi_gro_receive(&sky2->hw->napi, skb);
2534 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2535 unsigned packets, unsigned bytes)
2538 struct net_device *dev = hw->dev[port];
2540 dev->stats.rx_packets += packets;
2541 dev->stats.rx_bytes += bytes;
2542 dev->last_rx = jiffies;
2543 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2547 static void sky2_rx_checksum(struct sky2_port *sky2, u32 status)
2549 /* If this happens then driver assuming wrong format for chip type */
2550 BUG_ON(sky2->hw->flags & SKY2_HW_NEW_LE);
2552 /* Both checksum counters are programmed to start at
2553 * the same offset, so unless there is a problem they
2554 * should match. This failure is an early indication that
2555 * hardware receive checksumming won't work.
2557 if (likely((u16)(status >> 16) == (u16)status)) {
2558 struct sk_buff *skb = sky2->rx_ring[sky2->rx_next].skb;
2559 skb->ip_summed = CHECKSUM_COMPLETE;
2560 skb->csum = le16_to_cpu(status);
2562 dev_notice(&sky2->hw->pdev->dev,
2563 "%s: receive checksum problem (status = %#x)\n",
2564 sky2->netdev->name, status);
2566 /* Disable checksum offload */
2567 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2568 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2573 static void sky2_rx_hash(struct sky2_port *sky2, u32 status)
2575 struct sk_buff *skb;
2577 skb = sky2->rx_ring[sky2->rx_next].skb;
2578 skb->rxhash = le32_to_cpu(status);
2581 /* Process status response ring */
2582 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2585 unsigned int total_bytes[2] = { 0 };
2586 unsigned int total_packets[2] = { 0 };
2590 struct sky2_port *sky2;
2591 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2593 struct net_device *dev;
2594 struct sk_buff *skb;
2597 u8 opcode = le->opcode;
2599 if (!(opcode & HW_OWNER))
2602 hw->st_idx = RING_NEXT(hw->st_idx, hw->st_size);
2604 port = le->css & CSS_LINK_BIT;
2605 dev = hw->dev[port];
2606 sky2 = netdev_priv(dev);
2607 length = le16_to_cpu(le->length);
2608 status = le32_to_cpu(le->status);
2611 switch (opcode & ~HW_OWNER) {
2613 total_packets[port]++;
2614 total_bytes[port] += length;
2616 skb = sky2_receive(dev, length, status);
2620 /* This chip reports checksum status differently */
2621 if (hw->flags & SKY2_HW_NEW_LE) {
2622 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2623 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2624 (le->css & CSS_TCPUDPCSOK))
2625 skb->ip_summed = CHECKSUM_UNNECESSARY;
2627 skb->ip_summed = CHECKSUM_NONE;
2630 skb->protocol = eth_type_trans(skb, dev);
2632 sky2_skb_rx(sky2, status, skb);
2634 /* Stop after net poll weight */
2635 if (++work_done >= to_do)
2639 #ifdef SKY2_VLAN_TAG_USED
2641 sky2->rx_tag = length;
2645 sky2->rx_tag = length;
2649 if (likely(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2650 sky2_rx_checksum(sky2, status);
2654 sky2_rx_hash(sky2, status);
2658 /* TX index reports status for both ports */
2659 sky2_tx_done(hw->dev[0], status & 0xfff);
2661 sky2_tx_done(hw->dev[1],
2662 ((status >> 24) & 0xff)
2663 | (u16)(length & 0xf) << 8);
2667 if (net_ratelimit())
2668 pr_warning("unknown status opcode 0x%x\n", opcode);
2670 } while (hw->st_idx != idx);
2672 /* Fully processed status ring so clear irq */
2673 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2676 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2677 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2682 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2684 struct net_device *dev = hw->dev[port];
2686 if (net_ratelimit())
2687 netdev_info(dev, "hw error interrupt status 0x%x\n", status);
2689 if (status & Y2_IS_PAR_RD1) {
2690 if (net_ratelimit())
2691 netdev_err(dev, "ram data read parity error\n");
2693 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2696 if (status & Y2_IS_PAR_WR1) {
2697 if (net_ratelimit())
2698 netdev_err(dev, "ram data write parity error\n");
2700 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2703 if (status & Y2_IS_PAR_MAC1) {
2704 if (net_ratelimit())
2705 netdev_err(dev, "MAC parity error\n");
2706 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2709 if (status & Y2_IS_PAR_RX1) {
2710 if (net_ratelimit())
2711 netdev_err(dev, "RX parity error\n");
2712 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2715 if (status & Y2_IS_TCP_TXA1) {
2716 if (net_ratelimit())
2717 netdev_err(dev, "TCP segmentation error\n");
2718 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2722 static void sky2_hw_intr(struct sky2_hw *hw)
2724 struct pci_dev *pdev = hw->pdev;
2725 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2726 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2730 if (status & Y2_IS_TIST_OV)
2731 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2733 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2736 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2737 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2738 if (net_ratelimit())
2739 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2742 sky2_pci_write16(hw, PCI_STATUS,
2743 pci_err | PCI_STATUS_ERROR_BITS);
2744 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2747 if (status & Y2_IS_PCI_EXP) {
2748 /* PCI-Express uncorrectable Error occurred */
2751 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2752 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2753 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2755 if (net_ratelimit())
2756 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2758 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2759 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2762 if (status & Y2_HWE_L1_MASK)
2763 sky2_hw_error(hw, 0, status);
2765 if (status & Y2_HWE_L1_MASK)
2766 sky2_hw_error(hw, 1, status);
2769 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2771 struct net_device *dev = hw->dev[port];
2772 struct sky2_port *sky2 = netdev_priv(dev);
2773 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2775 netif_info(sky2, intr, dev, "mac interrupt status 0x%x\n", status);
2777 if (status & GM_IS_RX_CO_OV)
2778 gma_read16(hw, port, GM_RX_IRQ_SRC);
2780 if (status & GM_IS_TX_CO_OV)
2781 gma_read16(hw, port, GM_TX_IRQ_SRC);
2783 if (status & GM_IS_RX_FF_OR) {
2784 ++dev->stats.rx_fifo_errors;
2785 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2788 if (status & GM_IS_TX_FF_UR) {
2789 ++dev->stats.tx_fifo_errors;
2790 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2794 /* This should never happen it is a bug. */
2795 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2797 struct net_device *dev = hw->dev[port];
2798 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2800 dev_err(&hw->pdev->dev, "%s: descriptor error q=%#x get=%u put=%u\n",
2801 dev->name, (unsigned) q, (unsigned) idx,
2802 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2804 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2807 static int sky2_rx_hung(struct net_device *dev)
2809 struct sky2_port *sky2 = netdev_priv(dev);
2810 struct sky2_hw *hw = sky2->hw;
2811 unsigned port = sky2->port;
2812 unsigned rxq = rxqaddr[port];
2813 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2814 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2815 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2816 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2818 /* If idle and MAC or PCI is stuck */
2819 if (sky2->check.last == dev->last_rx &&
2820 ((mac_rp == sky2->check.mac_rp &&
2821 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2822 /* Check if the PCI RX hang */
2823 (fifo_rp == sky2->check.fifo_rp &&
2824 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2825 netdev_printk(KERN_DEBUG, dev,
2826 "hung mac %d:%d fifo %d (%d:%d)\n",
2827 mac_lev, mac_rp, fifo_lev,
2828 fifo_rp, sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2831 sky2->check.last = dev->last_rx;
2832 sky2->check.mac_rp = mac_rp;
2833 sky2->check.mac_lev = mac_lev;
2834 sky2->check.fifo_rp = fifo_rp;
2835 sky2->check.fifo_lev = fifo_lev;
2840 static void sky2_watchdog(unsigned long arg)
2842 struct sky2_hw *hw = (struct sky2_hw *) arg;
2844 /* Check for lost IRQ once a second */
2845 if (sky2_read32(hw, B0_ISRC)) {
2846 napi_schedule(&hw->napi);
2850 for (i = 0; i < hw->ports; i++) {
2851 struct net_device *dev = hw->dev[i];
2852 if (!netif_running(dev))
2856 /* For chips with Rx FIFO, check if stuck */
2857 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2858 sky2_rx_hung(dev)) {
2859 netdev_info(dev, "receiver hang detected\n");
2860 schedule_work(&hw->restart_work);
2869 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2872 /* Hardware/software error handling */
2873 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2875 if (net_ratelimit())
2876 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2878 if (status & Y2_IS_HW_ERR)
2881 if (status & Y2_IS_IRQ_MAC1)
2882 sky2_mac_intr(hw, 0);
2884 if (status & Y2_IS_IRQ_MAC2)
2885 sky2_mac_intr(hw, 1);
2887 if (status & Y2_IS_CHK_RX1)
2888 sky2_le_error(hw, 0, Q_R1);
2890 if (status & Y2_IS_CHK_RX2)
2891 sky2_le_error(hw, 1, Q_R2);
2893 if (status & Y2_IS_CHK_TXA1)
2894 sky2_le_error(hw, 0, Q_XA1);
2896 if (status & Y2_IS_CHK_TXA2)
2897 sky2_le_error(hw, 1, Q_XA2);
2900 static int sky2_poll(struct napi_struct *napi, int work_limit)
2902 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2903 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2907 if (unlikely(status & Y2_IS_ERROR))
2908 sky2_err_intr(hw, status);
2910 if (status & Y2_IS_IRQ_PHY1)
2911 sky2_phy_intr(hw, 0);
2913 if (status & Y2_IS_IRQ_PHY2)
2914 sky2_phy_intr(hw, 1);
2916 if (status & Y2_IS_PHY_QLNK)
2917 sky2_qlink_intr(hw);
2919 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2920 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2922 if (work_done >= work_limit)
2926 napi_complete(napi);
2927 sky2_read32(hw, B0_Y2_SP_LISR);
2933 static irqreturn_t sky2_intr(int irq, void *dev_id)
2935 struct sky2_hw *hw = dev_id;
2938 /* Reading this mask interrupts as side effect */
2939 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2940 if (status == 0 || status == ~0)
2943 prefetch(&hw->st_le[hw->st_idx]);
2945 napi_schedule(&hw->napi);
2950 #ifdef CONFIG_NET_POLL_CONTROLLER
2951 static void sky2_netpoll(struct net_device *dev)
2953 struct sky2_port *sky2 = netdev_priv(dev);
2955 napi_schedule(&sky2->hw->napi);
2959 /* Chip internal frequency for clock calculations */
2960 static u32 sky2_mhz(const struct sky2_hw *hw)
2962 switch (hw->chip_id) {
2963 case CHIP_ID_YUKON_EC:
2964 case CHIP_ID_YUKON_EC_U:
2965 case CHIP_ID_YUKON_EX:
2966 case CHIP_ID_YUKON_SUPR:
2967 case CHIP_ID_YUKON_UL_2:
2968 case CHIP_ID_YUKON_OPT:
2971 case CHIP_ID_YUKON_FE:
2974 case CHIP_ID_YUKON_FE_P:
2977 case CHIP_ID_YUKON_XL:
2985 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2987 return sky2_mhz(hw) * us;
2990 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2992 return clk / sky2_mhz(hw);
2996 static int __devinit sky2_init(struct sky2_hw *hw)
3000 /* Enable all clocks and check for bad PCI access */
3001 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3003 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3005 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
3006 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
3008 switch(hw->chip_id) {
3009 case CHIP_ID_YUKON_XL:
3010 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
3011 if (hw->chip_rev < CHIP_REV_YU_XL_A2)
3012 hw->flags |= SKY2_HW_RSS_BROKEN;
3015 case CHIP_ID_YUKON_EC_U:
3016 hw->flags = SKY2_HW_GIGABIT
3018 | SKY2_HW_ADV_POWER_CTL;
3021 case CHIP_ID_YUKON_EX:
3022 hw->flags = SKY2_HW_GIGABIT
3025 | SKY2_HW_ADV_POWER_CTL;
3027 /* New transmit checksum */
3028 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
3029 hw->flags |= SKY2_HW_AUTO_TX_SUM;
3032 case CHIP_ID_YUKON_EC:
3033 /* This rev is really old, and requires untested workarounds */
3034 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
3035 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
3038 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_RSS_BROKEN;
3041 case CHIP_ID_YUKON_FE:
3042 hw->flags = SKY2_HW_RSS_BROKEN;
3045 case CHIP_ID_YUKON_FE_P:
3046 hw->flags = SKY2_HW_NEWER_PHY
3048 | SKY2_HW_AUTO_TX_SUM
3049 | SKY2_HW_ADV_POWER_CTL;
3052 case CHIP_ID_YUKON_SUPR:
3053 hw->flags = SKY2_HW_GIGABIT
3056 | SKY2_HW_AUTO_TX_SUM
3057 | SKY2_HW_ADV_POWER_CTL;
3060 case CHIP_ID_YUKON_UL_2:
3061 hw->flags = SKY2_HW_GIGABIT
3062 | SKY2_HW_ADV_POWER_CTL;
3065 case CHIP_ID_YUKON_OPT:
3066 hw->flags = SKY2_HW_GIGABIT
3068 | SKY2_HW_ADV_POWER_CTL;
3072 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3077 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
3078 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
3079 hw->flags |= SKY2_HW_FIBRE_PHY;
3082 t8 = sky2_read8(hw, B2_Y2_HW_RES);
3083 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
3084 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
3088 if (sky2_read8(hw, B2_E_0))
3089 hw->flags |= SKY2_HW_RAM_BUFFER;
3094 static void sky2_reset(struct sky2_hw *hw)
3096 struct pci_dev *pdev = hw->pdev;
3099 u32 hwe_mask = Y2_HWE_ALL_MASK;
3102 if (hw->chip_id == CHIP_ID_YUKON_EX
3103 || hw->chip_id == CHIP_ID_YUKON_SUPR) {
3104 sky2_write32(hw, CPU_WDOG, 0);
3105 status = sky2_read16(hw, HCU_CCSR);
3106 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3107 HCU_CCSR_UC_STATE_MSK);
3109 * CPU clock divider shouldn't be used because
3110 * - ASF firmware may malfunction
3111 * - Yukon-Supreme: Parallel FLASH doesn't support divided clocks
3113 status &= ~HCU_CCSR_CPU_CLK_DIVIDE_MSK;
3114 sky2_write16(hw, HCU_CCSR, status);
3115 sky2_write32(hw, CPU_WDOG, 0);
3117 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3118 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3121 sky2_write8(hw, B0_CTST, CS_RST_SET);
3122 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3124 /* allow writes to PCI config */
3125 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3127 /* clear PCI errors, if any */
3128 status = sky2_pci_read16(hw, PCI_STATUS);
3129 status |= PCI_STATUS_ERROR_BITS;
3130 sky2_pci_write16(hw, PCI_STATUS, status);
3132 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3134 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3136 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3139 /* If error bit is stuck on ignore it */
3140 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3141 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3143 hwe_mask |= Y2_IS_PCI_EXP;
3147 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3149 for (i = 0; i < hw->ports; i++) {
3150 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3151 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3153 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3154 hw->chip_id == CHIP_ID_YUKON_SUPR)
3155 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3156 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3161 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3162 /* enable MACSec clock gating */
3163 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3166 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3170 if (hw->chip_rev == 0) {
3171 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3172 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3174 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3177 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3181 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3183 /* reset PHY Link Detect */
3184 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3185 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3186 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3187 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3190 /* enable PHY Quick Link */
3191 msk = sky2_read32(hw, B0_IMSK);
3192 msk |= Y2_IS_PHY_QLNK;
3193 sky2_write32(hw, B0_IMSK, msk);
3195 /* check if PSMv2 was running before */
3196 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3197 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3198 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3199 /* restore the PCIe Link Control register */
3200 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3202 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3204 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3205 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3208 /* Clear I2C IRQ noise */
3209 sky2_write32(hw, B2_I2C_IRQ, 1);
3211 /* turn off hardware timer (unused) */
3212 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3213 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3215 /* Turn off descriptor polling */
3216 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3218 /* Turn off receive timestamp */
3219 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3220 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3222 /* enable the Tx Arbiters */
3223 for (i = 0; i < hw->ports; i++)
3224 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3226 /* Initialize ram interface */
3227 for (i = 0; i < hw->ports; i++) {
3228 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3230 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3231 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3232 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3233 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3234 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3235 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3236 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3237 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3238 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3239 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3240 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3241 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3244 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3246 for (i = 0; i < hw->ports; i++)
3247 sky2_gmac_reset(hw, i);
3249 memset(hw->st_le, 0, hw->st_size * sizeof(struct sky2_status_le));
3252 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3253 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3255 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3256 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3258 /* Set the list last index */
3259 sky2_write16(hw, STAT_LAST_IDX, hw->st_size - 1);
3261 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3262 sky2_write8(hw, STAT_FIFO_WM, 16);
3264 /* set Status-FIFO ISR watermark */
3265 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3266 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3268 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3270 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3271 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3272 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3274 /* enable status unit */
3275 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3277 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3278 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3279 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3282 /* Take device down (offline).
3283 * Equivalent to doing dev_stop() but this does not
3284 * inform upper layers of the transistion.
3286 static void sky2_detach(struct net_device *dev)
3288 if (netif_running(dev)) {
3290 netif_device_detach(dev); /* stop txq */
3291 netif_tx_unlock(dev);
3296 /* Bring device back after doing sky2_detach */
3297 static int sky2_reattach(struct net_device *dev)
3301 if (netif_running(dev)) {
3304 netdev_info(dev, "could not restart %d\n", err);
3307 netif_device_attach(dev);
3308 sky2_set_multicast(dev);
3315 static void sky2_restart(struct work_struct *work)
3317 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3323 napi_disable(&hw->napi);
3324 synchronize_irq(hw->pdev->irq);
3325 imask = sky2_read32(hw, B0_IMSK);
3326 sky2_write32(hw, B0_IMSK, 0);
3328 for (i = 0; i < hw->ports; i++) {
3329 struct net_device *dev = hw->dev[i];
3330 struct sky2_port *sky2 = netdev_priv(dev);
3332 if (!netif_running(dev))
3335 netif_carrier_off(dev);
3336 netif_tx_disable(dev);
3342 for (i = 0; i < hw->ports; i++) {
3343 struct net_device *dev = hw->dev[i];
3344 struct sky2_port *sky2 = netdev_priv(dev);
3346 if (!netif_running(dev))
3350 netif_wake_queue(dev);
3353 sky2_write32(hw, B0_IMSK, imask);
3354 sky2_read32(hw, B0_IMSK);
3356 sky2_read32(hw, B0_Y2_SP_LISR);
3357 napi_enable(&hw->napi);
3362 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3364 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3367 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3369 const struct sky2_port *sky2 = netdev_priv(dev);
3371 wol->supported = sky2_wol_supported(sky2->hw);
3372 wol->wolopts = sky2->wol;
3375 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3377 struct sky2_port *sky2 = netdev_priv(dev);
3378 struct sky2_hw *hw = sky2->hw;
3380 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3381 !device_can_wakeup(&hw->pdev->dev))
3384 sky2->wol = wol->wolopts;
3388 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3390 if (sky2_is_copper(hw)) {
3391 u32 modes = SUPPORTED_10baseT_Half
3392 | SUPPORTED_10baseT_Full
3393 | SUPPORTED_100baseT_Half
3394 | SUPPORTED_100baseT_Full
3395 | SUPPORTED_Autoneg | SUPPORTED_TP;
3397 if (hw->flags & SKY2_HW_GIGABIT)
3398 modes |= SUPPORTED_1000baseT_Half
3399 | SUPPORTED_1000baseT_Full;
3402 return SUPPORTED_1000baseT_Half
3403 | SUPPORTED_1000baseT_Full
3408 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3410 struct sky2_port *sky2 = netdev_priv(dev);
3411 struct sky2_hw *hw = sky2->hw;
3413 ecmd->transceiver = XCVR_INTERNAL;
3414 ecmd->supported = sky2_supported_modes(hw);
3415 ecmd->phy_address = PHY_ADDR_MARV;
3416 if (sky2_is_copper(hw)) {
3417 ecmd->port = PORT_TP;
3418 ecmd->speed = sky2->speed;
3420 ecmd->speed = SPEED_1000;
3421 ecmd->port = PORT_FIBRE;
3424 ecmd->advertising = sky2->advertising;
3425 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3426 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3427 ecmd->duplex = sky2->duplex;
3431 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3433 struct sky2_port *sky2 = netdev_priv(dev);
3434 const struct sky2_hw *hw = sky2->hw;
3435 u32 supported = sky2_supported_modes(hw);
3437 if (ecmd->autoneg == AUTONEG_ENABLE) {
3438 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3439 ecmd->advertising = supported;
3445 switch (ecmd->speed) {
3447 if (ecmd->duplex == DUPLEX_FULL)
3448 setting = SUPPORTED_1000baseT_Full;
3449 else if (ecmd->duplex == DUPLEX_HALF)
3450 setting = SUPPORTED_1000baseT_Half;
3455 if (ecmd->duplex == DUPLEX_FULL)
3456 setting = SUPPORTED_100baseT_Full;
3457 else if (ecmd->duplex == DUPLEX_HALF)
3458 setting = SUPPORTED_100baseT_Half;
3464 if (ecmd->duplex == DUPLEX_FULL)
3465 setting = SUPPORTED_10baseT_Full;
3466 else if (ecmd->duplex == DUPLEX_HALF)
3467 setting = SUPPORTED_10baseT_Half;
3475 if ((setting & supported) == 0)
3478 sky2->speed = ecmd->speed;
3479 sky2->duplex = ecmd->duplex;
3480 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3483 sky2->advertising = ecmd->advertising;
3485 if (netif_running(dev)) {
3486 sky2_phy_reinit(sky2);
3487 sky2_set_multicast(dev);
3493 static void sky2_get_drvinfo(struct net_device *dev,
3494 struct ethtool_drvinfo *info)
3496 struct sky2_port *sky2 = netdev_priv(dev);
3498 strcpy(info->driver, DRV_NAME);
3499 strcpy(info->version, DRV_VERSION);
3500 strcpy(info->fw_version, "N/A");
3501 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3504 static const struct sky2_stat {
3505 char name[ETH_GSTRING_LEN];
3508 { "tx_bytes", GM_TXO_OK_HI },
3509 { "rx_bytes", GM_RXO_OK_HI },
3510 { "tx_broadcast", GM_TXF_BC_OK },
3511 { "rx_broadcast", GM_RXF_BC_OK },
3512 { "tx_multicast", GM_TXF_MC_OK },
3513 { "rx_multicast", GM_RXF_MC_OK },
3514 { "tx_unicast", GM_TXF_UC_OK },
3515 { "rx_unicast", GM_RXF_UC_OK },
3516 { "tx_mac_pause", GM_TXF_MPAUSE },
3517 { "rx_mac_pause", GM_RXF_MPAUSE },
3518 { "collisions", GM_TXF_COL },
3519 { "late_collision",GM_TXF_LAT_COL },
3520 { "aborted", GM_TXF_ABO_COL },
3521 { "single_collisions", GM_TXF_SNG_COL },
3522 { "multi_collisions", GM_TXF_MUL_COL },
3524 { "rx_short", GM_RXF_SHT },
3525 { "rx_runt", GM_RXE_FRAG },
3526 { "rx_64_byte_packets", GM_RXF_64B },
3527 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3528 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3529 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3530 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3531 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3532 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3533 { "rx_too_long", GM_RXF_LNG_ERR },
3534 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3535 { "rx_jabber", GM_RXF_JAB_PKT },
3536 { "rx_fcs_error", GM_RXF_FCS_ERR },
3538 { "tx_64_byte_packets", GM_TXF_64B },
3539 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3540 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3541 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3542 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3543 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3544 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3545 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3548 static u32 sky2_get_rx_csum(struct net_device *dev)
3550 struct sky2_port *sky2 = netdev_priv(dev);
3552 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3555 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3557 struct sky2_port *sky2 = netdev_priv(dev);
3560 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3562 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3564 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3565 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3570 static u32 sky2_get_msglevel(struct net_device *netdev)
3572 struct sky2_port *sky2 = netdev_priv(netdev);
3573 return sky2->msg_enable;
3576 static int sky2_nway_reset(struct net_device *dev)
3578 struct sky2_port *sky2 = netdev_priv(dev);
3580 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3583 sky2_phy_reinit(sky2);
3584 sky2_set_multicast(dev);
3589 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3591 struct sky2_hw *hw = sky2->hw;
3592 unsigned port = sky2->port;
3595 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3596 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3597 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3598 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3600 for (i = 2; i < count; i++)
3601 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3604 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3606 struct sky2_port *sky2 = netdev_priv(netdev);
3607 sky2->msg_enable = value;
3610 static int sky2_get_sset_count(struct net_device *dev, int sset)
3614 return ARRAY_SIZE(sky2_stats);
3620 static void sky2_get_ethtool_stats(struct net_device *dev,
3621 struct ethtool_stats *stats, u64 * data)
3623 struct sky2_port *sky2 = netdev_priv(dev);
3625 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3628 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3632 switch (stringset) {
3634 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3635 memcpy(data + i * ETH_GSTRING_LEN,
3636 sky2_stats[i].name, ETH_GSTRING_LEN);
3641 static int sky2_set_mac_address(struct net_device *dev, void *p)
3643 struct sky2_port *sky2 = netdev_priv(dev);
3644 struct sky2_hw *hw = sky2->hw;
3645 unsigned port = sky2->port;
3646 const struct sockaddr *addr = p;
3648 if (!is_valid_ether_addr(addr->sa_data))
3649 return -EADDRNOTAVAIL;
3651 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3652 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3653 dev->dev_addr, ETH_ALEN);
3654 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3655 dev->dev_addr, ETH_ALEN);
3657 /* virtual address for data */
3658 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3660 /* physical address: used for pause frames */
3661 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3666 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3670 bit = ether_crc(ETH_ALEN, addr) & 63;
3671 filter[bit >> 3] |= 1 << (bit & 7);
3674 static void sky2_set_multicast(struct net_device *dev)
3676 struct sky2_port *sky2 = netdev_priv(dev);
3677 struct sky2_hw *hw = sky2->hw;
3678 unsigned port = sky2->port;
3679 struct netdev_hw_addr *ha;
3683 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3685 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3686 memset(filter, 0, sizeof(filter));
3688 reg = gma_read16(hw, port, GM_RX_CTRL);
3689 reg |= GM_RXCR_UCF_ENA;
3691 if (dev->flags & IFF_PROMISC) /* promiscuous */
3692 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3693 else if (dev->flags & IFF_ALLMULTI)
3694 memset(filter, 0xff, sizeof(filter));
3695 else if (netdev_mc_empty(dev) && !rx_pause)
3696 reg &= ~GM_RXCR_MCF_ENA;
3698 reg |= GM_RXCR_MCF_ENA;
3701 sky2_add_filter(filter, pause_mc_addr);
3703 netdev_for_each_mc_addr(ha, dev)
3704 sky2_add_filter(filter, ha->addr);
3707 gma_write16(hw, port, GM_MC_ADDR_H1,
3708 (u16) filter[0] | ((u16) filter[1] << 8));
3709 gma_write16(hw, port, GM_MC_ADDR_H2,
3710 (u16) filter[2] | ((u16) filter[3] << 8));
3711 gma_write16(hw, port, GM_MC_ADDR_H3,
3712 (u16) filter[4] | ((u16) filter[5] << 8));
3713 gma_write16(hw, port, GM_MC_ADDR_H4,
3714 (u16) filter[6] | ((u16) filter[7] << 8));
3716 gma_write16(hw, port, GM_RX_CTRL, reg);
3719 /* Can have one global because blinking is controlled by
3720 * ethtool and that is always under RTNL mutex
3722 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3724 struct sky2_hw *hw = sky2->hw;
3725 unsigned port = sky2->port;
3727 spin_lock_bh(&sky2->phy_lock);
3728 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3729 hw->chip_id == CHIP_ID_YUKON_EX ||
3730 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3732 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3733 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3737 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3738 PHY_M_LEDC_LOS_CTRL(8) |
3739 PHY_M_LEDC_INIT_CTRL(8) |
3740 PHY_M_LEDC_STA1_CTRL(8) |
3741 PHY_M_LEDC_STA0_CTRL(8));
3744 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3745 PHY_M_LEDC_LOS_CTRL(9) |
3746 PHY_M_LEDC_INIT_CTRL(9) |
3747 PHY_M_LEDC_STA1_CTRL(9) |
3748 PHY_M_LEDC_STA0_CTRL(9));
3751 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3752 PHY_M_LEDC_LOS_CTRL(0xa) |
3753 PHY_M_LEDC_INIT_CTRL(0xa) |
3754 PHY_M_LEDC_STA1_CTRL(0xa) |
3755 PHY_M_LEDC_STA0_CTRL(0xa));
3758 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3759 PHY_M_LEDC_LOS_CTRL(1) |
3760 PHY_M_LEDC_INIT_CTRL(8) |
3761 PHY_M_LEDC_STA1_CTRL(7) |
3762 PHY_M_LEDC_STA0_CTRL(7));
3765 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3767 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3768 PHY_M_LED_MO_DUP(mode) |
3769 PHY_M_LED_MO_10(mode) |
3770 PHY_M_LED_MO_100(mode) |
3771 PHY_M_LED_MO_1000(mode) |
3772 PHY_M_LED_MO_RX(mode) |
3773 PHY_M_LED_MO_TX(mode));
3775 spin_unlock_bh(&sky2->phy_lock);
3778 /* blink LED's for finding board */
3779 static int sky2_phys_id(struct net_device *dev, u32 data)
3781 struct sky2_port *sky2 = netdev_priv(dev);
3787 for (i = 0; i < data; i++) {
3788 sky2_led(sky2, MO_LED_ON);
3789 if (msleep_interruptible(500))
3791 sky2_led(sky2, MO_LED_OFF);
3792 if (msleep_interruptible(500))
3795 sky2_led(sky2, MO_LED_NORM);
3800 static void sky2_get_pauseparam(struct net_device *dev,
3801 struct ethtool_pauseparam *ecmd)
3803 struct sky2_port *sky2 = netdev_priv(dev);
3805 switch (sky2->flow_mode) {
3807 ecmd->tx_pause = ecmd->rx_pause = 0;
3810 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3813 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3816 ecmd->tx_pause = ecmd->rx_pause = 1;
3819 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3820 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3823 static int sky2_set_pauseparam(struct net_device *dev,
3824 struct ethtool_pauseparam *ecmd)
3826 struct sky2_port *sky2 = netdev_priv(dev);
3828 if (ecmd->autoneg == AUTONEG_ENABLE)
3829 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3831 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3833 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3835 if (netif_running(dev))
3836 sky2_phy_reinit(sky2);
3841 static int sky2_get_coalesce(struct net_device *dev,
3842 struct ethtool_coalesce *ecmd)
3844 struct sky2_port *sky2 = netdev_priv(dev);
3845 struct sky2_hw *hw = sky2->hw;
3847 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3848 ecmd->tx_coalesce_usecs = 0;
3850 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3851 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3853 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3855 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3856 ecmd->rx_coalesce_usecs = 0;
3858 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3859 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3861 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3863 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3864 ecmd->rx_coalesce_usecs_irq = 0;
3866 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3867 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3870 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3875 /* Note: this affect both ports */
3876 static int sky2_set_coalesce(struct net_device *dev,
3877 struct ethtool_coalesce *ecmd)
3879 struct sky2_port *sky2 = netdev_priv(dev);
3880 struct sky2_hw *hw = sky2->hw;
3881 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3883 if (ecmd->tx_coalesce_usecs > tmax ||
3884 ecmd->rx_coalesce_usecs > tmax ||
3885 ecmd->rx_coalesce_usecs_irq > tmax)
3888 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3890 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3892 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3895 if (ecmd->tx_coalesce_usecs == 0)
3896 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3898 sky2_write32(hw, STAT_TX_TIMER_INI,
3899 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3900 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3902 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3904 if (ecmd->rx_coalesce_usecs == 0)
3905 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3907 sky2_write32(hw, STAT_LEV_TIMER_INI,
3908 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3909 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3911 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3913 if (ecmd->rx_coalesce_usecs_irq == 0)
3914 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3916 sky2_write32(hw, STAT_ISR_TIMER_INI,
3917 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3918 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3920 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3924 static void sky2_get_ringparam(struct net_device *dev,
3925 struct ethtool_ringparam *ering)
3927 struct sky2_port *sky2 = netdev_priv(dev);
3929 ering->rx_max_pending = RX_MAX_PENDING;
3930 ering->rx_mini_max_pending = 0;
3931 ering->rx_jumbo_max_pending = 0;
3932 ering->tx_max_pending = TX_MAX_PENDING;
3934 ering->rx_pending = sky2->rx_pending;
3935 ering->rx_mini_pending = 0;
3936 ering->rx_jumbo_pending = 0;
3937 ering->tx_pending = sky2->tx_pending;
3940 static int sky2_set_ringparam(struct net_device *dev,
3941 struct ethtool_ringparam *ering)
3943 struct sky2_port *sky2 = netdev_priv(dev);
3945 if (ering->rx_pending > RX_MAX_PENDING ||
3946 ering->rx_pending < 8 ||
3947 ering->tx_pending < TX_MIN_PENDING ||
3948 ering->tx_pending > TX_MAX_PENDING)
3953 sky2->rx_pending = ering->rx_pending;
3954 sky2->tx_pending = ering->tx_pending;
3955 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3957 return sky2_reattach(dev);
3960 static int sky2_get_regs_len(struct net_device *dev)
3965 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3967 /* This complicated switch statement is to make sure and
3968 * only access regions that are unreserved.
3969 * Some blocks are only valid on dual port cards.
3973 case 5: /* Tx Arbiter 2 */
3975 case 14 ... 15: /* TX2 */
3976 case 17: case 19: /* Ram Buffer 2 */
3977 case 22 ... 23: /* Tx Ram Buffer 2 */
3978 case 25: /* Rx MAC Fifo 1 */
3979 case 27: /* Tx MAC Fifo 2 */
3980 case 31: /* GPHY 2 */
3981 case 40 ... 47: /* Pattern Ram 2 */
3982 case 52: case 54: /* TCP Segmentation 2 */
3983 case 112 ... 116: /* GMAC 2 */
3984 return hw->ports > 1;
3986 case 0: /* Control */
3987 case 2: /* Mac address */
3988 case 4: /* Tx Arbiter 1 */
3989 case 7: /* PCI express reg */
3991 case 12 ... 13: /* TX1 */
3992 case 16: case 18:/* Rx Ram Buffer 1 */
3993 case 20 ... 21: /* Tx Ram Buffer 1 */
3994 case 24: /* Rx MAC Fifo 1 */
3995 case 26: /* Tx MAC Fifo 1 */
3996 case 28 ... 29: /* Descriptor and status unit */
3997 case 30: /* GPHY 1*/
3998 case 32 ... 39: /* Pattern Ram 1 */
3999 case 48: case 50: /* TCP Segmentation 1 */
4000 case 56 ... 60: /* PCI space */
4001 case 80 ... 84: /* GMAC 1 */
4010 * Returns copy of control register region
4011 * Note: ethtool_get_regs always provides full size (16k) buffer
4013 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
4016 const struct sky2_port *sky2 = netdev_priv(dev);
4017 const void __iomem *io = sky2->hw->regs;
4022 for (b = 0; b < 128; b++) {
4023 /* skip poisonous diagnostic ram region in block 3 */
4025 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
4026 else if (sky2_reg_access_ok(sky2->hw, b))
4027 memcpy_fromio(p, io, 128);
4036 /* In order to do Jumbo packets on these chips, need to turn off the
4037 * transmit store/forward. Therefore checksum offload won't work.
4039 static int no_tx_offload(struct net_device *dev)
4041 const struct sky2_port *sky2 = netdev_priv(dev);
4042 const struct sky2_hw *hw = sky2->hw;
4044 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
4047 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
4049 if (data && no_tx_offload(dev))
4052 return ethtool_op_set_tx_csum(dev, data);
4056 static int sky2_set_tso(struct net_device *dev, u32 data)
4058 if (data && no_tx_offload(dev))
4061 return ethtool_op_set_tso(dev, data);
4064 static int sky2_get_eeprom_len(struct net_device *dev)
4066 struct sky2_port *sky2 = netdev_priv(dev);
4067 struct sky2_hw *hw = sky2->hw;
4070 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4071 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4074 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
4076 unsigned long start = jiffies;
4078 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
4079 /* Can take up to 10.6 ms for write */
4080 if (time_after(jiffies, start + HZ/4)) {
4081 dev_err(&hw->pdev->dev, "VPD cycle timed out\n");
4090 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
4091 u16 offset, size_t length)
4095 while (length > 0) {
4098 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4099 rc = sky2_vpd_wait(hw, cap, 0);
4103 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4105 memcpy(data, &val, min(sizeof(val), length));
4106 offset += sizeof(u32);
4107 data += sizeof(u32);
4108 length -= sizeof(u32);
4114 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4115 u16 offset, unsigned int length)
4120 for (i = 0; i < length; i += sizeof(u32)) {
4121 u32 val = *(u32 *)(data + i);
4123 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4124 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4126 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4133 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4136 struct sky2_port *sky2 = netdev_priv(dev);
4137 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4142 eeprom->magic = SKY2_EEPROM_MAGIC;
4144 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4147 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4150 struct sky2_port *sky2 = netdev_priv(dev);
4151 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4156 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4159 /* Partial writes not supported */
4160 if ((eeprom->offset & 3) || (eeprom->len & 3))
4163 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4166 static int sky2_set_flags(struct net_device *dev, u32 data)
4168 struct sky2_port *sky2 = netdev_priv(dev);
4170 if (data & ~ETH_FLAG_RXHASH)
4173 if (data & ETH_FLAG_RXHASH) {
4174 if (sky2->hw->flags & SKY2_HW_RSS_BROKEN)
4177 dev->features |= NETIF_F_RXHASH;
4179 dev->features &= ~NETIF_F_RXHASH;
4186 static const struct ethtool_ops sky2_ethtool_ops = {
4187 .get_settings = sky2_get_settings,
4188 .set_settings = sky2_set_settings,
4189 .get_drvinfo = sky2_get_drvinfo,
4190 .get_wol = sky2_get_wol,
4191 .set_wol = sky2_set_wol,
4192 .get_msglevel = sky2_get_msglevel,
4193 .set_msglevel = sky2_set_msglevel,
4194 .nway_reset = sky2_nway_reset,
4195 .get_regs_len = sky2_get_regs_len,
4196 .get_regs = sky2_get_regs,
4197 .get_link = ethtool_op_get_link,
4198 .get_eeprom_len = sky2_get_eeprom_len,
4199 .get_eeprom = sky2_get_eeprom,
4200 .set_eeprom = sky2_set_eeprom,
4201 .set_sg = ethtool_op_set_sg,
4202 .set_tx_csum = sky2_set_tx_csum,
4203 .set_tso = sky2_set_tso,
4204 .get_rx_csum = sky2_get_rx_csum,
4205 .set_rx_csum = sky2_set_rx_csum,
4206 .get_strings = sky2_get_strings,
4207 .get_coalesce = sky2_get_coalesce,
4208 .set_coalesce = sky2_set_coalesce,
4209 .get_ringparam = sky2_get_ringparam,
4210 .set_ringparam = sky2_set_ringparam,
4211 .get_pauseparam = sky2_get_pauseparam,
4212 .set_pauseparam = sky2_set_pauseparam,
4213 .phys_id = sky2_phys_id,
4214 .get_sset_count = sky2_get_sset_count,
4215 .get_ethtool_stats = sky2_get_ethtool_stats,
4216 .set_flags = sky2_set_flags,
4219 #ifdef CONFIG_SKY2_DEBUG
4221 static struct dentry *sky2_debug;
4225 * Read and parse the first part of Vital Product Data
4227 #define VPD_SIZE 128
4228 #define VPD_MAGIC 0x82
4230 static const struct vpd_tag {
4234 { "PN", "Part Number" },
4235 { "EC", "Engineering Level" },
4236 { "MN", "Manufacturer" },
4237 { "SN", "Serial Number" },
4238 { "YA", "Asset Tag" },
4239 { "VL", "First Error Log Message" },
4240 { "VF", "Second Error Log Message" },
4241 { "VB", "Boot Agent ROM Configuration" },
4242 { "VE", "EFI UNDI Configuration" },
4245 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4253 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4254 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4256 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4257 buf = kmalloc(vpd_size, GFP_KERNEL);
4259 seq_puts(seq, "no memory!\n");
4263 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4264 seq_puts(seq, "VPD read failed\n");
4268 if (buf[0] != VPD_MAGIC) {
4269 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4273 if (len == 0 || len > vpd_size - 4) {
4274 seq_printf(seq, "Invalid id length: %d\n", len);
4278 seq_printf(seq, "%.*s\n", len, buf + 3);
4281 while (offs < vpd_size - 4) {
4284 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4286 len = buf[offs + 2];
4287 if (offs + len + 3 >= vpd_size)
4290 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4291 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4292 seq_printf(seq, " %s: %.*s\n",
4293 vpd_tags[i].label, len, buf + offs + 3);
4303 static int sky2_debug_show(struct seq_file *seq, void *v)
4305 struct net_device *dev = seq->private;
4306 const struct sky2_port *sky2 = netdev_priv(dev);
4307 struct sky2_hw *hw = sky2->hw;
4308 unsigned port = sky2->port;
4312 sky2_show_vpd(seq, hw);
4314 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4315 sky2_read32(hw, B0_ISRC),
4316 sky2_read32(hw, B0_IMSK),
4317 sky2_read32(hw, B0_Y2_SP_ICR));
4319 if (!netif_running(dev)) {
4320 seq_printf(seq, "network not running\n");
4324 napi_disable(&hw->napi);
4325 last = sky2_read16(hw, STAT_PUT_IDX);
4327 seq_printf(seq, "Status ring %u\n", hw->st_size);
4328 if (hw->st_idx == last)
4329 seq_puts(seq, "Status ring (empty)\n");
4331 seq_puts(seq, "Status ring\n");
4332 for (idx = hw->st_idx; idx != last && idx < hw->st_size;
4333 idx = RING_NEXT(idx, hw->st_size)) {
4334 const struct sky2_status_le *le = hw->st_le + idx;
4335 seq_printf(seq, "[%d] %#x %d %#x\n",
4336 idx, le->opcode, le->length, le->status);
4338 seq_puts(seq, "\n");
4341 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4342 sky2->tx_cons, sky2->tx_prod,
4343 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4344 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4346 /* Dump contents of tx ring */
4348 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4349 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4350 const struct sky2_tx_le *le = sky2->tx_le + idx;
4351 u32 a = le32_to_cpu(le->addr);
4354 seq_printf(seq, "%u:", idx);
4357 switch(le->opcode & ~HW_OWNER) {
4359 seq_printf(seq, " %#x:", a);
4362 seq_printf(seq, " mtu=%d", a);
4365 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4368 seq_printf(seq, " csum=%#x", a);
4371 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4374 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4377 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4380 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4381 a, le16_to_cpu(le->length));
4384 if (le->ctrl & EOP) {
4385 seq_putc(seq, '\n');
4390 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4391 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4392 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4393 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4395 sky2_read32(hw, B0_Y2_SP_LISR);
4396 napi_enable(&hw->napi);
4400 static int sky2_debug_open(struct inode *inode, struct file *file)
4402 return single_open(file, sky2_debug_show, inode->i_private);
4405 static const struct file_operations sky2_debug_fops = {
4406 .owner = THIS_MODULE,
4407 .open = sky2_debug_open,
4409 .llseek = seq_lseek,
4410 .release = single_release,
4414 * Use network device events to create/remove/rename
4415 * debugfs file entries
4417 static int sky2_device_event(struct notifier_block *unused,
4418 unsigned long event, void *ptr)
4420 struct net_device *dev = ptr;
4421 struct sky2_port *sky2 = netdev_priv(dev);
4423 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4427 case NETDEV_CHANGENAME:
4428 if (sky2->debugfs) {
4429 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4430 sky2_debug, dev->name);
4434 case NETDEV_GOING_DOWN:
4435 if (sky2->debugfs) {
4436 netdev_printk(KERN_DEBUG, dev, "remove debugfs\n");
4437 debugfs_remove(sky2->debugfs);
4438 sky2->debugfs = NULL;
4443 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4446 if (IS_ERR(sky2->debugfs))
4447 sky2->debugfs = NULL;
4453 static struct notifier_block sky2_notifier = {
4454 .notifier_call = sky2_device_event,
4458 static __init void sky2_debug_init(void)
4462 ent = debugfs_create_dir("sky2", NULL);
4463 if (!ent || IS_ERR(ent))
4467 register_netdevice_notifier(&sky2_notifier);
4470 static __exit void sky2_debug_cleanup(void)
4473 unregister_netdevice_notifier(&sky2_notifier);
4474 debugfs_remove(sky2_debug);
4480 #define sky2_debug_init()
4481 #define sky2_debug_cleanup()
4484 /* Two copies of network device operations to handle special case of
4485 not allowing netpoll on second port */
4486 static const struct net_device_ops sky2_netdev_ops[2] = {
4488 .ndo_open = sky2_up,
4489 .ndo_stop = sky2_down,
4490 .ndo_start_xmit = sky2_xmit_frame,
4491 .ndo_do_ioctl = sky2_ioctl,
4492 .ndo_validate_addr = eth_validate_addr,
4493 .ndo_set_mac_address = sky2_set_mac_address,
4494 .ndo_set_multicast_list = sky2_set_multicast,
4495 .ndo_change_mtu = sky2_change_mtu,
4496 .ndo_tx_timeout = sky2_tx_timeout,
4497 #ifdef SKY2_VLAN_TAG_USED
4498 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4500 #ifdef CONFIG_NET_POLL_CONTROLLER
4501 .ndo_poll_controller = sky2_netpoll,
4505 .ndo_open = sky2_up,
4506 .ndo_stop = sky2_down,
4507 .ndo_start_xmit = sky2_xmit_frame,
4508 .ndo_do_ioctl = sky2_ioctl,
4509 .ndo_validate_addr = eth_validate_addr,
4510 .ndo_set_mac_address = sky2_set_mac_address,
4511 .ndo_set_multicast_list = sky2_set_multicast,
4512 .ndo_change_mtu = sky2_change_mtu,
4513 .ndo_tx_timeout = sky2_tx_timeout,
4514 #ifdef SKY2_VLAN_TAG_USED
4515 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4520 /* Initialize network device */
4521 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4523 int highmem, int wol)
4525 struct sky2_port *sky2;
4526 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4529 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4533 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4534 dev->irq = hw->pdev->irq;
4535 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4536 dev->watchdog_timeo = TX_WATCHDOG;
4537 dev->netdev_ops = &sky2_netdev_ops[port];
4539 sky2 = netdev_priv(dev);
4542 sky2->msg_enable = netif_msg_init(debug, default_msg);
4544 /* Auto speed and flow control */
4545 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4546 if (hw->chip_id != CHIP_ID_YUKON_XL)
4547 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4549 sky2->flow_mode = FC_BOTH;
4553 sky2->advertising = sky2_supported_modes(hw);
4556 spin_lock_init(&sky2->phy_lock);
4558 sky2->tx_pending = TX_DEF_PENDING;
4559 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4560 sky2->rx_pending = RX_DEF_PENDING;
4562 hw->dev[port] = dev;
4566 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4568 dev->features |= NETIF_F_HIGHDMA;
4570 /* Enable receive hashing unless hardware is known broken */
4571 if (!(hw->flags & SKY2_HW_RSS_BROKEN))
4572 dev->features |= NETIF_F_RXHASH;
4574 #ifdef SKY2_VLAN_TAG_USED
4575 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4576 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4577 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4578 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4582 /* read the mac address */
4583 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4584 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4589 static void __devinit sky2_show_addr(struct net_device *dev)
4591 const struct sky2_port *sky2 = netdev_priv(dev);
4593 netif_info(sky2, probe, dev, "addr %pM\n", dev->dev_addr);
4596 /* Handle software interrupt used during MSI test */
4597 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4599 struct sky2_hw *hw = dev_id;
4600 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4605 if (status & Y2_IS_IRQ_SW) {
4606 hw->flags |= SKY2_HW_USE_MSI;
4607 wake_up(&hw->msi_wait);
4608 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4610 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4615 /* Test interrupt path by forcing a a software IRQ */
4616 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4618 struct pci_dev *pdev = hw->pdev;
4621 init_waitqueue_head (&hw->msi_wait);
4623 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4625 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4627 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4631 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4632 sky2_read8(hw, B0_CTST);
4634 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4636 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4637 /* MSI test failed, go back to INTx mode */
4638 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4639 "switching to INTx mode.\n");
4642 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4645 sky2_write32(hw, B0_IMSK, 0);
4646 sky2_read32(hw, B0_IMSK);
4648 free_irq(pdev->irq, hw);
4653 /* This driver supports yukon2 chipset only */
4654 static const char *sky2_name(u8 chipid, char *buf, int sz)
4656 const char *name[] = {
4658 "EC Ultra", /* 0xb4 */
4659 "Extreme", /* 0xb5 */
4663 "Supreme", /* 0xb9 */
4665 "Unknown", /* 0xbb */
4666 "Optima", /* 0xbc */
4669 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4670 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4672 snprintf(buf, sz, "(chip %#x)", chipid);
4676 static int __devinit sky2_probe(struct pci_dev *pdev,
4677 const struct pci_device_id *ent)
4679 struct net_device *dev;
4681 int err, using_dac = 0, wol_default;
4685 err = pci_enable_device(pdev);
4687 dev_err(&pdev->dev, "cannot enable PCI device\n");
4691 /* Get configuration information
4692 * Note: only regular PCI config access once to test for HW issues
4693 * other PCI access through shared memory for speed and to
4694 * avoid MMCONFIG problems.
4696 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4698 dev_err(&pdev->dev, "PCI read config failed\n");
4703 dev_err(&pdev->dev, "PCI configuration read error\n");
4707 err = pci_request_regions(pdev, DRV_NAME);
4709 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4710 goto err_out_disable;
4713 pci_set_master(pdev);
4715 if (sizeof(dma_addr_t) > sizeof(u32) &&
4716 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4718 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4720 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4721 "for consistent allocations\n");
4722 goto err_out_free_regions;
4725 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4727 dev_err(&pdev->dev, "no usable DMA configuration\n");
4728 goto err_out_free_regions;
4734 /* The sk98lin vendor driver uses hardware byte swapping but
4735 * this driver uses software swapping.
4737 reg &= ~PCI_REV_DESC;
4738 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4740 dev_err(&pdev->dev, "PCI write config failed\n");
4741 goto err_out_free_regions;
4745 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4749 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4750 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4752 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4753 goto err_out_free_regions;
4757 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4759 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4761 dev_err(&pdev->dev, "cannot map device registers\n");
4762 goto err_out_free_hw;
4765 err = sky2_init(hw);
4767 goto err_out_iounmap;
4769 /* ring for status responses */
4770 hw->st_size = hw->ports * roundup_pow_of_two(3*RX_MAX_PENDING + TX_MAX_PENDING);
4771 hw->st_le = pci_alloc_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4776 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4777 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4781 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4784 goto err_out_free_pci;
4787 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4788 err = sky2_test_msi(hw);
4789 if (err == -EOPNOTSUPP)
4790 pci_disable_msi(pdev);
4792 goto err_out_free_netdev;
4795 err = register_netdev(dev);
4797 dev_err(&pdev->dev, "cannot register net device\n");
4798 goto err_out_free_netdev;
4801 netif_carrier_off(dev);
4803 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4805 err = request_irq(pdev->irq, sky2_intr,
4806 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4809 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4810 goto err_out_unregister;
4812 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4813 napi_enable(&hw->napi);
4815 sky2_show_addr(dev);
4817 if (hw->ports > 1) {
4818 struct net_device *dev1;
4821 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4822 if (dev1 && (err = register_netdev(dev1)) == 0)
4823 sky2_show_addr(dev1);
4825 dev_warn(&pdev->dev,
4826 "register of second port failed (%d)\n", err);
4834 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4835 INIT_WORK(&hw->restart_work, sky2_restart);
4837 pci_set_drvdata(pdev, hw);
4838 pdev->d3_delay = 150;
4843 if (hw->flags & SKY2_HW_USE_MSI)
4844 pci_disable_msi(pdev);
4845 unregister_netdev(dev);
4846 err_out_free_netdev:
4849 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4850 hw->st_le, hw->st_dma);
4852 sky2_write8(hw, B0_CTST, CS_RST_SET);
4857 err_out_free_regions:
4858 pci_release_regions(pdev);
4860 pci_disable_device(pdev);
4862 pci_set_drvdata(pdev, NULL);
4866 static void __devexit sky2_remove(struct pci_dev *pdev)
4868 struct sky2_hw *hw = pci_get_drvdata(pdev);
4874 del_timer_sync(&hw->watchdog_timer);
4875 cancel_work_sync(&hw->restart_work);
4877 for (i = hw->ports-1; i >= 0; --i)
4878 unregister_netdev(hw->dev[i]);
4880 sky2_write32(hw, B0_IMSK, 0);
4884 sky2_write8(hw, B0_CTST, CS_RST_SET);
4885 sky2_read8(hw, B0_CTST);
4887 free_irq(pdev->irq, hw);
4888 if (hw->flags & SKY2_HW_USE_MSI)
4889 pci_disable_msi(pdev);
4890 pci_free_consistent(pdev, hw->st_size * sizeof(struct sky2_status_le),
4891 hw->st_le, hw->st_dma);
4892 pci_release_regions(pdev);
4893 pci_disable_device(pdev);
4895 for (i = hw->ports-1; i >= 0; --i)
4896 free_netdev(hw->dev[i]);
4901 pci_set_drvdata(pdev, NULL);
4904 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4906 struct sky2_hw *hw = pci_get_drvdata(pdev);
4912 del_timer_sync(&hw->watchdog_timer);
4913 cancel_work_sync(&hw->restart_work);
4916 for (i = 0; i < hw->ports; i++) {
4917 struct net_device *dev = hw->dev[i];
4918 struct sky2_port *sky2 = netdev_priv(dev);
4923 sky2_wol_init(sky2);
4928 device_set_wakeup_enable(&pdev->dev, wol != 0);
4930 sky2_write32(hw, B0_IMSK, 0);
4931 napi_disable(&hw->napi);
4935 pci_save_state(pdev);
4936 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4937 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4943 static int sky2_resume(struct pci_dev *pdev)
4945 struct sky2_hw *hw = pci_get_drvdata(pdev);
4952 err = pci_set_power_state(pdev, PCI_D0);
4956 err = pci_restore_state(pdev);
4960 pci_enable_wake(pdev, PCI_D0, 0);
4962 /* Re-enable all clocks */
4963 err = pci_write_config_dword(pdev, PCI_DEV_REG3, 0);
4965 dev_err(&pdev->dev, "PCI write config failed\n");
4970 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4971 napi_enable(&hw->napi);
4973 for (i = 0; i < hw->ports; i++) {
4974 err = sky2_reattach(hw->dev[i]);
4984 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4985 pci_disable_device(pdev);
4990 static void sky2_shutdown(struct pci_dev *pdev)
4992 sky2_suspend(pdev, PMSG_SUSPEND);
4995 static struct pci_driver sky2_driver = {
4997 .id_table = sky2_id_table,
4998 .probe = sky2_probe,
4999 .remove = __devexit_p(sky2_remove),
5001 .suspend = sky2_suspend,
5002 .resume = sky2_resume,
5004 .shutdown = sky2_shutdown,
5007 static int __init sky2_init_module(void)
5009 pr_info("driver version " DRV_VERSION "\n");
5012 return pci_register_driver(&sky2_driver);
5015 static void __exit sky2_cleanup_module(void)
5017 pci_unregister_driver(&sky2_driver);
5018 sky2_debug_cleanup();
5021 module_init(sky2_init_module);
5022 module_exit(sky2_cleanup_module);
5024 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
5025 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
5026 MODULE_LICENSE("GPL");
5027 MODULE_VERSION(DRV_VERSION);