2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/netdevice.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/etherdevice.h>
31 #include <linux/ethtool.h>
32 #include <linux/pci.h>
35 #include <linux/tcp.h>
37 #include <linux/delay.h>
38 #include <linux/workqueue.h>
39 #include <linux/if_vlan.h>
40 #include <linux/prefetch.h>
41 #include <linux/debugfs.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.26"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
67 /* This is the worst case number of transmit list elements for a single skb:
68 VLAN:GSO + CKSUM + Data + skb_frags * DMA */
69 #define MAX_SKB_TX_LE (2 + (sizeof(dma_addr_t)/sizeof(u32))*(MAX_SKB_FRAGS+1))
70 #define TX_MIN_PENDING (MAX_SKB_TX_LE+1)
71 #define TX_MAX_PENDING 4096
72 #define TX_DEF_PENDING 127
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define SKY2_EEPROM_MAGIC 0x9955aabb
83 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
85 static const u32 default_msg =
86 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
87 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
88 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
90 static int debug = -1; /* defaults above */
91 module_param(debug, int, 0);
92 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
94 static int copybreak __read_mostly = 128;
95 module_param(copybreak, int, 0);
96 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
98 static int disable_msi = 0;
99 module_param(disable_msi, int, 0);
100 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
102 static DEFINE_PCI_DEVICE_TABLE(sky2_id_table) = {
103 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E01) }, /* SK-9E21M */
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4354) }, /* 88E8040 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4355) }, /* 88E8040T */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4357) }, /* 88E8042 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x435A) }, /* 88E8048 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4365) }, /* 88E8070 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
134 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
135 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
136 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
137 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
138 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
139 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436C) }, /* 88E8072 */
140 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436D) }, /* 88E8055 */
141 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4370) }, /* 88E8075 */
142 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4380) }, /* 88E8057 */
143 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4381) }, /* 88E8059 */
147 MODULE_DEVICE_TABLE(pci, sky2_id_table);
149 /* Avoid conditionals by using array */
150 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
151 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
152 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
154 static void sky2_set_multicast(struct net_device *dev);
156 /* Access to PHY via serial interconnect */
157 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
165 for (i = 0; i < PHY_RETRIES; i++) {
166 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
170 if (!(ctrl & GM_SMI_CT_BUSY))
176 dev_warn(&hw->pdev->dev,"%s: phy write timeout\n", hw->dev[port]->name);
180 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
184 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
188 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
189 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
191 for (i = 0; i < PHY_RETRIES; i++) {
192 u16 ctrl = gma_read16(hw, port, GM_SMI_CTRL);
196 if (ctrl & GM_SMI_CT_RD_VAL) {
197 *val = gma_read16(hw, port, GM_SMI_DATA);
204 dev_warn(&hw->pdev->dev, "%s: phy read timeout\n", hw->dev[port]->name);
207 dev_err(&hw->pdev->dev, "%s: phy I/O error\n", hw->dev[port]->name);
211 static inline u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
214 __gm_phy_read(hw, port, reg, &v);
219 static void sky2_power_on(struct sky2_hw *hw)
221 /* switch power to VCC (WA for VAUX problem) */
222 sky2_write8(hw, B0_POWER_CTRL,
223 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
225 /* disable Core Clock Division, */
226 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
228 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
229 /* enable bits are inverted */
230 sky2_write8(hw, B2_Y2_CLK_GATE,
231 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
232 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
233 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
235 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
237 if (hw->flags & SKY2_HW_ADV_POWER_CTL) {
240 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
242 reg = sky2_pci_read32(hw, PCI_DEV_REG4);
243 /* set all bits to 0 except bits 15..12 and 8 */
244 reg &= P_ASPM_CONTROL_MSK;
245 sky2_pci_write32(hw, PCI_DEV_REG4, reg);
247 reg = sky2_pci_read32(hw, PCI_DEV_REG5);
248 /* set all bits to 0 except bits 28 & 27 */
249 reg &= P_CTL_TIM_VMAIN_AV_MSK;
250 sky2_pci_write32(hw, PCI_DEV_REG5, reg);
252 sky2_pci_write32(hw, PCI_CFG_REG_1, 0);
254 /* Enable workaround for dev 4.107 on Yukon-Ultra & Extreme */
255 reg = sky2_read32(hw, B2_GP_IO);
256 reg |= GLB_GPIO_STAT_RACE_DIS;
257 sky2_write32(hw, B2_GP_IO, reg);
259 sky2_read32(hw, B2_GP_IO);
262 /* Turn on "driver loaded" LED */
263 sky2_write16(hw, B0_CTST, Y2_LED_STAT_ON);
266 static void sky2_power_aux(struct sky2_hw *hw)
268 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
269 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
271 /* enable bits are inverted */
272 sky2_write8(hw, B2_Y2_CLK_GATE,
273 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
274 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
275 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
277 /* switch power to VAUX if supported and PME from D3cold */
278 if ( (sky2_read32(hw, B0_CTST) & Y2_VAUX_AVAIL) &&
279 pci_pme_capable(hw->pdev, PCI_D3cold))
280 sky2_write8(hw, B0_POWER_CTRL,
281 (PC_VAUX_ENA | PC_VCC_ENA |
282 PC_VAUX_ON | PC_VCC_OFF));
284 /* turn off "driver loaded LED" */
285 sky2_write16(hw, B0_CTST, Y2_LED_STAT_OFF);
288 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
292 /* disable all GMAC IRQ's */
293 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
295 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
296 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
297 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
298 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
300 reg = gma_read16(hw, port, GM_RX_CTRL);
301 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
302 gma_write16(hw, port, GM_RX_CTRL, reg);
305 /* flow control to advertise bits */
306 static const u16 copper_fc_adv[] = {
308 [FC_TX] = PHY_M_AN_ASP,
309 [FC_RX] = PHY_M_AN_PC,
310 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
313 /* flow control to advertise bits when using 1000BaseX */
314 static const u16 fiber_fc_adv[] = {
315 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
316 [FC_TX] = PHY_M_P_ASYM_MD_X,
317 [FC_RX] = PHY_M_P_SYM_MD_X,
318 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
321 /* flow control to GMA disable bits */
322 static const u16 gm_fc_disable[] = {
323 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
324 [FC_TX] = GM_GPCR_FC_RX_DIS,
325 [FC_RX] = GM_GPCR_FC_TX_DIS,
330 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
332 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
333 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
335 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
336 !(hw->flags & SKY2_HW_NEWER_PHY)) {
337 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
339 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
341 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
343 /* on PHY 88E1040 Rev.D0 (and newer) downshift control changed */
344 if (hw->chip_id == CHIP_ID_YUKON_EC)
345 /* set downshift counter to 3x and enable downshift */
346 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
348 /* set master & slave downshift counter to 1x */
349 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
351 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
354 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
355 if (sky2_is_copper(hw)) {
356 if (!(hw->flags & SKY2_HW_GIGABIT)) {
357 /* enable automatic crossover */
358 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
360 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
361 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
364 /* Enable Class A driver for FE+ A0 */
365 spec = gm_phy_read(hw, port, PHY_MARV_FE_SPEC_2);
366 spec |= PHY_M_FESC_SEL_CL_A;
367 gm_phy_write(hw, port, PHY_MARV_FE_SPEC_2, spec);
370 /* disable energy detect */
371 ctrl &= ~PHY_M_PC_EN_DET_MSK;
373 /* enable automatic crossover */
374 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
376 /* downshift on PHY 88E1112 and 88E1149 is changed */
377 if ( (sky2->flags & SKY2_FLAG_AUTO_SPEED) &&
378 (hw->flags & SKY2_HW_NEWER_PHY)) {
379 /* set downshift counter to 3x and enable downshift */
380 ctrl &= ~PHY_M_PC_DSC_MSK;
381 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
385 /* workaround for deviation #4.88 (CRC errors) */
386 /* disable Automatic Crossover */
388 ctrl &= ~PHY_M_PC_MDIX_MSK;
391 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
393 /* special setup for PHY 88E1112 Fiber */
394 if (hw->chip_id == CHIP_ID_YUKON_XL && (hw->flags & SKY2_HW_FIBRE_PHY)) {
395 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
397 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
398 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
399 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
400 ctrl &= ~PHY_M_MAC_MD_MSK;
401 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
402 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
404 if (hw->pmd_type == 'P') {
405 /* select page 1 to access Fiber registers */
406 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
408 /* for SFP-module set SIGDET polarity to low */
409 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
410 ctrl |= PHY_M_FIB_SIGD_POL;
411 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
414 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
422 if (sky2->flags & SKY2_FLAG_AUTO_SPEED) {
423 if (sky2_is_copper(hw)) {
424 if (sky2->advertising & ADVERTISED_1000baseT_Full)
425 ct1000 |= PHY_M_1000C_AFD;
426 if (sky2->advertising & ADVERTISED_1000baseT_Half)
427 ct1000 |= PHY_M_1000C_AHD;
428 if (sky2->advertising & ADVERTISED_100baseT_Full)
429 adv |= PHY_M_AN_100_FD;
430 if (sky2->advertising & ADVERTISED_100baseT_Half)
431 adv |= PHY_M_AN_100_HD;
432 if (sky2->advertising & ADVERTISED_10baseT_Full)
433 adv |= PHY_M_AN_10_FD;
434 if (sky2->advertising & ADVERTISED_10baseT_Half)
435 adv |= PHY_M_AN_10_HD;
437 } else { /* special defines for FIBER (88E1040S only) */
438 if (sky2->advertising & ADVERTISED_1000baseT_Full)
439 adv |= PHY_M_AN_1000X_AFD;
440 if (sky2->advertising & ADVERTISED_1000baseT_Half)
441 adv |= PHY_M_AN_1000X_AHD;
444 /* Restart Auto-negotiation */
445 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
447 /* forced speed/duplex settings */
448 ct1000 = PHY_M_1000C_MSE;
450 /* Disable auto update for duplex flow control and duplex */
451 reg |= GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_SPD_DIS;
453 switch (sky2->speed) {
455 ctrl |= PHY_CT_SP1000;
456 reg |= GM_GPCR_SPEED_1000;
459 ctrl |= PHY_CT_SP100;
460 reg |= GM_GPCR_SPEED_100;
464 if (sky2->duplex == DUPLEX_FULL) {
465 reg |= GM_GPCR_DUP_FULL;
466 ctrl |= PHY_CT_DUP_MD;
467 } else if (sky2->speed < SPEED_1000)
468 sky2->flow_mode = FC_NONE;
471 if (sky2->flags & SKY2_FLAG_AUTO_PAUSE) {
472 if (sky2_is_copper(hw))
473 adv |= copper_fc_adv[sky2->flow_mode];
475 adv |= fiber_fc_adv[sky2->flow_mode];
477 reg |= GM_GPCR_AU_FCT_DIS;
478 reg |= gm_fc_disable[sky2->flow_mode];
480 /* Forward pause packets to GMAC? */
481 if (sky2->flow_mode & FC_RX)
482 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
484 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
487 gma_write16(hw, port, GM_GP_CTRL, reg);
489 if (hw->flags & SKY2_HW_GIGABIT)
490 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
492 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
493 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
495 /* Setup Phy LED's */
496 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
499 switch (hw->chip_id) {
500 case CHIP_ID_YUKON_FE:
501 /* on 88E3082 these bits are at 11..9 (shifted left) */
502 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
504 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
506 /* delete ACT LED control bits */
507 ctrl &= ~PHY_M_FELP_LED1_MSK;
508 /* change ACT LED control to blink mode */
509 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
510 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
513 case CHIP_ID_YUKON_FE_P:
514 /* Enable Link Partner Next Page */
515 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
516 ctrl |= PHY_M_PC_ENA_LIP_NP;
518 /* disable Energy Detect and enable scrambler */
519 ctrl &= ~(PHY_M_PC_ENA_ENE_DT | PHY_M_PC_DIS_SCRAMB);
520 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
522 /* set LED2 -> ACT, LED1 -> LINK, LED0 -> SPEED */
523 ctrl = PHY_M_FELP_LED2_CTRL(LED_PAR_CTRL_ACT_BL) |
524 PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_LINK) |
525 PHY_M_FELP_LED0_CTRL(LED_PAR_CTRL_SPEED);
527 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
530 case CHIP_ID_YUKON_XL:
531 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
533 /* select page 3 to access LED control register */
534 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
536 /* set LED Function Control register */
537 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
538 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
539 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
540 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
541 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
543 /* set Polarity Control register */
544 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
545 (PHY_M_POLC_LS1_P_MIX(4) |
546 PHY_M_POLC_IS0_P_MIX(4) |
547 PHY_M_POLC_LOS_CTRL(2) |
548 PHY_M_POLC_INIT_CTRL(2) |
549 PHY_M_POLC_STA1_CTRL(2) |
550 PHY_M_POLC_STA0_CTRL(2)));
552 /* restore page register */
553 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
556 case CHIP_ID_YUKON_EC_U:
557 case CHIP_ID_YUKON_EX:
558 case CHIP_ID_YUKON_SUPR:
559 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
561 /* select page 3 to access LED control register */
562 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
564 /* set LED Function Control register */
565 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
566 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
567 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
568 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
569 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
571 /* set Blink Rate in LED Timer Control Register */
572 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
573 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
574 /* restore page register */
575 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
579 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
580 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
582 /* turn off the Rx LED (LED_RX) */
583 ledover |= PHY_M_LED_MO_RX(MO_LED_OFF);
586 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_UL_2) {
587 /* apply fixes in PHY AFE */
588 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
590 /* increase differential signal amplitude in 10BASE-T */
591 gm_phy_write(hw, port, 0x18, 0xaa99);
592 gm_phy_write(hw, port, 0x17, 0x2011);
594 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
595 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
596 gm_phy_write(hw, port, 0x18, 0xa204);
597 gm_phy_write(hw, port, 0x17, 0x2002);
600 /* set page register to 0 */
601 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
602 } else if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
603 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
604 /* apply workaround for integrated resistors calibration */
605 gm_phy_write(hw, port, PHY_MARV_PAGE_ADDR, 17);
606 gm_phy_write(hw, port, PHY_MARV_PAGE_DATA, 0x3f60);
607 } else if (hw->chip_id == CHIP_ID_YUKON_OPT && hw->chip_rev == 0) {
608 /* apply fixes in PHY AFE */
609 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0x00ff);
611 /* apply RDAC termination workaround */
612 gm_phy_write(hw, port, 24, 0x2800);
613 gm_phy_write(hw, port, 23, 0x2001);
615 /* set page register back to 0 */
616 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
617 } else if (hw->chip_id != CHIP_ID_YUKON_EX &&
618 hw->chip_id < CHIP_ID_YUKON_SUPR) {
619 /* no effect on Yukon-XL */
620 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
622 if (!(sky2->flags & SKY2_FLAG_AUTO_SPEED) ||
623 sky2->speed == SPEED_100) {
624 /* turn on 100 Mbps LED (LED_LINK100) */
625 ledover |= PHY_M_LED_MO_100(MO_LED_ON);
629 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
633 /* Enable phy interrupt on auto-negotiation complete (or link up) */
634 if (sky2->flags & SKY2_FLAG_AUTO_SPEED)
635 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
637 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
640 static const u32 phy_power[] = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
641 static const u32 coma_mode[] = { PCI_Y2_PHY1_COMA, PCI_Y2_PHY2_COMA };
643 static void sky2_phy_power_up(struct sky2_hw *hw, unsigned port)
647 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
648 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
649 reg1 &= ~phy_power[port];
651 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
652 reg1 |= coma_mode[port];
654 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
655 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
656 sky2_pci_read32(hw, PCI_DEV_REG1);
658 if (hw->chip_id == CHIP_ID_YUKON_FE)
659 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_ANE);
660 else if (hw->flags & SKY2_HW_ADV_POWER_CTL)
661 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
664 static void sky2_phy_power_down(struct sky2_hw *hw, unsigned port)
669 /* release GPHY Control reset */
670 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
672 /* release GMAC reset */
673 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
675 if (hw->flags & SKY2_HW_NEWER_PHY) {
676 /* select page 2 to access MAC control register */
677 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
679 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
680 /* allow GMII Power Down */
681 ctrl &= ~PHY_M_MAC_GMIF_PUP;
682 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
684 /* set page register back to 0 */
685 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
688 /* setup General Purpose Control Register */
689 gma_write16(hw, port, GM_GP_CTRL,
690 GM_GPCR_FL_PASS | GM_GPCR_SPEED_100 |
691 GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS |
694 if (hw->chip_id != CHIP_ID_YUKON_EC) {
695 if (hw->chip_id == CHIP_ID_YUKON_EC_U) {
696 /* select page 2 to access MAC control register */
697 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
699 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
700 /* enable Power Down */
701 ctrl |= PHY_M_PC_POW_D_ENA;
702 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
704 /* set page register back to 0 */
705 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
708 /* set IEEE compatible Power Down Mode (dev. #4.99) */
709 gm_phy_write(hw, port, PHY_MARV_CTRL, PHY_CT_PDOWN);
712 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
713 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
714 reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */
715 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
716 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
719 /* Force a renegotiation */
720 static void sky2_phy_reinit(struct sky2_port *sky2)
722 spin_lock_bh(&sky2->phy_lock);
723 sky2_phy_init(sky2->hw, sky2->port);
724 spin_unlock_bh(&sky2->phy_lock);
727 /* Put device in state to listen for Wake On Lan */
728 static void sky2_wol_init(struct sky2_port *sky2)
730 struct sky2_hw *hw = sky2->hw;
731 unsigned port = sky2->port;
732 enum flow_control save_mode;
736 /* Bring hardware out of reset */
737 sky2_write16(hw, B0_CTST, CS_RST_CLR);
738 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
740 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
741 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
744 * sky2_reset will re-enable on resume
746 save_mode = sky2->flow_mode;
747 ctrl = sky2->advertising;
749 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
750 sky2->flow_mode = FC_NONE;
752 spin_lock_bh(&sky2->phy_lock);
753 sky2_phy_power_up(hw, port);
754 sky2_phy_init(hw, port);
755 spin_unlock_bh(&sky2->phy_lock);
757 sky2->flow_mode = save_mode;
758 sky2->advertising = ctrl;
760 /* Set GMAC to no flow control and auto update for speed/duplex */
761 gma_write16(hw, port, GM_GP_CTRL,
762 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
763 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
765 /* Set WOL address */
766 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
767 sky2->netdev->dev_addr, ETH_ALEN);
769 /* Turn on appropriate WOL control bits */
770 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
772 if (sky2->wol & WAKE_PHY)
773 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
775 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
777 if (sky2->wol & WAKE_MAGIC)
778 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
780 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
782 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
783 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
785 /* Turn on legacy PCI-Express PME mode */
786 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
787 reg1 |= PCI_Y2_PME_LEGACY;
788 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
791 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
795 static void sky2_set_tx_stfwd(struct sky2_hw *hw, unsigned port)
797 struct net_device *dev = hw->dev[port];
799 if ( (hw->chip_id == CHIP_ID_YUKON_EX &&
800 hw->chip_rev != CHIP_REV_YU_EX_A0) ||
801 hw->chip_id >= CHIP_ID_YUKON_FE_P) {
802 /* Yukon-Extreme B0 and further Extreme devices */
803 /* enable Store & Forward mode for TX */
805 if (dev->mtu <= ETH_DATA_LEN)
806 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
807 TX_JUMBO_DIS | TX_STFW_ENA);
810 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
811 TX_JUMBO_ENA| TX_STFW_ENA);
813 if (dev->mtu <= ETH_DATA_LEN)
814 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_ENA);
816 /* set Tx GMAC FIFO Almost Empty Threshold */
817 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
818 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
820 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_STFW_DIS);
822 /* Can't do offload because of lack of store/forward */
823 dev->features &= ~(NETIF_F_TSO | NETIF_F_SG | NETIF_F_ALL_CSUM);
828 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
830 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
834 const u8 *addr = hw->dev[port]->dev_addr;
836 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
837 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
839 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
841 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
842 /* WA DEV_472 -- looks like crossed wires on port 2 */
843 /* clear GMAC 1 Control reset */
844 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
846 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
847 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
848 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
849 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
850 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
853 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
855 /* Enable Transmit FIFO Underrun */
856 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
858 spin_lock_bh(&sky2->phy_lock);
859 sky2_phy_power_up(hw, port);
860 sky2_phy_init(hw, port);
861 spin_unlock_bh(&sky2->phy_lock);
864 reg = gma_read16(hw, port, GM_PHY_ADDR);
865 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
867 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
868 gma_read16(hw, port, i);
869 gma_write16(hw, port, GM_PHY_ADDR, reg);
871 /* transmit control */
872 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
874 /* receive control reg: unicast + multicast + no FCS */
875 gma_write16(hw, port, GM_RX_CTRL,
876 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
878 /* transmit flow control */
879 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
881 /* transmit parameter */
882 gma_write16(hw, port, GM_TX_PARAM,
883 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
884 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
885 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
886 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
888 /* serial mode register */
889 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
890 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
892 if (hw->dev[port]->mtu > ETH_DATA_LEN)
893 reg |= GM_SMOD_JUMBO_ENA;
895 gma_write16(hw, port, GM_SERIAL_MODE, reg);
897 /* virtual address for data */
898 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
900 /* physical address: used for pause frames */
901 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
903 /* ignore counter overflows */
904 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
905 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
906 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
908 /* Configure Rx MAC FIFO */
909 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
910 rx_reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
911 if (hw->chip_id == CHIP_ID_YUKON_EX ||
912 hw->chip_id == CHIP_ID_YUKON_FE_P)
913 rx_reg |= GMF_RX_OVER_ON;
915 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), rx_reg);
917 if (hw->chip_id == CHIP_ID_YUKON_XL) {
918 /* Hardware errata - clear flush mask */
919 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), 0);
921 /* Flush Rx MAC FIFO on any flow control or error */
922 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
925 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
926 reg = RX_GMF_FL_THR_DEF + 1;
927 /* Another magic mystery workaround from sk98lin */
928 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
929 hw->chip_rev == CHIP_REV_YU_FE2_A0)
931 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), reg);
933 /* Configure Tx MAC FIFO */
934 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
935 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
937 /* On chips without ram buffer, pause is controled by MAC level */
938 if (!(hw->flags & SKY2_HW_RAM_BUFFER)) {
939 /* Pause threshold is scaled by 8 in bytes */
940 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
941 hw->chip_rev == CHIP_REV_YU_FE2_A0)
945 sky2_write16(hw, SK_REG(port, RX_GMF_UP_THR), reg);
946 sky2_write16(hw, SK_REG(port, RX_GMF_LP_THR), 768 / 8);
948 sky2_set_tx_stfwd(hw, port);
951 if (hw->chip_id == CHIP_ID_YUKON_FE_P &&
952 hw->chip_rev == CHIP_REV_YU_FE2_A0) {
953 /* disable dynamic watermark */
954 reg = sky2_read16(hw, SK_REG(port, TX_GMF_EA));
955 reg &= ~TX_DYN_WM_ENA;
956 sky2_write16(hw, SK_REG(port, TX_GMF_EA), reg);
960 /* Assign Ram Buffer allocation to queue */
961 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
965 /* convert from K bytes to qwords used for hw register */
968 end = start + space - 1;
970 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
971 sky2_write32(hw, RB_ADDR(q, RB_START), start);
972 sky2_write32(hw, RB_ADDR(q, RB_END), end);
973 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
974 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
976 if (q == Q_R1 || q == Q_R2) {
977 u32 tp = space - space/4;
979 /* On receive queue's set the thresholds
980 * give receiver priority when > 3/4 full
981 * send pause when down to 2K
983 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
984 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
987 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
988 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
990 /* Enable store & forward on Tx queue's because
991 * Tx FIFO is only 1K on Yukon
993 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
996 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
997 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
1000 /* Setup Bus Memory Interface */
1001 static void sky2_qset(struct sky2_hw *hw, u16 q)
1003 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
1004 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
1005 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
1006 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
1009 /* Setup prefetch unit registers. This is the interface between
1010 * hardware and driver list elements
1012 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
1013 dma_addr_t addr, u32 last)
1015 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1016 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
1017 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), upper_32_bits(addr));
1018 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), lower_32_bits(addr));
1019 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
1020 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
1022 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
1025 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2, u16 *slot)
1027 struct sky2_tx_le *le = sky2->tx_le + *slot;
1029 *slot = RING_NEXT(*slot, sky2->tx_ring_size);
1034 static void tx_init(struct sky2_port *sky2)
1036 struct sky2_tx_le *le;
1038 sky2->tx_prod = sky2->tx_cons = 0;
1039 sky2->tx_tcpsum = 0;
1040 sky2->tx_last_mss = 0;
1042 le = get_tx_le(sky2, &sky2->tx_prod);
1044 le->opcode = OP_ADDR64 | HW_OWNER;
1045 sky2->tx_last_upper = 0;
1048 /* Update chip's next pointer */
1049 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
1051 /* Make sure write' to descriptors are complete before we tell hardware */
1053 sky2_write16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX), idx);
1055 /* Synchronize I/O on since next processor may write to tail */
1060 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
1062 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
1063 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
1068 /* Build description to hardware for one receive segment */
1069 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
1070 dma_addr_t map, unsigned len)
1072 struct sky2_rx_le *le;
1074 if (sizeof(dma_addr_t) > sizeof(u32)) {
1075 le = sky2_next_rx(sky2);
1076 le->addr = cpu_to_le32(upper_32_bits(map));
1077 le->opcode = OP_ADDR64 | HW_OWNER;
1080 le = sky2_next_rx(sky2);
1081 le->addr = cpu_to_le32(lower_32_bits(map));
1082 le->length = cpu_to_le16(len);
1083 le->opcode = op | HW_OWNER;
1086 /* Build description to hardware for one possibly fragmented skb */
1087 static void sky2_rx_submit(struct sky2_port *sky2,
1088 const struct rx_ring_info *re)
1092 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
1094 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
1095 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
1099 static int sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
1102 struct sk_buff *skb = re->skb;
1105 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
1106 if (unlikely(pci_dma_mapping_error(pdev, re->data_addr)))
1109 pci_unmap_len_set(re, data_size, size);
1111 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1112 re->frag_addr[i] = pci_map_page(pdev,
1113 skb_shinfo(skb)->frags[i].page,
1114 skb_shinfo(skb)->frags[i].page_offset,
1115 skb_shinfo(skb)->frags[i].size,
1116 PCI_DMA_FROMDEVICE);
1120 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
1122 struct sk_buff *skb = re->skb;
1125 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
1126 PCI_DMA_FROMDEVICE);
1128 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
1129 pci_unmap_page(pdev, re->frag_addr[i],
1130 skb_shinfo(skb)->frags[i].size,
1131 PCI_DMA_FROMDEVICE);
1134 /* Tell chip where to start receive checksum.
1135 * Actually has two checksums, but set both same to avoid possible byte
1138 static void rx_set_checksum(struct sky2_port *sky2)
1140 struct sky2_rx_le *le = sky2_next_rx(sky2);
1142 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
1144 le->opcode = OP_TCPSTART | HW_OWNER;
1146 sky2_write32(sky2->hw,
1147 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
1148 (sky2->flags & SKY2_FLAG_RX_CHECKSUM)
1149 ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
1153 * The RX Stop command will not work for Yukon-2 if the BMU does not
1154 * reach the end of packet and since we can't make sure that we have
1155 * incoming data, we must reset the BMU while it is not doing a DMA
1156 * transfer. Since it is possible that the RX path is still active,
1157 * the RX RAM buffer will be stopped first, so any possible incoming
1158 * data will not trigger a DMA. After the RAM buffer is stopped, the
1159 * BMU is polled until any DMA in progress is ended and only then it
1162 static void sky2_rx_stop(struct sky2_port *sky2)
1164 struct sky2_hw *hw = sky2->hw;
1165 unsigned rxq = rxqaddr[sky2->port];
1168 /* disable the RAM Buffer receive queue */
1169 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
1171 for (i = 0; i < 0xffff; i++)
1172 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
1173 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
1176 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
1177 sky2->netdev->name);
1179 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
1181 /* reset the Rx prefetch unit */
1182 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
1186 /* Clean out receive buffer area, assumes receiver hardware stopped */
1187 static void sky2_rx_clean(struct sky2_port *sky2)
1191 memset(sky2->rx_le, 0, RX_LE_BYTES);
1192 for (i = 0; i < sky2->rx_pending; i++) {
1193 struct rx_ring_info *re = sky2->rx_ring + i;
1196 sky2_rx_unmap_skb(sky2->hw->pdev, re);
1203 /* Basic MII support */
1204 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1206 struct mii_ioctl_data *data = if_mii(ifr);
1207 struct sky2_port *sky2 = netdev_priv(dev);
1208 struct sky2_hw *hw = sky2->hw;
1209 int err = -EOPNOTSUPP;
1211 if (!netif_running(dev))
1212 return -ENODEV; /* Phy still in reset */
1216 data->phy_id = PHY_ADDR_MARV;
1222 spin_lock_bh(&sky2->phy_lock);
1223 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1224 spin_unlock_bh(&sky2->phy_lock);
1226 data->val_out = val;
1231 spin_lock_bh(&sky2->phy_lock);
1232 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1234 spin_unlock_bh(&sky2->phy_lock);
1240 #ifdef SKY2_VLAN_TAG_USED
1241 static void sky2_set_vlan_mode(struct sky2_hw *hw, u16 port, bool onoff)
1244 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1246 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1249 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
1251 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1256 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1258 struct sky2_port *sky2 = netdev_priv(dev);
1259 struct sky2_hw *hw = sky2->hw;
1260 u16 port = sky2->port;
1262 netif_tx_lock_bh(dev);
1263 napi_disable(&hw->napi);
1266 sky2_set_vlan_mode(hw, port, grp != NULL);
1268 sky2_read32(hw, B0_Y2_SP_LISR);
1269 napi_enable(&hw->napi);
1270 netif_tx_unlock_bh(dev);
1274 /* Amount of required worst case padding in rx buffer */
1275 static inline unsigned sky2_rx_pad(const struct sky2_hw *hw)
1277 return (hw->flags & SKY2_HW_RAM_BUFFER) ? 8 : 2;
1281 * Allocate an skb for receiving. If the MTU is large enough
1282 * make the skb non-linear with a fragment list of pages.
1284 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1286 struct sk_buff *skb;
1289 skb = netdev_alloc_skb(sky2->netdev,
1290 sky2->rx_data_size + sky2_rx_pad(sky2->hw));
1294 if (sky2->hw->flags & SKY2_HW_RAM_BUFFER) {
1295 unsigned char *start;
1297 * Workaround for a bug in FIFO that cause hang
1298 * if the FIFO if the receive buffer is not 64 byte aligned.
1299 * The buffer returned from netdev_alloc_skb is
1300 * aligned except if slab debugging is enabled.
1302 start = PTR_ALIGN(skb->data, 8);
1303 skb_reserve(skb, start - skb->data);
1305 skb_reserve(skb, NET_IP_ALIGN);
1307 for (i = 0; i < sky2->rx_nfrags; i++) {
1308 struct page *page = alloc_page(GFP_ATOMIC);
1312 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1322 static inline void sky2_rx_update(struct sky2_port *sky2, unsigned rxq)
1324 sky2_put_idx(sky2->hw, rxq, sky2->rx_put);
1328 * Allocate and setup receiver buffer pool.
1329 * Normal case this ends up creating one list element for skb
1330 * in the receive ring. Worst case if using large MTU and each
1331 * allocation falls on a different 64 bit region, that results
1332 * in 6 list elements per ring entry.
1333 * One element is used for checksum enable/disable, and one
1334 * extra to avoid wrap.
1336 static int sky2_rx_start(struct sky2_port *sky2)
1338 struct sky2_hw *hw = sky2->hw;
1339 struct rx_ring_info *re;
1340 unsigned rxq = rxqaddr[sky2->port];
1341 unsigned i, size, thresh;
1343 sky2->rx_put = sky2->rx_next = 0;
1346 /* On PCI express lowering the watermark gives better performance */
1347 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1348 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1350 /* These chips have no ram buffer?
1351 * MAC Rx RAM Read is controlled by hardware */
1352 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1353 (hw->chip_rev == CHIP_REV_YU_EC_U_A1 ||
1354 hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1355 sky2_write32(hw, Q_ADDR(rxq, Q_TEST), F_M_RX_RAM_DIS);
1357 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1359 if (!(hw->flags & SKY2_HW_NEW_LE))
1360 rx_set_checksum(sky2);
1362 /* Space needed for frame data + headers rounded up */
1363 size = roundup(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8);
1365 /* Stopping point for hardware truncation */
1366 thresh = (size - 8) / sizeof(u32);
1368 sky2->rx_nfrags = size >> PAGE_SHIFT;
1369 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1371 /* Compute residue after pages */
1372 size -= sky2->rx_nfrags << PAGE_SHIFT;
1374 /* Optimize to handle small packets and headers */
1375 if (size < copybreak)
1377 if (size < ETH_HLEN)
1380 sky2->rx_data_size = size;
1383 for (i = 0; i < sky2->rx_pending; i++) {
1384 re = sky2->rx_ring + i;
1386 re->skb = sky2_rx_alloc(sky2);
1390 if (sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size)) {
1391 dev_kfree_skb(re->skb);
1396 sky2_rx_submit(sky2, re);
1400 * The receiver hangs if it receives frames larger than the
1401 * packet buffer. As a workaround, truncate oversize frames, but
1402 * the register is limited to 9 bits, so if you do frames > 2052
1403 * you better get the MTU right!
1406 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1408 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1409 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1412 /* Tell chip about available buffers */
1413 sky2_rx_update(sky2, rxq);
1415 if (hw->chip_id == CHIP_ID_YUKON_EX ||
1416 hw->chip_id == CHIP_ID_YUKON_SUPR) {
1418 * Disable flushing of non ASF packets;
1419 * must be done after initializing the BMUs;
1420 * drivers without ASF support should do this too, otherwise
1421 * it may happen that they cannot run on ASF devices;
1422 * remember that the MAC FIFO isn't reset during initialization.
1424 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_MACSEC_FLUSH_OFF);
1427 if (hw->chip_id >= CHIP_ID_YUKON_SUPR) {
1428 /* Enable RX Home Address & Routing Header checksum fix */
1429 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_FL_CTRL),
1430 RX_IPV6_SA_MOB_ENA | RX_IPV6_DA_MOB_ENA);
1432 /* Enable TX Home Address & Routing Header checksum fix */
1433 sky2_write32(hw, Q_ADDR(txqaddr[sky2->port], Q_TEST),
1434 TBMU_TEST_HOME_ADD_FIX_EN | TBMU_TEST_ROUTING_ADD_FIX_EN);
1441 sky2_rx_clean(sky2);
1445 static int sky2_alloc_buffers(struct sky2_port *sky2)
1447 struct sky2_hw *hw = sky2->hw;
1449 /* must be power of 2 */
1450 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1451 sky2->tx_ring_size *
1452 sizeof(struct sky2_tx_le),
1457 sky2->tx_ring = kcalloc(sky2->tx_ring_size, sizeof(struct tx_ring_info),
1462 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1466 memset(sky2->rx_le, 0, RX_LE_BYTES);
1468 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1478 static void sky2_free_buffers(struct sky2_port *sky2)
1480 struct sky2_hw *hw = sky2->hw;
1483 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1484 sky2->rx_le, sky2->rx_le_map);
1488 pci_free_consistent(hw->pdev,
1489 sky2->tx_ring_size * sizeof(struct sky2_tx_le),
1490 sky2->tx_le, sky2->tx_le_map);
1493 kfree(sky2->tx_ring);
1494 kfree(sky2->rx_ring);
1496 sky2->tx_ring = NULL;
1497 sky2->rx_ring = NULL;
1500 /* Bring up network interface. */
1501 static int sky2_up(struct net_device *dev)
1503 struct sky2_port *sky2 = netdev_priv(dev);
1504 struct sky2_hw *hw = sky2->hw;
1505 unsigned port = sky2->port;
1508 struct net_device *otherdev = hw->dev[sky2->port^1];
1511 * On dual port PCI-X card, there is an problem where status
1512 * can be received out of order due to split transactions
1514 if (otherdev && netif_running(otherdev) &&
1515 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1518 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1519 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1520 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1524 netif_carrier_off(dev);
1526 err = sky2_alloc_buffers(sky2);
1532 sky2_mac_init(hw, port);
1534 /* Register is number of 4K blocks on internal RAM buffer. */
1535 ramsize = sky2_read8(hw, B2_E_0) * 4;
1539 pr_debug(PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1541 rxspace = ramsize / 2;
1543 rxspace = 8 + (2*(ramsize - 16))/3;
1545 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1546 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1548 /* Make sure SyncQ is disabled */
1549 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1553 sky2_qset(hw, txqaddr[port]);
1555 /* This is copied from sk98lin 10.0.5.3; no one tells me about erratta's */
1556 if (hw->chip_id == CHIP_ID_YUKON_EX && hw->chip_rev == CHIP_REV_YU_EX_B0)
1557 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_TEST), F_TX_CHK_AUTO_OFF);
1559 /* Set almost empty threshold */
1560 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1561 hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1562 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1564 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1565 sky2->tx_ring_size - 1);
1567 #ifdef SKY2_VLAN_TAG_USED
1568 sky2_set_vlan_mode(hw, port, sky2->vlgrp != NULL);
1571 err = sky2_rx_start(sky2);
1575 /* Enable interrupts from phy/mac for port */
1576 imask = sky2_read32(hw, B0_IMSK);
1577 imask |= portirq_msk[port];
1578 sky2_write32(hw, B0_IMSK, imask);
1579 sky2_read32(hw, B0_IMSK);
1581 if (netif_msg_ifup(sky2))
1582 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1587 sky2_free_buffers(sky2);
1591 /* Modular subtraction in ring */
1592 static inline int tx_inuse(const struct sky2_port *sky2)
1594 return (sky2->tx_prod - sky2->tx_cons) & (sky2->tx_ring_size - 1);
1597 /* Number of list elements available for next tx */
1598 static inline int tx_avail(const struct sky2_port *sky2)
1600 return sky2->tx_pending - tx_inuse(sky2);
1603 /* Estimate of number of transmit list elements required */
1604 static unsigned tx_le_req(const struct sk_buff *skb)
1608 count = (skb_shinfo(skb)->nr_frags + 1)
1609 * (sizeof(dma_addr_t) / sizeof(u32));
1611 if (skb_is_gso(skb))
1613 else if (sizeof(dma_addr_t) == sizeof(u32))
1614 ++count; /* possible vlan */
1616 if (skb->ip_summed == CHECKSUM_PARTIAL)
1622 static void sky2_tx_unmap(struct pci_dev *pdev, struct tx_ring_info *re)
1624 if (re->flags & TX_MAP_SINGLE)
1625 pci_unmap_single(pdev, pci_unmap_addr(re, mapaddr),
1626 pci_unmap_len(re, maplen),
1628 else if (re->flags & TX_MAP_PAGE)
1629 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1630 pci_unmap_len(re, maplen),
1636 * Put one packet in ring for transmit.
1637 * A single packet can generate multiple list elements, and
1638 * the number of ring elements will probably be less than the number
1639 * of list elements used.
1641 static netdev_tx_t sky2_xmit_frame(struct sk_buff *skb,
1642 struct net_device *dev)
1644 struct sky2_port *sky2 = netdev_priv(dev);
1645 struct sky2_hw *hw = sky2->hw;
1646 struct sky2_tx_le *le = NULL;
1647 struct tx_ring_info *re;
1655 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1656 return NETDEV_TX_BUSY;
1658 len = skb_headlen(skb);
1659 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1661 if (pci_dma_mapping_error(hw->pdev, mapping))
1664 slot = sky2->tx_prod;
1665 if (unlikely(netif_msg_tx_queued(sky2)))
1666 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1667 dev->name, slot, skb->len);
1669 /* Send high bits if needed */
1670 upper = upper_32_bits(mapping);
1671 if (upper != sky2->tx_last_upper) {
1672 le = get_tx_le(sky2, &slot);
1673 le->addr = cpu_to_le32(upper);
1674 sky2->tx_last_upper = upper;
1675 le->opcode = OP_ADDR64 | HW_OWNER;
1678 /* Check for TCP Segmentation Offload */
1679 mss = skb_shinfo(skb)->gso_size;
1682 if (!(hw->flags & SKY2_HW_NEW_LE))
1683 mss += ETH_HLEN + ip_hdrlen(skb) + tcp_hdrlen(skb);
1685 if (mss != sky2->tx_last_mss) {
1686 le = get_tx_le(sky2, &slot);
1687 le->addr = cpu_to_le32(mss);
1689 if (hw->flags & SKY2_HW_NEW_LE)
1690 le->opcode = OP_MSS | HW_OWNER;
1692 le->opcode = OP_LRGLEN | HW_OWNER;
1693 sky2->tx_last_mss = mss;
1698 #ifdef SKY2_VLAN_TAG_USED
1699 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1700 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1702 le = get_tx_le(sky2, &slot);
1704 le->opcode = OP_VLAN|HW_OWNER;
1706 le->opcode |= OP_VLAN;
1707 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1712 /* Handle TCP checksum offload */
1713 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1714 /* On Yukon EX (some versions) encoding change. */
1715 if (hw->flags & SKY2_HW_AUTO_TX_SUM)
1716 ctrl |= CALSUM; /* auto checksum */
1718 const unsigned offset = skb_transport_offset(skb);
1721 tcpsum = offset << 16; /* sum start */
1722 tcpsum |= offset + skb->csum_offset; /* sum write */
1724 ctrl |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1725 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1728 if (tcpsum != sky2->tx_tcpsum) {
1729 sky2->tx_tcpsum = tcpsum;
1731 le = get_tx_le(sky2, &slot);
1732 le->addr = cpu_to_le32(tcpsum);
1733 le->length = 0; /* initial checksum value */
1734 le->ctrl = 1; /* one packet */
1735 le->opcode = OP_TCPLISW | HW_OWNER;
1740 re = sky2->tx_ring + slot;
1741 re->flags = TX_MAP_SINGLE;
1742 pci_unmap_addr_set(re, mapaddr, mapping);
1743 pci_unmap_len_set(re, maplen, len);
1745 le = get_tx_le(sky2, &slot);
1746 le->addr = cpu_to_le32(lower_32_bits(mapping));
1747 le->length = cpu_to_le16(len);
1749 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1752 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1753 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1755 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1756 frag->size, PCI_DMA_TODEVICE);
1758 if (pci_dma_mapping_error(hw->pdev, mapping))
1759 goto mapping_unwind;
1761 upper = upper_32_bits(mapping);
1762 if (upper != sky2->tx_last_upper) {
1763 le = get_tx_le(sky2, &slot);
1764 le->addr = cpu_to_le32(upper);
1765 sky2->tx_last_upper = upper;
1766 le->opcode = OP_ADDR64 | HW_OWNER;
1769 re = sky2->tx_ring + slot;
1770 re->flags = TX_MAP_PAGE;
1771 pci_unmap_addr_set(re, mapaddr, mapping);
1772 pci_unmap_len_set(re, maplen, frag->size);
1774 le = get_tx_le(sky2, &slot);
1775 le->addr = cpu_to_le32(lower_32_bits(mapping));
1776 le->length = cpu_to_le16(frag->size);
1778 le->opcode = OP_BUFFER | HW_OWNER;
1784 sky2->tx_prod = slot;
1786 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1787 netif_stop_queue(dev);
1789 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1791 return NETDEV_TX_OK;
1794 for (i = sky2->tx_prod; i != slot; i = RING_NEXT(i, sky2->tx_ring_size)) {
1795 re = sky2->tx_ring + i;
1797 sky2_tx_unmap(hw->pdev, re);
1801 if (net_ratelimit())
1802 dev_warn(&hw->pdev->dev, "%s: tx mapping error\n", dev->name);
1804 return NETDEV_TX_OK;
1808 * Free ring elements from starting at tx_cons until "done"
1811 * 1. The hardware will tell us about partial completion of multi-part
1812 * buffers so make sure not to free skb to early.
1813 * 2. This may run in parallel start_xmit because the it only
1814 * looks at the tail of the queue of FIFO (tx_cons), not
1815 * the head (tx_prod)
1817 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1819 struct net_device *dev = sky2->netdev;
1822 BUG_ON(done >= sky2->tx_ring_size);
1824 for (idx = sky2->tx_cons; idx != done;
1825 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
1826 struct tx_ring_info *re = sky2->tx_ring + idx;
1827 struct sk_buff *skb = re->skb;
1829 sky2_tx_unmap(sky2->hw->pdev, re);
1832 if (unlikely(netif_msg_tx_done(sky2)))
1833 printk(KERN_DEBUG "%s: tx done %u\n",
1836 dev->stats.tx_packets++;
1837 dev->stats.tx_bytes += skb->len;
1840 dev_kfree_skb_any(skb);
1842 sky2->tx_next = RING_NEXT(idx, sky2->tx_ring_size);
1846 sky2->tx_cons = idx;
1849 /* Wake unless it's detached, and called e.g. from sky2_down() */
1850 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4 && netif_device_present(dev))
1851 netif_wake_queue(dev);
1854 static void sky2_tx_reset(struct sky2_hw *hw, unsigned port)
1856 /* Disable Force Sync bit and Enable Alloc bit */
1857 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1858 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1860 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1861 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1862 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1864 /* Reset the PCI FIFO of the async Tx queue */
1865 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1866 BMU_RST_SET | BMU_FIFO_RST);
1868 /* Reset the Tx prefetch units */
1869 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1872 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1873 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1876 /* Network shutdown */
1877 static int sky2_down(struct net_device *dev)
1879 struct sky2_port *sky2 = netdev_priv(dev);
1880 struct sky2_hw *hw = sky2->hw;
1881 unsigned port = sky2->port;
1885 /* Never really got started! */
1889 if (netif_msg_ifdown(sky2))
1890 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1892 /* Force flow control off */
1893 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1895 /* Stop transmitter */
1896 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1897 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1899 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1900 RB_RST_SET | RB_DIS_OP_MD);
1902 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1903 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1904 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1906 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1908 /* Workaround shared GMAC reset */
1909 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 &&
1910 port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1911 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1913 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1915 /* Force any delayed status interrrupt and NAPI */
1916 sky2_write32(hw, STAT_LEV_TIMER_CNT, 0);
1917 sky2_write32(hw, STAT_TX_TIMER_CNT, 0);
1918 sky2_write32(hw, STAT_ISR_TIMER_CNT, 0);
1919 sky2_read8(hw, STAT_ISR_TIMER_CTRL);
1923 /* Disable port IRQ */
1924 imask = sky2_read32(hw, B0_IMSK);
1925 imask &= ~portirq_msk[port];
1926 sky2_write32(hw, B0_IMSK, imask);
1927 sky2_read32(hw, B0_IMSK);
1929 synchronize_irq(hw->pdev->irq);
1930 napi_synchronize(&hw->napi);
1932 spin_lock_bh(&sky2->phy_lock);
1933 sky2_phy_power_down(hw, port);
1934 spin_unlock_bh(&sky2->phy_lock);
1936 sky2_tx_reset(hw, port);
1938 /* Free any pending frames stuck in HW queue */
1939 sky2_tx_complete(sky2, sky2->tx_prod);
1941 sky2_rx_clean(sky2);
1943 sky2_free_buffers(sky2);
1948 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1950 if (hw->flags & SKY2_HW_FIBRE_PHY)
1953 if (!(hw->flags & SKY2_HW_GIGABIT)) {
1954 if (aux & PHY_M_PS_SPEED_100)
1960 switch (aux & PHY_M_PS_SPEED_MSK) {
1961 case PHY_M_PS_SPEED_1000:
1963 case PHY_M_PS_SPEED_100:
1970 static void sky2_link_up(struct sky2_port *sky2)
1972 struct sky2_hw *hw = sky2->hw;
1973 unsigned port = sky2->port;
1975 static const char *fc_name[] = {
1983 reg = gma_read16(hw, port, GM_GP_CTRL);
1984 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1985 gma_write16(hw, port, GM_GP_CTRL, reg);
1987 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1989 netif_carrier_on(sky2->netdev);
1991 mod_timer(&hw->watchdog_timer, jiffies + 1);
1993 /* Turn on link LED */
1994 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1995 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1997 if (netif_msg_link(sky2))
1998 printk(KERN_INFO PFX
1999 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
2000 sky2->netdev->name, sky2->speed,
2001 sky2->duplex == DUPLEX_FULL ? "full" : "half",
2002 fc_name[sky2->flow_status]);
2005 static void sky2_link_down(struct sky2_port *sky2)
2007 struct sky2_hw *hw = sky2->hw;
2008 unsigned port = sky2->port;
2011 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
2013 reg = gma_read16(hw, port, GM_GP_CTRL);
2014 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2015 gma_write16(hw, port, GM_GP_CTRL, reg);
2017 netif_carrier_off(sky2->netdev);
2019 /* Turn off link LED */
2020 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
2022 if (netif_msg_link(sky2))
2023 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
2025 sky2_phy_init(hw, port);
2028 static enum flow_control sky2_flow(int rx, int tx)
2031 return tx ? FC_BOTH : FC_RX;
2033 return tx ? FC_TX : FC_NONE;
2036 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
2038 struct sky2_hw *hw = sky2->hw;
2039 unsigned port = sky2->port;
2042 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2043 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
2044 if (lpa & PHY_M_AN_RF) {
2045 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
2049 if (!(aux & PHY_M_PS_SPDUP_RES)) {
2050 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
2051 sky2->netdev->name);
2055 sky2->speed = sky2_phy_speed(hw, aux);
2056 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2058 /* Since the pause result bits seem to in different positions on
2059 * different chips. look at registers.
2061 if (hw->flags & SKY2_HW_FIBRE_PHY) {
2062 /* Shift for bits in fiber PHY */
2063 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
2064 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
2066 if (advert & ADVERTISE_1000XPAUSE)
2067 advert |= ADVERTISE_PAUSE_CAP;
2068 if (advert & ADVERTISE_1000XPSE_ASYM)
2069 advert |= ADVERTISE_PAUSE_ASYM;
2070 if (lpa & LPA_1000XPAUSE)
2071 lpa |= LPA_PAUSE_CAP;
2072 if (lpa & LPA_1000XPAUSE_ASYM)
2073 lpa |= LPA_PAUSE_ASYM;
2076 sky2->flow_status = FC_NONE;
2077 if (advert & ADVERTISE_PAUSE_CAP) {
2078 if (lpa & LPA_PAUSE_CAP)
2079 sky2->flow_status = FC_BOTH;
2080 else if (advert & ADVERTISE_PAUSE_ASYM)
2081 sky2->flow_status = FC_RX;
2082 } else if (advert & ADVERTISE_PAUSE_ASYM) {
2083 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
2084 sky2->flow_status = FC_TX;
2087 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000 &&
2088 !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
2089 sky2->flow_status = FC_NONE;
2091 if (sky2->flow_status & FC_TX)
2092 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2094 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2099 /* Interrupt from PHY */
2100 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
2102 struct net_device *dev = hw->dev[port];
2103 struct sky2_port *sky2 = netdev_priv(dev);
2104 u16 istatus, phystat;
2106 if (!netif_running(dev))
2109 spin_lock(&sky2->phy_lock);
2110 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2111 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2113 if (netif_msg_intr(sky2))
2114 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
2115 sky2->netdev->name, istatus, phystat);
2117 if (istatus & PHY_M_IS_AN_COMPL) {
2118 if (sky2_autoneg_done(sky2, phystat) == 0)
2123 if (istatus & PHY_M_IS_LSP_CHANGE)
2124 sky2->speed = sky2_phy_speed(hw, phystat);
2126 if (istatus & PHY_M_IS_DUP_CHANGE)
2128 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2130 if (istatus & PHY_M_IS_LST_CHANGE) {
2131 if (phystat & PHY_M_PS_LINK_UP)
2134 sky2_link_down(sky2);
2137 spin_unlock(&sky2->phy_lock);
2140 /* Special quick link interrupt (Yukon-2 Optima only) */
2141 static void sky2_qlink_intr(struct sky2_hw *hw)
2143 struct sky2_port *sky2 = netdev_priv(hw->dev[0]);
2148 imask = sky2_read32(hw, B0_IMSK);
2149 imask &= ~Y2_IS_PHY_QLNK;
2150 sky2_write32(hw, B0_IMSK, imask);
2152 /* reset PHY Link Detect */
2153 phy = sky2_pci_read16(hw, PSM_CONFIG_REG4);
2154 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2155 sky2_pci_write16(hw, PSM_CONFIG_REG4, phy | 1);
2156 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2161 /* Transmit timeout is only called if we are running, carrier is up
2162 * and tx queue is full (stopped).
2164 static void sky2_tx_timeout(struct net_device *dev)
2166 struct sky2_port *sky2 = netdev_priv(dev);
2167 struct sky2_hw *hw = sky2->hw;
2169 if (netif_msg_timer(sky2))
2170 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
2172 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
2173 dev->name, sky2->tx_cons, sky2->tx_prod,
2174 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
2175 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
2177 /* can't restart safely under softirq */
2178 schedule_work(&hw->restart_work);
2181 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
2183 struct sky2_port *sky2 = netdev_priv(dev);
2184 struct sky2_hw *hw = sky2->hw;
2185 unsigned port = sky2->port;
2190 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2193 if (new_mtu > ETH_DATA_LEN &&
2194 (hw->chip_id == CHIP_ID_YUKON_FE ||
2195 hw->chip_id == CHIP_ID_YUKON_FE_P))
2198 if (!netif_running(dev)) {
2203 imask = sky2_read32(hw, B0_IMSK);
2204 sky2_write32(hw, B0_IMSK, 0);
2206 dev->trans_start = jiffies; /* prevent tx timeout */
2207 netif_stop_queue(dev);
2208 napi_disable(&hw->napi);
2210 synchronize_irq(hw->pdev->irq);
2212 if (!(hw->flags & SKY2_HW_RAM_BUFFER))
2213 sky2_set_tx_stfwd(hw, port);
2215 ctl = gma_read16(hw, port, GM_GP_CTRL);
2216 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
2218 sky2_rx_clean(sky2);
2222 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
2223 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2225 if (dev->mtu > ETH_DATA_LEN)
2226 mode |= GM_SMOD_JUMBO_ENA;
2228 gma_write16(hw, port, GM_SERIAL_MODE, mode);
2230 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
2232 err = sky2_rx_start(sky2);
2233 sky2_write32(hw, B0_IMSK, imask);
2235 sky2_read32(hw, B0_Y2_SP_LISR);
2236 napi_enable(&hw->napi);
2241 gma_write16(hw, port, GM_GP_CTRL, ctl);
2243 netif_wake_queue(dev);
2249 /* For small just reuse existing skb for next receive */
2250 static struct sk_buff *receive_copy(struct sky2_port *sky2,
2251 const struct rx_ring_info *re,
2254 struct sk_buff *skb;
2256 skb = netdev_alloc_skb_ip_align(sky2->netdev, length);
2258 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
2259 length, PCI_DMA_FROMDEVICE);
2260 skb_copy_from_linear_data(re->skb, skb->data, length);
2261 skb->ip_summed = re->skb->ip_summed;
2262 skb->csum = re->skb->csum;
2263 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
2264 length, PCI_DMA_FROMDEVICE);
2265 re->skb->ip_summed = CHECKSUM_NONE;
2266 skb_put(skb, length);
2271 /* Adjust length of skb with fragments to match received data */
2272 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
2273 unsigned int length)
2278 /* put header into skb */
2279 size = min(length, hdr_space);
2284 num_frags = skb_shinfo(skb)->nr_frags;
2285 for (i = 0; i < num_frags; i++) {
2286 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2289 /* don't need this page */
2290 __free_page(frag->page);
2291 --skb_shinfo(skb)->nr_frags;
2293 size = min(length, (unsigned) PAGE_SIZE);
2296 skb->data_len += size;
2297 skb->truesize += size;
2304 /* Normal packet - take skb from ring element and put in a new one */
2305 static struct sk_buff *receive_new(struct sky2_port *sky2,
2306 struct rx_ring_info *re,
2307 unsigned int length)
2309 struct sk_buff *skb, *nskb;
2310 unsigned hdr_space = sky2->rx_data_size;
2312 /* Don't be tricky about reusing pages (yet) */
2313 nskb = sky2_rx_alloc(sky2);
2314 if (unlikely(!nskb))
2318 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2320 prefetch(skb->data);
2322 if (sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space)) {
2323 dev_kfree_skb(nskb);
2328 if (skb_shinfo(skb)->nr_frags)
2329 skb_put_frags(skb, hdr_space, length);
2331 skb_put(skb, length);
2336 * Receive one packet.
2337 * For larger packets, get new buffer.
2339 static struct sk_buff *sky2_receive(struct net_device *dev,
2340 u16 length, u32 status)
2342 struct sky2_port *sky2 = netdev_priv(dev);
2343 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2344 struct sk_buff *skb = NULL;
2345 u16 count = (status & GMR_FS_LEN) >> 16;
2347 #ifdef SKY2_VLAN_TAG_USED
2348 /* Account for vlan tag */
2349 if (sky2->vlgrp && (status & GMR_FS_VLAN))
2353 if (unlikely(netif_msg_rx_status(sky2)))
2354 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2355 dev->name, sky2->rx_next, status, length);
2357 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2358 prefetch(sky2->rx_ring + sky2->rx_next);
2360 /* This chip has hardware problems that generates bogus status.
2361 * So do only marginal checking and expect higher level protocols
2362 * to handle crap frames.
2364 if (sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
2365 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0 &&
2369 if (status & GMR_FS_ANY_ERR)
2372 if (!(status & GMR_FS_RX_OK))
2375 /* if length reported by DMA does not match PHY, packet was truncated */
2376 if (length != count)
2380 if (length < copybreak)
2381 skb = receive_copy(sky2, re, length);
2383 skb = receive_new(sky2, re, length);
2385 sky2_rx_submit(sky2, re);
2390 /* Truncation of overlength packets
2391 causes PHY length to not match MAC length */
2392 ++dev->stats.rx_length_errors;
2393 if (netif_msg_rx_err(sky2) && net_ratelimit())
2394 pr_info(PFX "%s: rx length error: status %#x length %d\n",
2395 dev->name, status, length);
2399 ++dev->stats.rx_errors;
2400 if (status & GMR_FS_RX_FF_OV) {
2401 dev->stats.rx_over_errors++;
2405 if (netif_msg_rx_err(sky2) && net_ratelimit())
2406 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2407 dev->name, status, length);
2409 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2410 dev->stats.rx_length_errors++;
2411 if (status & GMR_FS_FRAGMENT)
2412 dev->stats.rx_frame_errors++;
2413 if (status & GMR_FS_CRC_ERR)
2414 dev->stats.rx_crc_errors++;
2419 /* Transmit complete */
2420 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2422 struct sky2_port *sky2 = netdev_priv(dev);
2424 if (netif_running(dev))
2425 sky2_tx_complete(sky2, last);
2428 static inline void sky2_skb_rx(const struct sky2_port *sky2,
2429 u32 status, struct sk_buff *skb)
2431 #ifdef SKY2_VLAN_TAG_USED
2432 u16 vlan_tag = be16_to_cpu(sky2->rx_tag);
2433 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2434 if (skb->ip_summed == CHECKSUM_NONE)
2435 vlan_hwaccel_receive_skb(skb, sky2->vlgrp, vlan_tag);
2437 vlan_gro_receive(&sky2->hw->napi, sky2->vlgrp,
2442 if (skb->ip_summed == CHECKSUM_NONE)
2443 netif_receive_skb(skb);
2445 napi_gro_receive(&sky2->hw->napi, skb);
2448 static inline void sky2_rx_done(struct sky2_hw *hw, unsigned port,
2449 unsigned packets, unsigned bytes)
2452 struct net_device *dev = hw->dev[port];
2454 dev->stats.rx_packets += packets;
2455 dev->stats.rx_bytes += bytes;
2456 dev->last_rx = jiffies;
2457 sky2_rx_update(netdev_priv(dev), rxqaddr[port]);
2461 /* Process status response ring */
2462 static int sky2_status_intr(struct sky2_hw *hw, int to_do, u16 idx)
2465 unsigned int total_bytes[2] = { 0 };
2466 unsigned int total_packets[2] = { 0 };
2470 struct sky2_port *sky2;
2471 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2473 struct net_device *dev;
2474 struct sk_buff *skb;
2477 u8 opcode = le->opcode;
2479 if (!(opcode & HW_OWNER))
2482 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2484 port = le->css & CSS_LINK_BIT;
2485 dev = hw->dev[port];
2486 sky2 = netdev_priv(dev);
2487 length = le16_to_cpu(le->length);
2488 status = le32_to_cpu(le->status);
2491 switch (opcode & ~HW_OWNER) {
2493 total_packets[port]++;
2494 total_bytes[port] += length;
2495 skb = sky2_receive(dev, length, status);
2496 if (unlikely(!skb)) {
2497 dev->stats.rx_dropped++;
2501 /* This chip reports checksum status differently */
2502 if (hw->flags & SKY2_HW_NEW_LE) {
2503 if ((sky2->flags & SKY2_FLAG_RX_CHECKSUM) &&
2504 (le->css & (CSS_ISIPV4 | CSS_ISIPV6)) &&
2505 (le->css & CSS_TCPUDPCSOK))
2506 skb->ip_summed = CHECKSUM_UNNECESSARY;
2508 skb->ip_summed = CHECKSUM_NONE;
2511 skb->protocol = eth_type_trans(skb, dev);
2513 sky2_skb_rx(sky2, status, skb);
2515 /* Stop after net poll weight */
2516 if (++work_done >= to_do)
2520 #ifdef SKY2_VLAN_TAG_USED
2522 sky2->rx_tag = length;
2526 sky2->rx_tag = length;
2530 if (!(sky2->flags & SKY2_FLAG_RX_CHECKSUM))
2533 /* If this happens then driver assuming wrong format */
2534 if (unlikely(hw->flags & SKY2_HW_NEW_LE)) {
2535 if (net_ratelimit())
2536 printk(KERN_NOTICE "%s: unexpected"
2537 " checksum status\n",
2542 /* Both checksum counters are programmed to start at
2543 * the same offset, so unless there is a problem they
2544 * should match. This failure is an early indication that
2545 * hardware receive checksumming won't work.
2547 if (likely(status >> 16 == (status & 0xffff))) {
2548 skb = sky2->rx_ring[sky2->rx_next].skb;
2549 skb->ip_summed = CHECKSUM_COMPLETE;
2550 skb->csum = le16_to_cpu(status);
2552 printk(KERN_NOTICE PFX "%s: hardware receive "
2553 "checksum problem (status = %#x)\n",
2555 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
2557 sky2_write32(sky2->hw,
2558 Q_ADDR(rxqaddr[port], Q_CSR),
2564 /* TX index reports status for both ports */
2565 sky2_tx_done(hw->dev[0], status & 0xfff);
2567 sky2_tx_done(hw->dev[1],
2568 ((status >> 24) & 0xff)
2569 | (u16)(length & 0xf) << 8);
2573 if (net_ratelimit())
2574 printk(KERN_WARNING PFX
2575 "unknown status opcode 0x%x\n", opcode);
2577 } while (hw->st_idx != idx);
2579 /* Fully processed status ring so clear irq */
2580 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2583 sky2_rx_done(hw, 0, total_packets[0], total_bytes[0]);
2584 sky2_rx_done(hw, 1, total_packets[1], total_bytes[1]);
2589 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2591 struct net_device *dev = hw->dev[port];
2593 if (net_ratelimit())
2594 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2597 if (status & Y2_IS_PAR_RD1) {
2598 if (net_ratelimit())
2599 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2602 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2605 if (status & Y2_IS_PAR_WR1) {
2606 if (net_ratelimit())
2607 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2610 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2613 if (status & Y2_IS_PAR_MAC1) {
2614 if (net_ratelimit())
2615 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2616 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2619 if (status & Y2_IS_PAR_RX1) {
2620 if (net_ratelimit())
2621 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2622 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2625 if (status & Y2_IS_TCP_TXA1) {
2626 if (net_ratelimit())
2627 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2629 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2633 static void sky2_hw_intr(struct sky2_hw *hw)
2635 struct pci_dev *pdev = hw->pdev;
2636 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2637 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2641 if (status & Y2_IS_TIST_OV)
2642 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2644 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2647 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2648 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2649 if (net_ratelimit())
2650 dev_err(&pdev->dev, "PCI hardware error (0x%x)\n",
2653 sky2_pci_write16(hw, PCI_STATUS,
2654 pci_err | PCI_STATUS_ERROR_BITS);
2655 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2658 if (status & Y2_IS_PCI_EXP) {
2659 /* PCI-Express uncorrectable Error occurred */
2662 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2663 err = sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2664 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
2666 if (net_ratelimit())
2667 dev_err(&pdev->dev, "PCI Express error (0x%x)\n", err);
2669 sky2_read32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS);
2670 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2673 if (status & Y2_HWE_L1_MASK)
2674 sky2_hw_error(hw, 0, status);
2676 if (status & Y2_HWE_L1_MASK)
2677 sky2_hw_error(hw, 1, status);
2680 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2682 struct net_device *dev = hw->dev[port];
2683 struct sky2_port *sky2 = netdev_priv(dev);
2684 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2686 if (netif_msg_intr(sky2))
2687 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2690 if (status & GM_IS_RX_CO_OV)
2691 gma_read16(hw, port, GM_RX_IRQ_SRC);
2693 if (status & GM_IS_TX_CO_OV)
2694 gma_read16(hw, port, GM_TX_IRQ_SRC);
2696 if (status & GM_IS_RX_FF_OR) {
2697 ++dev->stats.rx_fifo_errors;
2698 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2701 if (status & GM_IS_TX_FF_UR) {
2702 ++dev->stats.tx_fifo_errors;
2703 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2707 /* This should never happen it is a bug. */
2708 static void sky2_le_error(struct sky2_hw *hw, unsigned port, u16 q)
2710 struct net_device *dev = hw->dev[port];
2711 u16 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2713 dev_err(&hw->pdev->dev, PFX
2714 "%s: descriptor error q=%#x get=%u put=%u\n",
2715 dev->name, (unsigned) q, (unsigned) idx,
2716 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2718 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2721 static int sky2_rx_hung(struct net_device *dev)
2723 struct sky2_port *sky2 = netdev_priv(dev);
2724 struct sky2_hw *hw = sky2->hw;
2725 unsigned port = sky2->port;
2726 unsigned rxq = rxqaddr[port];
2727 u32 mac_rp = sky2_read32(hw, SK_REG(port, RX_GMF_RP));
2728 u8 mac_lev = sky2_read8(hw, SK_REG(port, RX_GMF_RLEV));
2729 u8 fifo_rp = sky2_read8(hw, Q_ADDR(rxq, Q_RP));
2730 u8 fifo_lev = sky2_read8(hw, Q_ADDR(rxq, Q_RL));
2732 /* If idle and MAC or PCI is stuck */
2733 if (sky2->check.last == dev->last_rx &&
2734 ((mac_rp == sky2->check.mac_rp &&
2735 mac_lev != 0 && mac_lev >= sky2->check.mac_lev) ||
2736 /* Check if the PCI RX hang */
2737 (fifo_rp == sky2->check.fifo_rp &&
2738 fifo_lev != 0 && fifo_lev >= sky2->check.fifo_lev))) {
2739 printk(KERN_DEBUG PFX "%s: hung mac %d:%d fifo %d (%d:%d)\n",
2740 dev->name, mac_lev, mac_rp, fifo_lev, fifo_rp,
2741 sky2_read8(hw, Q_ADDR(rxq, Q_WP)));
2744 sky2->check.last = dev->last_rx;
2745 sky2->check.mac_rp = mac_rp;
2746 sky2->check.mac_lev = mac_lev;
2747 sky2->check.fifo_rp = fifo_rp;
2748 sky2->check.fifo_lev = fifo_lev;
2753 static void sky2_watchdog(unsigned long arg)
2755 struct sky2_hw *hw = (struct sky2_hw *) arg;
2757 /* Check for lost IRQ once a second */
2758 if (sky2_read32(hw, B0_ISRC)) {
2759 napi_schedule(&hw->napi);
2763 for (i = 0; i < hw->ports; i++) {
2764 struct net_device *dev = hw->dev[i];
2765 if (!netif_running(dev))
2769 /* For chips with Rx FIFO, check if stuck */
2770 if ((hw->flags & SKY2_HW_RAM_BUFFER) &&
2771 sky2_rx_hung(dev)) {
2772 pr_info(PFX "%s: receiver hang detected\n",
2774 schedule_work(&hw->restart_work);
2783 mod_timer(&hw->watchdog_timer, round_jiffies(jiffies + HZ));
2786 /* Hardware/software error handling */
2787 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2789 if (net_ratelimit())
2790 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2792 if (status & Y2_IS_HW_ERR)
2795 if (status & Y2_IS_IRQ_MAC1)
2796 sky2_mac_intr(hw, 0);
2798 if (status & Y2_IS_IRQ_MAC2)
2799 sky2_mac_intr(hw, 1);
2801 if (status & Y2_IS_CHK_RX1)
2802 sky2_le_error(hw, 0, Q_R1);
2804 if (status & Y2_IS_CHK_RX2)
2805 sky2_le_error(hw, 1, Q_R2);
2807 if (status & Y2_IS_CHK_TXA1)
2808 sky2_le_error(hw, 0, Q_XA1);
2810 if (status & Y2_IS_CHK_TXA2)
2811 sky2_le_error(hw, 1, Q_XA2);
2814 static int sky2_poll(struct napi_struct *napi, int work_limit)
2816 struct sky2_hw *hw = container_of(napi, struct sky2_hw, napi);
2817 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2821 if (unlikely(status & Y2_IS_ERROR))
2822 sky2_err_intr(hw, status);
2824 if (status & Y2_IS_IRQ_PHY1)
2825 sky2_phy_intr(hw, 0);
2827 if (status & Y2_IS_IRQ_PHY2)
2828 sky2_phy_intr(hw, 1);
2830 if (status & Y2_IS_PHY_QLNK)
2831 sky2_qlink_intr(hw);
2833 while ((idx = sky2_read16(hw, STAT_PUT_IDX)) != hw->st_idx) {
2834 work_done += sky2_status_intr(hw, work_limit - work_done, idx);
2836 if (work_done >= work_limit)
2840 napi_complete(napi);
2841 sky2_read32(hw, B0_Y2_SP_LISR);
2847 static irqreturn_t sky2_intr(int irq, void *dev_id)
2849 struct sky2_hw *hw = dev_id;
2852 /* Reading this mask interrupts as side effect */
2853 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2854 if (status == 0 || status == ~0)
2857 prefetch(&hw->st_le[hw->st_idx]);
2859 napi_schedule(&hw->napi);
2864 #ifdef CONFIG_NET_POLL_CONTROLLER
2865 static void sky2_netpoll(struct net_device *dev)
2867 struct sky2_port *sky2 = netdev_priv(dev);
2869 napi_schedule(&sky2->hw->napi);
2873 /* Chip internal frequency for clock calculations */
2874 static u32 sky2_mhz(const struct sky2_hw *hw)
2876 switch (hw->chip_id) {
2877 case CHIP_ID_YUKON_EC:
2878 case CHIP_ID_YUKON_EC_U:
2879 case CHIP_ID_YUKON_EX:
2880 case CHIP_ID_YUKON_SUPR:
2881 case CHIP_ID_YUKON_UL_2:
2882 case CHIP_ID_YUKON_OPT:
2885 case CHIP_ID_YUKON_FE:
2888 case CHIP_ID_YUKON_FE_P:
2891 case CHIP_ID_YUKON_XL:
2899 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2901 return sky2_mhz(hw) * us;
2904 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2906 return clk / sky2_mhz(hw);
2910 static int __devinit sky2_init(struct sky2_hw *hw)
2914 /* Enable all clocks and check for bad PCI access */
2915 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2917 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2919 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2920 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2922 switch(hw->chip_id) {
2923 case CHIP_ID_YUKON_XL:
2924 hw->flags = SKY2_HW_GIGABIT | SKY2_HW_NEWER_PHY;
2927 case CHIP_ID_YUKON_EC_U:
2928 hw->flags = SKY2_HW_GIGABIT
2930 | SKY2_HW_ADV_POWER_CTL;
2933 case CHIP_ID_YUKON_EX:
2934 hw->flags = SKY2_HW_GIGABIT
2937 | SKY2_HW_ADV_POWER_CTL;
2939 /* New transmit checksum */
2940 if (hw->chip_rev != CHIP_REV_YU_EX_B0)
2941 hw->flags |= SKY2_HW_AUTO_TX_SUM;
2944 case CHIP_ID_YUKON_EC:
2945 /* This rev is really old, and requires untested workarounds */
2946 if (hw->chip_rev == CHIP_REV_YU_EC_A1) {
2947 dev_err(&hw->pdev->dev, "unsupported revision Yukon-EC rev A1\n");
2950 hw->flags = SKY2_HW_GIGABIT;
2953 case CHIP_ID_YUKON_FE:
2956 case CHIP_ID_YUKON_FE_P:
2957 hw->flags = SKY2_HW_NEWER_PHY
2959 | SKY2_HW_AUTO_TX_SUM
2960 | SKY2_HW_ADV_POWER_CTL;
2963 case CHIP_ID_YUKON_SUPR:
2964 hw->flags = SKY2_HW_GIGABIT
2967 | SKY2_HW_AUTO_TX_SUM
2968 | SKY2_HW_ADV_POWER_CTL;
2971 case CHIP_ID_YUKON_UL_2:
2972 hw->flags = SKY2_HW_GIGABIT
2973 | SKY2_HW_ADV_POWER_CTL;
2976 case CHIP_ID_YUKON_OPT:
2977 hw->flags = SKY2_HW_GIGABIT
2979 | SKY2_HW_ADV_POWER_CTL;
2983 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2988 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2989 if (hw->pmd_type == 'L' || hw->pmd_type == 'S' || hw->pmd_type == 'P')
2990 hw->flags |= SKY2_HW_FIBRE_PHY;
2993 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2994 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2995 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2999 if (sky2_read8(hw, B2_E_0))
3000 hw->flags |= SKY2_HW_RAM_BUFFER;
3005 static void sky2_reset(struct sky2_hw *hw)
3007 struct pci_dev *pdev = hw->pdev;
3010 u32 hwe_mask = Y2_HWE_ALL_MASK;
3013 if (hw->chip_id == CHIP_ID_YUKON_EX) {
3014 status = sky2_read16(hw, HCU_CCSR);
3015 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
3016 HCU_CCSR_UC_STATE_MSK);
3017 sky2_write16(hw, HCU_CCSR, status);
3019 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
3020 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
3023 sky2_write8(hw, B0_CTST, CS_RST_SET);
3024 sky2_write8(hw, B0_CTST, CS_RST_CLR);
3026 /* allow writes to PCI config */
3027 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3029 /* clear PCI errors, if any */
3030 status = sky2_pci_read16(hw, PCI_STATUS);
3031 status |= PCI_STATUS_ERROR_BITS;
3032 sky2_pci_write16(hw, PCI_STATUS, status);
3034 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
3036 cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3038 sky2_write32(hw, Y2_CFG_AER + PCI_ERR_UNCOR_STATUS,
3041 /* If error bit is stuck on ignore it */
3042 if (sky2_read32(hw, B0_HWE_ISRC) & Y2_IS_PCI_EXP)
3043 dev_info(&pdev->dev, "ignoring stuck error report bit\n");
3045 hwe_mask |= Y2_IS_PCI_EXP;
3049 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3051 for (i = 0; i < hw->ports; i++) {
3052 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3053 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3055 if (hw->chip_id == CHIP_ID_YUKON_EX ||
3056 hw->chip_id == CHIP_ID_YUKON_SUPR)
3057 sky2_write16(hw, SK_REG(i, GMAC_CTRL),
3058 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON
3063 if (hw->chip_id == CHIP_ID_YUKON_SUPR && hw->chip_rev > CHIP_REV_YU_SU_B0) {
3064 /* enable MACSec clock gating */
3065 sky2_pci_write32(hw, PCI_DEV_REG3, P_CLK_MACSEC_DIS);
3068 if (hw->chip_id == CHIP_ID_YUKON_OPT) {
3072 if (hw->chip_rev == 0) {
3073 /* disable PCI-E PHY power down (set PHY reg 0x80, bit 7 */
3074 sky2_write32(hw, Y2_PEX_PHY_DATA, (0x80UL << 16) | (1 << 7));
3076 /* set PHY Link Detect Timer to 1.1 second (11x 100ms) */
3079 /* set PHY Link Detect Timer to 0.4 second (4x 100ms) */
3083 reg <<= PSM_CONFIG_REG4_TIMER_PHY_LINK_DETECT_BASE;
3085 /* reset PHY Link Detect */
3086 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3087 sky2_pci_write16(hw, PSM_CONFIG_REG4,
3088 reg | PSM_CONFIG_REG4_RST_PHY_LINK_DETECT);
3089 sky2_pci_write16(hw, PSM_CONFIG_REG4, reg);
3092 /* enable PHY Quick Link */
3093 msk = sky2_read32(hw, B0_IMSK);
3094 msk |= Y2_IS_PHY_QLNK;
3095 sky2_write32(hw, B0_IMSK, msk);
3097 /* check if PSMv2 was running before */
3098 reg = sky2_pci_read16(hw, PSM_CONFIG_REG3);
3099 if (reg & PCI_EXP_LNKCTL_ASPMC) {
3100 int cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3101 /* restore the PCIe Link Control register */
3102 sky2_pci_write16(hw, cap + PCI_EXP_LNKCTL, reg);
3104 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3106 /* re-enable PEX PM in PEX PHY debug reg. 8 (clear bit 12) */
3107 sky2_write32(hw, Y2_PEX_PHY_DATA, PEX_DB_ACCESS | (0x08UL << 16));
3110 /* Clear I2C IRQ noise */
3111 sky2_write32(hw, B2_I2C_IRQ, 1);
3113 /* turn off hardware timer (unused) */
3114 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
3115 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3117 /* Turn off descriptor polling */
3118 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
3120 /* Turn off receive timestamp */
3121 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
3122 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3124 /* enable the Tx Arbiters */
3125 for (i = 0; i < hw->ports; i++)
3126 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3128 /* Initialize ram interface */
3129 for (i = 0; i < hw->ports; i++) {
3130 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
3132 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
3133 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
3134 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
3135 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
3136 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
3137 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
3138 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
3139 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
3140 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
3141 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
3142 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
3143 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
3146 sky2_write32(hw, B0_HWE_IMSK, hwe_mask);
3148 for (i = 0; i < hw->ports; i++)
3149 sky2_gmac_reset(hw, i);
3151 memset(hw->st_le, 0, STATUS_LE_BYTES);
3154 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
3155 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
3157 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
3158 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
3160 /* Set the list last index */
3161 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
3163 sky2_write16(hw, STAT_TX_IDX_TH, 10);
3164 sky2_write8(hw, STAT_FIFO_WM, 16);
3166 /* set Status-FIFO ISR watermark */
3167 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
3168 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
3170 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
3172 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
3173 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
3174 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
3176 /* enable status unit */
3177 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
3179 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3180 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3181 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3184 /* Take device down (offline).
3185 * Equivalent to doing dev_stop() but this does not
3186 * inform upper layers of the transistion.
3188 static void sky2_detach(struct net_device *dev)
3190 if (netif_running(dev)) {
3192 netif_device_detach(dev); /* stop txq */
3193 netif_tx_unlock(dev);
3198 /* Bring device back after doing sky2_detach */
3199 static int sky2_reattach(struct net_device *dev)
3203 if (netif_running(dev)) {
3206 printk(KERN_INFO PFX "%s: could not restart %d\n",
3210 netif_device_attach(dev);
3211 sky2_set_multicast(dev);
3218 static void sky2_restart(struct work_struct *work)
3220 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
3224 for (i = 0; i < hw->ports; i++)
3225 sky2_detach(hw->dev[i]);
3227 napi_disable(&hw->napi);
3228 sky2_write32(hw, B0_IMSK, 0);
3230 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3231 napi_enable(&hw->napi);
3233 for (i = 0; i < hw->ports; i++)
3234 sky2_reattach(hw->dev[i]);
3239 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
3241 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
3244 static void sky2_hw_set_wol(struct sky2_hw *hw)
3249 for (i = 0; i < hw->ports; i++) {
3250 struct net_device *dev = hw->dev[i];
3251 struct sky2_port *sky2 = netdev_priv(dev);
3257 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3258 hw->chip_id == CHIP_ID_YUKON_EX ||
3259 hw->chip_id == CHIP_ID_YUKON_FE_P)
3260 sky2_write32(hw, B0_CTST, wol ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
3262 device_set_wakeup_enable(&hw->pdev->dev, wol);
3265 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3267 const struct sky2_port *sky2 = netdev_priv(dev);
3269 wol->supported = sky2_wol_supported(sky2->hw);
3270 wol->wolopts = sky2->wol;
3273 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
3275 struct sky2_port *sky2 = netdev_priv(dev);
3276 struct sky2_hw *hw = sky2->hw;
3278 if ((wol->wolopts & ~sky2_wol_supported(sky2->hw)) ||
3279 !device_can_wakeup(&hw->pdev->dev))
3282 sky2->wol = wol->wolopts;
3284 sky2_hw_set_wol(hw);
3286 if (!netif_running(dev))
3287 sky2_wol_init(sky2);
3291 static u32 sky2_supported_modes(const struct sky2_hw *hw)
3293 if (sky2_is_copper(hw)) {
3294 u32 modes = SUPPORTED_10baseT_Half
3295 | SUPPORTED_10baseT_Full
3296 | SUPPORTED_100baseT_Half
3297 | SUPPORTED_100baseT_Full
3298 | SUPPORTED_Autoneg | SUPPORTED_TP;
3300 if (hw->flags & SKY2_HW_GIGABIT)
3301 modes |= SUPPORTED_1000baseT_Half
3302 | SUPPORTED_1000baseT_Full;
3305 return SUPPORTED_1000baseT_Half
3306 | SUPPORTED_1000baseT_Full
3311 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3313 struct sky2_port *sky2 = netdev_priv(dev);
3314 struct sky2_hw *hw = sky2->hw;
3316 ecmd->transceiver = XCVR_INTERNAL;
3317 ecmd->supported = sky2_supported_modes(hw);
3318 ecmd->phy_address = PHY_ADDR_MARV;
3319 if (sky2_is_copper(hw)) {
3320 ecmd->port = PORT_TP;
3321 ecmd->speed = sky2->speed;
3323 ecmd->speed = SPEED_1000;
3324 ecmd->port = PORT_FIBRE;
3327 ecmd->advertising = sky2->advertising;
3328 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_SPEED)
3329 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3330 ecmd->duplex = sky2->duplex;
3334 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
3336 struct sky2_port *sky2 = netdev_priv(dev);
3337 const struct sky2_hw *hw = sky2->hw;
3338 u32 supported = sky2_supported_modes(hw);
3340 if (ecmd->autoneg == AUTONEG_ENABLE) {
3341 sky2->flags |= SKY2_FLAG_AUTO_SPEED;
3342 ecmd->advertising = supported;
3348 switch (ecmd->speed) {
3350 if (ecmd->duplex == DUPLEX_FULL)
3351 setting = SUPPORTED_1000baseT_Full;
3352 else if (ecmd->duplex == DUPLEX_HALF)
3353 setting = SUPPORTED_1000baseT_Half;
3358 if (ecmd->duplex == DUPLEX_FULL)
3359 setting = SUPPORTED_100baseT_Full;
3360 else if (ecmd->duplex == DUPLEX_HALF)
3361 setting = SUPPORTED_100baseT_Half;
3367 if (ecmd->duplex == DUPLEX_FULL)
3368 setting = SUPPORTED_10baseT_Full;
3369 else if (ecmd->duplex == DUPLEX_HALF)
3370 setting = SUPPORTED_10baseT_Half;
3378 if ((setting & supported) == 0)
3381 sky2->speed = ecmd->speed;
3382 sky2->duplex = ecmd->duplex;
3383 sky2->flags &= ~SKY2_FLAG_AUTO_SPEED;
3386 sky2->advertising = ecmd->advertising;
3388 if (netif_running(dev)) {
3389 sky2_phy_reinit(sky2);
3390 sky2_set_multicast(dev);
3396 static void sky2_get_drvinfo(struct net_device *dev,
3397 struct ethtool_drvinfo *info)
3399 struct sky2_port *sky2 = netdev_priv(dev);
3401 strcpy(info->driver, DRV_NAME);
3402 strcpy(info->version, DRV_VERSION);
3403 strcpy(info->fw_version, "N/A");
3404 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
3407 static const struct sky2_stat {
3408 char name[ETH_GSTRING_LEN];
3411 { "tx_bytes", GM_TXO_OK_HI },
3412 { "rx_bytes", GM_RXO_OK_HI },
3413 { "tx_broadcast", GM_TXF_BC_OK },
3414 { "rx_broadcast", GM_RXF_BC_OK },
3415 { "tx_multicast", GM_TXF_MC_OK },
3416 { "rx_multicast", GM_RXF_MC_OK },
3417 { "tx_unicast", GM_TXF_UC_OK },
3418 { "rx_unicast", GM_RXF_UC_OK },
3419 { "tx_mac_pause", GM_TXF_MPAUSE },
3420 { "rx_mac_pause", GM_RXF_MPAUSE },
3421 { "collisions", GM_TXF_COL },
3422 { "late_collision",GM_TXF_LAT_COL },
3423 { "aborted", GM_TXF_ABO_COL },
3424 { "single_collisions", GM_TXF_SNG_COL },
3425 { "multi_collisions", GM_TXF_MUL_COL },
3427 { "rx_short", GM_RXF_SHT },
3428 { "rx_runt", GM_RXE_FRAG },
3429 { "rx_64_byte_packets", GM_RXF_64B },
3430 { "rx_65_to_127_byte_packets", GM_RXF_127B },
3431 { "rx_128_to_255_byte_packets", GM_RXF_255B },
3432 { "rx_256_to_511_byte_packets", GM_RXF_511B },
3433 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
3434 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
3435 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
3436 { "rx_too_long", GM_RXF_LNG_ERR },
3437 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
3438 { "rx_jabber", GM_RXF_JAB_PKT },
3439 { "rx_fcs_error", GM_RXF_FCS_ERR },
3441 { "tx_64_byte_packets", GM_TXF_64B },
3442 { "tx_65_to_127_byte_packets", GM_TXF_127B },
3443 { "tx_128_to_255_byte_packets", GM_TXF_255B },
3444 { "tx_256_to_511_byte_packets", GM_TXF_511B },
3445 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
3446 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
3447 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
3448 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
3451 static u32 sky2_get_rx_csum(struct net_device *dev)
3453 struct sky2_port *sky2 = netdev_priv(dev);
3455 return !!(sky2->flags & SKY2_FLAG_RX_CHECKSUM);
3458 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
3460 struct sky2_port *sky2 = netdev_priv(dev);
3463 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
3465 sky2->flags &= ~SKY2_FLAG_RX_CHECKSUM;
3467 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
3468 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
3473 static u32 sky2_get_msglevel(struct net_device *netdev)
3475 struct sky2_port *sky2 = netdev_priv(netdev);
3476 return sky2->msg_enable;
3479 static int sky2_nway_reset(struct net_device *dev)
3481 struct sky2_port *sky2 = netdev_priv(dev);
3483 if (!netif_running(dev) || !(sky2->flags & SKY2_FLAG_AUTO_SPEED))
3486 sky2_phy_reinit(sky2);
3487 sky2_set_multicast(dev);
3492 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
3494 struct sky2_hw *hw = sky2->hw;
3495 unsigned port = sky2->port;
3498 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
3499 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
3500 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
3501 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
3503 for (i = 2; i < count; i++)
3504 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
3507 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
3509 struct sky2_port *sky2 = netdev_priv(netdev);
3510 sky2->msg_enable = value;
3513 static int sky2_get_sset_count(struct net_device *dev, int sset)
3517 return ARRAY_SIZE(sky2_stats);
3523 static void sky2_get_ethtool_stats(struct net_device *dev,
3524 struct ethtool_stats *stats, u64 * data)
3526 struct sky2_port *sky2 = netdev_priv(dev);
3528 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
3531 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
3535 switch (stringset) {
3537 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
3538 memcpy(data + i * ETH_GSTRING_LEN,
3539 sky2_stats[i].name, ETH_GSTRING_LEN);
3544 static int sky2_set_mac_address(struct net_device *dev, void *p)
3546 struct sky2_port *sky2 = netdev_priv(dev);
3547 struct sky2_hw *hw = sky2->hw;
3548 unsigned port = sky2->port;
3549 const struct sockaddr *addr = p;
3551 if (!is_valid_ether_addr(addr->sa_data))
3552 return -EADDRNOTAVAIL;
3554 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3555 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3556 dev->dev_addr, ETH_ALEN);
3557 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3558 dev->dev_addr, ETH_ALEN);
3560 /* virtual address for data */
3561 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3563 /* physical address: used for pause frames */
3564 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3569 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3573 bit = ether_crc(ETH_ALEN, addr) & 63;
3574 filter[bit >> 3] |= 1 << (bit & 7);
3577 static void sky2_set_multicast(struct net_device *dev)
3579 struct sky2_port *sky2 = netdev_priv(dev);
3580 struct sky2_hw *hw = sky2->hw;
3581 unsigned port = sky2->port;
3582 struct dev_mc_list *list = dev->mc_list;
3586 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3588 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3589 memset(filter, 0, sizeof(filter));
3591 reg = gma_read16(hw, port, GM_RX_CTRL);
3592 reg |= GM_RXCR_UCF_ENA;
3594 if (dev->flags & IFF_PROMISC) /* promiscuous */
3595 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3596 else if (dev->flags & IFF_ALLMULTI)
3597 memset(filter, 0xff, sizeof(filter));
3598 else if (dev->mc_count == 0 && !rx_pause)
3599 reg &= ~GM_RXCR_MCF_ENA;
3602 reg |= GM_RXCR_MCF_ENA;
3605 sky2_add_filter(filter, pause_mc_addr);
3607 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3608 sky2_add_filter(filter, list->dmi_addr);
3611 gma_write16(hw, port, GM_MC_ADDR_H1,
3612 (u16) filter[0] | ((u16) filter[1] << 8));
3613 gma_write16(hw, port, GM_MC_ADDR_H2,
3614 (u16) filter[2] | ((u16) filter[3] << 8));
3615 gma_write16(hw, port, GM_MC_ADDR_H3,
3616 (u16) filter[4] | ((u16) filter[5] << 8));
3617 gma_write16(hw, port, GM_MC_ADDR_H4,
3618 (u16) filter[6] | ((u16) filter[7] << 8));
3620 gma_write16(hw, port, GM_RX_CTRL, reg);
3623 /* Can have one global because blinking is controlled by
3624 * ethtool and that is always under RTNL mutex
3626 static void sky2_led(struct sky2_port *sky2, enum led_mode mode)
3628 struct sky2_hw *hw = sky2->hw;
3629 unsigned port = sky2->port;
3631 spin_lock_bh(&sky2->phy_lock);
3632 if (hw->chip_id == CHIP_ID_YUKON_EC_U ||
3633 hw->chip_id == CHIP_ID_YUKON_EX ||
3634 hw->chip_id == CHIP_ID_YUKON_SUPR) {
3636 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3637 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3641 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3642 PHY_M_LEDC_LOS_CTRL(8) |
3643 PHY_M_LEDC_INIT_CTRL(8) |
3644 PHY_M_LEDC_STA1_CTRL(8) |
3645 PHY_M_LEDC_STA0_CTRL(8));
3648 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3649 PHY_M_LEDC_LOS_CTRL(9) |
3650 PHY_M_LEDC_INIT_CTRL(9) |
3651 PHY_M_LEDC_STA1_CTRL(9) |
3652 PHY_M_LEDC_STA0_CTRL(9));
3655 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3656 PHY_M_LEDC_LOS_CTRL(0xa) |
3657 PHY_M_LEDC_INIT_CTRL(0xa) |
3658 PHY_M_LEDC_STA1_CTRL(0xa) |
3659 PHY_M_LEDC_STA0_CTRL(0xa));
3662 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3663 PHY_M_LEDC_LOS_CTRL(1) |
3664 PHY_M_LEDC_INIT_CTRL(8) |
3665 PHY_M_LEDC_STA1_CTRL(7) |
3666 PHY_M_LEDC_STA0_CTRL(7));
3669 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3671 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3672 PHY_M_LED_MO_DUP(mode) |
3673 PHY_M_LED_MO_10(mode) |
3674 PHY_M_LED_MO_100(mode) |
3675 PHY_M_LED_MO_1000(mode) |
3676 PHY_M_LED_MO_RX(mode) |
3677 PHY_M_LED_MO_TX(mode));
3679 spin_unlock_bh(&sky2->phy_lock);
3682 /* blink LED's for finding board */
3683 static int sky2_phys_id(struct net_device *dev, u32 data)
3685 struct sky2_port *sky2 = netdev_priv(dev);
3691 for (i = 0; i < data; i++) {
3692 sky2_led(sky2, MO_LED_ON);
3693 if (msleep_interruptible(500))
3695 sky2_led(sky2, MO_LED_OFF);
3696 if (msleep_interruptible(500))
3699 sky2_led(sky2, MO_LED_NORM);
3704 static void sky2_get_pauseparam(struct net_device *dev,
3705 struct ethtool_pauseparam *ecmd)
3707 struct sky2_port *sky2 = netdev_priv(dev);
3709 switch (sky2->flow_mode) {
3711 ecmd->tx_pause = ecmd->rx_pause = 0;
3714 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3717 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3720 ecmd->tx_pause = ecmd->rx_pause = 1;
3723 ecmd->autoneg = (sky2->flags & SKY2_FLAG_AUTO_PAUSE)
3724 ? AUTONEG_ENABLE : AUTONEG_DISABLE;
3727 static int sky2_set_pauseparam(struct net_device *dev,
3728 struct ethtool_pauseparam *ecmd)
3730 struct sky2_port *sky2 = netdev_priv(dev);
3732 if (ecmd->autoneg == AUTONEG_ENABLE)
3733 sky2->flags |= SKY2_FLAG_AUTO_PAUSE;
3735 sky2->flags &= ~SKY2_FLAG_AUTO_PAUSE;
3737 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3739 if (netif_running(dev))
3740 sky2_phy_reinit(sky2);
3745 static int sky2_get_coalesce(struct net_device *dev,
3746 struct ethtool_coalesce *ecmd)
3748 struct sky2_port *sky2 = netdev_priv(dev);
3749 struct sky2_hw *hw = sky2->hw;
3751 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3752 ecmd->tx_coalesce_usecs = 0;
3754 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3755 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3757 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3759 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3760 ecmd->rx_coalesce_usecs = 0;
3762 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3763 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3765 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3767 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3768 ecmd->rx_coalesce_usecs_irq = 0;
3770 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3771 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3774 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3779 /* Note: this affect both ports */
3780 static int sky2_set_coalesce(struct net_device *dev,
3781 struct ethtool_coalesce *ecmd)
3783 struct sky2_port *sky2 = netdev_priv(dev);
3784 struct sky2_hw *hw = sky2->hw;
3785 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3787 if (ecmd->tx_coalesce_usecs > tmax ||
3788 ecmd->rx_coalesce_usecs > tmax ||
3789 ecmd->rx_coalesce_usecs_irq > tmax)
3792 if (ecmd->tx_max_coalesced_frames >= sky2->tx_ring_size-1)
3794 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3796 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3799 if (ecmd->tx_coalesce_usecs == 0)
3800 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3802 sky2_write32(hw, STAT_TX_TIMER_INI,
3803 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3804 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3806 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3808 if (ecmd->rx_coalesce_usecs == 0)
3809 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3811 sky2_write32(hw, STAT_LEV_TIMER_INI,
3812 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3813 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3815 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3817 if (ecmd->rx_coalesce_usecs_irq == 0)
3818 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3820 sky2_write32(hw, STAT_ISR_TIMER_INI,
3821 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3822 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3824 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3828 static void sky2_get_ringparam(struct net_device *dev,
3829 struct ethtool_ringparam *ering)
3831 struct sky2_port *sky2 = netdev_priv(dev);
3833 ering->rx_max_pending = RX_MAX_PENDING;
3834 ering->rx_mini_max_pending = 0;
3835 ering->rx_jumbo_max_pending = 0;
3836 ering->tx_max_pending = TX_MAX_PENDING;
3838 ering->rx_pending = sky2->rx_pending;
3839 ering->rx_mini_pending = 0;
3840 ering->rx_jumbo_pending = 0;
3841 ering->tx_pending = sky2->tx_pending;
3844 static int sky2_set_ringparam(struct net_device *dev,
3845 struct ethtool_ringparam *ering)
3847 struct sky2_port *sky2 = netdev_priv(dev);
3849 if (ering->rx_pending > RX_MAX_PENDING ||
3850 ering->rx_pending < 8 ||
3851 ering->tx_pending < TX_MIN_PENDING ||
3852 ering->tx_pending > TX_MAX_PENDING)
3857 sky2->rx_pending = ering->rx_pending;
3858 sky2->tx_pending = ering->tx_pending;
3859 sky2->tx_ring_size = roundup_pow_of_two(sky2->tx_pending+1);
3861 return sky2_reattach(dev);
3864 static int sky2_get_regs_len(struct net_device *dev)
3869 static int sky2_reg_access_ok(struct sky2_hw *hw, unsigned int b)
3871 /* This complicated switch statement is to make sure and
3872 * only access regions that are unreserved.
3873 * Some blocks are only valid on dual port cards.
3877 case 5: /* Tx Arbiter 2 */
3879 case 14 ... 15: /* TX2 */
3880 case 17: case 19: /* Ram Buffer 2 */
3881 case 22 ... 23: /* Tx Ram Buffer 2 */
3882 case 25: /* Rx MAC Fifo 1 */
3883 case 27: /* Tx MAC Fifo 2 */
3884 case 31: /* GPHY 2 */
3885 case 40 ... 47: /* Pattern Ram 2 */
3886 case 52: case 54: /* TCP Segmentation 2 */
3887 case 112 ... 116: /* GMAC 2 */
3888 return hw->ports > 1;
3890 case 0: /* Control */
3891 case 2: /* Mac address */
3892 case 4: /* Tx Arbiter 1 */
3893 case 7: /* PCI express reg */
3895 case 12 ... 13: /* TX1 */
3896 case 16: case 18:/* Rx Ram Buffer 1 */
3897 case 20 ... 21: /* Tx Ram Buffer 1 */
3898 case 24: /* Rx MAC Fifo 1 */
3899 case 26: /* Tx MAC Fifo 1 */
3900 case 28 ... 29: /* Descriptor and status unit */
3901 case 30: /* GPHY 1*/
3902 case 32 ... 39: /* Pattern Ram 1 */
3903 case 48: case 50: /* TCP Segmentation 1 */
3904 case 56 ... 60: /* PCI space */
3905 case 80 ... 84: /* GMAC 1 */
3914 * Returns copy of control register region
3915 * Note: ethtool_get_regs always provides full size (16k) buffer
3917 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3920 const struct sky2_port *sky2 = netdev_priv(dev);
3921 const void __iomem *io = sky2->hw->regs;
3926 for (b = 0; b < 128; b++) {
3927 /* skip poisonous diagnostic ram region in block 3 */
3929 memcpy_fromio(p + 0x10, io + 0x10, 128 - 0x10);
3930 else if (sky2_reg_access_ok(sky2->hw, b))
3931 memcpy_fromio(p, io, 128);
3940 /* In order to do Jumbo packets on these chips, need to turn off the
3941 * transmit store/forward. Therefore checksum offload won't work.
3943 static int no_tx_offload(struct net_device *dev)
3945 const struct sky2_port *sky2 = netdev_priv(dev);
3946 const struct sky2_hw *hw = sky2->hw;
3948 return dev->mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_EC_U;
3951 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3953 if (data && no_tx_offload(dev))
3956 return ethtool_op_set_tx_csum(dev, data);
3960 static int sky2_set_tso(struct net_device *dev, u32 data)
3962 if (data && no_tx_offload(dev))
3965 return ethtool_op_set_tso(dev, data);
3968 static int sky2_get_eeprom_len(struct net_device *dev)
3970 struct sky2_port *sky2 = netdev_priv(dev);
3971 struct sky2_hw *hw = sky2->hw;
3974 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
3975 return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
3978 static int sky2_vpd_wait(const struct sky2_hw *hw, int cap, u16 busy)
3980 unsigned long start = jiffies;
3982 while ( (sky2_pci_read16(hw, cap + PCI_VPD_ADDR) & PCI_VPD_ADDR_F) == busy) {
3983 /* Can take up to 10.6 ms for write */
3984 if (time_after(jiffies, start + HZ/4)) {
3985 dev_err(&hw->pdev->dev, PFX "VPD cycle timed out");
3994 static int sky2_vpd_read(struct sky2_hw *hw, int cap, void *data,
3995 u16 offset, size_t length)
3999 while (length > 0) {
4002 sky2_pci_write16(hw, cap + PCI_VPD_ADDR, offset);
4003 rc = sky2_vpd_wait(hw, cap, 0);
4007 val = sky2_pci_read32(hw, cap + PCI_VPD_DATA);
4009 memcpy(data, &val, min(sizeof(val), length));
4010 offset += sizeof(u32);
4011 data += sizeof(u32);
4012 length -= sizeof(u32);
4018 static int sky2_vpd_write(struct sky2_hw *hw, int cap, const void *data,
4019 u16 offset, unsigned int length)
4024 for (i = 0; i < length; i += sizeof(u32)) {
4025 u32 val = *(u32 *)(data + i);
4027 sky2_pci_write32(hw, cap + PCI_VPD_DATA, val);
4028 sky2_pci_write32(hw, cap + PCI_VPD_ADDR, offset | PCI_VPD_ADDR_F);
4030 rc = sky2_vpd_wait(hw, cap, PCI_VPD_ADDR_F);
4037 static int sky2_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4040 struct sky2_port *sky2 = netdev_priv(dev);
4041 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4046 eeprom->magic = SKY2_EEPROM_MAGIC;
4048 return sky2_vpd_read(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4051 static int sky2_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
4054 struct sky2_port *sky2 = netdev_priv(dev);
4055 int cap = pci_find_capability(sky2->hw->pdev, PCI_CAP_ID_VPD);
4060 if (eeprom->magic != SKY2_EEPROM_MAGIC)
4063 /* Partial writes not supported */
4064 if ((eeprom->offset & 3) || (eeprom->len & 3))
4067 return sky2_vpd_write(sky2->hw, cap, data, eeprom->offset, eeprom->len);
4071 static const struct ethtool_ops sky2_ethtool_ops = {
4072 .get_settings = sky2_get_settings,
4073 .set_settings = sky2_set_settings,
4074 .get_drvinfo = sky2_get_drvinfo,
4075 .get_wol = sky2_get_wol,
4076 .set_wol = sky2_set_wol,
4077 .get_msglevel = sky2_get_msglevel,
4078 .set_msglevel = sky2_set_msglevel,
4079 .nway_reset = sky2_nway_reset,
4080 .get_regs_len = sky2_get_regs_len,
4081 .get_regs = sky2_get_regs,
4082 .get_link = ethtool_op_get_link,
4083 .get_eeprom_len = sky2_get_eeprom_len,
4084 .get_eeprom = sky2_get_eeprom,
4085 .set_eeprom = sky2_set_eeprom,
4086 .set_sg = ethtool_op_set_sg,
4087 .set_tx_csum = sky2_set_tx_csum,
4088 .set_tso = sky2_set_tso,
4089 .get_rx_csum = sky2_get_rx_csum,
4090 .set_rx_csum = sky2_set_rx_csum,
4091 .get_strings = sky2_get_strings,
4092 .get_coalesce = sky2_get_coalesce,
4093 .set_coalesce = sky2_set_coalesce,
4094 .get_ringparam = sky2_get_ringparam,
4095 .set_ringparam = sky2_set_ringparam,
4096 .get_pauseparam = sky2_get_pauseparam,
4097 .set_pauseparam = sky2_set_pauseparam,
4098 .phys_id = sky2_phys_id,
4099 .get_sset_count = sky2_get_sset_count,
4100 .get_ethtool_stats = sky2_get_ethtool_stats,
4103 #ifdef CONFIG_SKY2_DEBUG
4105 static struct dentry *sky2_debug;
4109 * Read and parse the first part of Vital Product Data
4111 #define VPD_SIZE 128
4112 #define VPD_MAGIC 0x82
4114 static const struct vpd_tag {
4118 { "PN", "Part Number" },
4119 { "EC", "Engineering Level" },
4120 { "MN", "Manufacturer" },
4121 { "SN", "Serial Number" },
4122 { "YA", "Asset Tag" },
4123 { "VL", "First Error Log Message" },
4124 { "VF", "Second Error Log Message" },
4125 { "VB", "Boot Agent ROM Configuration" },
4126 { "VE", "EFI UNDI Configuration" },
4129 static void sky2_show_vpd(struct seq_file *seq, struct sky2_hw *hw)
4137 reg2 = sky2_pci_read16(hw, PCI_DEV_REG2);
4138 vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
4140 seq_printf(seq, "%s Product Data\n", pci_name(hw->pdev));
4141 buf = kmalloc(vpd_size, GFP_KERNEL);
4143 seq_puts(seq, "no memory!\n");
4147 if (pci_read_vpd(hw->pdev, 0, vpd_size, buf) < 0) {
4148 seq_puts(seq, "VPD read failed\n");
4152 if (buf[0] != VPD_MAGIC) {
4153 seq_printf(seq, "VPD tag mismatch: %#x\n", buf[0]);
4157 if (len == 0 || len > vpd_size - 4) {
4158 seq_printf(seq, "Invalid id length: %d\n", len);
4162 seq_printf(seq, "%.*s\n", len, buf + 3);
4165 while (offs < vpd_size - 4) {
4168 if (!memcmp("RW", buf + offs, 2)) /* end marker */
4170 len = buf[offs + 2];
4171 if (offs + len + 3 >= vpd_size)
4174 for (i = 0; i < ARRAY_SIZE(vpd_tags); i++) {
4175 if (!memcmp(vpd_tags[i].tag, buf + offs, 2)) {
4176 seq_printf(seq, " %s: %.*s\n",
4177 vpd_tags[i].label, len, buf + offs + 3);
4187 static int sky2_debug_show(struct seq_file *seq, void *v)
4189 struct net_device *dev = seq->private;
4190 const struct sky2_port *sky2 = netdev_priv(dev);
4191 struct sky2_hw *hw = sky2->hw;
4192 unsigned port = sky2->port;
4196 sky2_show_vpd(seq, hw);
4198 seq_printf(seq, "\nIRQ src=%x mask=%x control=%x\n",
4199 sky2_read32(hw, B0_ISRC),
4200 sky2_read32(hw, B0_IMSK),
4201 sky2_read32(hw, B0_Y2_SP_ICR));
4203 if (!netif_running(dev)) {
4204 seq_printf(seq, "network not running\n");
4208 napi_disable(&hw->napi);
4209 last = sky2_read16(hw, STAT_PUT_IDX);
4211 if (hw->st_idx == last)
4212 seq_puts(seq, "Status ring (empty)\n");
4214 seq_puts(seq, "Status ring\n");
4215 for (idx = hw->st_idx; idx != last && idx < STATUS_RING_SIZE;
4216 idx = RING_NEXT(idx, STATUS_RING_SIZE)) {
4217 const struct sky2_status_le *le = hw->st_le + idx;
4218 seq_printf(seq, "[%d] %#x %d %#x\n",
4219 idx, le->opcode, le->length, le->status);
4221 seq_puts(seq, "\n");
4224 seq_printf(seq, "Tx ring pending=%u...%u report=%d done=%d\n",
4225 sky2->tx_cons, sky2->tx_prod,
4226 sky2_read16(hw, port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
4227 sky2_read16(hw, Q_ADDR(txqaddr[port], Q_DONE)));
4229 /* Dump contents of tx ring */
4231 for (idx = sky2->tx_next; idx != sky2->tx_prod && idx < sky2->tx_ring_size;
4232 idx = RING_NEXT(idx, sky2->tx_ring_size)) {
4233 const struct sky2_tx_le *le = sky2->tx_le + idx;
4234 u32 a = le32_to_cpu(le->addr);
4237 seq_printf(seq, "%u:", idx);
4240 switch(le->opcode & ~HW_OWNER) {
4242 seq_printf(seq, " %#x:", a);
4245 seq_printf(seq, " mtu=%d", a);
4248 seq_printf(seq, " vlan=%d", be16_to_cpu(le->length));
4251 seq_printf(seq, " csum=%#x", a);
4254 seq_printf(seq, " tso=%#x(%d)", a, le16_to_cpu(le->length));
4257 seq_printf(seq, " %#x(%d)", a, le16_to_cpu(le->length));
4260 seq_printf(seq, " frag=%#x(%d)", a, le16_to_cpu(le->length));
4263 seq_printf(seq, " op=%#x,%#x(%d)", le->opcode,
4264 a, le16_to_cpu(le->length));
4267 if (le->ctrl & EOP) {
4268 seq_putc(seq, '\n');
4273 seq_printf(seq, "\nRx ring hw get=%d put=%d last=%d\n",
4274 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_GET_IDX)),
4275 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_PUT_IDX)),
4276 sky2_read16(hw, Y2_QADDR(rxqaddr[port], PREF_UNIT_LAST_IDX)));
4278 sky2_read32(hw, B0_Y2_SP_LISR);
4279 napi_enable(&hw->napi);
4283 static int sky2_debug_open(struct inode *inode, struct file *file)
4285 return single_open(file, sky2_debug_show, inode->i_private);
4288 static const struct file_operations sky2_debug_fops = {
4289 .owner = THIS_MODULE,
4290 .open = sky2_debug_open,
4292 .llseek = seq_lseek,
4293 .release = single_release,
4297 * Use network device events to create/remove/rename
4298 * debugfs file entries
4300 static int sky2_device_event(struct notifier_block *unused,
4301 unsigned long event, void *ptr)
4303 struct net_device *dev = ptr;
4304 struct sky2_port *sky2 = netdev_priv(dev);
4306 if (dev->netdev_ops->ndo_open != sky2_up || !sky2_debug)
4310 case NETDEV_CHANGENAME:
4311 if (sky2->debugfs) {
4312 sky2->debugfs = debugfs_rename(sky2_debug, sky2->debugfs,
4313 sky2_debug, dev->name);
4317 case NETDEV_GOING_DOWN:
4318 if (sky2->debugfs) {
4319 printk(KERN_DEBUG PFX "%s: remove debugfs\n",
4321 debugfs_remove(sky2->debugfs);
4322 sky2->debugfs = NULL;
4327 sky2->debugfs = debugfs_create_file(dev->name, S_IRUGO,
4330 if (IS_ERR(sky2->debugfs))
4331 sky2->debugfs = NULL;
4337 static struct notifier_block sky2_notifier = {
4338 .notifier_call = sky2_device_event,
4342 static __init void sky2_debug_init(void)
4346 ent = debugfs_create_dir("sky2", NULL);
4347 if (!ent || IS_ERR(ent))
4351 register_netdevice_notifier(&sky2_notifier);
4354 static __exit void sky2_debug_cleanup(void)
4357 unregister_netdevice_notifier(&sky2_notifier);
4358 debugfs_remove(sky2_debug);
4364 #define sky2_debug_init()
4365 #define sky2_debug_cleanup()
4368 /* Two copies of network device operations to handle special case of
4369 not allowing netpoll on second port */
4370 static const struct net_device_ops sky2_netdev_ops[2] = {
4372 .ndo_open = sky2_up,
4373 .ndo_stop = sky2_down,
4374 .ndo_start_xmit = sky2_xmit_frame,
4375 .ndo_do_ioctl = sky2_ioctl,
4376 .ndo_validate_addr = eth_validate_addr,
4377 .ndo_set_mac_address = sky2_set_mac_address,
4378 .ndo_set_multicast_list = sky2_set_multicast,
4379 .ndo_change_mtu = sky2_change_mtu,
4380 .ndo_tx_timeout = sky2_tx_timeout,
4381 #ifdef SKY2_VLAN_TAG_USED
4382 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4384 #ifdef CONFIG_NET_POLL_CONTROLLER
4385 .ndo_poll_controller = sky2_netpoll,
4389 .ndo_open = sky2_up,
4390 .ndo_stop = sky2_down,
4391 .ndo_start_xmit = sky2_xmit_frame,
4392 .ndo_do_ioctl = sky2_ioctl,
4393 .ndo_validate_addr = eth_validate_addr,
4394 .ndo_set_mac_address = sky2_set_mac_address,
4395 .ndo_set_multicast_list = sky2_set_multicast,
4396 .ndo_change_mtu = sky2_change_mtu,
4397 .ndo_tx_timeout = sky2_tx_timeout,
4398 #ifdef SKY2_VLAN_TAG_USED
4399 .ndo_vlan_rx_register = sky2_vlan_rx_register,
4404 /* Initialize network device */
4405 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
4407 int highmem, int wol)
4409 struct sky2_port *sky2;
4410 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
4413 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
4417 SET_NETDEV_DEV(dev, &hw->pdev->dev);
4418 dev->irq = hw->pdev->irq;
4419 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
4420 dev->watchdog_timeo = TX_WATCHDOG;
4421 dev->netdev_ops = &sky2_netdev_ops[port];
4423 sky2 = netdev_priv(dev);
4426 sky2->msg_enable = netif_msg_init(debug, default_msg);
4428 /* Auto speed and flow control */
4429 sky2->flags = SKY2_FLAG_AUTO_SPEED | SKY2_FLAG_AUTO_PAUSE;
4430 if (hw->chip_id != CHIP_ID_YUKON_XL)
4431 sky2->flags |= SKY2_FLAG_RX_CHECKSUM;
4433 sky2->flow_mode = FC_BOTH;
4437 sky2->advertising = sky2_supported_modes(hw);
4440 spin_lock_init(&sky2->phy_lock);
4442 sky2->tx_pending = TX_DEF_PENDING;
4443 sky2->tx_ring_size = roundup_pow_of_two(TX_DEF_PENDING+1);
4444 sky2->rx_pending = RX_DEF_PENDING;
4446 hw->dev[port] = dev;
4450 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
4452 dev->features |= NETIF_F_HIGHDMA;
4454 #ifdef SKY2_VLAN_TAG_USED
4455 /* The workaround for FE+ status conflicts with VLAN tag detection. */
4456 if (!(sky2->hw->chip_id == CHIP_ID_YUKON_FE_P &&
4457 sky2->hw->chip_rev == CHIP_REV_YU_FE2_A0)) {
4458 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
4462 /* read the mac address */
4463 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
4464 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
4469 static void __devinit sky2_show_addr(struct net_device *dev)
4471 const struct sky2_port *sky2 = netdev_priv(dev);
4473 if (netif_msg_probe(sky2))
4474 printk(KERN_INFO PFX "%s: addr %pM\n",
4475 dev->name, dev->dev_addr);
4478 /* Handle software interrupt used during MSI test */
4479 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
4481 struct sky2_hw *hw = dev_id;
4482 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
4487 if (status & Y2_IS_IRQ_SW) {
4488 hw->flags |= SKY2_HW_USE_MSI;
4489 wake_up(&hw->msi_wait);
4490 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4492 sky2_write32(hw, B0_Y2_SP_ICR, 2);
4497 /* Test interrupt path by forcing a a software IRQ */
4498 static int __devinit sky2_test_msi(struct sky2_hw *hw)
4500 struct pci_dev *pdev = hw->pdev;
4503 init_waitqueue_head (&hw->msi_wait);
4505 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
4507 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
4509 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4513 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
4514 sky2_read8(hw, B0_CTST);
4516 wait_event_timeout(hw->msi_wait, (hw->flags & SKY2_HW_USE_MSI), HZ/10);
4518 if (!(hw->flags & SKY2_HW_USE_MSI)) {
4519 /* MSI test failed, go back to INTx mode */
4520 dev_info(&pdev->dev, "No interrupt generated using MSI, "
4521 "switching to INTx mode.\n");
4524 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
4527 sky2_write32(hw, B0_IMSK, 0);
4528 sky2_read32(hw, B0_IMSK);
4530 free_irq(pdev->irq, hw);
4535 /* This driver supports yukon2 chipset only */
4536 static const char *sky2_name(u8 chipid, char *buf, int sz)
4538 const char *name[] = {
4540 "EC Ultra", /* 0xb4 */
4541 "Extreme", /* 0xb5 */
4545 "Supreme", /* 0xb9 */
4547 "Unknown", /* 0xbb */
4548 "Optima", /* 0xbc */
4551 if (chipid >= CHIP_ID_YUKON_XL && chipid <= CHIP_ID_YUKON_OPT)
4552 strncpy(buf, name[chipid - CHIP_ID_YUKON_XL], sz);
4554 snprintf(buf, sz, "(chip %#x)", chipid);
4558 static int __devinit sky2_probe(struct pci_dev *pdev,
4559 const struct pci_device_id *ent)
4561 struct net_device *dev;
4563 int err, using_dac = 0, wol_default;
4567 err = pci_enable_device(pdev);
4569 dev_err(&pdev->dev, "cannot enable PCI device\n");
4573 /* Get configuration information
4574 * Note: only regular PCI config access once to test for HW issues
4575 * other PCI access through shared memory for speed and to
4576 * avoid MMCONFIG problems.
4578 err = pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
4580 dev_err(&pdev->dev, "PCI read config failed\n");
4585 dev_err(&pdev->dev, "PCI configuration read error\n");
4589 err = pci_request_regions(pdev, DRV_NAME);
4591 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
4592 goto err_out_disable;
4595 pci_set_master(pdev);
4597 if (sizeof(dma_addr_t) > sizeof(u32) &&
4598 !(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)))) {
4600 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
4602 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
4603 "for consistent allocations\n");
4604 goto err_out_free_regions;
4607 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
4609 dev_err(&pdev->dev, "no usable DMA configuration\n");
4610 goto err_out_free_regions;
4616 /* The sk98lin vendor driver uses hardware byte swapping but
4617 * this driver uses software swapping.
4619 reg &= ~PCI_REV_DESC;
4620 err = pci_write_config_dword(pdev,PCI_DEV_REG2, reg);
4622 dev_err(&pdev->dev, "PCI write config failed\n");
4623 goto err_out_free_regions;
4627 wol_default = device_may_wakeup(&pdev->dev) ? WAKE_MAGIC : 0;
4631 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
4632 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
4634 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
4635 goto err_out_free_regions;
4639 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
4641 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
4643 dev_err(&pdev->dev, "cannot map device registers\n");
4644 goto err_out_free_hw;
4647 /* ring for status responses */
4648 hw->st_le = pci_alloc_consistent(pdev, STATUS_LE_BYTES, &hw->st_dma);
4650 goto err_out_iounmap;
4652 err = sky2_init(hw);
4654 goto err_out_iounmap;
4656 dev_info(&pdev->dev, "Yukon-2 %s chip revision %d\n",
4657 sky2_name(hw->chip_id, buf1, sizeof(buf1)), hw->chip_rev);
4661 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
4664 goto err_out_free_pci;
4667 if (!disable_msi && pci_enable_msi(pdev) == 0) {
4668 err = sky2_test_msi(hw);
4669 if (err == -EOPNOTSUPP)
4670 pci_disable_msi(pdev);
4672 goto err_out_free_netdev;
4675 err = register_netdev(dev);
4677 dev_err(&pdev->dev, "cannot register net device\n");
4678 goto err_out_free_netdev;
4681 netif_carrier_off(dev);
4683 netif_napi_add(dev, &hw->napi, sky2_poll, NAPI_WEIGHT);
4685 err = request_irq(pdev->irq, sky2_intr,
4686 (hw->flags & SKY2_HW_USE_MSI) ? 0 : IRQF_SHARED,
4689 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
4690 goto err_out_unregister;
4692 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4693 napi_enable(&hw->napi);
4695 sky2_show_addr(dev);
4697 if (hw->ports > 1) {
4698 struct net_device *dev1;
4701 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
4702 if (dev1 && (err = register_netdev(dev1)) == 0)
4703 sky2_show_addr(dev1);
4705 dev_warn(&pdev->dev,
4706 "register of second port failed (%d)\n", err);
4714 setup_timer(&hw->watchdog_timer, sky2_watchdog, (unsigned long) hw);
4715 INIT_WORK(&hw->restart_work, sky2_restart);
4717 pci_set_drvdata(pdev, hw);
4718 pdev->d3_delay = 150;
4723 if (hw->flags & SKY2_HW_USE_MSI)
4724 pci_disable_msi(pdev);
4725 unregister_netdev(dev);
4726 err_out_free_netdev:
4729 sky2_write8(hw, B0_CTST, CS_RST_SET);
4730 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4735 err_out_free_regions:
4736 pci_release_regions(pdev);
4738 pci_disable_device(pdev);
4740 pci_set_drvdata(pdev, NULL);
4744 static void __devexit sky2_remove(struct pci_dev *pdev)
4746 struct sky2_hw *hw = pci_get_drvdata(pdev);
4752 del_timer_sync(&hw->watchdog_timer);
4753 cancel_work_sync(&hw->restart_work);
4755 for (i = hw->ports-1; i >= 0; --i)
4756 unregister_netdev(hw->dev[i]);
4758 sky2_write32(hw, B0_IMSK, 0);
4762 sky2_write8(hw, B0_CTST, CS_RST_SET);
4763 sky2_read8(hw, B0_CTST);
4765 free_irq(pdev->irq, hw);
4766 if (hw->flags & SKY2_HW_USE_MSI)
4767 pci_disable_msi(pdev);
4768 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
4769 pci_release_regions(pdev);
4770 pci_disable_device(pdev);
4772 for (i = hw->ports-1; i >= 0; --i)
4773 free_netdev(hw->dev[i]);
4778 pci_set_drvdata(pdev, NULL);
4782 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
4784 struct sky2_hw *hw = pci_get_drvdata(pdev);
4790 del_timer_sync(&hw->watchdog_timer);
4791 cancel_work_sync(&hw->restart_work);
4794 for (i = 0; i < hw->ports; i++) {
4795 struct net_device *dev = hw->dev[i];
4796 struct sky2_port *sky2 = netdev_priv(dev);
4801 sky2_wol_init(sky2);
4806 sky2_write32(hw, B0_IMSK, 0);
4807 napi_disable(&hw->napi);
4811 pci_save_state(pdev);
4812 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
4813 pci_set_power_state(pdev, pci_choose_state(pdev, state));
4818 static int sky2_resume(struct pci_dev *pdev)
4820 struct sky2_hw *hw = pci_get_drvdata(pdev);
4826 err = pci_set_power_state(pdev, PCI_D0);
4830 err = pci_restore_state(pdev);
4834 pci_enable_wake(pdev, PCI_D0, 0);
4836 /* Re-enable all clocks */
4837 if (hw->chip_id == CHIP_ID_YUKON_EX ||
4838 hw->chip_id == CHIP_ID_YUKON_EC_U ||
4839 hw->chip_id == CHIP_ID_YUKON_FE_P)
4840 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
4843 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
4844 napi_enable(&hw->napi);
4847 for (i = 0; i < hw->ports; i++) {
4848 err = sky2_reattach(hw->dev[i]);
4858 dev_err(&pdev->dev, "resume failed (%d)\n", err);
4859 pci_disable_device(pdev);
4864 static void sky2_shutdown(struct pci_dev *pdev)
4866 struct sky2_hw *hw = pci_get_drvdata(pdev);
4873 del_timer_sync(&hw->watchdog_timer);
4875 for (i = 0; i < hw->ports; i++) {
4876 struct net_device *dev = hw->dev[i];
4877 struct sky2_port *sky2 = netdev_priv(dev);
4881 sky2_wol_init(sky2);
4889 pci_enable_wake(pdev, PCI_D3hot, wol);
4890 pci_enable_wake(pdev, PCI_D3cold, wol);
4892 pci_disable_device(pdev);
4893 pci_set_power_state(pdev, PCI_D3hot);
4896 static struct pci_driver sky2_driver = {
4898 .id_table = sky2_id_table,
4899 .probe = sky2_probe,
4900 .remove = __devexit_p(sky2_remove),
4902 .suspend = sky2_suspend,
4903 .resume = sky2_resume,
4905 .shutdown = sky2_shutdown,
4908 static int __init sky2_init_module(void)
4910 pr_info(PFX "driver version " DRV_VERSION "\n");
4913 return pci_register_driver(&sky2_driver);
4916 static void __exit sky2_cleanup_module(void)
4918 pci_unregister_driver(&sky2_driver);
4919 sky2_debug_cleanup();
4922 module_init(sky2_init_module);
4923 module_exit(sky2_cleanup_module);
4925 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
4926 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
4927 MODULE_LICENSE("GPL");
4928 MODULE_VERSION(DRV_VERSION);