2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29 #include <linux/kernel.h>
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/netdevice.h>
33 #include <linux/etherdevice.h>
34 #include <linux/ethtool.h>
35 #include <linux/pci.h>
36 #include <linux/if_vlan.h>
38 #include <linux/delay.h>
39 #include <linux/crc32.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/debugfs.h>
42 #include <linux/sched.h>
43 #include <linux/seq_file.h>
44 #include <linux/mii.h>
45 #include <linux/slab.h>
46 #include <linux/dmi.h>
51 #define DRV_NAME "skge"
52 #define DRV_VERSION "1.13"
54 #define DEFAULT_TX_RING_SIZE 128
55 #define DEFAULT_RX_RING_SIZE 512
56 #define MAX_TX_RING_SIZE 1024
57 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
58 #define MAX_RX_RING_SIZE 4096
59 #define RX_COPY_THRESHOLD 128
60 #define RX_BUF_SIZE 1536
61 #define PHY_RETRIES 1000
62 #define ETH_JUMBO_MTU 9000
63 #define TX_WATCHDOG (5 * HZ)
64 #define NAPI_WEIGHT 64
68 #define SKGE_EEPROM_MAGIC 0x9933aabb
71 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
72 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
73 MODULE_LICENSE("GPL");
74 MODULE_VERSION(DRV_VERSION);
76 static const u32 default_msg = (NETIF_MSG_DRV | NETIF_MSG_PROBE |
77 NETIF_MSG_LINK | NETIF_MSG_IFUP |
80 static int debug = -1; /* defaults above */
81 module_param(debug, int, 0);
82 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
84 static DEFINE_PCI_DEVICE_TABLE(skge_id_table) = {
85 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
86 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
87 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
88 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
89 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
90 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
91 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
92 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
93 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
94 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
95 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
98 MODULE_DEVICE_TABLE(pci, skge_id_table);
100 static int skge_up(struct net_device *dev);
101 static int skge_down(struct net_device *dev);
102 static void skge_phy_reset(struct skge_port *skge);
103 static void skge_tx_clean(struct net_device *dev);
104 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
105 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
106 static void genesis_get_stats(struct skge_port *skge, u64 *data);
107 static void yukon_get_stats(struct skge_port *skge, u64 *data);
108 static void yukon_init(struct skge_hw *hw, int port);
109 static void genesis_mac_init(struct skge_hw *hw, int port);
110 static void genesis_link_up(struct skge_port *skge);
111 static void skge_set_multicast(struct net_device *dev);
113 /* Avoid conditionals by using array */
114 static const int txqaddr[] = { Q_XA1, Q_XA2 };
115 static const int rxqaddr[] = { Q_R1, Q_R2 };
116 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
117 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
118 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
119 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
121 static int skge_get_regs_len(struct net_device *dev)
127 * Returns copy of whole control register region
128 * Note: skip RAM address register because accessing it will
131 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
134 const struct skge_port *skge = netdev_priv(dev);
135 const void __iomem *io = skge->hw->regs;
138 memset(p, 0, regs->len);
139 memcpy_fromio(p, io, B3_RAM_ADDR);
141 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
142 regs->len - B3_RI_WTO_R1);
145 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
146 static u32 wol_supported(const struct skge_hw *hw)
148 if (hw->chip_id == CHIP_ID_GENESIS)
151 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
154 return WAKE_MAGIC | WAKE_PHY;
157 static void skge_wol_init(struct skge_port *skge)
159 struct skge_hw *hw = skge->hw;
160 int port = skge->port;
163 skge_write16(hw, B0_CTST, CS_RST_CLR);
164 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
167 skge_write8(hw, B0_POWER_CTRL,
168 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
170 /* WA code for COMA mode -- clear PHY reset */
171 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
172 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
173 u32 reg = skge_read32(hw, B2_GP_IO);
176 skge_write32(hw, B2_GP_IO, reg);
179 skge_write32(hw, SK_REG(port, GPHY_CTRL),
181 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
182 GPC_ANEG_1 | GPC_RST_SET);
184 skge_write32(hw, SK_REG(port, GPHY_CTRL),
186 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
187 GPC_ANEG_1 | GPC_RST_CLR);
189 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
191 /* Force to 10/100 skge_reset will re-enable on resume */
192 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
193 (PHY_AN_100FULL | PHY_AN_100HALF |
194 PHY_AN_10FULL | PHY_AN_10HALF | PHY_AN_CSMA));
196 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
197 gm_phy_write(hw, port, PHY_MARV_CTRL,
198 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
199 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
202 /* Set GMAC to no flow control and auto update for speed/duplex */
203 gma_write16(hw, port, GM_GP_CTRL,
204 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
205 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
207 /* Set WOL address */
208 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
209 skge->netdev->dev_addr, ETH_ALEN);
211 /* Turn on appropriate WOL control bits */
212 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
214 if (skge->wol & WAKE_PHY)
215 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
217 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
219 if (skge->wol & WAKE_MAGIC)
220 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
222 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;
224 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
225 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
228 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
231 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
233 struct skge_port *skge = netdev_priv(dev);
235 wol->supported = wol_supported(skge->hw);
236 wol->wolopts = skge->wol;
239 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
241 struct skge_port *skge = netdev_priv(dev);
242 struct skge_hw *hw = skge->hw;
244 if ((wol->wolopts & ~wol_supported(hw)) ||
245 !device_can_wakeup(&hw->pdev->dev))
248 skge->wol = wol->wolopts;
250 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
255 /* Determine supported/advertised modes based on hardware.
256 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
258 static u32 skge_supported_modes(const struct skge_hw *hw)
263 supported = (SUPPORTED_10baseT_Half |
264 SUPPORTED_10baseT_Full |
265 SUPPORTED_100baseT_Half |
266 SUPPORTED_100baseT_Full |
267 SUPPORTED_1000baseT_Half |
268 SUPPORTED_1000baseT_Full |
272 if (hw->chip_id == CHIP_ID_GENESIS)
273 supported &= ~(SUPPORTED_10baseT_Half |
274 SUPPORTED_10baseT_Full |
275 SUPPORTED_100baseT_Half |
276 SUPPORTED_100baseT_Full);
278 else if (hw->chip_id == CHIP_ID_YUKON)
279 supported &= ~SUPPORTED_1000baseT_Half;
281 supported = (SUPPORTED_1000baseT_Full |
282 SUPPORTED_1000baseT_Half |
289 static int skge_get_settings(struct net_device *dev,
290 struct ethtool_cmd *ecmd)
292 struct skge_port *skge = netdev_priv(dev);
293 struct skge_hw *hw = skge->hw;
295 ecmd->transceiver = XCVR_INTERNAL;
296 ecmd->supported = skge_supported_modes(hw);
299 ecmd->port = PORT_TP;
300 ecmd->phy_address = hw->phy_addr;
302 ecmd->port = PORT_FIBRE;
304 ecmd->advertising = skge->advertising;
305 ecmd->autoneg = skge->autoneg;
306 ethtool_cmd_speed_set(ecmd, skge->speed);
307 ecmd->duplex = skge->duplex;
311 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
313 struct skge_port *skge = netdev_priv(dev);
314 const struct skge_hw *hw = skge->hw;
315 u32 supported = skge_supported_modes(hw);
318 if (ecmd->autoneg == AUTONEG_ENABLE) {
319 ecmd->advertising = supported;
324 u32 speed = ethtool_cmd_speed(ecmd);
328 if (ecmd->duplex == DUPLEX_FULL)
329 setting = SUPPORTED_1000baseT_Full;
330 else if (ecmd->duplex == DUPLEX_HALF)
331 setting = SUPPORTED_1000baseT_Half;
336 if (ecmd->duplex == DUPLEX_FULL)
337 setting = SUPPORTED_100baseT_Full;
338 else if (ecmd->duplex == DUPLEX_HALF)
339 setting = SUPPORTED_100baseT_Half;
345 if (ecmd->duplex == DUPLEX_FULL)
346 setting = SUPPORTED_10baseT_Full;
347 else if (ecmd->duplex == DUPLEX_HALF)
348 setting = SUPPORTED_10baseT_Half;
356 if ((setting & supported) == 0)
360 skge->duplex = ecmd->duplex;
363 skge->autoneg = ecmd->autoneg;
364 skge->advertising = ecmd->advertising;
366 if (netif_running(dev)) {
378 static void skge_get_drvinfo(struct net_device *dev,
379 struct ethtool_drvinfo *info)
381 struct skge_port *skge = netdev_priv(dev);
383 strcpy(info->driver, DRV_NAME);
384 strcpy(info->version, DRV_VERSION);
385 strcpy(info->fw_version, "N/A");
386 strcpy(info->bus_info, pci_name(skge->hw->pdev));
389 static const struct skge_stat {
390 char name[ETH_GSTRING_LEN];
394 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
395 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
397 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
398 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
399 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
400 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
401 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
402 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
403 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
404 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
406 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
407 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
408 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
409 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
410 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
411 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
413 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
414 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
415 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
416 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
417 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
420 static int skge_get_sset_count(struct net_device *dev, int sset)
424 return ARRAY_SIZE(skge_stats);
430 static void skge_get_ethtool_stats(struct net_device *dev,
431 struct ethtool_stats *stats, u64 *data)
433 struct skge_port *skge = netdev_priv(dev);
435 if (skge->hw->chip_id == CHIP_ID_GENESIS)
436 genesis_get_stats(skge, data);
438 yukon_get_stats(skge, data);
441 /* Use hardware MIB variables for critical path statistics and
442 * transmit feedback not reported at interrupt.
443 * Other errors are accounted for in interrupt handler.
445 static struct net_device_stats *skge_get_stats(struct net_device *dev)
447 struct skge_port *skge = netdev_priv(dev);
448 u64 data[ARRAY_SIZE(skge_stats)];
450 if (skge->hw->chip_id == CHIP_ID_GENESIS)
451 genesis_get_stats(skge, data);
453 yukon_get_stats(skge, data);
455 dev->stats.tx_bytes = data[0];
456 dev->stats.rx_bytes = data[1];
457 dev->stats.tx_packets = data[2] + data[4] + data[6];
458 dev->stats.rx_packets = data[3] + data[5] + data[7];
459 dev->stats.multicast = data[3] + data[5];
460 dev->stats.collisions = data[10];
461 dev->stats.tx_aborted_errors = data[12];
466 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
472 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
473 memcpy(data + i * ETH_GSTRING_LEN,
474 skge_stats[i].name, ETH_GSTRING_LEN);
479 static void skge_get_ring_param(struct net_device *dev,
480 struct ethtool_ringparam *p)
482 struct skge_port *skge = netdev_priv(dev);
484 p->rx_max_pending = MAX_RX_RING_SIZE;
485 p->tx_max_pending = MAX_TX_RING_SIZE;
486 p->rx_mini_max_pending = 0;
487 p->rx_jumbo_max_pending = 0;
489 p->rx_pending = skge->rx_ring.count;
490 p->tx_pending = skge->tx_ring.count;
491 p->rx_mini_pending = 0;
492 p->rx_jumbo_pending = 0;
495 static int skge_set_ring_param(struct net_device *dev,
496 struct ethtool_ringparam *p)
498 struct skge_port *skge = netdev_priv(dev);
501 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
502 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
505 skge->rx_ring.count = p->rx_pending;
506 skge->tx_ring.count = p->tx_pending;
508 if (netif_running(dev)) {
518 static u32 skge_get_msglevel(struct net_device *netdev)
520 struct skge_port *skge = netdev_priv(netdev);
521 return skge->msg_enable;
524 static void skge_set_msglevel(struct net_device *netdev, u32 value)
526 struct skge_port *skge = netdev_priv(netdev);
527 skge->msg_enable = value;
530 static int skge_nway_reset(struct net_device *dev)
532 struct skge_port *skge = netdev_priv(dev);
534 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
537 skge_phy_reset(skge);
541 static void skge_get_pauseparam(struct net_device *dev,
542 struct ethtool_pauseparam *ecmd)
544 struct skge_port *skge = netdev_priv(dev);
546 ecmd->rx_pause = ((skge->flow_control == FLOW_MODE_SYMMETRIC) ||
547 (skge->flow_control == FLOW_MODE_SYM_OR_REM));
548 ecmd->tx_pause = (ecmd->rx_pause ||
549 (skge->flow_control == FLOW_MODE_LOC_SEND));
551 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
554 static int skge_set_pauseparam(struct net_device *dev,
555 struct ethtool_pauseparam *ecmd)
557 struct skge_port *skge = netdev_priv(dev);
558 struct ethtool_pauseparam old;
561 skge_get_pauseparam(dev, &old);
563 if (ecmd->autoneg != old.autoneg)
564 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
566 if (ecmd->rx_pause && ecmd->tx_pause)
567 skge->flow_control = FLOW_MODE_SYMMETRIC;
568 else if (ecmd->rx_pause && !ecmd->tx_pause)
569 skge->flow_control = FLOW_MODE_SYM_OR_REM;
570 else if (!ecmd->rx_pause && ecmd->tx_pause)
571 skge->flow_control = FLOW_MODE_LOC_SEND;
573 skge->flow_control = FLOW_MODE_NONE;
576 if (netif_running(dev)) {
588 /* Chip internal frequency for clock calculations */
589 static inline u32 hwkhz(const struct skge_hw *hw)
591 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
594 /* Chip HZ to microseconds */
595 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
597 return (ticks * 1000) / hwkhz(hw);
600 /* Microseconds to chip HZ */
601 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
603 return hwkhz(hw) * usec / 1000;
606 static int skge_get_coalesce(struct net_device *dev,
607 struct ethtool_coalesce *ecmd)
609 struct skge_port *skge = netdev_priv(dev);
610 struct skge_hw *hw = skge->hw;
611 int port = skge->port;
613 ecmd->rx_coalesce_usecs = 0;
614 ecmd->tx_coalesce_usecs = 0;
616 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
617 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
618 u32 msk = skge_read32(hw, B2_IRQM_MSK);
620 if (msk & rxirqmask[port])
621 ecmd->rx_coalesce_usecs = delay;
622 if (msk & txirqmask[port])
623 ecmd->tx_coalesce_usecs = delay;
629 /* Note: interrupt timer is per board, but can turn on/off per port */
630 static int skge_set_coalesce(struct net_device *dev,
631 struct ethtool_coalesce *ecmd)
633 struct skge_port *skge = netdev_priv(dev);
634 struct skge_hw *hw = skge->hw;
635 int port = skge->port;
636 u32 msk = skge_read32(hw, B2_IRQM_MSK);
639 if (ecmd->rx_coalesce_usecs == 0)
640 msk &= ~rxirqmask[port];
641 else if (ecmd->rx_coalesce_usecs < 25 ||
642 ecmd->rx_coalesce_usecs > 33333)
645 msk |= rxirqmask[port];
646 delay = ecmd->rx_coalesce_usecs;
649 if (ecmd->tx_coalesce_usecs == 0)
650 msk &= ~txirqmask[port];
651 else if (ecmd->tx_coalesce_usecs < 25 ||
652 ecmd->tx_coalesce_usecs > 33333)
655 msk |= txirqmask[port];
656 delay = min(delay, ecmd->rx_coalesce_usecs);
659 skge_write32(hw, B2_IRQM_MSK, msk);
661 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
663 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
664 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
669 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
670 static void skge_led(struct skge_port *skge, enum led_mode mode)
672 struct skge_hw *hw = skge->hw;
673 int port = skge->port;
675 spin_lock_bh(&hw->phy_lock);
676 if (hw->chip_id == CHIP_ID_GENESIS) {
679 if (hw->phy_type == SK_PHY_BCOM)
680 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
682 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
683 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
685 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
686 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
687 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
691 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
692 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
694 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
695 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
700 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
701 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
702 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
704 if (hw->phy_type == SK_PHY_BCOM)
705 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
707 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
708 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
709 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
716 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
717 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
718 PHY_M_LED_MO_DUP(MO_LED_OFF) |
719 PHY_M_LED_MO_10(MO_LED_OFF) |
720 PHY_M_LED_MO_100(MO_LED_OFF) |
721 PHY_M_LED_MO_1000(MO_LED_OFF) |
722 PHY_M_LED_MO_RX(MO_LED_OFF));
725 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
726 PHY_M_LED_PULS_DUR(PULS_170MS) |
727 PHY_M_LED_BLINK_RT(BLINK_84MS) |
731 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
732 PHY_M_LED_MO_RX(MO_LED_OFF) |
733 (skge->speed == SPEED_100 ?
734 PHY_M_LED_MO_100(MO_LED_ON) : 0));
737 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
738 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
739 PHY_M_LED_MO_DUP(MO_LED_ON) |
740 PHY_M_LED_MO_10(MO_LED_ON) |
741 PHY_M_LED_MO_100(MO_LED_ON) |
742 PHY_M_LED_MO_1000(MO_LED_ON) |
743 PHY_M_LED_MO_RX(MO_LED_ON));
746 spin_unlock_bh(&hw->phy_lock);
749 /* blink LED's for finding board */
750 static int skge_set_phys_id(struct net_device *dev,
751 enum ethtool_phys_id_state state)
753 struct skge_port *skge = netdev_priv(dev);
756 case ETHTOOL_ID_ACTIVE:
757 return 2; /* cycle on/off twice per second */
760 skge_led(skge, LED_MODE_TST);
764 skge_led(skge, LED_MODE_OFF);
767 case ETHTOOL_ID_INACTIVE:
768 /* back to regular LED state */
769 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
775 static int skge_get_eeprom_len(struct net_device *dev)
777 struct skge_port *skge = netdev_priv(dev);
780 pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2);
781 return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8);
784 static u32 skge_vpd_read(struct pci_dev *pdev, int cap, u16 offset)
788 pci_write_config_word(pdev, cap + PCI_VPD_ADDR, offset);
791 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
792 } while (!(offset & PCI_VPD_ADDR_F));
794 pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &val);
798 static void skge_vpd_write(struct pci_dev *pdev, int cap, u16 offset, u32 val)
800 pci_write_config_dword(pdev, cap + PCI_VPD_DATA, val);
801 pci_write_config_word(pdev, cap + PCI_VPD_ADDR,
802 offset | PCI_VPD_ADDR_F);
805 pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &offset);
806 } while (offset & PCI_VPD_ADDR_F);
809 static int skge_get_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
812 struct skge_port *skge = netdev_priv(dev);
813 struct pci_dev *pdev = skge->hw->pdev;
814 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
815 int length = eeprom->len;
816 u16 offset = eeprom->offset;
821 eeprom->magic = SKGE_EEPROM_MAGIC;
824 u32 val = skge_vpd_read(pdev, cap, offset);
825 int n = min_t(int, length, sizeof(val));
827 memcpy(data, &val, n);
835 static int skge_set_eeprom(struct net_device *dev, struct ethtool_eeprom *eeprom,
838 struct skge_port *skge = netdev_priv(dev);
839 struct pci_dev *pdev = skge->hw->pdev;
840 int cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
841 int length = eeprom->len;
842 u16 offset = eeprom->offset;
847 if (eeprom->magic != SKGE_EEPROM_MAGIC)
852 int n = min_t(int, length, sizeof(val));
855 val = skge_vpd_read(pdev, cap, offset);
856 memcpy(&val, data, n);
858 skge_vpd_write(pdev, cap, offset, val);
867 static const struct ethtool_ops skge_ethtool_ops = {
868 .get_settings = skge_get_settings,
869 .set_settings = skge_set_settings,
870 .get_drvinfo = skge_get_drvinfo,
871 .get_regs_len = skge_get_regs_len,
872 .get_regs = skge_get_regs,
873 .get_wol = skge_get_wol,
874 .set_wol = skge_set_wol,
875 .get_msglevel = skge_get_msglevel,
876 .set_msglevel = skge_set_msglevel,
877 .nway_reset = skge_nway_reset,
878 .get_link = ethtool_op_get_link,
879 .get_eeprom_len = skge_get_eeprom_len,
880 .get_eeprom = skge_get_eeprom,
881 .set_eeprom = skge_set_eeprom,
882 .get_ringparam = skge_get_ring_param,
883 .set_ringparam = skge_set_ring_param,
884 .get_pauseparam = skge_get_pauseparam,
885 .set_pauseparam = skge_set_pauseparam,
886 .get_coalesce = skge_get_coalesce,
887 .set_coalesce = skge_set_coalesce,
888 .get_strings = skge_get_strings,
889 .set_phys_id = skge_set_phys_id,
890 .get_sset_count = skge_get_sset_count,
891 .get_ethtool_stats = skge_get_ethtool_stats,
895 * Allocate ring elements and chain them together
896 * One-to-one association of board descriptors with ring elements
898 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
900 struct skge_tx_desc *d;
901 struct skge_element *e;
904 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
908 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
910 if (i == ring->count - 1) {
911 e->next = ring->start;
912 d->next_offset = base;
915 d->next_offset = base + (i+1) * sizeof(*d);
918 ring->to_use = ring->to_clean = ring->start;
923 /* Allocate and setup a new buffer for receiving */
924 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
925 struct sk_buff *skb, unsigned int bufsize)
927 struct skge_rx_desc *rd = e->desc;
930 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
934 rd->dma_hi = map >> 32;
936 rd->csum1_start = ETH_HLEN;
937 rd->csum2_start = ETH_HLEN;
943 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
944 dma_unmap_addr_set(e, mapaddr, map);
945 dma_unmap_len_set(e, maplen, bufsize);
948 /* Resume receiving using existing skb,
949 * Note: DMA address is not changed by chip.
950 * MTU not changed while receiver active.
952 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
954 struct skge_rx_desc *rd = e->desc;
957 rd->csum2_start = ETH_HLEN;
961 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
965 /* Free all buffers in receive ring, assumes receiver stopped */
966 static void skge_rx_clean(struct skge_port *skge)
968 struct skge_hw *hw = skge->hw;
969 struct skge_ring *ring = &skge->rx_ring;
970 struct skge_element *e;
974 struct skge_rx_desc *rd = e->desc;
977 pci_unmap_single(hw->pdev,
978 dma_unmap_addr(e, mapaddr),
979 dma_unmap_len(e, maplen),
981 dev_kfree_skb(e->skb);
984 } while ((e = e->next) != ring->start);
988 /* Allocate buffers for receive ring
989 * For receive: to_clean is next received frame.
991 static int skge_rx_fill(struct net_device *dev)
993 struct skge_port *skge = netdev_priv(dev);
994 struct skge_ring *ring = &skge->rx_ring;
995 struct skge_element *e;
1001 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
1006 skb_reserve(skb, NET_IP_ALIGN);
1007 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
1008 } while ((e = e->next) != ring->start);
1010 ring->to_clean = ring->start;
1014 static const char *skge_pause(enum pause_status status)
1017 case FLOW_STAT_NONE:
1019 case FLOW_STAT_REM_SEND:
1021 case FLOW_STAT_LOC_SEND:
1023 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
1026 return "indeterminated";
1031 static void skge_link_up(struct skge_port *skge)
1033 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
1034 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
1036 netif_carrier_on(skge->netdev);
1037 netif_wake_queue(skge->netdev);
1039 netif_info(skge, link, skge->netdev,
1040 "Link is up at %d Mbps, %s duplex, flow control %s\n",
1042 skge->duplex == DUPLEX_FULL ? "full" : "half",
1043 skge_pause(skge->flow_status));
1046 static void skge_link_down(struct skge_port *skge)
1048 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
1049 netif_carrier_off(skge->netdev);
1050 netif_stop_queue(skge->netdev);
1052 netif_info(skge, link, skge->netdev, "Link is down\n");
1056 static void xm_link_down(struct skge_hw *hw, int port)
1058 struct net_device *dev = hw->dev[port];
1059 struct skge_port *skge = netdev_priv(dev);
1061 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1063 if (netif_carrier_ok(dev))
1064 skge_link_down(skge);
1067 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1071 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1072 *val = xm_read16(hw, port, XM_PHY_DATA);
1074 if (hw->phy_type == SK_PHY_XMAC)
1077 for (i = 0; i < PHY_RETRIES; i++) {
1078 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1085 *val = xm_read16(hw, port, XM_PHY_DATA);
1090 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1093 if (__xm_phy_read(hw, port, reg, &v))
1094 pr_warning("%s: phy read timed out\n", hw->dev[port]->name);
1098 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1102 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1103 for (i = 0; i < PHY_RETRIES; i++) {
1104 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1111 xm_write16(hw, port, XM_PHY_DATA, val);
1112 for (i = 0; i < PHY_RETRIES; i++) {
1113 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1120 static void genesis_init(struct skge_hw *hw)
1122 /* set blink source counter */
1123 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1124 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1126 /* configure mac arbiter */
1127 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1129 /* configure mac arbiter timeout values */
1130 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1131 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1132 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1133 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1135 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1136 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1137 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1138 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1140 /* configure packet arbiter timeout */
1141 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1142 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1143 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1144 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1145 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1148 static void genesis_reset(struct skge_hw *hw, int port)
1150 static const u8 zero[8] = { 0 };
1153 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1155 /* reset the statistics module */
1156 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1157 xm_write16(hw, port, XM_IMSK, XM_IMSK_DISABLE);
1158 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1159 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1160 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1162 /* disable Broadcom PHY IRQ */
1163 if (hw->phy_type == SK_PHY_BCOM)
1164 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1166 xm_outhash(hw, port, XM_HSM, zero);
1168 /* Flush TX and RX fifo */
1169 reg = xm_read32(hw, port, XM_MODE);
1170 xm_write32(hw, port, XM_MODE, reg | XM_MD_FTF);
1171 xm_write32(hw, port, XM_MODE, reg | XM_MD_FRF);
1175 /* Convert mode to MII values */
1176 static const u16 phy_pause_map[] = {
1177 [FLOW_MODE_NONE] = 0,
1178 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1179 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1180 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1183 /* special defines for FIBER (88E1011S only) */
1184 static const u16 fiber_pause_map[] = {
1185 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1186 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1187 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1188 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1192 /* Check status of Broadcom phy link */
1193 static void bcom_check_link(struct skge_hw *hw, int port)
1195 struct net_device *dev = hw->dev[port];
1196 struct skge_port *skge = netdev_priv(dev);
1199 /* read twice because of latch */
1200 xm_phy_read(hw, port, PHY_BCOM_STAT);
1201 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1203 if ((status & PHY_ST_LSYNC) == 0) {
1204 xm_link_down(hw, port);
1208 if (skge->autoneg == AUTONEG_ENABLE) {
1211 if (!(status & PHY_ST_AN_OVER))
1214 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1215 if (lpa & PHY_B_AN_RF) {
1216 netdev_notice(dev, "remote fault\n");
1220 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1222 /* Check Duplex mismatch */
1223 switch (aux & PHY_B_AS_AN_RES_MSK) {
1224 case PHY_B_RES_1000FD:
1225 skge->duplex = DUPLEX_FULL;
1227 case PHY_B_RES_1000HD:
1228 skge->duplex = DUPLEX_HALF;
1231 netdev_notice(dev, "duplex mismatch\n");
1235 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1236 switch (aux & PHY_B_AS_PAUSE_MSK) {
1237 case PHY_B_AS_PAUSE_MSK:
1238 skge->flow_status = FLOW_STAT_SYMMETRIC;
1241 skge->flow_status = FLOW_STAT_REM_SEND;
1244 skge->flow_status = FLOW_STAT_LOC_SEND;
1247 skge->flow_status = FLOW_STAT_NONE;
1249 skge->speed = SPEED_1000;
1252 if (!netif_carrier_ok(dev))
1253 genesis_link_up(skge);
1256 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1257 * Phy on for 100 or 10Mbit operation
1259 static void bcom_phy_init(struct skge_port *skge)
1261 struct skge_hw *hw = skge->hw;
1262 int port = skge->port;
1264 u16 id1, r, ext, ctl;
1266 /* magic workaround patterns for Broadcom */
1267 static const struct {
1271 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1272 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1273 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1274 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1276 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1277 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1280 /* read Id from external PHY (all have the same address) */
1281 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1283 /* Optimize MDIO transfer by suppressing preamble. */
1284 r = xm_read16(hw, port, XM_MMU_CMD);
1286 xm_write16(hw, port, XM_MMU_CMD, r);
1289 case PHY_BCOM_ID1_C0:
1291 * Workaround BCOM Errata for the C0 type.
1292 * Write magic patterns to reserved registers.
1294 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1295 xm_phy_write(hw, port,
1296 C0hack[i].reg, C0hack[i].val);
1299 case PHY_BCOM_ID1_A1:
1301 * Workaround BCOM Errata for the A1 type.
1302 * Write magic patterns to reserved registers.
1304 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1305 xm_phy_write(hw, port,
1306 A1hack[i].reg, A1hack[i].val);
1311 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1312 * Disable Power Management after reset.
1314 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1315 r |= PHY_B_AC_DIS_PM;
1316 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1319 xm_read16(hw, port, XM_ISRC);
1321 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1322 ctl = PHY_CT_SP1000; /* always 1000mbit */
1324 if (skge->autoneg == AUTONEG_ENABLE) {
1326 * Workaround BCOM Errata #1 for the C5 type.
1327 * 1000Base-T Link Acquisition Failure in Slave Mode
1328 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1330 u16 adv = PHY_B_1000C_RD;
1331 if (skge->advertising & ADVERTISED_1000baseT_Half)
1332 adv |= PHY_B_1000C_AHD;
1333 if (skge->advertising & ADVERTISED_1000baseT_Full)
1334 adv |= PHY_B_1000C_AFD;
1335 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1337 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1339 if (skge->duplex == DUPLEX_FULL)
1340 ctl |= PHY_CT_DUP_MD;
1341 /* Force to slave */
1342 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1345 /* Set autonegotiation pause parameters */
1346 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1347 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1349 /* Handle Jumbo frames */
1350 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1351 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1352 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1354 ext |= PHY_B_PEC_HIGH_LA;
1358 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1359 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1361 /* Use link status change interrupt */
1362 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1365 static void xm_phy_init(struct skge_port *skge)
1367 struct skge_hw *hw = skge->hw;
1368 int port = skge->port;
1371 if (skge->autoneg == AUTONEG_ENABLE) {
1372 if (skge->advertising & ADVERTISED_1000baseT_Half)
1373 ctrl |= PHY_X_AN_HD;
1374 if (skge->advertising & ADVERTISED_1000baseT_Full)
1375 ctrl |= PHY_X_AN_FD;
1377 ctrl |= fiber_pause_map[skge->flow_control];
1379 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1381 /* Restart Auto-negotiation */
1382 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1384 /* Set DuplexMode in Config register */
1385 if (skge->duplex == DUPLEX_FULL)
1386 ctrl |= PHY_CT_DUP_MD;
1388 * Do NOT enable Auto-negotiation here. This would hold
1389 * the link down because no IDLEs are transmitted
1393 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1395 /* Poll PHY for status changes */
1396 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1399 static int xm_check_link(struct net_device *dev)
1401 struct skge_port *skge = netdev_priv(dev);
1402 struct skge_hw *hw = skge->hw;
1403 int port = skge->port;
1406 /* read twice because of latch */
1407 xm_phy_read(hw, port, PHY_XMAC_STAT);
1408 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1410 if ((status & PHY_ST_LSYNC) == 0) {
1411 xm_link_down(hw, port);
1415 if (skge->autoneg == AUTONEG_ENABLE) {
1418 if (!(status & PHY_ST_AN_OVER))
1421 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1422 if (lpa & PHY_B_AN_RF) {
1423 netdev_notice(dev, "remote fault\n");
1427 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1429 /* Check Duplex mismatch */
1430 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1432 skge->duplex = DUPLEX_FULL;
1435 skge->duplex = DUPLEX_HALF;
1438 netdev_notice(dev, "duplex mismatch\n");
1442 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1443 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1444 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1445 (lpa & PHY_X_P_SYM_MD))
1446 skge->flow_status = FLOW_STAT_SYMMETRIC;
1447 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1448 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1449 /* Enable PAUSE receive, disable PAUSE transmit */
1450 skge->flow_status = FLOW_STAT_REM_SEND;
1451 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1452 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1453 /* Disable PAUSE receive, enable PAUSE transmit */
1454 skge->flow_status = FLOW_STAT_LOC_SEND;
1456 skge->flow_status = FLOW_STAT_NONE;
1458 skge->speed = SPEED_1000;
1461 if (!netif_carrier_ok(dev))
1462 genesis_link_up(skge);
1466 /* Poll to check for link coming up.
1468 * Since internal PHY is wired to a level triggered pin, can't
1469 * get an interrupt when carrier is detected, need to poll for
1472 static void xm_link_timer(unsigned long arg)
1474 struct skge_port *skge = (struct skge_port *) arg;
1475 struct net_device *dev = skge->netdev;
1476 struct skge_hw *hw = skge->hw;
1477 int port = skge->port;
1479 unsigned long flags;
1481 if (!netif_running(dev))
1484 spin_lock_irqsave(&hw->phy_lock, flags);
1487 * Verify that the link by checking GPIO register three times.
1488 * This pin has the signal from the link_sync pin connected to it.
1490 for (i = 0; i < 3; i++) {
1491 if (xm_read16(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1495 /* Re-enable interrupt to detect link down */
1496 if (xm_check_link(dev)) {
1497 u16 msk = xm_read16(hw, port, XM_IMSK);
1498 msk &= ~XM_IS_INP_ASS;
1499 xm_write16(hw, port, XM_IMSK, msk);
1500 xm_read16(hw, port, XM_ISRC);
1503 mod_timer(&skge->link_timer,
1504 round_jiffies(jiffies + LINK_HZ));
1506 spin_unlock_irqrestore(&hw->phy_lock, flags);
1509 static void genesis_mac_init(struct skge_hw *hw, int port)
1511 struct net_device *dev = hw->dev[port];
1512 struct skge_port *skge = netdev_priv(dev);
1513 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1516 static const u8 zero[6] = { 0 };
1518 for (i = 0; i < 10; i++) {
1519 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1521 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1526 netdev_warn(dev, "genesis reset failed\n");
1529 /* Unreset the XMAC. */
1530 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1533 * Perform additional initialization for external PHYs,
1534 * namely for the 1000baseTX cards that use the XMAC's
1537 if (hw->phy_type != SK_PHY_XMAC) {
1538 /* Take external Phy out of reset */
1539 r = skge_read32(hw, B2_GP_IO);
1541 r |= GP_DIR_0|GP_IO_0;
1543 r |= GP_DIR_2|GP_IO_2;
1545 skge_write32(hw, B2_GP_IO, r);
1547 /* Enable GMII interface */
1548 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1552 switch (hw->phy_type) {
1557 bcom_phy_init(skge);
1558 bcom_check_link(hw, port);
1561 /* Set Station Address */
1562 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1564 /* We don't use match addresses so clear */
1565 for (i = 1; i < 16; i++)
1566 xm_outaddr(hw, port, XM_EXM(i), zero);
1568 /* Clear MIB counters */
1569 xm_write16(hw, port, XM_STAT_CMD,
1570 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1571 /* Clear two times according to Errata #3 */
1572 xm_write16(hw, port, XM_STAT_CMD,
1573 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1575 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1576 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1578 /* We don't need the FCS appended to the packet. */
1579 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1581 r |= XM_RX_BIG_PK_OK;
1583 if (skge->duplex == DUPLEX_HALF) {
1585 * If in manual half duplex mode the other side might be in
1586 * full duplex mode, so ignore if a carrier extension is not seen
1587 * on frames received
1589 r |= XM_RX_DIS_CEXT;
1591 xm_write16(hw, port, XM_RX_CMD, r);
1593 /* We want short frames padded to 60 bytes. */
1594 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1596 /* Increase threshold for jumbo frames on dual port */
1597 if (hw->ports > 1 && jumbo)
1598 xm_write16(hw, port, XM_TX_THR, 1020);
1600 xm_write16(hw, port, XM_TX_THR, 512);
1603 * Enable the reception of all error frames. This is is
1604 * a necessary evil due to the design of the XMAC. The
1605 * XMAC's receive FIFO is only 8K in size, however jumbo
1606 * frames can be up to 9000 bytes in length. When bad
1607 * frame filtering is enabled, the XMAC's RX FIFO operates
1608 * in 'store and forward' mode. For this to work, the
1609 * entire frame has to fit into the FIFO, but that means
1610 * that jumbo frames larger than 8192 bytes will be
1611 * truncated. Disabling all bad frame filtering causes
1612 * the RX FIFO to operate in streaming mode, in which
1613 * case the XMAC will start transferring frames out of the
1614 * RX FIFO as soon as the FIFO threshold is reached.
1616 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1620 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1621 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1622 * and 'Octets Rx OK Hi Cnt Ov'.
1624 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1627 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1628 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1629 * and 'Octets Tx OK Hi Cnt Ov'.
1631 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1633 /* Configure MAC arbiter */
1634 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1636 /* configure timeout values */
1637 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1638 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1639 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1640 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1642 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1643 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1644 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1645 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1647 /* Configure Rx MAC FIFO */
1648 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1649 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1650 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1652 /* Configure Tx MAC FIFO */
1653 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1654 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1655 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1658 /* Enable frame flushing if jumbo frames used */
1659 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_FLUSH);
1661 /* enable timeout timers if normal frames */
1662 skge_write16(hw, B3_PA_CTRL,
1663 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1667 static void genesis_stop(struct skge_port *skge)
1669 struct skge_hw *hw = skge->hw;
1670 int port = skge->port;
1671 unsigned retries = 1000;
1674 /* Disable Tx and Rx */
1675 cmd = xm_read16(hw, port, XM_MMU_CMD);
1676 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1677 xm_write16(hw, port, XM_MMU_CMD, cmd);
1679 genesis_reset(hw, port);
1681 /* Clear Tx packet arbiter timeout IRQ */
1682 skge_write16(hw, B3_PA_CTRL,
1683 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1686 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1688 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1689 if (!(skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST))
1691 } while (--retries > 0);
1693 /* For external PHYs there must be special handling */
1694 if (hw->phy_type != SK_PHY_XMAC) {
1695 u32 reg = skge_read32(hw, B2_GP_IO);
1703 skge_write32(hw, B2_GP_IO, reg);
1704 skge_read32(hw, B2_GP_IO);
1707 xm_write16(hw, port, XM_MMU_CMD,
1708 xm_read16(hw, port, XM_MMU_CMD)
1709 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1711 xm_read16(hw, port, XM_MMU_CMD);
1715 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1717 struct skge_hw *hw = skge->hw;
1718 int port = skge->port;
1720 unsigned long timeout = jiffies + HZ;
1722 xm_write16(hw, port,
1723 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1725 /* wait for update to complete */
1726 while (xm_read16(hw, port, XM_STAT_CMD)
1727 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1728 if (time_after(jiffies, timeout))
1733 /* special case for 64 bit octet counter */
1734 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1735 | xm_read32(hw, port, XM_TXO_OK_LO);
1736 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1737 | xm_read32(hw, port, XM_RXO_OK_LO);
1739 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1740 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1743 static void genesis_mac_intr(struct skge_hw *hw, int port)
1745 struct net_device *dev = hw->dev[port];
1746 struct skge_port *skge = netdev_priv(dev);
1747 u16 status = xm_read16(hw, port, XM_ISRC);
1749 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1750 "mac interrupt status 0x%x\n", status);
1752 if (hw->phy_type == SK_PHY_XMAC && (status & XM_IS_INP_ASS)) {
1753 xm_link_down(hw, port);
1754 mod_timer(&skge->link_timer, jiffies + 1);
1757 if (status & XM_IS_TXF_UR) {
1758 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1759 ++dev->stats.tx_fifo_errors;
1763 static void genesis_link_up(struct skge_port *skge)
1765 struct skge_hw *hw = skge->hw;
1766 int port = skge->port;
1770 cmd = xm_read16(hw, port, XM_MMU_CMD);
1773 * enabling pause frame reception is required for 1000BT
1774 * because the XMAC is not reset if the link is going down
1776 if (skge->flow_status == FLOW_STAT_NONE ||
1777 skge->flow_status == FLOW_STAT_LOC_SEND)
1778 /* Disable Pause Frame Reception */
1779 cmd |= XM_MMU_IGN_PF;
1781 /* Enable Pause Frame Reception */
1782 cmd &= ~XM_MMU_IGN_PF;
1784 xm_write16(hw, port, XM_MMU_CMD, cmd);
1786 mode = xm_read32(hw, port, XM_MODE);
1787 if (skge->flow_status == FLOW_STAT_SYMMETRIC ||
1788 skge->flow_status == FLOW_STAT_LOC_SEND) {
1790 * Configure Pause Frame Generation
1791 * Use internal and external Pause Frame Generation.
1792 * Sending pause frames is edge triggered.
1793 * Send a Pause frame with the maximum pause time if
1794 * internal oder external FIFO full condition occurs.
1795 * Send a zero pause time frame to re-start transmission.
1797 /* XM_PAUSE_DA = '010000C28001' (default) */
1798 /* XM_MAC_PTIME = 0xffff (maximum) */
1799 /* remember this value is defined in big endian (!) */
1800 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1802 mode |= XM_PAUSE_MODE;
1803 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1806 * disable pause frame generation is required for 1000BT
1807 * because the XMAC is not reset if the link is going down
1809 /* Disable Pause Mode in Mode Register */
1810 mode &= ~XM_PAUSE_MODE;
1812 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1815 xm_write32(hw, port, XM_MODE, mode);
1817 /* Turn on detection of Tx underrun */
1818 msk = xm_read16(hw, port, XM_IMSK);
1819 msk &= ~XM_IS_TXF_UR;
1820 xm_write16(hw, port, XM_IMSK, msk);
1822 xm_read16(hw, port, XM_ISRC);
1824 /* get MMU Command Reg. */
1825 cmd = xm_read16(hw, port, XM_MMU_CMD);
1826 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1827 cmd |= XM_MMU_GMII_FD;
1830 * Workaround BCOM Errata (#10523) for all BCom Phys
1831 * Enable Power Management after link up
1833 if (hw->phy_type == SK_PHY_BCOM) {
1834 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1835 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1836 & ~PHY_B_AC_DIS_PM);
1837 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1841 xm_write16(hw, port, XM_MMU_CMD,
1842 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1847 static inline void bcom_phy_intr(struct skge_port *skge)
1849 struct skge_hw *hw = skge->hw;
1850 int port = skge->port;
1853 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1854 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
1855 "phy interrupt status 0x%x\n", isrc);
1857 if (isrc & PHY_B_IS_PSE)
1858 pr_err("%s: uncorrectable pair swap error\n",
1859 hw->dev[port]->name);
1861 /* Workaround BCom Errata:
1862 * enable and disable loopback mode if "NO HCD" occurs.
1864 if (isrc & PHY_B_IS_NO_HDCL) {
1865 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1866 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1867 ctrl | PHY_CT_LOOP);
1868 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1869 ctrl & ~PHY_CT_LOOP);
1872 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1873 bcom_check_link(hw, port);
1877 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1881 gma_write16(hw, port, GM_SMI_DATA, val);
1882 gma_write16(hw, port, GM_SMI_CTRL,
1883 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1884 for (i = 0; i < PHY_RETRIES; i++) {
1887 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1891 pr_warning("%s: phy write timeout\n", hw->dev[port]->name);
1895 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1899 gma_write16(hw, port, GM_SMI_CTRL,
1900 GM_SMI_CT_PHY_AD(hw->phy_addr)
1901 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1903 for (i = 0; i < PHY_RETRIES; i++) {
1905 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1911 *val = gma_read16(hw, port, GM_SMI_DATA);
1915 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1918 if (__gm_phy_read(hw, port, reg, &v))
1919 pr_warning("%s: phy read timeout\n", hw->dev[port]->name);
1923 /* Marvell Phy Initialization */
1924 static void yukon_init(struct skge_hw *hw, int port)
1926 struct skge_port *skge = netdev_priv(hw->dev[port]);
1927 u16 ctrl, ct1000, adv;
1929 if (skge->autoneg == AUTONEG_ENABLE) {
1930 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1932 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1933 PHY_M_EC_MAC_S_MSK);
1934 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1936 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1938 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1941 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1942 if (skge->autoneg == AUTONEG_DISABLE)
1943 ctrl &= ~PHY_CT_ANE;
1945 ctrl |= PHY_CT_RESET;
1946 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1952 if (skge->autoneg == AUTONEG_ENABLE) {
1954 if (skge->advertising & ADVERTISED_1000baseT_Full)
1955 ct1000 |= PHY_M_1000C_AFD;
1956 if (skge->advertising & ADVERTISED_1000baseT_Half)
1957 ct1000 |= PHY_M_1000C_AHD;
1958 if (skge->advertising & ADVERTISED_100baseT_Full)
1959 adv |= PHY_M_AN_100_FD;
1960 if (skge->advertising & ADVERTISED_100baseT_Half)
1961 adv |= PHY_M_AN_100_HD;
1962 if (skge->advertising & ADVERTISED_10baseT_Full)
1963 adv |= PHY_M_AN_10_FD;
1964 if (skge->advertising & ADVERTISED_10baseT_Half)
1965 adv |= PHY_M_AN_10_HD;
1967 /* Set Flow-control capabilities */
1968 adv |= phy_pause_map[skge->flow_control];
1970 if (skge->advertising & ADVERTISED_1000baseT_Full)
1971 adv |= PHY_M_AN_1000X_AFD;
1972 if (skge->advertising & ADVERTISED_1000baseT_Half)
1973 adv |= PHY_M_AN_1000X_AHD;
1975 adv |= fiber_pause_map[skge->flow_control];
1978 /* Restart Auto-negotiation */
1979 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1981 /* forced speed/duplex settings */
1982 ct1000 = PHY_M_1000C_MSE;
1984 if (skge->duplex == DUPLEX_FULL)
1985 ctrl |= PHY_CT_DUP_MD;
1987 switch (skge->speed) {
1989 ctrl |= PHY_CT_SP1000;
1992 ctrl |= PHY_CT_SP100;
1996 ctrl |= PHY_CT_RESET;
1999 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
2001 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
2002 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2004 /* Enable phy interrupt on autonegotiation complete (or link up) */
2005 if (skge->autoneg == AUTONEG_ENABLE)
2006 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
2008 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2011 static void yukon_reset(struct skge_hw *hw, int port)
2013 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
2014 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
2015 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
2016 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
2017 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
2019 gma_write16(hw, port, GM_RX_CTRL,
2020 gma_read16(hw, port, GM_RX_CTRL)
2021 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2024 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
2025 static int is_yukon_lite_a0(struct skge_hw *hw)
2030 if (hw->chip_id != CHIP_ID_YUKON)
2033 reg = skge_read32(hw, B2_FAR);
2034 skge_write8(hw, B2_FAR + 3, 0xff);
2035 ret = (skge_read8(hw, B2_FAR + 3) != 0);
2036 skge_write32(hw, B2_FAR, reg);
2040 static void yukon_mac_init(struct skge_hw *hw, int port)
2042 struct skge_port *skge = netdev_priv(hw->dev[port]);
2045 const u8 *addr = hw->dev[port]->dev_addr;
2047 /* WA code for COMA mode -- set PHY reset */
2048 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2049 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2050 reg = skge_read32(hw, B2_GP_IO);
2051 reg |= GP_DIR_9 | GP_IO_9;
2052 skge_write32(hw, B2_GP_IO, reg);
2056 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2057 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2059 /* WA code for COMA mode -- clear PHY reset */
2060 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2061 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2062 reg = skge_read32(hw, B2_GP_IO);
2065 skge_write32(hw, B2_GP_IO, reg);
2068 /* Set hardware config mode */
2069 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2070 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2071 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2073 /* Clear GMC reset */
2074 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2075 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2076 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2078 if (skge->autoneg == AUTONEG_DISABLE) {
2079 reg = GM_GPCR_AU_ALL_DIS;
2080 gma_write16(hw, port, GM_GP_CTRL,
2081 gma_read16(hw, port, GM_GP_CTRL) | reg);
2083 switch (skge->speed) {
2085 reg &= ~GM_GPCR_SPEED_100;
2086 reg |= GM_GPCR_SPEED_1000;
2089 reg &= ~GM_GPCR_SPEED_1000;
2090 reg |= GM_GPCR_SPEED_100;
2093 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2097 if (skge->duplex == DUPLEX_FULL)
2098 reg |= GM_GPCR_DUP_FULL;
2100 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2102 switch (skge->flow_control) {
2103 case FLOW_MODE_NONE:
2104 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2105 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2107 case FLOW_MODE_LOC_SEND:
2108 /* disable Rx flow-control */
2109 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2111 case FLOW_MODE_SYMMETRIC:
2112 case FLOW_MODE_SYM_OR_REM:
2113 /* enable Tx & Rx flow-control */
2117 gma_write16(hw, port, GM_GP_CTRL, reg);
2118 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2120 yukon_init(hw, port);
2123 reg = gma_read16(hw, port, GM_PHY_ADDR);
2124 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2126 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2127 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2128 gma_write16(hw, port, GM_PHY_ADDR, reg);
2130 /* transmit control */
2131 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2133 /* receive control reg: unicast + multicast + no FCS */
2134 gma_write16(hw, port, GM_RX_CTRL,
2135 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2137 /* transmit flow control */
2138 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2140 /* transmit parameter */
2141 gma_write16(hw, port, GM_TX_PARAM,
2142 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2143 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2144 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2146 /* configure the Serial Mode Register */
2147 reg = DATA_BLIND_VAL(DATA_BLIND_DEF)
2149 | IPG_DATA_VAL(IPG_DATA_DEF);
2151 if (hw->dev[port]->mtu > ETH_DATA_LEN)
2152 reg |= GM_SMOD_JUMBO_ENA;
2154 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2156 /* physical address: used for pause frames */
2157 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2158 /* virtual address for data */
2159 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2161 /* enable interrupt mask for counter overflows */
2162 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2163 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2164 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2166 /* Initialize Mac Fifo */
2168 /* Configure Rx MAC FIFO */
2169 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2170 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2172 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2173 if (is_yukon_lite_a0(hw))
2174 reg &= ~GMF_RX_F_FL_ON;
2176 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2177 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2179 * because Pause Packet Truncation in GMAC is not working
2180 * we have to increase the Flush Threshold to 64 bytes
2181 * in order to flush pause packets in Rx FIFO on Yukon-1
2183 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2185 /* Configure Tx MAC FIFO */
2186 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2187 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2190 /* Go into power down mode */
2191 static void yukon_suspend(struct skge_hw *hw, int port)
2195 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2196 ctrl |= PHY_M_PC_POL_R_DIS;
2197 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2199 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2200 ctrl |= PHY_CT_RESET;
2201 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2203 /* switch IEEE compatible power down mode on */
2204 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2205 ctrl |= PHY_CT_PDOWN;
2206 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2209 static void yukon_stop(struct skge_port *skge)
2211 struct skge_hw *hw = skge->hw;
2212 int port = skge->port;
2214 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2215 yukon_reset(hw, port);
2217 gma_write16(hw, port, GM_GP_CTRL,
2218 gma_read16(hw, port, GM_GP_CTRL)
2219 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2220 gma_read16(hw, port, GM_GP_CTRL);
2222 yukon_suspend(hw, port);
2224 /* set GPHY Control reset */
2225 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2226 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2229 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2231 struct skge_hw *hw = skge->hw;
2232 int port = skge->port;
2235 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2236 | gma_read32(hw, port, GM_TXO_OK_LO);
2237 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2238 | gma_read32(hw, port, GM_RXO_OK_LO);
2240 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2241 data[i] = gma_read32(hw, port,
2242 skge_stats[i].gma_offset);
2245 static void yukon_mac_intr(struct skge_hw *hw, int port)
2247 struct net_device *dev = hw->dev[port];
2248 struct skge_port *skge = netdev_priv(dev);
2249 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2251 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2252 "mac interrupt status 0x%x\n", status);
2254 if (status & GM_IS_RX_FF_OR) {
2255 ++dev->stats.rx_fifo_errors;
2256 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2259 if (status & GM_IS_TX_FF_UR) {
2260 ++dev->stats.tx_fifo_errors;
2261 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2266 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2268 switch (aux & PHY_M_PS_SPEED_MSK) {
2269 case PHY_M_PS_SPEED_1000:
2271 case PHY_M_PS_SPEED_100:
2278 static void yukon_link_up(struct skge_port *skge)
2280 struct skge_hw *hw = skge->hw;
2281 int port = skge->port;
2284 /* Enable Transmit FIFO Underrun */
2285 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2287 reg = gma_read16(hw, port, GM_GP_CTRL);
2288 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2289 reg |= GM_GPCR_DUP_FULL;
2292 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2293 gma_write16(hw, port, GM_GP_CTRL, reg);
2295 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2299 static void yukon_link_down(struct skge_port *skge)
2301 struct skge_hw *hw = skge->hw;
2302 int port = skge->port;
2305 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2306 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2307 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2309 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2310 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2311 ctrl |= PHY_M_AN_ASP;
2312 /* restore Asymmetric Pause bit */
2313 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2316 skge_link_down(skge);
2318 yukon_init(hw, port);
2321 static void yukon_phy_intr(struct skge_port *skge)
2323 struct skge_hw *hw = skge->hw;
2324 int port = skge->port;
2325 const char *reason = NULL;
2326 u16 istatus, phystat;
2328 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2329 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2331 netif_printk(skge, intr, KERN_DEBUG, skge->netdev,
2332 "phy interrupt status 0x%x 0x%x\n", istatus, phystat);
2334 if (istatus & PHY_M_IS_AN_COMPL) {
2335 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2337 reason = "remote fault";
2341 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2342 reason = "master/slave fault";
2346 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2347 reason = "speed/duplex";
2351 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2352 ? DUPLEX_FULL : DUPLEX_HALF;
2353 skge->speed = yukon_speed(hw, phystat);
2355 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2356 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2357 case PHY_M_PS_PAUSE_MSK:
2358 skge->flow_status = FLOW_STAT_SYMMETRIC;
2360 case PHY_M_PS_RX_P_EN:
2361 skge->flow_status = FLOW_STAT_REM_SEND;
2363 case PHY_M_PS_TX_P_EN:
2364 skge->flow_status = FLOW_STAT_LOC_SEND;
2367 skge->flow_status = FLOW_STAT_NONE;
2370 if (skge->flow_status == FLOW_STAT_NONE ||
2371 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2372 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2374 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2375 yukon_link_up(skge);
2379 if (istatus & PHY_M_IS_LSP_CHANGE)
2380 skge->speed = yukon_speed(hw, phystat);
2382 if (istatus & PHY_M_IS_DUP_CHANGE)
2383 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2384 if (istatus & PHY_M_IS_LST_CHANGE) {
2385 if (phystat & PHY_M_PS_LINK_UP)
2386 yukon_link_up(skge);
2388 yukon_link_down(skge);
2392 pr_err("%s: autonegotiation failed (%s)\n", skge->netdev->name, reason);
2394 /* XXX restart autonegotiation? */
2397 static void skge_phy_reset(struct skge_port *skge)
2399 struct skge_hw *hw = skge->hw;
2400 int port = skge->port;
2401 struct net_device *dev = hw->dev[port];
2403 netif_stop_queue(skge->netdev);
2404 netif_carrier_off(skge->netdev);
2406 spin_lock_bh(&hw->phy_lock);
2407 if (hw->chip_id == CHIP_ID_GENESIS) {
2408 genesis_reset(hw, port);
2409 genesis_mac_init(hw, port);
2411 yukon_reset(hw, port);
2412 yukon_init(hw, port);
2414 spin_unlock_bh(&hw->phy_lock);
2416 skge_set_multicast(dev);
2419 /* Basic MII support */
2420 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2422 struct mii_ioctl_data *data = if_mii(ifr);
2423 struct skge_port *skge = netdev_priv(dev);
2424 struct skge_hw *hw = skge->hw;
2425 int err = -EOPNOTSUPP;
2427 if (!netif_running(dev))
2428 return -ENODEV; /* Phy still in reset */
2432 data->phy_id = hw->phy_addr;
2437 spin_lock_bh(&hw->phy_lock);
2438 if (hw->chip_id == CHIP_ID_GENESIS)
2439 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2441 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2442 spin_unlock_bh(&hw->phy_lock);
2443 data->val_out = val;
2448 spin_lock_bh(&hw->phy_lock);
2449 if (hw->chip_id == CHIP_ID_GENESIS)
2450 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2453 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2455 spin_unlock_bh(&hw->phy_lock);
2461 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2467 end = start + len - 1;
2469 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2470 skge_write32(hw, RB_ADDR(q, RB_START), start);
2471 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2472 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2473 skge_write32(hw, RB_ADDR(q, RB_END), end);
2475 if (q == Q_R1 || q == Q_R2) {
2476 /* Set thresholds on receive queue's */
2477 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2479 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2482 /* Enable store & forward on Tx queue's because
2483 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2485 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2488 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2491 /* Setup Bus Memory Interface */
2492 static void skge_qset(struct skge_port *skge, u16 q,
2493 const struct skge_element *e)
2495 struct skge_hw *hw = skge->hw;
2496 u32 watermark = 0x600;
2497 u64 base = skge->dma + (e->desc - skge->mem);
2499 /* optimization to reduce window on 32bit/33mhz */
2500 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2503 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2504 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2505 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2506 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2509 static int skge_up(struct net_device *dev)
2511 struct skge_port *skge = netdev_priv(dev);
2512 struct skge_hw *hw = skge->hw;
2513 int port = skge->port;
2514 u32 chunk, ram_addr;
2515 size_t rx_size, tx_size;
2518 if (!is_valid_ether_addr(dev->dev_addr))
2521 netif_info(skge, ifup, skge->netdev, "enabling interface\n");
2523 if (dev->mtu > RX_BUF_SIZE)
2524 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2526 skge->rx_buf_size = RX_BUF_SIZE;
2529 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2530 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2531 skge->mem_size = tx_size + rx_size;
2532 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2536 BUG_ON(skge->dma & 7);
2538 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2539 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2544 memset(skge->mem, 0, skge->mem_size);
2546 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2550 err = skge_rx_fill(dev);
2554 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2555 skge->dma + rx_size);
2559 /* Initialize MAC */
2560 spin_lock_bh(&hw->phy_lock);
2561 if (hw->chip_id == CHIP_ID_GENESIS)
2562 genesis_mac_init(hw, port);
2564 yukon_mac_init(hw, port);
2565 spin_unlock_bh(&hw->phy_lock);
2567 /* Configure RAMbuffers - equally between ports and tx/rx */
2568 chunk = (hw->ram_size - hw->ram_offset) / (hw->ports * 2);
2569 ram_addr = hw->ram_offset + 2 * chunk * port;
2571 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2572 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2574 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2575 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2576 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2578 /* Start receiver BMU */
2580 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2581 skge_led(skge, LED_MODE_ON);
2583 spin_lock_irq(&hw->hw_lock);
2584 hw->intr_mask |= portmask[port];
2585 skge_write32(hw, B0_IMSK, hw->intr_mask);
2586 spin_unlock_irq(&hw->hw_lock);
2588 napi_enable(&skge->napi);
2592 skge_rx_clean(skge);
2593 kfree(skge->rx_ring.start);
2595 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2602 static void skge_rx_stop(struct skge_hw *hw, int port)
2604 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2605 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2606 RB_RST_SET|RB_DIS_OP_MD);
2607 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2610 static int skge_down(struct net_device *dev)
2612 struct skge_port *skge = netdev_priv(dev);
2613 struct skge_hw *hw = skge->hw;
2614 int port = skge->port;
2616 if (skge->mem == NULL)
2619 netif_info(skge, ifdown, skge->netdev, "disabling interface\n");
2621 netif_tx_disable(dev);
2623 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2624 del_timer_sync(&skge->link_timer);
2626 napi_disable(&skge->napi);
2627 netif_carrier_off(dev);
2629 spin_lock_irq(&hw->hw_lock);
2630 hw->intr_mask &= ~portmask[port];
2631 skge_write32(hw, B0_IMSK, hw->intr_mask);
2632 spin_unlock_irq(&hw->hw_lock);
2634 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2635 if (hw->chip_id == CHIP_ID_GENESIS)
2640 /* Stop transmitter */
2641 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2642 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2643 RB_RST_SET|RB_DIS_OP_MD);
2646 /* Disable Force Sync bit and Enable Alloc bit */
2647 skge_write8(hw, SK_REG(port, TXA_CTRL),
2648 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2650 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2651 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2652 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2654 /* Reset PCI FIFO */
2655 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2656 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2658 /* Reset the RAM Buffer async Tx queue */
2659 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2661 skge_rx_stop(hw, port);
2663 if (hw->chip_id == CHIP_ID_GENESIS) {
2664 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2665 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2667 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2668 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2671 skge_led(skge, LED_MODE_OFF);
2673 netif_tx_lock_bh(dev);
2675 netif_tx_unlock_bh(dev);
2677 skge_rx_clean(skge);
2679 kfree(skge->rx_ring.start);
2680 kfree(skge->tx_ring.start);
2681 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2686 static inline int skge_avail(const struct skge_ring *ring)
2689 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2690 + (ring->to_clean - ring->to_use) - 1;
2693 static netdev_tx_t skge_xmit_frame(struct sk_buff *skb,
2694 struct net_device *dev)
2696 struct skge_port *skge = netdev_priv(dev);
2697 struct skge_hw *hw = skge->hw;
2698 struct skge_element *e;
2699 struct skge_tx_desc *td;
2704 if (skb_padto(skb, ETH_ZLEN))
2705 return NETDEV_TX_OK;
2707 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2708 return NETDEV_TX_BUSY;
2710 e = skge->tx_ring.to_use;
2712 BUG_ON(td->control & BMU_OWN);
2714 len = skb_headlen(skb);
2715 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2716 dma_unmap_addr_set(e, mapaddr, map);
2717 dma_unmap_len_set(e, maplen, len);
2720 td->dma_hi = map >> 32;
2722 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2723 const int offset = skb_checksum_start_offset(skb);
2725 /* This seems backwards, but it is what the sk98lin
2726 * does. Looks like hardware is wrong?
2728 if (ipip_hdr(skb)->protocol == IPPROTO_UDP &&
2729 hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2730 control = BMU_TCP_CHECK;
2732 control = BMU_UDP_CHECK;
2735 td->csum_start = offset;
2736 td->csum_write = offset + skb->csum_offset;
2738 control = BMU_CHECK;
2740 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2741 control |= BMU_EOF | BMU_IRQ_EOF;
2743 struct skge_tx_desc *tf = td;
2745 control |= BMU_STFWD;
2746 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2747 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2749 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2750 frag->size, PCI_DMA_TODEVICE);
2755 BUG_ON(tf->control & BMU_OWN);
2758 tf->dma_hi = (u64) map >> 32;
2759 dma_unmap_addr_set(e, mapaddr, map);
2760 dma_unmap_len_set(e, maplen, frag->size);
2762 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2764 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2766 /* Make sure all the descriptors written */
2768 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2771 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2773 netif_printk(skge, tx_queued, KERN_DEBUG, skge->netdev,
2774 "tx queued, slot %td, len %d\n",
2775 e - skge->tx_ring.start, skb->len);
2777 skge->tx_ring.to_use = e->next;
2780 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2781 netdev_dbg(dev, "transmit queue full\n");
2782 netif_stop_queue(dev);
2785 return NETDEV_TX_OK;
2789 /* Free resources associated with this reing element */
2790 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2793 struct pci_dev *pdev = skge->hw->pdev;
2795 /* skb header vs. fragment */
2796 if (control & BMU_STF)
2797 pci_unmap_single(pdev, dma_unmap_addr(e, mapaddr),
2798 dma_unmap_len(e, maplen),
2801 pci_unmap_page(pdev, dma_unmap_addr(e, mapaddr),
2802 dma_unmap_len(e, maplen),
2805 if (control & BMU_EOF) {
2806 netif_printk(skge, tx_done, KERN_DEBUG, skge->netdev,
2807 "tx done slot %td\n", e - skge->tx_ring.start);
2809 dev_kfree_skb(e->skb);
2813 /* Free all buffers in transmit ring */
2814 static void skge_tx_clean(struct net_device *dev)
2816 struct skge_port *skge = netdev_priv(dev);
2817 struct skge_element *e;
2819 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2820 struct skge_tx_desc *td = e->desc;
2821 skge_tx_free(skge, e, td->control);
2825 skge->tx_ring.to_clean = e;
2828 static void skge_tx_timeout(struct net_device *dev)
2830 struct skge_port *skge = netdev_priv(dev);
2832 netif_printk(skge, timer, KERN_DEBUG, skge->netdev, "tx timeout\n");
2834 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2836 netif_wake_queue(dev);
2839 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2843 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2846 if (!netif_running(dev)) {
2862 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2864 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2868 crc = ether_crc_le(ETH_ALEN, addr);
2870 filter[bit/8] |= 1 << (bit%8);
2873 static void genesis_set_multicast(struct net_device *dev)
2875 struct skge_port *skge = netdev_priv(dev);
2876 struct skge_hw *hw = skge->hw;
2877 int port = skge->port;
2878 struct netdev_hw_addr *ha;
2882 mode = xm_read32(hw, port, XM_MODE);
2883 mode |= XM_MD_ENA_HASH;
2884 if (dev->flags & IFF_PROMISC)
2885 mode |= XM_MD_ENA_PROM;
2887 mode &= ~XM_MD_ENA_PROM;
2889 if (dev->flags & IFF_ALLMULTI)
2890 memset(filter, 0xff, sizeof(filter));
2892 memset(filter, 0, sizeof(filter));
2894 if (skge->flow_status == FLOW_STAT_REM_SEND ||
2895 skge->flow_status == FLOW_STAT_SYMMETRIC)
2896 genesis_add_filter(filter, pause_mc_addr);
2898 netdev_for_each_mc_addr(ha, dev)
2899 genesis_add_filter(filter, ha->addr);
2902 xm_write32(hw, port, XM_MODE, mode);
2903 xm_outhash(hw, port, XM_HSM, filter);
2906 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2908 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2909 filter[bit/8] |= 1 << (bit%8);
2912 static void yukon_set_multicast(struct net_device *dev)
2914 struct skge_port *skge = netdev_priv(dev);
2915 struct skge_hw *hw = skge->hw;
2916 int port = skge->port;
2917 struct netdev_hw_addr *ha;
2918 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND ||
2919 skge->flow_status == FLOW_STAT_SYMMETRIC);
2923 memset(filter, 0, sizeof(filter));
2925 reg = gma_read16(hw, port, GM_RX_CTRL);
2926 reg |= GM_RXCR_UCF_ENA;
2928 if (dev->flags & IFF_PROMISC) /* promiscuous */
2929 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2930 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2931 memset(filter, 0xff, sizeof(filter));
2932 else if (netdev_mc_empty(dev) && !rx_pause)/* no multicast */
2933 reg &= ~GM_RXCR_MCF_ENA;
2935 reg |= GM_RXCR_MCF_ENA;
2938 yukon_add_filter(filter, pause_mc_addr);
2940 netdev_for_each_mc_addr(ha, dev)
2941 yukon_add_filter(filter, ha->addr);
2945 gma_write16(hw, port, GM_MC_ADDR_H1,
2946 (u16)filter[0] | ((u16)filter[1] << 8));
2947 gma_write16(hw, port, GM_MC_ADDR_H2,
2948 (u16)filter[2] | ((u16)filter[3] << 8));
2949 gma_write16(hw, port, GM_MC_ADDR_H3,
2950 (u16)filter[4] | ((u16)filter[5] << 8));
2951 gma_write16(hw, port, GM_MC_ADDR_H4,
2952 (u16)filter[6] | ((u16)filter[7] << 8));
2954 gma_write16(hw, port, GM_RX_CTRL, reg);
2957 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2959 if (hw->chip_id == CHIP_ID_GENESIS)
2960 return status >> XMR_FS_LEN_SHIFT;
2962 return status >> GMR_FS_LEN_SHIFT;
2965 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2967 if (hw->chip_id == CHIP_ID_GENESIS)
2968 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2970 return (status & GMR_FS_ANY_ERR) ||
2971 (status & GMR_FS_RX_OK) == 0;
2974 static void skge_set_multicast(struct net_device *dev)
2976 struct skge_port *skge = netdev_priv(dev);
2977 struct skge_hw *hw = skge->hw;
2979 if (hw->chip_id == CHIP_ID_GENESIS)
2980 genesis_set_multicast(dev);
2982 yukon_set_multicast(dev);
2987 /* Get receive buffer from descriptor.
2988 * Handles copy of small buffers and reallocation failures
2990 static struct sk_buff *skge_rx_get(struct net_device *dev,
2991 struct skge_element *e,
2992 u32 control, u32 status, u16 csum)
2994 struct skge_port *skge = netdev_priv(dev);
2995 struct sk_buff *skb;
2996 u16 len = control & BMU_BBC;
2998 netif_printk(skge, rx_status, KERN_DEBUG, skge->netdev,
2999 "rx slot %td status 0x%x len %d\n",
3000 e - skge->rx_ring.start, status, len);
3002 if (len > skge->rx_buf_size)
3005 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
3008 if (bad_phy_status(skge->hw, status))
3011 if (phy_length(skge->hw, status) != len)
3014 if (len < RX_COPY_THRESHOLD) {
3015 skb = netdev_alloc_skb_ip_align(dev, len);
3019 pci_dma_sync_single_for_cpu(skge->hw->pdev,
3020 dma_unmap_addr(e, mapaddr),
3021 len, PCI_DMA_FROMDEVICE);
3022 skb_copy_from_linear_data(e->skb, skb->data, len);
3023 pci_dma_sync_single_for_device(skge->hw->pdev,
3024 dma_unmap_addr(e, mapaddr),
3025 len, PCI_DMA_FROMDEVICE);
3026 skge_rx_reuse(e, skge->rx_buf_size);
3028 struct sk_buff *nskb;
3030 nskb = netdev_alloc_skb_ip_align(dev, skge->rx_buf_size);
3034 pci_unmap_single(skge->hw->pdev,
3035 dma_unmap_addr(e, mapaddr),
3036 dma_unmap_len(e, maplen),
3037 PCI_DMA_FROMDEVICE);
3039 prefetch(skb->data);
3040 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
3045 if (dev->features & NETIF_F_RXCSUM) {
3047 skb->ip_summed = CHECKSUM_COMPLETE;
3050 skb->protocol = eth_type_trans(skb, dev);
3055 netif_printk(skge, rx_err, KERN_DEBUG, skge->netdev,
3056 "rx err, slot %td control 0x%x status 0x%x\n",
3057 e - skge->rx_ring.start, control, status);
3059 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
3060 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
3061 dev->stats.rx_length_errors++;
3062 if (status & XMR_FS_FRA_ERR)
3063 dev->stats.rx_frame_errors++;
3064 if (status & XMR_FS_FCS_ERR)
3065 dev->stats.rx_crc_errors++;
3067 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3068 dev->stats.rx_length_errors++;
3069 if (status & GMR_FS_FRAGMENT)
3070 dev->stats.rx_frame_errors++;
3071 if (status & GMR_FS_CRC_ERR)
3072 dev->stats.rx_crc_errors++;
3076 skge_rx_reuse(e, skge->rx_buf_size);
3080 /* Free all buffers in Tx ring which are no longer owned by device */
3081 static void skge_tx_done(struct net_device *dev)
3083 struct skge_port *skge = netdev_priv(dev);
3084 struct skge_ring *ring = &skge->tx_ring;
3085 struct skge_element *e;
3087 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3089 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3090 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3092 if (control & BMU_OWN)
3095 skge_tx_free(skge, e, control);
3097 skge->tx_ring.to_clean = e;
3099 /* Can run lockless until we need to synchronize to restart queue. */
3102 if (unlikely(netif_queue_stopped(dev) &&
3103 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3105 if (unlikely(netif_queue_stopped(dev) &&
3106 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3107 netif_wake_queue(dev);
3110 netif_tx_unlock(dev);
3114 static int skge_poll(struct napi_struct *napi, int to_do)
3116 struct skge_port *skge = container_of(napi, struct skge_port, napi);
3117 struct net_device *dev = skge->netdev;
3118 struct skge_hw *hw = skge->hw;
3119 struct skge_ring *ring = &skge->rx_ring;
3120 struct skge_element *e;
3125 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3127 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3128 struct skge_rx_desc *rd = e->desc;
3129 struct sk_buff *skb;
3133 control = rd->control;
3134 if (control & BMU_OWN)
3137 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3139 napi_gro_receive(napi, skb);
3145 /* restart receiver */
3147 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3149 if (work_done < to_do) {
3150 unsigned long flags;
3152 napi_gro_flush(napi);
3153 spin_lock_irqsave(&hw->hw_lock, flags);
3154 __napi_complete(napi);
3155 hw->intr_mask |= napimask[skge->port];
3156 skge_write32(hw, B0_IMSK, hw->intr_mask);
3157 skge_read32(hw, B0_IMSK);
3158 spin_unlock_irqrestore(&hw->hw_lock, flags);
3164 /* Parity errors seem to happen when Genesis is connected to a switch
3165 * with no other ports present. Heartbeat error??
3167 static void skge_mac_parity(struct skge_hw *hw, int port)
3169 struct net_device *dev = hw->dev[port];
3171 ++dev->stats.tx_heartbeat_errors;
3173 if (hw->chip_id == CHIP_ID_GENESIS)
3174 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3177 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3178 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3179 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3180 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3183 static void skge_mac_intr(struct skge_hw *hw, int port)
3185 if (hw->chip_id == CHIP_ID_GENESIS)
3186 genesis_mac_intr(hw, port);
3188 yukon_mac_intr(hw, port);
3191 /* Handle device specific framing and timeout interrupts */
3192 static void skge_error_irq(struct skge_hw *hw)
3194 struct pci_dev *pdev = hw->pdev;
3195 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3197 if (hw->chip_id == CHIP_ID_GENESIS) {
3198 /* clear xmac errors */
3199 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3200 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3201 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3202 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3204 /* Timestamp (unused) overflow */
3205 if (hwstatus & IS_IRQ_TIST_OV)
3206 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3209 if (hwstatus & IS_RAM_RD_PAR) {
3210 dev_err(&pdev->dev, "Ram read data parity error\n");
3211 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3214 if (hwstatus & IS_RAM_WR_PAR) {
3215 dev_err(&pdev->dev, "Ram write data parity error\n");
3216 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3219 if (hwstatus & IS_M1_PAR_ERR)
3220 skge_mac_parity(hw, 0);
3222 if (hwstatus & IS_M2_PAR_ERR)
3223 skge_mac_parity(hw, 1);
3225 if (hwstatus & IS_R1_PAR_ERR) {
3226 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3228 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3231 if (hwstatus & IS_R2_PAR_ERR) {
3232 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3234 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3237 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3238 u16 pci_status, pci_cmd;
3240 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3241 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3243 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3244 pci_cmd, pci_status);
3246 /* Write the error bits back to clear them. */
3247 pci_status &= PCI_STATUS_ERROR_BITS;
3248 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3249 pci_write_config_word(pdev, PCI_COMMAND,
3250 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3251 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3252 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3254 /* if error still set then just ignore it */
3255 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3256 if (hwstatus & IS_IRQ_STAT) {
3257 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3258 hw->intr_mask &= ~IS_HW_ERR;
3264 * Interrupt from PHY are handled in tasklet (softirq)
3265 * because accessing phy registers requires spin wait which might
3266 * cause excess interrupt latency.
3268 static void skge_extirq(unsigned long arg)
3270 struct skge_hw *hw = (struct skge_hw *) arg;
3273 for (port = 0; port < hw->ports; port++) {
3274 struct net_device *dev = hw->dev[port];
3276 if (netif_running(dev)) {
3277 struct skge_port *skge = netdev_priv(dev);
3279 spin_lock(&hw->phy_lock);
3280 if (hw->chip_id != CHIP_ID_GENESIS)
3281 yukon_phy_intr(skge);
3282 else if (hw->phy_type == SK_PHY_BCOM)
3283 bcom_phy_intr(skge);
3284 spin_unlock(&hw->phy_lock);
3288 spin_lock_irq(&hw->hw_lock);
3289 hw->intr_mask |= IS_EXT_REG;
3290 skge_write32(hw, B0_IMSK, hw->intr_mask);
3291 skge_read32(hw, B0_IMSK);
3292 spin_unlock_irq(&hw->hw_lock);
3295 static irqreturn_t skge_intr(int irq, void *dev_id)
3297 struct skge_hw *hw = dev_id;
3301 spin_lock(&hw->hw_lock);
3302 /* Reading this register masks IRQ */
3303 status = skge_read32(hw, B0_SP_ISRC);
3304 if (status == 0 || status == ~0)
3308 status &= hw->intr_mask;
3309 if (status & IS_EXT_REG) {
3310 hw->intr_mask &= ~IS_EXT_REG;
3311 tasklet_schedule(&hw->phy_task);
3314 if (status & (IS_XA1_F|IS_R1_F)) {
3315 struct skge_port *skge = netdev_priv(hw->dev[0]);
3316 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3317 napi_schedule(&skge->napi);
3320 if (status & IS_PA_TO_TX1)
3321 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3323 if (status & IS_PA_TO_RX1) {
3324 ++hw->dev[0]->stats.rx_over_errors;
3325 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3329 if (status & IS_MAC1)
3330 skge_mac_intr(hw, 0);
3333 struct skge_port *skge = netdev_priv(hw->dev[1]);
3335 if (status & (IS_XA2_F|IS_R2_F)) {
3336 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3337 napi_schedule(&skge->napi);
3340 if (status & IS_PA_TO_RX2) {
3341 ++hw->dev[1]->stats.rx_over_errors;
3342 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3345 if (status & IS_PA_TO_TX2)
3346 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3348 if (status & IS_MAC2)
3349 skge_mac_intr(hw, 1);
3352 if (status & IS_HW_ERR)
3355 skge_write32(hw, B0_IMSK, hw->intr_mask);
3356 skge_read32(hw, B0_IMSK);
3358 spin_unlock(&hw->hw_lock);
3360 return IRQ_RETVAL(handled);
3363 #ifdef CONFIG_NET_POLL_CONTROLLER
3364 static void skge_netpoll(struct net_device *dev)
3366 struct skge_port *skge = netdev_priv(dev);
3368 disable_irq(dev->irq);
3369 skge_intr(dev->irq, skge->hw);
3370 enable_irq(dev->irq);
3374 static int skge_set_mac_address(struct net_device *dev, void *p)
3376 struct skge_port *skge = netdev_priv(dev);
3377 struct skge_hw *hw = skge->hw;
3378 unsigned port = skge->port;
3379 const struct sockaddr *addr = p;
3382 if (!is_valid_ether_addr(addr->sa_data))
3383 return -EADDRNOTAVAIL;
3385 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3387 if (!netif_running(dev)) {
3388 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3389 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3392 spin_lock_bh(&hw->phy_lock);
3393 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3394 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3396 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3397 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3399 if (hw->chip_id == CHIP_ID_GENESIS)
3400 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3402 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3403 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3406 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3407 spin_unlock_bh(&hw->phy_lock);
3413 static const struct {
3417 { CHIP_ID_GENESIS, "Genesis" },
3418 { CHIP_ID_YUKON, "Yukon" },
3419 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3420 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3423 static const char *skge_board_name(const struct skge_hw *hw)
3426 static char buf[16];
3428 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3429 if (skge_chips[i].id == hw->chip_id)
3430 return skge_chips[i].name;
3432 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3438 * Setup the board data structure, but don't bring up
3441 static int skge_reset(struct skge_hw *hw)
3444 u16 ctst, pci_status;
3445 u8 t8, mac_cfg, pmd_type;
3448 ctst = skge_read16(hw, B0_CTST);
3451 skge_write8(hw, B0_CTST, CS_RST_SET);
3452 skge_write8(hw, B0_CTST, CS_RST_CLR);
3454 /* clear PCI errors, if any */
3455 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3456 skge_write8(hw, B2_TST_CTRL2, 0);
3458 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3459 pci_write_config_word(hw->pdev, PCI_STATUS,
3460 pci_status | PCI_STATUS_ERROR_BITS);
3461 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3462 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3464 /* restore CLK_RUN bits (for Yukon-Lite) */
3465 skge_write16(hw, B0_CTST,
3466 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3468 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3469 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3470 pmd_type = skge_read8(hw, B2_PMD_TYP);
3471 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3473 switch (hw->chip_id) {
3474 case CHIP_ID_GENESIS:
3475 switch (hw->phy_type) {
3477 hw->phy_addr = PHY_ADDR_XMAC;
3480 hw->phy_addr = PHY_ADDR_BCOM;
3483 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3490 case CHIP_ID_YUKON_LITE:
3491 case CHIP_ID_YUKON_LP:
3492 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3495 hw->phy_addr = PHY_ADDR_MARV;
3499 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3504 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3505 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3506 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3508 /* read the adapters RAM size */
3509 t8 = skge_read8(hw, B2_E_0);
3510 if (hw->chip_id == CHIP_ID_GENESIS) {
3512 /* special case: 4 x 64k x 36, offset = 0x80000 */
3513 hw->ram_size = 0x100000;
3514 hw->ram_offset = 0x80000;
3516 hw->ram_size = t8 * 512;
3518 hw->ram_size = 0x20000;
3520 hw->ram_size = t8 * 4096;
3522 hw->intr_mask = IS_HW_ERR;
3524 /* Use PHY IRQ for all but fiber based Genesis board */
3525 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3526 hw->intr_mask |= IS_EXT_REG;
3528 if (hw->chip_id == CHIP_ID_GENESIS)
3531 /* switch power to VCC (WA for VAUX problem) */
3532 skge_write8(hw, B0_POWER_CTRL,
3533 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3535 /* avoid boards with stuck Hardware error bits */
3536 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3537 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3538 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3539 hw->intr_mask &= ~IS_HW_ERR;
3542 /* Clear PHY COMA */
3543 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3544 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, ®);
3545 reg &= ~PCI_PHY_COMA;
3546 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3547 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3550 for (i = 0; i < hw->ports; i++) {
3551 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3552 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3556 /* turn off hardware timer (unused) */
3557 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3558 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3559 skge_write8(hw, B0_LED, LED_STAT_ON);
3561 /* enable the Tx Arbiters */
3562 for (i = 0; i < hw->ports; i++)
3563 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3565 /* Initialize ram interface */
3566 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3568 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3569 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3570 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3571 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3572 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3573 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3574 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3575 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3576 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3577 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3578 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3579 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3581 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3583 /* Set interrupt moderation for Transmit only
3584 * Receive interrupts avoided by NAPI
3586 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3587 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3588 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3590 skge_write32(hw, B0_IMSK, hw->intr_mask);
3592 for (i = 0; i < hw->ports; i++) {
3593 if (hw->chip_id == CHIP_ID_GENESIS)
3594 genesis_reset(hw, i);
3603 #ifdef CONFIG_SKGE_DEBUG
3605 static struct dentry *skge_debug;
3607 static int skge_debug_show(struct seq_file *seq, void *v)
3609 struct net_device *dev = seq->private;
3610 const struct skge_port *skge = netdev_priv(dev);
3611 const struct skge_hw *hw = skge->hw;
3612 const struct skge_element *e;
3614 if (!netif_running(dev))
3617 seq_printf(seq, "IRQ src=%x mask=%x\n", skge_read32(hw, B0_ISRC),
3618 skge_read32(hw, B0_IMSK));
3620 seq_printf(seq, "Tx Ring: (%d)\n", skge_avail(&skge->tx_ring));
3621 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
3622 const struct skge_tx_desc *t = e->desc;
3623 seq_printf(seq, "%#x dma=%#x%08x %#x csum=%#x/%x/%x\n",
3624 t->control, t->dma_hi, t->dma_lo, t->status,
3625 t->csum_offs, t->csum_write, t->csum_start);
3628 seq_printf(seq, "\nRx Ring:\n");
3629 for (e = skge->rx_ring.to_clean; ; e = e->next) {
3630 const struct skge_rx_desc *r = e->desc;
3632 if (r->control & BMU_OWN)
3635 seq_printf(seq, "%#x dma=%#x%08x %#x %#x csum=%#x/%x\n",
3636 r->control, r->dma_hi, r->dma_lo, r->status,
3637 r->timestamp, r->csum1, r->csum1_start);
3643 static int skge_debug_open(struct inode *inode, struct file *file)
3645 return single_open(file, skge_debug_show, inode->i_private);
3648 static const struct file_operations skge_debug_fops = {
3649 .owner = THIS_MODULE,
3650 .open = skge_debug_open,
3652 .llseek = seq_lseek,
3653 .release = single_release,
3657 * Use network device events to create/remove/rename
3658 * debugfs file entries
3660 static int skge_device_event(struct notifier_block *unused,
3661 unsigned long event, void *ptr)
3663 struct net_device *dev = ptr;
3664 struct skge_port *skge;
3667 if (dev->netdev_ops->ndo_open != &skge_up || !skge_debug)
3670 skge = netdev_priv(dev);
3672 case NETDEV_CHANGENAME:
3673 if (skge->debugfs) {
3674 d = debugfs_rename(skge_debug, skge->debugfs,
3675 skge_debug, dev->name);
3679 netdev_info(dev, "rename failed\n");
3680 debugfs_remove(skge->debugfs);
3685 case NETDEV_GOING_DOWN:
3686 if (skge->debugfs) {
3687 debugfs_remove(skge->debugfs);
3688 skge->debugfs = NULL;
3693 d = debugfs_create_file(dev->name, S_IRUGO,
3696 if (!d || IS_ERR(d))
3697 netdev_info(dev, "debugfs create failed\n");
3707 static struct notifier_block skge_notifier = {
3708 .notifier_call = skge_device_event,
3712 static __init void skge_debug_init(void)
3716 ent = debugfs_create_dir("skge", NULL);
3717 if (!ent || IS_ERR(ent)) {
3718 pr_info("debugfs create directory failed\n");
3723 register_netdevice_notifier(&skge_notifier);
3726 static __exit void skge_debug_cleanup(void)
3729 unregister_netdevice_notifier(&skge_notifier);
3730 debugfs_remove(skge_debug);
3736 #define skge_debug_init()
3737 #define skge_debug_cleanup()
3740 static const struct net_device_ops skge_netdev_ops = {
3741 .ndo_open = skge_up,
3742 .ndo_stop = skge_down,
3743 .ndo_start_xmit = skge_xmit_frame,
3744 .ndo_do_ioctl = skge_ioctl,
3745 .ndo_get_stats = skge_get_stats,
3746 .ndo_tx_timeout = skge_tx_timeout,
3747 .ndo_change_mtu = skge_change_mtu,
3748 .ndo_validate_addr = eth_validate_addr,
3749 .ndo_set_multicast_list = skge_set_multicast,
3750 .ndo_set_mac_address = skge_set_mac_address,
3751 #ifdef CONFIG_NET_POLL_CONTROLLER
3752 .ndo_poll_controller = skge_netpoll,
3757 /* Initialize network device */
3758 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3761 struct skge_port *skge;
3762 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3765 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3769 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3770 dev->netdev_ops = &skge_netdev_ops;
3771 dev->ethtool_ops = &skge_ethtool_ops;
3772 dev->watchdog_timeo = TX_WATCHDOG;
3773 dev->irq = hw->pdev->irq;
3776 dev->features |= NETIF_F_HIGHDMA;
3778 skge = netdev_priv(dev);
3779 netif_napi_add(dev, &skge->napi, skge_poll, NAPI_WEIGHT);
3782 skge->msg_enable = netif_msg_init(debug, default_msg);
3784 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3785 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3787 /* Auto speed and flow control */
3788 skge->autoneg = AUTONEG_ENABLE;
3789 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3792 skge->advertising = skge_supported_modes(hw);
3794 if (device_can_wakeup(&hw->pdev->dev)) {
3795 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3796 device_set_wakeup_enable(&hw->pdev->dev, skge->wol);
3799 hw->dev[port] = dev;
3803 /* Only used for Genesis XMAC */
3804 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3806 if (hw->chip_id != CHIP_ID_GENESIS) {
3807 dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
3809 dev->features |= dev->hw_features;
3812 /* read the mac address */
3813 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3814 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3819 static void __devinit skge_show_addr(struct net_device *dev)
3821 const struct skge_port *skge = netdev_priv(dev);
3823 netif_info(skge, probe, skge->netdev, "addr %pM\n", dev->dev_addr);
3826 static int only_32bit_dma;
3828 static int __devinit skge_probe(struct pci_dev *pdev,
3829 const struct pci_device_id *ent)
3831 struct net_device *dev, *dev1;
3833 int err, using_dac = 0;
3835 err = pci_enable_device(pdev);
3837 dev_err(&pdev->dev, "cannot enable PCI device\n");
3841 err = pci_request_regions(pdev, DRV_NAME);
3843 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3844 goto err_out_disable_pdev;
3847 pci_set_master(pdev);
3849 if (!only_32bit_dma && !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
3851 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3852 } else if (!(err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)))) {
3854 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3858 dev_err(&pdev->dev, "no usable DMA configuration\n");
3859 goto err_out_free_regions;
3863 /* byte swap descriptors in hardware */
3867 pci_read_config_dword(pdev, PCI_DEV_REG2, ®);
3868 reg |= PCI_REV_DESC;
3869 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3874 /* space for skge@pci:0000:04:00.0 */
3875 hw = kzalloc(sizeof(*hw) + strlen(DRV_NAME "@pci:")
3876 + strlen(pci_name(pdev)) + 1, GFP_KERNEL);
3878 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3879 goto err_out_free_regions;
3881 sprintf(hw->irq_name, DRV_NAME "@pci:%s", pci_name(pdev));
3884 spin_lock_init(&hw->hw_lock);
3885 spin_lock_init(&hw->phy_lock);
3886 tasklet_init(&hw->phy_task, skge_extirq, (unsigned long) hw);
3888 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3890 dev_err(&pdev->dev, "cannot map device registers\n");
3891 goto err_out_free_hw;
3894 err = skge_reset(hw);
3896 goto err_out_iounmap;
3898 pr_info("%s addr 0x%llx irq %d chip %s rev %d\n",
3900 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3901 skge_board_name(hw), hw->chip_rev);
3903 dev = skge_devinit(hw, 0, using_dac);
3905 goto err_out_led_off;
3907 /* Some motherboards are broken and has zero in ROM. */
3908 if (!is_valid_ether_addr(dev->dev_addr))
3909 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3911 err = register_netdev(dev);
3913 dev_err(&pdev->dev, "cannot register net device\n");
3914 goto err_out_free_netdev;
3917 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, hw->irq_name, hw);
3919 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3920 dev->name, pdev->irq);
3921 goto err_out_unregister;
3923 skge_show_addr(dev);
3925 if (hw->ports > 1) {
3926 dev1 = skge_devinit(hw, 1, using_dac);
3927 if (dev1 && register_netdev(dev1) == 0)
3928 skge_show_addr(dev1);
3930 /* Failure to register second port need not be fatal */
3931 dev_warn(&pdev->dev, "register of second port failed\n");
3938 pci_set_drvdata(pdev, hw);
3943 unregister_netdev(dev);
3944 err_out_free_netdev:
3947 skge_write16(hw, B0_LED, LED_STAT_OFF);
3952 err_out_free_regions:
3953 pci_release_regions(pdev);
3954 err_out_disable_pdev:
3955 pci_disable_device(pdev);
3956 pci_set_drvdata(pdev, NULL);
3961 static void __devexit skge_remove(struct pci_dev *pdev)
3963 struct skge_hw *hw = pci_get_drvdata(pdev);
3964 struct net_device *dev0, *dev1;
3971 unregister_netdev(dev1);
3973 unregister_netdev(dev0);
3975 tasklet_disable(&hw->phy_task);
3977 spin_lock_irq(&hw->hw_lock);
3979 skge_write32(hw, B0_IMSK, 0);
3980 skge_read32(hw, B0_IMSK);
3981 spin_unlock_irq(&hw->hw_lock);
3983 skge_write16(hw, B0_LED, LED_STAT_OFF);
3984 skge_write8(hw, B0_CTST, CS_RST_SET);
3986 free_irq(pdev->irq, hw);
3987 pci_release_regions(pdev);
3988 pci_disable_device(pdev);
3995 pci_set_drvdata(pdev, NULL);
3999 static int skge_suspend(struct device *dev)
4001 struct pci_dev *pdev = to_pci_dev(dev);
4002 struct skge_hw *hw = pci_get_drvdata(pdev);
4008 for (i = 0; i < hw->ports; i++) {
4009 struct net_device *dev = hw->dev[i];
4010 struct skge_port *skge = netdev_priv(dev);
4012 if (netif_running(dev))
4016 skge_wol_init(skge);
4019 skge_write32(hw, B0_IMSK, 0);
4024 static int skge_resume(struct device *dev)
4026 struct pci_dev *pdev = to_pci_dev(dev);
4027 struct skge_hw *hw = pci_get_drvdata(pdev);
4033 err = skge_reset(hw);
4037 for (i = 0; i < hw->ports; i++) {
4038 struct net_device *dev = hw->dev[i];
4040 if (netif_running(dev)) {
4044 netdev_err(dev, "could not up: %d\n", err);
4054 static SIMPLE_DEV_PM_OPS(skge_pm_ops, skge_suspend, skge_resume);
4055 #define SKGE_PM_OPS (&skge_pm_ops)
4059 #define SKGE_PM_OPS NULL
4062 static void skge_shutdown(struct pci_dev *pdev)
4064 struct skge_hw *hw = pci_get_drvdata(pdev);
4070 for (i = 0; i < hw->ports; i++) {
4071 struct net_device *dev = hw->dev[i];
4072 struct skge_port *skge = netdev_priv(dev);
4075 skge_wol_init(skge);
4078 pci_wake_from_d3(pdev, device_may_wakeup(&pdev->dev));
4079 pci_set_power_state(pdev, PCI_D3hot);
4082 static struct pci_driver skge_driver = {
4084 .id_table = skge_id_table,
4085 .probe = skge_probe,
4086 .remove = __devexit_p(skge_remove),
4087 .shutdown = skge_shutdown,
4088 .driver.pm = SKGE_PM_OPS,
4091 static struct dmi_system_id skge_32bit_dma_boards[] = {
4093 .ident = "Gigabyte nForce boards",
4095 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co"),
4096 DMI_MATCH(DMI_BOARD_NAME, "nForce"),
4102 static int __init skge_init_module(void)
4104 if (dmi_check_system(skge_32bit_dma_boards))
4107 return pci_register_driver(&skge_driver);
4110 static void __exit skge_cleanup_module(void)
4112 pci_unregister_driver(&skge_driver);
4113 skge_debug_cleanup();
4116 module_init(skge_init_module);
4117 module_exit(skge_cleanup_module);