1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2007-2008 Solarflare Communications Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published
7 * by the Free Software Foundation, incorporated herein by reference.
10 #include <linux/delay.h>
11 #include <linux/rtnetlink.h>
12 #include <linux/seq_file.h>
17 #include "falcon_hwdefs.h"
19 #include "workarounds.h"
22 /* We expect these MMDs to be in the package. SFT9001 also has a
23 * clause 22 extension MMD, but since it doesn't have all the generic
24 * MMD registers it is pointless to include it here.
26 #define TENXPRESS_REQUIRED_DEVS (MDIO_DEVS_PMAPMD | \
31 #define SFX7101_LOOPBACKS ((1 << LOOPBACK_PHYXS) | \
32 (1 << LOOPBACK_PCS) | \
33 (1 << LOOPBACK_PMAPMD) | \
34 (1 << LOOPBACK_NETWORK))
36 #define SFT9001_LOOPBACKS ((1 << LOOPBACK_GPHY) | \
37 (1 << LOOPBACK_PHYXS) | \
38 (1 << LOOPBACK_PCS) | \
39 (1 << LOOPBACK_PMAPMD) | \
40 (1 << LOOPBACK_NETWORK))
42 /* We complain if we fail to see the link partner as 10G capable this many
43 * times in a row (must be > 1 as sampling the autoneg. registers is racy)
45 #define MAX_BAD_LP_TRIES (5)
48 #define PMA_PMD_LASI_CTRL 36866
49 #define PMA_PMD_LASI_STATUS 36869
50 #define PMA_PMD_LS_ALARM_LBN 0
51 #define PMA_PMD_LS_ALARM_WIDTH 1
52 #define PMA_PMD_TX_ALARM_LBN 1
53 #define PMA_PMD_TX_ALARM_WIDTH 1
54 #define PMA_PMD_RX_ALARM_LBN 2
55 #define PMA_PMD_RX_ALARM_WIDTH 1
56 #define PMA_PMD_AN_ALARM_LBN 3
57 #define PMA_PMD_AN_ALARM_WIDTH 1
59 /* Extended control register */
60 #define PMA_PMD_XCONTROL_REG 49152
61 #define PMA_PMD_EXT_GMII_EN_LBN 1
62 #define PMA_PMD_EXT_GMII_EN_WIDTH 1
63 #define PMA_PMD_EXT_CLK_OUT_LBN 2
64 #define PMA_PMD_EXT_CLK_OUT_WIDTH 1
65 #define PMA_PMD_LNPGA_POWERDOWN_LBN 8 /* SFX7101 only */
66 #define PMA_PMD_LNPGA_POWERDOWN_WIDTH 1
67 #define PMA_PMD_EXT_CLK312_LBN 8 /* SFT9001 only */
68 #define PMA_PMD_EXT_CLK312_WIDTH 1
69 #define PMA_PMD_EXT_LPOWER_LBN 12
70 #define PMA_PMD_EXT_LPOWER_WIDTH 1
71 #define PMA_PMD_EXT_ROBUST_LBN 14
72 #define PMA_PMD_EXT_ROBUST_WIDTH 1
73 #define PMA_PMD_EXT_SSR_LBN 15
74 #define PMA_PMD_EXT_SSR_WIDTH 1
76 /* extended status register */
77 #define PMA_PMD_XSTATUS_REG 49153
78 #define PMA_PMD_XSTAT_FLP_LBN (12)
80 /* LED control register */
81 #define PMA_PMD_LED_CTRL_REG 49159
82 #define PMA_PMA_LED_ACTIVITY_LBN (3)
84 /* LED function override register */
85 #define PMA_PMD_LED_OVERR_REG 49161
86 /* Bit positions for different LEDs (there are more but not wired on SFE4001)*/
87 #define PMA_PMD_LED_LINK_LBN (0)
88 #define PMA_PMD_LED_SPEED_LBN (2)
89 #define PMA_PMD_LED_TX_LBN (4)
90 #define PMA_PMD_LED_RX_LBN (6)
91 /* Override settings */
92 #define PMA_PMD_LED_AUTO (0) /* H/W control */
93 #define PMA_PMD_LED_ON (1)
94 #define PMA_PMD_LED_OFF (2)
95 #define PMA_PMD_LED_FLASH (3)
96 #define PMA_PMD_LED_MASK 3
97 /* All LEDs under hardware control */
98 #define PMA_PMD_LED_FULL_AUTO (0)
99 /* Green and Amber under hardware control, Red off */
100 #define PMA_PMD_LED_DEFAULT (PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN)
102 #define PMA_PMD_SPEED_ENABLE_REG 49192
103 #define PMA_PMD_100TX_ADV_LBN 1
104 #define PMA_PMD_100TX_ADV_WIDTH 1
105 #define PMA_PMD_1000T_ADV_LBN 2
106 #define PMA_PMD_1000T_ADV_WIDTH 1
107 #define PMA_PMD_10000T_ADV_LBN 3
108 #define PMA_PMD_10000T_ADV_WIDTH 1
109 #define PMA_PMD_SPEED_LBN 4
110 #define PMA_PMD_SPEED_WIDTH 4
112 /* Cable diagnostics - SFT9001 only */
113 #define PMA_PMD_CDIAG_CTRL_REG 49213
114 #define CDIAG_CTRL_IMMED_LBN 15
115 #define CDIAG_CTRL_BRK_LINK_LBN 12
116 #define CDIAG_CTRL_IN_PROG_LBN 11
117 #define CDIAG_CTRL_LEN_UNIT_LBN 10
118 #define CDIAG_CTRL_LEN_METRES 1
119 #define PMA_PMD_CDIAG_RES_REG 49174
120 #define CDIAG_RES_A_LBN 12
121 #define CDIAG_RES_B_LBN 8
122 #define CDIAG_RES_C_LBN 4
123 #define CDIAG_RES_D_LBN 0
124 #define CDIAG_RES_WIDTH 4
125 #define CDIAG_RES_OPEN 2
126 #define CDIAG_RES_OK 1
127 #define CDIAG_RES_INVALID 0
128 /* Set of 4 registers for pairs A-D */
129 #define PMA_PMD_CDIAG_LEN_REG 49175
131 /* Serdes control registers - SFT9001 only */
132 #define PMA_PMD_CSERDES_CTRL_REG 64258
133 /* Set the 156.25 MHz output to 312.5 MHz to drive Falcon's XMAC */
134 #define PMA_PMD_CSERDES_DEFAULT 0x000f
136 /* Misc register defines - SFX7101 only */
137 #define PCS_CLOCK_CTRL_REG 55297
138 #define PLL312_RST_N_LBN 2
140 #define PCS_SOFT_RST2_REG 55302
141 #define SERDES_RST_N_LBN 13
142 #define XGXS_RST_N_LBN 12
144 #define PCS_TEST_SELECT_REG 55303 /* PRM 10.5.8 */
145 #define CLK312_EN_LBN 3
147 /* PHYXS registers */
148 #define PHYXS_XCONTROL_REG 49152
149 #define PHYXS_RESET_LBN 15
150 #define PHYXS_RESET_WIDTH 1
152 #define PHYXS_TEST1 (49162)
153 #define LOOPBACK_NEAR_LBN (8)
154 #define LOOPBACK_NEAR_WIDTH (1)
156 /* Boot status register */
157 #define PCS_BOOT_STATUS_REG 53248
158 #define PCS_BOOT_FATAL_ERROR_LBN 0
159 #define PCS_BOOT_PROGRESS_LBN 1
160 #define PCS_BOOT_PROGRESS_WIDTH 2
161 #define PCS_BOOT_PROGRESS_INIT 0
162 #define PCS_BOOT_PROGRESS_WAIT_MDIO 1
163 #define PCS_BOOT_PROGRESS_CHECKSUM 2
164 #define PCS_BOOT_PROGRESS_JUMP 3
165 #define PCS_BOOT_DOWNLOAD_WAIT_LBN 3
166 #define PCS_BOOT_CODE_STARTED_LBN 4
168 /* 100M/1G PHY registers */
169 #define GPHY_XCONTROL_REG 49152
170 #define GPHY_ISOLATE_LBN 10
171 #define GPHY_ISOLATE_WIDTH 1
172 #define GPHY_DUPLEX_LBN 8
173 #define GPHY_DUPLEX_WIDTH 1
174 #define GPHY_LOOPBACK_NEAR_LBN 14
175 #define GPHY_LOOPBACK_NEAR_WIDTH 1
177 #define C22EXT_STATUS_REG 49153
178 #define C22EXT_STATUS_LINK_LBN 2
179 #define C22EXT_STATUS_LINK_WIDTH 1
181 #define C22EXT_MSTSLV_CTRL 49161
182 #define C22EXT_MSTSLV_CTRL_ADV_1000_HD_LBN 8
183 #define C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN 9
185 #define C22EXT_MSTSLV_STATUS 49162
186 #define C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN 10
187 #define C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN 11
189 /* Time to wait between powering down the LNPGA and turning off the power
191 #define LNPGA_PDOWN_WAIT (HZ / 5)
193 struct tenxpress_phy_data {
194 enum efx_loopback_mode loopback_mode;
195 enum efx_phy_mode phy_mode;
199 static ssize_t show_phy_short_reach(struct device *dev,
200 struct device_attribute *attr, char *buf)
202 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
205 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR);
206 return sprintf(buf, "%d\n", !!(reg & MDIO_PMA_10GBT_TXPWR_SHORT));
209 static ssize_t set_phy_short_reach(struct device *dev,
210 struct device_attribute *attr,
211 const char *buf, size_t count)
213 struct efx_nic *efx = pci_get_drvdata(to_pci_dev(dev));
216 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, MDIO_PMA_10GBT_TXPWR,
217 MDIO_PMA_10GBT_TXPWR_SHORT,
218 count != 0 && *buf != '0');
219 efx_reconfigure_port(efx);
225 static DEVICE_ATTR(phy_short_reach, 0644, show_phy_short_reach,
226 set_phy_short_reach);
228 int sft9001_wait_boot(struct efx_nic *efx)
230 unsigned long timeout = jiffies + HZ + 1;
234 boot_stat = efx_mdio_read(efx, MDIO_MMD_PCS,
235 PCS_BOOT_STATUS_REG);
236 if (boot_stat >= 0) {
237 EFX_LOG(efx, "PHY boot status = %#x\n", boot_stat);
239 ((1 << PCS_BOOT_FATAL_ERROR_LBN) |
240 (3 << PCS_BOOT_PROGRESS_LBN) |
241 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) |
242 (1 << PCS_BOOT_CODE_STARTED_LBN))) {
243 case ((1 << PCS_BOOT_FATAL_ERROR_LBN) |
244 (PCS_BOOT_PROGRESS_CHECKSUM <<
245 PCS_BOOT_PROGRESS_LBN)):
246 case ((1 << PCS_BOOT_FATAL_ERROR_LBN) |
247 (PCS_BOOT_PROGRESS_INIT <<
248 PCS_BOOT_PROGRESS_LBN) |
249 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)):
251 case ((PCS_BOOT_PROGRESS_WAIT_MDIO <<
252 PCS_BOOT_PROGRESS_LBN) |
253 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN)):
254 return (efx->phy_mode & PHY_MODE_SPECIAL) ?
256 case ((PCS_BOOT_PROGRESS_JUMP <<
257 PCS_BOOT_PROGRESS_LBN) |
258 (1 << PCS_BOOT_CODE_STARTED_LBN)):
259 case ((PCS_BOOT_PROGRESS_JUMP <<
260 PCS_BOOT_PROGRESS_LBN) |
261 (1 << PCS_BOOT_DOWNLOAD_WAIT_LBN) |
262 (1 << PCS_BOOT_CODE_STARTED_LBN)):
263 return (efx->phy_mode & PHY_MODE_SPECIAL) ?
266 if (boot_stat & (1 << PCS_BOOT_FATAL_ERROR_LBN))
272 if (time_after_eq(jiffies, timeout))
279 static int tenxpress_init(struct efx_nic *efx)
283 if (efx->phy_type == PHY_TYPE_SFX7101) {
284 /* Enable 312.5 MHz clock */
285 efx_mdio_write(efx, MDIO_MMD_PCS, PCS_TEST_SELECT_REG,
288 /* Enable 312.5 MHz clock and GMII */
289 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
290 reg |= ((1 << PMA_PMD_EXT_GMII_EN_LBN) |
291 (1 << PMA_PMD_EXT_CLK_OUT_LBN) |
292 (1 << PMA_PMD_EXT_CLK312_LBN) |
293 (1 << PMA_PMD_EXT_ROBUST_LBN));
295 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
296 efx_mdio_set_flag(efx, MDIO_MMD_C22EXT,
297 GPHY_XCONTROL_REG, 1 << GPHY_ISOLATE_LBN,
301 /* Set the LEDs up as: Green = Link, Amber = Link/Act, Red = Off */
302 if (efx->phy_type == PHY_TYPE_SFX7101) {
303 efx_mdio_set_flag(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_CTRL_REG,
304 1 << PMA_PMA_LED_ACTIVITY_LBN, true);
305 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG,
306 PMA_PMD_LED_DEFAULT);
312 static int tenxpress_phy_init(struct efx_nic *efx)
314 struct tenxpress_phy_data *phy_data;
317 phy_data = kzalloc(sizeof(*phy_data), GFP_KERNEL);
320 efx->phy_data = phy_data;
321 phy_data->phy_mode = efx->phy_mode;
323 if (!(efx->phy_mode & PHY_MODE_SPECIAL)) {
324 if (efx->phy_type == PHY_TYPE_SFT9001A) {
326 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
327 PMA_PMD_XCONTROL_REG);
328 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
329 efx_mdio_write(efx, MDIO_MMD_PMAPMD,
330 PMA_PMD_XCONTROL_REG, reg);
334 rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
338 rc = efx_mdio_check_mmds(efx, TENXPRESS_REQUIRED_DEVS, 0);
343 rc = tenxpress_init(efx);
347 if (efx->phy_type == PHY_TYPE_SFT9001B) {
348 rc = device_create_file(&efx->pci_dev->dev,
349 &dev_attr_phy_short_reach);
354 schedule_timeout_uninterruptible(HZ / 5); /* 200ms */
356 /* Let XGXS and SerDes out of reset */
357 falcon_reset_xaui(efx);
362 kfree(efx->phy_data);
363 efx->phy_data = NULL;
367 /* Perform a "special software reset" on the PHY. The caller is
368 * responsible for saving and restoring the PHY hardware registers
369 * properly, and masking/unmasking LASI */
370 static int tenxpress_special_reset(struct efx_nic *efx)
374 /* The XGMAC clock is driven from the SFC7101/SFT9001 312MHz clock, so
375 * a special software reset can glitch the XGMAC sufficiently for stats
376 * requests to fail. */
377 efx_stats_disable(efx);
380 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG);
381 reg |= (1 << PMA_PMD_EXT_SSR_LBN);
382 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
386 /* Wait for the blocks to come out of reset */
387 rc = efx_mdio_wait_reset_mmds(efx, TENXPRESS_REQUIRED_DEVS);
391 /* Try and reconfigure the device */
392 rc = tenxpress_init(efx);
396 /* Wait for the XGXS state machine to churn */
399 efx_stats_enable(efx);
403 static void sfx7101_check_bad_lp(struct efx_nic *efx, bool link_ok)
405 struct tenxpress_phy_data *pd = efx->phy_data;
412 /* Check that AN has started but not completed. */
413 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_STAT1);
414 if (!(reg & MDIO_AN_STAT1_LPABLE))
415 return; /* LP status is unknown */
416 bad_lp = !(reg & MDIO_AN_STAT1_COMPLETE);
421 /* Nothing to do if all is well and was previously so. */
422 if (!pd->bad_lp_tries)
425 /* Use the RX (red) LED as an error indicator once we've seen AN
426 * failure several times in a row, and also log a message. */
427 if (!bad_lp || pd->bad_lp_tries == MAX_BAD_LP_TRIES) {
428 reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
429 PMA_PMD_LED_OVERR_REG);
430 reg &= ~(PMA_PMD_LED_MASK << PMA_PMD_LED_RX_LBN);
432 reg |= PMA_PMD_LED_OFF << PMA_PMD_LED_RX_LBN;
434 reg |= PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN;
435 EFX_ERR(efx, "appears to be plugged into a port"
436 " that is not 10GBASE-T capable. The PHY"
437 " supports 10GBASE-T ONLY, so no link can"
438 " be established\n");
440 efx_mdio_write(efx, MDIO_MMD_PMAPMD,
441 PMA_PMD_LED_OVERR_REG, reg);
442 pd->bad_lp_tries = bad_lp;
446 static bool sfx7101_link_ok(struct efx_nic *efx)
448 return efx_mdio_links_ok(efx,
454 static bool sft9001_link_ok(struct efx_nic *efx, struct ethtool_cmd *ecmd)
458 if (efx_phy_mode_disabled(efx->phy_mode))
460 else if (efx->loopback_mode == LOOPBACK_GPHY)
462 else if (efx->loopback_mode)
463 return efx_mdio_links_ok(efx,
467 /* We must use the same definition of link state as LASI,
468 * otherwise we can miss a link state transition
470 if (ecmd->speed == 10000) {
471 reg = efx_mdio_read(efx, MDIO_MMD_PCS, MDIO_PCS_10GBRT_STAT1);
472 return reg & MDIO_PCS_10GBRT_STAT1_BLKLK;
474 reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_STATUS_REG);
475 return reg & (1 << C22EXT_STATUS_LINK_LBN);
479 static void tenxpress_ext_loopback(struct efx_nic *efx)
481 efx_mdio_set_flag(efx, MDIO_MMD_PHYXS, PHYXS_TEST1,
482 1 << LOOPBACK_NEAR_LBN,
483 efx->loopback_mode == LOOPBACK_PHYXS);
484 if (efx->phy_type != PHY_TYPE_SFX7101)
485 efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, GPHY_XCONTROL_REG,
486 1 << GPHY_LOOPBACK_NEAR_LBN,
487 efx->loopback_mode == LOOPBACK_GPHY);
490 static void tenxpress_low_power(struct efx_nic *efx)
492 if (efx->phy_type == PHY_TYPE_SFX7101)
493 efx_mdio_set_mmds_lpower(
494 efx, !!(efx->phy_mode & PHY_MODE_LOW_POWER),
495 TENXPRESS_REQUIRED_DEVS);
498 efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG,
499 1 << PMA_PMD_EXT_LPOWER_LBN,
500 !!(efx->phy_mode & PHY_MODE_LOW_POWER));
503 static void tenxpress_phy_reconfigure(struct efx_nic *efx)
505 struct tenxpress_phy_data *phy_data = efx->phy_data;
506 struct ethtool_cmd ecmd;
507 bool phy_mode_change, loop_reset;
509 if (efx->phy_mode & (PHY_MODE_OFF | PHY_MODE_SPECIAL)) {
510 phy_data->phy_mode = efx->phy_mode;
514 tenxpress_low_power(efx);
516 phy_mode_change = (efx->phy_mode == PHY_MODE_NORMAL &&
517 phy_data->phy_mode != PHY_MODE_NORMAL);
518 loop_reset = (LOOPBACK_OUT_OF(phy_data, efx, efx->phy_op->loopbacks) ||
519 LOOPBACK_CHANGED(phy_data, efx, 1 << LOOPBACK_GPHY));
521 if (loop_reset || phy_mode_change) {
524 efx->phy_op->get_settings(efx, &ecmd);
526 if (loop_reset || phy_mode_change) {
527 tenxpress_special_reset(efx);
529 /* Reset XAUI if we were in 10G, and are staying
530 * in 10G. If we're moving into and out of 10G
531 * then xaui will be reset anyway */
533 falcon_reset_xaui(efx);
536 rc = efx->phy_op->set_settings(efx, &ecmd);
540 efx_mdio_transmit_disable(efx);
541 efx_mdio_phy_reconfigure(efx);
542 tenxpress_ext_loopback(efx);
544 phy_data->loopback_mode = efx->loopback_mode;
545 phy_data->phy_mode = efx->phy_mode;
547 if (efx->phy_type == PHY_TYPE_SFX7101) {
548 efx->link_speed = 10000;
550 efx->link_up = sfx7101_link_ok(efx);
552 efx->phy_op->get_settings(efx, &ecmd);
553 efx->link_speed = ecmd.speed;
554 efx->link_fd = ecmd.duplex == DUPLEX_FULL;
555 efx->link_up = sft9001_link_ok(efx, &ecmd);
557 efx->link_fc = efx_mdio_get_pause(efx);
560 /* Poll PHY for interrupt */
561 static void tenxpress_phy_poll(struct efx_nic *efx)
563 struct tenxpress_phy_data *phy_data = efx->phy_data;
566 if (efx->phy_type == PHY_TYPE_SFX7101) {
567 bool link_ok = sfx7101_link_ok(efx);
568 if (link_ok != efx->link_up) {
571 unsigned int link_fc = efx_mdio_get_pause(efx);
572 if (link_fc != efx->link_fc)
575 sfx7101_check_bad_lp(efx, link_ok);
576 } else if (efx->loopback_mode) {
577 bool link_ok = sft9001_link_ok(efx, NULL);
578 if (link_ok != efx->link_up)
581 int status = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
582 PMA_PMD_LASI_STATUS);
583 if (status & (1 << PMA_PMD_LS_ALARM_LBN))
588 falcon_sim_phy_event(efx);
590 if (phy_data->phy_mode != PHY_MODE_NORMAL)
594 static void tenxpress_phy_fini(struct efx_nic *efx)
598 if (efx->phy_type == PHY_TYPE_SFT9001B)
599 device_remove_file(&efx->pci_dev->dev,
600 &dev_attr_phy_short_reach);
602 if (efx->phy_type == PHY_TYPE_SFX7101) {
603 /* Power down the LNPGA */
604 reg = (1 << PMA_PMD_LNPGA_POWERDOWN_LBN);
605 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_XCONTROL_REG, reg);
607 /* Waiting here ensures that the board fini, which can turn
608 * off the power to the PHY, won't get run until the LNPGA
609 * powerdown has been given long enough to complete. */
610 schedule_timeout_uninterruptible(LNPGA_PDOWN_WAIT); /* 200 ms */
613 kfree(efx->phy_data);
614 efx->phy_data = NULL;
618 /* Set the RX and TX LEDs and Link LED flashing. The other LEDs
619 * (which probably aren't wired anyway) are left in AUTO mode */
620 void tenxpress_phy_blink(struct efx_nic *efx, bool blink)
625 reg = (PMA_PMD_LED_FLASH << PMA_PMD_LED_TX_LBN) |
626 (PMA_PMD_LED_FLASH << PMA_PMD_LED_RX_LBN) |
627 (PMA_PMD_LED_FLASH << PMA_PMD_LED_LINK_LBN);
629 reg = PMA_PMD_LED_DEFAULT;
631 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_LED_OVERR_REG, reg);
634 static const char *const sfx7101_test_names[] = {
639 sfx7101_run_tests(struct efx_nic *efx, int *results, unsigned flags)
643 if (!(flags & ETH_TEST_FL_OFFLINE))
646 /* BIST is automatically run after a special software reset */
647 rc = tenxpress_special_reset(efx);
648 results[0] = rc ? -1 : 1;
652 static const char *const sft9001_test_names[] = {
654 "cable.pairA.status",
655 "cable.pairB.status",
656 "cable.pairC.status",
657 "cable.pairD.status",
658 "cable.pairA.length",
659 "cable.pairB.length",
660 "cable.pairC.length",
661 "cable.pairD.length",
664 static int sft9001_run_tests(struct efx_nic *efx, int *results, unsigned flags)
666 struct ethtool_cmd ecmd;
667 int rc = 0, rc2, i, ctrl_reg, res_reg;
669 if (flags & ETH_TEST_FL_OFFLINE)
670 efx->phy_op->get_settings(efx, &ecmd);
672 /* Initialise cable diagnostic results to unknown failure */
673 for (i = 1; i < 9; ++i)
676 /* Run cable diagnostics; wait up to 5 seconds for them to complete.
677 * A cable fault is not a self-test failure, but a timeout is. */
678 ctrl_reg = ((1 << CDIAG_CTRL_IMMED_LBN) |
679 (CDIAG_CTRL_LEN_METRES << CDIAG_CTRL_LEN_UNIT_LBN));
680 if (flags & ETH_TEST_FL_OFFLINE) {
681 /* Break the link in order to run full diagnostics. We
682 * must reset the PHY to resume normal service. */
683 ctrl_reg |= (1 << CDIAG_CTRL_BRK_LINK_LBN);
685 efx_mdio_write(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG,
688 while (efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_CTRL_REG) &
689 (1 << CDIAG_CTRL_IN_PROG_LBN)) {
696 res_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD, PMA_PMD_CDIAG_RES_REG);
697 for (i = 0; i < 4; i++) {
699 (res_reg >> (CDIAG_RES_A_LBN - i * CDIAG_RES_WIDTH))
700 & ((1 << CDIAG_RES_WIDTH) - 1);
701 int len_reg = efx_mdio_read(efx, MDIO_MMD_PMAPMD,
702 PMA_PMD_CDIAG_LEN_REG + i);
703 if (pair_res == CDIAG_RES_OK)
705 else if (pair_res == CDIAG_RES_INVALID)
708 results[1 + i] = -pair_res;
709 if (pair_res != CDIAG_RES_INVALID &&
710 pair_res != CDIAG_RES_OPEN &&
712 results[5 + i] = len_reg;
716 if (flags & ETH_TEST_FL_OFFLINE) {
717 /* Reset, running the BIST and then resuming normal service. */
718 rc2 = tenxpress_special_reset(efx);
719 results[0] = rc2 ? -1 : 1;
723 rc2 = efx->phy_op->set_settings(efx, &ecmd);
732 tenxpress_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
734 u32 adv = 0, lpa = 0;
737 if (efx->phy_type != PHY_TYPE_SFX7101) {
738 reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL);
739 if (reg & (1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN))
740 adv |= ADVERTISED_1000baseT_Full;
741 reg = efx_mdio_read(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_STATUS);
742 if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_HD_LBN))
743 lpa |= ADVERTISED_1000baseT_Half;
744 if (reg & (1 << C22EXT_MSTSLV_STATUS_LP_1000_FD_LBN))
745 lpa |= ADVERTISED_1000baseT_Full;
747 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL);
748 if (reg & MDIO_AN_10GBT_CTRL_ADV10G)
749 adv |= ADVERTISED_10000baseT_Full;
750 reg = efx_mdio_read(efx, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
751 if (reg & MDIO_AN_10GBT_STAT_LP10G)
752 lpa |= ADVERTISED_10000baseT_Full;
754 mdio45_ethtool_gset_npage(&efx->mdio, ecmd, adv, lpa);
756 if (efx->phy_type != PHY_TYPE_SFX7101)
757 ecmd->supported |= (SUPPORTED_100baseT_Full |
758 SUPPORTED_1000baseT_Full);
760 /* In loopback, the PHY automatically brings up the correct interface,
761 * but doesn't advertise the correct speed. So override it */
762 if (efx->loopback_mode == LOOPBACK_GPHY)
763 ecmd->speed = SPEED_1000;
764 else if (LOOPBACK_MASK(efx) & efx->phy_op->loopbacks)
765 ecmd->speed = SPEED_10000;
768 static int tenxpress_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
773 return efx_mdio_set_settings(efx, ecmd);
776 static void sfx7101_set_npage_adv(struct efx_nic *efx, u32 advertising)
778 efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
779 MDIO_AN_10GBT_CTRL_ADV10G,
780 advertising & ADVERTISED_10000baseT_Full);
783 static void sft9001_set_npage_adv(struct efx_nic *efx, u32 advertising)
785 efx_mdio_set_flag(efx, MDIO_MMD_C22EXT, C22EXT_MSTSLV_CTRL,
786 1 << C22EXT_MSTSLV_CTRL_ADV_1000_FD_LBN,
787 advertising & ADVERTISED_1000baseT_Full);
788 efx_mdio_set_flag(efx, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
789 MDIO_AN_10GBT_CTRL_ADV10G,
790 advertising & ADVERTISED_10000baseT_Full);
793 struct efx_phy_operations falcon_sfx7101_phy_ops = {
795 .init = tenxpress_phy_init,
796 .reconfigure = tenxpress_phy_reconfigure,
797 .poll = tenxpress_phy_poll,
798 .fini = tenxpress_phy_fini,
799 .clear_interrupt = efx_port_dummy_op_void,
800 .get_settings = tenxpress_get_settings,
801 .set_settings = tenxpress_set_settings,
802 .set_npage_adv = sfx7101_set_npage_adv,
803 .num_tests = ARRAY_SIZE(sfx7101_test_names),
804 .test_names = sfx7101_test_names,
805 .run_tests = sfx7101_run_tests,
806 .mmds = TENXPRESS_REQUIRED_DEVS,
807 .loopbacks = SFX7101_LOOPBACKS,
810 struct efx_phy_operations falcon_sft9001_phy_ops = {
811 .macs = EFX_GMAC | EFX_XMAC,
812 .init = tenxpress_phy_init,
813 .reconfigure = tenxpress_phy_reconfigure,
814 .poll = tenxpress_phy_poll,
815 .fini = tenxpress_phy_fini,
816 .clear_interrupt = efx_port_dummy_op_void,
817 .get_settings = tenxpress_get_settings,
818 .set_settings = tenxpress_set_settings,
819 .set_npage_adv = sft9001_set_npage_adv,
820 .num_tests = ARRAY_SIZE(sft9001_test_names),
821 .test_names = sft9001_test_names,
822 .run_tests = sft9001_run_tests,
823 .mmds = TENXPRESS_REQUIRED_DEVS,
824 .loopbacks = SFT9001_LOOPBACKS,