1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2005-2009 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 /* Common definitions for all Efx net driver code */
13 #ifndef EFX_NET_DRIVER_H
14 #define EFX_NET_DRIVER_H
16 #include <linux/version.h>
17 #include <linux/netdevice.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_vlan.h>
21 #include <linux/mdio.h>
22 #include <linux/list.h>
23 #include <linux/pci.h>
24 #include <linux/device.h>
25 #include <linux/highmem.h>
26 #include <linux/workqueue.h>
27 #include <linux/i2c.h>
32 /**************************************************************************
36 **************************************************************************/
37 #ifndef EFX_DRIVER_NAME
38 #define EFX_DRIVER_NAME "sfc"
40 #define EFX_DRIVER_VERSION "3.0"
42 #ifdef EFX_ENABLE_DEBUG
43 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
44 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
46 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
47 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
50 /* Un-rate-limited logging */
51 #define EFX_ERR(efx, fmt, args...) \
52 dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args)
54 #define EFX_INFO(efx, fmt, args...) \
55 dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args)
57 #ifdef EFX_ENABLE_DEBUG
58 #define EFX_LOG(efx, fmt, args...) \
59 dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
61 #define EFX_LOG(efx, fmt, args...) \
62 dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
65 #define EFX_TRACE(efx, fmt, args...) do {} while (0)
67 #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
69 /* Rate-limited logging */
70 #define EFX_ERR_RL(efx, fmt, args...) \
71 do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
73 #define EFX_INFO_RL(efx, fmt, args...) \
74 do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
76 #define EFX_LOG_RL(efx, fmt, args...) \
77 do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
79 /**************************************************************************
83 **************************************************************************/
85 #define EFX_MAX_CHANNELS 32
86 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
88 #define EFX_TX_QUEUE_OFFLOAD_CSUM 0
89 #define EFX_TX_QUEUE_NO_CSUM 1
90 #define EFX_TX_QUEUE_COUNT 2
93 * struct efx_special_buffer - An Efx special buffer
94 * @addr: CPU base address of the buffer
95 * @dma_addr: DMA base address of the buffer
96 * @len: Buffer length, in bytes
97 * @index: Buffer index within controller;s buffer table
98 * @entries: Number of buffer table entries
100 * Special buffers are used for the event queues and the TX and RX
101 * descriptor queues for each channel. They are *not* used for the
102 * actual transmit and receive buffers.
104 struct efx_special_buffer {
112 enum efx_flush_state {
120 * struct efx_tx_buffer - An Efx TX buffer
121 * @skb: The associated socket buffer.
122 * Set only on the final fragment of a packet; %NULL for all other
123 * fragments. When this fragment completes, then we can free this
125 * @tsoh: The associated TSO header structure, or %NULL if this
126 * buffer is not a TSO header.
127 * @dma_addr: DMA address of the fragment.
128 * @len: Length of this fragment.
129 * This field is zero when the queue slot is empty.
130 * @continuation: True if this fragment is not the end of a packet.
131 * @unmap_single: True if pci_unmap_single should be used.
132 * @unmap_len: Length of this fragment to unmap
134 struct efx_tx_buffer {
135 const struct sk_buff *skb;
136 struct efx_tso_header *tsoh;
141 unsigned short unmap_len;
145 * struct efx_tx_queue - An Efx TX queue
147 * This is a ring buffer of TX fragments.
148 * Since the TX completion path always executes on the same
149 * CPU and the xmit path can operate on different CPUs,
150 * performance is increased by ensuring that the completion
151 * path and the xmit path operate on different cache lines.
152 * This is particularly important if the xmit path is always
153 * executing on one CPU which is different from the completion
154 * path. There is also a cache line for members which are
155 * read but not written on the fast path.
157 * @efx: The associated Efx NIC
158 * @queue: DMA queue number
159 * @channel: The associated channel
160 * @buffer: The software buffer ring
161 * @txd: The hardware descriptor ring
162 * @flushed: Used when handling queue flushing
163 * @read_count: Current read pointer.
164 * This is the number of buffers that have been removed from both rings.
165 * @stopped: Stopped count.
166 * Set if this TX queue is currently stopping its port.
167 * @insert_count: Current insert pointer
168 * This is the number of buffers that have been added to the
170 * @write_count: Current write pointer
171 * This is the number of buffers that have been added to the
173 * @old_read_count: The value of read_count when last checked.
174 * This is here for performance reasons. The xmit path will
175 * only get the up-to-date value of read_count if this
176 * variable indicates that the queue is full. This is to
177 * avoid cache-line ping-pong between the xmit path and the
179 * @tso_headers_free: A list of TSO headers allocated for this TX queue
180 * that are not in use, and so available for new TSO sends. The list
181 * is protected by the TX queue lock.
182 * @tso_bursts: Number of times TSO xmit invoked by kernel
183 * @tso_long_headers: Number of packets with headers too long for standard
185 * @tso_packets: Number of packets via the TSO xmit path
187 struct efx_tx_queue {
188 /* Members which don't change on the fast path */
189 struct efx_nic *efx ____cacheline_aligned_in_smp;
191 struct efx_channel *channel;
193 struct efx_tx_buffer *buffer;
194 struct efx_special_buffer txd;
195 enum efx_flush_state flushed;
197 /* Members used mainly on the completion path */
198 unsigned int read_count ____cacheline_aligned_in_smp;
201 /* Members used only on the xmit path */
202 unsigned int insert_count ____cacheline_aligned_in_smp;
203 unsigned int write_count;
204 unsigned int old_read_count;
205 struct efx_tso_header *tso_headers_free;
206 unsigned int tso_bursts;
207 unsigned int tso_long_headers;
208 unsigned int tso_packets;
212 * struct efx_rx_buffer - An Efx RX data buffer
213 * @dma_addr: DMA base address of the buffer
214 * @skb: The associated socket buffer, if any.
215 * If both this and page are %NULL, the buffer slot is currently free.
216 * @page: The associated page buffer, if any.
217 * If both this and skb are %NULL, the buffer slot is currently free.
218 * @data: Pointer to ethernet header
219 * @len: Buffer length, in bytes.
220 * @unmap_addr: DMA address to unmap
222 struct efx_rx_buffer {
228 dma_addr_t unmap_addr;
232 * struct efx_rx_queue - An Efx RX queue
233 * @efx: The associated Efx NIC
234 * @queue: DMA queue number
235 * @channel: The associated channel
236 * @buffer: The software buffer ring
237 * @rxd: The hardware descriptor ring
238 * @added_count: Number of buffers added to the receive queue.
239 * @notified_count: Number of buffers given to NIC (<= @added_count).
240 * @removed_count: Number of buffers removed from the receive queue.
241 * @add_lock: Receive queue descriptor add spin lock.
242 * This lock must be held in order to add buffers to the RX
243 * descriptor ring (rxd and buffer) and to update added_count (but
244 * not removed_count).
245 * @max_fill: RX descriptor maximum fill level (<= ring size)
246 * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
248 * @fast_fill_limit: The level to which a fast fill will fill
249 * (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
250 * @min_fill: RX descriptor minimum non-zero fill level.
251 * This records the minimum fill level observed when a ring
252 * refill was triggered.
253 * @min_overfill: RX descriptor minimum overflow fill level.
254 * This records the minimum fill level at which RX queue
255 * overflow was observed. It should never be set.
256 * @alloc_page_count: RX allocation strategy counter.
257 * @alloc_skb_count: RX allocation strategy counter.
258 * @work: Descriptor push work thread
259 * @buf_page: Page for next RX buffer.
260 * We can use a single page for multiple RX buffers. This tracks
261 * the remaining space in the allocation.
262 * @buf_dma_addr: Page's DMA address.
263 * @buf_data: Page's host address.
264 * @flushed: Use when handling queue flushing
266 struct efx_rx_queue {
269 struct efx_channel *channel;
270 struct efx_rx_buffer *buffer;
271 struct efx_special_buffer rxd;
277 unsigned int max_fill;
278 unsigned int fast_fill_trigger;
279 unsigned int fast_fill_limit;
280 unsigned int min_fill;
281 unsigned int min_overfill;
282 unsigned int alloc_page_count;
283 unsigned int alloc_skb_count;
284 struct delayed_work work;
285 unsigned int slow_fill_count;
287 struct page *buf_page;
288 dma_addr_t buf_dma_addr;
290 enum efx_flush_state flushed;
294 * struct efx_buffer - An Efx general-purpose buffer
295 * @addr: host base address of the buffer
296 * @dma_addr: DMA base address of the buffer
297 * @len: Buffer length, in bytes
299 * The NIC uses these buffers for its interrupt status registers and
309 /* Flags for channel->used_flags */
310 #define EFX_USED_BY_RX 1
311 #define EFX_USED_BY_TX 2
312 #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
314 enum efx_rx_alloc_method {
315 RX_ALLOC_METHOD_AUTO = 0,
316 RX_ALLOC_METHOD_SKB = 1,
317 RX_ALLOC_METHOD_PAGE = 2,
321 * struct efx_channel - An Efx channel
323 * A channel comprises an event queue, at least one TX queue, at least
324 * one RX queue, and an associated tasklet for processing the event
327 * @efx: Associated Efx NIC
328 * @channel: Channel instance number
329 * @name: Name for channel and IRQ
330 * @used_flags: Channel is used by net driver
331 * @enabled: Channel enabled indicator
332 * @irq: IRQ number (MSI and MSI-X only)
333 * @irq_moderation: IRQ moderation value (in hardware ticks)
334 * @napi_dev: Net device used with NAPI
335 * @napi_str: NAPI control structure
336 * @reset_work: Scheduled reset work thread
337 * @work_pending: Is work pending via NAPI?
338 * @eventq: Event queue buffer
339 * @eventq_read_ptr: Event queue read pointer
340 * @last_eventq_read_ptr: Last event queue read pointer value.
341 * @eventq_magic: Event queue magic value for driver-generated test events
342 * @irq_count: Number of IRQs since last adaptive moderation decision
343 * @irq_mod_score: IRQ moderation score
344 * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
345 * and diagnostic counters
346 * @rx_alloc_push_pages: RX allocation method currently in use for pushing
348 * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
349 * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
350 * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
351 * @n_rx_mcast_mismatch: Count of unmatched multicast frames
352 * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
353 * @n_rx_overlength: Count of RX_OVERLENGTH errors
354 * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
359 char name[IFNAMSIZ + 6];
363 unsigned int irq_moderation;
364 struct net_device *napi_dev;
365 struct napi_struct napi_str;
367 struct efx_special_buffer eventq;
368 unsigned int eventq_read_ptr;
369 unsigned int last_eventq_read_ptr;
370 unsigned int eventq_magic;
372 unsigned int irq_count;
373 unsigned int irq_mod_score;
376 int rx_alloc_push_pages;
378 unsigned n_rx_tobe_disc;
379 unsigned n_rx_ip_hdr_chksum_err;
380 unsigned n_rx_tcp_udp_chksum_err;
381 unsigned n_rx_mcast_mismatch;
382 unsigned n_rx_frm_trunc;
383 unsigned n_rx_overlength;
384 unsigned n_skbuff_leaks;
386 /* Used to pipeline received packets in order to optimise memory
387 * access with prefetches.
389 struct efx_rx_buffer *rx_pkt;
400 #define STRING_TABLE_LOOKUP(val, member) \
401 ((val) < member ## _max) ? member ## _names[val] : "(invalid)"
403 extern const char *efx_loopback_mode_names[];
404 extern const unsigned int efx_loopback_mode_max;
405 #define LOOPBACK_MODE(efx) \
406 STRING_TABLE_LOOKUP((efx)->loopback_mode, efx_loopback_mode)
408 extern const char *efx_interrupt_mode_names[];
409 extern const unsigned int efx_interrupt_mode_max;
410 #define INT_MODE(efx) \
411 STRING_TABLE_LOOKUP(efx->interrupt_mode, efx_interrupt_mode)
413 extern const char *efx_reset_type_names[];
414 extern const unsigned int efx_reset_type_max;
415 #define RESET_TYPE(type) \
416 STRING_TABLE_LOOKUP(type, efx_reset_type)
419 /* Be careful if altering to correct macro below */
420 EFX_INT_MODE_MSIX = 0,
421 EFX_INT_MODE_MSI = 1,
422 EFX_INT_MODE_LEGACY = 2,
423 EFX_INT_MODE_MAX /* Insert any new items before this */
425 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
427 #define EFX_IS10G(efx) ((efx)->link_state.speed == 10000)
438 * Alignment of page-allocated RX buffers
440 * Controls the number of bytes inserted at the start of an RX buffer.
441 * This is the equivalent of NET_IP_ALIGN [which controls the alignment
442 * of the skb->head for hardware DMA].
444 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
445 #define EFX_PAGE_IP_ALIGN 0
447 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
451 * Alignment of the skb->head which wraps a page-allocated RX buffer
453 * The skb allocated to wrap an rx_buffer can have this alignment. Since
454 * the data is memcpy'd from the rx_buf, it does not need to be equal to
457 #define EFX_PAGE_SKB_ALIGN 2
459 /* Forward declaration */
462 /* Pseudo bit-mask flow control field */
464 EFX_FC_RX = FLOW_CTRL_RX,
465 EFX_FC_TX = FLOW_CTRL_TX,
470 * struct efx_link_state - Current state of the link
472 * @fd: Link is full-duplex
473 * @fc: Actual flow control flags
474 * @speed: Link speed (Mbps)
476 struct efx_link_state {
483 static inline bool efx_link_state_equal(const struct efx_link_state *left,
484 const struct efx_link_state *right)
486 return left->up == right->up && left->fd == right->fd &&
487 left->fc == right->fc && left->speed == right->speed;
491 * struct efx_mac_operations - Efx MAC operations table
492 * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
493 * @update_stats: Update statistics
494 * @check_fault: Check fault state. True if fault present.
496 struct efx_mac_operations {
497 int (*reconfigure) (struct efx_nic *efx);
498 void (*update_stats) (struct efx_nic *efx);
499 bool (*check_fault)(struct efx_nic *efx);
503 * struct efx_phy_operations - Efx PHY operations table
504 * @probe: Probe PHY and initialise efx->mdio.mode_support, efx->mdio.mmds,
505 * efx->loopback_modes.
506 * @init: Initialise PHY
507 * @fini: Shut down PHY
508 * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
509 * @poll: Update @link_state and report whether it changed.
510 * Serialised by the mac_lock.
511 * @get_settings: Get ethtool settings. Serialised by the mac_lock.
512 * @set_settings: Set ethtool settings. Serialised by the mac_lock.
513 * @set_npage_adv: Set abilities advertised in (Extended) Next Page
514 * (only needed where AN bit is set in mmds)
515 * @test_alive: Test that PHY is 'alive' (online)
516 * @test_name: Get the name of a PHY-specific test/result
517 * @run_tests: Run tests and record results as appropriate (offline).
518 * Flags are the ethtool tests flags.
520 struct efx_phy_operations {
521 int (*probe) (struct efx_nic *efx);
522 int (*init) (struct efx_nic *efx);
523 void (*fini) (struct efx_nic *efx);
524 void (*remove) (struct efx_nic *efx);
525 int (*reconfigure) (struct efx_nic *efx);
526 bool (*poll) (struct efx_nic *efx);
527 void (*get_settings) (struct efx_nic *efx,
528 struct ethtool_cmd *ecmd);
529 int (*set_settings) (struct efx_nic *efx,
530 struct ethtool_cmd *ecmd);
531 void (*set_npage_adv) (struct efx_nic *efx, u32);
532 int (*test_alive) (struct efx_nic *efx);
533 const char *(*test_name) (struct efx_nic *efx, unsigned int index);
534 int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
538 * @enum efx_phy_mode - PHY operating mode flags
539 * @PHY_MODE_NORMAL: on and should pass traffic
540 * @PHY_MODE_TX_DISABLED: on with TX disabled
541 * @PHY_MODE_LOW_POWER: set to low power through MDIO
542 * @PHY_MODE_OFF: switched off through external control
543 * @PHY_MODE_SPECIAL: on but will not pass traffic
547 PHY_MODE_TX_DISABLED = 1,
548 PHY_MODE_LOW_POWER = 2,
550 PHY_MODE_SPECIAL = 8,
553 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
555 return !!(mode & ~PHY_MODE_TX_DISABLED);
559 * Efx extended statistics
561 * Not all statistics are provided by all supported MACs. The purpose
562 * is this structure is to contain the raw statistics provided by each
565 struct efx_mac_stats {
569 unsigned long tx_packets;
570 unsigned long tx_bad;
571 unsigned long tx_pause;
572 unsigned long tx_control;
573 unsigned long tx_unicast;
574 unsigned long tx_multicast;
575 unsigned long tx_broadcast;
576 unsigned long tx_lt64;
578 unsigned long tx_65_to_127;
579 unsigned long tx_128_to_255;
580 unsigned long tx_256_to_511;
581 unsigned long tx_512_to_1023;
582 unsigned long tx_1024_to_15xx;
583 unsigned long tx_15xx_to_jumbo;
584 unsigned long tx_gtjumbo;
585 unsigned long tx_collision;
586 unsigned long tx_single_collision;
587 unsigned long tx_multiple_collision;
588 unsigned long tx_excessive_collision;
589 unsigned long tx_deferred;
590 unsigned long tx_late_collision;
591 unsigned long tx_excessive_deferred;
592 unsigned long tx_non_tcpudp;
593 unsigned long tx_mac_src_error;
594 unsigned long tx_ip_src_error;
598 unsigned long rx_packets;
599 unsigned long rx_good;
600 unsigned long rx_bad;
601 unsigned long rx_pause;
602 unsigned long rx_control;
603 unsigned long rx_unicast;
604 unsigned long rx_multicast;
605 unsigned long rx_broadcast;
606 unsigned long rx_lt64;
608 unsigned long rx_65_to_127;
609 unsigned long rx_128_to_255;
610 unsigned long rx_256_to_511;
611 unsigned long rx_512_to_1023;
612 unsigned long rx_1024_to_15xx;
613 unsigned long rx_15xx_to_jumbo;
614 unsigned long rx_gtjumbo;
615 unsigned long rx_bad_lt64;
616 unsigned long rx_bad_64_to_15xx;
617 unsigned long rx_bad_15xx_to_jumbo;
618 unsigned long rx_bad_gtjumbo;
619 unsigned long rx_overflow;
620 unsigned long rx_missed;
621 unsigned long rx_false_carrier;
622 unsigned long rx_symbol_error;
623 unsigned long rx_align_error;
624 unsigned long rx_length_error;
625 unsigned long rx_internal_error;
626 unsigned long rx_good_lt64;
629 /* Number of bits used in a multicast filter hash address */
630 #define EFX_MCAST_HASH_BITS 8
632 /* Number of (single-bit) entries in a multicast filter hash */
633 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
635 /* An Efx multicast filter hash */
636 union efx_multicast_hash {
637 u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
638 efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
642 * struct efx_nic - an Efx NIC
643 * @name: Device name (net device name or bus id before net device registered)
644 * @pci_dev: The PCI device
645 * @type: Controller type attributes
646 * @legacy_irq: IRQ number
647 * @workqueue: Workqueue for port reconfigures and the HW monitor.
648 * Work items do not hold and must not acquire RTNL.
649 * @workqueue_name: Name of workqueue
650 * @reset_work: Scheduled reset workitem
651 * @monitor_work: Hardware monitor workitem
652 * @membase_phys: Memory BAR value as physical address
653 * @membase: Memory BAR value
654 * @biu_lock: BIU (bus interface unit) lock
655 * @interrupt_mode: Interrupt mode
656 * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
657 * @irq_rx_moderation: IRQ moderation time for RX event queues
658 * @state: Device state flag. Serialised by the rtnl_lock.
659 * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
660 * @tx_queue: TX DMA queues
661 * @rx_queue: RX DMA queues
663 * @next_buffer_table: First available buffer table id
664 * @n_rx_queues: Number of RX queues
665 * @n_channels: Number of channels in use
666 * @rx_buffer_len: RX buffer length
667 * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
668 * @int_error_count: Number of internal errors seen recently
669 * @int_error_expire: Time at which error count will be expired
670 * @irq_status: Interrupt status buffer
671 * @last_irq_cpu: Last CPU to handle interrupt.
672 * This register is written with the SMP processor ID whenever an
673 * interrupt is handled. It is used by efx_nic_test_interrupt()
674 * to verify that an interrupt has occurred.
675 * @spi_flash: SPI flash device
676 * This field will be %NULL if no flash device is present (or for Siena).
677 * @spi_eeprom: SPI EEPROM device
678 * This field will be %NULL if no EEPROM device is present (or for Siena).
679 * @spi_lock: SPI bus lock
680 * @mtd_list: List of MTDs attached to the NIC
681 * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
682 * @nic_data: Hardware dependant state
683 * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
684 * @port_inhibited, efx_monitor() and efx_reconfigure_port()
685 * @port_enabled: Port enabled indicator.
686 * Serialises efx_stop_all(), efx_start_all(), efx_monitor() and
687 * efx_mac_work() with kernel interfaces. Safe to read under any
688 * one of the rtnl_lock, mac_lock, or netif_tx_lock, but all three must
689 * be held to modify it.
690 * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
691 * @port_initialized: Port initialized?
692 * @net_dev: Operating system network device. Consider holding the rtnl lock
693 * @rx_checksum_enabled: RX checksumming enabled
694 * @netif_stop_count: Port stop count
695 * @netif_stop_lock: Port stop lock
696 * @mac_stats: MAC statistics. These include all statistics the MACs
697 * can provide. Generic code converts these into a standard
698 * &struct net_device_stats.
699 * @stats_buffer: DMA buffer for statistics
700 * @stats_lock: Statistics update lock. Serialises statistics fetches
701 * @mac_op: MAC interface
702 * @mac_address: Permanent MAC address
703 * @phy_type: PHY type
704 * @mdio_lock: MDIO lock
705 * @phy_op: PHY interface
706 * @phy_data: PHY private data (including PHY-specific stats)
707 * @mdio: PHY MDIO interface
708 * @mdio_bus: PHY MDIO bus ID (only used by Siena)
709 * @phy_mode: PHY operating mode. Serialised by @mac_lock.
710 * @xmac_poll_required: XMAC link state needs polling
711 * @link_advertising: Autonegotiation advertising flags
712 * @link_state: Current state of the link
713 * @n_link_state_changes: Number of times the link has changed state
714 * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
715 * @multicast_hash: Multicast hash table
716 * @wanted_fc: Wanted flow control flags
717 * @mac_work: Work item for changing MAC promiscuity and multicast hash
718 * @loopback_mode: Loopback status
719 * @loopback_modes: Supported loopback mode bitmask
720 * @loopback_selftest: Offline self-test private state
722 * This is stored in the private area of the &struct net_device.
726 struct pci_dev *pci_dev;
727 const struct efx_nic_type *type;
729 struct workqueue_struct *workqueue;
730 char workqueue_name[16];
731 struct work_struct reset_work;
732 struct delayed_work monitor_work;
733 resource_size_t membase_phys;
734 void __iomem *membase;
736 enum efx_int_mode interrupt_mode;
737 bool irq_rx_adaptive;
738 unsigned int irq_rx_moderation;
740 enum nic_state state;
741 enum reset_type reset_pending;
743 struct efx_tx_queue tx_queue[EFX_TX_QUEUE_COUNT];
744 struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
745 struct efx_channel channel[EFX_MAX_CHANNELS];
747 unsigned next_buffer_table;
750 unsigned int rx_buffer_len;
751 unsigned int rx_buffer_order;
753 unsigned int_error_count;
754 unsigned long int_error_expire;
756 struct efx_buffer irq_status;
757 volatile signed int last_irq_cpu;
758 unsigned long irq_zero_count;
760 struct efx_spi_device *spi_flash;
761 struct efx_spi_device *spi_eeprom;
762 struct mutex spi_lock;
763 #ifdef CONFIG_SFC_MTD
764 struct list_head mtd_list;
767 unsigned n_rx_nodesc_drop_cnt;
771 struct mutex mac_lock;
772 struct work_struct mac_work;
776 bool port_initialized;
777 struct net_device *net_dev;
778 bool rx_checksum_enabled;
780 atomic_t netif_stop_count;
781 spinlock_t netif_stop_lock;
783 struct efx_mac_stats mac_stats;
784 struct efx_buffer stats_buffer;
785 spinlock_t stats_lock;
787 struct efx_mac_operations *mac_op;
788 unsigned char mac_address[ETH_ALEN];
790 unsigned int phy_type;
791 struct mutex mdio_lock;
792 struct efx_phy_operations *phy_op;
794 struct mdio_if_info mdio;
795 unsigned int mdio_bus;
796 enum efx_phy_mode phy_mode;
798 bool xmac_poll_required;
799 u32 link_advertising;
800 struct efx_link_state link_state;
801 unsigned int n_link_state_changes;
804 union efx_multicast_hash multicast_hash;
805 enum efx_fc_type wanted_fc;
808 enum efx_loopback_mode loopback_mode;
811 void *loopback_selftest;
814 static inline int efx_dev_registered(struct efx_nic *efx)
816 return efx->net_dev->reg_state == NETREG_REGISTERED;
819 /* Net device name, for inclusion in log messages if it has been registered.
820 * Use efx->name not efx->net_dev->name so that races with (un)registration
823 static inline const char *efx_dev_name(struct efx_nic *efx)
825 return efx_dev_registered(efx) ? efx->name : "";
828 static inline unsigned int efx_port_num(struct efx_nic *efx)
830 return PCI_FUNC(efx->pci_dev->devfn);
834 * struct efx_nic_type - Efx device type definition
835 * @probe: Probe the controller
836 * @remove: Free resources allocated by probe()
837 * @init: Initialise the controller
838 * @fini: Shut down the controller
839 * @monitor: Periodic function for polling link state and hardware monitor
840 * @reset: Reset the controller hardware and possibly the PHY. This will
841 * be called while the controller is uninitialised.
842 * @probe_port: Probe the MAC and PHY
843 * @remove_port: Free resources allocated by probe_port()
844 * @prepare_flush: Prepare the hardware for flushing the DMA queues
845 * @update_stats: Update statistics not provided by event handling
846 * @start_stats: Start the regular fetching of statistics
847 * @stop_stats: Stop the regular fetching of statistics
848 * @set_id_led: Set state of identifying LED or revert to automatic function
849 * @push_irq_moderation: Apply interrupt moderation value
850 * @push_multicast_hash: Apply multicast hash table
851 * @reconfigure_port: Push loopback/power/txdis changes to the MAC and PHY
852 * @get_wol: Get WoL configuration from driver state
853 * @set_wol: Push WoL configuration to the NIC
854 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)
855 * @test_registers: Test read/write functionality of control registers
856 * @test_nvram: Test validity of NVRAM contents
857 * @default_mac_ops: efx_mac_operations to set at startup
858 * @revision: Hardware architecture revision
859 * @mem_map_size: Memory BAR mapped size
860 * @txd_ptr_tbl_base: TX descriptor ring base address
861 * @rxd_ptr_tbl_base: RX descriptor ring base address
862 * @buf_tbl_base: Buffer table base address
863 * @evq_ptr_tbl_base: Event queue pointer table base address
864 * @evq_rptr_tbl_base: Event queue read-pointer table base address
865 * @max_dma_mask: Maximum possible DMA mask
866 * @rx_buffer_padding: Padding added to each RX buffer
867 * @max_interrupt_mode: Highest capability interrupt mode supported
868 * from &enum efx_init_mode.
869 * @phys_addr_channels: Number of channels with physically addressed
871 * @tx_dc_base: Base address in SRAM of TX queue descriptor caches
872 * @rx_dc_base: Base address in SRAM of RX queue descriptor caches
873 * @offload_features: net_device feature flags for protocol offload
874 * features implemented in hardware
875 * @reset_world_flags: Flags for additional components covered by
876 * reset method RESET_TYPE_WORLD
878 struct efx_nic_type {
879 int (*probe)(struct efx_nic *efx);
880 void (*remove)(struct efx_nic *efx);
881 int (*init)(struct efx_nic *efx);
882 void (*fini)(struct efx_nic *efx);
883 void (*monitor)(struct efx_nic *efx);
884 int (*reset)(struct efx_nic *efx, enum reset_type method);
885 int (*probe_port)(struct efx_nic *efx);
886 void (*remove_port)(struct efx_nic *efx);
887 void (*prepare_flush)(struct efx_nic *efx);
888 void (*update_stats)(struct efx_nic *efx);
889 void (*start_stats)(struct efx_nic *efx);
890 void (*stop_stats)(struct efx_nic *efx);
891 void (*set_id_led)(struct efx_nic *efx, enum efx_led_mode mode);
892 void (*push_irq_moderation)(struct efx_channel *channel);
893 void (*push_multicast_hash)(struct efx_nic *efx);
894 int (*reconfigure_port)(struct efx_nic *efx);
895 void (*get_wol)(struct efx_nic *efx, struct ethtool_wolinfo *wol);
896 int (*set_wol)(struct efx_nic *efx, u32 type);
897 void (*resume_wol)(struct efx_nic *efx);
898 int (*test_registers)(struct efx_nic *efx);
899 int (*test_nvram)(struct efx_nic *efx);
900 struct efx_mac_operations *default_mac_ops;
903 unsigned int mem_map_size;
904 unsigned int txd_ptr_tbl_base;
905 unsigned int rxd_ptr_tbl_base;
906 unsigned int buf_tbl_base;
907 unsigned int evq_ptr_tbl_base;
908 unsigned int evq_rptr_tbl_base;
910 unsigned int rx_buffer_padding;
911 unsigned int max_interrupt_mode;
912 unsigned int phys_addr_channels;
913 unsigned int tx_dc_base;
914 unsigned int rx_dc_base;
915 unsigned long offload_features;
916 u32 reset_world_flags;
919 /**************************************************************************
921 * Prototypes and inline functions
923 *************************************************************************/
925 /* Iterate over all used channels */
926 #define efx_for_each_channel(_channel, _efx) \
927 for (_channel = &_efx->channel[0]; \
928 _channel < &_efx->channel[EFX_MAX_CHANNELS]; \
930 if (!_channel->used_flags) \
934 /* Iterate over all used TX queues */
935 #define efx_for_each_tx_queue(_tx_queue, _efx) \
936 for (_tx_queue = &_efx->tx_queue[0]; \
937 _tx_queue < &_efx->tx_queue[EFX_TX_QUEUE_COUNT]; \
940 /* Iterate over all TX queues belonging to a channel */
941 #define efx_for_each_channel_tx_queue(_tx_queue, _channel) \
942 for (_tx_queue = &_channel->efx->tx_queue[0]; \
943 _tx_queue < &_channel->efx->tx_queue[EFX_TX_QUEUE_COUNT]; \
945 if (_tx_queue->channel != _channel) \
949 /* Iterate over all used RX queues */
950 #define efx_for_each_rx_queue(_rx_queue, _efx) \
951 for (_rx_queue = &_efx->rx_queue[0]; \
952 _rx_queue < &_efx->rx_queue[_efx->n_rx_queues]; \
955 /* Iterate over all RX queues belonging to a channel */
956 #define efx_for_each_channel_rx_queue(_rx_queue, _channel) \
957 for (_rx_queue = &_channel->efx->rx_queue[_channel->channel]; \
960 if (_rx_queue->channel != _channel) \
964 /* Returns a pointer to the specified receive buffer in the RX
967 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
970 return (&rx_queue->buffer[index]);
973 /* Set bit in a little-endian bitfield */
974 static inline void set_bit_le(unsigned nr, unsigned char *addr)
976 addr[nr / 8] |= (1 << (nr % 8));
979 /* Clear bit in a little-endian bitfield */
980 static inline void clear_bit_le(unsigned nr, unsigned char *addr)
982 addr[nr / 8] &= ~(1 << (nr % 8));
987 * EFX_MAX_FRAME_LEN - calculate maximum frame length
989 * This calculates the maximum frame length that will be used for a
990 * given MTU. The frame length will be equal to the MTU plus a
991 * constant amount of header space and padding. This is the quantity
992 * that the net driver will program into the MAC as the maximum frame
995 * The 10G MAC requires 8-byte alignment on the frame
996 * length, so we round up to the nearest 8.
998 * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
999 * XGMII cycle). If the frame length reaches the maximum value in the
1000 * same cycle, the XMAC can miss the IPG altogether. We work around
1001 * this by adding a further 16 bytes.
1003 #define EFX_MAX_FRAME_LEN(mtu) \
1004 ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
1007 #endif /* EFX_NET_DRIVER_H */