1 /****************************************************************************
2 * Driver for Solarflare Solarstorm network controllers and boards
3 * Copyright 2005-2006 Fen Systems Ltd.
4 * Copyright 2006-2009 Solarflare Communications Inc.
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation, incorporated herein by reference.
11 #include <linux/bitops.h>
12 #include <linux/delay.h>
13 #include <linux/pci.h>
14 #include <linux/module.h>
15 #include <linux/seq_file.h>
16 #include <linux/i2c.h>
17 #include <linux/mii.h>
18 #include <linux/slab.h>
19 #include "net_driver.h"
29 #include "workarounds.h"
31 /* Hardware control for SFC4000 (aka Falcon). */
33 static const unsigned int
34 /* "Large" EEPROM device: Atmel AT25640 or similar
35 * 8 KB, 16-bit address, 32 B write block */
36 large_eeprom_type = ((13 << SPI_DEV_TYPE_SIZE_LBN)
37 | (2 << SPI_DEV_TYPE_ADDR_LEN_LBN)
38 | (5 << SPI_DEV_TYPE_BLOCK_SIZE_LBN)),
39 /* Default flash device: Atmel AT25F1024
40 * 128 KB, 24-bit address, 32 KB erase block, 256 B write block */
41 default_flash_type = ((17 << SPI_DEV_TYPE_SIZE_LBN)
42 | (3 << SPI_DEV_TYPE_ADDR_LEN_LBN)
43 | (0x52 << SPI_DEV_TYPE_ERASE_CMD_LBN)
44 | (15 << SPI_DEV_TYPE_ERASE_SIZE_LBN)
45 | (8 << SPI_DEV_TYPE_BLOCK_SIZE_LBN));
47 /**************************************************************************
49 * I2C bus - this is a bit-bashing interface using GPIO pins
50 * Note that it uses the output enables to tristate the outputs
51 * SDA is the data pin and SCL is the clock
53 **************************************************************************
55 static void falcon_setsda(void *data, int state)
57 struct efx_nic *efx = (struct efx_nic *)data;
60 efx_reado(efx, ®, FR_AB_GPIO_CTL);
61 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO3_OEN, !state);
62 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
65 static void falcon_setscl(void *data, int state)
67 struct efx_nic *efx = (struct efx_nic *)data;
70 efx_reado(efx, ®, FR_AB_GPIO_CTL);
71 EFX_SET_OWORD_FIELD(reg, FRF_AB_GPIO0_OEN, !state);
72 efx_writeo(efx, ®, FR_AB_GPIO_CTL);
75 static int falcon_getsda(void *data)
77 struct efx_nic *efx = (struct efx_nic *)data;
80 efx_reado(efx, ®, FR_AB_GPIO_CTL);
81 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO3_IN);
84 static int falcon_getscl(void *data)
86 struct efx_nic *efx = (struct efx_nic *)data;
89 efx_reado(efx, ®, FR_AB_GPIO_CTL);
90 return EFX_OWORD_FIELD(reg, FRF_AB_GPIO0_IN);
93 static struct i2c_algo_bit_data falcon_i2c_bit_operations = {
94 .setsda = falcon_setsda,
95 .setscl = falcon_setscl,
96 .getsda = falcon_getsda,
97 .getscl = falcon_getscl,
99 /* Wait up to 50 ms for slave to let us pull SCL high */
100 .timeout = DIV_ROUND_UP(HZ, 20),
103 static void falcon_push_irq_moderation(struct efx_channel *channel)
105 efx_dword_t timer_cmd;
106 struct efx_nic *efx = channel->efx;
108 /* Set timer register */
109 if (channel->irq_moderation) {
110 EFX_POPULATE_DWORD_2(timer_cmd,
111 FRF_AB_TC_TIMER_MODE,
112 FFE_BB_TIMER_MODE_INT_HLDOFF,
114 channel->irq_moderation - 1);
116 EFX_POPULATE_DWORD_2(timer_cmd,
117 FRF_AB_TC_TIMER_MODE,
118 FFE_BB_TIMER_MODE_DIS,
119 FRF_AB_TC_TIMER_VAL, 0);
121 BUILD_BUG_ON(FR_AA_TIMER_COMMAND_KER != FR_BZ_TIMER_COMMAND_P0);
122 efx_writed_page_locked(efx, &timer_cmd, FR_BZ_TIMER_COMMAND_P0,
126 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx);
128 static void falcon_prepare_flush(struct efx_nic *efx)
130 falcon_deconfigure_mac_wrapper(efx);
132 /* Wait for the tx and rx fifo's to get to the next packet boundary
133 * (~1ms without back-pressure), then to drain the remainder of the
134 * fifo's at data path speeds (negligible), with a healthy margin. */
138 /* Acknowledge a legacy interrupt from Falcon
140 * This acknowledges a legacy (not MSI) interrupt via INT_ACK_KER_REG.
142 * Due to SFC bug 3706 (silicon revision <=A1) reads can be duplicated in the
143 * BIU. Interrupt acknowledge is read sensitive so must write instead
144 * (then read to ensure the BIU collector is flushed)
146 * NB most hardware supports MSI interrupts
148 inline void falcon_irq_ack_a1(struct efx_nic *efx)
152 EFX_POPULATE_DWORD_1(reg, FRF_AA_INT_ACK_KER_FIELD, 0xb7eb7e);
153 efx_writed(efx, ®, FR_AA_INT_ACK_KER);
154 efx_readd(efx, ®, FR_AA_WORK_AROUND_BROKEN_PCI_READS);
158 irqreturn_t falcon_legacy_interrupt_a1(int irq, void *dev_id)
160 struct efx_nic *efx = dev_id;
161 efx_oword_t *int_ker = efx->irq_status.addr;
165 /* Check to see if this is our interrupt. If it isn't, we
166 * exit without having touched the hardware.
168 if (unlikely(EFX_OWORD_IS_ZERO(*int_ker))) {
169 netif_vdbg(efx, intr, efx->net_dev,
170 "IRQ %d on CPU %d not for me\n", irq,
171 raw_smp_processor_id());
174 efx->last_irq_cpu = raw_smp_processor_id();
175 netif_vdbg(efx, intr, efx->net_dev,
176 "IRQ %d on CPU %d status " EFX_OWORD_FMT "\n",
177 irq, raw_smp_processor_id(), EFX_OWORD_VAL(*int_ker));
179 /* Determine interrupting queues, clear interrupt status
180 * register and acknowledge the device interrupt.
182 BUILD_BUG_ON(FSF_AZ_NET_IVEC_INT_Q_WIDTH > EFX_MAX_CHANNELS);
183 queues = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_INT_Q);
185 /* Check to see if we have a serious error condition */
186 if (queues & (1U << efx->fatal_irq_level)) {
187 syserr = EFX_OWORD_FIELD(*int_ker, FSF_AZ_NET_IVEC_FATAL_INT);
188 if (unlikely(syserr))
189 return efx_nic_fatal_interrupt(efx);
192 EFX_ZERO_OWORD(*int_ker);
193 wmb(); /* Ensure the vector is cleared before interrupt ack */
194 falcon_irq_ack_a1(efx);
197 efx_schedule_channel(efx_get_channel(efx, 0));
199 efx_schedule_channel(efx_get_channel(efx, 1));
202 /**************************************************************************
206 **************************************************************************
209 #define FALCON_SPI_MAX_LEN sizeof(efx_oword_t)
211 static int falcon_spi_poll(struct efx_nic *efx)
214 efx_reado(efx, ®, FR_AB_EE_SPI_HCMD);
215 return EFX_OWORD_FIELD(reg, FRF_AB_EE_SPI_HCMD_CMD_EN) ? -EBUSY : 0;
218 /* Wait for SPI command completion */
219 static int falcon_spi_wait(struct efx_nic *efx)
221 /* Most commands will finish quickly, so we start polling at
222 * very short intervals. Sometimes the command may have to
223 * wait for VPD or expansion ROM access outside of our
224 * control, so we allow up to 100 ms. */
225 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 10);
228 for (i = 0; i < 10; i++) {
229 if (!falcon_spi_poll(efx))
235 if (!falcon_spi_poll(efx))
237 if (time_after_eq(jiffies, timeout)) {
238 netif_err(efx, hw, efx->net_dev,
239 "timed out waiting for SPI\n");
242 schedule_timeout_uninterruptible(1);
246 int falcon_spi_cmd(struct efx_nic *efx, const struct efx_spi_device *spi,
247 unsigned int command, int address,
248 const void *in, void *out, size_t len)
250 bool addressed = (address >= 0);
251 bool reading = (out != NULL);
255 /* Input validation */
256 if (len > FALCON_SPI_MAX_LEN)
258 BUG_ON(!mutex_is_locked(&efx->spi_lock));
260 /* Check that previous command is not still running */
261 rc = falcon_spi_poll(efx);
265 /* Program address register, if we have an address */
267 EFX_POPULATE_OWORD_1(reg, FRF_AB_EE_SPI_HADR_ADR, address);
268 efx_writeo(efx, ®, FR_AB_EE_SPI_HADR);
271 /* Program data register, if we have data */
273 memcpy(®, in, len);
274 efx_writeo(efx, ®, FR_AB_EE_SPI_HDATA);
277 /* Issue read/write command */
278 EFX_POPULATE_OWORD_7(reg,
279 FRF_AB_EE_SPI_HCMD_CMD_EN, 1,
280 FRF_AB_EE_SPI_HCMD_SF_SEL, spi->device_id,
281 FRF_AB_EE_SPI_HCMD_DABCNT, len,
282 FRF_AB_EE_SPI_HCMD_READ, reading,
283 FRF_AB_EE_SPI_HCMD_DUBCNT, 0,
284 FRF_AB_EE_SPI_HCMD_ADBCNT,
285 (addressed ? spi->addr_len : 0),
286 FRF_AB_EE_SPI_HCMD_ENC, command);
287 efx_writeo(efx, ®, FR_AB_EE_SPI_HCMD);
289 /* Wait for read/write to complete */
290 rc = falcon_spi_wait(efx);
296 efx_reado(efx, ®, FR_AB_EE_SPI_HDATA);
297 memcpy(out, ®, len);
304 falcon_spi_write_limit(const struct efx_spi_device *spi, size_t start)
306 return min(FALCON_SPI_MAX_LEN,
307 (spi->block_size - (start & (spi->block_size - 1))));
311 efx_spi_munge_command(const struct efx_spi_device *spi,
312 const u8 command, const unsigned int address)
314 return command | (((address >> 8) & spi->munge_address) << 3);
317 /* Wait up to 10 ms for buffered write completion */
319 falcon_spi_wait_write(struct efx_nic *efx, const struct efx_spi_device *spi)
321 unsigned long timeout = jiffies + 1 + DIV_ROUND_UP(HZ, 100);
326 rc = falcon_spi_cmd(efx, spi, SPI_RDSR, -1, NULL,
327 &status, sizeof(status));
330 if (!(status & SPI_STATUS_NRDY))
332 if (time_after_eq(jiffies, timeout)) {
333 netif_err(efx, hw, efx->net_dev,
334 "SPI write timeout on device %d"
335 " last status=0x%02x\n",
336 spi->device_id, status);
339 schedule_timeout_uninterruptible(1);
343 int falcon_spi_read(struct efx_nic *efx, const struct efx_spi_device *spi,
344 loff_t start, size_t len, size_t *retlen, u8 *buffer)
346 size_t block_len, pos = 0;
347 unsigned int command;
351 block_len = min(len - pos, FALCON_SPI_MAX_LEN);
353 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
354 rc = falcon_spi_cmd(efx, spi, command, start + pos, NULL,
355 buffer + pos, block_len);
360 /* Avoid locking up the system */
362 if (signal_pending(current)) {
374 falcon_spi_write(struct efx_nic *efx, const struct efx_spi_device *spi,
375 loff_t start, size_t len, size_t *retlen, const u8 *buffer)
377 u8 verify_buffer[FALCON_SPI_MAX_LEN];
378 size_t block_len, pos = 0;
379 unsigned int command;
383 rc = falcon_spi_cmd(efx, spi, SPI_WREN, -1, NULL, NULL, 0);
387 block_len = min(len - pos,
388 falcon_spi_write_limit(spi, start + pos));
389 command = efx_spi_munge_command(spi, SPI_WRITE, start + pos);
390 rc = falcon_spi_cmd(efx, spi, command, start + pos,
391 buffer + pos, NULL, block_len);
395 rc = falcon_spi_wait_write(efx, spi);
399 command = efx_spi_munge_command(spi, SPI_READ, start + pos);
400 rc = falcon_spi_cmd(efx, spi, command, start + pos,
401 NULL, verify_buffer, block_len);
402 if (memcmp(verify_buffer, buffer + pos, block_len)) {
409 /* Avoid locking up the system */
411 if (signal_pending(current)) {
422 /**************************************************************************
426 **************************************************************************
429 static void falcon_push_multicast_hash(struct efx_nic *efx)
431 union efx_multicast_hash *mc_hash = &efx->multicast_hash;
433 WARN_ON(!mutex_is_locked(&efx->mac_lock));
435 efx_writeo(efx, &mc_hash->oword[0], FR_AB_MAC_MC_HASH_REG0);
436 efx_writeo(efx, &mc_hash->oword[1], FR_AB_MAC_MC_HASH_REG1);
439 static void falcon_reset_macs(struct efx_nic *efx)
441 struct falcon_nic_data *nic_data = efx->nic_data;
442 efx_oword_t reg, mac_ctrl;
445 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0) {
446 /* It's not safe to use GLB_CTL_REG to reset the
447 * macs, so instead use the internal MAC resets
449 EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_CORE_RST, 1);
450 efx_writeo(efx, ®, FR_AB_XM_GLB_CFG);
452 for (count = 0; count < 10000; count++) {
453 efx_reado(efx, ®, FR_AB_XM_GLB_CFG);
454 if (EFX_OWORD_FIELD(reg, FRF_AB_XM_CORE_RST) ==
460 netif_err(efx, hw, efx->net_dev,
461 "timed out waiting for XMAC core reset\n");
464 /* Mac stats will fail whist the TX fifo is draining */
465 WARN_ON(nic_data->stats_disable_count == 0);
467 efx_reado(efx, &mac_ctrl, FR_AB_MAC_CTRL);
468 EFX_SET_OWORD_FIELD(mac_ctrl, FRF_BB_TXFIFO_DRAIN_EN, 1);
469 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
471 efx_reado(efx, ®, FR_AB_GLB_CTL);
472 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGTX, 1);
473 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_XGRX, 1);
474 EFX_SET_OWORD_FIELD(reg, FRF_AB_RST_EM, 1);
475 efx_writeo(efx, ®, FR_AB_GLB_CTL);
479 efx_reado(efx, ®, FR_AB_GLB_CTL);
480 if (!EFX_OWORD_FIELD(reg, FRF_AB_RST_XGTX) &&
481 !EFX_OWORD_FIELD(reg, FRF_AB_RST_XGRX) &&
482 !EFX_OWORD_FIELD(reg, FRF_AB_RST_EM)) {
483 netif_dbg(efx, hw, efx->net_dev,
484 "Completed MAC reset after %d loops\n",
489 netif_err(efx, hw, efx->net_dev, "MAC reset failed\n");
496 /* Ensure the correct MAC is selected before statistics
497 * are re-enabled by the caller */
498 efx_writeo(efx, &mac_ctrl, FR_AB_MAC_CTRL);
500 falcon_setup_xaui(efx);
503 void falcon_drain_tx_fifo(struct efx_nic *efx)
507 if ((efx_nic_rev(efx) < EFX_REV_FALCON_B0) ||
508 (efx->loopback_mode != LOOPBACK_NONE))
511 efx_reado(efx, ®, FR_AB_MAC_CTRL);
512 /* There is no point in draining more than once */
513 if (EFX_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN))
516 falcon_reset_macs(efx);
519 static void falcon_deconfigure_mac_wrapper(struct efx_nic *efx)
523 if (efx_nic_rev(efx) < EFX_REV_FALCON_B0)
526 /* Isolate the MAC -> RX */
527 efx_reado(efx, ®, FR_AZ_RX_CFG);
528 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 0);
529 efx_writeo(efx, ®, FR_AZ_RX_CFG);
531 /* Isolate TX -> MAC */
532 falcon_drain_tx_fifo(efx);
535 void falcon_reconfigure_mac_wrapper(struct efx_nic *efx)
537 struct efx_link_state *link_state = &efx->link_state;
539 int link_speed, isolate;
541 isolate = (efx->reset_pending != RESET_TYPE_NONE);
543 switch (link_state->speed) {
544 case 10000: link_speed = 3; break;
545 case 1000: link_speed = 2; break;
546 case 100: link_speed = 1; break;
547 default: link_speed = 0; break;
549 /* MAC_LINK_STATUS controls MAC backpressure but doesn't work
550 * as advertised. Disable to ensure packets are not
551 * indefinitely held and TX queue can be flushed at any point
552 * while the link is down. */
553 EFX_POPULATE_OWORD_5(reg,
554 FRF_AB_MAC_XOFF_VAL, 0xffff /* max pause time */,
555 FRF_AB_MAC_BCAD_ACPT, 1,
556 FRF_AB_MAC_UC_PROM, efx->promiscuous,
557 FRF_AB_MAC_LINK_STATUS, 1, /* always set */
558 FRF_AB_MAC_SPEED, link_speed);
559 /* On B0, MAC backpressure can be disabled and packets get
561 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
562 EFX_SET_OWORD_FIELD(reg, FRF_BB_TXFIFO_DRAIN_EN,
563 !link_state->up || isolate);
566 efx_writeo(efx, ®, FR_AB_MAC_CTRL);
568 /* Restore the multicast hash registers. */
569 falcon_push_multicast_hash(efx);
571 efx_reado(efx, ®, FR_AZ_RX_CFG);
572 /* Enable XOFF signal from RX FIFO (we enabled it during NIC
573 * initialisation but it may read back as 0) */
574 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
575 /* Unisolate the MAC -> RX */
576 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
577 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, !isolate);
578 efx_writeo(efx, ®, FR_AZ_RX_CFG);
581 static void falcon_stats_request(struct efx_nic *efx)
583 struct falcon_nic_data *nic_data = efx->nic_data;
586 WARN_ON(nic_data->stats_pending);
587 WARN_ON(nic_data->stats_disable_count);
589 if (nic_data->stats_dma_done == NULL)
590 return; /* no mac selected */
592 *nic_data->stats_dma_done = FALCON_STATS_NOT_DONE;
593 nic_data->stats_pending = true;
594 wmb(); /* ensure done flag is clear */
596 /* Initiate DMA transfer of stats */
597 EFX_POPULATE_OWORD_2(reg,
598 FRF_AB_MAC_STAT_DMA_CMD, 1,
599 FRF_AB_MAC_STAT_DMA_ADR,
600 efx->stats_buffer.dma_addr);
601 efx_writeo(efx, ®, FR_AB_MAC_STAT_DMA);
603 mod_timer(&nic_data->stats_timer, round_jiffies_up(jiffies + HZ / 2));
606 static void falcon_stats_complete(struct efx_nic *efx)
608 struct falcon_nic_data *nic_data = efx->nic_data;
610 if (!nic_data->stats_pending)
613 nic_data->stats_pending = 0;
614 if (*nic_data->stats_dma_done == FALCON_STATS_DONE) {
615 rmb(); /* read the done flag before the stats */
616 efx->mac_op->update_stats(efx);
618 netif_err(efx, hw, efx->net_dev,
619 "timed out waiting for statistics\n");
623 static void falcon_stats_timer_func(unsigned long context)
625 struct efx_nic *efx = (struct efx_nic *)context;
626 struct falcon_nic_data *nic_data = efx->nic_data;
628 spin_lock(&efx->stats_lock);
630 falcon_stats_complete(efx);
631 if (nic_data->stats_disable_count == 0)
632 falcon_stats_request(efx);
634 spin_unlock(&efx->stats_lock);
637 static bool falcon_loopback_link_poll(struct efx_nic *efx)
639 struct efx_link_state old_state = efx->link_state;
641 WARN_ON(!mutex_is_locked(&efx->mac_lock));
642 WARN_ON(!LOOPBACK_INTERNAL(efx));
644 efx->link_state.fd = true;
645 efx->link_state.fc = efx->wanted_fc;
646 efx->link_state.up = true;
647 efx->link_state.speed = 10000;
649 return !efx_link_state_equal(&efx->link_state, &old_state);
652 static int falcon_reconfigure_port(struct efx_nic *efx)
656 WARN_ON(efx_nic_rev(efx) > EFX_REV_FALCON_B0);
658 /* Poll the PHY link state *before* reconfiguring it. This means we
659 * will pick up the correct speed (in loopback) to select the correct
662 if (LOOPBACK_INTERNAL(efx))
663 falcon_loopback_link_poll(efx);
665 efx->phy_op->poll(efx);
667 falcon_stop_nic_stats(efx);
668 falcon_deconfigure_mac_wrapper(efx);
670 falcon_reset_macs(efx);
672 efx->phy_op->reconfigure(efx);
673 rc = efx->mac_op->reconfigure(efx);
676 falcon_start_nic_stats(efx);
678 /* Synchronise efx->link_state with the kernel */
679 efx_link_status_changed(efx);
684 /**************************************************************************
686 * PHY access via GMII
688 **************************************************************************
691 /* Wait for GMII access to complete */
692 static int falcon_gmii_wait(struct efx_nic *efx)
697 /* wait upto 50ms - taken max from datasheet */
698 for (count = 0; count < 5000; count++) {
699 efx_reado(efx, &md_stat, FR_AB_MD_STAT);
700 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSY) == 0) {
701 if (EFX_OWORD_FIELD(md_stat, FRF_AB_MD_LNFL) != 0 ||
702 EFX_OWORD_FIELD(md_stat, FRF_AB_MD_BSERR) != 0) {
703 netif_err(efx, hw, efx->net_dev,
704 "error from GMII access "
706 EFX_OWORD_VAL(md_stat));
713 netif_err(efx, hw, efx->net_dev, "timed out waiting for GMII\n");
717 /* Write an MDIO register of a PHY connected to Falcon. */
718 static int falcon_mdio_write(struct net_device *net_dev,
719 int prtad, int devad, u16 addr, u16 value)
721 struct efx_nic *efx = netdev_priv(net_dev);
725 netif_vdbg(efx, hw, efx->net_dev,
726 "writing MDIO %d register %d.%d with 0x%04x\n",
727 prtad, devad, addr, value);
729 mutex_lock(&efx->mdio_lock);
731 /* Check MDIO not currently being accessed */
732 rc = falcon_gmii_wait(efx);
736 /* Write the address/ID register */
737 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
738 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
740 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
741 FRF_AB_MD_DEV_ADR, devad);
742 efx_writeo(efx, ®, FR_AB_MD_ID);
745 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_TXD, value);
746 efx_writeo(efx, ®, FR_AB_MD_TXD);
748 EFX_POPULATE_OWORD_2(reg,
751 efx_writeo(efx, ®, FR_AB_MD_CS);
753 /* Wait for data to be written */
754 rc = falcon_gmii_wait(efx);
756 /* Abort the write operation */
757 EFX_POPULATE_OWORD_2(reg,
760 efx_writeo(efx, ®, FR_AB_MD_CS);
765 mutex_unlock(&efx->mdio_lock);
769 /* Read an MDIO register of a PHY connected to Falcon. */
770 static int falcon_mdio_read(struct net_device *net_dev,
771 int prtad, int devad, u16 addr)
773 struct efx_nic *efx = netdev_priv(net_dev);
777 mutex_lock(&efx->mdio_lock);
779 /* Check MDIO not currently being accessed */
780 rc = falcon_gmii_wait(efx);
784 EFX_POPULATE_OWORD_1(reg, FRF_AB_MD_PHY_ADR, addr);
785 efx_writeo(efx, ®, FR_AB_MD_PHY_ADR);
787 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_PRT_ADR, prtad,
788 FRF_AB_MD_DEV_ADR, devad);
789 efx_writeo(efx, ®, FR_AB_MD_ID);
791 /* Request data to be read */
792 EFX_POPULATE_OWORD_2(reg, FRF_AB_MD_RDC, 1, FRF_AB_MD_GC, 0);
793 efx_writeo(efx, ®, FR_AB_MD_CS);
795 /* Wait for data to become available */
796 rc = falcon_gmii_wait(efx);
798 efx_reado(efx, ®, FR_AB_MD_RXD);
799 rc = EFX_OWORD_FIELD(reg, FRF_AB_MD_RXD);
800 netif_vdbg(efx, hw, efx->net_dev,
801 "read from MDIO %d register %d.%d, got %04x\n",
802 prtad, devad, addr, rc);
804 /* Abort the read operation */
805 EFX_POPULATE_OWORD_2(reg,
808 efx_writeo(efx, ®, FR_AB_MD_CS);
810 netif_dbg(efx, hw, efx->net_dev,
811 "read from MDIO %d register %d.%d, got error %d\n",
812 prtad, devad, addr, rc);
816 mutex_unlock(&efx->mdio_lock);
820 /* This call is responsible for hooking in the MAC and PHY operations */
821 static int falcon_probe_port(struct efx_nic *efx)
823 struct falcon_nic_data *nic_data = efx->nic_data;
826 switch (efx->phy_type) {
827 case PHY_TYPE_SFX7101:
828 efx->phy_op = &falcon_sfx7101_phy_ops;
830 case PHY_TYPE_QT2022C2:
831 case PHY_TYPE_QT2025C:
832 efx->phy_op = &falcon_qt202x_phy_ops;
835 netif_err(efx, probe, efx->net_dev, "Unknown PHY type %d\n",
840 /* Fill out MDIO structure and loopback modes */
841 efx->mdio.mdio_read = falcon_mdio_read;
842 efx->mdio.mdio_write = falcon_mdio_write;
843 rc = efx->phy_op->probe(efx);
847 /* Initial assumption */
848 efx->link_state.speed = 10000;
849 efx->link_state.fd = true;
851 /* Hardware flow ctrl. FalconA RX FIFO too small for pause generation */
852 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0)
853 efx->wanted_fc = EFX_FC_RX | EFX_FC_TX;
855 efx->wanted_fc = EFX_FC_RX;
856 if (efx->mdio.mmds & MDIO_DEVS_AN)
857 efx->wanted_fc |= EFX_FC_AUTO;
859 /* Allocate buffer for stats */
860 rc = efx_nic_alloc_buffer(efx, &efx->stats_buffer,
861 FALCON_MAC_STATS_SIZE);
864 netif_dbg(efx, probe, efx->net_dev,
865 "stats buffer at %llx (virt %p phys %llx)\n",
866 (u64)efx->stats_buffer.dma_addr,
867 efx->stats_buffer.addr,
868 (u64)virt_to_phys(efx->stats_buffer.addr));
869 nic_data->stats_dma_done = efx->stats_buffer.addr + XgDmaDone_offset;
874 static void falcon_remove_port(struct efx_nic *efx)
876 efx->phy_op->remove(efx);
877 efx_nic_free_buffer(efx, &efx->stats_buffer);
880 /**************************************************************************
884 **************************************************************************/
887 falcon_read_nvram(struct efx_nic *efx, struct falcon_nvconfig *nvconfig_out)
889 struct falcon_nvconfig *nvconfig;
890 struct efx_spi_device *spi;
892 int rc, magic_num, struct_ver;
893 __le16 *word, *limit;
896 spi = efx->spi_flash ? efx->spi_flash : efx->spi_eeprom;
900 region = kmalloc(FALCON_NVCONFIG_END, GFP_KERNEL);
903 nvconfig = region + FALCON_NVCONFIG_OFFSET;
905 mutex_lock(&efx->spi_lock);
906 rc = falcon_spi_read(efx, spi, 0, FALCON_NVCONFIG_END, NULL, region);
907 mutex_unlock(&efx->spi_lock);
909 netif_err(efx, hw, efx->net_dev, "Failed to read %s\n",
910 efx->spi_flash ? "flash" : "EEPROM");
915 magic_num = le16_to_cpu(nvconfig->board_magic_num);
916 struct_ver = le16_to_cpu(nvconfig->board_struct_ver);
919 if (magic_num != FALCON_NVCONFIG_BOARD_MAGIC_NUM) {
920 netif_err(efx, hw, efx->net_dev,
921 "NVRAM bad magic 0x%x\n", magic_num);
924 if (struct_ver < 2) {
925 netif_err(efx, hw, efx->net_dev,
926 "NVRAM has ancient version 0x%x\n", struct_ver);
928 } else if (struct_ver < 4) {
929 word = &nvconfig->board_magic_num;
930 limit = (__le16 *) (nvconfig + 1);
933 limit = region + FALCON_NVCONFIG_END;
935 for (csum = 0; word < limit; ++word)
936 csum += le16_to_cpu(*word);
938 if (~csum & 0xffff) {
939 netif_err(efx, hw, efx->net_dev,
940 "NVRAM has incorrect checksum\n");
946 memcpy(nvconfig_out, nvconfig, sizeof(*nvconfig));
953 static int falcon_test_nvram(struct efx_nic *efx)
955 return falcon_read_nvram(efx, NULL);
958 static const struct efx_nic_register_test falcon_b0_register_tests[] = {
960 EFX_OWORD32(0x0003FFFF, 0x0003FFFF, 0x0003FFFF, 0x0003FFFF) },
962 EFX_OWORD32(0xFFFFFFFE, 0x00017FFF, 0x00000000, 0x00000000) },
964 EFX_OWORD32(0x7FFF0037, 0x00000000, 0x00000000, 0x00000000) },
966 EFX_OWORD32(0xFFFEFE80, 0x1FFFFFFF, 0x020000FE, 0x007FFFFF) },
968 EFX_OWORD32(0xFFFF0000, 0x00000000, 0x00000000, 0x00000000) },
969 { FR_AZ_SRM_TX_DC_CFG,
970 EFX_OWORD32(0x001FFFFF, 0x00000000, 0x00000000, 0x00000000) },
972 EFX_OWORD32(0x0000000F, 0x00000000, 0x00000000, 0x00000000) },
974 EFX_OWORD32(0x000003FF, 0x00000000, 0x00000000, 0x00000000) },
976 EFX_OWORD32(0x00000FFF, 0x00000000, 0x00000000, 0x00000000) },
978 EFX_OWORD32(0x00007337, 0x00000000, 0x00000000, 0x00000000) },
980 EFX_OWORD32(0x00001F1F, 0x00000000, 0x00000000, 0x00000000) },
982 EFX_OWORD32(0x00000C68, 0x00000000, 0x00000000, 0x00000000) },
984 EFX_OWORD32(0x00080164, 0x00000000, 0x00000000, 0x00000000) },
986 EFX_OWORD32(0x07100A0C, 0x00000000, 0x00000000, 0x00000000) },
988 EFX_OWORD32(0x00001FF8, 0x00000000, 0x00000000, 0x00000000) },
990 EFX_OWORD32(0xFFFF0001, 0x00000000, 0x00000000, 0x00000000) },
992 EFX_OWORD32(0xFFFFFFFF, 0x00000000, 0x00000000, 0x00000000) },
994 EFX_OWORD32(0x0003FF0F, 0x00000000, 0x00000000, 0x00000000) },
997 static int falcon_b0_test_registers(struct efx_nic *efx)
999 return efx_nic_test_registers(efx, falcon_b0_register_tests,
1000 ARRAY_SIZE(falcon_b0_register_tests));
1003 /**************************************************************************
1007 **************************************************************************
1010 /* Resets NIC to known state. This routine must be called in process
1011 * context and is allowed to sleep. */
1012 static int falcon_reset_hw(struct efx_nic *efx, enum reset_type method)
1014 struct falcon_nic_data *nic_data = efx->nic_data;
1015 efx_oword_t glb_ctl_reg_ker;
1018 netif_dbg(efx, hw, efx->net_dev, "performing %s hardware reset\n",
1019 RESET_TYPE(method));
1021 /* Initiate device reset */
1022 if (method == RESET_TYPE_WORLD) {
1023 rc = pci_save_state(efx->pci_dev);
1025 netif_err(efx, drv, efx->net_dev,
1026 "failed to backup PCI state of primary "
1027 "function prior to hardware reset\n");
1030 if (efx_nic_is_dual_func(efx)) {
1031 rc = pci_save_state(nic_data->pci_dev2);
1033 netif_err(efx, drv, efx->net_dev,
1034 "failed to backup PCI state of "
1035 "secondary function prior to "
1036 "hardware reset\n");
1041 EFX_POPULATE_OWORD_2(glb_ctl_reg_ker,
1042 FRF_AB_EXT_PHY_RST_DUR,
1043 FFE_AB_EXT_PHY_RST_DUR_10240US,
1046 EFX_POPULATE_OWORD_7(glb_ctl_reg_ker,
1047 /* exclude PHY from "invisible" reset */
1048 FRF_AB_EXT_PHY_RST_CTL,
1049 method == RESET_TYPE_INVISIBLE,
1050 /* exclude EEPROM/flash and PCIe */
1051 FRF_AB_PCIE_CORE_RST_CTL, 1,
1052 FRF_AB_PCIE_NSTKY_RST_CTL, 1,
1053 FRF_AB_PCIE_SD_RST_CTL, 1,
1054 FRF_AB_EE_RST_CTL, 1,
1055 FRF_AB_EXT_PHY_RST_DUR,
1056 FFE_AB_EXT_PHY_RST_DUR_10240US,
1059 efx_writeo(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1061 netif_dbg(efx, hw, efx->net_dev, "waiting for hardware reset\n");
1062 schedule_timeout_uninterruptible(HZ / 20);
1064 /* Restore PCI configuration if needed */
1065 if (method == RESET_TYPE_WORLD) {
1066 if (efx_nic_is_dual_func(efx)) {
1067 rc = pci_restore_state(nic_data->pci_dev2);
1069 netif_err(efx, drv, efx->net_dev,
1070 "failed to restore PCI config for "
1071 "the secondary function\n");
1075 rc = pci_restore_state(efx->pci_dev);
1077 netif_err(efx, drv, efx->net_dev,
1078 "failed to restore PCI config for the "
1079 "primary function\n");
1082 netif_dbg(efx, drv, efx->net_dev,
1083 "successfully restored PCI config\n");
1086 /* Assert that reset complete */
1087 efx_reado(efx, &glb_ctl_reg_ker, FR_AB_GLB_CTL);
1088 if (EFX_OWORD_FIELD(glb_ctl_reg_ker, FRF_AB_SWRST) != 0) {
1090 netif_err(efx, hw, efx->net_dev,
1091 "timed out waiting for hardware reset\n");
1094 netif_dbg(efx, hw, efx->net_dev, "hardware reset complete\n");
1098 /* pci_save_state() and pci_restore_state() MUST be called in pairs */
1101 pci_restore_state(efx->pci_dev);
1108 static void falcon_monitor(struct efx_nic *efx)
1113 BUG_ON(!mutex_is_locked(&efx->mac_lock));
1115 rc = falcon_board(efx)->type->monitor(efx);
1117 netif_err(efx, hw, efx->net_dev,
1118 "Board sensor %s; shutting down PHY\n",
1119 (rc == -ERANGE) ? "reported fault" : "failed");
1120 efx->phy_mode |= PHY_MODE_LOW_POWER;
1121 rc = __efx_reconfigure_port(efx);
1125 if (LOOPBACK_INTERNAL(efx))
1126 link_changed = falcon_loopback_link_poll(efx);
1128 link_changed = efx->phy_op->poll(efx);
1131 falcon_stop_nic_stats(efx);
1132 falcon_deconfigure_mac_wrapper(efx);
1134 falcon_reset_macs(efx);
1135 rc = efx->mac_op->reconfigure(efx);
1138 falcon_start_nic_stats(efx);
1140 efx_link_status_changed(efx);
1143 falcon_poll_xmac(efx);
1146 /* Zeroes out the SRAM contents. This routine must be called in
1147 * process context and is allowed to sleep.
1149 static int falcon_reset_sram(struct efx_nic *efx)
1151 efx_oword_t srm_cfg_reg_ker, gpio_cfg_reg_ker;
1154 /* Set the SRAM wake/sleep GPIO appropriately. */
1155 efx_reado(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1156 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OEN, 1);
1157 EFX_SET_OWORD_FIELD(gpio_cfg_reg_ker, FRF_AB_GPIO1_OUT, 1);
1158 efx_writeo(efx, &gpio_cfg_reg_ker, FR_AB_GPIO_CTL);
1160 /* Initiate SRAM reset */
1161 EFX_POPULATE_OWORD_2(srm_cfg_reg_ker,
1162 FRF_AZ_SRM_INIT_EN, 1,
1163 FRF_AZ_SRM_NB_SZ, 0);
1164 efx_writeo(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1166 /* Wait for SRAM reset to complete */
1169 netif_dbg(efx, hw, efx->net_dev,
1170 "waiting for SRAM reset (attempt %d)...\n", count);
1172 /* SRAM reset is slow; expect around 16ms */
1173 schedule_timeout_uninterruptible(HZ / 50);
1175 /* Check for reset complete */
1176 efx_reado(efx, &srm_cfg_reg_ker, FR_AZ_SRM_CFG);
1177 if (!EFX_OWORD_FIELD(srm_cfg_reg_ker, FRF_AZ_SRM_INIT_EN)) {
1178 netif_dbg(efx, hw, efx->net_dev,
1179 "SRAM reset complete\n");
1183 } while (++count < 20); /* wait upto 0.4 sec */
1185 netif_err(efx, hw, efx->net_dev, "timed out waiting for SRAM reset\n");
1189 static int falcon_spi_device_init(struct efx_nic *efx,
1190 struct efx_spi_device **spi_device_ret,
1191 unsigned int device_id, u32 device_type)
1193 struct efx_spi_device *spi_device;
1195 if (device_type != 0) {
1196 spi_device = kzalloc(sizeof(*spi_device), GFP_KERNEL);
1199 spi_device->device_id = device_id;
1201 1 << SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_SIZE);
1202 spi_device->addr_len =
1203 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ADDR_LEN);
1204 spi_device->munge_address = (spi_device->size == 1 << 9 &&
1205 spi_device->addr_len == 1);
1206 spi_device->erase_command =
1207 SPI_DEV_TYPE_FIELD(device_type, SPI_DEV_TYPE_ERASE_CMD);
1208 spi_device->erase_size =
1209 1 << SPI_DEV_TYPE_FIELD(device_type,
1210 SPI_DEV_TYPE_ERASE_SIZE);
1211 spi_device->block_size =
1212 1 << SPI_DEV_TYPE_FIELD(device_type,
1213 SPI_DEV_TYPE_BLOCK_SIZE);
1218 kfree(*spi_device_ret);
1219 *spi_device_ret = spi_device;
1223 static void falcon_remove_spi_devices(struct efx_nic *efx)
1225 kfree(efx->spi_eeprom);
1226 efx->spi_eeprom = NULL;
1227 kfree(efx->spi_flash);
1228 efx->spi_flash = NULL;
1231 /* Extract non-volatile configuration */
1232 static int falcon_probe_nvconfig(struct efx_nic *efx)
1234 struct falcon_nvconfig *nvconfig;
1238 nvconfig = kmalloc(sizeof(*nvconfig), GFP_KERNEL);
1242 rc = falcon_read_nvram(efx, nvconfig);
1243 if (rc == -EINVAL) {
1244 netif_err(efx, probe, efx->net_dev,
1245 "NVRAM is invalid therefore using defaults\n");
1246 efx->phy_type = PHY_TYPE_NONE;
1247 efx->mdio.prtad = MDIO_PRTAD_NONE;
1253 struct falcon_nvconfig_board_v2 *v2 = &nvconfig->board_v2;
1254 struct falcon_nvconfig_board_v3 *v3 = &nvconfig->board_v3;
1256 efx->phy_type = v2->port0_phy_type;
1257 efx->mdio.prtad = v2->port0_phy_addr;
1258 board_rev = le16_to_cpu(v2->board_revision);
1260 if (le16_to_cpu(nvconfig->board_struct_ver) >= 3) {
1261 rc = falcon_spi_device_init(
1262 efx, &efx->spi_flash, FFE_AB_SPI_DEVICE_FLASH,
1263 le32_to_cpu(v3->spi_device_type
1264 [FFE_AB_SPI_DEVICE_FLASH]));
1267 rc = falcon_spi_device_init(
1268 efx, &efx->spi_eeprom, FFE_AB_SPI_DEVICE_EEPROM,
1269 le32_to_cpu(v3->spi_device_type
1270 [FFE_AB_SPI_DEVICE_EEPROM]));
1276 /* Read the MAC addresses */
1277 memcpy(efx->mac_address, nvconfig->mac_address[0], ETH_ALEN);
1279 netif_dbg(efx, probe, efx->net_dev, "PHY is %d phy_id %d\n",
1280 efx->phy_type, efx->mdio.prtad);
1282 rc = falcon_probe_board(efx, board_rev);
1290 falcon_remove_spi_devices(efx);
1296 /* Probe all SPI devices on the NIC */
1297 static void falcon_probe_spi_devices(struct efx_nic *efx)
1299 efx_oword_t nic_stat, gpio_ctl, ee_vpd_cfg;
1302 efx_reado(efx, &gpio_ctl, FR_AB_GPIO_CTL);
1303 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1304 efx_reado(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1306 if (EFX_OWORD_FIELD(gpio_ctl, FRF_AB_GPIO3_PWRUP_VALUE)) {
1307 boot_dev = (EFX_OWORD_FIELD(nic_stat, FRF_AB_SF_PRST) ?
1308 FFE_AB_SPI_DEVICE_FLASH : FFE_AB_SPI_DEVICE_EEPROM);
1309 netif_dbg(efx, probe, efx->net_dev, "Booted from %s\n",
1310 boot_dev == FFE_AB_SPI_DEVICE_FLASH ?
1311 "flash" : "EEPROM");
1313 /* Disable VPD and set clock dividers to safe
1314 * values for initial programming. */
1316 netif_dbg(efx, probe, efx->net_dev,
1317 "Booted from internal ASIC settings;"
1318 " setting SPI config\n");
1319 EFX_POPULATE_OWORD_3(ee_vpd_cfg, FRF_AB_EE_VPD_EN, 0,
1320 /* 125 MHz / 7 ~= 20 MHz */
1321 FRF_AB_EE_SF_CLOCK_DIV, 7,
1322 /* 125 MHz / 63 ~= 2 MHz */
1323 FRF_AB_EE_EE_CLOCK_DIV, 63);
1324 efx_writeo(efx, &ee_vpd_cfg, FR_AB_EE_VPD_CFG0);
1327 if (boot_dev == FFE_AB_SPI_DEVICE_FLASH)
1328 falcon_spi_device_init(efx, &efx->spi_flash,
1329 FFE_AB_SPI_DEVICE_FLASH,
1330 default_flash_type);
1331 if (boot_dev == FFE_AB_SPI_DEVICE_EEPROM)
1332 falcon_spi_device_init(efx, &efx->spi_eeprom,
1333 FFE_AB_SPI_DEVICE_EEPROM,
1337 static int falcon_probe_nic(struct efx_nic *efx)
1339 struct falcon_nic_data *nic_data;
1340 struct falcon_board *board;
1343 /* Allocate storage for hardware specific data */
1344 nic_data = kzalloc(sizeof(*nic_data), GFP_KERNEL);
1347 efx->nic_data = nic_data;
1351 if (efx_nic_fpga_ver(efx) != 0) {
1352 netif_err(efx, probe, efx->net_dev,
1353 "Falcon FPGA not supported\n");
1357 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1358 efx_oword_t nic_stat;
1359 struct pci_dev *dev;
1360 u8 pci_rev = efx->pci_dev->revision;
1362 if ((pci_rev == 0xff) || (pci_rev == 0)) {
1363 netif_err(efx, probe, efx->net_dev,
1364 "Falcon rev A0 not supported\n");
1367 efx_reado(efx, &nic_stat, FR_AB_NIC_STAT);
1368 if (EFX_OWORD_FIELD(nic_stat, FRF_AB_STRAP_10G) == 0) {
1369 netif_err(efx, probe, efx->net_dev,
1370 "Falcon rev A1 1G not supported\n");
1373 if (EFX_OWORD_FIELD(nic_stat, FRF_AA_STRAP_PCIE) == 0) {
1374 netif_err(efx, probe, efx->net_dev,
1375 "Falcon rev A1 PCI-X not supported\n");
1379 dev = pci_dev_get(efx->pci_dev);
1380 while ((dev = pci_get_device(EFX_VENDID_SFC, FALCON_A_S_DEVID,
1382 if (dev->bus == efx->pci_dev->bus &&
1383 dev->devfn == efx->pci_dev->devfn + 1) {
1384 nic_data->pci_dev2 = dev;
1388 if (!nic_data->pci_dev2) {
1389 netif_err(efx, probe, efx->net_dev,
1390 "failed to find secondary function\n");
1396 /* Now we can reset the NIC */
1397 rc = falcon_reset_hw(efx, RESET_TYPE_ALL);
1399 netif_err(efx, probe, efx->net_dev, "failed to reset NIC\n");
1403 /* Allocate memory for INT_KER */
1404 rc = efx_nic_alloc_buffer(efx, &efx->irq_status, sizeof(efx_oword_t));
1407 BUG_ON(efx->irq_status.dma_addr & 0x0f);
1409 netif_dbg(efx, probe, efx->net_dev,
1410 "INT_KER at %llx (virt %p phys %llx)\n",
1411 (u64)efx->irq_status.dma_addr,
1412 efx->irq_status.addr,
1413 (u64)virt_to_phys(efx->irq_status.addr));
1415 falcon_probe_spi_devices(efx);
1417 /* Read in the non-volatile configuration */
1418 rc = falcon_probe_nvconfig(efx);
1422 /* Initialise I2C adapter */
1423 board = falcon_board(efx);
1424 board->i2c_adap.owner = THIS_MODULE;
1425 board->i2c_data = falcon_i2c_bit_operations;
1426 board->i2c_data.data = efx;
1427 board->i2c_adap.algo_data = &board->i2c_data;
1428 board->i2c_adap.dev.parent = &efx->pci_dev->dev;
1429 strlcpy(board->i2c_adap.name, "SFC4000 GPIO",
1430 sizeof(board->i2c_adap.name));
1431 rc = i2c_bit_add_bus(&board->i2c_adap);
1435 rc = falcon_board(efx)->type->init(efx);
1437 netif_err(efx, probe, efx->net_dev,
1438 "failed to initialise board\n");
1442 nic_data->stats_disable_count = 1;
1443 setup_timer(&nic_data->stats_timer, &falcon_stats_timer_func,
1444 (unsigned long)efx);
1449 BUG_ON(i2c_del_adapter(&board->i2c_adap));
1450 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1452 falcon_remove_spi_devices(efx);
1453 efx_nic_free_buffer(efx, &efx->irq_status);
1456 if (nic_data->pci_dev2) {
1457 pci_dev_put(nic_data->pci_dev2);
1458 nic_data->pci_dev2 = NULL;
1462 kfree(efx->nic_data);
1466 static void falcon_init_rx_cfg(struct efx_nic *efx)
1468 /* Prior to Siena the RX DMA engine will split each frame at
1469 * intervals of RX_USR_BUF_SIZE (32-byte units). We set it to
1470 * be so large that that never happens. */
1471 const unsigned huge_buf_size = (3 * 4096) >> 5;
1472 /* RX control FIFO thresholds (32 entries) */
1473 const unsigned ctrl_xon_thr = 20;
1474 const unsigned ctrl_xoff_thr = 25;
1475 /* RX data FIFO thresholds (256-byte units; size varies) */
1476 int data_xon_thr = efx_nic_rx_xon_thresh >> 8;
1477 int data_xoff_thr = efx_nic_rx_xoff_thresh >> 8;
1480 efx_reado(efx, ®, FR_AZ_RX_CFG);
1481 if (efx_nic_rev(efx) <= EFX_REV_FALCON_A1) {
1482 /* Data FIFO size is 5.5K */
1483 if (data_xon_thr < 0)
1484 data_xon_thr = 512 >> 8;
1485 if (data_xoff_thr < 0)
1486 data_xoff_thr = 2048 >> 8;
1487 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_DESC_PUSH_EN, 0);
1488 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_USR_BUF_SIZE,
1490 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_MAC_TH, data_xon_thr);
1491 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_MAC_TH, data_xoff_thr);
1492 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XON_TX_TH, ctrl_xon_thr);
1493 EFX_SET_OWORD_FIELD(reg, FRF_AA_RX_XOFF_TX_TH, ctrl_xoff_thr);
1495 /* Data FIFO size is 80K; register fields moved */
1496 if (data_xon_thr < 0)
1497 data_xon_thr = 27648 >> 8; /* ~3*max MTU */
1498 if (data_xoff_thr < 0)
1499 data_xoff_thr = 54272 >> 8; /* ~80Kb - 3*max MTU */
1500 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_DESC_PUSH_EN, 0);
1501 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_USR_BUF_SIZE,
1503 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_MAC_TH, data_xon_thr);
1504 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_MAC_TH, data_xoff_thr);
1505 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XON_TX_TH, ctrl_xon_thr);
1506 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_XOFF_TX_TH, ctrl_xoff_thr);
1507 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_INGR_EN, 1);
1509 /* Enable hash insertion. This is broken for the
1510 * 'Falcon' hash so also select Toeplitz TCP/IPv4 and
1512 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_INSRT_HDR, 1);
1513 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_HASH_ALG, 1);
1514 EFX_SET_OWORD_FIELD(reg, FRF_BZ_RX_IP_HASH, 1);
1516 /* Always enable XOFF signal from RX FIFO. We enable
1517 * or disable transmission of pause frames at the MAC. */
1518 EFX_SET_OWORD_FIELD(reg, FRF_AZ_RX_XOFF_MAC_EN, 1);
1519 efx_writeo(efx, ®, FR_AZ_RX_CFG);
1522 /* This call performs hardware-specific global initialisation, such as
1523 * defining the descriptor cache sizes and number of RSS channels.
1524 * It does not set up any buffers, descriptor rings or event queues.
1526 static int falcon_init_nic(struct efx_nic *efx)
1531 /* Use on-chip SRAM */
1532 efx_reado(efx, &temp, FR_AB_NIC_STAT);
1533 EFX_SET_OWORD_FIELD(temp, FRF_AB_ONCHIP_SRAM, 1);
1534 efx_writeo(efx, &temp, FR_AB_NIC_STAT);
1536 rc = falcon_reset_sram(efx);
1540 /* Clear the parity enables on the TX data fifos as
1541 * they produce false parity errors because of timing issues
1543 if (EFX_WORKAROUND_5129(efx)) {
1544 efx_reado(efx, &temp, FR_AZ_CSR_SPARE);
1545 EFX_SET_OWORD_FIELD(temp, FRF_AB_MEM_PERR_EN_TX_DATA, 0);
1546 efx_writeo(efx, &temp, FR_AZ_CSR_SPARE);
1549 if (EFX_WORKAROUND_7244(efx)) {
1550 efx_reado(efx, &temp, FR_BZ_RX_FILTER_CTL);
1551 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_FULL_SRCH_LIMIT, 8);
1552 EFX_SET_OWORD_FIELD(temp, FRF_BZ_UDP_WILD_SRCH_LIMIT, 8);
1553 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_FULL_SRCH_LIMIT, 8);
1554 EFX_SET_OWORD_FIELD(temp, FRF_BZ_TCP_WILD_SRCH_LIMIT, 8);
1555 efx_writeo(efx, &temp, FR_BZ_RX_FILTER_CTL);
1558 /* XXX This is documented only for Falcon A0/A1 */
1559 /* Setup RX. Wait for descriptor is broken and must
1560 * be disabled. RXDP recovery shouldn't be needed, but is.
1562 efx_reado(efx, &temp, FR_AA_RX_SELF_RST);
1563 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_NODESC_WAIT_DIS, 1);
1564 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_SELF_RST_EN, 1);
1565 if (EFX_WORKAROUND_5583(efx))
1566 EFX_SET_OWORD_FIELD(temp, FRF_AA_RX_ISCSI_DIS, 1);
1567 efx_writeo(efx, &temp, FR_AA_RX_SELF_RST);
1569 /* Do not enable TX_NO_EOP_DISC_EN, since it limits packets to 16
1570 * descriptors (which is bad).
1572 efx_reado(efx, &temp, FR_AZ_TX_CFG);
1573 EFX_SET_OWORD_FIELD(temp, FRF_AZ_TX_NO_EOP_DISC_EN, 0);
1574 efx_writeo(efx, &temp, FR_AZ_TX_CFG);
1576 falcon_init_rx_cfg(efx);
1578 if (efx_nic_rev(efx) >= EFX_REV_FALCON_B0) {
1579 /* Set hash key for IPv4 */
1580 memcpy(&temp, efx->rx_hash_key, sizeof(temp));
1581 efx_writeo(efx, &temp, FR_BZ_RX_RSS_TKEY);
1583 /* Set destination of both TX and RX Flush events */
1584 EFX_POPULATE_OWORD_1(temp, FRF_BZ_FLS_EVQ_ID, 0);
1585 efx_writeo(efx, &temp, FR_BZ_DP_CTRL);
1588 efx_nic_init_common(efx);
1593 static void falcon_remove_nic(struct efx_nic *efx)
1595 struct falcon_nic_data *nic_data = efx->nic_data;
1596 struct falcon_board *board = falcon_board(efx);
1599 board->type->fini(efx);
1601 /* Remove I2C adapter and clear it in preparation for a retry */
1602 rc = i2c_del_adapter(&board->i2c_adap);
1604 memset(&board->i2c_adap, 0, sizeof(board->i2c_adap));
1606 falcon_remove_spi_devices(efx);
1607 efx_nic_free_buffer(efx, &efx->irq_status);
1609 falcon_reset_hw(efx, RESET_TYPE_ALL);
1611 /* Release the second function after the reset */
1612 if (nic_data->pci_dev2) {
1613 pci_dev_put(nic_data->pci_dev2);
1614 nic_data->pci_dev2 = NULL;
1617 /* Tear down the private nic state */
1618 kfree(efx->nic_data);
1619 efx->nic_data = NULL;
1622 static void falcon_update_nic_stats(struct efx_nic *efx)
1624 struct falcon_nic_data *nic_data = efx->nic_data;
1627 if (nic_data->stats_disable_count)
1630 efx_reado(efx, &cnt, FR_AZ_RX_NODESC_DROP);
1631 efx->n_rx_nodesc_drop_cnt +=
1632 EFX_OWORD_FIELD(cnt, FRF_AB_RX_NODESC_DROP_CNT);
1634 if (nic_data->stats_pending &&
1635 *nic_data->stats_dma_done == FALCON_STATS_DONE) {
1636 nic_data->stats_pending = false;
1637 rmb(); /* read the done flag before the stats */
1638 efx->mac_op->update_stats(efx);
1642 void falcon_start_nic_stats(struct efx_nic *efx)
1644 struct falcon_nic_data *nic_data = efx->nic_data;
1646 spin_lock_bh(&efx->stats_lock);
1647 if (--nic_data->stats_disable_count == 0)
1648 falcon_stats_request(efx);
1649 spin_unlock_bh(&efx->stats_lock);
1652 void falcon_stop_nic_stats(struct efx_nic *efx)
1654 struct falcon_nic_data *nic_data = efx->nic_data;
1659 spin_lock_bh(&efx->stats_lock);
1660 ++nic_data->stats_disable_count;
1661 spin_unlock_bh(&efx->stats_lock);
1663 del_timer_sync(&nic_data->stats_timer);
1665 /* Wait enough time for the most recent transfer to
1667 for (i = 0; i < 4 && nic_data->stats_pending; i++) {
1668 if (*nic_data->stats_dma_done == FALCON_STATS_DONE)
1673 spin_lock_bh(&efx->stats_lock);
1674 falcon_stats_complete(efx);
1675 spin_unlock_bh(&efx->stats_lock);
1678 static void falcon_set_id_led(struct efx_nic *efx, enum efx_led_mode mode)
1680 falcon_board(efx)->type->set_id_led(efx, mode);
1683 /**************************************************************************
1687 **************************************************************************
1690 static void falcon_get_wol(struct efx_nic *efx, struct ethtool_wolinfo *wol)
1694 memset(&wol->sopass, 0, sizeof(wol->sopass));
1697 static int falcon_set_wol(struct efx_nic *efx, u32 type)
1704 /**************************************************************************
1706 * Revision-dependent attributes used by efx.c and nic.c
1708 **************************************************************************
1711 struct efx_nic_type falcon_a1_nic_type = {
1712 .probe = falcon_probe_nic,
1713 .remove = falcon_remove_nic,
1714 .init = falcon_init_nic,
1715 .fini = efx_port_dummy_op_void,
1716 .monitor = falcon_monitor,
1717 .reset = falcon_reset_hw,
1718 .probe_port = falcon_probe_port,
1719 .remove_port = falcon_remove_port,
1720 .prepare_flush = falcon_prepare_flush,
1721 .update_stats = falcon_update_nic_stats,
1722 .start_stats = falcon_start_nic_stats,
1723 .stop_stats = falcon_stop_nic_stats,
1724 .set_id_led = falcon_set_id_led,
1725 .push_irq_moderation = falcon_push_irq_moderation,
1726 .push_multicast_hash = falcon_push_multicast_hash,
1727 .reconfigure_port = falcon_reconfigure_port,
1728 .get_wol = falcon_get_wol,
1729 .set_wol = falcon_set_wol,
1730 .resume_wol = efx_port_dummy_op_void,
1731 .test_nvram = falcon_test_nvram,
1732 .default_mac_ops = &falcon_xmac_operations,
1734 .revision = EFX_REV_FALCON_A1,
1735 .mem_map_size = 0x20000,
1736 .txd_ptr_tbl_base = FR_AA_TX_DESC_PTR_TBL_KER,
1737 .rxd_ptr_tbl_base = FR_AA_RX_DESC_PTR_TBL_KER,
1738 .buf_tbl_base = FR_AA_BUF_FULL_TBL_KER,
1739 .evq_ptr_tbl_base = FR_AA_EVQ_PTR_TBL_KER,
1740 .evq_rptr_tbl_base = FR_AA_EVQ_RPTR_KER,
1741 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1742 .rx_buffer_padding = 0x24,
1743 .max_interrupt_mode = EFX_INT_MODE_MSI,
1744 .phys_addr_channels = 4,
1745 .tx_dc_base = 0x130000,
1746 .rx_dc_base = 0x100000,
1747 .offload_features = NETIF_F_IP_CSUM,
1748 .reset_world_flags = ETH_RESET_IRQ,
1751 struct efx_nic_type falcon_b0_nic_type = {
1752 .probe = falcon_probe_nic,
1753 .remove = falcon_remove_nic,
1754 .init = falcon_init_nic,
1755 .fini = efx_port_dummy_op_void,
1756 .monitor = falcon_monitor,
1757 .reset = falcon_reset_hw,
1758 .probe_port = falcon_probe_port,
1759 .remove_port = falcon_remove_port,
1760 .prepare_flush = falcon_prepare_flush,
1761 .update_stats = falcon_update_nic_stats,
1762 .start_stats = falcon_start_nic_stats,
1763 .stop_stats = falcon_stop_nic_stats,
1764 .set_id_led = falcon_set_id_led,
1765 .push_irq_moderation = falcon_push_irq_moderation,
1766 .push_multicast_hash = falcon_push_multicast_hash,
1767 .reconfigure_port = falcon_reconfigure_port,
1768 .get_wol = falcon_get_wol,
1769 .set_wol = falcon_set_wol,
1770 .resume_wol = efx_port_dummy_op_void,
1771 .test_registers = falcon_b0_test_registers,
1772 .test_nvram = falcon_test_nvram,
1773 .default_mac_ops = &falcon_xmac_operations,
1775 .revision = EFX_REV_FALCON_B0,
1776 /* Map everything up to and including the RSS indirection
1777 * table. Don't map MSI-X table, MSI-X PBA since Linux
1778 * requires that they not be mapped. */
1779 .mem_map_size = (FR_BZ_RX_INDIRECTION_TBL +
1780 FR_BZ_RX_INDIRECTION_TBL_STEP *
1781 FR_BZ_RX_INDIRECTION_TBL_ROWS),
1782 .txd_ptr_tbl_base = FR_BZ_TX_DESC_PTR_TBL,
1783 .rxd_ptr_tbl_base = FR_BZ_RX_DESC_PTR_TBL,
1784 .buf_tbl_base = FR_BZ_BUF_FULL_TBL,
1785 .evq_ptr_tbl_base = FR_BZ_EVQ_PTR_TBL,
1786 .evq_rptr_tbl_base = FR_BZ_EVQ_RPTR,
1787 .max_dma_mask = DMA_BIT_MASK(FSF_AZ_TX_KER_BUF_ADDR_WIDTH),
1788 .rx_buffer_hash_size = 0x10,
1789 .rx_buffer_padding = 0,
1790 .max_interrupt_mode = EFX_INT_MODE_MSIX,
1791 .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
1792 * interrupt handler only supports 32
1794 .tx_dc_base = 0x130000,
1795 .rx_dc_base = 0x100000,
1796 .offload_features = NETIF_F_IP_CSUM | NETIF_F_RXHASH | NETIF_F_NTUPLE,
1797 .reset_world_flags = ETH_RESET_IRQ,