drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/firmware.h>
  29 #include <linux/pci-aspm.h>
  30 #include <linux/prefetch.h>
  31
  32 #include <asm/system.h>
  33 #include <asm/io.h>
  34 #include <asm/irq.h>
  35
  36 #define RTL8169_VERSION "2.3LK-NAPI"
  37 #define MODULENAME "r8169"
  38 #define PFX MODULENAME ": "
  39
  40 #define FIRMWARE_8168D_1        "rtl_nic/rtl8168d-1.fw"
  41 #define FIRMWARE_8168D_2        "rtl_nic/rtl8168d-2.fw"
  42 #define FIRMWARE_8168E_1        "rtl_nic/rtl8168e-1.fw"
  43 #define FIRMWARE_8168E_2        "rtl_nic/rtl8168e-2.fw"
  44 #define FIRMWARE_8105E_1        "rtl_nic/rtl8105e-1.fw"
  45
  46 #ifdef RTL8169_DEBUG
  47 #define assert(expr) \
  48         if (!(expr)) {                                  \
  49                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  50                 #expr,__FILE__,__func__,__LINE__);              \
  51         }
  52 #define dprintk(fmt, args...) \
  53         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  54 #else
  55 #define assert(expr) do {} while (0)
  56 #define dprintk(fmt, args...)   do {} while (0)
  57 #endif /* RTL8169_DEBUG */
  58
  59 #define R8169_MSG_DEFAULT \
  60         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  61
  62 #define TX_BUFFS_AVAIL(tp) \
  63         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  64
  65 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  66    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  67 static const int multicast_filter_limit = 32;
  68
  69 /* MAC address length */
  70 #define MAC_ADDR_LEN    6
  71
  72 #define MAX_READ_REQUEST_SHIFT  12
  73 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  74 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  75 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  76 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  77 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  78
  79 #define R8169_REGS_SIZE         256
  80 #define R8169_NAPI_WEIGHT       64
  81 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  82 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  83 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  84 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  85 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  86
  87 #define RTL8169_TX_TIMEOUT      (6*HZ)
  88 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  89
  90 #define RTL_EEPROM_SIG          cpu_to_le32(0x8129)
  91 #define RTL_EEPROM_SIG_MASK     cpu_to_le32(0xffff)
  92 #define RTL_EEPROM_SIG_ADDR     0x0000
  93
  94 /* write/read MMIO register */
  95 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  96 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  97 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  98 #define RTL_R8(reg)             readb (ioaddr + (reg))
  99 #define RTL_R16(reg)            readw (ioaddr + (reg))
 100 #define RTL_R32(reg)            readl (ioaddr + (reg))
 101
 102 enum mac_version {
 103         RTL_GIGA_MAC_VER_01 = 0,
 104         RTL_GIGA_MAC_VER_02,
 105         RTL_GIGA_MAC_VER_03,
 106         RTL_GIGA_MAC_VER_04,
 107         RTL_GIGA_MAC_VER_05,
 108         RTL_GIGA_MAC_VER_06,
 109         RTL_GIGA_MAC_VER_07,
 110         RTL_GIGA_MAC_VER_08,
 111         RTL_GIGA_MAC_VER_09,
 112         RTL_GIGA_MAC_VER_10,
 113         RTL_GIGA_MAC_VER_11,
 114         RTL_GIGA_MAC_VER_12,
 115         RTL_GIGA_MAC_VER_13,
 116         RTL_GIGA_MAC_VER_14,
 117         RTL_GIGA_MAC_VER_15,
 118         RTL_GIGA_MAC_VER_16,
 119         RTL_GIGA_MAC_VER_17,
 120         RTL_GIGA_MAC_VER_18,
 121         RTL_GIGA_MAC_VER_19,
 122         RTL_GIGA_MAC_VER_20,
 123         RTL_GIGA_MAC_VER_21,
 124         RTL_GIGA_MAC_VER_22,
 125         RTL_GIGA_MAC_VER_23,
 126         RTL_GIGA_MAC_VER_24,
 127         RTL_GIGA_MAC_VER_25,
 128         RTL_GIGA_MAC_VER_26,
 129         RTL_GIGA_MAC_VER_27,
 130         RTL_GIGA_MAC_VER_28,
 131         RTL_GIGA_MAC_VER_29,
 132         RTL_GIGA_MAC_VER_30,
 133         RTL_GIGA_MAC_VER_31,
 134         RTL_GIGA_MAC_VER_32,
 135         RTL_GIGA_MAC_VER_33,
 136         RTL_GIGA_MAC_NONE   = 0xff,
 137 };
 138
 139 enum rtl_tx_desc_version {
 140         RTL_TD_0        = 0,
 141         RTL_TD_1        = 1,
 142 };
 143
 144 #define _R(NAME,TD,FW) \
 145         { .name = NAME, .txd_version = TD, .fw_name = FW }
 146
 147 static const struct {
 148         const char *name;
 149         enum rtl_tx_desc_version txd_version;
 150         const char *fw_name;
 151 } rtl_chip_infos[] = {
 152         /* PCI devices. */
 153         [RTL_GIGA_MAC_VER_01] =
 154                 _R("RTL8169",           RTL_TD_0, NULL),
 155         [RTL_GIGA_MAC_VER_02] =
 156                 _R("RTL8169s",          RTL_TD_0, NULL),
 157         [RTL_GIGA_MAC_VER_03] =
 158                 _R("RTL8110s",          RTL_TD_0, NULL),
 159         [RTL_GIGA_MAC_VER_04] =
 160                 _R("RTL8169sb/8110sb",  RTL_TD_0, NULL),
 161         [RTL_GIGA_MAC_VER_05] =
 162                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 163         [RTL_GIGA_MAC_VER_06] =
 164                 _R("RTL8169sc/8110sc",  RTL_TD_0, NULL),
 165         /* PCI-E devices. */
 166         [RTL_GIGA_MAC_VER_07] =
 167                 _R("RTL8102e",          RTL_TD_1, NULL),
 168         [RTL_GIGA_MAC_VER_08] =
 169                 _R("RTL8102e",          RTL_TD_1, NULL),
 170         [RTL_GIGA_MAC_VER_09] =
 171                 _R("RTL8102e",          RTL_TD_1, NULL),
 172         [RTL_GIGA_MAC_VER_10] =
 173                 _R("RTL8101e",          RTL_TD_0, NULL),
 174         [RTL_GIGA_MAC_VER_11] =
 175                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 176         [RTL_GIGA_MAC_VER_12] =
 177                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 178         [RTL_GIGA_MAC_VER_13] =
 179                 _R("RTL8101e",          RTL_TD_0, NULL),
 180         [RTL_GIGA_MAC_VER_14] =
 181                 _R("RTL8100e",          RTL_TD_0, NULL),
 182         [RTL_GIGA_MAC_VER_15] =
 183                 _R("RTL8100e",          RTL_TD_0, NULL),
 184         [RTL_GIGA_MAC_VER_16] =
 185                 _R("RTL8101e",          RTL_TD_0, NULL),
 186         [RTL_GIGA_MAC_VER_17] =
 187                 _R("RTL8168b/8111b",    RTL_TD_0, NULL),
 188         [RTL_GIGA_MAC_VER_18] =
 189                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 190         [RTL_GIGA_MAC_VER_19] =
 191                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 192         [RTL_GIGA_MAC_VER_20] =
 193                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 194         [RTL_GIGA_MAC_VER_21] =
 195                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 196         [RTL_GIGA_MAC_VER_22] =
 197                 _R("RTL8168c/8111c",    RTL_TD_1, NULL),
 198         [RTL_GIGA_MAC_VER_23] =
 199                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 200         [RTL_GIGA_MAC_VER_24] =
 201                 _R("RTL8168cp/8111cp",  RTL_TD_1, NULL),
 202         [RTL_GIGA_MAC_VER_25] =
 203                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_1),
 204         [RTL_GIGA_MAC_VER_26] =
 205                 _R("RTL8168d/8111d",    RTL_TD_1, FIRMWARE_8168D_2),
 206         [RTL_GIGA_MAC_VER_27] =
 207                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 208         [RTL_GIGA_MAC_VER_28] =
 209                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 210         [RTL_GIGA_MAC_VER_29] =
 211                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 212         [RTL_GIGA_MAC_VER_30] =
 213                 _R("RTL8105e",          RTL_TD_1, FIRMWARE_8105E_1),
 214         [RTL_GIGA_MAC_VER_31] =
 215                 _R("RTL8168dp/8111dp",  RTL_TD_1, NULL),
 216         [RTL_GIGA_MAC_VER_32] =
 217                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_1),
 218         [RTL_GIGA_MAC_VER_33] =
 219                 _R("RTL8168e/8111e",    RTL_TD_1, FIRMWARE_8168E_2)
 220 };
 221 #undef _R
 222
 223 enum cfg_version {
 224         RTL_CFG_0 = 0x00,
 225         RTL_CFG_1,
 226         RTL_CFG_2
 227 };
 228
 229 static void rtl_hw_start_8169(struct net_device *);
 230 static void rtl_hw_start_8168(struct net_device *);
 231 static void rtl_hw_start_8101(struct net_device *);
 232
 233 static DEFINE_PCI_DEVICE_TABLE(rtl8169_pci_tbl) = {
 234         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 235         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 236         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 237         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 238         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 239         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 240         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 241         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 242         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 243                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 244         { 0x0001,                               0x8168,
 245                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 246         {0,},
 247 };
 248
 249 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 250
 251 static int rx_buf_sz = 16383;
 252 static int use_dac;
 253 static struct {
 254         u32 msg_enable;
 255 } debug = { -1 };
 256
 257 enum rtl_registers {
 258         MAC0            = 0,    /* Ethernet hardware address. */
 259         MAC4            = 4,
 260         MAR0            = 8,    /* Multicast filter. */
 261         CounterAddrLow          = 0x10,
 262         CounterAddrHigh         = 0x14,
 263         TxDescStartAddrLow      = 0x20,
 264         TxDescStartAddrHigh     = 0x24,
 265         TxHDescStartAddrLow     = 0x28,
 266         TxHDescStartAddrHigh    = 0x2c,
 267         FLASH           = 0x30,
 268         ERSR            = 0x36,
 269         ChipCmd         = 0x37,
 270         TxPoll          = 0x38,
 271         IntrMask        = 0x3c,
 272         IntrStatus      = 0x3e,
 273         TxConfig        = 0x40,
 274         RxConfig        = 0x44,
 275
 276 #define RTL_RX_CONFIG_MASK              0xff7e1880u
 277
 278         RxMissed        = 0x4c,
 279         Cfg9346         = 0x50,
 280         Config0         = 0x51,
 281         Config1         = 0x52,
 282         Config2         = 0x53,
 283         Config3         = 0x54,
 284         Config4         = 0x55,
 285         Config5         = 0x56,
 286         MultiIntr       = 0x5c,
 287         PHYAR           = 0x60,
 288         PHYstatus       = 0x6c,
 289         RxMaxSize       = 0xda,
 290         CPlusCmd        = 0xe0,
 291         IntrMitigate    = 0xe2,
 292         RxDescAddrLow   = 0xe4,
 293         RxDescAddrHigh  = 0xe8,
 294         EarlyTxThres    = 0xec, /* 8169. Unit of 32 bytes. */
 295
 296 #define NoEarlyTx       0x3f    /* Max value : no early transmit. */
 297
 298         MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
 299
 300 #define TxPacketMax     (8064 >> 7)
 301
 302         FuncEvent       = 0xf0,
 303         FuncEventMask   = 0xf4,
 304         FuncPresetState = 0xf8,
 305         FuncForceEvent  = 0xfc,
 306 };
 307
 308 enum rtl8110_registers {
 309         TBICSR                  = 0x64,
 310         TBI_ANAR                = 0x68,
 311         TBI_LPAR                = 0x6a,
 312 };
 313
 314 enum rtl8168_8101_registers {
 315         CSIDR                   = 0x64,
 316         CSIAR                   = 0x68,
 317 #define CSIAR_FLAG                      0x80000000
 318 #define CSIAR_WRITE_CMD                 0x80000000
 319 #define CSIAR_BYTE_ENABLE               0x0f
 320 #define CSIAR_BYTE_ENABLE_SHIFT         12
 321 #define CSIAR_ADDR_MASK                 0x0fff
 322         PMCH                    = 0x6f,
 323         EPHYAR                  = 0x80,
 324 #define EPHYAR_FLAG                     0x80000000
 325 #define EPHYAR_WRITE_CMD                0x80000000
 326 #define EPHYAR_REG_MASK                 0x1f
 327 #define EPHYAR_REG_SHIFT                16
 328 #define EPHYAR_DATA_MASK                0xffff
 329         DLLPR                   = 0xd0,
 330 #define PM_SWITCH                       (1 << 6)
 331         DBG_REG                 = 0xd1,
 332 #define FIX_NAK_1                       (1 << 4)
 333 #define FIX_NAK_2                       (1 << 3)
 334         TWSI                    = 0xd2,
 335         MCU                     = 0xd3,
 336 #define EN_NDP                          (1 << 3)
 337 #define EN_OOB_RESET                    (1 << 2)
 338         EFUSEAR                 = 0xdc,
 339 #define EFUSEAR_FLAG                    0x80000000
 340 #define EFUSEAR_WRITE_CMD               0x80000000
 341 #define EFUSEAR_READ_CMD                0x00000000
 342 #define EFUSEAR_REG_MASK                0x03ff
 343 #define EFUSEAR_REG_SHIFT               8
 344 #define EFUSEAR_DATA_MASK               0xff
 345 };
 346
 347 enum rtl8168_registers {
 348         ERIDR                   = 0x70,
 349         ERIAR                   = 0x74,
 350 #define ERIAR_FLAG                      0x80000000
 351 #define ERIAR_WRITE_CMD                 0x80000000
 352 #define ERIAR_READ_CMD                  0x00000000
 353 #define ERIAR_ADDR_BYTE_ALIGN           4
 354 #define ERIAR_EXGMAC                    0
 355 #define ERIAR_MSIX                      1
 356 #define ERIAR_ASF                       2
 357 #define ERIAR_TYPE_SHIFT                16
 358 #define ERIAR_BYTEEN                    0x0f
 359 #define ERIAR_BYTEEN_SHIFT              12
 360         EPHY_RXER_NUM           = 0x7c,
 361         OCPDR                   = 0xb0, /* OCP GPHY access */
 362 #define OCPDR_WRITE_CMD                 0x80000000
 363 #define OCPDR_READ_CMD                  0x00000000
 364 #define OCPDR_REG_MASK                  0x7f
 365 #define OCPDR_GPHY_REG_SHIFT            16
 366 #define OCPDR_DATA_MASK                 0xffff
 367         OCPAR                   = 0xb4,
 368 #define OCPAR_FLAG                      0x80000000
 369 #define OCPAR_GPHY_WRITE_CMD            0x8000f060
 370 #define OCPAR_GPHY_READ_CMD             0x0000f060
 371         RDSAR1                  = 0xd0, /* 8168c only. Undocumented on 8168dp */
 372         MISC                    = 0xf0, /* 8168e only. */
 373 #define TXPLA_RST                       (1 << 29)
 374 };
 375
 376 enum rtl_register_content {
 377         /* InterruptStatusBits */
 378         SYSErr          = 0x8000,
 379         PCSTimeout      = 0x4000,
 380         SWInt           = 0x0100,
 381         TxDescUnavail   = 0x0080,
 382         RxFIFOOver      = 0x0040,
 383         LinkChg         = 0x0020,
 384         RxOverflow      = 0x0010,
 385         TxErr           = 0x0008,
 386         TxOK            = 0x0004,
 387         RxErr           = 0x0002,
 388         RxOK            = 0x0001,
 389
 390         /* RxStatusDesc */
 391         RxFOVF  = (1 << 23),
 392         RxRWT   = (1 << 22),
 393         RxRES   = (1 << 21),
 394         RxRUNT  = (1 << 20),
 395         RxCRC   = (1 << 19),
 396
 397         /* ChipCmdBits */
 398         CmdReset        = 0x10,
 399         CmdRxEnb        = 0x08,
 400         CmdTxEnb        = 0x04,
 401         RxBufEmpty      = 0x01,
 402
 403         /* TXPoll register p.5 */
 404         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 405         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 406         FSWInt          = 0x01,         /* Forced software interrupt */
 407
 408         /* Cfg9346Bits */
 409         Cfg9346_Lock    = 0x00,
 410         Cfg9346_Unlock  = 0xc0,
 411
 412         /* rx_mode_bits */
 413         AcceptErr       = 0x20,
 414         AcceptRunt      = 0x10,
 415         AcceptBroadcast = 0x08,
 416         AcceptMulticast = 0x04,
 417         AcceptMyPhys    = 0x02,
 418         AcceptAllPhys   = 0x01,
 419
 420         /* RxConfigBits */
 421         RxCfgFIFOShift  = 13,
 422         RxCfgDMAShift   =  8,
 423
 424         /* TxConfigBits */
 425         TxInterFrameGapShift = 24,
 426         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 427
 428         /* Config1 register p.24 */
 429         LEDS1           = (1 << 7),
 430         LEDS0           = (1 << 6),
 431         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 432         Speed_down      = (1 << 4),
 433         MEMMAP          = (1 << 3),
 434         IOMAP           = (1 << 2),
 435         VPD             = (1 << 1),
 436         PMEnable        = (1 << 0),     /* Power Management Enable */
 437
 438         /* Config2 register p. 25 */
 439         PCI_Clock_66MHz = 0x01,
 440         PCI_Clock_33MHz = 0x00,
 441
 442         /* Config3 register p.25 */
 443         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 444         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 445         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 446
 447         /* Config5 register p.27 */
 448         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 449         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 450         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 451         Spi_en          = (1 << 3),
 452         LanWake         = (1 << 1),     /* LanWake enable/disable */
 453         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 454
 455         /* TBICSR p.28 */
 456         TBIReset        = 0x80000000,
 457         TBILoopback     = 0x40000000,
 458         TBINwEnable     = 0x20000000,
 459         TBINwRestart    = 0x10000000,
 460         TBILinkOk       = 0x02000000,
 461         TBINwComplete   = 0x01000000,
 462
 463         /* CPlusCmd p.31 */
 464         EnableBist      = (1 << 15),    // 8168 8101
 465         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 466         Normal_mode     = (1 << 13),    // unused
 467         Force_half_dup  = (1 << 12),    // 8168 8101
 468         Force_rxflow_en = (1 << 11),    // 8168 8101
 469         Force_txflow_en = (1 << 10),    // 8168 8101
 470         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 471         ASF             = (1 << 8),     // 8168 8101
 472         PktCntrDisable  = (1 << 7),     // 8168 8101
 473         Mac_dbgo_sel    = 0x001c,       // 8168
 474         RxVlan          = (1 << 6),
 475         RxChkSum        = (1 << 5),
 476         PCIDAC          = (1 << 4),
 477         PCIMulRW        = (1 << 3),
 478         INTT_0          = 0x0000,       // 8168
 479         INTT_1          = 0x0001,       // 8168
 480         INTT_2          = 0x0002,       // 8168
 481         INTT_3          = 0x0003,       // 8168
 482
 483         /* rtl8169_PHYstatus */
 484         TBI_Enable      = 0x80,
 485         TxFlowCtrl      = 0x40,
 486         RxFlowCtrl      = 0x20,
 487         _1000bpsF       = 0x10,
 488         _100bps         = 0x08,
 489         _10bps          = 0x04,
 490         LinkStatus      = 0x02,
 491         FullDup         = 0x01,
 492
 493         /* _TBICSRBit */
 494         TBILinkOK       = 0x02000000,
 495
 496         /* DumpCounterCommand */
 497         CounterDump     = 0x8,
 498 };
 499
 500 enum rtl_desc_bit {
 501         /* First doubleword. */
 502         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 503         RingEnd         = (1 << 30), /* End of descriptor ring */
 504         FirstFrag       = (1 << 29), /* First segment of a packet */
 505         LastFrag        = (1 << 28), /* Final segment of a packet */
 506 };
 507
 508 /* Generic case. */
 509 enum rtl_tx_desc_bit {
 510         /* First doubleword. */
 511         TD_LSO          = (1 << 27),            /* Large Send Offload */
 512 #define TD_MSS_MAX                      0x07ffu /* MSS value */
 513
 514         /* Second doubleword. */
 515         TxVlanTag       = (1 << 17),            /* Add VLAN tag */
 516 };
 517
 518 /* 8169, 8168b and 810x except 8102e. */
 519 enum rtl_tx_desc_bit_0 {
 520         /* First doubleword. */
 521 #define TD0_MSS_SHIFT                   16      /* MSS position (11 bits) */
 522         TD0_TCP_CS      = (1 << 16),            /* Calculate TCP/IP checksum */
 523         TD0_UDP_CS      = (1 << 17),            /* Calculate UDP/IP checksum */
 524         TD0_IP_CS       = (1 << 18),            /* Calculate IP checksum */
 525 };
 526
 527 /* 8102e, 8168c and beyond. */
 528 enum rtl_tx_desc_bit_1 {
 529         /* Second doubleword. */
 530 #define TD1_MSS_SHIFT                   18      /* MSS position (11 bits) */
 531         TD1_IP_CS       = (1 << 29),            /* Calculate IP checksum */
 532         TD1_TCP_CS      = (1 << 30),            /* Calculate TCP/IP checksum */
 533         TD1_UDP_CS      = (1 << 31),            /* Calculate UDP/IP checksum */
 534 };
 535
 536 static const struct rtl_tx_desc_info {
 537         struct {
 538                 u32 udp;
 539                 u32 tcp;
 540         } checksum;
 541         u16 mss_shift;
 542         u16 opts_offset;
 543 } tx_desc_info [] = {
 544         [RTL_TD_0] = {
 545                 .checksum = {
 546                         .udp    = TD0_IP_CS | TD0_UDP_CS,
 547                         .tcp    = TD0_IP_CS | TD0_TCP_CS
 548                 },
 549                 .mss_shift      = TD0_MSS_SHIFT,
 550                 .opts_offset    = 0
 551         },
 552         [RTL_TD_1] = {
 553                 .checksum = {
 554                         .udp    = TD1_IP_CS | TD1_UDP_CS,
 555                         .tcp    = TD1_IP_CS | TD1_TCP_CS
 556                 },
 557                 .mss_shift      = TD1_MSS_SHIFT,
 558                 .opts_offset    = 1
 559         }
 560 };
 561
 562 enum rtl_rx_desc_bit {
 563         /* Rx private */
 564         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 565         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 566
 567 #define RxProtoUDP      (PID1)
 568 #define RxProtoTCP      (PID0)
 569 #define RxProtoIP       (PID1 | PID0)
 570 #define RxProtoMask     RxProtoIP
 571
 572         IPFail          = (1 << 16), /* IP checksum failed */
 573         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 574         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 575         RxVlanTag       = (1 << 16), /* VLAN tag available */
 576 };
 577
 578 #define RsvdMask        0x3fffc000
 579
 580 struct TxDesc {
 581         __le32 opts1;
 582         __le32 opts2;
 583         __le64 addr;
 584 };
 585
 586 struct RxDesc {
 587         __le32 opts1;
 588         __le32 opts2;
 589         __le64 addr;
 590 };
 591
 592 struct ring_info {
 593         struct sk_buff  *skb;
 594         u32             len;
 595         u8              __pad[sizeof(void *) - sizeof(u32)];
 596 };
 597
 598 enum features {
 599         RTL_FEATURE_WOL         = (1 << 0),
 600         RTL_FEATURE_MSI         = (1 << 1),
 601         RTL_FEATURE_GMII        = (1 << 2),
 602 };
 603
 604 struct rtl8169_counters {
 605         __le64  tx_packets;
 606         __le64  rx_packets;
 607         __le64  tx_errors;
 608         __le32  rx_errors;
 609         __le16  rx_missed;
 610         __le16  align_errors;
 611         __le32  tx_one_collision;
 612         __le32  tx_multi_collision;
 613         __le64  rx_unicast;
 614         __le64  rx_broadcast;
 615         __le32  rx_multicast;
 616         __le16  tx_aborted;
 617         __le16  tx_underun;
 618 };
 619
 620 struct rtl8169_private {
 621         void __iomem *mmio_addr;        /* memory map physical address */
 622         struct pci_dev *pci_dev;
 623         struct net_device *dev;
 624         struct napi_struct napi;
 625         spinlock_t lock;
 626         u32 msg_enable;
 627         u16 txd_version;
 628         u16 mac_version;
 629         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 630         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 631         u32 dirty_rx;
 632         u32 dirty_tx;
 633         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 634         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 635         dma_addr_t TxPhyAddr;
 636         dma_addr_t RxPhyAddr;
 637         void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
 638         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 639         struct timer_list timer;
 640         u16 cp_cmd;
 641         u16 intr_event;
 642         u16 napi_event;
 643         u16 intr_mask;
 644
 645         struct mdio_ops {
 646                 void (*write)(void __iomem *, int, int);
 647                 int (*read)(void __iomem *, int);
 648         } mdio_ops;
 649
 650         struct pll_power_ops {
 651                 void (*down)(struct rtl8169_private *);
 652                 void (*up)(struct rtl8169_private *);
 653         } pll_power_ops;
 654
 655         int (*set_speed)(struct net_device *, u8 aneg, u16 sp, u8 dpx, u32 adv);
 656         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 657         void (*phy_reset_enable)(struct rtl8169_private *tp);
 658         void (*hw_start)(struct net_device *);
 659         unsigned int (*phy_reset_pending)(struct rtl8169_private *tp);
 660         unsigned int (*link_ok)(void __iomem *);
 661         int (*do_ioctl)(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd);
 662         int pcie_cap;
 663         struct delayed_work task;
 664         unsigned features;
 665
 666         struct mii_if_info mii;
 667         struct rtl8169_counters counters;
 668         u32 saved_wolopts;
 669
 670         struct rtl_fw {
 671                 const struct firmware *fw;
 672
 673 #define RTL_VER_SIZE            32
 674
 675                 char version[RTL_VER_SIZE];
 676
 677                 struct rtl_fw_phy_action {
 678                         __le32 *code;
 679                         size_t size;
 680                 } phy_action;
 681         } *rtl_fw;
 682 #define RTL_FIRMWARE_UNKNOWN    ERR_PTR(-EAGAIN);
 683 };
 684
 685 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 686 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 687 module_param(use_dac, int, 0);
 688 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 689 module_param_named(debug, debug.msg_enable, int, 0);
 690 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 691 MODULE_LICENSE("GPL");
 692 MODULE_VERSION(RTL8169_VERSION);
 693 MODULE_FIRMWARE(FIRMWARE_8168D_1);
 694 MODULE_FIRMWARE(FIRMWARE_8168D_2);
 695 MODULE_FIRMWARE(FIRMWARE_8168E_1);
 696 MODULE_FIRMWARE(FIRMWARE_8168E_2);
 697 MODULE_FIRMWARE(FIRMWARE_8105E_1);
 698
 699 static int rtl8169_open(struct net_device *dev);
 700 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
 701                                       struct net_device *dev);
 702 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 703 static int rtl8169_init_ring(struct net_device *dev);
 704 static void rtl_hw_start(struct net_device *dev);
 705 static int rtl8169_close(struct net_device *dev);
 706 static void rtl_set_rx_mode(struct net_device *dev);
 707 static void rtl8169_tx_timeout(struct net_device *dev);
 708 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 709 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 710                                 void __iomem *, u32 budget);
 711 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 712 static void rtl8169_down(struct net_device *dev);
 713 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 714 static int rtl8169_poll(struct napi_struct *napi, int budget);
 715
 716 static const unsigned int rtl8169_rx_config =
 717         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 718
 719 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
 720 {
 721         void __iomem *ioaddr = tp->mmio_addr;
 722         int i;
 723
 724         RTL_W32(OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 725         for (i = 0; i < 20; i++) {
 726                 udelay(100);
 727                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 728                         break;
 729         }
 730         return RTL_R32(OCPDR);
 731 }
 732
 733 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
 734 {
 735         void __iomem *ioaddr = tp->mmio_addr;
 736         int i;
 737
 738         RTL_W32(OCPDR, data);
 739         RTL_W32(OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
 740         for (i = 0; i < 20; i++) {
 741                 udelay(100);
 742                 if ((RTL_R32(OCPAR) & OCPAR_FLAG) == 0)
 743                         break;
 744         }
 745 }
 746
 747 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
 748 {
 749         void __iomem *ioaddr = tp->mmio_addr;
 750         int i;
 751
 752         RTL_W8(ERIDR, cmd);
 753         RTL_W32(ERIAR, 0x800010e8);
 754         msleep(2);
 755         for (i = 0; i < 5; i++) {
 756                 udelay(100);
 757                 if (!(RTL_R32(ERIDR) & ERIAR_FLAG))
 758                         break;
 759         }
 760
 761         ocp_write(tp, 0x1, 0x30, 0x00000001);
 762 }
 763
 764 #define OOB_CMD_RESET           0x00
 765 #define OOB_CMD_DRIVER_START    0x05
 766 #define OOB_CMD_DRIVER_STOP     0x06
 767
 768 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
 769 {
 770         return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
 771 }
 772
 773 static void rtl8168_driver_start(struct rtl8169_private *tp)
 774 {
 775         u16 reg;
 776         int i;
 777
 778         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
 779
 780         reg = rtl8168_get_ocp_reg(tp);
 781
 782         for (i = 0; i < 10; i++) {
 783                 msleep(10);
 784                 if (ocp_read(tp, 0x0f, reg) & 0x00000800)
 785                         break;
 786         }
 787 }
 788
 789 static void rtl8168_driver_stop(struct rtl8169_private *tp)
 790 {
 791         u16 reg;
 792         int i;
 793
 794         rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
 795
 796         reg = rtl8168_get_ocp_reg(tp);
 797
 798         for (i = 0; i < 10; i++) {
 799                 msleep(10);
 800                 if ((ocp_read(tp, 0x0f, reg) & 0x00000800) == 0)
 801                         break;
 802         }
 803 }
 804
 805 static int r8168dp_check_dash(struct rtl8169_private *tp)
 806 {
 807         u16 reg = rtl8168_get_ocp_reg(tp);
 808
 809         return (ocp_read(tp, 0x0f, reg) & 0x00008000) ? 1 : 0;
 810 }
 811
 812 static void r8169_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 813 {
 814         int i;
 815
 816         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 817
 818         for (i = 20; i > 0; i--) {
 819                 /*
 820                  * Check if the RTL8169 has completed writing to the specified
 821                  * MII register.
 822                  */
 823                 if (!(RTL_R32(PHYAR) & 0x80000000))
 824                         break;
 825                 udelay(25);
 826         }
 827         /*
 828          * According to hardware specs a 20us delay is required after write
 829          * complete indication, but before sending next command.
 830          */
 831         udelay(20);
 832 }
 833
 834 static int r8169_mdio_read(void __iomem *ioaddr, int reg_addr)
 835 {
 836         int i, value = -1;
 837
 838         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 839
 840         for (i = 20; i > 0; i--) {
 841                 /*
 842                  * Check if the RTL8169 has completed retrieving data from
 843                  * the specified MII register.
 844                  */
 845                 if (RTL_R32(PHYAR) & 0x80000000) {
 846                         value = RTL_R32(PHYAR) & 0xffff;
 847                         break;
 848                 }
 849                 udelay(25);
 850         }
 851         /*
 852          * According to hardware specs a 20us delay is required after read
 853          * complete indication, but before sending next command.
 854          */
 855         udelay(20);
 856
 857         return value;
 858 }
 859
 860 static void r8168dp_1_mdio_access(void __iomem *ioaddr, int reg_addr, u32 data)
 861 {
 862         int i;
 863
 864         RTL_W32(OCPDR, data |
 865                 ((reg_addr & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
 866         RTL_W32(OCPAR, OCPAR_GPHY_WRITE_CMD);
 867         RTL_W32(EPHY_RXER_NUM, 0);
 868
 869         for (i = 0; i < 100; i++) {
 870                 mdelay(1);
 871                 if (!(RTL_R32(OCPAR) & OCPAR_FLAG))
 872                         break;
 873         }
 874 }
 875
 876 static void r8168dp_1_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 877 {
 878         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_WRITE_CMD |
 879                 (value & OCPDR_DATA_MASK));
 880 }
 881
 882 static int r8168dp_1_mdio_read(void __iomem *ioaddr, int reg_addr)
 883 {
 884         int i;
 885
 886         r8168dp_1_mdio_access(ioaddr, reg_addr, OCPDR_READ_CMD);
 887
 888         mdelay(1);
 889         RTL_W32(OCPAR, OCPAR_GPHY_READ_CMD);
 890         RTL_W32(EPHY_RXER_NUM, 0);
 891
 892         for (i = 0; i < 100; i++) {
 893                 mdelay(1);
 894                 if (RTL_R32(OCPAR) & OCPAR_FLAG)
 895                         break;
 896         }
 897
 898         return RTL_R32(OCPDR) & OCPDR_DATA_MASK;
 899 }
 900
 901 #define R8168DP_1_MDIO_ACCESS_BIT       0x00020000
 902
 903 static void r8168dp_2_mdio_start(void __iomem *ioaddr)
 904 {
 905         RTL_W32(0xd0, RTL_R32(0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
 906 }
 907
 908 static void r8168dp_2_mdio_stop(void __iomem *ioaddr)
 909 {
 910         RTL_W32(0xd0, RTL_R32(0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
 911 }
 912
 913 static void r8168dp_2_mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 914 {
 915         r8168dp_2_mdio_start(ioaddr);
 916
 917         r8169_mdio_write(ioaddr, reg_addr, value);
 918
 919         r8168dp_2_mdio_stop(ioaddr);
 920 }
 921
 922 static int r8168dp_2_mdio_read(void __iomem *ioaddr, int reg_addr)
 923 {
 924         int value;
 925
 926         r8168dp_2_mdio_start(ioaddr);
 927
 928         value = r8169_mdio_read(ioaddr, reg_addr);
 929
 930         r8168dp_2_mdio_stop(ioaddr);
 931
 932         return value;
 933 }
 934
 935 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
 936 {
 937         tp->mdio_ops.write(tp->mmio_addr, location, val);
 938 }
 939
 940 static int rtl_readphy(struct rtl8169_private *tp, int location)
 941 {
 942         return tp->mdio_ops.read(tp->mmio_addr, location);
 943 }
 944
 945 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
 946 {
 947         rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
 948 }
 949
 950 static void rtl_w1w0_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
 951 {
 952         int val;
 953
 954         val = rtl_readphy(tp, reg_addr);
 955         rtl_writephy(tp, reg_addr, (val | p) & ~m);
 956 }
 957
 958 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 959                            int val)
 960 {
 961         struct rtl8169_private *tp = netdev_priv(dev);
 962
 963         rtl_writephy(tp, location, val);
 964 }
 965
 966 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 967 {
 968         struct rtl8169_private *tp = netdev_priv(dev);
 969
 970         return rtl_readphy(tp, location);
 971 }
 972
 973 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 974 {
 975         unsigned int i;
 976
 977         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 978                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 979
 980         for (i = 0; i < 100; i++) {
 981                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 982                         break;
 983                 udelay(10);
 984         }
 985 }
 986
 987 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 988 {
 989         u16 value = 0xffff;
 990         unsigned int i;
 991
 992         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 993
 994         for (i = 0; i < 100; i++) {
 995                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 996                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 997                         break;
 998                 }
 999                 udelay(10);
1000         }
1001
1002         return value;
1003 }
1004
1005 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
1006 {
1007         unsigned int i;
1008
1009         RTL_W32(CSIDR, value);
1010         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
1011                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1012
1013         for (i = 0; i < 100; i++) {
1014                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
1015                         break;
1016                 udelay(10);
1017         }
1018 }
1019
1020 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
1021 {
1022         u32 value = ~0x00;
1023         unsigned int i;
1024
1025         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
1026                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
1027
1028         for (i = 0; i < 100; i++) {
1029                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
1030                         value = RTL_R32(CSIDR);
1031                         break;
1032                 }
1033                 udelay(10);
1034         }
1035
1036         return value;
1037 }
1038
1039 static u8 rtl8168d_efuse_read(void __iomem *ioaddr, int reg_addr)
1040 {
1041         u8 value = 0xff;
1042         unsigned int i;
1043
1044         RTL_W32(EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1045
1046         for (i = 0; i < 300; i++) {
1047                 if (RTL_R32(EFUSEAR) & EFUSEAR_FLAG) {
1048                         value = RTL_R32(EFUSEAR) & EFUSEAR_DATA_MASK;
1049                         break;
1050                 }
1051                 udelay(100);
1052         }
1053
1054         return value;
1055 }
1056
1057 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
1058 {
1059         RTL_W16(IntrMask, 0x0000);
1060
1061         RTL_W16(IntrStatus, 0xffff);
1062 }
1063
1064 static void rtl8169_asic_down(void __iomem *ioaddr)
1065 {
1066         RTL_W8(ChipCmd, 0x00);
1067         rtl8169_irq_mask_and_ack(ioaddr);
1068         RTL_R16(CPlusCmd);
1069 }
1070
1071 static unsigned int rtl8169_tbi_reset_pending(struct rtl8169_private *tp)
1072 {
1073         void __iomem *ioaddr = tp->mmio_addr;
1074
1075         return RTL_R32(TBICSR) & TBIReset;
1076 }
1077
1078 static unsigned int rtl8169_xmii_reset_pending(struct rtl8169_private *tp)
1079 {
1080         return rtl_readphy(tp, MII_BMCR) & BMCR_RESET;
1081 }
1082
1083 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
1084 {
1085         return RTL_R32(TBICSR) & TBILinkOk;
1086 }
1087
1088 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
1089 {
1090         return RTL_R8(PHYstatus) & LinkStatus;
1091 }
1092
1093 static void rtl8169_tbi_reset_enable(struct rtl8169_private *tp)
1094 {
1095         void __iomem *ioaddr = tp->mmio_addr;
1096
1097         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
1098 }
1099
1100 static void rtl8169_xmii_reset_enable(struct rtl8169_private *tp)
1101 {
1102         unsigned int val;
1103
1104         val = rtl_readphy(tp, MII_BMCR) | BMCR_RESET;
1105         rtl_writephy(tp, MII_BMCR, val & 0xffff);
1106 }
1107
1108 static void __rtl8169_check_link_status(struct net_device *dev,
1109                                         struct rtl8169_private *tp,
1110                                         void __iomem *ioaddr, bool pm)
1111 {
1112         unsigned long flags;
1113
1114         spin_lock_irqsave(&tp->lock, flags);
1115         if (tp->link_ok(ioaddr)) {
1116                 /* This is to cancel a scheduled suspend if there's one. */
1117                 if (pm)
1118                         pm_request_resume(&tp->pci_dev->dev);
1119                 netif_carrier_on(dev);
1120                 if (net_ratelimit())
1121                         netif_info(tp, ifup, dev, "link up\n");
1122         } else {
1123                 netif_carrier_off(dev);
1124                 netif_info(tp, ifdown, dev, "link down\n");
1125                 if (pm)
1126                         pm_schedule_suspend(&tp->pci_dev->dev, 100);
1127         }
1128         spin_unlock_irqrestore(&tp->lock, flags);
1129 }
1130
1131 static void rtl8169_check_link_status(struct net_device *dev,
1132                                       struct rtl8169_private *tp,
1133                                       void __iomem *ioaddr)
1134 {
1135         __rtl8169_check_link_status(dev, tp, ioaddr, false);
1136 }
1137
1138 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1139
1140 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1141 {
1142         void __iomem *ioaddr = tp->mmio_addr;
1143         u8 options;
1144         u32 wolopts = 0;
1145
1146         options = RTL_R8(Config1);
1147         if (!(options & PMEnable))
1148                 return 0;
1149
1150         options = RTL_R8(Config3);
1151         if (options & LinkUp)
1152                 wolopts |= WAKE_PHY;
1153         if (options & MagicPacket)
1154                 wolopts |= WAKE_MAGIC;
1155
1156         options = RTL_R8(Config5);
1157         if (options & UWF)
1158                 wolopts |= WAKE_UCAST;
1159         if (options & BWF)
1160                 wolopts |= WAKE_BCAST;
1161         if (options & MWF)
1162                 wolopts |= WAKE_MCAST;
1163
1164         return wolopts;
1165 }
1166
1167 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1168 {
1169         struct rtl8169_private *tp = netdev_priv(dev);
1170
1171         spin_lock_irq(&tp->lock);
1172
1173         wol->supported = WAKE_ANY;
1174         wol->wolopts = __rtl8169_get_wol(tp);
1175
1176         spin_unlock_irq(&tp->lock);
1177 }
1178
1179 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1180 {
1181         void __iomem *ioaddr = tp->mmio_addr;
1182         unsigned int i;
1183         static const struct {
1184                 u32 opt;
1185                 u16 reg;
1186                 u8  mask;
1187         } cfg[] = {
1188                 { WAKE_ANY,   Config1, PMEnable },
1189                 { WAKE_PHY,   Config3, LinkUp },
1190                 { WAKE_MAGIC, Config3, MagicPacket },
1191                 { WAKE_UCAST, Config5, UWF },
1192                 { WAKE_BCAST, Config5, BWF },
1193                 { WAKE_MCAST, Config5, MWF },
1194                 { WAKE_ANY,   Config5, LanWake }
1195         };
1196
1197         RTL_W8(Cfg9346, Cfg9346_Unlock);
1198
1199         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
1200                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
1201                 if (wolopts & cfg[i].opt)
1202                         options |= cfg[i].mask;
1203                 RTL_W8(cfg[i].reg, options);
1204         }
1205
1206         RTL_W8(Cfg9346, Cfg9346_Lock);
1207 }
1208
1209 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1210 {
1211         struct rtl8169_private *tp = netdev_priv(dev);
1212
1213         spin_lock_irq(&tp->lock);
1214
1215         if (wol->wolopts)
1216                 tp->features |= RTL_FEATURE_WOL;
1217         else
1218                 tp->features &= ~RTL_FEATURE_WOL;
1219         __rtl8169_set_wol(tp, wol->wolopts);
1220         spin_unlock_irq(&tp->lock);
1221
1222         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
1223
1224         return 0;
1225 }
1226
1227 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1228 {
1229         return rtl_chip_infos[tp->mac_version].fw_name;
1230 }
1231
1232 static void rtl8169_get_drvinfo(struct net_device *dev,
1233                                 struct ethtool_drvinfo *info)
1234 {
1235         struct rtl8169_private *tp = netdev_priv(dev);
1236         struct rtl_fw *rtl_fw = tp->rtl_fw;
1237
1238         strcpy(info->driver, MODULENAME);
1239         strcpy(info->version, RTL8169_VERSION);
1240         strcpy(info->bus_info, pci_name(tp->pci_dev));
1241         BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1242         strcpy(info->fw_version, IS_ERR_OR_NULL(rtl_fw) ? "N/A" :
1243                rtl_fw->version);
1244 }
1245
1246 static int rtl8169_get_regs_len(struct net_device *dev)
1247 {
1248         return R8169_REGS_SIZE;
1249 }
1250
1251 static int rtl8169_set_speed_tbi(struct net_device *dev,
1252                                  u8 autoneg, u16 speed, u8 duplex, u32 ignored)
1253 {
1254         struct rtl8169_private *tp = netdev_priv(dev);
1255         void __iomem *ioaddr = tp->mmio_addr;
1256         int ret = 0;
1257         u32 reg;
1258
1259         reg = RTL_R32(TBICSR);
1260         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
1261             (duplex == DUPLEX_FULL)) {
1262                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
1263         } else if (autoneg == AUTONEG_ENABLE)
1264                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
1265         else {
1266                 netif_warn(tp, link, dev,
1267                            "incorrect speed setting refused in TBI mode\n");
1268                 ret = -EOPNOTSUPP;
1269         }
1270
1271         return ret;
1272 }
1273
1274 static int rtl8169_set_speed_xmii(struct net_device *dev,
1275                                   u8 autoneg, u16 speed, u8 duplex, u32 adv)
1276 {
1277         struct rtl8169_private *tp = netdev_priv(dev);
1278         int giga_ctrl, bmcr;
1279         int rc = -EINVAL;
1280
1281         rtl_writephy(tp, 0x1f, 0x0000);
1282
1283         if (autoneg == AUTONEG_ENABLE) {
1284                 int auto_nego;
1285
1286                 auto_nego = rtl_readphy(tp, MII_ADVERTISE);
1287                 auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1288                                 ADVERTISE_100HALF | ADVERTISE_100FULL);
1289
1290                 if (adv & ADVERTISED_10baseT_Half)
1291                         auto_nego |= ADVERTISE_10HALF;
1292                 if (adv & ADVERTISED_10baseT_Full)
1293                         auto_nego |= ADVERTISE_10FULL;
1294                 if (adv & ADVERTISED_100baseT_Half)
1295                         auto_nego |= ADVERTISE_100HALF;
1296                 if (adv & ADVERTISED_100baseT_Full)
1297                         auto_nego |= ADVERTISE_100FULL;
1298
1299                 auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
1300
1301                 giga_ctrl = rtl_readphy(tp, MII_CTRL1000);
1302                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
1303
1304                 /* The 8100e/8101e/8102e do Fast Ethernet only. */
1305                 if (tp->mii.supports_gmii) {
1306                         if (adv & ADVERTISED_1000baseT_Half)
1307                                 giga_ctrl |= ADVERTISE_1000HALF;
1308                         if (adv & ADVERTISED_1000baseT_Full)
1309                                 giga_ctrl |= ADVERTISE_1000FULL;
1310                 } else if (adv & (ADVERTISED_1000baseT_Half |
1311                                   ADVERTISED_1000baseT_Full)) {
1312                         netif_info(tp, link, dev,
1313                                    "PHY does not support 1000Mbps\n");
1314                         goto out;
1315                 }
1316
1317                 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1318
1319                 rtl_writephy(tp, MII_ADVERTISE, auto_nego);
1320                 rtl_writephy(tp, MII_CTRL1000, giga_ctrl);
1321         } else {
1322                 giga_ctrl = 0;
1323
1324                 if (speed == SPEED_10)
1325                         bmcr = 0;
1326                 else if (speed == SPEED_100)
1327                         bmcr = BMCR_SPEED100;
1328                 else
1329                         goto out;
1330
1331                 if (duplex == DUPLEX_FULL)
1332                         bmcr |= BMCR_FULLDPLX;
1333         }
1334
1335         rtl_writephy(tp, MII_BMCR, bmcr);
1336
1337         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
1338             tp->mac_version == RTL_GIGA_MAC_VER_03) {
1339                 if ((speed == SPEED_100) && (autoneg != AUTONEG_ENABLE)) {
1340                         rtl_writephy(tp, 0x17, 0x2138);
1341                         rtl_writephy(tp, 0x0e, 0x0260);
1342                 } else {
1343                         rtl_writephy(tp, 0x17, 0x2108);
1344                         rtl_writephy(tp, 0x0e, 0x0000);
1345                 }
1346         }
1347
1348         rc = 0;
1349 out:
1350         return rc;
1351 }
1352
1353 static int rtl8169_set_speed(struct net_device *dev,
1354                              u8 autoneg, u16 speed, u8 duplex, u32 advertising)
1355 {
1356         struct rtl8169_private *tp = netdev_priv(dev);
1357         int ret;
1358
1359         ret = tp->set_speed(dev, autoneg, speed, duplex, advertising);
1360         if (ret < 0)
1361                 goto out;
1362
1363         if (netif_running(dev) && (autoneg == AUTONEG_ENABLE) &&
1364             (advertising & ADVERTISED_1000baseT_Full)) {
1365                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
1366         }
1367 out:
1368         return ret;
1369 }
1370
1371 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1372 {
1373         struct rtl8169_private *tp = netdev_priv(dev);
1374         unsigned long flags;
1375         int ret;
1376
1377         del_timer_sync(&tp->timer);
1378
1379         spin_lock_irqsave(&tp->lock, flags);
1380         ret = rtl8169_set_speed(dev, cmd->autoneg, ethtool_cmd_speed(cmd),
1381                                 cmd->duplex, cmd->advertising);
1382         spin_unlock_irqrestore(&tp->lock, flags);
1383
1384         return ret;
1385 }
1386
1387 static u32 rtl8169_fix_features(struct net_device *dev, u32 features)
1388 {
1389         if (dev->mtu > TD_MSS_MAX)
1390                 features &= ~NETIF_F_ALL_TSO;
1391
1392         return features;
1393 }
1394
1395 static int rtl8169_set_features(struct net_device *dev, u32 features)
1396 {
1397         struct rtl8169_private *tp = netdev_priv(dev);
1398         void __iomem *ioaddr = tp->mmio_addr;
1399         unsigned long flags;
1400
1401         spin_lock_irqsave(&tp->lock, flags);
1402
1403         if (features & NETIF_F_RXCSUM)
1404                 tp->cp_cmd |= RxChkSum;
1405         else
1406                 tp->cp_cmd &= ~RxChkSum;
1407
1408         if (dev->features & NETIF_F_HW_VLAN_RX)
1409                 tp->cp_cmd |= RxVlan;
1410         else
1411                 tp->cp_cmd &= ~RxVlan;
1412
1413         RTL_W16(CPlusCmd, tp->cp_cmd);
1414         RTL_R16(CPlusCmd);
1415
1416         spin_unlock_irqrestore(&tp->lock, flags);
1417
1418         return 0;
1419 }
1420
1421 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
1422                                       struct sk_buff *skb)
1423 {
1424         return (vlan_tx_tag_present(skb)) ?
1425                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
1426 }
1427
1428 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1429 {
1430         u32 opts2 = le32_to_cpu(desc->opts2);
1431
1432         if (opts2 & RxVlanTag)
1433                 __vlan_hwaccel_put_tag(skb, swab16(opts2 & 0xffff));
1434
1435         desc->opts2 = 0;
1436 }
1437
1438 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1439 {
1440         struct rtl8169_private *tp = netdev_priv(dev);
1441         void __iomem *ioaddr = tp->mmio_addr;
1442         u32 status;
1443
1444         cmd->supported =
1445                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1446         cmd->port = PORT_FIBRE;
1447         cmd->transceiver = XCVR_INTERNAL;
1448
1449         status = RTL_R32(TBICSR);
1450         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1451         cmd->autoneg = !!(status & TBINwEnable);
1452
1453         ethtool_cmd_speed_set(cmd, SPEED_1000);
1454         cmd->duplex = DUPLEX_FULL; /* Always set */
1455
1456         return 0;
1457 }
1458
1459 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1460 {
1461         struct rtl8169_private *tp = netdev_priv(dev);
1462
1463         return mii_ethtool_gset(&tp->mii, cmd);
1464 }
1465
1466 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1467 {
1468         struct rtl8169_private *tp = netdev_priv(dev);
1469         unsigned long flags;
1470         int rc;
1471
1472         spin_lock_irqsave(&tp->lock, flags);
1473
1474         rc = tp->get_settings(dev, cmd);
1475
1476         spin_unlock_irqrestore(&tp->lock, flags);
1477         return rc;
1478 }
1479
1480 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1481                              void *p)
1482 {
1483         struct rtl8169_private *tp = netdev_priv(dev);
1484         unsigned long flags;
1485
1486         if (regs->len > R8169_REGS_SIZE)
1487                 regs->len = R8169_REGS_SIZE;
1488
1489         spin_lock_irqsave(&tp->lock, flags);
1490         memcpy_fromio(p, tp->mmio_addr, regs->len);
1491         spin_unlock_irqrestore(&tp->lock, flags);
1492 }
1493
1494 static u32 rtl8169_get_msglevel(struct net_device *dev)
1495 {
1496         struct rtl8169_private *tp = netdev_priv(dev);
1497
1498         return tp->msg_enable;
1499 }
1500
1501 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1502 {
1503         struct rtl8169_private *tp = netdev_priv(dev);
1504
1505         tp->msg_enable = value;
1506 }
1507
1508 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1509         "tx_packets",
1510         "rx_packets",
1511         "tx_errors",
1512         "rx_errors",
1513         "rx_missed",
1514         "align_errors",
1515         "tx_single_collisions",
1516         "tx_multi_collisions",
1517         "unicast",
1518         "broadcast",
1519         "multicast",
1520         "tx_aborted",
1521         "tx_underrun",
1522 };
1523
1524 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1525 {
1526         switch (sset) {
1527         case ETH_SS_STATS:
1528                 return ARRAY_SIZE(rtl8169_gstrings);
1529         default:
1530                 return -EOPNOTSUPP;
1531         }
1532 }
1533
1534 static void rtl8169_update_counters(struct net_device *dev)
1535 {
1536         struct rtl8169_private *tp = netdev_priv(dev);
1537         void __iomem *ioaddr = tp->mmio_addr;
1538         struct device *d = &tp->pci_dev->dev;
1539         struct rtl8169_counters *counters;
1540         dma_addr_t paddr;
1541         u32 cmd;
1542         int wait = 1000;
1543
1544         /*
1545          * Some chips are unable to dump tally counters when the receiver
1546          * is disabled.
1547          */
1548         if ((RTL_R8(ChipCmd) & CmdRxEnb) == 0)
1549                 return;
1550
1551         counters = dma_alloc_coherent(d, sizeof(*counters), &paddr, GFP_KERNEL);
1552         if (!counters)
1553                 return;
1554
1555         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1556         cmd = (u64)paddr & DMA_BIT_MASK(32);
1557         RTL_W32(CounterAddrLow, cmd);
1558         RTL_W32(CounterAddrLow, cmd | CounterDump);
1559
1560         while (wait--) {
1561                 if ((RTL_R32(CounterAddrLow) & CounterDump) == 0) {
1562                         memcpy(&tp->counters, counters, sizeof(*counters));
1563                         break;
1564                 }
1565                 udelay(10);
1566         }
1567
1568         RTL_W32(CounterAddrLow, 0);
1569         RTL_W32(CounterAddrHigh, 0);
1570
1571         dma_free_coherent(d, sizeof(*counters), counters, paddr);
1572 }
1573
1574 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1575                                       struct ethtool_stats *stats, u64 *data)
1576 {
1577         struct rtl8169_private *tp = netdev_priv(dev);
1578
1579         ASSERT_RTNL();
1580
1581         rtl8169_update_counters(dev);
1582
1583         data[0] = le64_to_cpu(tp->counters.tx_packets);
1584         data[1] = le64_to_cpu(tp->counters.rx_packets);
1585         data[2] = le64_to_cpu(tp->counters.tx_errors);
1586         data[3] = le32_to_cpu(tp->counters.rx_errors);
1587         data[4] = le16_to_cpu(tp->counters.rx_missed);
1588         data[5] = le16_to_cpu(tp->counters.align_errors);
1589         data[6] = le32_to_cpu(tp->counters.tx_one_collision);
1590         data[7] = le32_to_cpu(tp->counters.tx_multi_collision);
1591         data[8] = le64_to_cpu(tp->counters.rx_unicast);
1592         data[9] = le64_to_cpu(tp->counters.rx_broadcast);
1593         data[10] = le32_to_cpu(tp->counters.rx_multicast);
1594         data[11] = le16_to_cpu(tp->counters.tx_aborted);
1595         data[12] = le16_to_cpu(tp->counters.tx_underun);
1596 }
1597
1598 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1599 {
1600         switch(stringset) {
1601         case ETH_SS_STATS:
1602                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1603                 break;
1604         }
1605 }
1606
1607 static const struct ethtool_ops rtl8169_ethtool_ops = {
1608         .get_drvinfo            = rtl8169_get_drvinfo,
1609         .get_regs_len           = rtl8169_get_regs_len,
1610         .get_link               = ethtool_op_get_link,
1611         .get_settings           = rtl8169_get_settings,
1612         .set_settings           = rtl8169_set_settings,
1613         .get_msglevel           = rtl8169_get_msglevel,
1614         .set_msglevel           = rtl8169_set_msglevel,
1615         .get_regs               = rtl8169_get_regs,
1616         .get_wol                = rtl8169_get_wol,
1617         .set_wol                = rtl8169_set_wol,
1618         .get_strings            = rtl8169_get_strings,
1619         .get_sset_count         = rtl8169_get_sset_count,
1620         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1621 };
1622
1623 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1624                                     struct net_device *dev, u8 default_version)
1625 {
1626         void __iomem *ioaddr = tp->mmio_addr;
1627         /*
1628          * The driver currently handles the 8168Bf and the 8168Be identically
1629          * but they can be identified more specifically through the test below
1630          * if needed:
1631          *
1632          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1633          *
1634          * Same thing for the 8101Eb and the 8101Ec:
1635          *
1636          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1637          */
1638         static const struct rtl_mac_info {
1639                 u32 mask;
1640                 u32 val;
1641                 int mac_version;
1642         } mac_info[] = {
1643                 /* 8168E family. */
1644                 { 0x7cf00000, 0x2c200000,       RTL_GIGA_MAC_VER_33 },
1645                 { 0x7cf00000, 0x2c100000,       RTL_GIGA_MAC_VER_32 },
1646                 { 0x7c800000, 0x2c000000,       RTL_GIGA_MAC_VER_33 },
1647
1648                 /* 8168D family. */
1649                 { 0x7cf00000, 0x28300000,       RTL_GIGA_MAC_VER_26 },
1650                 { 0x7cf00000, 0x28100000,       RTL_GIGA_MAC_VER_25 },
1651                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_26 },
1652
1653                 /* 8168DP family. */
1654                 { 0x7cf00000, 0x28800000,       RTL_GIGA_MAC_VER_27 },
1655                 { 0x7cf00000, 0x28a00000,       RTL_GIGA_MAC_VER_28 },
1656                 { 0x7cf00000, 0x28b00000,       RTL_GIGA_MAC_VER_31 },
1657
1658                 /* 8168C family. */
1659                 { 0x7cf00000, 0x3cb00000,       RTL_GIGA_MAC_VER_24 },
1660                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1661                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1662                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1663                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1664                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1665                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1666                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1667                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1668
1669                 /* 8168B family. */
1670                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1671                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1672                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1673                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1674
1675                 /* 8101 family. */
1676                 { 0x7cf00000, 0x40b00000,       RTL_GIGA_MAC_VER_30 },
1677                 { 0x7cf00000, 0x40a00000,       RTL_GIGA_MAC_VER_30 },
1678                 { 0x7cf00000, 0x40900000,       RTL_GIGA_MAC_VER_29 },
1679                 { 0x7c800000, 0x40800000,       RTL_GIGA_MAC_VER_30 },
1680                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1681                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1682                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1683                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1684                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1685                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1686                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1687                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1688                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1689                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1690                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1691                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1692                 /* FIXME: where did these entries come from ? -- FR */
1693                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1694                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1695
1696                 /* 8110 family. */
1697                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1698                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1699                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1700                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1701                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1702                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1703
1704                 /* Catch-all */
1705                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_NONE   }
1706         };
1707         const struct rtl_mac_info *p = mac_info;
1708         u32 reg;
1709
1710         reg = RTL_R32(TxConfig);
1711         while ((reg & p->mask) != p->val)
1712                 p++;
1713         tp->mac_version = p->mac_version;
1714
1715         if (tp->mac_version == RTL_GIGA_MAC_NONE) {
1716                 netif_notice(tp, probe, dev,
1717                              "unknown MAC, using family default\n");
1718                 tp->mac_version = default_version;
1719         }
1720 }
1721
1722 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1723 {
1724         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1725 }
1726
1727 struct phy_reg {
1728         u16 reg;
1729         u16 val;
1730 };
1731
1732 static void rtl_writephy_batch(struct rtl8169_private *tp,
1733                                const struct phy_reg *regs, int len)
1734 {
1735         while (len-- > 0) {
1736                 rtl_writephy(tp, regs->reg, regs->val);
1737                 regs++;
1738         }
1739 }
1740
1741 #define PHY_READ                0x00000000
1742 #define PHY_DATA_OR             0x10000000
1743 #define PHY_DATA_AND            0x20000000
1744 #define PHY_BJMPN               0x30000000
1745 #define PHY_READ_EFUSE          0x40000000
1746 #define PHY_READ_MAC_BYTE       0x50000000
1747 #define PHY_WRITE_MAC_BYTE      0x60000000
1748 #define PHY_CLEAR_READCOUNT     0x70000000
1749 #define PHY_WRITE               0x80000000
1750 #define PHY_READCOUNT_EQ_SKIP   0x90000000
1751 #define PHY_COMP_EQ_SKIPN       0xa0000000
1752 #define PHY_COMP_NEQ_SKIPN      0xb0000000
1753 #define PHY_WRITE_PREVIOUS      0xc0000000
1754 #define PHY_SKIPN               0xd0000000
1755 #define PHY_DELAY_MS            0xe0000000
1756 #define PHY_WRITE_ERI_WORD      0xf0000000
1757
1758 struct fw_info {
1759         u32     magic;
1760         char    version[RTL_VER_SIZE];
1761         __le32  fw_start;
1762         __le32  fw_len;
1763         u8      chksum;
1764 } __packed;
1765
1766 #define FW_OPCODE_SIZE  sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
1767
1768 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1769 {
1770         const struct firmware *fw = rtl_fw->fw;
1771         struct fw_info *fw_info = (struct fw_info *)fw->data;
1772         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1773         char *version = rtl_fw->version;
1774         bool rc = false;
1775
1776         if (fw->size < FW_OPCODE_SIZE)
1777                 goto out;
1778
1779         if (!fw_info->magic) {
1780                 size_t i, size, start;
1781                 u8 checksum = 0;
1782
1783                 if (fw->size < sizeof(*fw_info))
1784                         goto out;
1785
1786                 for (i = 0; i < fw->size; i++)
1787                         checksum += fw->data[i];
1788                 if (checksum != 0)
1789                         goto out;
1790
1791                 start = le32_to_cpu(fw_info->fw_start);
1792                 if (start > fw->size)
1793                         goto out;
1794
1795                 size = le32_to_cpu(fw_info->fw_len);
1796                 if (size > (fw->size - start) / FW_OPCODE_SIZE)
1797                         goto out;
1798
1799                 memcpy(version, fw_info->version, RTL_VER_SIZE);
1800
1801                 pa->code = (__le32 *)(fw->data + start);
1802                 pa->size = size;
1803         } else {
1804                 if (fw->size % FW_OPCODE_SIZE)
1805                         goto out;
1806
1807                 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
1808
1809                 pa->code = (__le32 *)fw->data;
1810                 pa->size = fw->size / FW_OPCODE_SIZE;
1811         }
1812         version[RTL_VER_SIZE - 1] = 0;
1813
1814         rc = true;
1815 out:
1816         return rc;
1817 }
1818
1819 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
1820                            struct rtl_fw_phy_action *pa)
1821 {
1822         bool rc = false;
1823         size_t index;
1824
1825         for (index = 0; index < pa->size; index++) {
1826                 u32 action = le32_to_cpu(pa->code[index]);
1827                 u32 regno = (action & 0x0fff0000) >> 16;
1828
1829                 switch(action & 0xf0000000) {
1830                 case PHY_READ:
1831                 case PHY_DATA_OR:
1832                 case PHY_DATA_AND:
1833                 case PHY_READ_EFUSE:
1834                 case PHY_CLEAR_READCOUNT:
1835                 case PHY_WRITE:
1836                 case PHY_WRITE_PREVIOUS:
1837                 case PHY_DELAY_MS:
1838                         break;
1839
1840                 case PHY_BJMPN:
1841                         if (regno > index) {
1842                                 netif_err(tp, ifup, tp->dev,
1843                                           "Out of range of firmware\n");
1844                                 goto out;
1845                         }
1846                         break;
1847                 case PHY_READCOUNT_EQ_SKIP:
1848                         if (index + 2 >= pa->size) {
1849                                 netif_err(tp, ifup, tp->dev,
1850                                           "Out of range of firmware\n");
1851                                 goto out;
1852                         }
1853                         break;
1854                 case PHY_COMP_EQ_SKIPN:
1855                 case PHY_COMP_NEQ_SKIPN:
1856                 case PHY_SKIPN:
1857                         if (index + 1 + regno >= pa->size) {
1858                                 netif_err(tp, ifup, tp->dev,
1859                                           "Out of range of firmware\n");
1860                                 goto out;
1861                         }
1862                         break;
1863
1864                 case PHY_READ_MAC_BYTE:
1865                 case PHY_WRITE_MAC_BYTE:
1866                 case PHY_WRITE_ERI_WORD:
1867                 default:
1868                         netif_err(tp, ifup, tp->dev,
1869                                   "Invalid action 0x%08x\n", action);
1870                         goto out;
1871                 }
1872         }
1873         rc = true;
1874 out:
1875         return rc;
1876 }
1877
1878 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1879 {
1880         struct net_device *dev = tp->dev;
1881         int rc = -EINVAL;
1882
1883         if (!rtl_fw_format_ok(tp, rtl_fw)) {
1884                 netif_err(tp, ifup, dev, "invalid firwmare\n");
1885                 goto out;
1886         }
1887
1888         if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
1889                 rc = 0;
1890 out:
1891         return rc;
1892 }
1893
1894 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
1895 {
1896         struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
1897         u32 predata, count;
1898         size_t index;
1899
1900         predata = count = 0;
1901
1902         for (index = 0; index < pa->size; ) {
1903                 u32 action = le32_to_cpu(pa->code[index]);
1904                 u32 data = action & 0x0000ffff;
1905                 u32 regno = (action & 0x0fff0000) >> 16;
1906
1907                 if (!action)
1908                         break;
1909
1910                 switch(action & 0xf0000000) {
1911                 case PHY_READ:
1912                         predata = rtl_readphy(tp, regno);
1913                         count++;
1914                         index++;
1915                         break;
1916                 case PHY_DATA_OR:
1917                         predata |= data;
1918                         index++;
1919                         break;
1920                 case PHY_DATA_AND:
1921                         predata &= data;
1922                         index++;
1923                         break;
1924                 case PHY_BJMPN:
1925                         index -= regno;
1926                         break;
1927                 case PHY_READ_EFUSE:
1928                         predata = rtl8168d_efuse_read(tp->mmio_addr, regno);
1929                         index++;
1930                         break;
1931                 case PHY_CLEAR_READCOUNT:
1932                         count = 0;
1933                         index++;
1934                         break;
1935                 case PHY_WRITE:
1936                         rtl_writephy(tp, regno, data);
1937                         index++;
1938                         break;
1939                 case PHY_READCOUNT_EQ_SKIP:
1940                         index += (count == data) ? 2 : 1;
1941                         break;
1942                 case PHY_COMP_EQ_SKIPN:
1943                         if (predata == data)
1944                                 index += regno;
1945                         index++;
1946                         break;
1947                 case PHY_COMP_NEQ_SKIPN:
1948                         if (predata != data)
1949                                 index += regno;
1950                         index++;
1951                         break;
1952                 case PHY_WRITE_PREVIOUS:
1953                         rtl_writephy(tp, regno, predata);
1954                         index++;
1955                         break;
1956                 case PHY_SKIPN:
1957                         index += regno + 1;
1958                         break;
1959                 case PHY_DELAY_MS:
1960                         mdelay(data);
1961                         index++;
1962                         break;
1963
1964                 case PHY_READ_MAC_BYTE:
1965                 case PHY_WRITE_MAC_BYTE:
1966                 case PHY_WRITE_ERI_WORD:
1967                 default:
1968                         BUG();
1969                 }
1970         }
1971 }
1972
1973 static void rtl_release_firmware(struct rtl8169_private *tp)
1974 {
1975         if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
1976                 release_firmware(tp->rtl_fw->fw);
1977                 kfree(tp->rtl_fw);
1978         }
1979         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
1980 }
1981
1982 static void rtl_apply_firmware(struct rtl8169_private *tp)
1983 {
1984         struct rtl_fw *rtl_fw = tp->rtl_fw;
1985
1986         /* TODO: release firmware once rtl_phy_write_fw signals failures. */
1987         if (!IS_ERR_OR_NULL(rtl_fw))
1988                 rtl_phy_write_fw(tp, rtl_fw);
1989 }
1990
1991 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
1992 {
1993         if (rtl_readphy(tp, reg) != val)
1994                 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
1995         else
1996                 rtl_apply_firmware(tp);
1997 }
1998
1999 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2000 {
2001         static const struct phy_reg phy_reg_init[] = {
2002                 { 0x1f, 0x0001 },
2003                 { 0x06, 0x006e },
2004                 { 0x08, 0x0708 },
2005                 { 0x15, 0x4000 },
2006                 { 0x18, 0x65c7 },
2007
2008                 { 0x1f, 0x0001 },
2009                 { 0x03, 0x00a1 },
2010                 { 0x02, 0x0008 },
2011                 { 0x01, 0x0120 },
2012                 { 0x00, 0x1000 },
2013                 { 0x04, 0x0800 },
2014                 { 0x04, 0x0000 },
2015
2016                 { 0x03, 0xff41 },
2017                 { 0x02, 0xdf60 },
2018                 { 0x01, 0x0140 },
2019                 { 0x00, 0x0077 },
2020                 { 0x04, 0x7800 },
2021                 { 0x04, 0x7000 },
2022
2023                 { 0x03, 0x802f },
2024                 { 0x02, 0x4f02 },
2025                 { 0x01, 0x0409 },
2026                 { 0x00, 0xf0f9 },
2027                 { 0x04, 0x9800 },
2028                 { 0x04, 0x9000 },
2029
2030                 { 0x03, 0xdf01 },
2031                 { 0x02, 0xdf20 },
2032                 { 0x01, 0xff95 },
2033                 { 0x00, 0xba00 },
2034                 { 0x04, 0xa800 },
2035                 { 0x04, 0xa000 },
2036
2037                 { 0x03, 0xff41 },
2038                 { 0x02, 0xdf20 },
2039                 { 0x01, 0x0140 },
2040                 { 0x00, 0x00bb },
2041                 { 0x04, 0xb800 },
2042                 { 0x04, 0xb000 },
2043
2044                 { 0x03, 0xdf41 },
2045                 { 0x02, 0xdc60 },
2046                 { 0x01, 0x6340 },
2047                 { 0x00, 0x007d },
2048                 { 0x04, 0xd800 },
2049                 { 0x04, 0xd000 },
2050
2051                 { 0x03, 0xdf01 },
2052                 { 0x02, 0xdf20 },
2053                 { 0x01, 0x100a },
2054                 { 0x00, 0xa0ff },
2055                 { 0x04, 0xf800 },
2056                 { 0x04, 0xf000 },
2057
2058                 { 0x1f, 0x0000 },
2059                 { 0x0b, 0x0000 },
2060                 { 0x00, 0x9200 }
2061         };
2062
2063         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2064 }
2065
2066 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2067 {
2068         static const struct phy_reg phy_reg_init[] = {
2069                 { 0x1f, 0x0002 },
2070                 { 0x01, 0x90d0 },
2071                 { 0x1f, 0x0000 }
2072         };
2073
2074         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2075 }
2076
2077 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2078 {
2079         struct pci_dev *pdev = tp->pci_dev;
2080         u16 vendor_id, device_id;
2081
2082         pci_read_config_word(pdev, PCI_SUBSYSTEM_VENDOR_ID, &vendor_id);
2083         pci_read_config_word(pdev, PCI_SUBSYSTEM_ID, &device_id);
2084
2085         if ((vendor_id != PCI_VENDOR_ID_GIGABYTE) || (device_id != 0xe000))
2086                 return;
2087
2088         rtl_writephy(tp, 0x1f, 0x0001);
2089         rtl_writephy(tp, 0x10, 0xf01b);
2090         rtl_writephy(tp, 0x1f, 0x0000);
2091 }
2092
2093 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2094 {
2095         static const struct phy_reg phy_reg_init[] = {
2096                 { 0x1f, 0x0001 },
2097                 { 0x04, 0x0000 },
2098                 { 0x03, 0x00a1 },
2099                 { 0x02, 0x0008 },
2100                 { 0x01, 0x0120 },
2101                 { 0x00, 0x1000 },
2102                 { 0x04, 0x0800 },
2103                 { 0x04, 0x9000 },
2104                 { 0x03, 0x802f },
2105                 { 0x02, 0x4f02 },
2106                 { 0x01, 0x0409 },
2107                 { 0x00, 0xf099 },
2108                 { 0x04, 0x9800 },
2109                 { 0x04, 0xa000 },
2110                 { 0x03, 0xdf01 },
2111                 { 0x02, 0xdf20 },
2112                 { 0x01, 0xff95 },
2113                 { 0x00, 0xba00 },
2114                 { 0x04, 0xa800 },
2115                 { 0x04, 0xf000 },
2116                 { 0x03, 0xdf01 },
2117                 { 0x02, 0xdf20 },
2118                 { 0x01, 0x101a },
2119                 { 0x00, 0xa0ff },
2120                 { 0x04, 0xf800 },
2121                 { 0x04, 0x0000 },
2122                 { 0x1f, 0x0000 },
2123
2124                 { 0x1f, 0x0001 },
2125                 { 0x10, 0xf41b },
2126                 { 0x14, 0xfb54 },
2127                 { 0x18, 0xf5c7 },
2128                 { 0x1f, 0x0000 },
2129
2130                 { 0x1f, 0x0001 },
2131                 { 0x17, 0x0cc0 },
2132                 { 0x1f, 0x0000 }
2133         };
2134
2135         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2136
2137         rtl8169scd_hw_phy_config_quirk(tp);
2138 }
2139
2140 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2141 {
2142         static const struct phy_reg phy_reg_init[] = {
2143                 { 0x1f, 0x0001 },
2144                 { 0x04, 0x0000 },
2145                 { 0x03, 0x00a1 },
2146                 { 0x02, 0x0008 },
2147                 { 0x01, 0x0120 },
2148                 { 0x00, 0x1000 },
2149                 { 0x04, 0x0800 },
2150                 { 0x04, 0x9000 },
2151                 { 0x03, 0x802f },
2152                 { 0x02, 0x4f02 },
2153                 { 0x01, 0x0409 },
2154                 { 0x00, 0xf099 },
2155                 { 0x04, 0x9800 },
2156                 { 0x04, 0xa000 },
2157                 { 0x03, 0xdf01 },
2158                 { 0x02, 0xdf20 },
2159                 { 0x01, 0xff95 },
2160                 { 0x00, 0xba00 },
2161                 { 0x04, 0xa800 },
2162                 { 0x04, 0xf000 },
2163                 { 0x03, 0xdf01 },
2164                 { 0x02, 0xdf20 },
2165                 { 0x01, 0x101a },
2166                 { 0x00, 0xa0ff },
2167                 { 0x04, 0xf800 },
2168                 { 0x04, 0x0000 },
2169                 { 0x1f, 0x0000 },
2170
2171                 { 0x1f, 0x0001 },
2172                 { 0x0b, 0x8480 },
2173                 { 0x1f, 0x0000 },
2174
2175                 { 0x1f, 0x0001 },
2176                 { 0x18, 0x67c7 },
2177                 { 0x04, 0x2000 },
2178                 { 0x03, 0x002f },
2179                 { 0x02, 0x4360 },
2180                 { 0x01, 0x0109 },
2181                 { 0x00, 0x3022 },
2182                 { 0x04, 0x2800 },
2183                 { 0x1f, 0x0000 },
2184
2185                 { 0x1f, 0x0001 },
2186                 { 0x17, 0x0cc0 },
2187                 { 0x1f, 0x0000 }
2188         };
2189
2190         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2191 }
2192
2193 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2194 {
2195         static const struct phy_reg phy_reg_init[] = {
2196                 { 0x10, 0xf41b },
2197                 { 0x1f, 0x0000 }
2198         };
2199
2200         rtl_writephy(tp, 0x1f, 0x0001);
2201         rtl_patchphy(tp, 0x16, 1 << 0);
2202
2203         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2204 }
2205
2206 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2207 {
2208         static const struct phy_reg phy_reg_init[] = {
2209                 { 0x1f, 0x0001 },
2210                 { 0x10, 0xf41b },
2211                 { 0x1f, 0x0000 }
2212         };
2213
2214         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2215 }
2216
2217 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2218 {
2219         static const struct phy_reg phy_reg_init[] = {
2220                 { 0x1f, 0x0000 },
2221                 { 0x1d, 0x0f00 },
2222                 { 0x1f, 0x0002 },
2223                 { 0x0c, 0x1ec8 },
2224                 { 0x1f, 0x0000 }
2225         };
2226
2227         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2228 }
2229
2230 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2231 {
2232         static const struct phy_reg phy_reg_init[] = {
2233                 { 0x1f, 0x0001 },
2234                 { 0x1d, 0x3d98 },
2235                 { 0x1f, 0x0000 }
2236         };
2237
2238         rtl_writephy(tp, 0x1f, 0x0000);
2239         rtl_patchphy(tp, 0x14, 1 << 5);
2240         rtl_patchphy(tp, 0x0d, 1 << 5);
2241
2242         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2243 }
2244
2245 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2246 {
2247         static const struct phy_reg phy_reg_init[] = {
2248                 { 0x1f, 0x0001 },
2249                 { 0x12, 0x2300 },
2250                 { 0x1f, 0x0002 },
2251                 { 0x00, 0x88d4 },
2252                 { 0x01, 0x82b1 },
2253                 { 0x03, 0x7002 },
2254                 { 0x08, 0x9e30 },
2255                 { 0x09, 0x01f0 },
2256                 { 0x0a, 0x5500 },
2257                 { 0x0c, 0x00c8 },
2258                 { 0x1f, 0x0003 },
2259                 { 0x12, 0xc096 },
2260                 { 0x16, 0x000a },
2261                 { 0x1f, 0x0000 },
2262                 { 0x1f, 0x0000 },
2263                 { 0x09, 0x2000 },
2264                 { 0x09, 0x0000 }
2265         };
2266
2267         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2268
2269         rtl_patchphy(tp, 0x14, 1 << 5);
2270         rtl_patchphy(tp, 0x0d, 1 << 5);
2271         rtl_writephy(tp, 0x1f, 0x0000);
2272 }
2273
2274 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2275 {
2276         static const struct phy_reg phy_reg_init[] = {
2277                 { 0x1f, 0x0001 },
2278                 { 0x12, 0x2300 },
2279                 { 0x03, 0x802f },
2280                 { 0x02, 0x4f02 },
2281                 { 0x01, 0x0409 },
2282                 { 0x00, 0xf099 },
2283                 { 0x04, 0x9800 },
2284                 { 0x04, 0x9000 },
2285                 { 0x1d, 0x3d98 },
2286                 { 0x1f, 0x0002 },
2287                 { 0x0c, 0x7eb8 },
2288                 { 0x06, 0x0761 },
2289                 { 0x1f, 0x0003 },
2290                 { 0x16, 0x0f0a },
2291                 { 0x1f, 0x0000 }
2292         };
2293
2294         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2295
2296         rtl_patchphy(tp, 0x16, 1 << 0);
2297         rtl_patchphy(tp, 0x14, 1 << 5);
2298         rtl_patchphy(tp, 0x0d, 1 << 5);
2299         rtl_writephy(tp, 0x1f, 0x0000);
2300 }
2301
2302 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2303 {
2304         static const struct phy_reg phy_reg_init[] = {
2305                 { 0x1f, 0x0001 },
2306                 { 0x12, 0x2300 },
2307                 { 0x1d, 0x3d98 },
2308                 { 0x1f, 0x0002 },
2309                 { 0x0c, 0x7eb8 },
2310                 { 0x06, 0x5461 },
2311                 { 0x1f, 0x0003 },
2312                 { 0x16, 0x0f0a },
2313                 { 0x1f, 0x0000 }
2314         };
2315
2316         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2317
2318         rtl_patchphy(tp, 0x16, 1 << 0);
2319         rtl_patchphy(tp, 0x14, 1 << 5);
2320         rtl_patchphy(tp, 0x0d, 1 << 5);
2321         rtl_writephy(tp, 0x1f, 0x0000);
2322 }
2323
2324 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2325 {
2326         rtl8168c_3_hw_phy_config(tp);
2327 }
2328
2329 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2330 {
2331         static const struct phy_reg phy_reg_init_0[] = {
2332                 /* Channel Estimation */
2333                 { 0x1f, 0x0001 },
2334                 { 0x06, 0x4064 },
2335                 { 0x07, 0x2863 },
2336                 { 0x08, 0x059c },
2337                 { 0x09, 0x26b4 },
2338                 { 0x0a, 0x6a19 },
2339                 { 0x0b, 0xdcc8 },
2340                 { 0x10, 0xf06d },
2341                 { 0x14, 0x7f68 },
2342                 { 0x18, 0x7fd9 },
2343                 { 0x1c, 0xf0ff },
2344                 { 0x1d, 0x3d9c },
2345                 { 0x1f, 0x0003 },
2346                 { 0x12, 0xf49f },
2347                 { 0x13, 0x070b },
2348                 { 0x1a, 0x05ad },
2349                 { 0x14, 0x94c0 },
2350
2351                 /*
2352                  * Tx Error Issue
2353                  * Enhance line driver power
2354                  */
2355                 { 0x1f, 0x0002 },
2356                 { 0x06, 0x5561 },
2357                 { 0x1f, 0x0005 },
2358                 { 0x05, 0x8332 },
2359                 { 0x06, 0x5561 },
2360
2361                 /*
2362                  * Can not link to 1Gbps with bad cable
2363                  * Decrease SNR threshold form 21.07dB to 19.04dB
2364                  */
2365                 { 0x1f, 0x0001 },
2366                 { 0x17, 0x0cc0 },
2367
2368                 { 0x1f, 0x0000 },
2369                 { 0x0d, 0xf880 }
2370         };
2371         void __iomem *ioaddr = tp->mmio_addr;
2372
2373         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2374
2375         /*
2376          * Rx Error Issue
2377          * Fine Tune Switching regulator parameter
2378          */
2379         rtl_writephy(tp, 0x1f, 0x0002);
2380         rtl_w1w0_phy(tp, 0x0b, 0x0010, 0x00ef);
2381         rtl_w1w0_phy(tp, 0x0c, 0xa200, 0x5d00);
2382
2383         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2384                 static const struct phy_reg phy_reg_init[] = {
2385                         { 0x1f, 0x0002 },
2386                         { 0x05, 0x669a },
2387                         { 0x1f, 0x0005 },
2388                         { 0x05, 0x8330 },
2389                         { 0x06, 0x669a },
2390                         { 0x1f, 0x0002 }
2391                 };
2392                 int val;
2393
2394                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2395
2396                 val = rtl_readphy(tp, 0x0d);
2397
2398                 if ((val & 0x00ff) != 0x006c) {
2399                         static const u32 set[] = {
2400                                 0x0065, 0x0066, 0x0067, 0x0068,
2401                                 0x0069, 0x006a, 0x006b, 0x006c
2402                         };
2403                         int i;
2404
2405                         rtl_writephy(tp, 0x1f, 0x0002);
2406
2407                         val &= 0xff00;
2408                         for (i = 0; i < ARRAY_SIZE(set); i++)
2409                                 rtl_writephy(tp, 0x0d, val | set[i]);
2410                 }
2411         } else {
2412                 static const struct phy_reg phy_reg_init[] = {
2413                         { 0x1f, 0x0002 },
2414                         { 0x05, 0x6662 },
2415                         { 0x1f, 0x0005 },
2416                         { 0x05, 0x8330 },
2417                         { 0x06, 0x6662 }
2418                 };
2419
2420                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2421         }
2422
2423         /* RSET couple improve */
2424         rtl_writephy(tp, 0x1f, 0x0002);
2425         rtl_patchphy(tp, 0x0d, 0x0300);
2426         rtl_patchphy(tp, 0x0f, 0x0010);
2427
2428         /* Fine tune PLL performance */
2429         rtl_writephy(tp, 0x1f, 0x0002);
2430         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2431         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2432
2433         rtl_writephy(tp, 0x1f, 0x0005);
2434         rtl_writephy(tp, 0x05, 0x001b);
2435
2436         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2437
2438         rtl_writephy(tp, 0x1f, 0x0000);
2439 }
2440
2441 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2442 {
2443         static const struct phy_reg phy_reg_init_0[] = {
2444                 /* Channel Estimation */
2445                 { 0x1f, 0x0001 },
2446                 { 0x06, 0x4064 },
2447                 { 0x07, 0x2863 },
2448                 { 0x08, 0x059c },
2449                 { 0x09, 0x26b4 },
2450                 { 0x0a, 0x6a19 },
2451                 { 0x0b, 0xdcc8 },
2452                 { 0x10, 0xf06d },
2453                 { 0x14, 0x7f68 },
2454                 { 0x18, 0x7fd9 },
2455                 { 0x1c, 0xf0ff },
2456                 { 0x1d, 0x3d9c },
2457                 { 0x1f, 0x0003 },
2458                 { 0x12, 0xf49f },
2459                 { 0x13, 0x070b },
2460                 { 0x1a, 0x05ad },
2461                 { 0x14, 0x94c0 },
2462
2463                 /*
2464                  * Tx Error Issue
2465                  * Enhance line driver power
2466                  */
2467                 { 0x1f, 0x0002 },
2468                 { 0x06, 0x5561 },
2469                 { 0x1f, 0x0005 },
2470                 { 0x05, 0x8332 },
2471                 { 0x06, 0x5561 },
2472
2473                 /*
2474                  * Can not link to 1Gbps with bad cable
2475                  * Decrease SNR threshold form 21.07dB to 19.04dB
2476                  */
2477                 { 0x1f, 0x0001 },
2478                 { 0x17, 0x0cc0 },
2479
2480                 { 0x1f, 0x0000 },
2481                 { 0x0d, 0xf880 }
2482         };
2483         void __iomem *ioaddr = tp->mmio_addr;
2484
2485         rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2486
2487         if (rtl8168d_efuse_read(ioaddr, 0x01) == 0xb1) {
2488                 static const struct phy_reg phy_reg_init[] = {
2489                         { 0x1f, 0x0002 },
2490                         { 0x05, 0x669a },
2491                         { 0x1f, 0x0005 },
2492                         { 0x05, 0x8330 },
2493                         { 0x06, 0x669a },
2494
2495                         { 0x1f, 0x0002 }
2496                 };
2497                 int val;
2498
2499                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2500
2501                 val = rtl_readphy(tp, 0x0d);
2502                 if ((val & 0x00ff) != 0x006c) {
2503                         static const u32 set[] = {
2504                                 0x0065, 0x0066, 0x0067, 0x0068,
2505                                 0x0069, 0x006a, 0x006b, 0x006c
2506                         };
2507                         int i;
2508
2509                         rtl_writephy(tp, 0x1f, 0x0002);
2510
2511                         val &= 0xff00;
2512                         for (i = 0; i < ARRAY_SIZE(set); i++)
2513                                 rtl_writephy(tp, 0x0d, val | set[i]);
2514                 }
2515         } else {
2516                 static const struct phy_reg phy_reg_init[] = {
2517                         { 0x1f, 0x0002 },
2518                         { 0x05, 0x2642 },
2519                         { 0x1f, 0x0005 },
2520                         { 0x05, 0x8330 },
2521                         { 0x06, 0x2642 }
2522                 };
2523
2524                 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2525         }
2526
2527         /* Fine tune PLL performance */
2528         rtl_writephy(tp, 0x1f, 0x0002);
2529         rtl_w1w0_phy(tp, 0x02, 0x0100, 0x0600);
2530         rtl_w1w0_phy(tp, 0x03, 0x0000, 0xe000);
2531
2532         /* Switching regulator Slew rate */
2533         rtl_writephy(tp, 0x1f, 0x0002);
2534         rtl_patchphy(tp, 0x0f, 0x0017);
2535
2536         rtl_writephy(tp, 0x1f, 0x0005);
2537         rtl_writephy(tp, 0x05, 0x001b);
2538
2539         rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
2540
2541         rtl_writephy(tp, 0x1f, 0x0000);
2542 }
2543
2544 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
2545 {
2546         static const struct phy_reg phy_reg_init[] = {
2547                 { 0x1f, 0x0002 },
2548                 { 0x10, 0x0008 },
2549                 { 0x0d, 0x006c },
2550
2551                 { 0x1f, 0x0000 },
2552                 { 0x0d, 0xf880 },
2553
2554                 { 0x1f, 0x0001 },
2555                 { 0x17, 0x0cc0 },
2556
2557                 { 0x1f, 0x0001 },
2558                 { 0x0b, 0xa4d8 },
2559                 { 0x09, 0x281c },
2560                 { 0x07, 0x2883 },
2561                 { 0x0a, 0x6b35 },
2562                 { 0x1d, 0x3da4 },
2563                 { 0x1c, 0xeffd },
2564                 { 0x14, 0x7f52 },
2565                 { 0x18, 0x7fc6 },
2566                 { 0x08, 0x0601 },
2567                 { 0x06, 0x4063 },
2568                 { 0x10, 0xf074 },
2569                 { 0x1f, 0x0003 },
2570                 { 0x13, 0x0789 },
2571                 { 0x12, 0xf4bd },
2572                 { 0x1a, 0x04fd },
2573                 { 0x14, 0x84b0 },
2574                 { 0x1f, 0x0000 },
2575                 { 0x00, 0x9200 },
2576
2577                 { 0x1f, 0x0005 },
2578                 { 0x01, 0x0340 },
2579                 { 0x1f, 0x0001 },
2580                 { 0x04, 0x4000 },
2581                 { 0x03, 0x1d21 },
2582                 { 0x02, 0x0c32 },
2583                 { 0x01, 0x0200 },
2584                 { 0x00, 0x5554 },
2585                 { 0x04, 0x4800 },
2586                 { 0x04, 0x4000 },
2587                 { 0x04, 0xf000 },
2588                 { 0x03, 0xdf01 },
2589                 { 0x02, 0xdf20 },
2590                 { 0x01, 0x101a },
2591                 { 0x00, 0xa0ff },
2592                 { 0x04, 0xf800 },
2593                 { 0x04, 0xf000 },
2594                 { 0x1f, 0x0000 },
2595
2596                 { 0x1f, 0x0007 },
2597                 { 0x1e, 0x0023 },
2598                 { 0x16, 0x0000 },
2599                 { 0x1f, 0x0000 }
2600         };
2601
2602         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2603 }
2604
2605 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
2606 {
2607         static const struct phy_reg phy_reg_init[] = {
2608                 { 0x1f, 0x0001 },
2609                 { 0x17, 0x0cc0 },
2610
2611                 { 0x1f, 0x0007 },
2612                 { 0x1e, 0x002d },
2613                 { 0x18, 0x0040 },
2614                 { 0x1f, 0x0000 }
2615         };
2616
2617         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2618         rtl_patchphy(tp, 0x0d, 1 << 5);
2619 }
2620
2621 static void rtl8168e_hw_phy_config(struct rtl8169_private *tp)
2622 {
2623         static const struct phy_reg phy_reg_init[] = {
2624                 /* Enable Delay cap */
2625                 { 0x1f, 0x0005 },
2626                 { 0x05, 0x8b80 },
2627                 { 0x06, 0xc896 },
2628                 { 0x1f, 0x0000 },
2629
2630                 /* Channel estimation fine tune */
2631                 { 0x1f, 0x0001 },
2632                 { 0x0b, 0x6c20 },
2633                 { 0x07, 0x2872 },
2634                 { 0x1c, 0xefff },
2635                 { 0x1f, 0x0003 },
2636                 { 0x14, 0x6420 },
2637                 { 0x1f, 0x0000 },
2638
2639                 /* Update PFM & 10M TX idle timer */
2640                 { 0x1f, 0x0007 },
2641                 { 0x1e, 0x002f },
2642                 { 0x15, 0x1919 },
2643                 { 0x1f, 0x0000 },
2644
2645                 { 0x1f, 0x0007 },
2646                 { 0x1e, 0x00ac },
2647                 { 0x18, 0x0006 },
2648                 { 0x1f, 0x0000 }
2649         };
2650
2651         rtl_apply_firmware(tp);
2652
2653         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2654
2655         /* DCO enable for 10M IDLE Power */
2656         rtl_writephy(tp, 0x1f, 0x0007);
2657         rtl_writephy(tp, 0x1e, 0x0023);
2658         rtl_w1w0_phy(tp, 0x17, 0x0006, 0x0000);
2659         rtl_writephy(tp, 0x1f, 0x0000);
2660
2661         /* For impedance matching */
2662         rtl_writephy(tp, 0x1f, 0x0002);
2663         rtl_w1w0_phy(tp, 0x08, 0x8000, 0x7f00);
2664         rtl_writephy(tp, 0x1f, 0x0000);
2665
2666         /* PHY auto speed down */
2667         rtl_writephy(tp, 0x1f, 0x0007);
2668         rtl_writephy(tp, 0x1e, 0x002d);
2669         rtl_w1w0_phy(tp, 0x18, 0x0050, 0x0000);
2670         rtl_writephy(tp, 0x1f, 0x0000);
2671         rtl_w1w0_phy(tp, 0x14, 0x8000, 0x0000);
2672
2673         rtl_writephy(tp, 0x1f, 0x0005);
2674         rtl_writephy(tp, 0x05, 0x8b86);
2675         rtl_w1w0_phy(tp, 0x06, 0x0001, 0x0000);
2676         rtl_writephy(tp, 0x1f, 0x0000);
2677
2678         rtl_writephy(tp, 0x1f, 0x0005);
2679         rtl_writephy(tp, 0x05, 0x8b85);
2680         rtl_w1w0_phy(tp, 0x06, 0x0000, 0x2000);
2681         rtl_writephy(tp, 0x1f, 0x0007);
2682         rtl_writephy(tp, 0x1e, 0x0020);
2683         rtl_w1w0_phy(tp, 0x15, 0x0000, 0x1100);
2684         rtl_writephy(tp, 0x1f, 0x0006);
2685         rtl_writephy(tp, 0x00, 0x5a00);
2686         rtl_writephy(tp, 0x1f, 0x0000);
2687         rtl_writephy(tp, 0x0d, 0x0007);
2688         rtl_writephy(tp, 0x0e, 0x003c);
2689         rtl_writephy(tp, 0x0d, 0x4007);
2690         rtl_writephy(tp, 0x0e, 0x0000);
2691         rtl_writephy(tp, 0x0d, 0x0000);
2692 }
2693
2694 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
2695 {
2696         static const struct phy_reg phy_reg_init[] = {
2697                 { 0x1f, 0x0003 },
2698                 { 0x08, 0x441d },
2699                 { 0x01, 0x9100 },
2700                 { 0x1f, 0x0000 }
2701         };
2702
2703         rtl_writephy(tp, 0x1f, 0x0000);
2704         rtl_patchphy(tp, 0x11, 1 << 12);
2705         rtl_patchphy(tp, 0x19, 1 << 13);
2706         rtl_patchphy(tp, 0x10, 1 << 15);
2707
2708         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2709 }
2710
2711 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
2712 {
2713         static const struct phy_reg phy_reg_init[] = {
2714                 { 0x1f, 0x0005 },
2715                 { 0x1a, 0x0000 },
2716                 { 0x1f, 0x0000 },
2717
2718                 { 0x1f, 0x0004 },
2719                 { 0x1c, 0x0000 },
2720                 { 0x1f, 0x0000 },
2721
2722                 { 0x1f, 0x0001 },
2723                 { 0x15, 0x7701 },
2724                 { 0x1f, 0x0000 }
2725         };
2726
2727         /* Disable ALDPS before ram code */
2728         rtl_writephy(tp, 0x1f, 0x0000);
2729         rtl_writephy(tp, 0x18, 0x0310);
2730         msleep(100);
2731
2732         rtl_apply_firmware(tp);
2733
2734         rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2735 }
2736
2737 static void rtl_hw_phy_config(struct net_device *dev)
2738 {
2739         struct rtl8169_private *tp = netdev_priv(dev);
2740
2741         rtl8169_print_mac_version(tp);
2742
2743         switch (tp->mac_version) {
2744         case RTL_GIGA_MAC_VER_01:
2745                 break;
2746         case RTL_GIGA_MAC_VER_02:
2747         case RTL_GIGA_MAC_VER_03:
2748                 rtl8169s_hw_phy_config(tp);
2749                 break;
2750         case RTL_GIGA_MAC_VER_04:
2751                 rtl8169sb_hw_phy_config(tp);
2752                 break;
2753         case RTL_GIGA_MAC_VER_05:
2754                 rtl8169scd_hw_phy_config(tp);
2755                 break;
2756         case RTL_GIGA_MAC_VER_06:
2757                 rtl8169sce_hw_phy_config(tp);
2758                 break;
2759         case RTL_GIGA_MAC_VER_07:
2760         case RTL_GIGA_MAC_VER_08:
2761         case RTL_GIGA_MAC_VER_09:
2762                 rtl8102e_hw_phy_config(tp);
2763                 break;
2764         case RTL_GIGA_MAC_VER_11:
2765                 rtl8168bb_hw_phy_config(tp);
2766                 break;
2767         case RTL_GIGA_MAC_VER_12:
2768                 rtl8168bef_hw_phy_config(tp);
2769                 break;
2770         case RTL_GIGA_MAC_VER_17:
2771                 rtl8168bef_hw_phy_config(tp);
2772                 break;
2773         case RTL_GIGA_MAC_VER_18:
2774                 rtl8168cp_1_hw_phy_config(tp);
2775                 break;
2776         case RTL_GIGA_MAC_VER_19:
2777                 rtl8168c_1_hw_phy_config(tp);
2778                 break;
2779         case RTL_GIGA_MAC_VER_20:
2780                 rtl8168c_2_hw_phy_config(tp);
2781                 break;
2782         case RTL_GIGA_MAC_VER_21:
2783                 rtl8168c_3_hw_phy_config(tp);
2784                 break;
2785         case RTL_GIGA_MAC_VER_22:
2786                 rtl8168c_4_hw_phy_config(tp);
2787                 break;
2788         case RTL_GIGA_MAC_VER_23:
2789         case RTL_GIGA_MAC_VER_24:
2790                 rtl8168cp_2_hw_phy_config(tp);
2791                 break;
2792         case RTL_GIGA_MAC_VER_25:
2793                 rtl8168d_1_hw_phy_config(tp);
2794                 break;
2795         case RTL_GIGA_MAC_VER_26:
2796                 rtl8168d_2_hw_phy_config(tp);
2797                 break;
2798         case RTL_GIGA_MAC_VER_27:
2799                 rtl8168d_3_hw_phy_config(tp);
2800                 break;
2801         case RTL_GIGA_MAC_VER_28:
2802                 rtl8168d_4_hw_phy_config(tp);
2803                 break;
2804         case RTL_GIGA_MAC_VER_29:
2805         case RTL_GIGA_MAC_VER_30:
2806                 rtl8105e_hw_phy_config(tp);
2807                 break;
2808         case RTL_GIGA_MAC_VER_31:
2809                 /* None. */
2810                 break;
2811         case RTL_GIGA_MAC_VER_32:
2812         case RTL_GIGA_MAC_VER_33:
2813                 rtl8168e_hw_phy_config(tp);
2814                 break;
2815
2816         default:
2817                 break;
2818         }
2819 }
2820
2821 static void rtl8169_phy_timer(unsigned long __opaque)
2822 {
2823         struct net_device *dev = (struct net_device *)__opaque;
2824         struct rtl8169_private *tp = netdev_priv(dev);
2825         struct timer_list *timer = &tp->timer;
2826         void __iomem *ioaddr = tp->mmio_addr;
2827         unsigned long timeout = RTL8169_PHY_TIMEOUT;
2828
2829         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
2830
2831         spin_lock_irq(&tp->lock);
2832
2833         if (tp->phy_reset_pending(tp)) {
2834                 /*
2835                  * A busy loop could burn quite a few cycles on nowadays CPU.
2836                  * Let's delay the execution of the timer for a few ticks.
2837                  */
2838                 timeout = HZ/10;
2839                 goto out_mod_timer;
2840         }
2841
2842         if (tp->link_ok(ioaddr))
2843                 goto out_unlock;
2844
2845         netif_warn(tp, link, dev, "PHY reset until link up\n");
2846
2847         tp->phy_reset_enable(tp);
2848
2849 out_mod_timer:
2850         mod_timer(timer, jiffies + timeout);
2851 out_unlock:
2852         spin_unlock_irq(&tp->lock);
2853 }
2854
2855 #ifdef CONFIG_NET_POLL_CONTROLLER
2856 /*
2857  * Polling 'interrupt' - used by things like netconsole to send skbs
2858  * without having to re-enable interrupts. It's not called while
2859  * the interrupt routine is executing.
2860  */
2861 static void rtl8169_netpoll(struct net_device *dev)
2862 {
2863         struct rtl8169_private *tp = netdev_priv(dev);
2864         struct pci_dev *pdev = tp->pci_dev;
2865
2866         disable_irq(pdev->irq);
2867         rtl8169_interrupt(pdev->irq, dev);
2868         enable_irq(pdev->irq);
2869 }
2870 #endif
2871
2872 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
2873                                   void __iomem *ioaddr)
2874 {
2875         iounmap(ioaddr);
2876         pci_release_regions(pdev);
2877         pci_clear_mwi(pdev);
2878         pci_disable_device(pdev);
2879         free_netdev(dev);
2880 }
2881
2882 static void rtl8169_phy_reset(struct net_device *dev,
2883                               struct rtl8169_private *tp)
2884 {
2885         unsigned int i;
2886
2887         tp->phy_reset_enable(tp);
2888         for (i = 0; i < 100; i++) {
2889                 if (!tp->phy_reset_pending(tp))
2890                         return;
2891                 msleep(1);
2892         }
2893         netif_err(tp, link, dev, "PHY reset failed\n");
2894 }
2895
2896 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
2897 {
2898         void __iomem *ioaddr = tp->mmio_addr;
2899
2900         rtl_hw_phy_config(dev);
2901
2902         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
2903                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2904                 RTL_W8(0x82, 0x01);
2905         }
2906
2907         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
2908
2909         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
2910                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
2911
2912         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
2913                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
2914                 RTL_W8(0x82, 0x01);
2915                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
2916                 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
2917         }
2918
2919         rtl8169_phy_reset(dev, tp);
2920
2921         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL,
2922                           ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
2923                           ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
2924                           (tp->mii.supports_gmii ?
2925                            ADVERTISED_1000baseT_Half |
2926                            ADVERTISED_1000baseT_Full : 0));
2927
2928         if (RTL_R8(PHYstatus) & TBI_Enable)
2929                 netif_info(tp, link, dev, "TBI auto-negotiating\n");
2930 }
2931
2932 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
2933 {
2934         void __iomem *ioaddr = tp->mmio_addr;
2935         u32 high;
2936         u32 low;
2937
2938         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
2939         high = addr[4] | (addr[5] << 8);
2940
2941         spin_lock_irq(&tp->lock);
2942
2943         RTL_W8(Cfg9346, Cfg9346_Unlock);
2944
2945         RTL_W32(MAC4, high);
2946         RTL_R32(MAC4);
2947
2948         RTL_W32(MAC0, low);
2949         RTL_R32(MAC0);
2950
2951         RTL_W8(Cfg9346, Cfg9346_Lock);
2952
2953         spin_unlock_irq(&tp->lock);
2954 }
2955
2956 static int rtl_set_mac_address(struct net_device *dev, void *p)
2957 {
2958         struct rtl8169_private *tp = netdev_priv(dev);
2959         struct sockaddr *addr = p;
2960
2961         if (!is_valid_ether_addr(addr->sa_data))
2962                 return -EADDRNOTAVAIL;
2963
2964         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
2965
2966         rtl_rar_set(tp, dev->dev_addr);
2967
2968         return 0;
2969 }
2970
2971 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2972 {
2973         struct rtl8169_private *tp = netdev_priv(dev);
2974         struct mii_ioctl_data *data = if_mii(ifr);
2975
2976         return netif_running(dev) ? tp->do_ioctl(tp, data, cmd) : -ENODEV;
2977 }
2978
2979 static int rtl_xmii_ioctl(struct rtl8169_private *tp,
2980                           struct mii_ioctl_data *data, int cmd)
2981 {
2982         switch (cmd) {
2983         case SIOCGMIIPHY:
2984                 data->phy_id = 32; /* Internal PHY */
2985                 return 0;
2986
2987         case SIOCGMIIREG:
2988                 data->val_out = rtl_readphy(tp, data->reg_num & 0x1f);
2989                 return 0;
2990
2991         case SIOCSMIIREG:
2992                 rtl_writephy(tp, data->reg_num & 0x1f, data->val_in);
2993                 return 0;
2994         }
2995         return -EOPNOTSUPP;
2996 }
2997
2998 static int rtl_tbi_ioctl(struct rtl8169_private *tp, struct mii_ioctl_data *data, int cmd)
2999 {
3000         return -EOPNOTSUPP;
3001 }
3002
3003 static const struct rtl_cfg_info {
3004         void (*hw_start)(struct net_device *);
3005         unsigned int region;
3006         unsigned int align;
3007         u16 intr_event;
3008         u16 napi_event;
3009         unsigned features;
3010         u8 default_ver;
3011 } rtl_cfg_infos [] = {
3012         [RTL_CFG_0] = {
3013                 .hw_start       = rtl_hw_start_8169,
3014                 .region         = 1,
3015                 .align          = 0,
3016                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3017                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3018                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3019                 .features       = RTL_FEATURE_GMII,
3020                 .default_ver    = RTL_GIGA_MAC_VER_01,
3021         },
3022         [RTL_CFG_1] = {
3023                 .hw_start       = rtl_hw_start_8168,
3024                 .region         = 2,
3025                 .align          = 8,
3026                 .intr_event     = SYSErr | LinkChg | RxOverflow |
3027                                   TxErr | TxOK | RxOK | RxErr,
3028                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
3029                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI,
3030                 .default_ver    = RTL_GIGA_MAC_VER_11,
3031         },
3032         [RTL_CFG_2] = {
3033                 .hw_start       = rtl_hw_start_8101,
3034                 .region         = 2,
3035                 .align          = 8,
3036                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
3037                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
3038                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
3039                 .features       = RTL_FEATURE_MSI,
3040                 .default_ver    = RTL_GIGA_MAC_VER_13,
3041         }
3042 };
3043
3044 /* Cfg9346_Unlock assumed. */
3045 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
3046                             const struct rtl_cfg_info *cfg)
3047 {
3048         unsigned msi = 0;
3049         u8 cfg2;
3050
3051         cfg2 = RTL_R8(Config2) & ~MSIEnable;
3052         if (cfg->features & RTL_FEATURE_MSI) {
3053                 if (pci_enable_msi(pdev)) {
3054                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
3055                 } else {
3056                         cfg2 |= MSIEnable;
3057                         msi = RTL_FEATURE_MSI;
3058                 }
3059         }
3060         RTL_W8(Config2, cfg2);
3061         return msi;
3062 }
3063
3064 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
3065 {
3066         if (tp->features & RTL_FEATURE_MSI) {
3067                 pci_disable_msi(pdev);
3068                 tp->features &= ~RTL_FEATURE_MSI;
3069         }
3070 }
3071
3072 static const struct net_device_ops rtl8169_netdev_ops = {
3073         .ndo_open               = rtl8169_open,
3074         .ndo_stop               = rtl8169_close,
3075         .ndo_get_stats          = rtl8169_get_stats,
3076         .ndo_start_xmit         = rtl8169_start_xmit,
3077         .ndo_tx_timeout         = rtl8169_tx_timeout,
3078         .ndo_validate_addr      = eth_validate_addr,
3079         .ndo_change_mtu         = rtl8169_change_mtu,
3080         .ndo_fix_features       = rtl8169_fix_features,
3081         .ndo_set_features       = rtl8169_set_features,
3082         .ndo_set_mac_address    = rtl_set_mac_address,
3083         .ndo_do_ioctl           = rtl8169_ioctl,
3084         .ndo_set_multicast_list = rtl_set_rx_mode,
3085 #ifdef CONFIG_NET_POLL_CONTROLLER
3086         .ndo_poll_controller    = rtl8169_netpoll,
3087 #endif
3088
3089 };
3090
3091 static void __devinit rtl_init_mdio_ops(struct rtl8169_private *tp)
3092 {
3093         struct mdio_ops *ops = &tp->mdio_ops;
3094
3095         switch (tp->mac_version) {
3096         case RTL_GIGA_MAC_VER_27:
3097                 ops->write      = r8168dp_1_mdio_write;
3098                 ops->read       = r8168dp_1_mdio_read;
3099                 break;
3100         case RTL_GIGA_MAC_VER_28:
3101         case RTL_GIGA_MAC_VER_31:
3102                 ops->write      = r8168dp_2_mdio_write;
3103                 ops->read       = r8168dp_2_mdio_read;
3104                 break;
3105         default:
3106                 ops->write      = r8169_mdio_write;
3107                 ops->read       = r8169_mdio_read;
3108                 break;
3109         }
3110 }
3111
3112 static void r810x_phy_power_down(struct rtl8169_private *tp)
3113 {
3114         rtl_writephy(tp, 0x1f, 0x0000);
3115         rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3116 }
3117
3118 static void r810x_phy_power_up(struct rtl8169_private *tp)
3119 {
3120         rtl_writephy(tp, 0x1f, 0x0000);
3121         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3122 }
3123
3124 static void r810x_pll_power_down(struct rtl8169_private *tp)
3125 {
3126         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3127                 rtl_writephy(tp, 0x1f, 0x0000);
3128                 rtl_writephy(tp, MII_BMCR, 0x0000);
3129                 return;
3130         }
3131
3132         r810x_phy_power_down(tp);
3133 }
3134
3135 static void r810x_pll_power_up(struct rtl8169_private *tp)
3136 {
3137         r810x_phy_power_up(tp);
3138 }
3139
3140 static void r8168_phy_power_up(struct rtl8169_private *tp)
3141 {
3142         rtl_writephy(tp, 0x1f, 0x0000);
3143         switch (tp->mac_version) {
3144         case RTL_GIGA_MAC_VER_11:
3145         case RTL_GIGA_MAC_VER_12:
3146         case RTL_GIGA_MAC_VER_17:
3147         case RTL_GIGA_MAC_VER_18:
3148         case RTL_GIGA_MAC_VER_19:
3149         case RTL_GIGA_MAC_VER_20:
3150         case RTL_GIGA_MAC_VER_21:
3151         case RTL_GIGA_MAC_VER_22:
3152         case RTL_GIGA_MAC_VER_23:
3153         case RTL_GIGA_MAC_VER_24:
3154         case RTL_GIGA_MAC_VER_25:
3155         case RTL_GIGA_MAC_VER_26:
3156         case RTL_GIGA_MAC_VER_27:
3157         case RTL_GIGA_MAC_VER_28:
3158         case RTL_GIGA_MAC_VER_31:
3159                 rtl_writephy(tp, 0x0e, 0x0000);
3160                 break;
3161         default:
3162                 break;
3163         }
3164         rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE);
3165 }
3166
3167 static void r8168_phy_power_down(struct rtl8169_private *tp)
3168 {
3169         rtl_writephy(tp, 0x1f, 0x0000);
3170         switch (tp->mac_version) {
3171         case RTL_GIGA_MAC_VER_32:
3172         case RTL_GIGA_MAC_VER_33:
3173                 rtl_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_PDOWN);
3174                 break;
3175
3176         case RTL_GIGA_MAC_VER_11:
3177         case RTL_GIGA_MAC_VER_12:
3178         case RTL_GIGA_MAC_VER_17:
3179         case RTL_GIGA_MAC_VER_18:
3180         case RTL_GIGA_MAC_VER_19:
3181         case RTL_GIGA_MAC_VER_20:
3182         case RTL_GIGA_MAC_VER_21:
3183         case RTL_GIGA_MAC_VER_22:
3184         case RTL_GIGA_MAC_VER_23:
3185         case RTL_GIGA_MAC_VER_24:
3186         case RTL_GIGA_MAC_VER_25:
3187         case RTL_GIGA_MAC_VER_26:
3188         case RTL_GIGA_MAC_VER_27:
3189         case RTL_GIGA_MAC_VER_28:
3190         case RTL_GIGA_MAC_VER_31:
3191                 rtl_writephy(tp, 0x0e, 0x0200);
3192         default:
3193                 rtl_writephy(tp, MII_BMCR, BMCR_PDOWN);
3194                 break;
3195         }
3196 }
3197
3198 static void r8168_pll_power_down(struct rtl8169_private *tp)
3199 {
3200         void __iomem *ioaddr = tp->mmio_addr;
3201
3202         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3203              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3204              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3205             r8168dp_check_dash(tp)) {
3206                 return;
3207         }
3208
3209         if ((tp->mac_version == RTL_GIGA_MAC_VER_23 ||
3210              tp->mac_version == RTL_GIGA_MAC_VER_24) &&
3211             (RTL_R16(CPlusCmd) & ASF)) {
3212                 return;
3213         }
3214
3215         if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
3216             tp->mac_version == RTL_GIGA_MAC_VER_33)
3217                 rtl_ephy_write(ioaddr, 0x19, 0xff64);
3218
3219         if (__rtl8169_get_wol(tp) & WAKE_ANY) {
3220                 rtl_writephy(tp, 0x1f, 0x0000);
3221                 rtl_writephy(tp, MII_BMCR, 0x0000);
3222
3223                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
3224                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
3225                 return;
3226         }
3227
3228         r8168_phy_power_down(tp);
3229
3230         switch (tp->mac_version) {
3231         case RTL_GIGA_MAC_VER_25:
3232         case RTL_GIGA_MAC_VER_26:
3233         case RTL_GIGA_MAC_VER_27:
3234         case RTL_GIGA_MAC_VER_28:
3235         case RTL_GIGA_MAC_VER_31:
3236         case RTL_GIGA_MAC_VER_32:
3237         case RTL_GIGA_MAC_VER_33:
3238                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
3239                 break;
3240         }
3241 }
3242
3243 static void r8168_pll_power_up(struct rtl8169_private *tp)
3244 {
3245         void __iomem *ioaddr = tp->mmio_addr;
3246
3247         if ((tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3248              tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3249              tp->mac_version == RTL_GIGA_MAC_VER_31) &&
3250             r8168dp_check_dash(tp)) {
3251                 return;
3252         }
3253
3254         switch (tp->mac_version) {
3255         case RTL_GIGA_MAC_VER_25:
3256         case RTL_GIGA_MAC_VER_26:
3257         case RTL_GIGA_MAC_VER_27:
3258         case RTL_GIGA_MAC_VER_28:
3259         case RTL_GIGA_MAC_VER_31:
3260         case RTL_GIGA_MAC_VER_32:
3261         case RTL_GIGA_MAC_VER_33:
3262                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
3263                 break;
3264         }
3265
3266         r8168_phy_power_up(tp);
3267 }
3268
3269 static void rtl_pll_power_op(struct rtl8169_private *tp,
3270                              void (*op)(struct rtl8169_private *))
3271 {
3272         if (op)
3273                 op(tp);
3274 }
3275
3276 static void rtl_pll_power_down(struct rtl8169_private *tp)
3277 {
3278         rtl_pll_power_op(tp, tp->pll_power_ops.down);
3279 }
3280
3281 static void rtl_pll_power_up(struct rtl8169_private *tp)
3282 {
3283         rtl_pll_power_op(tp, tp->pll_power_ops.up);
3284 }
3285
3286 static void __devinit rtl_init_pll_power_ops(struct rtl8169_private *tp)
3287 {
3288         struct pll_power_ops *ops = &tp->pll_power_ops;
3289
3290         switch (tp->mac_version) {
3291         case RTL_GIGA_MAC_VER_07:
3292         case RTL_GIGA_MAC_VER_08:
3293         case RTL_GIGA_MAC_VER_09:
3294         case RTL_GIGA_MAC_VER_10:
3295         case RTL_GIGA_MAC_VER_16:
3296         case RTL_GIGA_MAC_VER_29:
3297         case RTL_GIGA_MAC_VER_30:
3298                 ops->down       = r810x_pll_power_down;
3299                 ops->up         = r810x_pll_power_up;
3300                 break;
3301
3302         case RTL_GIGA_MAC_VER_11:
3303         case RTL_GIGA_MAC_VER_12:
3304         case RTL_GIGA_MAC_VER_17:
3305         case RTL_GIGA_MAC_VER_18:
3306         case RTL_GIGA_MAC_VER_19:
3307         case RTL_GIGA_MAC_VER_20:
3308         case RTL_GIGA_MAC_VER_21:
3309         case RTL_GIGA_MAC_VER_22:
3310         case RTL_GIGA_MAC_VER_23:
3311         case RTL_GIGA_MAC_VER_24:
3312         case RTL_GIGA_MAC_VER_25:
3313         case RTL_GIGA_MAC_VER_26:
3314         case RTL_GIGA_MAC_VER_27:
3315         case RTL_GIGA_MAC_VER_28:
3316         case RTL_GIGA_MAC_VER_31:
3317         case RTL_GIGA_MAC_VER_32:
3318         case RTL_GIGA_MAC_VER_33:
3319                 ops->down       = r8168_pll_power_down;
3320                 ops->up         = r8168_pll_power_up;
3321                 break;
3322
3323         default:
3324                 ops->down       = NULL;
3325                 ops->up         = NULL;
3326                 break;
3327         }
3328 }
3329
3330 static void rtl_hw_reset(struct rtl8169_private *tp)
3331 {
3332         void __iomem *ioaddr = tp->mmio_addr;
3333         int i;
3334
3335         /* Soft reset the chip. */
3336         RTL_W8(ChipCmd, CmdReset);
3337
3338         /* Check that the chip has finished the reset. */
3339         for (i = 0; i < 100; i++) {
3340                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
3341                         break;
3342                 msleep_interruptible(1);
3343         }
3344 }
3345
3346 static int __devinit
3347 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
3348 {
3349         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
3350         const unsigned int region = cfg->region;
3351         struct rtl8169_private *tp;
3352         struct mii_if_info *mii;
3353         struct net_device *dev;
3354         void __iomem *ioaddr;
3355         int chipset, i;
3356         int rc;
3357
3358         if (netif_msg_drv(&debug)) {
3359                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
3360                        MODULENAME, RTL8169_VERSION);
3361         }
3362
3363         dev = alloc_etherdev(sizeof (*tp));
3364         if (!dev) {
3365                 if (netif_msg_drv(&debug))
3366                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
3367                 rc = -ENOMEM;
3368                 goto out;
3369         }
3370
3371         SET_NETDEV_DEV(dev, &pdev->dev);
3372         dev->netdev_ops = &rtl8169_netdev_ops;
3373         tp = netdev_priv(dev);
3374         tp->dev = dev;
3375         tp->pci_dev = pdev;
3376         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
3377
3378         mii = &tp->mii;
3379         mii->dev = dev;
3380         mii->mdio_read = rtl_mdio_read;
3381         mii->mdio_write = rtl_mdio_write;
3382         mii->phy_id_mask = 0x1f;
3383         mii->reg_num_mask = 0x1f;
3384         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
3385
3386         /* disable ASPM completely as that cause random device stop working
3387          * problems as well as full system hangs for some PCIe devices users */
3388         pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
3389                                      PCIE_LINK_STATE_CLKPM);
3390
3391         /* enable device (incl. PCI PM wakeup and hotplug setup) */
3392         rc = pci_enable_device(pdev);
3393         if (rc < 0) {
3394                 netif_err(tp, probe, dev, "enable failure\n");
3395                 goto err_out_free_dev_1;
3396         }
3397
3398         if (pci_set_mwi(pdev) < 0)
3399                 netif_info(tp, probe, dev, "Mem-Wr-Inval unavailable\n");
3400
3401         /* make sure PCI base addr 1 is MMIO */
3402         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
3403                 netif_err(tp, probe, dev,
3404                           "region #%d not an MMIO resource, aborting\n",
3405                           region);
3406                 rc = -ENODEV;
3407                 goto err_out_mwi_2;
3408         }
3409
3410         /* check for weird/broken PCI region reporting */
3411         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
3412                 netif_err(tp, probe, dev,
3413                           "Invalid PCI region size(s), aborting\n");
3414                 rc = -ENODEV;
3415                 goto err_out_mwi_2;
3416         }
3417
3418         rc = pci_request_regions(pdev, MODULENAME);
3419         if (rc < 0) {
3420                 netif_err(tp, probe, dev, "could not request regions\n");
3421                 goto err_out_mwi_2;
3422         }
3423
3424         tp->cp_cmd = RxChkSum;
3425
3426         if ((sizeof(dma_addr_t) > 4) &&
3427             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) && use_dac) {
3428                 tp->cp_cmd |= PCIDAC;
3429                 dev->features |= NETIF_F_HIGHDMA;
3430         } else {
3431                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3432                 if (rc < 0) {
3433                         netif_err(tp, probe, dev, "DMA configuration failed\n");
3434                         goto err_out_free_res_3;
3435                 }
3436         }
3437
3438         /* ioremap MMIO region */
3439         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
3440         if (!ioaddr) {
3441                 netif_err(tp, probe, dev, "cannot remap MMIO, aborting\n");
3442                 rc = -EIO;
3443                 goto err_out_free_res_3;
3444         }
3445         tp->mmio_addr = ioaddr;
3446
3447         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3448         if (!tp->pcie_cap)
3449                 netif_info(tp, probe, dev, "no PCI Express capability\n");
3450
3451         RTL_W16(IntrMask, 0x0000);
3452
3453         rtl_hw_reset(tp);
3454
3455         RTL_W16(IntrStatus, 0xffff);
3456
3457         pci_set_master(pdev);
3458
3459         /* Identify chip attached to board */
3460         rtl8169_get_mac_version(tp, dev, cfg->default_ver);
3461
3462         /*
3463          * Pretend we are using VLANs; This bypasses a nasty bug where
3464          * Interrupts stop flowing on high load on 8110SCd controllers.
3465          */
3466         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3467                 tp->cp_cmd |= RxVlan;
3468
3469         rtl_init_mdio_ops(tp);
3470         rtl_init_pll_power_ops(tp);
3471
3472         rtl8169_print_mac_version(tp);
3473
3474         chipset = tp->mac_version;
3475         tp->txd_version = rtl_chip_infos[chipset].txd_version;
3476
3477         RTL_W8(Cfg9346, Cfg9346_Unlock);
3478         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
3479         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
3480         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
3481                 tp->features |= RTL_FEATURE_WOL;
3482         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
3483                 tp->features |= RTL_FEATURE_WOL;
3484         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
3485         RTL_W8(Cfg9346, Cfg9346_Lock);
3486
3487         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
3488             (RTL_R8(PHYstatus) & TBI_Enable)) {
3489                 tp->set_speed = rtl8169_set_speed_tbi;
3490                 tp->get_settings = rtl8169_gset_tbi;
3491                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
3492                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
3493                 tp->link_ok = rtl8169_tbi_link_ok;
3494                 tp->do_ioctl = rtl_tbi_ioctl;
3495         } else {
3496                 tp->set_speed = rtl8169_set_speed_xmii;
3497                 tp->get_settings = rtl8169_gset_xmii;
3498                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
3499                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
3500                 tp->link_ok = rtl8169_xmii_link_ok;
3501                 tp->do_ioctl = rtl_xmii_ioctl;
3502         }
3503
3504         spin_lock_init(&tp->lock);
3505
3506         /* Get MAC address */
3507         for (i = 0; i < MAC_ADDR_LEN; i++)
3508                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
3509         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3510
3511         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
3512         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
3513         dev->irq = pdev->irq;
3514         dev->base_addr = (unsigned long) ioaddr;
3515
3516         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
3517
3518         /* don't enable SG, IP_CSUM and TSO by default - it might not work
3519          * properly for all devices */
3520         dev->features |= NETIF_F_RXCSUM |
3521                 NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3522
3523         dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3524                 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3525         dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
3526                 NETIF_F_HIGHDMA;
3527
3528         if (tp->mac_version == RTL_GIGA_MAC_VER_05)
3529                 /* 8110SCd requires hardware Rx VLAN - disallow toggling */
3530                 dev->hw_features &= ~NETIF_F_HW_VLAN_RX;
3531
3532         tp->intr_mask = 0xffff;
3533         tp->hw_start = cfg->hw_start;
3534         tp->intr_event = cfg->intr_event;
3535         tp->napi_event = cfg->napi_event;
3536
3537         init_timer(&tp->timer);
3538         tp->timer.data = (unsigned long) dev;
3539         tp->timer.function = rtl8169_phy_timer;
3540
3541         tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
3542
3543         rc = register_netdev(dev);
3544         if (rc < 0)
3545                 goto err_out_msi_4;
3546
3547         pci_set_drvdata(pdev, dev);
3548
3549         netif_info(tp, probe, dev, "%s at 0x%lx, %pM, XID %08x IRQ %d\n",
3550                    rtl_chip_infos[chipset].name, dev->base_addr, dev->dev_addr,
3551                    (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), dev->irq);
3552
3553         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3554             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3555             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3556                 rtl8168_driver_start(tp);
3557         }
3558
3559         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
3560
3561         if (pci_dev_run_wake(pdev))
3562                 pm_runtime_put_noidle(&pdev->dev);
3563
3564         netif_carrier_off(dev);
3565
3566 out:
3567         return rc;
3568
3569 err_out_msi_4:
3570         rtl_disable_msi(pdev, tp);
3571         iounmap(ioaddr);
3572 err_out_free_res_3:
3573         pci_release_regions(pdev);
3574 err_out_mwi_2:
3575         pci_clear_mwi(pdev);
3576         pci_disable_device(pdev);
3577 err_out_free_dev_1:
3578         free_netdev(dev);
3579         goto out;
3580 }
3581
3582 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
3583 {
3584         struct net_device *dev = pci_get_drvdata(pdev);
3585         struct rtl8169_private *tp = netdev_priv(dev);
3586
3587         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3588             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3589             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3590                 rtl8168_driver_stop(tp);
3591         }
3592
3593         cancel_delayed_work_sync(&tp->task);
3594
3595         unregister_netdev(dev);
3596
3597         rtl_release_firmware(tp);
3598
3599         if (pci_dev_run_wake(pdev))
3600                 pm_runtime_get_noresume(&pdev->dev);
3601
3602         /* restore original MAC address */
3603         rtl_rar_set(tp, dev->perm_addr);
3604
3605         rtl_disable_msi(pdev, tp);
3606         rtl8169_release_board(pdev, dev, tp->mmio_addr);
3607         pci_set_drvdata(pdev, NULL);
3608 }
3609
3610 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
3611 {
3612         struct rtl_fw *rtl_fw;
3613         const char *name;
3614         int rc = -ENOMEM;
3615
3616         name = rtl_lookup_firmware_name(tp);
3617         if (!name)
3618                 goto out_no_firmware;
3619
3620         rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
3621         if (!rtl_fw)
3622                 goto err_warn;
3623
3624         rc = request_firmware(&rtl_fw->fw, name, &tp->pci_dev->dev);
3625         if (rc < 0)
3626                 goto err_free;
3627
3628         rc = rtl_check_firmware(tp, rtl_fw);
3629         if (rc < 0)
3630                 goto err_release_firmware;
3631
3632         tp->rtl_fw = rtl_fw;
3633 out:
3634         return;
3635
3636 err_release_firmware:
3637         release_firmware(rtl_fw->fw);
3638 err_free:
3639         kfree(rtl_fw);
3640 err_warn:
3641         netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
3642                    name, rc);
3643 out_no_firmware:
3644         tp->rtl_fw = NULL;
3645         goto out;
3646 }
3647
3648 static void rtl_request_firmware(struct rtl8169_private *tp)
3649 {
3650         if (IS_ERR(tp->rtl_fw))
3651                 rtl_request_uncached_firmware(tp);
3652 }
3653
3654 static int rtl8169_open(struct net_device *dev)
3655 {
3656         struct rtl8169_private *tp = netdev_priv(dev);
3657         void __iomem *ioaddr = tp->mmio_addr;
3658         struct pci_dev *pdev = tp->pci_dev;
3659         int retval = -ENOMEM;
3660
3661         pm_runtime_get_sync(&pdev->dev);
3662
3663         /*
3664          * Rx and Tx desscriptors needs 256 bytes alignment.
3665          * dma_alloc_coherent provides more.
3666          */
3667         tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
3668                                              &tp->TxPhyAddr, GFP_KERNEL);
3669         if (!tp->TxDescArray)
3670                 goto err_pm_runtime_put;
3671
3672         tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
3673                                              &tp->RxPhyAddr, GFP_KERNEL);
3674         if (!tp->RxDescArray)
3675                 goto err_free_tx_0;
3676
3677         retval = rtl8169_init_ring(dev);
3678         if (retval < 0)
3679                 goto err_free_rx_1;
3680
3681         INIT_DELAYED_WORK(&tp->task, NULL);
3682
3683         smp_mb();
3684
3685         rtl_request_firmware(tp);
3686
3687         retval = request_irq(dev->irq, rtl8169_interrupt,
3688                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
3689                              dev->name, dev);
3690         if (retval < 0)
3691                 goto err_release_fw_2;
3692
3693         napi_enable(&tp->napi);
3694
3695         rtl8169_init_phy(dev, tp);
3696
3697         rtl8169_set_features(dev, dev->features);
3698
3699         rtl_pll_power_up(tp);
3700
3701         rtl_hw_start(dev);
3702
3703         tp->saved_wolopts = 0;
3704         pm_runtime_put_noidle(&pdev->dev);
3705
3706         rtl8169_check_link_status(dev, tp, ioaddr);
3707 out:
3708         return retval;
3709
3710 err_release_fw_2:
3711         rtl_release_firmware(tp);
3712         rtl8169_rx_clear(tp);
3713 err_free_rx_1:
3714         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
3715                           tp->RxPhyAddr);
3716         tp->RxDescArray = NULL;
3717 err_free_tx_0:
3718         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
3719                           tp->TxPhyAddr);
3720         tp->TxDescArray = NULL;
3721 err_pm_runtime_put:
3722         pm_runtime_put_noidle(&pdev->dev);
3723         goto out;
3724 }
3725
3726 static void rtl8169_hw_reset(struct rtl8169_private *tp)
3727 {
3728         void __iomem *ioaddr = tp->mmio_addr;
3729
3730         /* Disable interrupts */
3731         rtl8169_irq_mask_and_ack(ioaddr);
3732
3733         if (tp->mac_version == RTL_GIGA_MAC_VER_27 ||
3734             tp->mac_version == RTL_GIGA_MAC_VER_28 ||
3735             tp->mac_version == RTL_GIGA_MAC_VER_31) {
3736                 while (RTL_R8(TxPoll) & NPQ)
3737                         udelay(20);
3738
3739         }
3740
3741         /* Reset the chipset */
3742         RTL_W8(ChipCmd, CmdReset);
3743
3744         /* PCI commit */
3745         RTL_R8(ChipCmd);
3746 }
3747
3748 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
3749 {
3750         void __iomem *ioaddr = tp->mmio_addr;
3751         u32 cfg = rtl8169_rx_config;
3752
3753         cfg |= (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
3754         RTL_W32(RxConfig, cfg);
3755
3756         /* Set DMA burst size and Interframe Gap Time */
3757         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
3758                 (InterFrameGap << TxInterFrameGapShift));
3759 }
3760
3761 static void rtl_hw_start(struct net_device *dev)
3762 {
3763         struct rtl8169_private *tp = netdev_priv(dev);
3764
3765         rtl_hw_reset(tp);
3766
3767         tp->hw_start(dev);
3768
3769         netif_start_queue(dev);
3770 }
3771
3772 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
3773                                          void __iomem *ioaddr)
3774 {
3775         /*
3776          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
3777          * register to be written before TxDescAddrLow to work.
3778          * Switching from MMIO to I/O access fixes the issue as well.
3779          */
3780         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
3781         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
3782         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
3783         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
3784 }
3785
3786 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
3787 {
3788         u16 cmd;
3789
3790         cmd = RTL_R16(CPlusCmd);
3791         RTL_W16(CPlusCmd, cmd);
3792         return cmd;
3793 }
3794
3795 static void rtl_set_rx_max_size(void __iomem *ioaddr, unsigned int rx_buf_sz)
3796 {
3797         /* Low hurts. Let's disable the filtering. */
3798         RTL_W16(RxMaxSize, rx_buf_sz + 1);
3799 }
3800
3801 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
3802 {
3803         static const struct rtl_cfg2_info {
3804                 u32 mac_version;
3805                 u32 clk;
3806                 u32 val;
3807         } cfg2_info [] = {
3808                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
3809                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
3810                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
3811                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
3812         };
3813         const struct rtl_cfg2_info *p = cfg2_info;
3814         unsigned int i;
3815         u32 clk;
3816
3817         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
3818         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
3819                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
3820                         RTL_W32(0x7c, p->val);
3821                         break;
3822                 }
3823         }
3824 }
3825
3826 static void rtl_hw_start_8169(struct net_device *dev)
3827 {
3828         struct rtl8169_private *tp = netdev_priv(dev);
3829         void __iomem *ioaddr = tp->mmio_addr;
3830         struct pci_dev *pdev = tp->pci_dev;
3831
3832         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
3833                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
3834                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
3835         }
3836
3837         RTL_W8(Cfg9346, Cfg9346_Unlock);
3838         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3839             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3840             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3841             tp->mac_version == RTL_GIGA_MAC_VER_04)
3842                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3843
3844         RTL_W8(EarlyTxThres, NoEarlyTx);
3845
3846         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
3847
3848         if (tp->mac_version == RTL_GIGA_MAC_VER_01 ||
3849             tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3850             tp->mac_version == RTL_GIGA_MAC_VER_03 ||
3851             tp->mac_version == RTL_GIGA_MAC_VER_04)
3852                 rtl_set_rx_tx_config_registers(tp);
3853
3854         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
3855
3856         if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
3857             tp->mac_version == RTL_GIGA_MAC_VER_03) {
3858                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
3859                         "Bit-3 and bit-14 MUST be 1\n");
3860                 tp->cp_cmd |= (1 << 14);
3861         }
3862
3863         RTL_W16(CPlusCmd, tp->cp_cmd);
3864
3865         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
3866
3867         /*
3868          * Undocumented corner. Supposedly:
3869          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
3870          */
3871         RTL_W16(IntrMitigate, 0x0000);
3872
3873         rtl_set_rx_tx_desc_registers(tp, ioaddr);
3874
3875         if (tp->mac_version != RTL_GIGA_MAC_VER_01 &&
3876             tp->mac_version != RTL_GIGA_MAC_VER_02 &&
3877             tp->mac_version != RTL_GIGA_MAC_VER_03 &&
3878             tp->mac_version != RTL_GIGA_MAC_VER_04) {
3879                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
3880                 rtl_set_rx_tx_config_registers(tp);
3881         }
3882
3883         RTL_W8(Cfg9346, Cfg9346_Lock);
3884
3885         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
3886         RTL_R8(IntrMask);
3887
3888         RTL_W32(RxMissed, 0);
3889
3890         rtl_set_rx_mode(dev);
3891
3892         /* no early-rx interrupts */
3893         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
3894
3895         /* Enable all known interrupts by setting the interrupt mask. */
3896         RTL_W16(IntrMask, tp->intr_event);
3897 }
3898
3899 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
3900 {
3901         struct net_device *dev = pci_get_drvdata(pdev);
3902         struct rtl8169_private *tp = netdev_priv(dev);
3903         int cap = tp->pcie_cap;
3904
3905         if (cap) {
3906                 u16 ctl;
3907
3908                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
3909                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
3910                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
3911         }
3912 }
3913
3914 static void rtl_csi_access_enable(void __iomem *ioaddr, u32 bits)
3915 {
3916         u32 csi;
3917
3918         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
3919         rtl_csi_write(ioaddr, 0x070c, csi | bits);
3920 }
3921
3922 static void rtl_csi_access_enable_1(void __iomem *ioaddr)
3923 {
3924         rtl_csi_access_enable(ioaddr, 0x17000000);
3925 }
3926
3927 static void rtl_csi_access_enable_2(void __iomem *ioaddr)
3928 {
3929         rtl_csi_access_enable(ioaddr, 0x27000000);
3930 }
3931
3932 struct ephy_info {
3933         unsigned int offset;
3934         u16 mask;
3935         u16 bits;
3936 };
3937
3938 static void rtl_ephy_init(void __iomem *ioaddr, const struct ephy_info *e, int len)
3939 {
3940         u16 w;
3941
3942         while (len-- > 0) {
3943                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
3944                 rtl_ephy_write(ioaddr, e->offset, w);
3945                 e++;
3946         }
3947 }
3948
3949 static void rtl_disable_clock_request(struct pci_dev *pdev)
3950 {
3951         struct net_device *dev = pci_get_drvdata(pdev);
3952         struct rtl8169_private *tp = netdev_priv(dev);
3953         int cap = tp->pcie_cap;
3954
3955         if (cap) {
3956                 u16 ctl;
3957
3958                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3959                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
3960                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3961         }
3962 }
3963
3964 static void rtl_enable_clock_request(struct pci_dev *pdev)
3965 {
3966         struct net_device *dev = pci_get_drvdata(pdev);
3967         struct rtl8169_private *tp = netdev_priv(dev);
3968         int cap = tp->pcie_cap;
3969
3970         if (cap) {
3971                 u16 ctl;
3972
3973                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
3974                 ctl |= PCI_EXP_LNKCTL_CLKREQ_EN;
3975                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
3976         }
3977 }
3978
3979 #define R8168_CPCMD_QUIRK_MASK (\
3980         EnableBist | \
3981         Mac_dbgo_oe | \
3982         Force_half_dup | \
3983         Force_rxflow_en | \
3984         Force_txflow_en | \
3985         Cxpl_dbg_sel | \
3986         ASF | \
3987         PktCntrDisable | \
3988         Mac_dbgo_sel)
3989
3990 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
3991 {
3992         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
3993
3994         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
3995
3996         rtl_tx_performance_tweak(pdev,
3997                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
3998 }
3999
4000 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
4001 {
4002         rtl_hw_start_8168bb(ioaddr, pdev);
4003
4004         RTL_W8(MaxTxPacketSize, TxPacketMax);
4005
4006         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
4007 }
4008
4009 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
4010 {
4011         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
4012
4013         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4014
4015         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4016
4017         rtl_disable_clock_request(pdev);
4018
4019         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4020 }
4021
4022 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
4023 {
4024         static const struct ephy_info e_info_8168cp[] = {
4025                 { 0x01, 0,      0x0001 },
4026                 { 0x02, 0x0800, 0x1000 },
4027                 { 0x03, 0,      0x0042 },
4028                 { 0x06, 0x0080, 0x0000 },
4029                 { 0x07, 0,      0x2000 }
4030         };
4031
4032         rtl_csi_access_enable_2(ioaddr);
4033
4034         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4035
4036         __rtl_hw_start_8168cp(ioaddr, pdev);
4037 }
4038
4039 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
4040 {
4041         rtl_csi_access_enable_2(ioaddr);
4042
4043         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4044
4045         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4046
4047         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4048 }
4049
4050 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
4051 {
4052         rtl_csi_access_enable_2(ioaddr);
4053
4054         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4055
4056         /* Magic. */
4057         RTL_W8(DBG_REG, 0x20);
4058
4059         RTL_W8(MaxTxPacketSize, TxPacketMax);
4060
4061         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4062
4063         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4064 }
4065
4066 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
4067 {
4068         static const struct ephy_info e_info_8168c_1[] = {
4069                 { 0x02, 0x0800, 0x1000 },
4070                 { 0x03, 0,      0x0002 },
4071                 { 0x06, 0x0080, 0x0000 }
4072         };
4073
4074         rtl_csi_access_enable_2(ioaddr);
4075
4076         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4077
4078         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4079
4080         __rtl_hw_start_8168cp(ioaddr, pdev);
4081 }
4082
4083 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
4084 {
4085         static const struct ephy_info e_info_8168c_2[] = {
4086                 { 0x01, 0,      0x0001 },
4087                 { 0x03, 0x0400, 0x0220 }
4088         };
4089
4090         rtl_csi_access_enable_2(ioaddr);
4091
4092         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4093
4094         __rtl_hw_start_8168cp(ioaddr, pdev);
4095 }
4096
4097 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
4098 {
4099         rtl_hw_start_8168c_2(ioaddr, pdev);
4100 }
4101
4102 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
4103 {
4104         rtl_csi_access_enable_2(ioaddr);
4105
4106         __rtl_hw_start_8168cp(ioaddr, pdev);
4107 }
4108
4109 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
4110 {
4111         rtl_csi_access_enable_2(ioaddr);
4112
4113         rtl_disable_clock_request(pdev);
4114
4115         RTL_W8(MaxTxPacketSize, TxPacketMax);
4116
4117         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4118
4119         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
4120 }
4121
4122 static void rtl_hw_start_8168dp(void __iomem *ioaddr, struct pci_dev *pdev)
4123 {
4124         rtl_csi_access_enable_1(ioaddr);
4125
4126         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4127
4128         RTL_W8(MaxTxPacketSize, TxPacketMax);
4129
4130         rtl_disable_clock_request(pdev);
4131 }
4132
4133 static void rtl_hw_start_8168d_4(void __iomem *ioaddr, struct pci_dev *pdev)
4134 {
4135         static const struct ephy_info e_info_8168d_4[] = {
4136                 { 0x0b, ~0,     0x48 },
4137                 { 0x19, 0x20,   0x50 },
4138                 { 0x0c, ~0,     0x20 }
4139         };
4140         int i;
4141
4142         rtl_csi_access_enable_1(ioaddr);
4143
4144         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4145
4146         RTL_W8(MaxTxPacketSize, TxPacketMax);
4147
4148         for (i = 0; i < ARRAY_SIZE(e_info_8168d_4); i++) {
4149                 const struct ephy_info *e = e_info_8168d_4 + i;
4150                 u16 w;
4151
4152                 w = rtl_ephy_read(ioaddr, e->offset);
4153                 rtl_ephy_write(ioaddr, 0x03, (w & e->mask) | e->bits);
4154         }
4155
4156         rtl_enable_clock_request(pdev);
4157 }
4158
4159 static void rtl_hw_start_8168e(void __iomem *ioaddr, struct pci_dev *pdev)
4160 {
4161         static const struct ephy_info e_info_8168e[] = {
4162                 { 0x00, 0x0200, 0x0100 },
4163                 { 0x00, 0x0000, 0x0004 },
4164                 { 0x06, 0x0002, 0x0001 },
4165                 { 0x06, 0x0000, 0x0030 },
4166                 { 0x07, 0x0000, 0x2000 },
4167                 { 0x00, 0x0000, 0x0020 },
4168                 { 0x03, 0x5800, 0x2000 },
4169                 { 0x03, 0x0000, 0x0001 },
4170                 { 0x01, 0x0800, 0x1000 },
4171                 { 0x07, 0x0000, 0x4000 },
4172                 { 0x1e, 0x0000, 0x2000 },
4173                 { 0x19, 0xffff, 0xfe6c },
4174                 { 0x0a, 0x0000, 0x0040 }
4175         };
4176
4177         rtl_csi_access_enable_2(ioaddr);
4178
4179         rtl_ephy_init(ioaddr, e_info_8168e, ARRAY_SIZE(e_info_8168e));
4180
4181         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4182
4183         RTL_W8(MaxTxPacketSize, TxPacketMax);
4184
4185         rtl_disable_clock_request(pdev);
4186
4187         /* Reset tx FIFO pointer */
4188         RTL_W32(MISC, RTL_R32(MISC) | TXPLA_RST);
4189         RTL_W32(MISC, RTL_R32(MISC) & ~TXPLA_RST);
4190
4191         RTL_W8(Config5, RTL_R8(Config5) & ~Spi_en);
4192 }
4193
4194 static void rtl_hw_start_8168(struct net_device *dev)
4195 {
4196         struct rtl8169_private *tp = netdev_priv(dev);
4197         void __iomem *ioaddr = tp->mmio_addr;
4198         struct pci_dev *pdev = tp->pci_dev;
4199
4200         RTL_W8(Cfg9346, Cfg9346_Unlock);
4201
4202         RTL_W8(MaxTxPacketSize, TxPacketMax);
4203
4204         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4205
4206         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
4207
4208         RTL_W16(CPlusCmd, tp->cp_cmd);
4209
4210         RTL_W16(IntrMitigate, 0x5151);
4211
4212         /* Work around for RxFIFO overflow. */
4213         if (tp->mac_version == RTL_GIGA_MAC_VER_11 ||
4214             tp->mac_version == RTL_GIGA_MAC_VER_22) {
4215                 tp->intr_event |= RxFIFOOver | PCSTimeout;
4216                 tp->intr_event &= ~RxOverflow;
4217         }
4218
4219         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4220
4221         rtl_set_rx_mode(dev);
4222
4223         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
4224                 (InterFrameGap << TxInterFrameGapShift));
4225
4226         RTL_R8(IntrMask);
4227
4228         switch (tp->mac_version) {
4229         case RTL_GIGA_MAC_VER_11:
4230                 rtl_hw_start_8168bb(ioaddr, pdev);
4231                 break;
4232
4233         case RTL_GIGA_MAC_VER_12:
4234         case RTL_GIGA_MAC_VER_17:
4235                 rtl_hw_start_8168bef(ioaddr, pdev);
4236                 break;
4237
4238         case RTL_GIGA_MAC_VER_18:
4239                 rtl_hw_start_8168cp_1(ioaddr, pdev);
4240                 break;
4241
4242         case RTL_GIGA_MAC_VER_19:
4243                 rtl_hw_start_8168c_1(ioaddr, pdev);
4244                 break;
4245
4246         case RTL_GIGA_MAC_VER_20:
4247                 rtl_hw_start_8168c_2(ioaddr, pdev);
4248                 break;
4249
4250         case RTL_GIGA_MAC_VER_21:
4251                 rtl_hw_start_8168c_3(ioaddr, pdev);
4252                 break;
4253
4254         case RTL_GIGA_MAC_VER_22:
4255                 rtl_hw_start_8168c_4(ioaddr, pdev);
4256                 break;
4257
4258         case RTL_GIGA_MAC_VER_23:
4259                 rtl_hw_start_8168cp_2(ioaddr, pdev);
4260                 break;
4261
4262         case RTL_GIGA_MAC_VER_24:
4263                 rtl_hw_start_8168cp_3(ioaddr, pdev);
4264                 break;
4265
4266         case RTL_GIGA_MAC_VER_25:
4267         case RTL_GIGA_MAC_VER_26:
4268         case RTL_GIGA_MAC_VER_27:
4269                 rtl_hw_start_8168d(ioaddr, pdev);
4270                 break;
4271
4272         case RTL_GIGA_MAC_VER_28:
4273                 rtl_hw_start_8168d_4(ioaddr, pdev);
4274                 break;
4275
4276         case RTL_GIGA_MAC_VER_31:
4277                 rtl_hw_start_8168dp(ioaddr, pdev);
4278                 break;
4279
4280         case RTL_GIGA_MAC_VER_32:
4281         case RTL_GIGA_MAC_VER_33:
4282                 rtl_hw_start_8168e(ioaddr, pdev);
4283                 break;
4284
4285         default:
4286                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
4287                         dev->name, tp->mac_version);
4288                 break;
4289         }
4290
4291         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4292
4293         RTL_W8(Cfg9346, Cfg9346_Lock);
4294
4295         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
4296
4297         RTL_W16(IntrMask, tp->intr_event);
4298 }
4299
4300 #define R810X_CPCMD_QUIRK_MASK (\
4301         EnableBist | \
4302         Mac_dbgo_oe | \
4303         Force_half_dup | \
4304         Force_rxflow_en | \
4305         Force_txflow_en | \
4306         Cxpl_dbg_sel | \
4307         ASF | \
4308         PktCntrDisable | \
4309         Mac_dbgo_sel)
4310
4311 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4312 {
4313         static const struct ephy_info e_info_8102e_1[] = {
4314                 { 0x01, 0, 0x6e65 },
4315                 { 0x02, 0, 0x091f },
4316                 { 0x03, 0, 0xc2f9 },
4317                 { 0x06, 0, 0xafb5 },
4318                 { 0x07, 0, 0x0e00 },
4319                 { 0x19, 0, 0xec80 },
4320                 { 0x01, 0, 0x2e65 },
4321                 { 0x01, 0, 0x6e65 }
4322         };
4323         u8 cfg1;
4324
4325         rtl_csi_access_enable_2(ioaddr);
4326
4327         RTL_W8(DBG_REG, FIX_NAK_1);
4328
4329         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4330
4331         RTL_W8(Config1,
4332                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
4333         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4334
4335         cfg1 = RTL_R8(Config1);
4336         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
4337                 RTL_W8(Config1, cfg1 & ~LEDS0);
4338
4339         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
4340 }
4341
4342 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4343 {
4344         rtl_csi_access_enable_2(ioaddr);
4345
4346         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
4347
4348         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
4349         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
4350 }
4351
4352 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
4353 {
4354         rtl_hw_start_8102e_2(ioaddr, pdev);
4355
4356         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
4357 }
4358
4359 static void rtl_hw_start_8105e_1(void __iomem *ioaddr, struct pci_dev *pdev)
4360 {
4361         static const struct ephy_info e_info_8105e_1[] = {
4362                 { 0x07, 0, 0x4000 },
4363                 { 0x19, 0, 0x0200 },
4364                 { 0x19, 0, 0x0020 },
4365                 { 0x1e, 0, 0x2000 },
4366                 { 0x03, 0, 0x0001 },
4367                 { 0x19, 0, 0x0100 },
4368                 { 0x19, 0, 0x0004 },
4369                 { 0x0a, 0, 0x0020 }
4370         };
4371
4372         /* Force LAN exit from ASPM if Rx/Tx are not idle */
4373         RTL_W32(FuncEvent, RTL_R32(FuncEvent) | 0x002800);
4374
4375         /* Disable Early Tally Counter */
4376         RTL_W32(FuncEvent, RTL_R32(FuncEvent) & ~0x010000);
4377
4378         RTL_W8(MCU, RTL_R8(MCU) | EN_NDP | EN_OOB_RESET);
4379         RTL_W8(DLLPR, RTL_R8(DLLPR) | PM_SWITCH);
4380
4381         rtl_ephy_init(ioaddr, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
4382 }
4383
4384 static void rtl_hw_start_8105e_2(void __iomem *ioaddr, struct pci_dev *pdev)
4385 {
4386         rtl_hw_start_8105e_1(ioaddr, pdev);
4387         rtl_ephy_write(ioaddr, 0x1e, rtl_ephy_read(ioaddr, 0x1e) | 0x8000);
4388 }
4389
4390 static void rtl_hw_start_8101(struct net_device *dev)
4391 {
4392         struct rtl8169_private *tp = netdev_priv(dev);
4393         void __iomem *ioaddr = tp->mmio_addr;
4394         struct pci_dev *pdev = tp->pci_dev;
4395
4396         if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
4397             tp->mac_version == RTL_GIGA_MAC_VER_16) {
4398                 int cap = tp->pcie_cap;
4399
4400                 if (cap) {
4401                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
4402                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
4403                 }
4404         }
4405
4406         RTL_W8(Cfg9346, Cfg9346_Unlock);
4407
4408         switch (tp->mac_version) {
4409         case RTL_GIGA_MAC_VER_07:
4410                 rtl_hw_start_8102e_1(ioaddr, pdev);
4411                 break;
4412
4413         case RTL_GIGA_MAC_VER_08:
4414                 rtl_hw_start_8102e_3(ioaddr, pdev);
4415                 break;
4416
4417         case RTL_GIGA_MAC_VER_09:
4418                 rtl_hw_start_8102e_2(ioaddr, pdev);
4419                 break;
4420
4421         case RTL_GIGA_MAC_VER_29:
4422                 rtl_hw_start_8105e_1(ioaddr, pdev);
4423                 break;
4424         case RTL_GIGA_MAC_VER_30:
4425                 rtl_hw_start_8105e_2(ioaddr, pdev);
4426                 break;
4427         }
4428
4429         RTL_W8(Cfg9346, Cfg9346_Lock);
4430
4431         RTL_W8(MaxTxPacketSize, TxPacketMax);
4432
4433         rtl_set_rx_max_size(ioaddr, rx_buf_sz);
4434
4435         tp->cp_cmd &= ~R810X_CPCMD_QUIRK_MASK;
4436         RTL_W16(CPlusCmd, tp->cp_cmd);
4437
4438         RTL_W16(IntrMitigate, 0x0000);
4439
4440         rtl_set_rx_tx_desc_registers(tp, ioaddr);
4441
4442         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
4443         rtl_set_rx_tx_config_registers(tp);
4444
4445         RTL_R8(IntrMask);
4446
4447         rtl_set_rx_mode(dev);
4448
4449         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
4450
4451         RTL_W16(IntrMask, tp->intr_event);
4452 }
4453
4454 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
4455 {
4456         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
4457                 return -EINVAL;
4458
4459         dev->mtu = new_mtu;
4460         netdev_update_features(dev);
4461
4462         return 0;
4463 }
4464
4465 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
4466 {
4467         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
4468         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
4469 }
4470
4471 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
4472                                      void **data_buff, struct RxDesc *desc)
4473 {
4474         dma_unmap_single(&tp->pci_dev->dev, le64_to_cpu(desc->addr), rx_buf_sz,
4475                          DMA_FROM_DEVICE);
4476
4477         kfree(*data_buff);
4478         *data_buff = NULL;
4479         rtl8169_make_unusable_by_asic(desc);
4480 }
4481
4482 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
4483 {
4484         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
4485
4486         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
4487 }
4488
4489 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
4490                                        u32 rx_buf_sz)
4491 {
4492         desc->addr = cpu_to_le64(mapping);
4493         wmb();
4494         rtl8169_mark_to_asic(desc, rx_buf_sz);
4495 }
4496
4497 static inline void *rtl8169_align(void *data)
4498 {
4499         return (void *)ALIGN((long)data, 16);
4500 }
4501
4502 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
4503                                              struct RxDesc *desc)
4504 {
4505         void *data;
4506         dma_addr_t mapping;
4507         struct device *d = &tp->pci_dev->dev;
4508         struct net_device *dev = tp->dev;
4509         int node = dev->dev.parent ? dev_to_node(dev->dev.parent) : -1;
4510
4511         data = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
4512         if (!data)
4513                 return NULL;
4514
4515         if (rtl8169_align(data) != data) {
4516                 kfree(data);
4517                 data = kmalloc_node(rx_buf_sz + 15, GFP_KERNEL, node);
4518                 if (!data)
4519                         return NULL;
4520         }
4521
4522         mapping = dma_map_single(d, rtl8169_align(data), rx_buf_sz,
4523                                  DMA_FROM_DEVICE);
4524         if (unlikely(dma_mapping_error(d, mapping))) {
4525                 if (net_ratelimit())
4526                         netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
4527                 goto err_out;
4528         }
4529
4530         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
4531         return data;
4532
4533 err_out:
4534         kfree(data);
4535         return NULL;
4536 }
4537
4538 static void rtl8169_rx_clear(struct rtl8169_private *tp)
4539 {
4540         unsigned int i;
4541
4542         for (i = 0; i < NUM_RX_DESC; i++) {
4543                 if (tp->Rx_databuff[i]) {
4544                         rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
4545                                             tp->RxDescArray + i);
4546                 }
4547         }
4548 }
4549
4550 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
4551 {
4552         desc->opts1 |= cpu_to_le32(RingEnd);
4553 }
4554
4555 static int rtl8169_rx_fill(struct rtl8169_private *tp)
4556 {
4557         unsigned int i;
4558
4559         for (i = 0; i < NUM_RX_DESC; i++) {
4560                 void *data;
4561
4562                 if (tp->Rx_databuff[i])
4563                         continue;
4564
4565                 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
4566                 if (!data) {
4567                         rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
4568                         goto err_out;
4569                 }
4570                 tp->Rx_databuff[i] = data;
4571         }
4572
4573         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
4574         return 0;
4575
4576 err_out:
4577         rtl8169_rx_clear(tp);
4578         return -ENOMEM;
4579 }
4580
4581 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4582 {
4583         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
4584 }
4585
4586 static int rtl8169_init_ring(struct net_device *dev)
4587 {
4588         struct rtl8169_private *tp = netdev_priv(dev);
4589
4590         rtl8169_init_ring_indexes(tp);
4591
4592         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
4593         memset(tp->Rx_databuff, 0x0, NUM_RX_DESC * sizeof(void *));
4594
4595         return rtl8169_rx_fill(tp);
4596 }
4597
4598 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
4599                                  struct TxDesc *desc)
4600 {
4601         unsigned int len = tx_skb->len;
4602
4603         dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
4604
4605         desc->opts1 = 0x00;
4606         desc->opts2 = 0x00;
4607         desc->addr = 0x00;
4608         tx_skb->len = 0;
4609 }
4610
4611 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
4612                                    unsigned int n)
4613 {
4614         unsigned int i;
4615
4616         for (i = 0; i < n; i++) {
4617                 unsigned int entry = (start + i) % NUM_TX_DESC;
4618                 struct ring_info *tx_skb = tp->tx_skb + entry;
4619                 unsigned int len = tx_skb->len;
4620
4621                 if (len) {
4622                         struct sk_buff *skb = tx_skb->skb;
4623
4624                         rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4625                                              tp->TxDescArray + entry);
4626                         if (skb) {
4627                                 tp->dev->stats.tx_dropped++;
4628                                 dev_kfree_skb(skb);
4629                                 tx_skb->skb = NULL;
4630                         }
4631                 }
4632         }
4633 }
4634
4635 static void rtl8169_tx_clear(struct rtl8169_private *tp)
4636 {
4637         rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
4638         tp->cur_tx = tp->dirty_tx = 0;
4639 }
4640
4641 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
4642 {
4643         struct rtl8169_private *tp = netdev_priv(dev);
4644
4645         PREPARE_DELAYED_WORK(&tp->task, task);
4646         schedule_delayed_work(&tp->task, 4);
4647 }
4648
4649 static void rtl8169_wait_for_quiescence(struct net_device *dev)
4650 {
4651         struct rtl8169_private *tp = netdev_priv(dev);
4652         void __iomem *ioaddr = tp->mmio_addr;
4653
4654         synchronize_irq(dev->irq);
4655
4656         /* Wait for any pending NAPI task to complete */
4657         napi_disable(&tp->napi);
4658
4659         rtl8169_irq_mask_and_ack(ioaddr);
4660
4661         tp->intr_mask = 0xffff;
4662         RTL_W16(IntrMask, tp->intr_event);
4663         napi_enable(&tp->napi);
4664 }
4665
4666 static void rtl8169_reinit_task(struct work_struct *work)
4667 {
4668         struct rtl8169_private *tp =
4669                 container_of(work, struct rtl8169_private, task.work);
4670         struct net_device *dev = tp->dev;
4671         int ret;
4672
4673         rtnl_lock();
4674
4675         if (!netif_running(dev))
4676                 goto out_unlock;
4677
4678         rtl8169_wait_for_quiescence(dev);
4679         rtl8169_close(dev);
4680
4681         ret = rtl8169_open(dev);
4682         if (unlikely(ret < 0)) {
4683                 if (net_ratelimit())
4684                         netif_err(tp, drv, dev,
4685                                   "reinit failure (status = %d). Rescheduling\n",
4686                                   ret);
4687                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
4688         }
4689
4690 out_unlock:
4691         rtnl_unlock();
4692 }
4693
4694 static void rtl8169_reset_task(struct work_struct *work)
4695 {
4696         struct rtl8169_private *tp =
4697                 container_of(work, struct rtl8169_private, task.work);
4698         struct net_device *dev = tp->dev;
4699         int i;
4700
4701         rtnl_lock();
4702
4703         if (!netif_running(dev))
4704                 goto out_unlock;
4705
4706         rtl8169_wait_for_quiescence(dev);
4707
4708         for (i = 0; i < NUM_RX_DESC; i++)
4709                 rtl8169_mark_to_asic(tp->RxDescArray + i, rx_buf_sz);
4710
4711         rtl8169_tx_clear(tp);
4712
4713         rtl8169_init_ring_indexes(tp);
4714         rtl_hw_start(dev);
4715         netif_wake_queue(dev);
4716         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
4717
4718 out_unlock:
4719         rtnl_unlock();
4720 }
4721
4722 static void rtl8169_tx_timeout(struct net_device *dev)
4723 {
4724         struct rtl8169_private *tp = netdev_priv(dev);
4725
4726         rtl8169_hw_reset(tp);
4727
4728         /* Let's wait a bit while any (async) irq lands on */
4729         rtl8169_schedule_work(dev, rtl8169_reset_task);
4730 }
4731
4732 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
4733                               u32 *opts)
4734 {
4735         struct skb_shared_info *info = skb_shinfo(skb);
4736         unsigned int cur_frag, entry;
4737         struct TxDesc * uninitialized_var(txd);
4738         struct device *d = &tp->pci_dev->dev;
4739
4740         entry = tp->cur_tx;
4741         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
4742                 skb_frag_t *frag = info->frags + cur_frag;
4743                 dma_addr_t mapping;
4744                 u32 status, len;
4745                 void *addr;
4746
4747                 entry = (entry + 1) % NUM_TX_DESC;
4748
4749                 txd = tp->TxDescArray + entry;
4750                 len = frag->size;
4751                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
4752                 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
4753                 if (unlikely(dma_mapping_error(d, mapping))) {
4754                         if (net_ratelimit())
4755                                 netif_err(tp, drv, tp->dev,
4756                                           "Failed to map TX fragments DMA!\n");
4757                         goto err_out;
4758                 }
4759
4760                 /* Anti gcc 2.95.3 bugware (sic) */
4761                 status = opts[0] | len |
4762                         (RingEnd * !((entry + 1) % NUM_TX_DESC));
4763
4764                 txd->opts1 = cpu_to_le32(status);
4765                 txd->opts2 = cpu_to_le32(opts[1]);
4766                 txd->addr = cpu_to_le64(mapping);
4767
4768                 tp->tx_skb[entry].len = len;
4769         }
4770
4771         if (cur_frag) {
4772                 tp->tx_skb[entry].skb = skb;
4773                 txd->opts1 |= cpu_to_le32(LastFrag);
4774         }
4775
4776         return cur_frag;
4777
4778 err_out:
4779         rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
4780         return -EIO;
4781 }
4782
4783 static inline void rtl8169_tso_csum(struct rtl8169_private *tp,
4784                                     struct sk_buff *skb, u32 *opts)
4785 {
4786         const struct rtl_tx_desc_info *info = tx_desc_info + tp->txd_version;
4787         u32 mss = skb_shinfo(skb)->gso_size;
4788         int offset = info->opts_offset;
4789
4790         if (mss) {
4791                 opts[0] |= TD_LSO;
4792                 opts[offset] |= min(mss, TD_MSS_MAX) << info->mss_shift;
4793         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
4794                 const struct iphdr *ip = ip_hdr(skb);
4795
4796                 if (ip->protocol == IPPROTO_TCP)
4797                         opts[offset] |= info->checksum.tcp;
4798                 else if (ip->protocol == IPPROTO_UDP)
4799                         opts[offset] |= info->checksum.udp;
4800                 else
4801                         WARN_ON_ONCE(1);
4802         }
4803 }
4804
4805 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
4806                                       struct net_device *dev)
4807 {
4808         struct rtl8169_private *tp = netdev_priv(dev);
4809         unsigned int entry = tp->cur_tx % NUM_TX_DESC;
4810         struct TxDesc *txd = tp->TxDescArray + entry;
4811         void __iomem *ioaddr = tp->mmio_addr;
4812         struct device *d = &tp->pci_dev->dev;
4813         dma_addr_t mapping;
4814         u32 status, len;
4815         u32 opts[2];
4816         int frags;
4817
4818         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
4819                 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
4820                 goto err_stop_0;
4821         }
4822
4823         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
4824                 goto err_stop_0;
4825
4826         len = skb_headlen(skb);
4827         mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
4828         if (unlikely(dma_mapping_error(d, mapping))) {
4829                 if (net_ratelimit())
4830                         netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
4831                 goto err_dma_0;
4832         }
4833
4834         tp->tx_skb[entry].len = len;
4835         txd->addr = cpu_to_le64(mapping);
4836
4837         opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
4838         opts[0] = DescOwn;
4839
4840         rtl8169_tso_csum(tp, skb, opts);
4841
4842         frags = rtl8169_xmit_frags(tp, skb, opts);
4843         if (frags < 0)
4844                 goto err_dma_1;
4845         else if (frags)
4846                 opts[0] |= FirstFrag;
4847         else {
4848                 opts[0] |= FirstFrag | LastFrag;
4849                 tp->tx_skb[entry].skb = skb;
4850         }
4851
4852         txd->opts2 = cpu_to_le32(opts[1]);
4853
4854         wmb();
4855
4856         /* Anti gcc 2.95.3 bugware (sic) */
4857         status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
4858         txd->opts1 = cpu_to_le32(status);
4859
4860         tp->cur_tx += frags + 1;
4861
4862         wmb();
4863
4864         RTL_W8(TxPoll, NPQ);
4865
4866         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
4867                 netif_stop_queue(dev);
4868                 smp_rmb();
4869                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
4870                         netif_wake_queue(dev);
4871         }
4872
4873         return NETDEV_TX_OK;
4874
4875 err_dma_1:
4876         rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
4877 err_dma_0:
4878         dev_kfree_skb(skb);
4879         dev->stats.tx_dropped++;
4880         return NETDEV_TX_OK;
4881
4882 err_stop_0:
4883         netif_stop_queue(dev);
4884         dev->stats.tx_dropped++;
4885         return NETDEV_TX_BUSY;
4886 }
4887
4888 static void rtl8169_pcierr_interrupt(struct net_device *dev)
4889 {
4890         struct rtl8169_private *tp = netdev_priv(dev);
4891         struct pci_dev *pdev = tp->pci_dev;
4892         u16 pci_status, pci_cmd;
4893
4894         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
4895         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
4896
4897         netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
4898                   pci_cmd, pci_status);
4899
4900         /*
4901          * The recovery sequence below admits a very elaborated explanation:
4902          * - it seems to work;
4903          * - I did not see what else could be done;
4904          * - it makes iop3xx happy.
4905          *
4906          * Feel free to adjust to your needs.
4907          */
4908         if (pdev->broken_parity_status)
4909                 pci_cmd &= ~PCI_COMMAND_PARITY;
4910         else
4911                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
4912
4913         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
4914
4915         pci_write_config_word(pdev, PCI_STATUS,
4916                 pci_status & (PCI_STATUS_DETECTED_PARITY |
4917                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
4918                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
4919
4920         /* The infamous DAC f*ckup only happens at boot time */
4921         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
4922                 void __iomem *ioaddr = tp->mmio_addr;
4923
4924                 netif_info(tp, intr, dev, "disabling PCI DAC\n");
4925                 tp->cp_cmd &= ~PCIDAC;
4926                 RTL_W16(CPlusCmd, tp->cp_cmd);
4927                 dev->features &= ~NETIF_F_HIGHDMA;
4928         }
4929
4930         rtl8169_hw_reset(tp);
4931
4932         rtl8169_schedule_work(dev, rtl8169_reinit_task);
4933 }
4934
4935 static void rtl8169_tx_interrupt(struct net_device *dev,
4936                                  struct rtl8169_private *tp,
4937                                  void __iomem *ioaddr)
4938 {
4939         unsigned int dirty_tx, tx_left;
4940
4941         dirty_tx = tp->dirty_tx;
4942         smp_rmb();
4943         tx_left = tp->cur_tx - dirty_tx;
4944
4945         while (tx_left > 0) {
4946                 unsigned int entry = dirty_tx % NUM_TX_DESC;
4947                 struct ring_info *tx_skb = tp->tx_skb + entry;
4948                 u32 status;
4949
4950                 rmb();
4951                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
4952                 if (status & DescOwn)
4953                         break;
4954
4955                 rtl8169_unmap_tx_skb(&tp->pci_dev->dev, tx_skb,
4956                                      tp->TxDescArray + entry);
4957                 if (status & LastFrag) {
4958                         dev->stats.tx_packets++;
4959                         dev->stats.tx_bytes += tx_skb->skb->len;
4960                         dev_kfree_skb(tx_skb->skb);
4961                         tx_skb->skb = NULL;
4962                 }
4963                 dirty_tx++;
4964                 tx_left--;
4965         }
4966
4967         if (tp->dirty_tx != dirty_tx) {
4968                 tp->dirty_tx = dirty_tx;
4969                 smp_wmb();
4970                 if (netif_queue_stopped(dev) &&
4971                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
4972                         netif_wake_queue(dev);
4973                 }
4974                 /*
4975                  * 8168 hack: TxPoll requests are lost when the Tx packets are
4976                  * too close. Let's kick an extra TxPoll request when a burst
4977                  * of start_xmit activity is detected (if it is not detected,
4978                  * it is slow enough). -- FR
4979                  */
4980                 smp_rmb();
4981                 if (tp->cur_tx != dirty_tx)
4982                         RTL_W8(TxPoll, NPQ);
4983         }
4984 }
4985
4986 static inline int rtl8169_fragmented_frame(u32 status)
4987 {
4988         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
4989 }
4990
4991 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
4992 {
4993         u32 status = opts1 & RxProtoMask;
4994
4995         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
4996             ((status == RxProtoUDP) && !(opts1 & UDPFail)))
4997                 skb->ip_summed = CHECKSUM_UNNECESSARY;
4998         else
4999                 skb_checksum_none_assert(skb);
5000 }
5001
5002 static struct sk_buff *rtl8169_try_rx_copy(void *data,
5003                                            struct rtl8169_private *tp,
5004                                            int pkt_size,
5005                                            dma_addr_t addr)
5006 {
5007         struct sk_buff *skb;
5008         struct device *d = &tp->pci_dev->dev;
5009
5010         data = rtl8169_align(data);
5011         dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
5012         prefetch(data);
5013         skb = netdev_alloc_skb_ip_align(tp->dev, pkt_size);
5014         if (skb)
5015                 memcpy(skb->data, data, pkt_size);
5016         dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
5017
5018         return skb;
5019 }
5020
5021 static int rtl8169_rx_interrupt(struct net_device *dev,
5022                                 struct rtl8169_private *tp,
5023                                 void __iomem *ioaddr, u32 budget)
5024 {
5025         unsigned int cur_rx, rx_left;
5026         unsigned int count;
5027
5028         cur_rx = tp->cur_rx;
5029         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
5030         rx_left = min(rx_left, budget);
5031
5032         for (; rx_left > 0; rx_left--, cur_rx++) {
5033                 unsigned int entry = cur_rx % NUM_RX_DESC;
5034                 struct RxDesc *desc = tp->RxDescArray + entry;
5035                 u32 status;
5036
5037                 rmb();
5038                 status = le32_to_cpu(desc->opts1);
5039
5040                 if (status & DescOwn)
5041                         break;
5042                 if (unlikely(status & RxRES)) {
5043                         netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
5044                                    status);
5045                         dev->stats.rx_errors++;
5046                         if (status & (RxRWT | RxRUNT))
5047                                 dev->stats.rx_length_errors++;
5048                         if (status & RxCRC)
5049                                 dev->stats.rx_crc_errors++;
5050                         if (status & RxFOVF) {
5051                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
5052                                 dev->stats.rx_fifo_errors++;
5053                         }
5054                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5055                 } else {
5056                         struct sk_buff *skb;
5057                         dma_addr_t addr = le64_to_cpu(desc->addr);
5058                         int pkt_size = (status & 0x00001FFF) - 4;
5059
5060                         /*
5061                          * The driver does not support incoming fragmented
5062                          * frames. They are seen as a symptom of over-mtu
5063                          * sized frames.
5064                          */
5065                         if (unlikely(rtl8169_fragmented_frame(status))) {
5066                                 dev->stats.rx_dropped++;
5067                                 dev->stats.rx_length_errors++;
5068                                 rtl8169_mark_to_asic(desc, rx_buf_sz);
5069                                 continue;
5070                         }
5071
5072                         skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
5073                                                   tp, pkt_size, addr);
5074                         rtl8169_mark_to_asic(desc, rx_buf_sz);
5075                         if (!skb) {
5076                                 dev->stats.rx_dropped++;
5077                                 continue;
5078                         }
5079
5080                         rtl8169_rx_csum(skb, status);
5081                         skb_put(skb, pkt_size);
5082                         skb->protocol = eth_type_trans(skb, dev);
5083
5084                         rtl8169_rx_vlan_tag(desc, skb);
5085
5086                         napi_gro_receive(&tp->napi, skb);
5087
5088                         dev->stats.rx_bytes += pkt_size;
5089                         dev->stats.rx_packets++;
5090                 }
5091
5092                 /* Work around for AMD plateform. */
5093                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
5094                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
5095                         desc->opts2 = 0;
5096                         cur_rx++;
5097                 }
5098         }
5099
5100         count = cur_rx - tp->cur_rx;
5101         tp->cur_rx = cur_rx;
5102
5103         tp->dirty_rx += count;
5104
5105         return count;
5106 }
5107
5108 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
5109 {
5110         struct net_device *dev = dev_instance;
5111         struct rtl8169_private *tp = netdev_priv(dev);
5112         void __iomem *ioaddr = tp->mmio_addr;
5113         int handled = 0;
5114         int status;
5115
5116         /* loop handling interrupts until we have no new ones or
5117          * we hit a invalid/hotplug case.
5118          */
5119         status = RTL_R16(IntrStatus);
5120         while (status && status != 0xffff) {
5121                 handled = 1;
5122
5123                 /* Handle all of the error cases first. These will reset
5124                  * the chip, so just exit the loop.
5125                  */
5126                 if (unlikely(!netif_running(dev))) {
5127                         rtl8169_asic_down(ioaddr);
5128                         break;
5129                 }
5130
5131                 if (unlikely(status & RxFIFOOver)) {
5132                         switch (tp->mac_version) {
5133                         /* Work around for rx fifo overflow */
5134                         case RTL_GIGA_MAC_VER_11:
5135                         case RTL_GIGA_MAC_VER_22:
5136                         case RTL_GIGA_MAC_VER_26:
5137                                 netif_stop_queue(dev);
5138                                 rtl8169_tx_timeout(dev);
5139                                 goto done;
5140                         /* Testers needed. */
5141                         case RTL_GIGA_MAC_VER_17:
5142                         case RTL_GIGA_MAC_VER_19:
5143                         case RTL_GIGA_MAC_VER_20:
5144                         case RTL_GIGA_MAC_VER_21:
5145                         case RTL_GIGA_MAC_VER_23:
5146                         case RTL_GIGA_MAC_VER_24:
5147                         case RTL_GIGA_MAC_VER_27:
5148                         case RTL_GIGA_MAC_VER_28:
5149                         case RTL_GIGA_MAC_VER_31:
5150                         /* Experimental science. Pktgen proof. */
5151                         case RTL_GIGA_MAC_VER_12:
5152                         case RTL_GIGA_MAC_VER_25:
5153                                 if (status == RxFIFOOver)
5154                                         goto done;
5155                                 break;
5156                         default:
5157                                 break;
5158                         }
5159                 }
5160
5161                 if (unlikely(status & SYSErr)) {
5162                         rtl8169_pcierr_interrupt(dev);
5163                         break;
5164                 }
5165
5166                 if (status & LinkChg)
5167                         __rtl8169_check_link_status(dev, tp, ioaddr, true);
5168
5169                 /* We need to see the lastest version of tp->intr_mask to
5170                  * avoid ignoring an MSI interrupt and having to wait for
5171                  * another event which may never come.
5172                  */
5173                 smp_rmb();
5174                 if (status & tp->intr_mask & tp->napi_event) {
5175                         RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
5176                         tp->intr_mask = ~tp->napi_event;
5177
5178                         if (likely(napi_schedule_prep(&tp->napi)))
5179                                 __napi_schedule(&tp->napi);
5180                         else
5181                                 netif_info(tp, intr, dev,
5182                                            "interrupt %04x in poll\n", status);
5183                 }
5184
5185                 /* We only get a new MSI interrupt when all active irq
5186                  * sources on the chip have been acknowledged. So, ack
5187                  * everything we've seen and check if new sources have become
5188                  * active to avoid blocking all interrupts from the chip.
5189                  */
5190                 RTL_W16(IntrStatus,
5191                         (status & RxFIFOOver) ? (status | RxOverflow) : status);
5192                 status = RTL_R16(IntrStatus);
5193         }
5194 done:
5195         return IRQ_RETVAL(handled);
5196 }
5197
5198 static int rtl8169_poll(struct napi_struct *napi, int budget)
5199 {
5200         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
5201         struct net_device *dev = tp->dev;
5202         void __iomem *ioaddr = tp->mmio_addr;
5203         int work_done;
5204
5205         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
5206         rtl8169_tx_interrupt(dev, tp, ioaddr);
5207
5208         if (work_done < budget) {
5209                 napi_complete(napi);
5210
5211                 /* We need for force the visibility of tp->intr_mask
5212                  * for other CPUs, as we can loose an MSI interrupt
5213                  * and potentially wait for a retransmit timeout if we don't.
5214                  * The posted write to IntrMask is safe, as it will
5215                  * eventually make it to the chip and we won't loose anything
5216                  * until it does.
5217                  */
5218                 tp->intr_mask = 0xffff;
5219                 wmb();
5220                 RTL_W16(IntrMask, tp->intr_event);
5221         }
5222
5223         return work_done;
5224 }
5225
5226 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
5227 {
5228         struct rtl8169_private *tp = netdev_priv(dev);
5229
5230         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
5231                 return;
5232
5233         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
5234         RTL_W32(RxMissed, 0);
5235 }
5236
5237 static void rtl8169_down(struct net_device *dev)
5238 {
5239         struct rtl8169_private *tp = netdev_priv(dev);
5240         void __iomem *ioaddr = tp->mmio_addr;
5241
5242         del_timer_sync(&tp->timer);
5243
5244         netif_stop_queue(dev);
5245
5246         napi_disable(&tp->napi);
5247
5248         spin_lock_irq(&tp->lock);
5249
5250         rtl8169_asic_down(ioaddr);
5251         /*
5252          * At this point device interrupts can not be enabled in any function,
5253          * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task,
5254          * rtl8169_reinit_task) and napi is disabled (rtl8169_poll).
5255          */
5256         rtl8169_rx_missed(dev, ioaddr);
5257
5258         spin_unlock_irq(&tp->lock);
5259
5260         synchronize_irq(dev->irq);
5261
5262         /* Give a racing hard_start_xmit a few cycles to complete. */
5263         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
5264
5265         rtl8169_tx_clear(tp);
5266
5267         rtl8169_rx_clear(tp);
5268
5269         rtl_pll_power_down(tp);
5270 }
5271
5272 static int rtl8169_close(struct net_device *dev)
5273 {
5274         struct rtl8169_private *tp = netdev_priv(dev);
5275         struct pci_dev *pdev = tp->pci_dev;
5276
5277         pm_runtime_get_sync(&pdev->dev);
5278
5279         /* Update counters before going down */
5280         rtl8169_update_counters(dev);
5281
5282         rtl8169_down(dev);
5283
5284         free_irq(dev->irq, dev);
5285
5286         dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
5287                           tp->RxPhyAddr);
5288         dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
5289                           tp->TxPhyAddr);
5290         tp->TxDescArray = NULL;
5291         tp->RxDescArray = NULL;
5292
5293         pm_runtime_put_sync(&pdev->dev);
5294
5295         return 0;
5296 }
5297
5298 static void rtl_set_rx_mode(struct net_device *dev)
5299 {
5300         struct rtl8169_private *tp = netdev_priv(dev);
5301         void __iomem *ioaddr = tp->mmio_addr;
5302         unsigned long flags;
5303         u32 mc_filter[2];       /* Multicast hash filter */
5304         int rx_mode;
5305         u32 tmp = 0;
5306
5307         if (dev->flags & IFF_PROMISC) {
5308                 /* Unconditionally log net taps. */
5309                 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
5310                 rx_mode =
5311                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
5312                     AcceptAllPhys;
5313                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5314         } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
5315                    (dev->flags & IFF_ALLMULTI)) {
5316                 /* Too many to filter perfectly -- accept all multicasts. */
5317                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
5318                 mc_filter[1] = mc_filter[0] = 0xffffffff;
5319         } else {
5320                 struct netdev_hw_addr *ha;
5321
5322                 rx_mode = AcceptBroadcast | AcceptMyPhys;
5323                 mc_filter[1] = mc_filter[0] = 0;
5324                 netdev_for_each_mc_addr(ha, dev) {
5325                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
5326                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
5327                         rx_mode |= AcceptMulticast;
5328                 }
5329         }
5330
5331         spin_lock_irqsave(&tp->lock, flags);
5332
5333         tmp = rtl8169_rx_config | rx_mode |
5334               (RTL_R32(RxConfig) & RTL_RX_CONFIG_MASK);
5335
5336         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
5337                 u32 data = mc_filter[0];
5338
5339                 mc_filter[0] = swab32(mc_filter[1]);
5340                 mc_filter[1] = swab32(data);
5341         }
5342
5343         RTL_W32(MAR0 + 4, mc_filter[1]);
5344         RTL_W32(MAR0 + 0, mc_filter[0]);
5345
5346         RTL_W32(RxConfig, tmp);
5347
5348         spin_unlock_irqrestore(&tp->lock, flags);
5349 }
5350
5351 /**
5352  *  rtl8169_get_stats - Get rtl8169 read/write statistics
5353  *  @dev: The Ethernet Device to get statistics for
5354  *
5355  *  Get TX/RX statistics for rtl8169
5356  */
5357 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
5358 {
5359         struct rtl8169_private *tp = netdev_priv(dev);
5360         void __iomem *ioaddr = tp->mmio_addr;
5361         unsigned long flags;
5362
5363         if (netif_running(dev)) {
5364                 spin_lock_irqsave(&tp->lock, flags);
5365                 rtl8169_rx_missed(dev, ioaddr);
5366                 spin_unlock_irqrestore(&tp->lock, flags);
5367         }
5368
5369         return &dev->stats;
5370 }
5371
5372 static void rtl8169_net_suspend(struct net_device *dev)
5373 {
5374         struct rtl8169_private *tp = netdev_priv(dev);
5375
5376         if (!netif_running(dev))
5377                 return;
5378
5379         rtl_pll_power_down(tp);
5380
5381         netif_device_detach(dev);
5382         netif_stop_queue(dev);
5383 }
5384
5385 #ifdef CONFIG_PM
5386
5387 static int rtl8169_suspend(struct device *device)
5388 {
5389         struct pci_dev *pdev = to_pci_dev(device);
5390         struct net_device *dev = pci_get_drvdata(pdev);
5391
5392         rtl8169_net_suspend(dev);
5393
5394         return 0;
5395 }
5396
5397 static void __rtl8169_resume(struct net_device *dev)
5398 {
5399         struct rtl8169_private *tp = netdev_priv(dev);
5400
5401         netif_device_attach(dev);
5402
5403         rtl_pll_power_up(tp);
5404
5405         rtl8169_schedule_work(dev, rtl8169_reset_task);
5406 }
5407
5408 static int rtl8169_resume(struct device *device)
5409 {
5410         struct pci_dev *pdev = to_pci_dev(device);
5411         struct net_device *dev = pci_get_drvdata(pdev);
5412         struct rtl8169_private *tp = netdev_priv(dev);
5413
5414         rtl8169_init_phy(dev, tp);
5415
5416         if (netif_running(dev))
5417                 __rtl8169_resume(dev);
5418
5419         return 0;
5420 }
5421
5422 static int rtl8169_runtime_suspend(struct device *device)
5423 {
5424         struct pci_dev *pdev = to_pci_dev(device);
5425         struct net_device *dev = pci_get_drvdata(pdev);
5426         struct rtl8169_private *tp = netdev_priv(dev);
5427
5428         if (!tp->TxDescArray)
5429                 return 0;
5430
5431         spin_lock_irq(&tp->lock);
5432         tp->saved_wolopts = __rtl8169_get_wol(tp);
5433         __rtl8169_set_wol(tp, WAKE_ANY);
5434         spin_unlock_irq(&tp->lock);
5435
5436         rtl8169_net_suspend(dev);
5437
5438         return 0;
5439 }
5440
5441 static int rtl8169_runtime_resume(struct device *device)
5442 {
5443         struct pci_dev *pdev = to_pci_dev(device);
5444         struct net_device *dev = pci_get_drvdata(pdev);
5445         struct rtl8169_private *tp = netdev_priv(dev);
5446
5447         if (!tp->TxDescArray)
5448                 return 0;
5449
5450         spin_lock_irq(&tp->lock);
5451         __rtl8169_set_wol(tp, tp->saved_wolopts);
5452         tp->saved_wolopts = 0;
5453         spin_unlock_irq(&tp->lock);
5454
5455         rtl8169_init_phy(dev, tp);
5456
5457         __rtl8169_resume(dev);
5458
5459         return 0;
5460 }
5461
5462 static int rtl8169_runtime_idle(struct device *device)
5463 {
5464         struct pci_dev *pdev = to_pci_dev(device);
5465         struct net_device *dev = pci_get_drvdata(pdev);
5466         struct rtl8169_private *tp = netdev_priv(dev);
5467
5468         return tp->TxDescArray ? -EBUSY : 0;
5469 }
5470
5471 static const struct dev_pm_ops rtl8169_pm_ops = {
5472         .suspend                = rtl8169_suspend,
5473         .resume                 = rtl8169_resume,
5474         .freeze                 = rtl8169_suspend,
5475         .thaw                   = rtl8169_resume,
5476         .poweroff               = rtl8169_suspend,
5477         .restore                = rtl8169_resume,
5478         .runtime_suspend        = rtl8169_runtime_suspend,
5479         .runtime_resume         = rtl8169_runtime_resume,
5480         .runtime_idle           = rtl8169_runtime_idle,
5481 };
5482
5483 #define RTL8169_PM_OPS  (&rtl8169_pm_ops)
5484
5485 #else /* !CONFIG_PM */
5486
5487 #define RTL8169_PM_OPS  NULL
5488
5489 #endif /* !CONFIG_PM */
5490
5491 static void rtl_shutdown(struct pci_dev *pdev)
5492 {
5493         struct net_device *dev = pci_get_drvdata(pdev);
5494         struct rtl8169_private *tp = netdev_priv(dev);
5495         void __iomem *ioaddr = tp->mmio_addr;
5496
5497         rtl8169_net_suspend(dev);
5498
5499         /* Restore original MAC address */
5500         rtl_rar_set(tp, dev->perm_addr);
5501
5502         spin_lock_irq(&tp->lock);
5503
5504         rtl8169_asic_down(ioaddr);
5505
5506         spin_unlock_irq(&tp->lock);
5507
5508         if (system_state == SYSTEM_POWER_OFF) {
5509                 /* WoL fails with some 8168 when the receiver is disabled. */
5510                 if (tp->features & RTL_FEATURE_WOL) {
5511                         pci_clear_master(pdev);
5512
5513                         RTL_W8(ChipCmd, CmdRxEnb);
5514                         /* PCI commit */
5515                         RTL_R8(ChipCmd);
5516                 }
5517
5518                 pci_wake_from_d3(pdev, true);
5519                 pci_set_power_state(pdev, PCI_D3hot);
5520         }
5521 }
5522
5523 static struct pci_driver rtl8169_pci_driver = {
5524         .name           = MODULENAME,
5525         .id_table       = rtl8169_pci_tbl,
5526         .probe          = rtl8169_init_one,
5527         .remove         = __devexit_p(rtl8169_remove_one),
5528         .shutdown       = rtl_shutdown,
5529         .driver.pm      = RTL8169_PM_OPS,
5530 };
5531
5532 static int __init rtl8169_init_module(void)
5533 {
5534         return pci_register_driver(&rtl8169_pci_driver);
5535 }
5536
5537 static void __exit rtl8169_cleanup_module(void)
5538 {
5539         pci_unregister_driver(&rtl8169_pci_driver);
5540 }
5541
5542 module_init(rtl8169_init_module);
5543 module_exit(rtl8169_cleanup_module);