drivers/net/r8169.c

   1 /*
   2  * r8169.c: RealTek 8169/8168/8101 ethernet driver.
   3  *
   4  * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
   5  * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
   6  * Copyright (c) a lot of people too. Please respect their work.
   7  *
   8  * See MAINTAINERS file for support contact information.
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/moduleparam.h>
  13 #include <linux/pci.h>
  14 #include <linux/netdevice.h>
  15 #include <linux/etherdevice.h>
  16 #include <linux/delay.h>
  17 #include <linux/ethtool.h>
  18 #include <linux/mii.h>
  19 #include <linux/if_vlan.h>
  20 #include <linux/crc32.h>
  21 #include <linux/in.h>
  22 #include <linux/ip.h>
  23 #include <linux/tcp.h>
  24 #include <linux/init.h>
  25 #include <linux/dma-mapping.h>
  26
  27 #include <asm/system.h>
  28 #include <asm/io.h>
  29 #include <asm/irq.h>
  30
  31 #define RTL8169_VERSION "2.3LK-NAPI"
  32 #define MODULENAME "r8169"
  33 #define PFX MODULENAME ": "
  34
  35 #ifdef RTL8169_DEBUG
  36 #define assert(expr) \
  37         if (!(expr)) {                                  \
  38                 printk( "Assertion failed! %s,%s,%s,line=%d\n", \
  39                 #expr,__FILE__,__func__,__LINE__);              \
  40         }
  41 #define dprintk(fmt, args...) \
  42         do { printk(KERN_DEBUG PFX fmt, ## args); } while (0)
  43 #else
  44 #define assert(expr) do {} while (0)
  45 #define dprintk(fmt, args...)   do {} while (0)
  46 #endif /* RTL8169_DEBUG */
  47
  48 #define R8169_MSG_DEFAULT \
  49         (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
  50
  51 #define TX_BUFFS_AVAIL(tp) \
  52         (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx - 1)
  53
  54 /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
  55 static const int max_interrupt_work = 20;
  56
  57 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
  58    The RTL chips use a 64 element hash table based on the Ethernet CRC. */
  59 static const int multicast_filter_limit = 32;
  60
  61 /* MAC address length */
  62 #define MAC_ADDR_LEN    6
  63
  64 #define MAX_READ_REQUEST_SHIFT  12
  65 #define RX_FIFO_THRESH  7       /* 7 means NO threshold, Rx buffer level before first PCI xfer. */
  66 #define RX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  67 #define TX_DMA_BURST    6       /* Maximum PCI burst, '6' is 1024 */
  68 #define EarlyTxThld     0x3F    /* 0x3F means NO early transmit */
  69 #define RxPacketMaxSize 0x3FE8  /* 16K - 1 - ETH_HLEN - VLAN - CRC... */
  70 #define SafeMtu         0x1c20  /* ... actually life sucks beyond ~7k */
  71 #define InterFrameGap   0x03    /* 3 means InterFrameGap = the shortest one */
  72
  73 #define R8169_REGS_SIZE         256
  74 #define R8169_NAPI_WEIGHT       64
  75 #define NUM_TX_DESC     64      /* Number of Tx descriptor registers */
  76 #define NUM_RX_DESC     256     /* Number of Rx descriptor registers */
  77 #define RX_BUF_SIZE     1536    /* Rx Buffer size */
  78 #define R8169_TX_RING_BYTES     (NUM_TX_DESC * sizeof(struct TxDesc))
  79 #define R8169_RX_RING_BYTES     (NUM_RX_DESC * sizeof(struct RxDesc))
  80
  81 #define RTL8169_TX_TIMEOUT      (6*HZ)
  82 #define RTL8169_PHY_TIMEOUT     (10*HZ)
  83
  84 /* write/read MMIO register */
  85 #define RTL_W8(reg, val8)       writeb ((val8), ioaddr + (reg))
  86 #define RTL_W16(reg, val16)     writew ((val16), ioaddr + (reg))
  87 #define RTL_W32(reg, val32)     writel ((val32), ioaddr + (reg))
  88 #define RTL_R8(reg)             readb (ioaddr + (reg))
  89 #define RTL_R16(reg)            readw (ioaddr + (reg))
  90 #define RTL_R32(reg)            ((unsigned long) readl (ioaddr + (reg)))
  91
  92 enum mac_version {
  93         RTL_GIGA_MAC_VER_01 = 0x01, // 8169
  94         RTL_GIGA_MAC_VER_02 = 0x02, // 8169S
  95         RTL_GIGA_MAC_VER_03 = 0x03, // 8110S
  96         RTL_GIGA_MAC_VER_04 = 0x04, // 8169SB
  97         RTL_GIGA_MAC_VER_05 = 0x05, // 8110SCd
  98         RTL_GIGA_MAC_VER_06 = 0x06, // 8110SCe
  99         RTL_GIGA_MAC_VER_07 = 0x07, // 8102e
 100         RTL_GIGA_MAC_VER_08 = 0x08, // 8102e
 101         RTL_GIGA_MAC_VER_09 = 0x09, // 8102e
 102         RTL_GIGA_MAC_VER_10 = 0x0a, // 8101e
 103         RTL_GIGA_MAC_VER_11 = 0x0b, // 8168Bb
 104         RTL_GIGA_MAC_VER_12 = 0x0c, // 8168Be
 105         RTL_GIGA_MAC_VER_13 = 0x0d, // 8101Eb
 106         RTL_GIGA_MAC_VER_14 = 0x0e, // 8101 ?
 107         RTL_GIGA_MAC_VER_15 = 0x0f, // 8101 ?
 108         RTL_GIGA_MAC_VER_16 = 0x11, // 8101Ec
 109         RTL_GIGA_MAC_VER_17 = 0x10, // 8168Bf
 110         RTL_GIGA_MAC_VER_18 = 0x12, // 8168CP
 111         RTL_GIGA_MAC_VER_19 = 0x13, // 8168C
 112         RTL_GIGA_MAC_VER_20 = 0x14, // 8168C
 113         RTL_GIGA_MAC_VER_21 = 0x15, // 8168C
 114         RTL_GIGA_MAC_VER_22 = 0x16, // 8168C
 115         RTL_GIGA_MAC_VER_23 = 0x17, // 8168CP
 116         RTL_GIGA_MAC_VER_24 = 0x18, // 8168CP
 117         RTL_GIGA_MAC_VER_25 = 0x19  // 8168D
 118 };
 119
 120 #define _R(NAME,MAC,MASK) \
 121         { .name = NAME, .mac_version = MAC, .RxConfigMask = MASK }
 122
 123 static const struct {
 124         const char *name;
 125         u8 mac_version;
 126         u32 RxConfigMask;       /* Clears the bits supported by this chip */
 127 } rtl_chip_info[] = {
 128         _R("RTL8169",           RTL_GIGA_MAC_VER_01, 0xff7e1880), // 8169
 129         _R("RTL8169s",          RTL_GIGA_MAC_VER_02, 0xff7e1880), // 8169S
 130         _R("RTL8110s",          RTL_GIGA_MAC_VER_03, 0xff7e1880), // 8110S
 131         _R("RTL8169sb/8110sb",  RTL_GIGA_MAC_VER_04, 0xff7e1880), // 8169SB
 132         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_05, 0xff7e1880), // 8110SCd
 133         _R("RTL8169sc/8110sc",  RTL_GIGA_MAC_VER_06, 0xff7e1880), // 8110SCe
 134         _R("RTL8102e",          RTL_GIGA_MAC_VER_07, 0xff7e1880), // PCI-E
 135         _R("RTL8102e",          RTL_GIGA_MAC_VER_08, 0xff7e1880), // PCI-E
 136         _R("RTL8102e",          RTL_GIGA_MAC_VER_09, 0xff7e1880), // PCI-E
 137         _R("RTL8101e",          RTL_GIGA_MAC_VER_10, 0xff7e1880), // PCI-E
 138         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_11, 0xff7e1880), // PCI-E
 139         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_12, 0xff7e1880), // PCI-E
 140         _R("RTL8101e",          RTL_GIGA_MAC_VER_13, 0xff7e1880), // PCI-E 8139
 141         _R("RTL8100e",          RTL_GIGA_MAC_VER_14, 0xff7e1880), // PCI-E 8139
 142         _R("RTL8100e",          RTL_GIGA_MAC_VER_15, 0xff7e1880), // PCI-E 8139
 143         _R("RTL8168b/8111b",    RTL_GIGA_MAC_VER_17, 0xff7e1880), // PCI-E
 144         _R("RTL8101e",          RTL_GIGA_MAC_VER_16, 0xff7e1880), // PCI-E
 145         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_18, 0xff7e1880), // PCI-E
 146         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_19, 0xff7e1880), // PCI-E
 147         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_20, 0xff7e1880), // PCI-E
 148         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_21, 0xff7e1880), // PCI-E
 149         _R("RTL8168c/8111c",    RTL_GIGA_MAC_VER_22, 0xff7e1880), // PCI-E
 150         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_23, 0xff7e1880), // PCI-E
 151         _R("RTL8168cp/8111cp",  RTL_GIGA_MAC_VER_24, 0xff7e1880), // PCI-E
 152         _R("RTL8168d/8111d",    RTL_GIGA_MAC_VER_25, 0xff7e1880)  // PCI-E
 153 };
 154 #undef _R
 155
 156 enum cfg_version {
 157         RTL_CFG_0 = 0x00,
 158         RTL_CFG_1,
 159         RTL_CFG_2
 160 };
 161
 162 static void rtl_hw_start_8169(struct net_device *);
 163 static void rtl_hw_start_8168(struct net_device *);
 164 static void rtl_hw_start_8101(struct net_device *);
 165
 166 static struct pci_device_id rtl8169_pci_tbl[] = {
 167         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8129), 0, 0, RTL_CFG_0 },
 168         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8136), 0, 0, RTL_CFG_2 },
 169         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8167), 0, 0, RTL_CFG_0 },
 170         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8168), 0, 0, RTL_CFG_1 },
 171         { PCI_DEVICE(PCI_VENDOR_ID_REALTEK,     0x8169), 0, 0, RTL_CFG_0 },
 172         { PCI_DEVICE(PCI_VENDOR_ID_DLINK,       0x4300), 0, 0, RTL_CFG_0 },
 173         { PCI_DEVICE(PCI_VENDOR_ID_AT,          0xc107), 0, 0, RTL_CFG_0 },
 174         { PCI_DEVICE(0x16ec,                    0x0116), 0, 0, RTL_CFG_0 },
 175         { PCI_VENDOR_ID_LINKSYS,                0x1032,
 176                 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
 177         { 0x0001,                               0x8168,
 178                 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
 179         {0,},
 180 };
 181
 182 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
 183
 184 static int rx_copybreak = 200;
 185 static int use_dac;
 186 static struct {
 187         u32 msg_enable;
 188 } debug = { -1 };
 189
 190 enum rtl_registers {
 191         MAC0            = 0,    /* Ethernet hardware address. */
 192         MAC4            = 4,
 193         MAR0            = 8,    /* Multicast filter. */
 194         CounterAddrLow          = 0x10,
 195         CounterAddrHigh         = 0x14,
 196         TxDescStartAddrLow      = 0x20,
 197         TxDescStartAddrHigh     = 0x24,
 198         TxHDescStartAddrLow     = 0x28,
 199         TxHDescStartAddrHigh    = 0x2c,
 200         FLASH           = 0x30,
 201         ERSR            = 0x36,
 202         ChipCmd         = 0x37,
 203         TxPoll          = 0x38,
 204         IntrMask        = 0x3c,
 205         IntrStatus      = 0x3e,
 206         TxConfig        = 0x40,
 207         RxConfig        = 0x44,
 208         RxMissed        = 0x4c,
 209         Cfg9346         = 0x50,
 210         Config0         = 0x51,
 211         Config1         = 0x52,
 212         Config2         = 0x53,
 213         Config3         = 0x54,
 214         Config4         = 0x55,
 215         Config5         = 0x56,
 216         MultiIntr       = 0x5c,
 217         PHYAR           = 0x60,
 218         PHYstatus       = 0x6c,
 219         RxMaxSize       = 0xda,
 220         CPlusCmd        = 0xe0,
 221         IntrMitigate    = 0xe2,
 222         RxDescAddrLow   = 0xe4,
 223         RxDescAddrHigh  = 0xe8,
 224         EarlyTxThres    = 0xec,
 225         FuncEvent       = 0xf0,
 226         FuncEventMask   = 0xf4,
 227         FuncPresetState = 0xf8,
 228         FuncForceEvent  = 0xfc,
 229 };
 230
 231 enum rtl8110_registers {
 232         TBICSR                  = 0x64,
 233         TBI_ANAR                = 0x68,
 234         TBI_LPAR                = 0x6a,
 235 };
 236
 237 enum rtl8168_8101_registers {
 238         CSIDR                   = 0x64,
 239         CSIAR                   = 0x68,
 240 #define CSIAR_FLAG                      0x80000000
 241 #define CSIAR_WRITE_CMD                 0x80000000
 242 #define CSIAR_BYTE_ENABLE               0x0f
 243 #define CSIAR_BYTE_ENABLE_SHIFT         12
 244 #define CSIAR_ADDR_MASK                 0x0fff
 245
 246         EPHYAR                  = 0x80,
 247 #define EPHYAR_FLAG                     0x80000000
 248 #define EPHYAR_WRITE_CMD                0x80000000
 249 #define EPHYAR_REG_MASK                 0x1f
 250 #define EPHYAR_REG_SHIFT                16
 251 #define EPHYAR_DATA_MASK                0xffff
 252         DBG_REG                 = 0xd1,
 253 #define FIX_NAK_1                       (1 << 4)
 254 #define FIX_NAK_2                       (1 << 3)
 255 };
 256
 257 enum rtl_register_content {
 258         /* InterruptStatusBits */
 259         SYSErr          = 0x8000,
 260         PCSTimeout      = 0x4000,
 261         SWInt           = 0x0100,
 262         TxDescUnavail   = 0x0080,
 263         RxFIFOOver      = 0x0040,
 264         LinkChg         = 0x0020,
 265         RxOverflow      = 0x0010,
 266         TxErr           = 0x0008,
 267         TxOK            = 0x0004,
 268         RxErr           = 0x0002,
 269         RxOK            = 0x0001,
 270
 271         /* RxStatusDesc */
 272         RxFOVF  = (1 << 23),
 273         RxRWT   = (1 << 22),
 274         RxRES   = (1 << 21),
 275         RxRUNT  = (1 << 20),
 276         RxCRC   = (1 << 19),
 277
 278         /* ChipCmdBits */
 279         CmdReset        = 0x10,
 280         CmdRxEnb        = 0x08,
 281         CmdTxEnb        = 0x04,
 282         RxBufEmpty      = 0x01,
 283
 284         /* TXPoll register p.5 */
 285         HPQ             = 0x80,         /* Poll cmd on the high prio queue */
 286         NPQ             = 0x40,         /* Poll cmd on the low prio queue */
 287         FSWInt          = 0x01,         /* Forced software interrupt */
 288
 289         /* Cfg9346Bits */
 290         Cfg9346_Lock    = 0x00,
 291         Cfg9346_Unlock  = 0xc0,
 292
 293         /* rx_mode_bits */
 294         AcceptErr       = 0x20,
 295         AcceptRunt      = 0x10,
 296         AcceptBroadcast = 0x08,
 297         AcceptMulticast = 0x04,
 298         AcceptMyPhys    = 0x02,
 299         AcceptAllPhys   = 0x01,
 300
 301         /* RxConfigBits */
 302         RxCfgFIFOShift  = 13,
 303         RxCfgDMAShift   =  8,
 304
 305         /* TxConfigBits */
 306         TxInterFrameGapShift = 24,
 307         TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
 308
 309         /* Config1 register p.24 */
 310         LEDS1           = (1 << 7),
 311         LEDS0           = (1 << 6),
 312         MSIEnable       = (1 << 5),     /* Enable Message Signaled Interrupt */
 313         Speed_down      = (1 << 4),
 314         MEMMAP          = (1 << 3),
 315         IOMAP           = (1 << 2),
 316         VPD             = (1 << 1),
 317         PMEnable        = (1 << 0),     /* Power Management Enable */
 318
 319         /* Config2 register p. 25 */
 320         PCI_Clock_66MHz = 0x01,
 321         PCI_Clock_33MHz = 0x00,
 322
 323         /* Config3 register p.25 */
 324         MagicPacket     = (1 << 5),     /* Wake up when receives a Magic Packet */
 325         LinkUp          = (1 << 4),     /* Wake up when the cable connection is re-established */
 326         Beacon_en       = (1 << 0),     /* 8168 only. Reserved in the 8168b */
 327
 328         /* Config5 register p.27 */
 329         BWF             = (1 << 6),     /* Accept Broadcast wakeup frame */
 330         MWF             = (1 << 5),     /* Accept Multicast wakeup frame */
 331         UWF             = (1 << 4),     /* Accept Unicast wakeup frame */
 332         LanWake         = (1 << 1),     /* LanWake enable/disable */
 333         PMEStatus       = (1 << 0),     /* PME status can be reset by PCI RST# */
 334
 335         /* TBICSR p.28 */
 336         TBIReset        = 0x80000000,
 337         TBILoopback     = 0x40000000,
 338         TBINwEnable     = 0x20000000,
 339         TBINwRestart    = 0x10000000,
 340         TBILinkOk       = 0x02000000,
 341         TBINwComplete   = 0x01000000,
 342
 343         /* CPlusCmd p.31 */
 344         EnableBist      = (1 << 15),    // 8168 8101
 345         Mac_dbgo_oe     = (1 << 14),    // 8168 8101
 346         Normal_mode     = (1 << 13),    // unused
 347         Force_half_dup  = (1 << 12),    // 8168 8101
 348         Force_rxflow_en = (1 << 11),    // 8168 8101
 349         Force_txflow_en = (1 << 10),    // 8168 8101
 350         Cxpl_dbg_sel    = (1 << 9),     // 8168 8101
 351         ASF             = (1 << 8),     // 8168 8101
 352         PktCntrDisable  = (1 << 7),     // 8168 8101
 353         Mac_dbgo_sel    = 0x001c,       // 8168
 354         RxVlan          = (1 << 6),
 355         RxChkSum        = (1 << 5),
 356         PCIDAC          = (1 << 4),
 357         PCIMulRW        = (1 << 3),
 358         INTT_0          = 0x0000,       // 8168
 359         INTT_1          = 0x0001,       // 8168
 360         INTT_2          = 0x0002,       // 8168
 361         INTT_3          = 0x0003,       // 8168
 362
 363         /* rtl8169_PHYstatus */
 364         TBI_Enable      = 0x80,
 365         TxFlowCtrl      = 0x40,
 366         RxFlowCtrl      = 0x20,
 367         _1000bpsF       = 0x10,
 368         _100bps         = 0x08,
 369         _10bps          = 0x04,
 370         LinkStatus      = 0x02,
 371         FullDup         = 0x01,
 372
 373         /* _TBICSRBit */
 374         TBILinkOK       = 0x02000000,
 375
 376         /* DumpCounterCommand */
 377         CounterDump     = 0x8,
 378 };
 379
 380 enum desc_status_bit {
 381         DescOwn         = (1 << 31), /* Descriptor is owned by NIC */
 382         RingEnd         = (1 << 30), /* End of descriptor ring */
 383         FirstFrag       = (1 << 29), /* First segment of a packet */
 384         LastFrag        = (1 << 28), /* Final segment of a packet */
 385
 386         /* Tx private */
 387         LargeSend       = (1 << 27), /* TCP Large Send Offload (TSO) */
 388         MSSShift        = 16,        /* MSS value position */
 389         MSSMask         = 0xfff,     /* MSS value + LargeSend bit: 12 bits */
 390         IPCS            = (1 << 18), /* Calculate IP checksum */
 391         UDPCS           = (1 << 17), /* Calculate UDP/IP checksum */
 392         TCPCS           = (1 << 16), /* Calculate TCP/IP checksum */
 393         TxVlanTag       = (1 << 17), /* Add VLAN tag */
 394
 395         /* Rx private */
 396         PID1            = (1 << 18), /* Protocol ID bit 1/2 */
 397         PID0            = (1 << 17), /* Protocol ID bit 2/2 */
 398
 399 #define RxProtoUDP      (PID1)
 400 #define RxProtoTCP      (PID0)
 401 #define RxProtoIP       (PID1 | PID0)
 402 #define RxProtoMask     RxProtoIP
 403
 404         IPFail          = (1 << 16), /* IP checksum failed */
 405         UDPFail         = (1 << 15), /* UDP/IP checksum failed */
 406         TCPFail         = (1 << 14), /* TCP/IP checksum failed */
 407         RxVlanTag       = (1 << 16), /* VLAN tag available */
 408 };
 409
 410 #define RsvdMask        0x3fffc000
 411
 412 struct TxDesc {
 413         __le32 opts1;
 414         __le32 opts2;
 415         __le64 addr;
 416 };
 417
 418 struct RxDesc {
 419         __le32 opts1;
 420         __le32 opts2;
 421         __le64 addr;
 422 };
 423
 424 struct ring_info {
 425         struct sk_buff  *skb;
 426         u32             len;
 427         u8              __pad[sizeof(void *) - sizeof(u32)];
 428 };
 429
 430 enum features {
 431         RTL_FEATURE_WOL         = (1 << 0),
 432         RTL_FEATURE_MSI         = (1 << 1),
 433         RTL_FEATURE_GMII        = (1 << 2),
 434 };
 435
 436 struct rtl8169_private {
 437         void __iomem *mmio_addr;        /* memory map physical address */
 438         struct pci_dev *pci_dev;        /* Index of PCI device */
 439         struct net_device *dev;
 440         struct napi_struct napi;
 441         spinlock_t lock;                /* spin lock flag */
 442         u32 msg_enable;
 443         int chipset;
 444         int mac_version;
 445         u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
 446         u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
 447         u32 dirty_rx;
 448         u32 dirty_tx;
 449         struct TxDesc *TxDescArray;     /* 256-aligned Tx descriptor ring */
 450         struct RxDesc *RxDescArray;     /* 256-aligned Rx descriptor ring */
 451         dma_addr_t TxPhyAddr;
 452         dma_addr_t RxPhyAddr;
 453         struct sk_buff *Rx_skbuff[NUM_RX_DESC]; /* Rx data buffers */
 454         struct ring_info tx_skb[NUM_TX_DESC];   /* Tx data buffers */
 455         unsigned align;
 456         unsigned rx_buf_sz;
 457         struct timer_list timer;
 458         u16 cp_cmd;
 459         u16 intr_event;
 460         u16 napi_event;
 461         u16 intr_mask;
 462         int phy_auto_nego_reg;
 463         int phy_1000_ctrl_reg;
 464 #ifdef CONFIG_R8169_VLAN
 465         struct vlan_group *vlgrp;
 466 #endif
 467         int (*set_speed)(struct net_device *, u8 autoneg, u16 speed, u8 duplex);
 468         int (*get_settings)(struct net_device *, struct ethtool_cmd *);
 469         void (*phy_reset_enable)(void __iomem *);
 470         void (*hw_start)(struct net_device *);
 471         unsigned int (*phy_reset_pending)(void __iomem *);
 472         unsigned int (*link_ok)(void __iomem *);
 473         int pcie_cap;
 474         struct delayed_work task;
 475         unsigned features;
 476
 477         struct mii_if_info mii;
 478 };
 479
 480 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
 481 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
 482 module_param(rx_copybreak, int, 0);
 483 MODULE_PARM_DESC(rx_copybreak, "Copy breakpoint for copy-only-tiny-frames");
 484 module_param(use_dac, int, 0);
 485 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
 486 module_param_named(debug, debug.msg_enable, int, 0);
 487 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
 488 MODULE_LICENSE("GPL");
 489 MODULE_VERSION(RTL8169_VERSION);
 490
 491 static int rtl8169_open(struct net_device *dev);
 492 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev);
 493 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance);
 494 static int rtl8169_init_ring(struct net_device *dev);
 495 static void rtl_hw_start(struct net_device *dev);
 496 static int rtl8169_close(struct net_device *dev);
 497 static void rtl_set_rx_mode(struct net_device *dev);
 498 static void rtl8169_tx_timeout(struct net_device *dev);
 499 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev);
 500 static int rtl8169_rx_interrupt(struct net_device *, struct rtl8169_private *,
 501                                 void __iomem *, u32 budget);
 502 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu);
 503 static void rtl8169_down(struct net_device *dev);
 504 static void rtl8169_rx_clear(struct rtl8169_private *tp);
 505 static int rtl8169_poll(struct napi_struct *napi, int budget);
 506
 507 static const unsigned int rtl8169_rx_config =
 508         (RX_FIFO_THRESH << RxCfgFIFOShift) | (RX_DMA_BURST << RxCfgDMAShift);
 509
 510 static void mdio_write(void __iomem *ioaddr, int reg_addr, int value)
 511 {
 512         int i;
 513
 514         RTL_W32(PHYAR, 0x80000000 | (reg_addr & 0x1f) << 16 | (value & 0xffff));
 515
 516         for (i = 20; i > 0; i--) {
 517                 /*
 518                  * Check if the RTL8169 has completed writing to the specified
 519                  * MII register.
 520                  */
 521                 if (!(RTL_R32(PHYAR) & 0x80000000))
 522                         break;
 523                 udelay(25);
 524         }
 525 }
 526
 527 static int mdio_read(void __iomem *ioaddr, int reg_addr)
 528 {
 529         int i, value = -1;
 530
 531         RTL_W32(PHYAR, 0x0 | (reg_addr & 0x1f) << 16);
 532
 533         for (i = 20; i > 0; i--) {
 534                 /*
 535                  * Check if the RTL8169 has completed retrieving data from
 536                  * the specified MII register.
 537                  */
 538                 if (RTL_R32(PHYAR) & 0x80000000) {
 539                         value = RTL_R32(PHYAR) & 0xffff;
 540                         break;
 541                 }
 542                 udelay(25);
 543         }
 544         return value;
 545 }
 546
 547 static void mdio_patch(void __iomem *ioaddr, int reg_addr, int value)
 548 {
 549         mdio_write(ioaddr, reg_addr, mdio_read(ioaddr, reg_addr) | value);
 550 }
 551
 552 static void rtl_mdio_write(struct net_device *dev, int phy_id, int location,
 553                            int val)
 554 {
 555         struct rtl8169_private *tp = netdev_priv(dev);
 556         void __iomem *ioaddr = tp->mmio_addr;
 557
 558         mdio_write(ioaddr, location, val);
 559 }
 560
 561 static int rtl_mdio_read(struct net_device *dev, int phy_id, int location)
 562 {
 563         struct rtl8169_private *tp = netdev_priv(dev);
 564         void __iomem *ioaddr = tp->mmio_addr;
 565
 566         return mdio_read(ioaddr, location);
 567 }
 568
 569 static void rtl_ephy_write(void __iomem *ioaddr, int reg_addr, int value)
 570 {
 571         unsigned int i;
 572
 573         RTL_W32(EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
 574                 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 575
 576         for (i = 0; i < 100; i++) {
 577                 if (!(RTL_R32(EPHYAR) & EPHYAR_FLAG))
 578                         break;
 579                 udelay(10);
 580         }
 581 }
 582
 583 static u16 rtl_ephy_read(void __iomem *ioaddr, int reg_addr)
 584 {
 585         u16 value = 0xffff;
 586         unsigned int i;
 587
 588         RTL_W32(EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
 589
 590         for (i = 0; i < 100; i++) {
 591                 if (RTL_R32(EPHYAR) & EPHYAR_FLAG) {
 592                         value = RTL_R32(EPHYAR) & EPHYAR_DATA_MASK;
 593                         break;
 594                 }
 595                 udelay(10);
 596         }
 597
 598         return value;
 599 }
 600
 601 static void rtl_csi_write(void __iomem *ioaddr, int addr, int value)
 602 {
 603         unsigned int i;
 604
 605         RTL_W32(CSIDR, value);
 606         RTL_W32(CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
 607                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 608
 609         for (i = 0; i < 100; i++) {
 610                 if (!(RTL_R32(CSIAR) & CSIAR_FLAG))
 611                         break;
 612                 udelay(10);
 613         }
 614 }
 615
 616 static u32 rtl_csi_read(void __iomem *ioaddr, int addr)
 617 {
 618         u32 value = ~0x00;
 619         unsigned int i;
 620
 621         RTL_W32(CSIAR, (addr & CSIAR_ADDR_MASK) |
 622                 CSIAR_BYTE_ENABLE << CSIAR_BYTE_ENABLE_SHIFT);
 623
 624         for (i = 0; i < 100; i++) {
 625                 if (RTL_R32(CSIAR) & CSIAR_FLAG) {
 626                         value = RTL_R32(CSIDR);
 627                         break;
 628                 }
 629                 udelay(10);
 630         }
 631
 632         return value;
 633 }
 634
 635 static void rtl8169_irq_mask_and_ack(void __iomem *ioaddr)
 636 {
 637         RTL_W16(IntrMask, 0x0000);
 638
 639         RTL_W16(IntrStatus, 0xffff);
 640 }
 641
 642 static void rtl8169_asic_down(void __iomem *ioaddr)
 643 {
 644         RTL_W8(ChipCmd, 0x00);
 645         rtl8169_irq_mask_and_ack(ioaddr);
 646         RTL_R16(CPlusCmd);
 647 }
 648
 649 static unsigned int rtl8169_tbi_reset_pending(void __iomem *ioaddr)
 650 {
 651         return RTL_R32(TBICSR) & TBIReset;
 652 }
 653
 654 static unsigned int rtl8169_xmii_reset_pending(void __iomem *ioaddr)
 655 {
 656         return mdio_read(ioaddr, MII_BMCR) & BMCR_RESET;
 657 }
 658
 659 static unsigned int rtl8169_tbi_link_ok(void __iomem *ioaddr)
 660 {
 661         return RTL_R32(TBICSR) & TBILinkOk;
 662 }
 663
 664 static unsigned int rtl8169_xmii_link_ok(void __iomem *ioaddr)
 665 {
 666         return RTL_R8(PHYstatus) & LinkStatus;
 667 }
 668
 669 static void rtl8169_tbi_reset_enable(void __iomem *ioaddr)
 670 {
 671         RTL_W32(TBICSR, RTL_R32(TBICSR) | TBIReset);
 672 }
 673
 674 static void rtl8169_xmii_reset_enable(void __iomem *ioaddr)
 675 {
 676         unsigned int val;
 677
 678         val = mdio_read(ioaddr, MII_BMCR) | BMCR_RESET;
 679         mdio_write(ioaddr, MII_BMCR, val & 0xffff);
 680 }
 681
 682 static void rtl8169_check_link_status(struct net_device *dev,
 683                                       struct rtl8169_private *tp,
 684                                       void __iomem *ioaddr)
 685 {
 686         unsigned long flags;
 687
 688         spin_lock_irqsave(&tp->lock, flags);
 689         if (tp->link_ok(ioaddr)) {
 690                 netif_carrier_on(dev);
 691                 if (netif_msg_ifup(tp))
 692                         printk(KERN_INFO PFX "%s: link up\n", dev->name);
 693         } else {
 694                 if (netif_msg_ifdown(tp))
 695                         printk(KERN_INFO PFX "%s: link down\n", dev->name);
 696                 netif_carrier_off(dev);
 697         }
 698         spin_unlock_irqrestore(&tp->lock, flags);
 699 }
 700
 701 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 702 {
 703         struct rtl8169_private *tp = netdev_priv(dev);
 704         void __iomem *ioaddr = tp->mmio_addr;
 705         u8 options;
 706
 707         wol->wolopts = 0;
 708
 709 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
 710         wol->supported = WAKE_ANY;
 711
 712         spin_lock_irq(&tp->lock);
 713
 714         options = RTL_R8(Config1);
 715         if (!(options & PMEnable))
 716                 goto out_unlock;
 717
 718         options = RTL_R8(Config3);
 719         if (options & LinkUp)
 720                 wol->wolopts |= WAKE_PHY;
 721         if (options & MagicPacket)
 722                 wol->wolopts |= WAKE_MAGIC;
 723
 724         options = RTL_R8(Config5);
 725         if (options & UWF)
 726                 wol->wolopts |= WAKE_UCAST;
 727         if (options & BWF)
 728                 wol->wolopts |= WAKE_BCAST;
 729         if (options & MWF)
 730                 wol->wolopts |= WAKE_MCAST;
 731
 732 out_unlock:
 733         spin_unlock_irq(&tp->lock);
 734 }
 735
 736 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 737 {
 738         struct rtl8169_private *tp = netdev_priv(dev);
 739         void __iomem *ioaddr = tp->mmio_addr;
 740         unsigned int i;
 741         static struct {
 742                 u32 opt;
 743                 u16 reg;
 744                 u8  mask;
 745         } cfg[] = {
 746                 { WAKE_ANY,   Config1, PMEnable },
 747                 { WAKE_PHY,   Config3, LinkUp },
 748                 { WAKE_MAGIC, Config3, MagicPacket },
 749                 { WAKE_UCAST, Config5, UWF },
 750                 { WAKE_BCAST, Config5, BWF },
 751                 { WAKE_MCAST, Config5, MWF },
 752                 { WAKE_ANY,   Config5, LanWake }
 753         };
 754
 755         spin_lock_irq(&tp->lock);
 756
 757         RTL_W8(Cfg9346, Cfg9346_Unlock);
 758
 759         for (i = 0; i < ARRAY_SIZE(cfg); i++) {
 760                 u8 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
 761                 if (wol->wolopts & cfg[i].opt)
 762                         options |= cfg[i].mask;
 763                 RTL_W8(cfg[i].reg, options);
 764         }
 765
 766         RTL_W8(Cfg9346, Cfg9346_Lock);
 767
 768         if (wol->wolopts)
 769                 tp->features |= RTL_FEATURE_WOL;
 770         else
 771                 tp->features &= ~RTL_FEATURE_WOL;
 772         device_set_wakeup_enable(&tp->pci_dev->dev, wol->wolopts);
 773
 774         spin_unlock_irq(&tp->lock);
 775
 776         return 0;
 777 }
 778
 779 static void rtl8169_get_drvinfo(struct net_device *dev,
 780                                 struct ethtool_drvinfo *info)
 781 {
 782         struct rtl8169_private *tp = netdev_priv(dev);
 783
 784         strcpy(info->driver, MODULENAME);
 785         strcpy(info->version, RTL8169_VERSION);
 786         strcpy(info->bus_info, pci_name(tp->pci_dev));
 787 }
 788
 789 static int rtl8169_get_regs_len(struct net_device *dev)
 790 {
 791         return R8169_REGS_SIZE;
 792 }
 793
 794 static int rtl8169_set_speed_tbi(struct net_device *dev,
 795                                  u8 autoneg, u16 speed, u8 duplex)
 796 {
 797         struct rtl8169_private *tp = netdev_priv(dev);
 798         void __iomem *ioaddr = tp->mmio_addr;
 799         int ret = 0;
 800         u32 reg;
 801
 802         reg = RTL_R32(TBICSR);
 803         if ((autoneg == AUTONEG_DISABLE) && (speed == SPEED_1000) &&
 804             (duplex == DUPLEX_FULL)) {
 805                 RTL_W32(TBICSR, reg & ~(TBINwEnable | TBINwRestart));
 806         } else if (autoneg == AUTONEG_ENABLE)
 807                 RTL_W32(TBICSR, reg | TBINwEnable | TBINwRestart);
 808         else {
 809                 if (netif_msg_link(tp)) {
 810                         printk(KERN_WARNING "%s: "
 811                                "incorrect speed setting refused in TBI mode\n",
 812                                dev->name);
 813                 }
 814                 ret = -EOPNOTSUPP;
 815         }
 816
 817         return ret;
 818 }
 819
 820 static int rtl8169_set_speed_xmii(struct net_device *dev,
 821                                   u8 autoneg, u16 speed, u8 duplex)
 822 {
 823         struct rtl8169_private *tp = netdev_priv(dev);
 824         void __iomem *ioaddr = tp->mmio_addr;
 825         int auto_nego, giga_ctrl;
 826
 827         auto_nego = mdio_read(ioaddr, MII_ADVERTISE);
 828         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
 829                        ADVERTISE_100HALF | ADVERTISE_100FULL);
 830         giga_ctrl = mdio_read(ioaddr, MII_CTRL1000);
 831         giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 832
 833         if (autoneg == AUTONEG_ENABLE) {
 834                 auto_nego |= (ADVERTISE_10HALF | ADVERTISE_10FULL |
 835                               ADVERTISE_100HALF | ADVERTISE_100FULL);
 836                 giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 837         } else {
 838                 if (speed == SPEED_10)
 839                         auto_nego |= ADVERTISE_10HALF | ADVERTISE_10FULL;
 840                 else if (speed == SPEED_100)
 841                         auto_nego |= ADVERTISE_100HALF | ADVERTISE_100FULL;
 842                 else if (speed == SPEED_1000)
 843                         giga_ctrl |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
 844
 845                 if (duplex == DUPLEX_HALF)
 846                         auto_nego &= ~(ADVERTISE_10FULL | ADVERTISE_100FULL);
 847
 848                 if (duplex == DUPLEX_FULL)
 849                         auto_nego &= ~(ADVERTISE_10HALF | ADVERTISE_100HALF);
 850
 851                 /* This tweak comes straight from Realtek's driver. */
 852                 if ((speed == SPEED_100) && (duplex == DUPLEX_HALF) &&
 853                     ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 854                      (tp->mac_version == RTL_GIGA_MAC_VER_16))) {
 855                         auto_nego = ADVERTISE_100HALF | ADVERTISE_CSMA;
 856                 }
 857         }
 858
 859         /* The 8100e/8101e/8102e do Fast Ethernet only. */
 860         if ((tp->mac_version == RTL_GIGA_MAC_VER_07) ||
 861             (tp->mac_version == RTL_GIGA_MAC_VER_08) ||
 862             (tp->mac_version == RTL_GIGA_MAC_VER_09) ||
 863             (tp->mac_version == RTL_GIGA_MAC_VER_10) ||
 864             (tp->mac_version == RTL_GIGA_MAC_VER_13) ||
 865             (tp->mac_version == RTL_GIGA_MAC_VER_14) ||
 866             (tp->mac_version == RTL_GIGA_MAC_VER_15) ||
 867             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
 868                 if ((giga_ctrl & (ADVERTISE_1000FULL | ADVERTISE_1000HALF)) &&
 869                     netif_msg_link(tp)) {
 870                         printk(KERN_INFO "%s: PHY does not support 1000Mbps.\n",
 871                                dev->name);
 872                 }
 873                 giga_ctrl &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
 874         }
 875
 876         auto_nego |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 877
 878         if ((tp->mac_version == RTL_GIGA_MAC_VER_11) ||
 879             (tp->mac_version == RTL_GIGA_MAC_VER_12) ||
 880             (tp->mac_version >= RTL_GIGA_MAC_VER_17)) {
 881                 /*
 882                  * Wake up the PHY.
 883                  * Vendor specific (0x1f) and reserved (0x0e) MII registers.
 884                  */
 885                 mdio_write(ioaddr, 0x1f, 0x0000);
 886                 mdio_write(ioaddr, 0x0e, 0x0000);
 887         }
 888
 889         tp->phy_auto_nego_reg = auto_nego;
 890         tp->phy_1000_ctrl_reg = giga_ctrl;
 891
 892         mdio_write(ioaddr, MII_ADVERTISE, auto_nego);
 893         mdio_write(ioaddr, MII_CTRL1000, giga_ctrl);
 894         mdio_write(ioaddr, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
 895         return 0;
 896 }
 897
 898 static int rtl8169_set_speed(struct net_device *dev,
 899                              u8 autoneg, u16 speed, u8 duplex)
 900 {
 901         struct rtl8169_private *tp = netdev_priv(dev);
 902         int ret;
 903
 904         ret = tp->set_speed(dev, autoneg, speed, duplex);
 905
 906         if (netif_running(dev) && (tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
 907                 mod_timer(&tp->timer, jiffies + RTL8169_PHY_TIMEOUT);
 908
 909         return ret;
 910 }
 911
 912 static int rtl8169_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 913 {
 914         struct rtl8169_private *tp = netdev_priv(dev);
 915         unsigned long flags;
 916         int ret;
 917
 918         spin_lock_irqsave(&tp->lock, flags);
 919         ret = rtl8169_set_speed(dev, cmd->autoneg, cmd->speed, cmd->duplex);
 920         spin_unlock_irqrestore(&tp->lock, flags);
 921
 922         return ret;
 923 }
 924
 925 static u32 rtl8169_get_rx_csum(struct net_device *dev)
 926 {
 927         struct rtl8169_private *tp = netdev_priv(dev);
 928
 929         return tp->cp_cmd & RxChkSum;
 930 }
 931
 932 static int rtl8169_set_rx_csum(struct net_device *dev, u32 data)
 933 {
 934         struct rtl8169_private *tp = netdev_priv(dev);
 935         void __iomem *ioaddr = tp->mmio_addr;
 936         unsigned long flags;
 937
 938         spin_lock_irqsave(&tp->lock, flags);
 939
 940         if (data)
 941                 tp->cp_cmd |= RxChkSum;
 942         else
 943                 tp->cp_cmd &= ~RxChkSum;
 944
 945         RTL_W16(CPlusCmd, tp->cp_cmd);
 946         RTL_R16(CPlusCmd);
 947
 948         spin_unlock_irqrestore(&tp->lock, flags);
 949
 950         return 0;
 951 }
 952
 953 #ifdef CONFIG_R8169_VLAN
 954
 955 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 956                                       struct sk_buff *skb)
 957 {
 958         return (tp->vlgrp && vlan_tx_tag_present(skb)) ?
 959                 TxVlanTag | swab16(vlan_tx_tag_get(skb)) : 0x00;
 960 }
 961
 962 static void rtl8169_vlan_rx_register(struct net_device *dev,
 963                                      struct vlan_group *grp)
 964 {
 965         struct rtl8169_private *tp = netdev_priv(dev);
 966         void __iomem *ioaddr = tp->mmio_addr;
 967         unsigned long flags;
 968
 969         spin_lock_irqsave(&tp->lock, flags);
 970         tp->vlgrp = grp;
 971         if (tp->vlgrp)
 972                 tp->cp_cmd |= RxVlan;
 973         else
 974                 tp->cp_cmd &= ~RxVlan;
 975         RTL_W16(CPlusCmd, tp->cp_cmd);
 976         RTL_R16(CPlusCmd);
 977         spin_unlock_irqrestore(&tp->lock, flags);
 978 }
 979
 980 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
 981                                struct sk_buff *skb)
 982 {
 983         u32 opts2 = le32_to_cpu(desc->opts2);
 984         struct vlan_group *vlgrp = tp->vlgrp;
 985         int ret;
 986
 987         if (vlgrp && (opts2 & RxVlanTag)) {
 988                 vlan_hwaccel_receive_skb(skb, vlgrp, swab16(opts2 & 0xffff));
 989                 ret = 0;
 990         } else
 991                 ret = -1;
 992         desc->opts2 = 0;
 993         return ret;
 994 }
 995
 996 #else /* !CONFIG_R8169_VLAN */
 997
 998 static inline u32 rtl8169_tx_vlan_tag(struct rtl8169_private *tp,
 999                                       struct sk_buff *skb)
1000 {
1001         return 0;
1002 }
1003
1004 static int rtl8169_rx_vlan_skb(struct rtl8169_private *tp, struct RxDesc *desc,
1005                                struct sk_buff *skb)
1006 {
1007         return -1;
1008 }
1009
1010 #endif
1011
1012 static int rtl8169_gset_tbi(struct net_device *dev, struct ethtool_cmd *cmd)
1013 {
1014         struct rtl8169_private *tp = netdev_priv(dev);
1015         void __iomem *ioaddr = tp->mmio_addr;
1016         u32 status;
1017
1018         cmd->supported =
1019                 SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_FIBRE;
1020         cmd->port = PORT_FIBRE;
1021         cmd->transceiver = XCVR_INTERNAL;
1022
1023         status = RTL_R32(TBICSR);
1024         cmd->advertising = (status & TBINwEnable) ?  ADVERTISED_Autoneg : 0;
1025         cmd->autoneg = !!(status & TBINwEnable);
1026
1027         cmd->speed = SPEED_1000;
1028         cmd->duplex = DUPLEX_FULL; /* Always set */
1029
1030         return 0;
1031 }
1032
1033 static int rtl8169_gset_xmii(struct net_device *dev, struct ethtool_cmd *cmd)
1034 {
1035         struct rtl8169_private *tp = netdev_priv(dev);
1036
1037         return mii_ethtool_gset(&tp->mii, cmd);
1038 }
1039
1040 static int rtl8169_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1041 {
1042         struct rtl8169_private *tp = netdev_priv(dev);
1043         unsigned long flags;
1044         int rc;
1045
1046         spin_lock_irqsave(&tp->lock, flags);
1047
1048         rc = tp->get_settings(dev, cmd);
1049
1050         spin_unlock_irqrestore(&tp->lock, flags);
1051         return rc;
1052 }
1053
1054 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1055                              void *p)
1056 {
1057         struct rtl8169_private *tp = netdev_priv(dev);
1058         unsigned long flags;
1059
1060         if (regs->len > R8169_REGS_SIZE)
1061                 regs->len = R8169_REGS_SIZE;
1062
1063         spin_lock_irqsave(&tp->lock, flags);
1064         memcpy_fromio(p, tp->mmio_addr, regs->len);
1065         spin_unlock_irqrestore(&tp->lock, flags);
1066 }
1067
1068 static u32 rtl8169_get_msglevel(struct net_device *dev)
1069 {
1070         struct rtl8169_private *tp = netdev_priv(dev);
1071
1072         return tp->msg_enable;
1073 }
1074
1075 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1076 {
1077         struct rtl8169_private *tp = netdev_priv(dev);
1078
1079         tp->msg_enable = value;
1080 }
1081
1082 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1083         "tx_packets",
1084         "rx_packets",
1085         "tx_errors",
1086         "rx_errors",
1087         "rx_missed",
1088         "align_errors",
1089         "tx_single_collisions",
1090         "tx_multi_collisions",
1091         "unicast",
1092         "broadcast",
1093         "multicast",
1094         "tx_aborted",
1095         "tx_underrun",
1096 };
1097
1098 struct rtl8169_counters {
1099         __le64  tx_packets;
1100         __le64  rx_packets;
1101         __le64  tx_errors;
1102         __le32  rx_errors;
1103         __le16  rx_missed;
1104         __le16  align_errors;
1105         __le32  tx_one_collision;
1106         __le32  tx_multi_collision;
1107         __le64  rx_unicast;
1108         __le64  rx_broadcast;
1109         __le32  rx_multicast;
1110         __le16  tx_aborted;
1111         __le16  tx_underun;
1112 };
1113
1114 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1115 {
1116         switch (sset) {
1117         case ETH_SS_STATS:
1118                 return ARRAY_SIZE(rtl8169_gstrings);
1119         default:
1120                 return -EOPNOTSUPP;
1121         }
1122 }
1123
1124 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1125                                       struct ethtool_stats *stats, u64 *data)
1126 {
1127         struct rtl8169_private *tp = netdev_priv(dev);
1128         void __iomem *ioaddr = tp->mmio_addr;
1129         struct rtl8169_counters *counters;
1130         dma_addr_t paddr;
1131         u32 cmd;
1132
1133         ASSERT_RTNL();
1134
1135         counters = pci_alloc_consistent(tp->pci_dev, sizeof(*counters), &paddr);
1136         if (!counters)
1137                 return;
1138
1139         RTL_W32(CounterAddrHigh, (u64)paddr >> 32);
1140         cmd = (u64)paddr & DMA_32BIT_MASK;
1141         RTL_W32(CounterAddrLow, cmd);
1142         RTL_W32(CounterAddrLow, cmd | CounterDump);
1143
1144         while (RTL_R32(CounterAddrLow) & CounterDump) {
1145                 if (msleep_interruptible(1))
1146                         break;
1147         }
1148
1149         RTL_W32(CounterAddrLow, 0);
1150         RTL_W32(CounterAddrHigh, 0);
1151
1152         data[0] = le64_to_cpu(counters->tx_packets);
1153         data[1] = le64_to_cpu(counters->rx_packets);
1154         data[2] = le64_to_cpu(counters->tx_errors);
1155         data[3] = le32_to_cpu(counters->rx_errors);
1156         data[4] = le16_to_cpu(counters->rx_missed);
1157         data[5] = le16_to_cpu(counters->align_errors);
1158         data[6] = le32_to_cpu(counters->tx_one_collision);
1159         data[7] = le32_to_cpu(counters->tx_multi_collision);
1160         data[8] = le64_to_cpu(counters->rx_unicast);
1161         data[9] = le64_to_cpu(counters->rx_broadcast);
1162         data[10] = le32_to_cpu(counters->rx_multicast);
1163         data[11] = le16_to_cpu(counters->tx_aborted);
1164         data[12] = le16_to_cpu(counters->tx_underun);
1165
1166         pci_free_consistent(tp->pci_dev, sizeof(*counters), counters, paddr);
1167 }
1168
1169 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1170 {
1171         switch(stringset) {
1172         case ETH_SS_STATS:
1173                 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1174                 break;
1175         }
1176 }
1177
1178 static const struct ethtool_ops rtl8169_ethtool_ops = {
1179         .get_drvinfo            = rtl8169_get_drvinfo,
1180         .get_regs_len           = rtl8169_get_regs_len,
1181         .get_link               = ethtool_op_get_link,
1182         .get_settings           = rtl8169_get_settings,
1183         .set_settings           = rtl8169_set_settings,
1184         .get_msglevel           = rtl8169_get_msglevel,
1185         .set_msglevel           = rtl8169_set_msglevel,
1186         .get_rx_csum            = rtl8169_get_rx_csum,
1187         .set_rx_csum            = rtl8169_set_rx_csum,
1188         .set_tx_csum            = ethtool_op_set_tx_csum,
1189         .set_sg                 = ethtool_op_set_sg,
1190         .set_tso                = ethtool_op_set_tso,
1191         .get_regs               = rtl8169_get_regs,
1192         .get_wol                = rtl8169_get_wol,
1193         .set_wol                = rtl8169_set_wol,
1194         .get_strings            = rtl8169_get_strings,
1195         .get_sset_count         = rtl8169_get_sset_count,
1196         .get_ethtool_stats      = rtl8169_get_ethtool_stats,
1197 };
1198
1199 static void rtl8169_write_gmii_reg_bit(void __iomem *ioaddr, int reg,
1200                                        int bitnum, int bitval)
1201 {
1202         int val;
1203
1204         val = mdio_read(ioaddr, reg);
1205         val = (bitval == 1) ?
1206                 val | (bitval << bitnum) :  val & ~(0x0001 << bitnum);
1207         mdio_write(ioaddr, reg, val & 0xffff);
1208 }
1209
1210 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
1211                                     void __iomem *ioaddr)
1212 {
1213         /*
1214          * The driver currently handles the 8168Bf and the 8168Be identically
1215          * but they can be identified more specifically through the test below
1216          * if needed:
1217          *
1218          * (RTL_R32(TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
1219          *
1220          * Same thing for the 8101Eb and the 8101Ec:
1221          *
1222          * (RTL_R32(TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
1223          */
1224         const struct {
1225                 u32 mask;
1226                 u32 val;
1227                 int mac_version;
1228         } mac_info[] = {
1229                 /* 8168D family. */
1230                 { 0x7c800000, 0x28000000,       RTL_GIGA_MAC_VER_25 },
1231
1232                 /* 8168C family. */
1233                 { 0x7cf00000, 0x3ca00000,       RTL_GIGA_MAC_VER_24 },
1234                 { 0x7cf00000, 0x3c900000,       RTL_GIGA_MAC_VER_23 },
1235                 { 0x7cf00000, 0x3c800000,       RTL_GIGA_MAC_VER_18 },
1236                 { 0x7c800000, 0x3c800000,       RTL_GIGA_MAC_VER_24 },
1237                 { 0x7cf00000, 0x3c000000,       RTL_GIGA_MAC_VER_19 },
1238                 { 0x7cf00000, 0x3c200000,       RTL_GIGA_MAC_VER_20 },
1239                 { 0x7cf00000, 0x3c300000,       RTL_GIGA_MAC_VER_21 },
1240                 { 0x7cf00000, 0x3c400000,       RTL_GIGA_MAC_VER_22 },
1241                 { 0x7c800000, 0x3c000000,       RTL_GIGA_MAC_VER_22 },
1242
1243                 /* 8168B family. */
1244                 { 0x7cf00000, 0x38000000,       RTL_GIGA_MAC_VER_12 },
1245                 { 0x7cf00000, 0x38500000,       RTL_GIGA_MAC_VER_17 },
1246                 { 0x7c800000, 0x38000000,       RTL_GIGA_MAC_VER_17 },
1247                 { 0x7c800000, 0x30000000,       RTL_GIGA_MAC_VER_11 },
1248
1249                 /* 8101 family. */
1250                 { 0x7cf00000, 0x34a00000,       RTL_GIGA_MAC_VER_09 },
1251                 { 0x7cf00000, 0x24a00000,       RTL_GIGA_MAC_VER_09 },
1252                 { 0x7cf00000, 0x34900000,       RTL_GIGA_MAC_VER_08 },
1253                 { 0x7cf00000, 0x24900000,       RTL_GIGA_MAC_VER_08 },
1254                 { 0x7cf00000, 0x34800000,       RTL_GIGA_MAC_VER_07 },
1255                 { 0x7cf00000, 0x24800000,       RTL_GIGA_MAC_VER_07 },
1256                 { 0x7cf00000, 0x34000000,       RTL_GIGA_MAC_VER_13 },
1257                 { 0x7cf00000, 0x34300000,       RTL_GIGA_MAC_VER_10 },
1258                 { 0x7cf00000, 0x34200000,       RTL_GIGA_MAC_VER_16 },
1259                 { 0x7c800000, 0x34800000,       RTL_GIGA_MAC_VER_09 },
1260                 { 0x7c800000, 0x24800000,       RTL_GIGA_MAC_VER_09 },
1261                 { 0x7c800000, 0x34000000,       RTL_GIGA_MAC_VER_16 },
1262                 /* FIXME: where did these entries come from ? -- FR */
1263                 { 0xfc800000, 0x38800000,       RTL_GIGA_MAC_VER_15 },
1264                 { 0xfc800000, 0x30800000,       RTL_GIGA_MAC_VER_14 },
1265
1266                 /* 8110 family. */
1267                 { 0xfc800000, 0x98000000,       RTL_GIGA_MAC_VER_06 },
1268                 { 0xfc800000, 0x18000000,       RTL_GIGA_MAC_VER_05 },
1269                 { 0xfc800000, 0x10000000,       RTL_GIGA_MAC_VER_04 },
1270                 { 0xfc800000, 0x04000000,       RTL_GIGA_MAC_VER_03 },
1271                 { 0xfc800000, 0x00800000,       RTL_GIGA_MAC_VER_02 },
1272                 { 0xfc800000, 0x00000000,       RTL_GIGA_MAC_VER_01 },
1273
1274                 { 0x00000000, 0x00000000,       RTL_GIGA_MAC_VER_01 }   /* Catch-all */
1275         }, *p = mac_info;
1276         u32 reg;
1277
1278         reg = RTL_R32(TxConfig);
1279         while ((reg & p->mask) != p->val)
1280                 p++;
1281         tp->mac_version = p->mac_version;
1282
1283         if (p->mask == 0x00000000) {
1284                 struct pci_dev *pdev = tp->pci_dev;
1285
1286                 dev_info(&pdev->dev, "unknown MAC (%08x)\n", reg);
1287         }
1288 }
1289
1290 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
1291 {
1292         dprintk("mac_version = 0x%02x\n", tp->mac_version);
1293 }
1294
1295 struct phy_reg {
1296         u16 reg;
1297         u16 val;
1298 };
1299
1300 static void rtl_phy_write(void __iomem *ioaddr, struct phy_reg *regs, int len)
1301 {
1302         while (len-- > 0) {
1303                 mdio_write(ioaddr, regs->reg, regs->val);
1304                 regs++;
1305         }
1306 }
1307
1308 static void rtl8169s_hw_phy_config(void __iomem *ioaddr)
1309 {
1310         struct {
1311                 u16 regs[5]; /* Beware of bit-sign propagation */
1312         } phy_magic[5] = { {
1313                 { 0x0000,       //w 4 15 12 0
1314                   0x00a1,       //w 3 15 0 00a1
1315                   0x0008,       //w 2 15 0 0008
1316                   0x1020,       //w 1 15 0 1020
1317                   0x1000 } },{  //w 0 15 0 1000
1318                 { 0x7000,       //w 4 15 12 7
1319                   0xff41,       //w 3 15 0 ff41
1320                   0xde60,       //w 2 15 0 de60
1321                   0x0140,       //w 1 15 0 0140
1322                   0x0077 } },{  //w 0 15 0 0077
1323                 { 0xa000,       //w 4 15 12 a
1324                   0xdf01,       //w 3 15 0 df01
1325                   0xdf20,       //w 2 15 0 df20
1326                   0xff95,       //w 1 15 0 ff95
1327                   0xfa00 } },{  //w 0 15 0 fa00
1328                 { 0xb000,       //w 4 15 12 b
1329                   0xff41,       //w 3 15 0 ff41
1330                   0xde20,       //w 2 15 0 de20
1331                   0x0140,       //w 1 15 0 0140
1332                   0x00bb } },{  //w 0 15 0 00bb
1333                 { 0xf000,       //w 4 15 12 f
1334                   0xdf01,       //w 3 15 0 df01
1335                   0xdf20,       //w 2 15 0 df20
1336                   0xff95,       //w 1 15 0 ff95
1337                   0xbf00 }      //w 0 15 0 bf00
1338                 }
1339         }, *p = phy_magic;
1340         unsigned int i;
1341
1342         mdio_write(ioaddr, 0x1f, 0x0001);               //w 31 2 0 1
1343         mdio_write(ioaddr, 0x15, 0x1000);               //w 21 15 0 1000
1344         mdio_write(ioaddr, 0x18, 0x65c7);               //w 24 15 0 65c7
1345         rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0);   //w 4 11 11 0
1346
1347         for (i = 0; i < ARRAY_SIZE(phy_magic); i++, p++) {
1348                 int val, pos = 4;
1349
1350                 val = (mdio_read(ioaddr, pos) & 0x0fff) | (p->regs[0] & 0xffff);
1351                 mdio_write(ioaddr, pos, val);
1352                 while (--pos >= 0)
1353                         mdio_write(ioaddr, pos, p->regs[4 - pos] & 0xffff);
1354                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 1); //w 4 11 11 1
1355                 rtl8169_write_gmii_reg_bit(ioaddr, 4, 11, 0); //w 4 11 11 0
1356         }
1357         mdio_write(ioaddr, 0x1f, 0x0000); //w 31 2 0 0
1358 }
1359
1360 static void rtl8169sb_hw_phy_config(void __iomem *ioaddr)
1361 {
1362         struct phy_reg phy_reg_init[] = {
1363                 { 0x1f, 0x0002 },
1364                 { 0x01, 0x90d0 },
1365                 { 0x1f, 0x0000 }
1366         };
1367
1368         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1369 }
1370
1371 static void rtl8168bb_hw_phy_config(void __iomem *ioaddr)
1372 {
1373         struct phy_reg phy_reg_init[] = {
1374                 { 0x10, 0xf41b },
1375                 { 0x1f, 0x0000 }
1376         };
1377
1378         mdio_write(ioaddr, 0x1f, 0x0001);
1379         mdio_patch(ioaddr, 0x16, 1 << 0);
1380
1381         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1382 }
1383
1384 static void rtl8168bef_hw_phy_config(void __iomem *ioaddr)
1385 {
1386         struct phy_reg phy_reg_init[] = {
1387                 { 0x1f, 0x0001 },
1388                 { 0x10, 0xf41b },
1389                 { 0x1f, 0x0000 }
1390         };
1391
1392         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1393 }
1394
1395 static void rtl8168cp_1_hw_phy_config(void __iomem *ioaddr)
1396 {
1397         struct phy_reg phy_reg_init[] = {
1398                 { 0x1f, 0x0000 },
1399                 { 0x1d, 0x0f00 },
1400                 { 0x1f, 0x0002 },
1401                 { 0x0c, 0x1ec8 },
1402                 { 0x1f, 0x0000 }
1403         };
1404
1405         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1406 }
1407
1408 static void rtl8168cp_2_hw_phy_config(void __iomem *ioaddr)
1409 {
1410         struct phy_reg phy_reg_init[] = {
1411                 { 0x1f, 0x0001 },
1412                 { 0x1d, 0x3d98 },
1413                 { 0x1f, 0x0000 }
1414         };
1415
1416         mdio_write(ioaddr, 0x1f, 0x0000);
1417         mdio_patch(ioaddr, 0x14, 1 << 5);
1418         mdio_patch(ioaddr, 0x0d, 1 << 5);
1419
1420         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1421 }
1422
1423 static void rtl8168c_1_hw_phy_config(void __iomem *ioaddr)
1424 {
1425         struct phy_reg phy_reg_init[] = {
1426                 { 0x1f, 0x0001 },
1427                 { 0x12, 0x2300 },
1428                 { 0x1f, 0x0002 },
1429                 { 0x00, 0x88d4 },
1430                 { 0x01, 0x82b1 },
1431                 { 0x03, 0x7002 },
1432                 { 0x08, 0x9e30 },
1433                 { 0x09, 0x01f0 },
1434                 { 0x0a, 0x5500 },
1435                 { 0x0c, 0x00c8 },
1436                 { 0x1f, 0x0003 },
1437                 { 0x12, 0xc096 },
1438                 { 0x16, 0x000a },
1439                 { 0x1f, 0x0000 },
1440                 { 0x1f, 0x0000 },
1441                 { 0x09, 0x2000 },
1442                 { 0x09, 0x0000 }
1443         };
1444
1445         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1446
1447         mdio_patch(ioaddr, 0x14, 1 << 5);
1448         mdio_patch(ioaddr, 0x0d, 1 << 5);
1449         mdio_write(ioaddr, 0x1f, 0x0000);
1450 }
1451
1452 static void rtl8168c_2_hw_phy_config(void __iomem *ioaddr)
1453 {
1454         struct phy_reg phy_reg_init[] = {
1455                 { 0x1f, 0x0001 },
1456                 { 0x12, 0x2300 },
1457                 { 0x03, 0x802f },
1458                 { 0x02, 0x4f02 },
1459                 { 0x01, 0x0409 },
1460                 { 0x00, 0xf099 },
1461                 { 0x04, 0x9800 },
1462                 { 0x04, 0x9000 },
1463                 { 0x1d, 0x3d98 },
1464                 { 0x1f, 0x0002 },
1465                 { 0x0c, 0x7eb8 },
1466                 { 0x06, 0x0761 },
1467                 { 0x1f, 0x0003 },
1468                 { 0x16, 0x0f0a },
1469                 { 0x1f, 0x0000 }
1470         };
1471
1472         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1473
1474         mdio_patch(ioaddr, 0x16, 1 << 0);
1475         mdio_patch(ioaddr, 0x14, 1 << 5);
1476         mdio_patch(ioaddr, 0x0d, 1 << 5);
1477         mdio_write(ioaddr, 0x1f, 0x0000);
1478 }
1479
1480 static void rtl8168c_3_hw_phy_config(void __iomem *ioaddr)
1481 {
1482         struct phy_reg phy_reg_init[] = {
1483                 { 0x1f, 0x0001 },
1484                 { 0x12, 0x2300 },
1485                 { 0x1d, 0x3d98 },
1486                 { 0x1f, 0x0002 },
1487                 { 0x0c, 0x7eb8 },
1488                 { 0x06, 0x5461 },
1489                 { 0x1f, 0x0003 },
1490                 { 0x16, 0x0f0a },
1491                 { 0x1f, 0x0000 }
1492         };
1493
1494         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1495
1496         mdio_patch(ioaddr, 0x16, 1 << 0);
1497         mdio_patch(ioaddr, 0x14, 1 << 5);
1498         mdio_patch(ioaddr, 0x0d, 1 << 5);
1499         mdio_write(ioaddr, 0x1f, 0x0000);
1500 }
1501
1502 static void rtl8168c_4_hw_phy_config(void __iomem *ioaddr)
1503 {
1504         rtl8168c_3_hw_phy_config(ioaddr);
1505 }
1506
1507 static void rtl8168d_hw_phy_config(void __iomem *ioaddr)
1508 {
1509         struct phy_reg phy_reg_init_0[] = {
1510                 { 0x1f, 0x0001 },
1511                 { 0x09, 0x2770 },
1512                 { 0x08, 0x04d0 },
1513                 { 0x0b, 0xad15 },
1514                 { 0x0c, 0x5bf0 },
1515                 { 0x1c, 0xf101 },
1516                 { 0x1f, 0x0003 },
1517                 { 0x14, 0x94d7 },
1518                 { 0x12, 0xf4d6 },
1519                 { 0x09, 0xca0f },
1520                 { 0x1f, 0x0002 },
1521                 { 0x0b, 0x0b10 },
1522                 { 0x0c, 0xd1f7 },
1523                 { 0x1f, 0x0002 },
1524                 { 0x06, 0x5461 },
1525                 { 0x1f, 0x0002 },
1526                 { 0x05, 0x6662 },
1527                 { 0x1f, 0x0000 },
1528                 { 0x14, 0x0060 },
1529                 { 0x1f, 0x0000 },
1530                 { 0x0d, 0xf8a0 },
1531                 { 0x1f, 0x0005 },
1532                 { 0x05, 0xffc2 }
1533         };
1534
1535         rtl_phy_write(ioaddr, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
1536
1537         if (mdio_read(ioaddr, 0x06) == 0xc400) {
1538                 struct phy_reg phy_reg_init_1[] = {
1539                         { 0x1f, 0x0005 },
1540                         { 0x01, 0x0300 },
1541                         { 0x1f, 0x0000 },
1542                         { 0x11, 0x401c },
1543                         { 0x16, 0x4100 },
1544                         { 0x1f, 0x0005 },
1545                         { 0x07, 0x0010 },
1546                         { 0x05, 0x83dc },
1547                         { 0x06, 0x087d },
1548                         { 0x05, 0x8300 },
1549                         { 0x06, 0x0101 },
1550                         { 0x06, 0x05f8 },
1551                         { 0x06, 0xf9fa },
1552                         { 0x06, 0xfbef },
1553                         { 0x06, 0x79e2 },
1554                         { 0x06, 0x835f },
1555                         { 0x06, 0xe0f8 },
1556                         { 0x06, 0x9ae1 },
1557                         { 0x06, 0xf89b },
1558                         { 0x06, 0xef31 },
1559                         { 0x06, 0x3b65 },
1560                         { 0x06, 0xaa07 },
1561                         { 0x06, 0x81e4 },
1562                         { 0x06, 0xf89a },
1563                         { 0x06, 0xe5f8 },
1564                         { 0x06, 0x9baf },
1565                         { 0x06, 0x06ae },
1566                         { 0x05, 0x83dc },
1567                         { 0x06, 0x8300 },
1568                 };
1569
1570                 rtl_phy_write(ioaddr, phy_reg_init_1,
1571                               ARRAY_SIZE(phy_reg_init_1));
1572         }
1573
1574         mdio_write(ioaddr, 0x1f, 0x0000);
1575 }
1576
1577 static void rtl8102e_hw_phy_config(void __iomem *ioaddr)
1578 {
1579         struct phy_reg phy_reg_init[] = {
1580                 { 0x1f, 0x0003 },
1581                 { 0x08, 0x441d },
1582                 { 0x01, 0x9100 },
1583                 { 0x1f, 0x0000 }
1584         };
1585
1586         mdio_write(ioaddr, 0x1f, 0x0000);
1587         mdio_patch(ioaddr, 0x11, 1 << 12);
1588         mdio_patch(ioaddr, 0x19, 1 << 13);
1589
1590         rtl_phy_write(ioaddr, phy_reg_init, ARRAY_SIZE(phy_reg_init));
1591 }
1592
1593 static void rtl_hw_phy_config(struct net_device *dev)
1594 {
1595         struct rtl8169_private *tp = netdev_priv(dev);
1596         void __iomem *ioaddr = tp->mmio_addr;
1597
1598         rtl8169_print_mac_version(tp);
1599
1600         switch (tp->mac_version) {
1601         case RTL_GIGA_MAC_VER_01:
1602                 break;
1603         case RTL_GIGA_MAC_VER_02:
1604         case RTL_GIGA_MAC_VER_03:
1605                 rtl8169s_hw_phy_config(ioaddr);
1606                 break;
1607         case RTL_GIGA_MAC_VER_04:
1608                 rtl8169sb_hw_phy_config(ioaddr);
1609                 break;
1610         case RTL_GIGA_MAC_VER_07:
1611         case RTL_GIGA_MAC_VER_08:
1612         case RTL_GIGA_MAC_VER_09:
1613                 rtl8102e_hw_phy_config(ioaddr);
1614                 break;
1615         case RTL_GIGA_MAC_VER_11:
1616                 rtl8168bb_hw_phy_config(ioaddr);
1617                 break;
1618         case RTL_GIGA_MAC_VER_12:
1619                 rtl8168bef_hw_phy_config(ioaddr);
1620                 break;
1621         case RTL_GIGA_MAC_VER_17:
1622                 rtl8168bef_hw_phy_config(ioaddr);
1623                 break;
1624         case RTL_GIGA_MAC_VER_18:
1625                 rtl8168cp_1_hw_phy_config(ioaddr);
1626                 break;
1627         case RTL_GIGA_MAC_VER_19:
1628                 rtl8168c_1_hw_phy_config(ioaddr);
1629                 break;
1630         case RTL_GIGA_MAC_VER_20:
1631                 rtl8168c_2_hw_phy_config(ioaddr);
1632                 break;
1633         case RTL_GIGA_MAC_VER_21:
1634                 rtl8168c_3_hw_phy_config(ioaddr);
1635                 break;
1636         case RTL_GIGA_MAC_VER_22:
1637                 rtl8168c_4_hw_phy_config(ioaddr);
1638                 break;
1639         case RTL_GIGA_MAC_VER_23:
1640         case RTL_GIGA_MAC_VER_24:
1641                 rtl8168cp_2_hw_phy_config(ioaddr);
1642                 break;
1643         case RTL_GIGA_MAC_VER_25:
1644                 rtl8168d_hw_phy_config(ioaddr);
1645                 break;
1646
1647         default:
1648                 break;
1649         }
1650 }
1651
1652 static void rtl8169_phy_timer(unsigned long __opaque)
1653 {
1654         struct net_device *dev = (struct net_device *)__opaque;
1655         struct rtl8169_private *tp = netdev_priv(dev);
1656         struct timer_list *timer = &tp->timer;
1657         void __iomem *ioaddr = tp->mmio_addr;
1658         unsigned long timeout = RTL8169_PHY_TIMEOUT;
1659
1660         assert(tp->mac_version > RTL_GIGA_MAC_VER_01);
1661
1662         if (!(tp->phy_1000_ctrl_reg & ADVERTISE_1000FULL))
1663                 return;
1664
1665         spin_lock_irq(&tp->lock);
1666
1667         if (tp->phy_reset_pending(ioaddr)) {
1668                 /*
1669                  * A busy loop could burn quite a few cycles on nowadays CPU.
1670                  * Let's delay the execution of the timer for a few ticks.
1671                  */
1672                 timeout = HZ/10;
1673                 goto out_mod_timer;
1674         }
1675
1676         if (tp->link_ok(ioaddr))
1677                 goto out_unlock;
1678
1679         if (netif_msg_link(tp))
1680                 printk(KERN_WARNING "%s: PHY reset until link up\n", dev->name);
1681
1682         tp->phy_reset_enable(ioaddr);
1683
1684 out_mod_timer:
1685         mod_timer(timer, jiffies + timeout);
1686 out_unlock:
1687         spin_unlock_irq(&tp->lock);
1688 }
1689
1690 static inline void rtl8169_delete_timer(struct net_device *dev)
1691 {
1692         struct rtl8169_private *tp = netdev_priv(dev);
1693         struct timer_list *timer = &tp->timer;
1694
1695         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1696                 return;
1697
1698         del_timer_sync(timer);
1699 }
1700
1701 static inline void rtl8169_request_timer(struct net_device *dev)
1702 {
1703         struct rtl8169_private *tp = netdev_priv(dev);
1704         struct timer_list *timer = &tp->timer;
1705
1706         if (tp->mac_version <= RTL_GIGA_MAC_VER_01)
1707                 return;
1708
1709         mod_timer(timer, jiffies + RTL8169_PHY_TIMEOUT);
1710 }
1711
1712 #ifdef CONFIG_NET_POLL_CONTROLLER
1713 /*
1714  * Polling 'interrupt' - used by things like netconsole to send skbs
1715  * without having to re-enable interrupts. It's not called while
1716  * the interrupt routine is executing.
1717  */
1718 static void rtl8169_netpoll(struct net_device *dev)
1719 {
1720         struct rtl8169_private *tp = netdev_priv(dev);
1721         struct pci_dev *pdev = tp->pci_dev;
1722
1723         disable_irq(pdev->irq);
1724         rtl8169_interrupt(pdev->irq, dev);
1725         enable_irq(pdev->irq);
1726 }
1727 #endif
1728
1729 static void rtl8169_release_board(struct pci_dev *pdev, struct net_device *dev,
1730                                   void __iomem *ioaddr)
1731 {
1732         iounmap(ioaddr);
1733         pci_release_regions(pdev);
1734         pci_disable_device(pdev);
1735         free_netdev(dev);
1736 }
1737
1738 static void rtl8169_phy_reset(struct net_device *dev,
1739                               struct rtl8169_private *tp)
1740 {
1741         void __iomem *ioaddr = tp->mmio_addr;
1742         unsigned int i;
1743
1744         tp->phy_reset_enable(ioaddr);
1745         for (i = 0; i < 100; i++) {
1746                 if (!tp->phy_reset_pending(ioaddr))
1747                         return;
1748                 msleep(1);
1749         }
1750         if (netif_msg_link(tp))
1751                 printk(KERN_ERR "%s: PHY reset failed.\n", dev->name);
1752 }
1753
1754 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
1755 {
1756         void __iomem *ioaddr = tp->mmio_addr;
1757
1758         rtl_hw_phy_config(dev);
1759
1760         if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
1761                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1762                 RTL_W8(0x82, 0x01);
1763         }
1764
1765         pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
1766
1767         if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
1768                 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
1769
1770         if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
1771                 dprintk("Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
1772                 RTL_W8(0x82, 0x01);
1773                 dprintk("Set PHY Reg 0x0bh = 0x00h\n");
1774                 mdio_write(ioaddr, 0x0b, 0x0000); //w 0x0b 15 0 0
1775         }
1776
1777         rtl8169_phy_reset(dev, tp);
1778
1779         /*
1780          * rtl8169_set_speed_xmii takes good care of the Fast Ethernet
1781          * only 8101. Don't panic.
1782          */
1783         rtl8169_set_speed(dev, AUTONEG_ENABLE, SPEED_1000, DUPLEX_FULL);
1784
1785         if ((RTL_R8(PHYstatus) & TBI_Enable) && netif_msg_link(tp))
1786                 printk(KERN_INFO PFX "%s: TBI auto-negotiating\n", dev->name);
1787 }
1788
1789 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
1790 {
1791         void __iomem *ioaddr = tp->mmio_addr;
1792         u32 high;
1793         u32 low;
1794
1795         low  = addr[0] | (addr[1] << 8) | (addr[2] << 16) | (addr[3] << 24);
1796         high = addr[4] | (addr[5] << 8);
1797
1798         spin_lock_irq(&tp->lock);
1799
1800         RTL_W8(Cfg9346, Cfg9346_Unlock);
1801         RTL_W32(MAC0, low);
1802         RTL_W32(MAC4, high);
1803         RTL_W8(Cfg9346, Cfg9346_Lock);
1804
1805         spin_unlock_irq(&tp->lock);
1806 }
1807
1808 static int rtl_set_mac_address(struct net_device *dev, void *p)
1809 {
1810         struct rtl8169_private *tp = netdev_priv(dev);
1811         struct sockaddr *addr = p;
1812
1813         if (!is_valid_ether_addr(addr->sa_data))
1814                 return -EADDRNOTAVAIL;
1815
1816         memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
1817
1818         rtl_rar_set(tp, dev->dev_addr);
1819
1820         return 0;
1821 }
1822
1823 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1824 {
1825         struct rtl8169_private *tp = netdev_priv(dev);
1826         struct mii_ioctl_data *data = if_mii(ifr);
1827
1828         if (!netif_running(dev))
1829                 return -ENODEV;
1830
1831         switch (cmd) {
1832         case SIOCGMIIPHY:
1833                 data->phy_id = 32; /* Internal PHY */
1834                 return 0;
1835
1836         case SIOCGMIIREG:
1837                 data->val_out = mdio_read(tp->mmio_addr, data->reg_num & 0x1f);
1838                 return 0;
1839
1840         case SIOCSMIIREG:
1841                 if (!capable(CAP_NET_ADMIN))
1842                         return -EPERM;
1843                 mdio_write(tp->mmio_addr, data->reg_num & 0x1f, data->val_in);
1844                 return 0;
1845         }
1846         return -EOPNOTSUPP;
1847 }
1848
1849 static const struct rtl_cfg_info {
1850         void (*hw_start)(struct net_device *);
1851         unsigned int region;
1852         unsigned int align;
1853         u16 intr_event;
1854         u16 napi_event;
1855         unsigned features;
1856 } rtl_cfg_infos [] = {
1857         [RTL_CFG_0] = {
1858                 .hw_start       = rtl_hw_start_8169,
1859                 .region         = 1,
1860                 .align          = 0,
1861                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1862                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1863                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1864                 .features       = RTL_FEATURE_GMII
1865         },
1866         [RTL_CFG_1] = {
1867                 .hw_start       = rtl_hw_start_8168,
1868                 .region         = 2,
1869                 .align          = 8,
1870                 .intr_event     = SYSErr | LinkChg | RxOverflow |
1871                                   TxErr | TxOK | RxOK | RxErr,
1872                 .napi_event     = TxErr | TxOK | RxOK | RxOverflow,
1873                 .features       = RTL_FEATURE_GMII | RTL_FEATURE_MSI
1874         },
1875         [RTL_CFG_2] = {
1876                 .hw_start       = rtl_hw_start_8101,
1877                 .region         = 2,
1878                 .align          = 8,
1879                 .intr_event     = SYSErr | LinkChg | RxOverflow | PCSTimeout |
1880                                   RxFIFOOver | TxErr | TxOK | RxOK | RxErr,
1881                 .napi_event     = RxFIFOOver | TxErr | TxOK | RxOK | RxOverflow,
1882                 .features       = RTL_FEATURE_MSI
1883         }
1884 };
1885
1886 /* Cfg9346_Unlock assumed. */
1887 static unsigned rtl_try_msi(struct pci_dev *pdev, void __iomem *ioaddr,
1888                             const struct rtl_cfg_info *cfg)
1889 {
1890         unsigned msi = 0;
1891         u8 cfg2;
1892
1893         cfg2 = RTL_R8(Config2) & ~MSIEnable;
1894         if (cfg->features & RTL_FEATURE_MSI) {
1895                 if (pci_enable_msi(pdev)) {
1896                         dev_info(&pdev->dev, "no MSI. Back to INTx.\n");
1897                 } else {
1898                         cfg2 |= MSIEnable;
1899                         msi = RTL_FEATURE_MSI;
1900                 }
1901         }
1902         RTL_W8(Config2, cfg2);
1903         return msi;
1904 }
1905
1906 static void rtl_disable_msi(struct pci_dev *pdev, struct rtl8169_private *tp)
1907 {
1908         if (tp->features & RTL_FEATURE_MSI) {
1909                 pci_disable_msi(pdev);
1910                 tp->features &= ~RTL_FEATURE_MSI;
1911         }
1912 }
1913
1914 static int rtl_eeprom_read(struct pci_dev *pdev, int cap, int addr, __le32 *val)
1915 {
1916         int ret, count = 100;
1917         u16 status = 0;
1918         u32 value;
1919
1920         ret = pci_write_config_word(pdev, cap + PCI_VPD_ADDR, addr);
1921         if (ret < 0)
1922                 return ret;
1923
1924         do {
1925                 udelay(10);
1926                 ret = pci_read_config_word(pdev, cap + PCI_VPD_ADDR, &status);
1927                 if (ret < 0)
1928                         return ret;
1929         } while (!(status & PCI_VPD_ADDR_F) && --count);
1930
1931         if (!(status & PCI_VPD_ADDR_F))
1932                 return -ETIMEDOUT;
1933
1934         ret = pci_read_config_dword(pdev, cap + PCI_VPD_DATA, &value);
1935         if (ret < 0)
1936                 return ret;
1937
1938         *val = cpu_to_le32(value);
1939
1940         return 0;
1941 }
1942
1943 static void rtl_init_mac_address(struct rtl8169_private *tp,
1944                                  void __iomem *ioaddr)
1945 {
1946         struct pci_dev *pdev = tp->pci_dev;
1947         u8 cfg1;
1948         int vpd_cap;
1949         u8 mac[8];
1950         DECLARE_MAC_BUF(buf);
1951
1952         cfg1 = RTL_R8(Config1);
1953         if (!(cfg1  & VPD)) {
1954                 dprintk("VPD access not enabled, enabling\n");
1955                 RTL_W8(Cfg9346, Cfg9346_Unlock);
1956                 RTL_W8(Config1, cfg1 | VPD);
1957                 RTL_W8(Cfg9346, Cfg9346_Lock);
1958         }
1959
1960         vpd_cap = pci_find_capability(pdev, PCI_CAP_ID_VPD);
1961         if (!vpd_cap)
1962                 return;
1963
1964         /* MAC address is stored in EEPROM at offset 0x0e
1965          * Realtek says: "The VPD address does not have to be a DWORD-aligned
1966          * address as defined in the PCI 2.2 Specifications, but the VPD data
1967          * is always consecutive 4-byte data starting from the VPD address
1968          * specified."
1969          */
1970         if (rtl_eeprom_read(pdev, vpd_cap, 0x000e, (__le32*)&mac[0]) < 0 ||
1971             rtl_eeprom_read(pdev, vpd_cap, 0x0012, (__le32*)&mac[4]) < 0) {
1972                 dprintk("Reading MAC address from EEPROM failed\n");
1973                 return;
1974         }
1975
1976         dprintk("MAC address found in EEPROM: %s\n", print_mac(buf, mac));
1977
1978         /* Write MAC address */
1979         rtl_rar_set(tp, mac);
1980 }
1981
1982 static int __devinit
1983 rtl8169_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1984 {
1985         const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
1986         const unsigned int region = cfg->region;
1987         struct rtl8169_private *tp;
1988         struct mii_if_info *mii;
1989         struct net_device *dev;
1990         void __iomem *ioaddr;
1991         unsigned int i;
1992         int rc;
1993
1994         if (netif_msg_drv(&debug)) {
1995                 printk(KERN_INFO "%s Gigabit Ethernet driver %s loaded\n",
1996                        MODULENAME, RTL8169_VERSION);
1997         }
1998
1999         dev = alloc_etherdev(sizeof (*tp));
2000         if (!dev) {
2001                 if (netif_msg_drv(&debug))
2002                         dev_err(&pdev->dev, "unable to alloc new ethernet\n");
2003                 rc = -ENOMEM;
2004                 goto out;
2005         }
2006
2007         SET_NETDEV_DEV(dev, &pdev->dev);
2008         tp = netdev_priv(dev);
2009         tp->dev = dev;
2010         tp->pci_dev = pdev;
2011         tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
2012
2013         mii = &tp->mii;
2014         mii->dev = dev;
2015         mii->mdio_read = rtl_mdio_read;
2016         mii->mdio_write = rtl_mdio_write;
2017         mii->phy_id_mask = 0x1f;
2018         mii->reg_num_mask = 0x1f;
2019         mii->supports_gmii = !!(cfg->features & RTL_FEATURE_GMII);
2020
2021         /* enable device (incl. PCI PM wakeup and hotplug setup) */
2022         rc = pci_enable_device(pdev);
2023         if (rc < 0) {
2024                 if (netif_msg_probe(tp))
2025                         dev_err(&pdev->dev, "enable failure\n");
2026                 goto err_out_free_dev_1;
2027         }
2028
2029         rc = pci_set_mwi(pdev);
2030         if (rc < 0)
2031                 goto err_out_disable_2;
2032
2033         /* make sure PCI base addr 1 is MMIO */
2034         if (!(pci_resource_flags(pdev, region) & IORESOURCE_MEM)) {
2035                 if (netif_msg_probe(tp)) {
2036                         dev_err(&pdev->dev,
2037                                 "region #%d not an MMIO resource, aborting\n",
2038                                 region);
2039                 }
2040                 rc = -ENODEV;
2041                 goto err_out_mwi_3;
2042         }
2043
2044         /* check for weird/broken PCI region reporting */
2045         if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
2046                 if (netif_msg_probe(tp)) {
2047                         dev_err(&pdev->dev,
2048                                 "Invalid PCI region size(s), aborting\n");
2049                 }
2050                 rc = -ENODEV;
2051                 goto err_out_mwi_3;
2052         }
2053
2054         rc = pci_request_regions(pdev, MODULENAME);
2055         if (rc < 0) {
2056                 if (netif_msg_probe(tp))
2057                         dev_err(&pdev->dev, "could not request regions.\n");
2058                 goto err_out_mwi_3;
2059         }
2060
2061         tp->cp_cmd = PCIMulRW | RxChkSum;
2062
2063         if ((sizeof(dma_addr_t) > 4) &&
2064             !pci_set_dma_mask(pdev, DMA_64BIT_MASK) && use_dac) {
2065                 tp->cp_cmd |= PCIDAC;
2066                 dev->features |= NETIF_F_HIGHDMA;
2067         } else {
2068                 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
2069                 if (rc < 0) {
2070                         if (netif_msg_probe(tp)) {
2071                                 dev_err(&pdev->dev,
2072                                         "DMA configuration failed.\n");
2073                         }
2074                         goto err_out_free_res_4;
2075                 }
2076         }
2077
2078         pci_set_master(pdev);
2079
2080         /* ioremap MMIO region */
2081         ioaddr = ioremap(pci_resource_start(pdev, region), R8169_REGS_SIZE);
2082         if (!ioaddr) {
2083                 if (netif_msg_probe(tp))
2084                         dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
2085                 rc = -EIO;
2086                 goto err_out_free_res_4;
2087         }
2088
2089         tp->pcie_cap = pci_find_capability(pdev, PCI_CAP_ID_EXP);
2090         if (!tp->pcie_cap && netif_msg_probe(tp))
2091                 dev_info(&pdev->dev, "no PCI Express capability\n");
2092
2093         /* Unneeded ? Don't mess with Mrs. Murphy. */
2094         rtl8169_irq_mask_and_ack(ioaddr);
2095
2096         /* Soft reset the chip. */
2097         RTL_W8(ChipCmd, CmdReset);
2098
2099         /* Check that the chip has finished the reset. */
2100         for (i = 0; i < 100; i++) {
2101                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2102                         break;
2103                 msleep_interruptible(1);
2104         }
2105
2106         /* Identify chip attached to board */
2107         rtl8169_get_mac_version(tp, ioaddr);
2108
2109         rtl8169_print_mac_version(tp);
2110
2111         for (i = 0; i < ARRAY_SIZE(rtl_chip_info); i++) {
2112                 if (tp->mac_version == rtl_chip_info[i].mac_version)
2113                         break;
2114         }
2115         if (i == ARRAY_SIZE(rtl_chip_info)) {
2116                 /* Unknown chip: assume array element #0, original RTL-8169 */
2117                 if (netif_msg_probe(tp)) {
2118                         dev_printk(KERN_DEBUG, &pdev->dev,
2119                                 "unknown chip version, assuming %s\n",
2120                                 rtl_chip_info[0].name);
2121                 }
2122                 i = 0;
2123         }
2124         tp->chipset = i;
2125
2126         RTL_W8(Cfg9346, Cfg9346_Unlock);
2127         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
2128         RTL_W8(Config5, RTL_R8(Config5) & PMEStatus);
2129         if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
2130                 tp->features |= RTL_FEATURE_WOL;
2131         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
2132                 tp->features |= RTL_FEATURE_WOL;
2133         tp->features |= rtl_try_msi(pdev, ioaddr, cfg);
2134         RTL_W8(Cfg9346, Cfg9346_Lock);
2135
2136         if ((tp->mac_version <= RTL_GIGA_MAC_VER_06) &&
2137             (RTL_R8(PHYstatus) & TBI_Enable)) {
2138                 tp->set_speed = rtl8169_set_speed_tbi;
2139                 tp->get_settings = rtl8169_gset_tbi;
2140                 tp->phy_reset_enable = rtl8169_tbi_reset_enable;
2141                 tp->phy_reset_pending = rtl8169_tbi_reset_pending;
2142                 tp->link_ok = rtl8169_tbi_link_ok;
2143
2144                 tp->phy_1000_ctrl_reg = ADVERTISE_1000FULL; /* Implied by TBI */
2145         } else {
2146                 tp->set_speed = rtl8169_set_speed_xmii;
2147                 tp->get_settings = rtl8169_gset_xmii;
2148                 tp->phy_reset_enable = rtl8169_xmii_reset_enable;
2149                 tp->phy_reset_pending = rtl8169_xmii_reset_pending;
2150                 tp->link_ok = rtl8169_xmii_link_ok;
2151
2152                 dev->do_ioctl = rtl8169_ioctl;
2153         }
2154
2155         spin_lock_init(&tp->lock);
2156
2157         tp->mmio_addr = ioaddr;
2158
2159         rtl_init_mac_address(tp, ioaddr);
2160
2161         /* Get MAC address */
2162         for (i = 0; i < MAC_ADDR_LEN; i++)
2163                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
2164         memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
2165
2166         dev->open = rtl8169_open;
2167         dev->hard_start_xmit = rtl8169_start_xmit;
2168         dev->get_stats = rtl8169_get_stats;
2169         SET_ETHTOOL_OPS(dev, &rtl8169_ethtool_ops);
2170         dev->stop = rtl8169_close;
2171         dev->tx_timeout = rtl8169_tx_timeout;
2172         dev->set_multicast_list = rtl_set_rx_mode;
2173         dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
2174         dev->irq = pdev->irq;
2175         dev->base_addr = (unsigned long) ioaddr;
2176         dev->change_mtu = rtl8169_change_mtu;
2177         dev->set_mac_address = rtl_set_mac_address;
2178
2179         netif_napi_add(dev, &tp->napi, rtl8169_poll, R8169_NAPI_WEIGHT);
2180
2181 #ifdef CONFIG_R8169_VLAN
2182         dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
2183         dev->vlan_rx_register = rtl8169_vlan_rx_register;
2184 #endif
2185
2186 #ifdef CONFIG_NET_POLL_CONTROLLER
2187         dev->poll_controller = rtl8169_netpoll;
2188 #endif
2189
2190         tp->intr_mask = 0xffff;
2191         tp->align = cfg->align;
2192         tp->hw_start = cfg->hw_start;
2193         tp->intr_event = cfg->intr_event;
2194         tp->napi_event = cfg->napi_event;
2195
2196         init_timer(&tp->timer);
2197         tp->timer.data = (unsigned long) dev;
2198         tp->timer.function = rtl8169_phy_timer;
2199
2200         rc = register_netdev(dev);
2201         if (rc < 0)
2202                 goto err_out_msi_5;
2203
2204         pci_set_drvdata(pdev, dev);
2205
2206         if (netif_msg_probe(tp)) {
2207                 u32 xid = RTL_R32(TxConfig) & 0x7cf0f8ff;
2208
2209                 printk(KERN_INFO "%s: %s at 0x%lx, "
2210                        "%2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x, "
2211                        "XID %08x IRQ %d\n",
2212                        dev->name,
2213                        rtl_chip_info[tp->chipset].name,
2214                        dev->base_addr,
2215                        dev->dev_addr[0], dev->dev_addr[1],
2216                        dev->dev_addr[2], dev->dev_addr[3],
2217                        dev->dev_addr[4], dev->dev_addr[5], xid, dev->irq);
2218         }
2219
2220         rtl8169_init_phy(dev, tp);
2221         device_set_wakeup_enable(&pdev->dev, tp->features & RTL_FEATURE_WOL);
2222
2223 out:
2224         return rc;
2225
2226 err_out_msi_5:
2227         rtl_disable_msi(pdev, tp);
2228         iounmap(ioaddr);
2229 err_out_free_res_4:
2230         pci_release_regions(pdev);
2231 err_out_mwi_3:
2232         pci_clear_mwi(pdev);
2233 err_out_disable_2:
2234         pci_disable_device(pdev);
2235 err_out_free_dev_1:
2236         free_netdev(dev);
2237         goto out;
2238 }
2239
2240 static void __devexit rtl8169_remove_one(struct pci_dev *pdev)
2241 {
2242         struct net_device *dev = pci_get_drvdata(pdev);
2243         struct rtl8169_private *tp = netdev_priv(dev);
2244
2245         flush_scheduled_work();
2246
2247         unregister_netdev(dev);
2248         rtl_disable_msi(pdev, tp);
2249         rtl8169_release_board(pdev, dev, tp->mmio_addr);
2250         pci_set_drvdata(pdev, NULL);
2251 }
2252
2253 static void rtl8169_set_rxbufsize(struct rtl8169_private *tp,
2254                                   struct net_device *dev)
2255 {
2256         unsigned int mtu = dev->mtu;
2257
2258         tp->rx_buf_sz = (mtu > RX_BUF_SIZE) ? mtu + ETH_HLEN + 8 : RX_BUF_SIZE;
2259 }
2260
2261 static int rtl8169_open(struct net_device *dev)
2262 {
2263         struct rtl8169_private *tp = netdev_priv(dev);
2264         struct pci_dev *pdev = tp->pci_dev;
2265         int retval = -ENOMEM;
2266
2267
2268         rtl8169_set_rxbufsize(tp, dev);
2269
2270         /*
2271          * Rx and Tx desscriptors needs 256 bytes alignment.
2272          * pci_alloc_consistent provides more.
2273          */
2274         tp->TxDescArray = pci_alloc_consistent(pdev, R8169_TX_RING_BYTES,
2275                                                &tp->TxPhyAddr);
2276         if (!tp->TxDescArray)
2277                 goto out;
2278
2279         tp->RxDescArray = pci_alloc_consistent(pdev, R8169_RX_RING_BYTES,
2280                                                &tp->RxPhyAddr);
2281         if (!tp->RxDescArray)
2282                 goto err_free_tx_0;
2283
2284         retval = rtl8169_init_ring(dev);
2285         if (retval < 0)
2286                 goto err_free_rx_1;
2287
2288         INIT_DELAYED_WORK(&tp->task, NULL);
2289
2290         smp_mb();
2291
2292         retval = request_irq(dev->irq, rtl8169_interrupt,
2293                              (tp->features & RTL_FEATURE_MSI) ? 0 : IRQF_SHARED,
2294                              dev->name, dev);
2295         if (retval < 0)
2296                 goto err_release_ring_2;
2297
2298         napi_enable(&tp->napi);
2299
2300         rtl_hw_start(dev);
2301
2302         rtl8169_request_timer(dev);
2303
2304         rtl8169_check_link_status(dev, tp, tp->mmio_addr);
2305 out:
2306         return retval;
2307
2308 err_release_ring_2:
2309         rtl8169_rx_clear(tp);
2310 err_free_rx_1:
2311         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
2312                             tp->RxPhyAddr);
2313 err_free_tx_0:
2314         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
2315                             tp->TxPhyAddr);
2316         goto out;
2317 }
2318
2319 static void rtl8169_hw_reset(void __iomem *ioaddr)
2320 {
2321         /* Disable interrupts */
2322         rtl8169_irq_mask_and_ack(ioaddr);
2323
2324         /* Reset the chipset */
2325         RTL_W8(ChipCmd, CmdReset);
2326
2327         /* PCI commit */
2328         RTL_R8(ChipCmd);
2329 }
2330
2331 static void rtl_set_rx_tx_config_registers(struct rtl8169_private *tp)
2332 {
2333         void __iomem *ioaddr = tp->mmio_addr;
2334         u32 cfg = rtl8169_rx_config;
2335
2336         cfg |= (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
2337         RTL_W32(RxConfig, cfg);
2338
2339         /* Set DMA burst size and Interframe Gap Time */
2340         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2341                 (InterFrameGap << TxInterFrameGapShift));
2342 }
2343
2344 static void rtl_hw_start(struct net_device *dev)
2345 {
2346         struct rtl8169_private *tp = netdev_priv(dev);
2347         void __iomem *ioaddr = tp->mmio_addr;
2348         unsigned int i;
2349
2350         /* Soft reset the chip. */
2351         RTL_W8(ChipCmd, CmdReset);
2352
2353         /* Check that the chip has finished the reset. */
2354         for (i = 0; i < 100; i++) {
2355                 if ((RTL_R8(ChipCmd) & CmdReset) == 0)
2356                         break;
2357                 msleep_interruptible(1);
2358         }
2359
2360         tp->hw_start(dev);
2361
2362         netif_start_queue(dev);
2363 }
2364
2365
2366 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp,
2367                                          void __iomem *ioaddr)
2368 {
2369         /*
2370          * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
2371          * register to be written before TxDescAddrLow to work.
2372          * Switching from MMIO to I/O access fixes the issue as well.
2373          */
2374         RTL_W32(TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
2375         RTL_W32(TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_32BIT_MASK);
2376         RTL_W32(RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
2377         RTL_W32(RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_32BIT_MASK);
2378 }
2379
2380 static u16 rtl_rw_cpluscmd(void __iomem *ioaddr)
2381 {
2382         u16 cmd;
2383
2384         cmd = RTL_R16(CPlusCmd);
2385         RTL_W16(CPlusCmd, cmd);
2386         return cmd;
2387 }
2388
2389 static void rtl_set_rx_max_size(void __iomem *ioaddr)
2390 {
2391         /* Low hurts. Let's disable the filtering. */
2392         RTL_W16(RxMaxSize, 16383);
2393 }
2394
2395 static void rtl8169_set_magic_reg(void __iomem *ioaddr, unsigned mac_version)
2396 {
2397         struct {
2398                 u32 mac_version;
2399                 u32 clk;
2400                 u32 val;
2401         } cfg2_info [] = {
2402                 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
2403                 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
2404                 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
2405                 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
2406         }, *p = cfg2_info;
2407         unsigned int i;
2408         u32 clk;
2409
2410         clk = RTL_R8(Config2) & PCI_Clock_66MHz;
2411         for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
2412                 if ((p->mac_version == mac_version) && (p->clk == clk)) {
2413                         RTL_W32(0x7c, p->val);
2414                         break;
2415                 }
2416         }
2417 }
2418
2419 static void rtl_hw_start_8169(struct net_device *dev)
2420 {
2421         struct rtl8169_private *tp = netdev_priv(dev);
2422         void __iomem *ioaddr = tp->mmio_addr;
2423         struct pci_dev *pdev = tp->pci_dev;
2424
2425         if (tp->mac_version == RTL_GIGA_MAC_VER_05) {
2426                 RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) | PCIMulRW);
2427                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x08);
2428         }
2429
2430         RTL_W8(Cfg9346, Cfg9346_Unlock);
2431         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2432             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2433             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2434             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2435                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2436
2437         RTL_W8(EarlyTxThres, EarlyTxThld);
2438
2439         rtl_set_rx_max_size(ioaddr);
2440
2441         if ((tp->mac_version == RTL_GIGA_MAC_VER_01) ||
2442             (tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2443             (tp->mac_version == RTL_GIGA_MAC_VER_03) ||
2444             (tp->mac_version == RTL_GIGA_MAC_VER_04))
2445                 rtl_set_rx_tx_config_registers(tp);
2446
2447         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2448
2449         if ((tp->mac_version == RTL_GIGA_MAC_VER_02) ||
2450             (tp->mac_version == RTL_GIGA_MAC_VER_03)) {
2451                 dprintk("Set MAC Reg C+CR Offset 0xE0. "
2452                         "Bit-3 and bit-14 MUST be 1\n");
2453                 tp->cp_cmd |= (1 << 14);
2454         }
2455
2456         RTL_W16(CPlusCmd, tp->cp_cmd);
2457
2458         rtl8169_set_magic_reg(ioaddr, tp->mac_version);
2459
2460         /*
2461          * Undocumented corner. Supposedly:
2462          * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
2463          */
2464         RTL_W16(IntrMitigate, 0x0000);
2465
2466         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2467
2468         if ((tp->mac_version != RTL_GIGA_MAC_VER_01) &&
2469             (tp->mac_version != RTL_GIGA_MAC_VER_02) &&
2470             (tp->mac_version != RTL_GIGA_MAC_VER_03) &&
2471             (tp->mac_version != RTL_GIGA_MAC_VER_04)) {
2472                 RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2473                 rtl_set_rx_tx_config_registers(tp);
2474         }
2475
2476         RTL_W8(Cfg9346, Cfg9346_Lock);
2477
2478         /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
2479         RTL_R8(IntrMask);
2480
2481         RTL_W32(RxMissed, 0);
2482
2483         rtl_set_rx_mode(dev);
2484
2485         /* no early-rx interrupts */
2486         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2487
2488         /* Enable all known interrupts by setting the interrupt mask. */
2489         RTL_W16(IntrMask, tp->intr_event);
2490 }
2491
2492 static void rtl_tx_performance_tweak(struct pci_dev *pdev, u16 force)
2493 {
2494         struct net_device *dev = pci_get_drvdata(pdev);
2495         struct rtl8169_private *tp = netdev_priv(dev);
2496         int cap = tp->pcie_cap;
2497
2498         if (cap) {
2499                 u16 ctl;
2500
2501                 pci_read_config_word(pdev, cap + PCI_EXP_DEVCTL, &ctl);
2502                 ctl = (ctl & ~PCI_EXP_DEVCTL_READRQ) | force;
2503                 pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL, ctl);
2504         }
2505 }
2506
2507 static void rtl_csi_access_enable(void __iomem *ioaddr)
2508 {
2509         u32 csi;
2510
2511         csi = rtl_csi_read(ioaddr, 0x070c) & 0x00ffffff;
2512         rtl_csi_write(ioaddr, 0x070c, csi | 0x27000000);
2513 }
2514
2515 struct ephy_info {
2516         unsigned int offset;
2517         u16 mask;
2518         u16 bits;
2519 };
2520
2521 static void rtl_ephy_init(void __iomem *ioaddr, struct ephy_info *e, int len)
2522 {
2523         u16 w;
2524
2525         while (len-- > 0) {
2526                 w = (rtl_ephy_read(ioaddr, e->offset) & ~e->mask) | e->bits;
2527                 rtl_ephy_write(ioaddr, e->offset, w);
2528                 e++;
2529         }
2530 }
2531
2532 static void rtl_disable_clock_request(struct pci_dev *pdev)
2533 {
2534         struct net_device *dev = pci_get_drvdata(pdev);
2535         struct rtl8169_private *tp = netdev_priv(dev);
2536         int cap = tp->pcie_cap;
2537
2538         if (cap) {
2539                 u16 ctl;
2540
2541                 pci_read_config_word(pdev, cap + PCI_EXP_LNKCTL, &ctl);
2542                 ctl &= ~PCI_EXP_LNKCTL_CLKREQ_EN;
2543                 pci_write_config_word(pdev, cap + PCI_EXP_LNKCTL, ctl);
2544         }
2545 }
2546
2547 #define R8168_CPCMD_QUIRK_MASK (\
2548         EnableBist | \
2549         Mac_dbgo_oe | \
2550         Force_half_dup | \
2551         Force_rxflow_en | \
2552         Force_txflow_en | \
2553         Cxpl_dbg_sel | \
2554         ASF | \
2555         PktCntrDisable | \
2556         Mac_dbgo_sel)
2557
2558 static void rtl_hw_start_8168bb(void __iomem *ioaddr, struct pci_dev *pdev)
2559 {
2560         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2561
2562         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2563
2564         rtl_tx_performance_tweak(pdev,
2565                 (0x5 << MAX_READ_REQUEST_SHIFT) | PCI_EXP_DEVCTL_NOSNOOP_EN);
2566 }
2567
2568 static void rtl_hw_start_8168bef(void __iomem *ioaddr, struct pci_dev *pdev)
2569 {
2570         rtl_hw_start_8168bb(ioaddr, pdev);
2571
2572         RTL_W8(EarlyTxThres, EarlyTxThld);
2573
2574         RTL_W8(Config4, RTL_R8(Config4) & ~(1 << 0));
2575 }
2576
2577 static void __rtl_hw_start_8168cp(void __iomem *ioaddr, struct pci_dev *pdev)
2578 {
2579         RTL_W8(Config1, RTL_R8(Config1) | Speed_down);
2580
2581         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2582
2583         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2584
2585         rtl_disable_clock_request(pdev);
2586
2587         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2588 }
2589
2590 static void rtl_hw_start_8168cp_1(void __iomem *ioaddr, struct pci_dev *pdev)
2591 {
2592         static struct ephy_info e_info_8168cp[] = {
2593                 { 0x01, 0,      0x0001 },
2594                 { 0x02, 0x0800, 0x1000 },
2595                 { 0x03, 0,      0x0042 },
2596                 { 0x06, 0x0080, 0x0000 },
2597                 { 0x07, 0,      0x2000 }
2598         };
2599
2600         rtl_csi_access_enable(ioaddr);
2601
2602         rtl_ephy_init(ioaddr, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
2603
2604         __rtl_hw_start_8168cp(ioaddr, pdev);
2605 }
2606
2607 static void rtl_hw_start_8168cp_2(void __iomem *ioaddr, struct pci_dev *pdev)
2608 {
2609         rtl_csi_access_enable(ioaddr);
2610
2611         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2612
2613         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2614
2615         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2616 }
2617
2618 static void rtl_hw_start_8168cp_3(void __iomem *ioaddr, struct pci_dev *pdev)
2619 {
2620         rtl_csi_access_enable(ioaddr);
2621
2622         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2623
2624         /* Magic. */
2625         RTL_W8(DBG_REG, 0x20);
2626
2627         RTL_W8(EarlyTxThres, EarlyTxThld);
2628
2629         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2630
2631         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2632 }
2633
2634 static void rtl_hw_start_8168c_1(void __iomem *ioaddr, struct pci_dev *pdev)
2635 {
2636         static struct ephy_info e_info_8168c_1[] = {
2637                 { 0x02, 0x0800, 0x1000 },
2638                 { 0x03, 0,      0x0002 },
2639                 { 0x06, 0x0080, 0x0000 }
2640         };
2641
2642         rtl_csi_access_enable(ioaddr);
2643
2644         RTL_W8(DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
2645
2646         rtl_ephy_init(ioaddr, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
2647
2648         __rtl_hw_start_8168cp(ioaddr, pdev);
2649 }
2650
2651 static void rtl_hw_start_8168c_2(void __iomem *ioaddr, struct pci_dev *pdev)
2652 {
2653         static struct ephy_info e_info_8168c_2[] = {
2654                 { 0x01, 0,      0x0001 },
2655                 { 0x03, 0x0400, 0x0220 }
2656         };
2657
2658         rtl_csi_access_enable(ioaddr);
2659
2660         rtl_ephy_init(ioaddr, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
2661
2662         __rtl_hw_start_8168cp(ioaddr, pdev);
2663 }
2664
2665 static void rtl_hw_start_8168c_3(void __iomem *ioaddr, struct pci_dev *pdev)
2666 {
2667         rtl_hw_start_8168c_2(ioaddr, pdev);
2668 }
2669
2670 static void rtl_hw_start_8168c_4(void __iomem *ioaddr, struct pci_dev *pdev)
2671 {
2672         rtl_csi_access_enable(ioaddr);
2673
2674         __rtl_hw_start_8168cp(ioaddr, pdev);
2675 }
2676
2677 static void rtl_hw_start_8168d(void __iomem *ioaddr, struct pci_dev *pdev)
2678 {
2679         rtl_csi_access_enable(ioaddr);
2680
2681         rtl_disable_clock_request(pdev);
2682
2683         RTL_W8(EarlyTxThres, EarlyTxThld);
2684
2685         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2686
2687         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R8168_CPCMD_QUIRK_MASK);
2688 }
2689
2690 static void rtl_hw_start_8168(struct net_device *dev)
2691 {
2692         struct rtl8169_private *tp = netdev_priv(dev);
2693         void __iomem *ioaddr = tp->mmio_addr;
2694         struct pci_dev *pdev = tp->pci_dev;
2695
2696         RTL_W8(Cfg9346, Cfg9346_Unlock);
2697
2698         RTL_W8(EarlyTxThres, EarlyTxThld);
2699
2700         rtl_set_rx_max_size(ioaddr);
2701
2702         tp->cp_cmd |= RTL_R16(CPlusCmd) | PktCntrDisable | INTT_1;
2703
2704         RTL_W16(CPlusCmd, tp->cp_cmd);
2705
2706         RTL_W16(IntrMitigate, 0x5151);
2707
2708         /* Work around for RxFIFO overflow. */
2709         if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
2710                 tp->intr_event |= RxFIFOOver | PCSTimeout;
2711                 tp->intr_event &= ~RxOverflow;
2712         }
2713
2714         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2715
2716         rtl_set_rx_mode(dev);
2717
2718         RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
2719                 (InterFrameGap << TxInterFrameGapShift));
2720
2721         RTL_R8(IntrMask);
2722
2723         switch (tp->mac_version) {
2724         case RTL_GIGA_MAC_VER_11:
2725                 rtl_hw_start_8168bb(ioaddr, pdev);
2726         break;
2727
2728         case RTL_GIGA_MAC_VER_12:
2729         case RTL_GIGA_MAC_VER_17:
2730                 rtl_hw_start_8168bef(ioaddr, pdev);
2731         break;
2732
2733         case RTL_GIGA_MAC_VER_18:
2734                 rtl_hw_start_8168cp_1(ioaddr, pdev);
2735         break;
2736
2737         case RTL_GIGA_MAC_VER_19:
2738                 rtl_hw_start_8168c_1(ioaddr, pdev);
2739         break;
2740
2741         case RTL_GIGA_MAC_VER_20:
2742                 rtl_hw_start_8168c_2(ioaddr, pdev);
2743         break;
2744
2745         case RTL_GIGA_MAC_VER_21:
2746                 rtl_hw_start_8168c_3(ioaddr, pdev);
2747         break;
2748
2749         case RTL_GIGA_MAC_VER_22:
2750                 rtl_hw_start_8168c_4(ioaddr, pdev);
2751         break;
2752
2753         case RTL_GIGA_MAC_VER_23:
2754                 rtl_hw_start_8168cp_2(ioaddr, pdev);
2755         break;
2756
2757         case RTL_GIGA_MAC_VER_24:
2758                 rtl_hw_start_8168cp_3(ioaddr, pdev);
2759         break;
2760
2761         case RTL_GIGA_MAC_VER_25:
2762                 rtl_hw_start_8168d(ioaddr, pdev);
2763         break;
2764
2765         default:
2766                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
2767                         dev->name, tp->mac_version);
2768         break;
2769         }
2770
2771         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2772
2773         RTL_W8(Cfg9346, Cfg9346_Lock);
2774
2775         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xF000);
2776
2777         RTL_W16(IntrMask, tp->intr_event);
2778 }
2779
2780 #define R810X_CPCMD_QUIRK_MASK (\
2781         EnableBist | \
2782         Mac_dbgo_oe | \
2783         Force_half_dup | \
2784         Force_half_dup | \
2785         Force_txflow_en | \
2786         Cxpl_dbg_sel | \
2787         ASF | \
2788         PktCntrDisable | \
2789         PCIDAC | \
2790         PCIMulRW)
2791
2792 static void rtl_hw_start_8102e_1(void __iomem *ioaddr, struct pci_dev *pdev)
2793 {
2794         static struct ephy_info e_info_8102e_1[] = {
2795                 { 0x01, 0, 0x6e65 },
2796                 { 0x02, 0, 0x091f },
2797                 { 0x03, 0, 0xc2f9 },
2798                 { 0x06, 0, 0xafb5 },
2799                 { 0x07, 0, 0x0e00 },
2800                 { 0x19, 0, 0xec80 },
2801                 { 0x01, 0, 0x2e65 },
2802                 { 0x01, 0, 0x6e65 }
2803         };
2804         u8 cfg1;
2805
2806         rtl_csi_access_enable(ioaddr);
2807
2808         RTL_W8(DBG_REG, FIX_NAK_1);
2809
2810         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2811
2812         RTL_W8(Config1,
2813                LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
2814         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2815
2816         cfg1 = RTL_R8(Config1);
2817         if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
2818                 RTL_W8(Config1, cfg1 & ~LEDS0);
2819
2820         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2821
2822         rtl_ephy_init(ioaddr, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
2823 }
2824
2825 static void rtl_hw_start_8102e_2(void __iomem *ioaddr, struct pci_dev *pdev)
2826 {
2827         rtl_csi_access_enable(ioaddr);
2828
2829         rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
2830
2831         RTL_W8(Config1, MEMMAP | IOMAP | VPD | PMEnable);
2832         RTL_W8(Config3, RTL_R8(Config3) & ~Beacon_en);
2833
2834         RTL_W16(CPlusCmd, RTL_R16(CPlusCmd) & ~R810X_CPCMD_QUIRK_MASK);
2835 }
2836
2837 static void rtl_hw_start_8102e_3(void __iomem *ioaddr, struct pci_dev *pdev)
2838 {
2839         rtl_hw_start_8102e_2(ioaddr, pdev);
2840
2841         rtl_ephy_write(ioaddr, 0x03, 0xc2f9);
2842 }
2843
2844 static void rtl_hw_start_8101(struct net_device *dev)
2845 {
2846         struct rtl8169_private *tp = netdev_priv(dev);
2847         void __iomem *ioaddr = tp->mmio_addr;
2848         struct pci_dev *pdev = tp->pci_dev;
2849
2850         if ((tp->mac_version == RTL_GIGA_MAC_VER_13) ||
2851             (tp->mac_version == RTL_GIGA_MAC_VER_16)) {
2852                 int cap = tp->pcie_cap;
2853
2854                 if (cap) {
2855                         pci_write_config_word(pdev, cap + PCI_EXP_DEVCTL,
2856                                               PCI_EXP_DEVCTL_NOSNOOP_EN);
2857                 }
2858         }
2859
2860         switch (tp->mac_version) {
2861         case RTL_GIGA_MAC_VER_07:
2862                 rtl_hw_start_8102e_1(ioaddr, pdev);
2863                 break;
2864
2865         case RTL_GIGA_MAC_VER_08:
2866                 rtl_hw_start_8102e_3(ioaddr, pdev);
2867                 break;
2868
2869         case RTL_GIGA_MAC_VER_09:
2870                 rtl_hw_start_8102e_2(ioaddr, pdev);
2871                 break;
2872         }
2873
2874         RTL_W8(Cfg9346, Cfg9346_Unlock);
2875
2876         RTL_W8(EarlyTxThres, EarlyTxThld);
2877
2878         rtl_set_rx_max_size(ioaddr);
2879
2880         tp->cp_cmd |= rtl_rw_cpluscmd(ioaddr) | PCIMulRW;
2881
2882         RTL_W16(CPlusCmd, tp->cp_cmd);
2883
2884         RTL_W16(IntrMitigate, 0x0000);
2885
2886         rtl_set_rx_tx_desc_registers(tp, ioaddr);
2887
2888         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2889         rtl_set_rx_tx_config_registers(tp);
2890
2891         RTL_W8(Cfg9346, Cfg9346_Lock);
2892
2893         RTL_R8(IntrMask);
2894
2895         rtl_set_rx_mode(dev);
2896
2897         RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
2898
2899         RTL_W16(MultiIntr, RTL_R16(MultiIntr) & 0xf000);
2900
2901         RTL_W16(IntrMask, tp->intr_event);
2902 }
2903
2904 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
2905 {
2906         struct rtl8169_private *tp = netdev_priv(dev);
2907         int ret = 0;
2908
2909         if (new_mtu < ETH_ZLEN || new_mtu > SafeMtu)
2910                 return -EINVAL;
2911
2912         dev->mtu = new_mtu;
2913
2914         if (!netif_running(dev))
2915                 goto out;
2916
2917         rtl8169_down(dev);
2918
2919         rtl8169_set_rxbufsize(tp, dev);
2920
2921         ret = rtl8169_init_ring(dev);
2922         if (ret < 0)
2923                 goto out;
2924
2925         napi_enable(&tp->napi);
2926
2927         rtl_hw_start(dev);
2928
2929         rtl8169_request_timer(dev);
2930
2931 out:
2932         return ret;
2933 }
2934
2935 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
2936 {
2937         desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
2938         desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
2939 }
2940
2941 static void rtl8169_free_rx_skb(struct rtl8169_private *tp,
2942                                 struct sk_buff **sk_buff, struct RxDesc *desc)
2943 {
2944         struct pci_dev *pdev = tp->pci_dev;
2945
2946         pci_unmap_single(pdev, le64_to_cpu(desc->addr), tp->rx_buf_sz,
2947                          PCI_DMA_FROMDEVICE);
2948         dev_kfree_skb(*sk_buff);
2949         *sk_buff = NULL;
2950         rtl8169_make_unusable_by_asic(desc);
2951 }
2952
2953 static inline void rtl8169_mark_to_asic(struct RxDesc *desc, u32 rx_buf_sz)
2954 {
2955         u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
2956
2957         desc->opts1 = cpu_to_le32(DescOwn | eor | rx_buf_sz);
2958 }
2959
2960 static inline void rtl8169_map_to_asic(struct RxDesc *desc, dma_addr_t mapping,
2961                                        u32 rx_buf_sz)
2962 {
2963         desc->addr = cpu_to_le64(mapping);
2964         wmb();
2965         rtl8169_mark_to_asic(desc, rx_buf_sz);
2966 }
2967
2968 static struct sk_buff *rtl8169_alloc_rx_skb(struct pci_dev *pdev,
2969                                             struct net_device *dev,
2970                                             struct RxDesc *desc, int rx_buf_sz,
2971                                             unsigned int align)
2972 {
2973         struct sk_buff *skb;
2974         dma_addr_t mapping;
2975         unsigned int pad;
2976
2977         pad = align ? align : NET_IP_ALIGN;
2978
2979         skb = netdev_alloc_skb(dev, rx_buf_sz + pad);
2980         if (!skb)
2981                 goto err_out;
2982
2983         skb_reserve(skb, align ? ((pad - 1) & (unsigned long)skb->data) : pad);
2984
2985         mapping = pci_map_single(pdev, skb->data, rx_buf_sz,
2986                                  PCI_DMA_FROMDEVICE);
2987
2988         rtl8169_map_to_asic(desc, mapping, rx_buf_sz);
2989 out:
2990         return skb;
2991
2992 err_out:
2993         rtl8169_make_unusable_by_asic(desc);
2994         goto out;
2995 }
2996
2997 static void rtl8169_rx_clear(struct rtl8169_private *tp)
2998 {
2999         unsigned int i;
3000
3001         for (i = 0; i < NUM_RX_DESC; i++) {
3002                 if (tp->Rx_skbuff[i]) {
3003                         rtl8169_free_rx_skb(tp, tp->Rx_skbuff + i,
3004                                             tp->RxDescArray + i);
3005                 }
3006         }
3007 }
3008
3009 static u32 rtl8169_rx_fill(struct rtl8169_private *tp, struct net_device *dev,
3010                            u32 start, u32 end)
3011 {
3012         u32 cur;
3013
3014         for (cur = start; end - cur != 0; cur++) {
3015                 struct sk_buff *skb;
3016                 unsigned int i = cur % NUM_RX_DESC;
3017
3018                 WARN_ON((s32)(end - cur) < 0);
3019
3020                 if (tp->Rx_skbuff[i])
3021                         continue;
3022
3023                 skb = rtl8169_alloc_rx_skb(tp->pci_dev, dev,
3024                                            tp->RxDescArray + i,
3025                                            tp->rx_buf_sz, tp->align);
3026                 if (!skb)
3027                         break;
3028
3029                 tp->Rx_skbuff[i] = skb;
3030         }
3031         return cur - start;
3032 }
3033
3034 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
3035 {
3036         desc->opts1 |= cpu_to_le32(RingEnd);
3037 }
3038
3039 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
3040 {
3041         tp->dirty_tx = tp->dirty_rx = tp->cur_tx = tp->cur_rx = 0;
3042 }
3043
3044 static int rtl8169_init_ring(struct net_device *dev)
3045 {
3046         struct rtl8169_private *tp = netdev_priv(dev);
3047
3048         rtl8169_init_ring_indexes(tp);
3049
3050         memset(tp->tx_skb, 0x0, NUM_TX_DESC * sizeof(struct ring_info));
3051         memset(tp->Rx_skbuff, 0x0, NUM_RX_DESC * sizeof(struct sk_buff *));
3052
3053         if (rtl8169_rx_fill(tp, dev, 0, NUM_RX_DESC) != NUM_RX_DESC)
3054                 goto err_out;
3055
3056         rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
3057
3058         return 0;
3059
3060 err_out:
3061         rtl8169_rx_clear(tp);
3062         return -ENOMEM;
3063 }
3064
3065 static void rtl8169_unmap_tx_skb(struct pci_dev *pdev, struct ring_info *tx_skb,
3066                                  struct TxDesc *desc)
3067 {
3068         unsigned int len = tx_skb->len;
3069
3070         pci_unmap_single(pdev, le64_to_cpu(desc->addr), len, PCI_DMA_TODEVICE);
3071         desc->opts1 = 0x00;
3072         desc->opts2 = 0x00;
3073         desc->addr = 0x00;
3074         tx_skb->len = 0;
3075 }
3076
3077 static void rtl8169_tx_clear(struct rtl8169_private *tp)
3078 {
3079         unsigned int i;
3080
3081         for (i = tp->dirty_tx; i < tp->dirty_tx + NUM_TX_DESC; i++) {
3082                 unsigned int entry = i % NUM_TX_DESC;
3083                 struct ring_info *tx_skb = tp->tx_skb + entry;
3084                 unsigned int len = tx_skb->len;
3085
3086                 if (len) {
3087                         struct sk_buff *skb = tx_skb->skb;
3088
3089                         rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb,
3090                                              tp->TxDescArray + entry);
3091                         if (skb) {
3092                                 dev_kfree_skb(skb);
3093                                 tx_skb->skb = NULL;
3094                         }
3095                         tp->dev->stats.tx_dropped++;
3096                 }
3097         }
3098         tp->cur_tx = tp->dirty_tx = 0;
3099 }
3100
3101 static void rtl8169_schedule_work(struct net_device *dev, work_func_t task)
3102 {
3103         struct rtl8169_private *tp = netdev_priv(dev);
3104
3105         PREPARE_DELAYED_WORK(&tp->task, task);
3106         schedule_delayed_work(&tp->task, 4);
3107 }
3108
3109 static void rtl8169_wait_for_quiescence(struct net_device *dev)
3110 {
3111         struct rtl8169_private *tp = netdev_priv(dev);
3112         void __iomem *ioaddr = tp->mmio_addr;
3113
3114         synchronize_irq(dev->irq);
3115
3116         /* Wait for any pending NAPI task to complete */
3117         napi_disable(&tp->napi);
3118
3119         rtl8169_irq_mask_and_ack(ioaddr);
3120
3121         tp->intr_mask = 0xffff;
3122         RTL_W16(IntrMask, tp->intr_event);
3123         napi_enable(&tp->napi);
3124 }
3125
3126 static void rtl8169_reinit_task(struct work_struct *work)
3127 {
3128         struct rtl8169_private *tp =
3129                 container_of(work, struct rtl8169_private, task.work);
3130         struct net_device *dev = tp->dev;
3131         int ret;
3132
3133         rtnl_lock();
3134
3135         if (!netif_running(dev))
3136                 goto out_unlock;
3137
3138         rtl8169_wait_for_quiescence(dev);
3139         rtl8169_close(dev);
3140
3141         ret = rtl8169_open(dev);
3142         if (unlikely(ret < 0)) {
3143                 if (net_ratelimit() && netif_msg_drv(tp)) {
3144                         printk(KERN_ERR PFX "%s: reinit failure (status = %d)."
3145                                " Rescheduling.\n", dev->name, ret);
3146                 }
3147                 rtl8169_schedule_work(dev, rtl8169_reinit_task);
3148         }
3149
3150 out_unlock:
3151         rtnl_unlock();
3152 }
3153
3154 static void rtl8169_reset_task(struct work_struct *work)
3155 {
3156         struct rtl8169_private *tp =
3157                 container_of(work, struct rtl8169_private, task.work);
3158         struct net_device *dev = tp->dev;
3159
3160         rtnl_lock();
3161
3162         if (!netif_running(dev))
3163                 goto out_unlock;
3164
3165         rtl8169_wait_for_quiescence(dev);
3166
3167         rtl8169_rx_interrupt(dev, tp, tp->mmio_addr, ~(u32)0);
3168         rtl8169_tx_clear(tp);
3169
3170         if (tp->dirty_rx == tp->cur_rx) {
3171                 rtl8169_init_ring_indexes(tp);
3172                 rtl_hw_start(dev);
3173                 netif_wake_queue(dev);
3174                 rtl8169_check_link_status(dev, tp, tp->mmio_addr);
3175         } else {
3176                 if (net_ratelimit() && netif_msg_intr(tp)) {
3177                         printk(KERN_EMERG PFX "%s: Rx buffers shortage\n",
3178                                dev->name);
3179                 }
3180                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3181         }
3182
3183 out_unlock:
3184         rtnl_unlock();
3185 }
3186
3187 static void rtl8169_tx_timeout(struct net_device *dev)
3188 {
3189         struct rtl8169_private *tp = netdev_priv(dev);
3190
3191         rtl8169_hw_reset(tp->mmio_addr);
3192
3193         /* Let's wait a bit while any (async) irq lands on */
3194         rtl8169_schedule_work(dev, rtl8169_reset_task);
3195 }
3196
3197 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
3198                               u32 opts1)
3199 {
3200         struct skb_shared_info *info = skb_shinfo(skb);
3201         unsigned int cur_frag, entry;
3202         struct TxDesc * uninitialized_var(txd);
3203
3204         entry = tp->cur_tx;
3205         for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
3206                 skb_frag_t *frag = info->frags + cur_frag;
3207                 dma_addr_t mapping;
3208                 u32 status, len;
3209                 void *addr;
3210
3211                 entry = (entry + 1) % NUM_TX_DESC;
3212
3213                 txd = tp->TxDescArray + entry;
3214                 len = frag->size;
3215                 addr = ((void *) page_address(frag->page)) + frag->page_offset;
3216                 mapping = pci_map_single(tp->pci_dev, addr, len, PCI_DMA_TODEVICE);
3217
3218                 /* anti gcc 2.95.3 bugware (sic) */
3219                 status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3220
3221                 txd->opts1 = cpu_to_le32(status);
3222                 txd->addr = cpu_to_le64(mapping);
3223
3224                 tp->tx_skb[entry].len = len;
3225         }
3226
3227         if (cur_frag) {
3228                 tp->tx_skb[entry].skb = skb;
3229                 txd->opts1 |= cpu_to_le32(LastFrag);
3230         }
3231
3232         return cur_frag;
3233 }
3234
3235 static inline u32 rtl8169_tso_csum(struct sk_buff *skb, struct net_device *dev)
3236 {
3237         if (dev->features & NETIF_F_TSO) {
3238                 u32 mss = skb_shinfo(skb)->gso_size;
3239
3240                 if (mss)
3241                         return LargeSend | ((mss & MSSMask) << MSSShift);
3242         }
3243         if (skb->ip_summed == CHECKSUM_PARTIAL) {
3244                 const struct iphdr *ip = ip_hdr(skb);
3245
3246                 if (ip->protocol == IPPROTO_TCP)
3247                         return IPCS | TCPCS;
3248                 else if (ip->protocol == IPPROTO_UDP)
3249                         return IPCS | UDPCS;
3250                 WARN_ON(1);     /* we need a WARN() */
3251         }
3252         return 0;
3253 }
3254
3255 static int rtl8169_start_xmit(struct sk_buff *skb, struct net_device *dev)
3256 {
3257         struct rtl8169_private *tp = netdev_priv(dev);
3258         unsigned int frags, entry = tp->cur_tx % NUM_TX_DESC;
3259         struct TxDesc *txd = tp->TxDescArray + entry;
3260         void __iomem *ioaddr = tp->mmio_addr;
3261         dma_addr_t mapping;
3262         u32 status, len;
3263         u32 opts1;
3264         int ret = NETDEV_TX_OK;
3265
3266         if (unlikely(TX_BUFFS_AVAIL(tp) < skb_shinfo(skb)->nr_frags)) {
3267                 if (netif_msg_drv(tp)) {
3268                         printk(KERN_ERR
3269                                "%s: BUG! Tx Ring full when queue awake!\n",
3270                                dev->name);
3271                 }
3272                 goto err_stop;
3273         }
3274
3275         if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
3276                 goto err_stop;
3277
3278         opts1 = DescOwn | rtl8169_tso_csum(skb, dev);
3279
3280         frags = rtl8169_xmit_frags(tp, skb, opts1);
3281         if (frags) {
3282                 len = skb_headlen(skb);
3283                 opts1 |= FirstFrag;
3284         } else {
3285                 len = skb->len;
3286
3287                 if (unlikely(len < ETH_ZLEN)) {
3288                         if (skb_padto(skb, ETH_ZLEN))
3289                                 goto err_update_stats;
3290                         len = ETH_ZLEN;
3291                 }
3292
3293                 opts1 |= FirstFrag | LastFrag;
3294                 tp->tx_skb[entry].skb = skb;
3295         }
3296
3297         mapping = pci_map_single(tp->pci_dev, skb->data, len, PCI_DMA_TODEVICE);
3298
3299         tp->tx_skb[entry].len = len;
3300         txd->addr = cpu_to_le64(mapping);
3301         txd->opts2 = cpu_to_le32(rtl8169_tx_vlan_tag(tp, skb));
3302
3303         wmb();
3304
3305         /* anti gcc 2.95.3 bugware (sic) */
3306         status = opts1 | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
3307         txd->opts1 = cpu_to_le32(status);
3308
3309         dev->trans_start = jiffies;
3310
3311         tp->cur_tx += frags + 1;
3312
3313         smp_wmb();
3314
3315         RTL_W8(TxPoll, NPQ);    /* set polling bit */
3316
3317         if (TX_BUFFS_AVAIL(tp) < MAX_SKB_FRAGS) {
3318                 netif_stop_queue(dev);
3319                 smp_rmb();
3320                 if (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)
3321                         netif_wake_queue(dev);
3322         }
3323
3324 out:
3325         return ret;
3326
3327 err_stop:
3328         netif_stop_queue(dev);
3329         ret = NETDEV_TX_BUSY;
3330 err_update_stats:
3331         dev->stats.tx_dropped++;
3332         goto out;
3333 }
3334
3335 static void rtl8169_pcierr_interrupt(struct net_device *dev)
3336 {
3337         struct rtl8169_private *tp = netdev_priv(dev);
3338         struct pci_dev *pdev = tp->pci_dev;
3339         void __iomem *ioaddr = tp->mmio_addr;
3340         u16 pci_status, pci_cmd;
3341
3342         pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3343         pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3344
3345         if (netif_msg_intr(tp)) {
3346                 printk(KERN_ERR
3347                        "%s: PCI error (cmd = 0x%04x, status = 0x%04x).\n",
3348                        dev->name, pci_cmd, pci_status);
3349         }
3350
3351         /*
3352          * The recovery sequence below admits a very elaborated explanation:
3353          * - it seems to work;
3354          * - I did not see what else could be done;
3355          * - it makes iop3xx happy.
3356          *
3357          * Feel free to adjust to your needs.
3358          */
3359         if (pdev->broken_parity_status)
3360                 pci_cmd &= ~PCI_COMMAND_PARITY;
3361         else
3362                 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
3363
3364         pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
3365
3366         pci_write_config_word(pdev, PCI_STATUS,
3367                 pci_status & (PCI_STATUS_DETECTED_PARITY |
3368                 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
3369                 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
3370
3371         /* The infamous DAC f*ckup only happens at boot time */
3372         if ((tp->cp_cmd & PCIDAC) && !tp->dirty_rx && !tp->cur_rx) {
3373                 if (netif_msg_intr(tp))
3374                         printk(KERN_INFO "%s: disabling PCI DAC.\n", dev->name);
3375                 tp->cp_cmd &= ~PCIDAC;
3376                 RTL_W16(CPlusCmd, tp->cp_cmd);
3377                 dev->features &= ~NETIF_F_HIGHDMA;
3378         }
3379
3380         rtl8169_hw_reset(ioaddr);
3381
3382         rtl8169_schedule_work(dev, rtl8169_reinit_task);
3383 }
3384
3385 static void rtl8169_tx_interrupt(struct net_device *dev,
3386                                  struct rtl8169_private *tp,
3387                                  void __iomem *ioaddr)
3388 {
3389         unsigned int dirty_tx, tx_left;
3390
3391         dirty_tx = tp->dirty_tx;
3392         smp_rmb();
3393         tx_left = tp->cur_tx - dirty_tx;
3394
3395         while (tx_left > 0) {
3396                 unsigned int entry = dirty_tx % NUM_TX_DESC;
3397                 struct ring_info *tx_skb = tp->tx_skb + entry;
3398                 u32 len = tx_skb->len;
3399                 u32 status;
3400
3401                 rmb();
3402                 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
3403                 if (status & DescOwn)
3404                         break;
3405
3406                 dev->stats.tx_bytes += len;
3407                 dev->stats.tx_packets++;
3408
3409                 rtl8169_unmap_tx_skb(tp->pci_dev, tx_skb, tp->TxDescArray + entry);
3410
3411                 if (status & LastFrag) {
3412                         dev_kfree_skb_irq(tx_skb->skb);
3413                         tx_skb->skb = NULL;
3414                 }
3415                 dirty_tx++;
3416                 tx_left--;
3417         }
3418
3419         if (tp->dirty_tx != dirty_tx) {
3420                 tp->dirty_tx = dirty_tx;
3421                 smp_wmb();
3422                 if (netif_queue_stopped(dev) &&
3423                     (TX_BUFFS_AVAIL(tp) >= MAX_SKB_FRAGS)) {
3424                         netif_wake_queue(dev);
3425                 }
3426                 /*
3427                  * 8168 hack: TxPoll requests are lost when the Tx packets are
3428                  * too close. Let's kick an extra TxPoll request when a burst
3429                  * of start_xmit activity is detected (if it is not detected,
3430                  * it is slow enough). -- FR
3431                  */
3432                 smp_rmb();
3433                 if (tp->cur_tx != dirty_tx)
3434                         RTL_W8(TxPoll, NPQ);
3435         }
3436 }
3437
3438 static inline int rtl8169_fragmented_frame(u32 status)
3439 {
3440         return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
3441 }
3442
3443 static inline void rtl8169_rx_csum(struct sk_buff *skb, struct RxDesc *desc)
3444 {
3445         u32 opts1 = le32_to_cpu(desc->opts1);
3446         u32 status = opts1 & RxProtoMask;
3447
3448         if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
3449             ((status == RxProtoUDP) && !(opts1 & UDPFail)) ||
3450             ((status == RxProtoIP) && !(opts1 & IPFail)))
3451                 skb->ip_summed = CHECKSUM_UNNECESSARY;
3452         else
3453                 skb->ip_summed = CHECKSUM_NONE;
3454 }
3455
3456 static inline bool rtl8169_try_rx_copy(struct sk_buff **sk_buff,
3457                                        struct rtl8169_private *tp, int pkt_size,
3458                                        dma_addr_t addr)
3459 {
3460         struct sk_buff *skb;
3461         bool done = false;
3462
3463         if (pkt_size >= rx_copybreak)
3464                 goto out;
3465
3466         skb = netdev_alloc_skb(tp->dev, pkt_size + NET_IP_ALIGN);
3467         if (!skb)
3468                 goto out;
3469
3470         pci_dma_sync_single_for_cpu(tp->pci_dev, addr, pkt_size,
3471                                     PCI_DMA_FROMDEVICE);
3472         skb_reserve(skb, NET_IP_ALIGN);
3473         skb_copy_from_linear_data(*sk_buff, skb->data, pkt_size);
3474         *sk_buff = skb;
3475         done = true;
3476 out:
3477         return done;
3478 }
3479
3480 static int rtl8169_rx_interrupt(struct net_device *dev,
3481                                 struct rtl8169_private *tp,
3482                                 void __iomem *ioaddr, u32 budget)
3483 {
3484         unsigned int cur_rx, rx_left;
3485         unsigned int delta, count;
3486
3487         cur_rx = tp->cur_rx;
3488         rx_left = NUM_RX_DESC + tp->dirty_rx - cur_rx;
3489         rx_left = min(rx_left, budget);
3490
3491         for (; rx_left > 0; rx_left--, cur_rx++) {
3492                 unsigned int entry = cur_rx % NUM_RX_DESC;
3493                 struct RxDesc *desc = tp->RxDescArray + entry;
3494                 u32 status;
3495
3496                 rmb();
3497                 status = le32_to_cpu(desc->opts1);
3498
3499                 if (status & DescOwn)
3500                         break;
3501                 if (unlikely(status & RxRES)) {
3502                         if (netif_msg_rx_err(tp)) {
3503                                 printk(KERN_INFO
3504                                        "%s: Rx ERROR. status = %08x\n",
3505                                        dev->name, status);
3506                         }
3507                         dev->stats.rx_errors++;
3508                         if (status & (RxRWT | RxRUNT))
3509                                 dev->stats.rx_length_errors++;
3510                         if (status & RxCRC)
3511                                 dev->stats.rx_crc_errors++;
3512                         if (status & RxFOVF) {
3513                                 rtl8169_schedule_work(dev, rtl8169_reset_task);
3514                                 dev->stats.rx_fifo_errors++;
3515                         }
3516                         rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3517                 } else {
3518                         struct sk_buff *skb = tp->Rx_skbuff[entry];
3519                         dma_addr_t addr = le64_to_cpu(desc->addr);
3520                         int pkt_size = (status & 0x00001FFF) - 4;
3521                         struct pci_dev *pdev = tp->pci_dev;
3522
3523                         /*
3524                          * The driver does not support incoming fragmented
3525                          * frames. They are seen as a symptom of over-mtu
3526                          * sized frames.
3527                          */
3528                         if (unlikely(rtl8169_fragmented_frame(status))) {
3529                                 dev->stats.rx_dropped++;
3530                                 dev->stats.rx_length_errors++;
3531                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3532                                 continue;
3533                         }
3534
3535                         rtl8169_rx_csum(skb, desc);
3536
3537                         if (rtl8169_try_rx_copy(&skb, tp, pkt_size, addr)) {
3538                                 pci_dma_sync_single_for_device(pdev, addr,
3539                                         pkt_size, PCI_DMA_FROMDEVICE);
3540                                 rtl8169_mark_to_asic(desc, tp->rx_buf_sz);
3541                         } else {
3542                                 pci_unmap_single(pdev, addr, tp->rx_buf_sz,
3543                                                  PCI_DMA_FROMDEVICE);
3544                                 tp->Rx_skbuff[entry] = NULL;
3545                         }
3546
3547                         skb_put(skb, pkt_size);
3548                         skb->protocol = eth_type_trans(skb, dev);
3549
3550                         if (rtl8169_rx_vlan_skb(tp, desc, skb) < 0)
3551                                 netif_receive_skb(skb);
3552
3553                         dev->last_rx = jiffies;
3554                         dev->stats.rx_bytes += pkt_size;
3555                         dev->stats.rx_packets++;
3556                 }
3557
3558                 /* Work around for AMD plateform. */
3559                 if ((desc->opts2 & cpu_to_le32(0xfffe000)) &&
3560                     (tp->mac_version == RTL_GIGA_MAC_VER_05)) {
3561                         desc->opts2 = 0;
3562                         cur_rx++;
3563                 }
3564         }
3565
3566         count = cur_rx - tp->cur_rx;
3567         tp->cur_rx = cur_rx;
3568
3569         delta = rtl8169_rx_fill(tp, dev, tp->dirty_rx, tp->cur_rx);
3570         if (!delta && count && netif_msg_intr(tp))
3571                 printk(KERN_INFO "%s: no Rx buffer allocated\n", dev->name);
3572         tp->dirty_rx += delta;
3573
3574         /*
3575          * FIXME: until there is periodic timer to try and refill the ring,
3576          * a temporary shortage may definitely kill the Rx process.
3577          * - disable the asic to try and avoid an overflow and kick it again
3578          *   after refill ?
3579          * - how do others driver handle this condition (Uh oh...).
3580          */
3581         if ((tp->dirty_rx + NUM_RX_DESC == tp->cur_rx) && netif_msg_intr(tp))
3582                 printk(KERN_EMERG "%s: Rx buffers exhausted\n", dev->name);
3583
3584         return count;
3585 }
3586
3587 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
3588 {
3589         struct net_device *dev = dev_instance;
3590         struct rtl8169_private *tp = netdev_priv(dev);
3591         void __iomem *ioaddr = tp->mmio_addr;
3592         int handled = 0;
3593         int status;
3594
3595         status = RTL_R16(IntrStatus);
3596
3597         /* hotplug/major error/no more work/shared irq */
3598         if ((status == 0xffff) || !status)
3599                 goto out;
3600
3601         handled = 1;
3602
3603         if (unlikely(!netif_running(dev))) {
3604                 rtl8169_asic_down(ioaddr);
3605                 goto out;
3606         }
3607
3608         status &= tp->intr_mask;
3609         RTL_W16(IntrStatus,
3610                 (status & RxFIFOOver) ? (status | RxOverflow) : status);
3611
3612         if (!(status & tp->intr_event))
3613                 goto out;
3614
3615         /* Work around for rx fifo overflow */
3616         if (unlikely(status & RxFIFOOver) &&
3617             (tp->mac_version == RTL_GIGA_MAC_VER_11)) {
3618                 netif_stop_queue(dev);
3619                 rtl8169_tx_timeout(dev);
3620                 goto out;
3621         }
3622
3623         if (unlikely(status & SYSErr)) {
3624                 rtl8169_pcierr_interrupt(dev);
3625                 goto out;
3626         }
3627
3628         if (status & LinkChg)
3629                 rtl8169_check_link_status(dev, tp, ioaddr);
3630
3631         if (status & tp->napi_event) {
3632                 RTL_W16(IntrMask, tp->intr_event & ~tp->napi_event);
3633                 tp->intr_mask = ~tp->napi_event;
3634
3635                 if (likely(netif_rx_schedule_prep(dev, &tp->napi)))
3636                         __netif_rx_schedule(dev, &tp->napi);
3637                 else if (netif_msg_intr(tp)) {
3638                         printk(KERN_INFO "%s: interrupt %04x in poll\n",
3639                                dev->name, status);
3640                 }
3641         }
3642 out:
3643         return IRQ_RETVAL(handled);
3644 }
3645
3646 static int rtl8169_poll(struct napi_struct *napi, int budget)
3647 {
3648         struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
3649         struct net_device *dev = tp->dev;
3650         void __iomem *ioaddr = tp->mmio_addr;
3651         int work_done;
3652
3653         work_done = rtl8169_rx_interrupt(dev, tp, ioaddr, (u32) budget);
3654         rtl8169_tx_interrupt(dev, tp, ioaddr);
3655
3656         if (work_done < budget) {
3657                 netif_rx_complete(dev, napi);
3658                 tp->intr_mask = 0xffff;
3659                 /*
3660                  * 20040426: the barrier is not strictly required but the
3661                  * behavior of the irq handler could be less predictable
3662                  * without it. Btw, the lack of flush for the posted pci
3663                  * write is safe - FR
3664                  */
3665                 smp_wmb();
3666                 RTL_W16(IntrMask, tp->intr_event);
3667         }
3668
3669         return work_done;
3670 }
3671
3672 static void rtl8169_rx_missed(struct net_device *dev, void __iomem *ioaddr)
3673 {
3674         struct rtl8169_private *tp = netdev_priv(dev);
3675
3676         if (tp->mac_version > RTL_GIGA_MAC_VER_06)
3677                 return;
3678
3679         dev->stats.rx_missed_errors += (RTL_R32(RxMissed) & 0xffffff);
3680         RTL_W32(RxMissed, 0);
3681 }
3682
3683 static void rtl8169_down(struct net_device *dev)
3684 {
3685         struct rtl8169_private *tp = netdev_priv(dev);
3686         void __iomem *ioaddr = tp->mmio_addr;
3687         unsigned int intrmask;
3688
3689         rtl8169_delete_timer(dev);
3690
3691         netif_stop_queue(dev);
3692
3693         napi_disable(&tp->napi);
3694
3695 core_down:
3696         spin_lock_irq(&tp->lock);
3697
3698         rtl8169_asic_down(ioaddr);
3699
3700         rtl8169_rx_missed(dev, ioaddr);
3701
3702         spin_unlock_irq(&tp->lock);
3703
3704         synchronize_irq(dev->irq);
3705
3706         /* Give a racing hard_start_xmit a few cycles to complete. */
3707         synchronize_sched();  /* FIXME: should this be synchronize_irq()? */
3708
3709         /*
3710          * And now for the 50k$ question: are IRQ disabled or not ?
3711          *
3712          * Two paths lead here:
3713          * 1) dev->close
3714          *    -> netif_running() is available to sync the current code and the
3715          *       IRQ handler. See rtl8169_interrupt for details.
3716          * 2) dev->change_mtu
3717          *    -> rtl8169_poll can not be issued again and re-enable the
3718          *       interruptions. Let's simply issue the IRQ down sequence again.
3719          *
3720          * No loop if hotpluged or major error (0xffff).
3721          */
3722         intrmask = RTL_R16(IntrMask);
3723         if (intrmask && (intrmask != 0xffff))
3724                 goto core_down;
3725
3726         rtl8169_tx_clear(tp);
3727
3728         rtl8169_rx_clear(tp);
3729 }
3730
3731 static int rtl8169_close(struct net_device *dev)
3732 {
3733         struct rtl8169_private *tp = netdev_priv(dev);
3734         struct pci_dev *pdev = tp->pci_dev;
3735
3736         rtl8169_down(dev);
3737
3738         free_irq(dev->irq, dev);
3739
3740         pci_free_consistent(pdev, R8169_RX_RING_BYTES, tp->RxDescArray,
3741                             tp->RxPhyAddr);
3742         pci_free_consistent(pdev, R8169_TX_RING_BYTES, tp->TxDescArray,
3743                             tp->TxPhyAddr);
3744         tp->TxDescArray = NULL;
3745         tp->RxDescArray = NULL;
3746
3747         return 0;
3748 }
3749
3750 static void rtl_set_rx_mode(struct net_device *dev)
3751 {
3752         struct rtl8169_private *tp = netdev_priv(dev);
3753         void __iomem *ioaddr = tp->mmio_addr;
3754         unsigned long flags;
3755         u32 mc_filter[2];       /* Multicast hash filter */
3756         int rx_mode;
3757         u32 tmp = 0;
3758
3759         if (dev->flags & IFF_PROMISC) {
3760                 /* Unconditionally log net taps. */
3761                 if (netif_msg_link(tp)) {
3762                         printk(KERN_NOTICE "%s: Promiscuous mode enabled.\n",
3763                                dev->name);
3764                 }
3765                 rx_mode =
3766                     AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
3767                     AcceptAllPhys;
3768                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3769         } else if ((dev->mc_count > multicast_filter_limit)
3770                    || (dev->flags & IFF_ALLMULTI)) {
3771                 /* Too many to filter perfectly -- accept all multicasts. */
3772                 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
3773                 mc_filter[1] = mc_filter[0] = 0xffffffff;
3774         } else {
3775                 struct dev_mc_list *mclist;
3776                 unsigned int i;
3777
3778                 rx_mode = AcceptBroadcast | AcceptMyPhys;
3779                 mc_filter[1] = mc_filter[0] = 0;
3780                 for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
3781                      i++, mclist = mclist->next) {
3782                         int bit_nr = ether_crc(ETH_ALEN, mclist->dmi_addr) >> 26;
3783                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
3784                         rx_mode |= AcceptMulticast;
3785                 }
3786         }
3787
3788         spin_lock_irqsave(&tp->lock, flags);
3789
3790         tmp = rtl8169_rx_config | rx_mode |
3791               (RTL_R32(RxConfig) & rtl_chip_info[tp->chipset].RxConfigMask);
3792
3793         if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
3794                 u32 data = mc_filter[0];
3795
3796                 mc_filter[0] = swab32(mc_filter[1]);
3797                 mc_filter[1] = swab32(data);
3798         }
3799
3800         RTL_W32(MAR0 + 0, mc_filter[0]);
3801         RTL_W32(MAR0 + 4, mc_filter[1]);
3802
3803         RTL_W32(RxConfig, tmp);
3804
3805         spin_unlock_irqrestore(&tp->lock, flags);
3806 }
3807
3808 /**
3809  *  rtl8169_get_stats - Get rtl8169 read/write statistics
3810  *  @dev: The Ethernet Device to get statistics for
3811  *
3812  *  Get TX/RX statistics for rtl8169
3813  */
3814 static struct net_device_stats *rtl8169_get_stats(struct net_device *dev)
3815 {
3816         struct rtl8169_private *tp = netdev_priv(dev);
3817         void __iomem *ioaddr = tp->mmio_addr;
3818         unsigned long flags;
3819
3820         if (netif_running(dev)) {
3821                 spin_lock_irqsave(&tp->lock, flags);
3822                 rtl8169_rx_missed(dev, ioaddr);
3823                 spin_unlock_irqrestore(&tp->lock, flags);
3824         }
3825
3826         return &dev->stats;
3827 }
3828
3829 #ifdef CONFIG_PM
3830
3831 static int rtl8169_suspend(struct pci_dev *pdev, pm_message_t state)
3832 {
3833         struct net_device *dev = pci_get_drvdata(pdev);
3834         struct rtl8169_private *tp = netdev_priv(dev);
3835         void __iomem *ioaddr = tp->mmio_addr;
3836
3837         if (!netif_running(dev))
3838                 goto out_pci_suspend;
3839
3840         netif_device_detach(dev);
3841         netif_stop_queue(dev);
3842
3843         spin_lock_irq(&tp->lock);
3844
3845         rtl8169_asic_down(ioaddr);
3846
3847         rtl8169_rx_missed(dev, ioaddr);
3848
3849         spin_unlock_irq(&tp->lock);
3850
3851 out_pci_suspend:
3852         pci_save_state(pdev);
3853         pci_enable_wake(pdev, pci_choose_state(pdev, state),
3854                 (tp->features & RTL_FEATURE_WOL) ? 1 : 0);
3855         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3856
3857         return 0;
3858 }
3859
3860 static int rtl8169_resume(struct pci_dev *pdev)
3861 {
3862         struct net_device *dev = pci_get_drvdata(pdev);
3863
3864         pci_set_power_state(pdev, PCI_D0);
3865         pci_restore_state(pdev);
3866         pci_enable_wake(pdev, PCI_D0, 0);
3867
3868         if (!netif_running(dev))
3869                 goto out;
3870
3871         netif_device_attach(dev);
3872
3873         rtl8169_schedule_work(dev, rtl8169_reset_task);
3874 out:
3875         return 0;
3876 }
3877
3878 static void rtl_shutdown(struct pci_dev *pdev)
3879 {
3880         rtl8169_suspend(pdev, PMSG_SUSPEND);
3881 }
3882
3883 #endif /* CONFIG_PM */
3884
3885 static struct pci_driver rtl8169_pci_driver = {
3886         .name           = MODULENAME,
3887         .id_table       = rtl8169_pci_tbl,
3888         .probe          = rtl8169_init_one,
3889         .remove         = __devexit_p(rtl8169_remove_one),
3890 #ifdef CONFIG_PM
3891         .suspend        = rtl8169_suspend,
3892         .resume         = rtl8169_resume,
3893         .shutdown       = rtl_shutdown,
3894 #endif
3895 };
3896
3897 static int __init rtl8169_init_module(void)
3898 {
3899         return pci_register_driver(&rtl8169_pci_driver);
3900 }
3901
3902 static void __exit rtl8169_cleanup_module(void)
3903 {
3904         pci_unregister_driver(&rtl8169_pci_driver);
3905 }
3906
3907 module_init(rtl8169_init_module);
3908 module_exit(rtl8169_cleanup_module);