drivers/net/qlge/qlge_main.c

   1 /*
   2  * QLogic qlge NIC HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  * See LICENSE.qlge for copyright and licensing details.
   5  * Author:     Linux qlge network device driver by
   6  *                      Ron Mercer <ron.mercer@qlogic.com>
   7  */
   8 #include <linux/kernel.h>
   9 #include <linux/init.h>
  10 #include <linux/types.h>
  11 #include <linux/module.h>
  12 #include <linux/list.h>
  13 #include <linux/pci.h>
  14 #include <linux/dma-mapping.h>
  15 #include <linux/pagemap.h>
  16 #include <linux/sched.h>
  17 #include <linux/slab.h>
  18 #include <linux/dmapool.h>
  19 #include <linux/mempool.h>
  20 #include <linux/spinlock.h>
  21 #include <linux/kthread.h>
  22 #include <linux/interrupt.h>
  23 #include <linux/errno.h>
  24 #include <linux/ioport.h>
  25 #include <linux/in.h>
  26 #include <linux/ip.h>
  27 #include <linux/ipv6.h>
  28 #include <net/ipv6.h>
  29 #include <linux/tcp.h>
  30 #include <linux/udp.h>
  31 #include <linux/if_arp.h>
  32 #include <linux/if_ether.h>
  33 #include <linux/netdevice.h>
  34 #include <linux/etherdevice.h>
  35 #include <linux/ethtool.h>
  36 #include <linux/skbuff.h>
  37 #include <linux/rtnetlink.h>
  38 #include <linux/if_vlan.h>
  39 #include <linux/delay.h>
  40 #include <linux/mm.h>
  41 #include <linux/vmalloc.h>
  42 #include <net/ip6_checksum.h>
  43
  44 #include "qlge.h"
  45
  46 char qlge_driver_name[] = DRV_NAME;
  47 const char qlge_driver_version[] = DRV_VERSION;
  48
  49 MODULE_AUTHOR("Ron Mercer <ron.mercer@qlogic.com>");
  50 MODULE_DESCRIPTION(DRV_STRING " ");
  51 MODULE_LICENSE("GPL");
  52 MODULE_VERSION(DRV_VERSION);
  53
  54 static const u32 default_msg =
  55     NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK |
  56 /* NETIF_MSG_TIMER |    */
  57     NETIF_MSG_IFDOWN |
  58     NETIF_MSG_IFUP |
  59     NETIF_MSG_RX_ERR |
  60     NETIF_MSG_TX_ERR |
  61 /*  NETIF_MSG_TX_QUEUED | */
  62 /*  NETIF_MSG_INTR | NETIF_MSG_TX_DONE | NETIF_MSG_RX_STATUS | */
  63 /* NETIF_MSG_PKTDATA | */
  64     NETIF_MSG_HW | NETIF_MSG_WOL | 0;
  65
  66 static int debug = 0x00007fff;  /* defaults above */
  67 module_param(debug, int, 0);
  68 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
  69
  70 #define MSIX_IRQ 0
  71 #define MSI_IRQ 1
  72 #define LEG_IRQ 2
  73 static int irq_type = MSIX_IRQ;
  74 module_param(irq_type, int, MSIX_IRQ);
  75 MODULE_PARM_DESC(irq_type, "0 = MSI-X, 1 = MSI, 2 = Legacy.");
  76
  77 static struct pci_device_id qlge_pci_tbl[] __devinitdata = {
  78         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8012)},
  79         {PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, QLGE_DEVICE_ID_8000)},
  80         /* required last entry */
  81         {0,}
  82 };
  83
  84 MODULE_DEVICE_TABLE(pci, qlge_pci_tbl);
  85
  86 /* This hardware semaphore causes exclusive access to
  87  * resources shared between the NIC driver, MPI firmware,
  88  * FCOE firmware and the FC driver.
  89  */
  90 static int ql_sem_trylock(struct ql_adapter *qdev, u32 sem_mask)
  91 {
  92         u32 sem_bits = 0;
  93
  94         switch (sem_mask) {
  95         case SEM_XGMAC0_MASK:
  96                 sem_bits = SEM_SET << SEM_XGMAC0_SHIFT;
  97                 break;
  98         case SEM_XGMAC1_MASK:
  99                 sem_bits = SEM_SET << SEM_XGMAC1_SHIFT;
 100                 break;
 101         case SEM_ICB_MASK:
 102                 sem_bits = SEM_SET << SEM_ICB_SHIFT;
 103                 break;
 104         case SEM_MAC_ADDR_MASK:
 105                 sem_bits = SEM_SET << SEM_MAC_ADDR_SHIFT;
 106                 break;
 107         case SEM_FLASH_MASK:
 108                 sem_bits = SEM_SET << SEM_FLASH_SHIFT;
 109                 break;
 110         case SEM_PROBE_MASK:
 111                 sem_bits = SEM_SET << SEM_PROBE_SHIFT;
 112                 break;
 113         case SEM_RT_IDX_MASK:
 114                 sem_bits = SEM_SET << SEM_RT_IDX_SHIFT;
 115                 break;
 116         case SEM_PROC_REG_MASK:
 117                 sem_bits = SEM_SET << SEM_PROC_REG_SHIFT;
 118                 break;
 119         default:
 120                 QPRINTK(qdev, PROBE, ALERT, "Bad Semaphore mask!.\n");
 121                 return -EINVAL;
 122         }
 123
 124         ql_write32(qdev, SEM, sem_bits | sem_mask);
 125         return !(ql_read32(qdev, SEM) & sem_bits);
 126 }
 127
 128 int ql_sem_spinlock(struct ql_adapter *qdev, u32 sem_mask)
 129 {
 130         unsigned int wait_count = 30;
 131         do {
 132                 if (!ql_sem_trylock(qdev, sem_mask))
 133                         return 0;
 134                 udelay(100);
 135         } while (--wait_count);
 136         return -ETIMEDOUT;
 137 }
 138
 139 void ql_sem_unlock(struct ql_adapter *qdev, u32 sem_mask)
 140 {
 141         ql_write32(qdev, SEM, sem_mask);
 142         ql_read32(qdev, SEM);   /* flush */
 143 }
 144
 145 /* This function waits for a specific bit to come ready
 146  * in a given register.  It is used mostly by the initialize
 147  * process, but is also used in kernel thread API such as
 148  * netdev->set_multi, netdev->set_mac_address, netdev->vlan_rx_add_vid.
 149  */
 150 int ql_wait_reg_rdy(struct ql_adapter *qdev, u32 reg, u32 bit, u32 err_bit)
 151 {
 152         u32 temp;
 153         int count = UDELAY_COUNT;
 154
 155         while (count) {
 156                 temp = ql_read32(qdev, reg);
 157
 158                 /* check for errors */
 159                 if (temp & err_bit) {
 160                         QPRINTK(qdev, PROBE, ALERT,
 161                                 "register 0x%.08x access error, value = 0x%.08x!.\n",
 162                                 reg, temp);
 163                         return -EIO;
 164                 } else if (temp & bit)
 165                         return 0;
 166                 udelay(UDELAY_DELAY);
 167                 count--;
 168         }
 169         QPRINTK(qdev, PROBE, ALERT,
 170                 "Timed out waiting for reg %x to come ready.\n", reg);
 171         return -ETIMEDOUT;
 172 }
 173
 174 /* The CFG register is used to download TX and RX control blocks
 175  * to the chip. This function waits for an operation to complete.
 176  */
 177 static int ql_wait_cfg(struct ql_adapter *qdev, u32 bit)
 178 {
 179         int count = UDELAY_COUNT;
 180         u32 temp;
 181
 182         while (count) {
 183                 temp = ql_read32(qdev, CFG);
 184                 if (temp & CFG_LE)
 185                         return -EIO;
 186                 if (!(temp & bit))
 187                         return 0;
 188                 udelay(UDELAY_DELAY);
 189                 count--;
 190         }
 191         return -ETIMEDOUT;
 192 }
 193
 194
 195 /* Used to issue init control blocks to hw. Maps control block,
 196  * sets address, triggers download, waits for completion.
 197  */
 198 int ql_write_cfg(struct ql_adapter *qdev, void *ptr, int size, u32 bit,
 199                  u16 q_id)
 200 {
 201         u64 map;
 202         int status = 0;
 203         int direction;
 204         u32 mask;
 205         u32 value;
 206
 207         direction =
 208             (bit & (CFG_LRQ | CFG_LR | CFG_LCQ)) ? PCI_DMA_TODEVICE :
 209             PCI_DMA_FROMDEVICE;
 210
 211         map = pci_map_single(qdev->pdev, ptr, size, direction);
 212         if (pci_dma_mapping_error(qdev->pdev, map)) {
 213                 QPRINTK(qdev, IFUP, ERR, "Couldn't map DMA area.\n");
 214                 return -ENOMEM;
 215         }
 216
 217         status = ql_wait_cfg(qdev, bit);
 218         if (status) {
 219                 QPRINTK(qdev, IFUP, ERR,
 220                         "Timed out waiting for CFG to come ready.\n");
 221                 goto exit;
 222         }
 223
 224         status = ql_sem_spinlock(qdev, SEM_ICB_MASK);
 225         if (status)
 226                 goto exit;
 227         ql_write32(qdev, ICB_L, (u32) map);
 228         ql_write32(qdev, ICB_H, (u32) (map >> 32));
 229         ql_sem_unlock(qdev, SEM_ICB_MASK);      /* does flush too */
 230
 231         mask = CFG_Q_MASK | (bit << 16);
 232         value = bit | (q_id << CFG_Q_SHIFT);
 233         ql_write32(qdev, CFG, (mask | value));
 234
 235         /*
 236          * Wait for the bit to clear after signaling hw.
 237          */
 238         status = ql_wait_cfg(qdev, bit);
 239 exit:
 240         pci_unmap_single(qdev->pdev, map, size, direction);
 241         return status;
 242 }
 243
 244 /* Get a specific MAC address from the CAM.  Used for debug and reg dump. */
 245 int ql_get_mac_addr_reg(struct ql_adapter *qdev, u32 type, u16 index,
 246                         u32 *value)
 247 {
 248         u32 offset = 0;
 249         int status;
 250
 251         switch (type) {
 252         case MAC_ADDR_TYPE_MULTI_MAC:
 253         case MAC_ADDR_TYPE_CAM_MAC:
 254                 {
 255                         status =
 256                             ql_wait_reg_rdy(qdev,
 257                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 258                         if (status)
 259                                 goto exit;
 260                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 261                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 262                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 263                         status =
 264                             ql_wait_reg_rdy(qdev,
 265                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 266                         if (status)
 267                                 goto exit;
 268                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 269                         status =
 270                             ql_wait_reg_rdy(qdev,
 271                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 272                         if (status)
 273                                 goto exit;
 274                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 275                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 276                                    MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 277                         status =
 278                             ql_wait_reg_rdy(qdev,
 279                                 MAC_ADDR_IDX, MAC_ADDR_MR, 0);
 280                         if (status)
 281                                 goto exit;
 282                         *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 283                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 284                                 status =
 285                                     ql_wait_reg_rdy(qdev,
 286                                         MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 287                                 if (status)
 288                                         goto exit;
 289                                 ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 290                                            (index << MAC_ADDR_IDX_SHIFT) | /* index */
 291                                            MAC_ADDR_ADR | MAC_ADDR_RS | type); /* type */
 292                                 status =
 293                                     ql_wait_reg_rdy(qdev, MAC_ADDR_IDX,
 294                                                     MAC_ADDR_MR, 0);
 295                                 if (status)
 296                                         goto exit;
 297                                 *value++ = ql_read32(qdev, MAC_ADDR_DATA);
 298                         }
 299                         break;
 300                 }
 301         case MAC_ADDR_TYPE_VLAN:
 302         case MAC_ADDR_TYPE_MULTI_FLTR:
 303         default:
 304                 QPRINTK(qdev, IFUP, CRIT,
 305                         "Address type %d not yet supported.\n", type);
 306                 status = -EPERM;
 307         }
 308 exit:
 309         return status;
 310 }
 311
 312 /* Set up a MAC, multicast or VLAN address for the
 313  * inbound frame matching.
 314  */
 315 static int ql_set_mac_addr_reg(struct ql_adapter *qdev, u8 *addr, u32 type,
 316                                u16 index)
 317 {
 318         u32 offset = 0;
 319         int status = 0;
 320
 321         switch (type) {
 322         case MAC_ADDR_TYPE_MULTI_MAC:
 323         case MAC_ADDR_TYPE_CAM_MAC:
 324                 {
 325                         u32 cam_output;
 326                         u32 upper = (addr[0] << 8) | addr[1];
 327                         u32 lower =
 328                             (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) |
 329                             (addr[5]);
 330
 331                         QPRINTK(qdev, IFUP, DEBUG,
 332                                 "Adding %s address %pM"
 333                                 " at index %d in the CAM.\n",
 334                                 ((type ==
 335                                   MAC_ADDR_TYPE_MULTI_MAC) ? "MULTICAST" :
 336                                  "UNICAST"), addr, index);
 337
 338                         status =
 339                             ql_wait_reg_rdy(qdev,
 340                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 341                         if (status)
 342                                 goto exit;
 343                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 344                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 345                                    type);       /* type */
 346                         ql_write32(qdev, MAC_ADDR_DATA, lower);
 347                         status =
 348                             ql_wait_reg_rdy(qdev,
 349                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 350                         if (status)
 351                                 goto exit;
 352                         ql_write32(qdev, MAC_ADDR_IDX, (offset++) | /* offset */
 353                                    (index << MAC_ADDR_IDX_SHIFT) | /* index */
 354                                    type);       /* type */
 355                         ql_write32(qdev, MAC_ADDR_DATA, upper);
 356                         status =
 357                             ql_wait_reg_rdy(qdev,
 358                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 359                         if (status)
 360                                 goto exit;
 361                         ql_write32(qdev, MAC_ADDR_IDX, (offset) |       /* offset */
 362                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 363                                    type);       /* type */
 364                         /* This field should also include the queue id
 365                            and possibly the function id.  Right now we hardcode
 366                            the route field to NIC core.
 367                          */
 368                         if (type == MAC_ADDR_TYPE_CAM_MAC) {
 369                                 cam_output = (CAM_OUT_ROUTE_NIC |
 370                                               (qdev->
 371                                                func << CAM_OUT_FUNC_SHIFT) |
 372                                               (qdev->
 373                                                rss_ring_first_cq_id <<
 374                                                CAM_OUT_CQ_ID_SHIFT));
 375                                 if (qdev->vlgrp)
 376                                         cam_output |= CAM_OUT_RV;
 377                                 /* route to NIC core */
 378                                 ql_write32(qdev, MAC_ADDR_DATA, cam_output);
 379                         }
 380                         break;
 381                 }
 382         case MAC_ADDR_TYPE_VLAN:
 383                 {
 384                         u32 enable_bit = *((u32 *) &addr[0]);
 385                         /* For VLAN, the addr actually holds a bit that
 386                          * either enables or disables the vlan id we are
 387                          * addressing. It's either MAC_ADDR_E on or off.
 388                          * That's bit-27 we're talking about.
 389                          */
 390                         QPRINTK(qdev, IFUP, INFO, "%s VLAN ID %d %s the CAM.\n",
 391                                 (enable_bit ? "Adding" : "Removing"),
 392                                 index, (enable_bit ? "to" : "from"));
 393
 394                         status =
 395                             ql_wait_reg_rdy(qdev,
 396                                 MAC_ADDR_IDX, MAC_ADDR_MW, 0);
 397                         if (status)
 398                                 goto exit;
 399                         ql_write32(qdev, MAC_ADDR_IDX, offset | /* offset */
 400                                    (index << MAC_ADDR_IDX_SHIFT) |      /* index */
 401                                    type |       /* type */
 402                                    enable_bit); /* enable/disable */
 403                         break;
 404                 }
 405         case MAC_ADDR_TYPE_MULTI_FLTR:
 406         default:
 407                 QPRINTK(qdev, IFUP, CRIT,
 408                         "Address type %d not yet supported.\n", type);
 409                 status = -EPERM;
 410         }
 411 exit:
 412         return status;
 413 }
 414
 415 /* Get a specific frame routing value from the CAM.
 416  * Used for debug and reg dump.
 417  */
 418 int ql_get_routing_reg(struct ql_adapter *qdev, u32 index, u32 *value)
 419 {
 420         int status = 0;
 421
 422         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 423         if (status)
 424                 goto exit;
 425
 426         ql_write32(qdev, RT_IDX,
 427                    RT_IDX_TYPE_NICQ | RT_IDX_RS | (index << RT_IDX_IDX_SHIFT));
 428         status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MR, 0);
 429         if (status)
 430                 goto exit;
 431         *value = ql_read32(qdev, RT_DATA);
 432 exit:
 433         return status;
 434 }
 435
 436 /* The NIC function for this chip has 16 routing indexes.  Each one can be used
 437  * to route different frame types to various inbound queues.  We send broadcast/
 438  * multicast/error frames to the default queue for slow handling,
 439  * and CAM hit/RSS frames to the fast handling queues.
 440  */
 441 static int ql_set_routing_reg(struct ql_adapter *qdev, u32 index, u32 mask,
 442                               int enable)
 443 {
 444         int status = -EINVAL; /* Return error if no mask match. */
 445         u32 value = 0;
 446
 447         QPRINTK(qdev, IFUP, DEBUG,
 448                 "%s %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s mask %s the routing reg.\n",
 449                 (enable ? "Adding" : "Removing"),
 450                 ((index == RT_IDX_ALL_ERR_SLOT) ? "MAC ERROR/ALL ERROR" : ""),
 451                 ((index == RT_IDX_IP_CSUM_ERR_SLOT) ? "IP CSUM ERROR" : ""),
 452                 ((index ==
 453                   RT_IDX_TCP_UDP_CSUM_ERR_SLOT) ? "TCP/UDP CSUM ERROR" : ""),
 454                 ((index == RT_IDX_BCAST_SLOT) ? "BROADCAST" : ""),
 455                 ((index == RT_IDX_MCAST_MATCH_SLOT) ? "MULTICAST MATCH" : ""),
 456                 ((index == RT_IDX_ALLMULTI_SLOT) ? "ALL MULTICAST MATCH" : ""),
 457                 ((index == RT_IDX_UNUSED6_SLOT) ? "UNUSED6" : ""),
 458                 ((index == RT_IDX_UNUSED7_SLOT) ? "UNUSED7" : ""),
 459                 ((index == RT_IDX_RSS_MATCH_SLOT) ? "RSS ALL/IPV4 MATCH" : ""),
 460                 ((index == RT_IDX_RSS_IPV6_SLOT) ? "RSS IPV6" : ""),
 461                 ((index == RT_IDX_RSS_TCP4_SLOT) ? "RSS TCP4" : ""),
 462                 ((index == RT_IDX_RSS_TCP6_SLOT) ? "RSS TCP6" : ""),
 463                 ((index == RT_IDX_CAM_HIT_SLOT) ? "CAM HIT" : ""),
 464                 ((index == RT_IDX_UNUSED013) ? "UNUSED13" : ""),
 465                 ((index == RT_IDX_UNUSED014) ? "UNUSED14" : ""),
 466                 ((index == RT_IDX_PROMISCUOUS_SLOT) ? "PROMISCUOUS" : ""),
 467                 (enable ? "to" : "from"));
 468
 469         switch (mask) {
 470         case RT_IDX_CAM_HIT:
 471                 {
 472                         value = RT_IDX_DST_CAM_Q |      /* dest */
 473                             RT_IDX_TYPE_NICQ |  /* type */
 474                             (RT_IDX_CAM_HIT_SLOT << RT_IDX_IDX_SHIFT);/* index */
 475                         break;
 476                 }
 477         case RT_IDX_VALID:      /* Promiscuous Mode frames. */
 478                 {
 479                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 480                             RT_IDX_TYPE_NICQ |  /* type */
 481                             (RT_IDX_PROMISCUOUS_SLOT << RT_IDX_IDX_SHIFT);/* index */
 482                         break;
 483                 }
 484         case RT_IDX_ERR:        /* Pass up MAC,IP,TCP/UDP error frames. */
 485                 {
 486                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 487                             RT_IDX_TYPE_NICQ |  /* type */
 488                             (RT_IDX_ALL_ERR_SLOT << RT_IDX_IDX_SHIFT);/* index */
 489                         break;
 490                 }
 491         case RT_IDX_BCAST:      /* Pass up Broadcast frames to default Q. */
 492                 {
 493                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 494                             RT_IDX_TYPE_NICQ |  /* type */
 495                             (RT_IDX_BCAST_SLOT << RT_IDX_IDX_SHIFT);/* index */
 496                         break;
 497                 }
 498         case RT_IDX_MCAST:      /* Pass up All Multicast frames. */
 499                 {
 500                         value = RT_IDX_DST_CAM_Q |      /* dest */
 501                             RT_IDX_TYPE_NICQ |  /* type */
 502                             (RT_IDX_ALLMULTI_SLOT << RT_IDX_IDX_SHIFT);/* index */
 503                         break;
 504                 }
 505         case RT_IDX_MCAST_MATCH:        /* Pass up matched Multicast frames. */
 506                 {
 507                         value = RT_IDX_DST_CAM_Q |      /* dest */
 508                             RT_IDX_TYPE_NICQ |  /* type */
 509                             (RT_IDX_MCAST_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 510                         break;
 511                 }
 512         case RT_IDX_RSS_MATCH:  /* Pass up matched RSS frames. */
 513                 {
 514                         value = RT_IDX_DST_RSS |        /* dest */
 515                             RT_IDX_TYPE_NICQ |  /* type */
 516                             (RT_IDX_RSS_MATCH_SLOT << RT_IDX_IDX_SHIFT);/* index */
 517                         break;
 518                 }
 519         case 0:         /* Clear the E-bit on an entry. */
 520                 {
 521                         value = RT_IDX_DST_DFLT_Q |     /* dest */
 522                             RT_IDX_TYPE_NICQ |  /* type */
 523                             (index << RT_IDX_IDX_SHIFT);/* index */
 524                         break;
 525                 }
 526         default:
 527                 QPRINTK(qdev, IFUP, ERR, "Mask type %d not yet supported.\n",
 528                         mask);
 529                 status = -EPERM;
 530                 goto exit;
 531         }
 532
 533         if (value) {
 534                 status = ql_wait_reg_rdy(qdev, RT_IDX, RT_IDX_MW, 0);
 535                 if (status)
 536                         goto exit;
 537                 value |= (enable ? RT_IDX_E : 0);
 538                 ql_write32(qdev, RT_IDX, value);
 539                 ql_write32(qdev, RT_DATA, enable ? mask : 0);
 540         }
 541 exit:
 542         return status;
 543 }
 544
 545 static void ql_enable_interrupts(struct ql_adapter *qdev)
 546 {
 547         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16) | INTR_EN_EI);
 548 }
 549
 550 static void ql_disable_interrupts(struct ql_adapter *qdev)
 551 {
 552         ql_write32(qdev, INTR_EN, (INTR_EN_EI << 16));
 553 }
 554
 555 /* If we're running with multiple MSI-X vectors then we enable on the fly.
 556  * Otherwise, we may have multiple outstanding workers and don't want to
 557  * enable until the last one finishes. In this case, the irq_cnt gets
 558  * incremented everytime we queue a worker and decremented everytime
 559  * a worker finishes.  Once it hits zero we enable the interrupt.
 560  */
 561 u32 ql_enable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 562 {
 563         u32 var = 0;
 564         unsigned long hw_flags = 0;
 565         struct intr_context *ctx = qdev->intr_context + intr;
 566
 567         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr)) {
 568                 /* Always enable if we're MSIX multi interrupts and
 569                  * it's not the default (zeroeth) interrupt.
 570                  */
 571                 ql_write32(qdev, INTR_EN,
 572                            ctx->intr_en_mask);
 573                 var = ql_read32(qdev, STS);
 574                 return var;
 575         }
 576
 577         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 578         if (atomic_dec_and_test(&ctx->irq_cnt)) {
 579                 ql_write32(qdev, INTR_EN,
 580                            ctx->intr_en_mask);
 581                 var = ql_read32(qdev, STS);
 582         }
 583         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 584         return var;
 585 }
 586
 587 static u32 ql_disable_completion_interrupt(struct ql_adapter *qdev, u32 intr)
 588 {
 589         u32 var = 0;
 590         unsigned long hw_flags;
 591         struct intr_context *ctx;
 592
 593         /* HW disables for us if we're MSIX multi interrupts and
 594          * it's not the default (zeroeth) interrupt.
 595          */
 596         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags) && intr))
 597                 return 0;
 598
 599         ctx = qdev->intr_context + intr;
 600         spin_lock_irqsave(&qdev->hw_lock, hw_flags);
 601         if (!atomic_read(&ctx->irq_cnt)) {
 602                 ql_write32(qdev, INTR_EN,
 603                 ctx->intr_dis_mask);
 604                 var = ql_read32(qdev, STS);
 605         }
 606         atomic_inc(&ctx->irq_cnt);
 607         spin_unlock_irqrestore(&qdev->hw_lock, hw_flags);
 608         return var;
 609 }
 610
 611 static void ql_enable_all_completion_interrupts(struct ql_adapter *qdev)
 612 {
 613         int i;
 614         for (i = 0; i < qdev->intr_count; i++) {
 615                 /* The enable call does a atomic_dec_and_test
 616                  * and enables only if the result is zero.
 617                  * So we precharge it here.
 618                  */
 619                 if (unlikely(!test_bit(QL_MSIX_ENABLED, &qdev->flags) ||
 620                         i == 0))
 621                         atomic_set(&qdev->intr_context[i].irq_cnt, 1);
 622                 ql_enable_completion_interrupt(qdev, i);
 623         }
 624
 625 }
 626
 627 static int ql_validate_flash(struct ql_adapter *qdev, u32 size, const char *str)
 628 {
 629         int status, i;
 630         u16 csum = 0;
 631         __le16 *flash = (__le16 *)&qdev->flash;
 632
 633         status = strncmp((char *)&qdev->flash, str, 4);
 634         if (status) {
 635                 QPRINTK(qdev, IFUP, ERR, "Invalid flash signature.\n");
 636                 return  status;
 637         }
 638
 639         for (i = 0; i < size; i++)
 640                 csum += le16_to_cpu(*flash++);
 641
 642         if (csum)
 643                 QPRINTK(qdev, IFUP, ERR,
 644                         "Invalid flash checksum, csum = 0x%.04x.\n", csum);
 645
 646         return csum;
 647 }
 648
 649 static int ql_read_flash_word(struct ql_adapter *qdev, int offset, __le32 *data)
 650 {
 651         int status = 0;
 652         /* wait for reg to come ready */
 653         status = ql_wait_reg_rdy(qdev,
 654                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 655         if (status)
 656                 goto exit;
 657         /* set up for reg read */
 658         ql_write32(qdev, FLASH_ADDR, FLASH_ADDR_R | offset);
 659         /* wait for reg to come ready */
 660         status = ql_wait_reg_rdy(qdev,
 661                         FLASH_ADDR, FLASH_ADDR_RDY, FLASH_ADDR_ERR);
 662         if (status)
 663                 goto exit;
 664          /* This data is stored on flash as an array of
 665          * __le32.  Since ql_read32() returns cpu endian
 666          * we need to swap it back.
 667          */
 668         *data = cpu_to_le32(ql_read32(qdev, FLASH_DATA));
 669 exit:
 670         return status;
 671 }
 672
 673 static int ql_get_8000_flash_params(struct ql_adapter *qdev)
 674 {
 675         u32 i, size;
 676         int status;
 677         __le32 *p = (__le32 *)&qdev->flash;
 678         u32 offset;
 679
 680         /* Get flash offset for function and adjust
 681          * for dword access.
 682          */
 683         if (!qdev->func)
 684                 offset = FUNC0_FLASH_OFFSET / sizeof(u32);
 685         else
 686                 offset = FUNC1_FLASH_OFFSET / sizeof(u32);
 687
 688         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 689                 return -ETIMEDOUT;
 690
 691         size = sizeof(struct flash_params_8000) / sizeof(u32);
 692         for (i = 0; i < size; i++, p++) {
 693                 status = ql_read_flash_word(qdev, i+offset, p);
 694                 if (status) {
 695                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 696                         goto exit;
 697                 }
 698         }
 699
 700         status = ql_validate_flash(qdev,
 701                         sizeof(struct flash_params_8000) / sizeof(u16),
 702                         "8000");
 703         if (status) {
 704                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
 705                 status = -EINVAL;
 706                 goto exit;
 707         }
 708
 709         if (!is_valid_ether_addr(qdev->flash.flash_params_8000.mac_addr)) {
 710                 QPRINTK(qdev, IFUP, ERR, "Invalid MAC address.\n");
 711                 status = -EINVAL;
 712                 goto exit;
 713         }
 714
 715         memcpy(qdev->ndev->dev_addr,
 716                 qdev->flash.flash_params_8000.mac_addr,
 717                 qdev->ndev->addr_len);
 718
 719 exit:
 720         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 721         return status;
 722 }
 723
 724 static int ql_get_8012_flash_params(struct ql_adapter *qdev)
 725 {
 726         int i;
 727         int status;
 728         __le32 *p = (__le32 *)&qdev->flash;
 729         u32 offset = 0;
 730         u32 size = sizeof(struct flash_params_8012) / sizeof(u32);
 731
 732         /* Second function's parameters follow the first
 733          * function's.
 734          */
 735         if (qdev->func)
 736                 offset = size;
 737
 738         if (ql_sem_spinlock(qdev, SEM_FLASH_MASK))
 739                 return -ETIMEDOUT;
 740
 741         for (i = 0; i < size; i++, p++) {
 742                 status = ql_read_flash_word(qdev, i+offset, p);
 743                 if (status) {
 744                         QPRINTK(qdev, IFUP, ERR, "Error reading flash.\n");
 745                         goto exit;
 746                 }
 747
 748         }
 749
 750         status = ql_validate_flash(qdev,
 751                         sizeof(struct flash_params_8012) / sizeof(u16),
 752                         "8012");
 753         if (status) {
 754                 QPRINTK(qdev, IFUP, ERR, "Invalid flash.\n");
 755                 status = -EINVAL;
 756                 goto exit;
 757         }
 758
 759         if (!is_valid_ether_addr(qdev->flash.flash_params_8012.mac_addr)) {
 760                 status = -EINVAL;
 761                 goto exit;
 762         }
 763
 764         memcpy(qdev->ndev->dev_addr,
 765                 qdev->flash.flash_params_8012.mac_addr,
 766                 qdev->ndev->addr_len);
 767
 768 exit:
 769         ql_sem_unlock(qdev, SEM_FLASH_MASK);
 770         return status;
 771 }
 772
 773 /* xgmac register are located behind the xgmac_addr and xgmac_data
 774  * register pair.  Each read/write requires us to wait for the ready
 775  * bit before reading/writing the data.
 776  */
 777 static int ql_write_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 data)
 778 {
 779         int status;
 780         /* wait for reg to come ready */
 781         status = ql_wait_reg_rdy(qdev,
 782                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 783         if (status)
 784                 return status;
 785         /* write the data to the data reg */
 786         ql_write32(qdev, XGMAC_DATA, data);
 787         /* trigger the write */
 788         ql_write32(qdev, XGMAC_ADDR, reg);
 789         return status;
 790 }
 791
 792 /* xgmac register are located behind the xgmac_addr and xgmac_data
 793  * register pair.  Each read/write requires us to wait for the ready
 794  * bit before reading/writing the data.
 795  */
 796 int ql_read_xgmac_reg(struct ql_adapter *qdev, u32 reg, u32 *data)
 797 {
 798         int status = 0;
 799         /* wait for reg to come ready */
 800         status = ql_wait_reg_rdy(qdev,
 801                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 802         if (status)
 803                 goto exit;
 804         /* set up for reg read */
 805         ql_write32(qdev, XGMAC_ADDR, reg | XGMAC_ADDR_R);
 806         /* wait for reg to come ready */
 807         status = ql_wait_reg_rdy(qdev,
 808                         XGMAC_ADDR, XGMAC_ADDR_RDY, XGMAC_ADDR_XME);
 809         if (status)
 810                 goto exit;
 811         /* get the data */
 812         *data = ql_read32(qdev, XGMAC_DATA);
 813 exit:
 814         return status;
 815 }
 816
 817 /* This is used for reading the 64-bit statistics regs. */
 818 int ql_read_xgmac_reg64(struct ql_adapter *qdev, u32 reg, u64 *data)
 819 {
 820         int status = 0;
 821         u32 hi = 0;
 822         u32 lo = 0;
 823
 824         status = ql_read_xgmac_reg(qdev, reg, &lo);
 825         if (status)
 826                 goto exit;
 827
 828         status = ql_read_xgmac_reg(qdev, reg + 4, &hi);
 829         if (status)
 830                 goto exit;
 831
 832         *data = (u64) lo | ((u64) hi << 32);
 833
 834 exit:
 835         return status;
 836 }
 837
 838 static int ql_8000_port_initialize(struct ql_adapter *qdev)
 839 {
 840         int status;
 841         status = ql_mb_get_fw_state(qdev);
 842         if (status)
 843                 goto exit;
 844         /* Wake up a worker to get/set the TX/RX frame sizes. */
 845         queue_delayed_work(qdev->workqueue, &qdev->mpi_port_cfg_work, 0);
 846 exit:
 847         return status;
 848 }
 849
 850 /* Take the MAC Core out of reset.
 851  * Enable statistics counting.
 852  * Take the transmitter/receiver out of reset.
 853  * This functionality may be done in the MPI firmware at a
 854  * later date.
 855  */
 856 static int ql_8012_port_initialize(struct ql_adapter *qdev)
 857 {
 858         int status = 0;
 859         u32 data;
 860
 861         if (ql_sem_trylock(qdev, qdev->xg_sem_mask)) {
 862                 /* Another function has the semaphore, so
 863                  * wait for the port init bit to come ready.
 864                  */
 865                 QPRINTK(qdev, LINK, INFO,
 866                         "Another function has the semaphore, so wait for the port init bit to come ready.\n");
 867                 status = ql_wait_reg_rdy(qdev, STS, qdev->port_init, 0);
 868                 if (status) {
 869                         QPRINTK(qdev, LINK, CRIT,
 870                                 "Port initialize timed out.\n");
 871                 }
 872                 return status;
 873         }
 874
 875         QPRINTK(qdev, LINK, INFO, "Got xgmac semaphore!.\n");
 876         /* Set the core reset. */
 877         status = ql_read_xgmac_reg(qdev, GLOBAL_CFG, &data);
 878         if (status)
 879                 goto end;
 880         data |= GLOBAL_CFG_RESET;
 881         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 882         if (status)
 883                 goto end;
 884
 885         /* Clear the core reset and turn on jumbo for receiver. */
 886         data &= ~GLOBAL_CFG_RESET;      /* Clear core reset. */
 887         data |= GLOBAL_CFG_JUMBO;       /* Turn on jumbo. */
 888         data |= GLOBAL_CFG_TX_STAT_EN;
 889         data |= GLOBAL_CFG_RX_STAT_EN;
 890         status = ql_write_xgmac_reg(qdev, GLOBAL_CFG, data);
 891         if (status)
 892                 goto end;
 893
 894         /* Enable transmitter, and clear it's reset. */
 895         status = ql_read_xgmac_reg(qdev, TX_CFG, &data);
 896         if (status)
 897                 goto end;
 898         data &= ~TX_CFG_RESET;  /* Clear the TX MAC reset. */
 899         data |= TX_CFG_EN;      /* Enable the transmitter. */
 900         status = ql_write_xgmac_reg(qdev, TX_CFG, data);
 901         if (status)
 902                 goto end;
 903
 904         /* Enable receiver and clear it's reset. */
 905         status = ql_read_xgmac_reg(qdev, RX_CFG, &data);
 906         if (status)
 907                 goto end;
 908         data &= ~RX_CFG_RESET;  /* Clear the RX MAC reset. */
 909         data |= RX_CFG_EN;      /* Enable the receiver. */
 910         status = ql_write_xgmac_reg(qdev, RX_CFG, data);
 911         if (status)
 912                 goto end;
 913
 914         /* Turn on jumbo. */
 915         status =
 916             ql_write_xgmac_reg(qdev, MAC_TX_PARAMS, MAC_TX_PARAMS_JUMBO | (0x2580 << 16));
 917         if (status)
 918                 goto end;
 919         status =
 920             ql_write_xgmac_reg(qdev, MAC_RX_PARAMS, 0x2580);
 921         if (status)
 922                 goto end;
 923
 924         /* Signal to the world that the port is enabled.        */
 925         ql_write32(qdev, STS, ((qdev->port_init << 16) | qdev->port_init));
 926 end:
 927         ql_sem_unlock(qdev, qdev->xg_sem_mask);
 928         return status;
 929 }
 930
 931 /* Get the next large buffer. */
 932 static struct bq_desc *ql_get_curr_lbuf(struct rx_ring *rx_ring)
 933 {
 934         struct bq_desc *lbq_desc = &rx_ring->lbq[rx_ring->lbq_curr_idx];
 935         rx_ring->lbq_curr_idx++;
 936         if (rx_ring->lbq_curr_idx == rx_ring->lbq_len)
 937                 rx_ring->lbq_curr_idx = 0;
 938         rx_ring->lbq_free_cnt++;
 939         return lbq_desc;
 940 }
 941
 942 /* Get the next small buffer. */
 943 static struct bq_desc *ql_get_curr_sbuf(struct rx_ring *rx_ring)
 944 {
 945         struct bq_desc *sbq_desc = &rx_ring->sbq[rx_ring->sbq_curr_idx];
 946         rx_ring->sbq_curr_idx++;
 947         if (rx_ring->sbq_curr_idx == rx_ring->sbq_len)
 948                 rx_ring->sbq_curr_idx = 0;
 949         rx_ring->sbq_free_cnt++;
 950         return sbq_desc;
 951 }
 952
 953 /* Update an rx ring index. */
 954 static void ql_update_cq(struct rx_ring *rx_ring)
 955 {
 956         rx_ring->cnsmr_idx++;
 957         rx_ring->curr_entry++;
 958         if (unlikely(rx_ring->cnsmr_idx == rx_ring->cq_len)) {
 959                 rx_ring->cnsmr_idx = 0;
 960                 rx_ring->curr_entry = rx_ring->cq_base;
 961         }
 962 }
 963
 964 static void ql_write_cq_idx(struct rx_ring *rx_ring)
 965 {
 966         ql_write_db_reg(rx_ring->cnsmr_idx, rx_ring->cnsmr_idx_db_reg);
 967 }
 968
 969 /* Process (refill) a large buffer queue. */
 970 static void ql_update_lbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
 971 {
 972         u32 clean_idx = rx_ring->lbq_clean_idx;
 973         u32 start_idx = clean_idx;
 974         struct bq_desc *lbq_desc;
 975         u64 map;
 976         int i;
 977
 978         while (rx_ring->lbq_free_cnt > 16) {
 979                 for (i = 0; i < 16; i++) {
 980                         QPRINTK(qdev, RX_STATUS, DEBUG,
 981                                 "lbq: try cleaning clean_idx = %d.\n",
 982                                 clean_idx);
 983                         lbq_desc = &rx_ring->lbq[clean_idx];
 984                         if (lbq_desc->p.lbq_page == NULL) {
 985                                 QPRINTK(qdev, RX_STATUS, DEBUG,
 986                                         "lbq: getting new page for index %d.\n",
 987                                         lbq_desc->index);
 988                                 lbq_desc->p.lbq_page = alloc_page(GFP_ATOMIC);
 989                                 if (lbq_desc->p.lbq_page == NULL) {
 990                                         rx_ring->lbq_clean_idx = clean_idx;
 991                                         QPRINTK(qdev, RX_STATUS, ERR,
 992                                                 "Couldn't get a page.\n");
 993                                         return;
 994                                 }
 995                                 map = pci_map_page(qdev->pdev,
 996                                                    lbq_desc->p.lbq_page,
 997                                                    0, PAGE_SIZE,
 998                                                    PCI_DMA_FROMDEVICE);
 999                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1000                                         rx_ring->lbq_clean_idx = clean_idx;
1001                                         put_page(lbq_desc->p.lbq_page);
1002                                         lbq_desc->p.lbq_page = NULL;
1003                                         QPRINTK(qdev, RX_STATUS, ERR,
1004                                                 "PCI mapping failed.\n");
1005                                         return;
1006                                 }
1007                                 pci_unmap_addr_set(lbq_desc, mapaddr, map);
1008                                 pci_unmap_len_set(lbq_desc, maplen, PAGE_SIZE);
1009                                 *lbq_desc->addr = cpu_to_le64(map);
1010                         }
1011                         clean_idx++;
1012                         if (clean_idx == rx_ring->lbq_len)
1013                                 clean_idx = 0;
1014                 }
1015
1016                 rx_ring->lbq_clean_idx = clean_idx;
1017                 rx_ring->lbq_prod_idx += 16;
1018                 if (rx_ring->lbq_prod_idx == rx_ring->lbq_len)
1019                         rx_ring->lbq_prod_idx = 0;
1020                 rx_ring->lbq_free_cnt -= 16;
1021         }
1022
1023         if (start_idx != clean_idx) {
1024                 QPRINTK(qdev, RX_STATUS, DEBUG,
1025                         "lbq: updating prod idx = %d.\n",
1026                         rx_ring->lbq_prod_idx);
1027                 ql_write_db_reg(rx_ring->lbq_prod_idx,
1028                                 rx_ring->lbq_prod_idx_db_reg);
1029         }
1030 }
1031
1032 /* Process (refill) a small buffer queue. */
1033 static void ql_update_sbq(struct ql_adapter *qdev, struct rx_ring *rx_ring)
1034 {
1035         u32 clean_idx = rx_ring->sbq_clean_idx;
1036         u32 start_idx = clean_idx;
1037         struct bq_desc *sbq_desc;
1038         u64 map;
1039         int i;
1040
1041         while (rx_ring->sbq_free_cnt > 16) {
1042                 for (i = 0; i < 16; i++) {
1043                         sbq_desc = &rx_ring->sbq[clean_idx];
1044                         QPRINTK(qdev, RX_STATUS, DEBUG,
1045                                 "sbq: try cleaning clean_idx = %d.\n",
1046                                 clean_idx);
1047                         if (sbq_desc->p.skb == NULL) {
1048                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1049                                         "sbq: getting new skb for index %d.\n",
1050                                         sbq_desc->index);
1051                                 sbq_desc->p.skb =
1052                                     netdev_alloc_skb(qdev->ndev,
1053                                                      rx_ring->sbq_buf_size);
1054                                 if (sbq_desc->p.skb == NULL) {
1055                                         QPRINTK(qdev, PROBE, ERR,
1056                                                 "Couldn't get an skb.\n");
1057                                         rx_ring->sbq_clean_idx = clean_idx;
1058                                         return;
1059                                 }
1060                                 skb_reserve(sbq_desc->p.skb, QLGE_SB_PAD);
1061                                 map = pci_map_single(qdev->pdev,
1062                                                      sbq_desc->p.skb->data,
1063                                                      rx_ring->sbq_buf_size /
1064                                                      2, PCI_DMA_FROMDEVICE);
1065                                 if (pci_dma_mapping_error(qdev->pdev, map)) {
1066                                         QPRINTK(qdev, IFUP, ERR, "PCI mapping failed.\n");
1067                                         rx_ring->sbq_clean_idx = clean_idx;
1068                                         dev_kfree_skb_any(sbq_desc->p.skb);
1069                                         sbq_desc->p.skb = NULL;
1070                                         return;
1071                                 }
1072                                 pci_unmap_addr_set(sbq_desc, mapaddr, map);
1073                                 pci_unmap_len_set(sbq_desc, maplen,
1074                                                   rx_ring->sbq_buf_size / 2);
1075                                 *sbq_desc->addr = cpu_to_le64(map);
1076                         }
1077
1078                         clean_idx++;
1079                         if (clean_idx == rx_ring->sbq_len)
1080                                 clean_idx = 0;
1081                 }
1082                 rx_ring->sbq_clean_idx = clean_idx;
1083                 rx_ring->sbq_prod_idx += 16;
1084                 if (rx_ring->sbq_prod_idx == rx_ring->sbq_len)
1085                         rx_ring->sbq_prod_idx = 0;
1086                 rx_ring->sbq_free_cnt -= 16;
1087         }
1088
1089         if (start_idx != clean_idx) {
1090                 QPRINTK(qdev, RX_STATUS, DEBUG,
1091                         "sbq: updating prod idx = %d.\n",
1092                         rx_ring->sbq_prod_idx);
1093                 ql_write_db_reg(rx_ring->sbq_prod_idx,
1094                                 rx_ring->sbq_prod_idx_db_reg);
1095         }
1096 }
1097
1098 static void ql_update_buffer_queues(struct ql_adapter *qdev,
1099                                     struct rx_ring *rx_ring)
1100 {
1101         ql_update_sbq(qdev, rx_ring);
1102         ql_update_lbq(qdev, rx_ring);
1103 }
1104
1105 /* Unmaps tx buffers.  Can be called from send() if a pci mapping
1106  * fails at some stage, or from the interrupt when a tx completes.
1107  */
1108 static void ql_unmap_send(struct ql_adapter *qdev,
1109                           struct tx_ring_desc *tx_ring_desc, int mapped)
1110 {
1111         int i;
1112         for (i = 0; i < mapped; i++) {
1113                 if (i == 0 || (i == 7 && mapped > 7)) {
1114                         /*
1115                          * Unmap the skb->data area, or the
1116                          * external sglist (AKA the Outbound
1117                          * Address List (OAL)).
1118                          * If its the zeroeth element, then it's
1119                          * the skb->data area.  If it's the 7th
1120                          * element and there is more than 6 frags,
1121                          * then its an OAL.
1122                          */
1123                         if (i == 7) {
1124                                 QPRINTK(qdev, TX_DONE, DEBUG,
1125                                         "unmapping OAL area.\n");
1126                         }
1127                         pci_unmap_single(qdev->pdev,
1128                                          pci_unmap_addr(&tx_ring_desc->map[i],
1129                                                         mapaddr),
1130                                          pci_unmap_len(&tx_ring_desc->map[i],
1131                                                        maplen),
1132                                          PCI_DMA_TODEVICE);
1133                 } else {
1134                         QPRINTK(qdev, TX_DONE, DEBUG, "unmapping frag %d.\n",
1135                                 i);
1136                         pci_unmap_page(qdev->pdev,
1137                                        pci_unmap_addr(&tx_ring_desc->map[i],
1138                                                       mapaddr),
1139                                        pci_unmap_len(&tx_ring_desc->map[i],
1140                                                      maplen), PCI_DMA_TODEVICE);
1141                 }
1142         }
1143
1144 }
1145
1146 /* Map the buffers for this transmit.  This will return
1147  * NETDEV_TX_BUSY or NETDEV_TX_OK based on success.
1148  */
1149 static int ql_map_send(struct ql_adapter *qdev,
1150                        struct ob_mac_iocb_req *mac_iocb_ptr,
1151                        struct sk_buff *skb, struct tx_ring_desc *tx_ring_desc)
1152 {
1153         int len = skb_headlen(skb);
1154         dma_addr_t map;
1155         int frag_idx, err, map_idx = 0;
1156         struct tx_buf_desc *tbd = mac_iocb_ptr->tbd;
1157         int frag_cnt = skb_shinfo(skb)->nr_frags;
1158
1159         if (frag_cnt) {
1160                 QPRINTK(qdev, TX_QUEUED, DEBUG, "frag_cnt = %d.\n", frag_cnt);
1161         }
1162         /*
1163          * Map the skb buffer first.
1164          */
1165         map = pci_map_single(qdev->pdev, skb->data, len, PCI_DMA_TODEVICE);
1166
1167         err = pci_dma_mapping_error(qdev->pdev, map);
1168         if (err) {
1169                 QPRINTK(qdev, TX_QUEUED, ERR,
1170                         "PCI mapping failed with error: %d\n", err);
1171
1172                 return NETDEV_TX_BUSY;
1173         }
1174
1175         tbd->len = cpu_to_le32(len);
1176         tbd->addr = cpu_to_le64(map);
1177         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1178         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen, len);
1179         map_idx++;
1180
1181         /*
1182          * This loop fills the remainder of the 8 address descriptors
1183          * in the IOCB.  If there are more than 7 fragments, then the
1184          * eighth address desc will point to an external list (OAL).
1185          * When this happens, the remainder of the frags will be stored
1186          * in this list.
1187          */
1188         for (frag_idx = 0; frag_idx < frag_cnt; frag_idx++, map_idx++) {
1189                 skb_frag_t *frag = &skb_shinfo(skb)->frags[frag_idx];
1190                 tbd++;
1191                 if (frag_idx == 6 && frag_cnt > 7) {
1192                         /* Let's tack on an sglist.
1193                          * Our control block will now
1194                          * look like this:
1195                          * iocb->seg[0] = skb->data
1196                          * iocb->seg[1] = frag[0]
1197                          * iocb->seg[2] = frag[1]
1198                          * iocb->seg[3] = frag[2]
1199                          * iocb->seg[4] = frag[3]
1200                          * iocb->seg[5] = frag[4]
1201                          * iocb->seg[6] = frag[5]
1202                          * iocb->seg[7] = ptr to OAL (external sglist)
1203                          * oal->seg[0] = frag[6]
1204                          * oal->seg[1] = frag[7]
1205                          * oal->seg[2] = frag[8]
1206                          * oal->seg[3] = frag[9]
1207                          * oal->seg[4] = frag[10]
1208                          *      etc...
1209                          */
1210                         /* Tack on the OAL in the eighth segment of IOCB. */
1211                         map = pci_map_single(qdev->pdev, &tx_ring_desc->oal,
1212                                              sizeof(struct oal),
1213                                              PCI_DMA_TODEVICE);
1214                         err = pci_dma_mapping_error(qdev->pdev, map);
1215                         if (err) {
1216                                 QPRINTK(qdev, TX_QUEUED, ERR,
1217                                         "PCI mapping outbound address list with error: %d\n",
1218                                         err);
1219                                 goto map_error;
1220                         }
1221
1222                         tbd->addr = cpu_to_le64(map);
1223                         /*
1224                          * The length is the number of fragments
1225                          * that remain to be mapped times the length
1226                          * of our sglist (OAL).
1227                          */
1228                         tbd->len =
1229                             cpu_to_le32((sizeof(struct tx_buf_desc) *
1230                                          (frag_cnt - frag_idx)) | TX_DESC_C);
1231                         pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr,
1232                                            map);
1233                         pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1234                                           sizeof(struct oal));
1235                         tbd = (struct tx_buf_desc *)&tx_ring_desc->oal;
1236                         map_idx++;
1237                 }
1238
1239                 map =
1240                     pci_map_page(qdev->pdev, frag->page,
1241                                  frag->page_offset, frag->size,
1242                                  PCI_DMA_TODEVICE);
1243
1244                 err = pci_dma_mapping_error(qdev->pdev, map);
1245                 if (err) {
1246                         QPRINTK(qdev, TX_QUEUED, ERR,
1247                                 "PCI mapping frags failed with error: %d.\n",
1248                                 err);
1249                         goto map_error;
1250                 }
1251
1252                 tbd->addr = cpu_to_le64(map);
1253                 tbd->len = cpu_to_le32(frag->size);
1254                 pci_unmap_addr_set(&tx_ring_desc->map[map_idx], mapaddr, map);
1255                 pci_unmap_len_set(&tx_ring_desc->map[map_idx], maplen,
1256                                   frag->size);
1257
1258         }
1259         /* Save the number of segments we've mapped. */
1260         tx_ring_desc->map_cnt = map_idx;
1261         /* Terminate the last segment. */
1262         tbd->len = cpu_to_le32(le32_to_cpu(tbd->len) | TX_DESC_E);
1263         return NETDEV_TX_OK;
1264
1265 map_error:
1266         /*
1267          * If the first frag mapping failed, then i will be zero.
1268          * This causes the unmap of the skb->data area.  Otherwise
1269          * we pass in the number of frags that mapped successfully
1270          * so they can be umapped.
1271          */
1272         ql_unmap_send(qdev, tx_ring_desc, map_idx);
1273         return NETDEV_TX_BUSY;
1274 }
1275
1276 static void ql_realign_skb(struct sk_buff *skb, int len)
1277 {
1278         void *temp_addr = skb->data;
1279
1280         /* Undo the skb_reserve(skb,32) we did before
1281          * giving to hardware, and realign data on
1282          * a 2-byte boundary.
1283          */
1284         skb->data -= QLGE_SB_PAD - NET_IP_ALIGN;
1285         skb->tail -= QLGE_SB_PAD - NET_IP_ALIGN;
1286         skb_copy_to_linear_data(skb, temp_addr,
1287                 (unsigned int)len);
1288 }
1289
1290 /*
1291  * This function builds an skb for the given inbound
1292  * completion.  It will be rewritten for readability in the near
1293  * future, but for not it works well.
1294  */
1295 static struct sk_buff *ql_build_rx_skb(struct ql_adapter *qdev,
1296                                        struct rx_ring *rx_ring,
1297                                        struct ib_mac_iocb_rsp *ib_mac_rsp)
1298 {
1299         struct bq_desc *lbq_desc;
1300         struct bq_desc *sbq_desc;
1301         struct sk_buff *skb = NULL;
1302         u32 length = le32_to_cpu(ib_mac_rsp->data_len);
1303        u32 hdr_len = le32_to_cpu(ib_mac_rsp->hdr_len);
1304
1305         /*
1306          * Handle the header buffer if present.
1307          */
1308         if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HV &&
1309             ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1310                 QPRINTK(qdev, RX_STATUS, DEBUG, "Header of %d bytes in small buffer.\n", hdr_len);
1311                 /*
1312                  * Headers fit nicely into a small buffer.
1313                  */
1314                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1315                 pci_unmap_single(qdev->pdev,
1316                                 pci_unmap_addr(sbq_desc, mapaddr),
1317                                 pci_unmap_len(sbq_desc, maplen),
1318                                 PCI_DMA_FROMDEVICE);
1319                 skb = sbq_desc->p.skb;
1320                 ql_realign_skb(skb, hdr_len);
1321                 skb_put(skb, hdr_len);
1322                 sbq_desc->p.skb = NULL;
1323         }
1324
1325         /*
1326          * Handle the data buffer(s).
1327          */
1328         if (unlikely(!length)) {        /* Is there data too? */
1329                 QPRINTK(qdev, RX_STATUS, DEBUG,
1330                         "No Data buffer in this packet.\n");
1331                 return skb;
1332         }
1333
1334         if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DS) {
1335                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1336                         QPRINTK(qdev, RX_STATUS, DEBUG,
1337                                 "Headers in small, data of %d bytes in small, combine them.\n", length);
1338                         /*
1339                          * Data is less than small buffer size so it's
1340                          * stuffed in a small buffer.
1341                          * For this case we append the data
1342                          * from the "data" small buffer to the "header" small
1343                          * buffer.
1344                          */
1345                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1346                         pci_dma_sync_single_for_cpu(qdev->pdev,
1347                                                     pci_unmap_addr
1348                                                     (sbq_desc, mapaddr),
1349                                                     pci_unmap_len
1350                                                     (sbq_desc, maplen),
1351                                                     PCI_DMA_FROMDEVICE);
1352                         memcpy(skb_put(skb, length),
1353                                sbq_desc->p.skb->data, length);
1354                         pci_dma_sync_single_for_device(qdev->pdev,
1355                                                        pci_unmap_addr
1356                                                        (sbq_desc,
1357                                                         mapaddr),
1358                                                        pci_unmap_len
1359                                                        (sbq_desc,
1360                                                         maplen),
1361                                                        PCI_DMA_FROMDEVICE);
1362                 } else {
1363                         QPRINTK(qdev, RX_STATUS, DEBUG,
1364                                 "%d bytes in a single small buffer.\n", length);
1365                         sbq_desc = ql_get_curr_sbuf(rx_ring);
1366                         skb = sbq_desc->p.skb;
1367                         ql_realign_skb(skb, length);
1368                         skb_put(skb, length);
1369                         pci_unmap_single(qdev->pdev,
1370                                          pci_unmap_addr(sbq_desc,
1371                                                         mapaddr),
1372                                          pci_unmap_len(sbq_desc,
1373                                                        maplen),
1374                                          PCI_DMA_FROMDEVICE);
1375                         sbq_desc->p.skb = NULL;
1376                 }
1377         } else if (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_DL) {
1378                 if (ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS) {
1379                         QPRINTK(qdev, RX_STATUS, DEBUG,
1380                                 "Header in small, %d bytes in large. Chain large to small!\n", length);
1381                         /*
1382                          * The data is in a single large buffer.  We
1383                          * chain it to the header buffer's skb and let
1384                          * it rip.
1385                          */
1386                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1387                         pci_unmap_page(qdev->pdev,
1388                                        pci_unmap_addr(lbq_desc,
1389                                                       mapaddr),
1390                                        pci_unmap_len(lbq_desc, maplen),
1391                                        PCI_DMA_FROMDEVICE);
1392                         QPRINTK(qdev, RX_STATUS, DEBUG,
1393                                 "Chaining page to skb.\n");
1394                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1395                                            0, length);
1396                         skb->len += length;
1397                         skb->data_len += length;
1398                         skb->truesize += length;
1399                         lbq_desc->p.lbq_page = NULL;
1400                 } else {
1401                         /*
1402                          * The headers and data are in a single large buffer. We
1403                          * copy it to a new skb and let it go. This can happen with
1404                          * jumbo mtu on a non-TCP/UDP frame.
1405                          */
1406                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1407                         skb = netdev_alloc_skb(qdev->ndev, length);
1408                         if (skb == NULL) {
1409                                 QPRINTK(qdev, PROBE, DEBUG,
1410                                         "No skb available, drop the packet.\n");
1411                                 return NULL;
1412                         }
1413                         pci_unmap_page(qdev->pdev,
1414                                        pci_unmap_addr(lbq_desc,
1415                                                       mapaddr),
1416                                        pci_unmap_len(lbq_desc, maplen),
1417                                        PCI_DMA_FROMDEVICE);
1418                         skb_reserve(skb, NET_IP_ALIGN);
1419                         QPRINTK(qdev, RX_STATUS, DEBUG,
1420                                 "%d bytes of headers and data in large. Chain page to new skb and pull tail.\n", length);
1421                         skb_fill_page_desc(skb, 0, lbq_desc->p.lbq_page,
1422                                            0, length);
1423                         skb->len += length;
1424                         skb->data_len += length;
1425                         skb->truesize += length;
1426                         length -= length;
1427                         lbq_desc->p.lbq_page = NULL;
1428                         __pskb_pull_tail(skb,
1429                                 (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1430                                 VLAN_ETH_HLEN : ETH_HLEN);
1431                 }
1432         } else {
1433                 /*
1434                  * The data is in a chain of large buffers
1435                  * pointed to by a small buffer.  We loop
1436                  * thru and chain them to the our small header
1437                  * buffer's skb.
1438                  * frags:  There are 18 max frags and our small
1439                  *         buffer will hold 32 of them. The thing is,
1440                  *         we'll use 3 max for our 9000 byte jumbo
1441                  *         frames.  If the MTU goes up we could
1442                  *          eventually be in trouble.
1443                  */
1444                 int size, offset, i = 0;
1445                 __le64 *bq, bq_array[8];
1446                 sbq_desc = ql_get_curr_sbuf(rx_ring);
1447                 pci_unmap_single(qdev->pdev,
1448                                  pci_unmap_addr(sbq_desc, mapaddr),
1449                                  pci_unmap_len(sbq_desc, maplen),
1450                                  PCI_DMA_FROMDEVICE);
1451                 if (!(ib_mac_rsp->flags4 & IB_MAC_IOCB_RSP_HS)) {
1452                         /*
1453                          * This is an non TCP/UDP IP frame, so
1454                          * the headers aren't split into a small
1455                          * buffer.  We have to use the small buffer
1456                          * that contains our sg list as our skb to
1457                          * send upstairs. Copy the sg list here to
1458                          * a local buffer and use it to find the
1459                          * pages to chain.
1460                          */
1461                         QPRINTK(qdev, RX_STATUS, DEBUG,
1462                                 "%d bytes of headers & data in chain of large.\n", length);
1463                         skb = sbq_desc->p.skb;
1464                         bq = &bq_array[0];
1465                         memcpy(bq, skb->data, sizeof(bq_array));
1466                         sbq_desc->p.skb = NULL;
1467                         skb_reserve(skb, NET_IP_ALIGN);
1468                 } else {
1469                         QPRINTK(qdev, RX_STATUS, DEBUG,
1470                                 "Headers in small, %d bytes of data in chain of large.\n", length);
1471                         bq = (__le64 *)sbq_desc->p.skb->data;
1472                 }
1473                 while (length > 0) {
1474                         lbq_desc = ql_get_curr_lbuf(rx_ring);
1475                         pci_unmap_page(qdev->pdev,
1476                                        pci_unmap_addr(lbq_desc,
1477                                                       mapaddr),
1478                                        pci_unmap_len(lbq_desc,
1479                                                      maplen),
1480                                        PCI_DMA_FROMDEVICE);
1481                         size = (length < PAGE_SIZE) ? length : PAGE_SIZE;
1482                         offset = 0;
1483
1484                         QPRINTK(qdev, RX_STATUS, DEBUG,
1485                                 "Adding page %d to skb for %d bytes.\n",
1486                                 i, size);
1487                         skb_fill_page_desc(skb, i, lbq_desc->p.lbq_page,
1488                                            offset, size);
1489                         skb->len += size;
1490                         skb->data_len += size;
1491                         skb->truesize += size;
1492                         length -= size;
1493                         lbq_desc->p.lbq_page = NULL;
1494                         bq++;
1495                         i++;
1496                 }
1497                 __pskb_pull_tail(skb, (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V) ?
1498                                 VLAN_ETH_HLEN : ETH_HLEN);
1499         }
1500         return skb;
1501 }
1502
1503 /* Process an inbound completion from an rx ring. */
1504 static void ql_process_mac_rx_intr(struct ql_adapter *qdev,
1505                                    struct rx_ring *rx_ring,
1506                                    struct ib_mac_iocb_rsp *ib_mac_rsp)
1507 {
1508         struct net_device *ndev = qdev->ndev;
1509         struct sk_buff *skb = NULL;
1510
1511         QL_DUMP_IB_MAC_RSP(ib_mac_rsp);
1512
1513         skb = ql_build_rx_skb(qdev, rx_ring, ib_mac_rsp);
1514         if (unlikely(!skb)) {
1515                 QPRINTK(qdev, RX_STATUS, DEBUG,
1516                         "No skb available, drop packet.\n");
1517                 return;
1518         }
1519
1520         prefetch(skb->data);
1521         skb->dev = ndev;
1522         if (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) {
1523                 QPRINTK(qdev, RX_STATUS, DEBUG, "%s%s%s Multicast.\n",
1524                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1525                         IB_MAC_IOCB_RSP_M_HASH ? "Hash" : "",
1526                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1527                         IB_MAC_IOCB_RSP_M_REG ? "Registered" : "",
1528                         (ib_mac_rsp->flags1 & IB_MAC_IOCB_RSP_M_MASK) ==
1529                         IB_MAC_IOCB_RSP_M_PROM ? "Promiscuous" : "");
1530         }
1531         if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_P) {
1532                 QPRINTK(qdev, RX_STATUS, DEBUG, "Promiscuous Packet.\n");
1533         }
1534
1535
1536         skb->protocol = eth_type_trans(skb, ndev);
1537         skb->ip_summed = CHECKSUM_NONE;
1538
1539         /* If rx checksum is on, and there are no
1540          * csum or frame errors.
1541          */
1542         if (qdev->rx_csum &&
1543                 !(ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_ERR_MASK) &&
1544                 !(ib_mac_rsp->flags1 & IB_MAC_CSUM_ERR_MASK)) {
1545                 /* TCP frame. */
1546                 if (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_T) {
1547                         QPRINTK(qdev, RX_STATUS, DEBUG,
1548                                         "TCP checksum done!\n");
1549                         skb->ip_summed = CHECKSUM_UNNECESSARY;
1550                 } else if ((ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_U) &&
1551                                 (ib_mac_rsp->flags3 & IB_MAC_IOCB_RSP_V4)) {
1552                 /* Unfragmented ipv4 UDP frame. */
1553                         struct iphdr *iph = (struct iphdr *) skb->data;
1554                         if (!(iph->frag_off &
1555                                 cpu_to_be16(IP_MF|IP_OFFSET))) {
1556                                 skb->ip_summed = CHECKSUM_UNNECESSARY;
1557                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1558                                                 "TCP checksum done!\n");
1559                         }
1560                 }
1561         }
1562
1563         qdev->stats.rx_packets++;
1564         qdev->stats.rx_bytes += skb->len;
1565         skb_record_rx_queue(skb, rx_ring - &qdev->rx_ring[0]);
1566         if (qdev->vlgrp && (ib_mac_rsp->flags2 & IB_MAC_IOCB_RSP_V)) {
1567                 QPRINTK(qdev, RX_STATUS, DEBUG,
1568                         "Passing a VLAN packet upstream.\n");
1569                 vlan_hwaccel_receive_skb(skb, qdev->vlgrp,
1570                                 le16_to_cpu(ib_mac_rsp->vlan_id));
1571         } else {
1572                 QPRINTK(qdev, RX_STATUS, DEBUG,
1573                         "Passing a normal packet upstream.\n");
1574                 netif_receive_skb(skb);
1575         }
1576 }
1577
1578 /* Process an outbound completion from an rx ring. */
1579 static void ql_process_mac_tx_intr(struct ql_adapter *qdev,
1580                                    struct ob_mac_iocb_rsp *mac_rsp)
1581 {
1582         struct tx_ring *tx_ring;
1583         struct tx_ring_desc *tx_ring_desc;
1584
1585         QL_DUMP_OB_MAC_RSP(mac_rsp);
1586         tx_ring = &qdev->tx_ring[mac_rsp->txq_idx];
1587         tx_ring_desc = &tx_ring->q[mac_rsp->tid];
1588         ql_unmap_send(qdev, tx_ring_desc, tx_ring_desc->map_cnt);
1589         qdev->stats.tx_bytes += tx_ring_desc->map_cnt;
1590         qdev->stats.tx_packets++;
1591         dev_kfree_skb(tx_ring_desc->skb);
1592         tx_ring_desc->skb = NULL;
1593
1594         if (unlikely(mac_rsp->flags1 & (OB_MAC_IOCB_RSP_E |
1595                                         OB_MAC_IOCB_RSP_S |
1596                                         OB_MAC_IOCB_RSP_L |
1597                                         OB_MAC_IOCB_RSP_P | OB_MAC_IOCB_RSP_B))) {
1598                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_E) {
1599                         QPRINTK(qdev, TX_DONE, WARNING,
1600                                 "Total descriptor length did not match transfer length.\n");
1601                 }
1602                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_S) {
1603                         QPRINTK(qdev, TX_DONE, WARNING,
1604                                 "Frame too short to be legal, not sent.\n");
1605                 }
1606                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_L) {
1607                         QPRINTK(qdev, TX_DONE, WARNING,
1608                                 "Frame too long, but sent anyway.\n");
1609                 }
1610                 if (mac_rsp->flags1 & OB_MAC_IOCB_RSP_B) {
1611                         QPRINTK(qdev, TX_DONE, WARNING,
1612                                 "PCI backplane error. Frame not sent.\n");
1613                 }
1614         }
1615         atomic_inc(&tx_ring->tx_count);
1616 }
1617
1618 /* Fire up a handler to reset the MPI processor. */
1619 void ql_queue_fw_error(struct ql_adapter *qdev)
1620 {
1621         netif_stop_queue(qdev->ndev);
1622         netif_carrier_off(qdev->ndev);
1623         queue_delayed_work(qdev->workqueue, &qdev->mpi_reset_work, 0);
1624 }
1625
1626 void ql_queue_asic_error(struct ql_adapter *qdev)
1627 {
1628         netif_stop_queue(qdev->ndev);
1629         netif_carrier_off(qdev->ndev);
1630         ql_disable_interrupts(qdev);
1631         /* Clear adapter up bit to signal the recovery
1632          * process that it shouldn't kill the reset worker
1633          * thread
1634          */
1635         clear_bit(QL_ADAPTER_UP, &qdev->flags);
1636         queue_delayed_work(qdev->workqueue, &qdev->asic_reset_work, 0);
1637 }
1638
1639 static void ql_process_chip_ae_intr(struct ql_adapter *qdev,
1640                                     struct ib_ae_iocb_rsp *ib_ae_rsp)
1641 {
1642         switch (ib_ae_rsp->event) {
1643         case MGMT_ERR_EVENT:
1644                 QPRINTK(qdev, RX_ERR, ERR,
1645                         "Management Processor Fatal Error.\n");
1646                 ql_queue_fw_error(qdev);
1647                 return;
1648
1649         case CAM_LOOKUP_ERR_EVENT:
1650                 QPRINTK(qdev, LINK, ERR,
1651                         "Multiple CAM hits lookup occurred.\n");
1652                 QPRINTK(qdev, DRV, ERR, "This event shouldn't occur.\n");
1653                 ql_queue_asic_error(qdev);
1654                 return;
1655
1656         case SOFT_ECC_ERROR_EVENT:
1657                 QPRINTK(qdev, RX_ERR, ERR, "Soft ECC error detected.\n");
1658                 ql_queue_asic_error(qdev);
1659                 break;
1660
1661         case PCI_ERR_ANON_BUF_RD:
1662                 QPRINTK(qdev, RX_ERR, ERR,
1663                         "PCI error occurred when reading anonymous buffers from rx_ring %d.\n",
1664                         ib_ae_rsp->q_id);
1665                 ql_queue_asic_error(qdev);
1666                 break;
1667
1668         default:
1669                 QPRINTK(qdev, DRV, ERR, "Unexpected event %d.\n",
1670                         ib_ae_rsp->event);
1671                 ql_queue_asic_error(qdev);
1672                 break;
1673         }
1674 }
1675
1676 static int ql_clean_outbound_rx_ring(struct rx_ring *rx_ring)
1677 {
1678         struct ql_adapter *qdev = rx_ring->qdev;
1679         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1680         struct ob_mac_iocb_rsp *net_rsp = NULL;
1681         int count = 0;
1682
1683         /* While there are entries in the completion queue. */
1684         while (prod != rx_ring->cnsmr_idx) {
1685
1686                 QPRINTK(qdev, RX_STATUS, DEBUG,
1687                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1688                         prod, rx_ring->cnsmr_idx);
1689
1690                 net_rsp = (struct ob_mac_iocb_rsp *)rx_ring->curr_entry;
1691                 rmb();
1692                 switch (net_rsp->opcode) {
1693
1694                 case OPCODE_OB_MAC_TSO_IOCB:
1695                 case OPCODE_OB_MAC_IOCB:
1696                         ql_process_mac_tx_intr(qdev, net_rsp);
1697                         break;
1698                 default:
1699                         QPRINTK(qdev, RX_STATUS, DEBUG,
1700                                 "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1701                                 net_rsp->opcode);
1702                 }
1703                 count++;
1704                 ql_update_cq(rx_ring);
1705                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1706         }
1707         ql_write_cq_idx(rx_ring);
1708         if (netif_queue_stopped(qdev->ndev) && net_rsp != NULL) {
1709                 struct tx_ring *tx_ring = &qdev->tx_ring[net_rsp->txq_idx];
1710                 if (atomic_read(&tx_ring->queue_stopped) &&
1711                     (atomic_read(&tx_ring->tx_count) > (tx_ring->wq_len / 4)))
1712                         /*
1713                          * The queue got stopped because the tx_ring was full.
1714                          * Wake it up, because it's now at least 25% empty.
1715                          */
1716                         netif_wake_queue(qdev->ndev);
1717         }
1718
1719         return count;
1720 }
1721
1722 static int ql_clean_inbound_rx_ring(struct rx_ring *rx_ring, int budget)
1723 {
1724         struct ql_adapter *qdev = rx_ring->qdev;
1725         u32 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1726         struct ql_net_rsp_iocb *net_rsp;
1727         int count = 0;
1728
1729         /* While there are entries in the completion queue. */
1730         while (prod != rx_ring->cnsmr_idx) {
1731
1732                 QPRINTK(qdev, RX_STATUS, DEBUG,
1733                         "cq_id = %d, prod = %d, cnsmr = %d.\n.", rx_ring->cq_id,
1734                         prod, rx_ring->cnsmr_idx);
1735
1736                 net_rsp = rx_ring->curr_entry;
1737                 rmb();
1738                 switch (net_rsp->opcode) {
1739                 case OPCODE_IB_MAC_IOCB:
1740                         ql_process_mac_rx_intr(qdev, rx_ring,
1741                                                (struct ib_mac_iocb_rsp *)
1742                                                net_rsp);
1743                         break;
1744
1745                 case OPCODE_IB_AE_IOCB:
1746                         ql_process_chip_ae_intr(qdev, (struct ib_ae_iocb_rsp *)
1747                                                 net_rsp);
1748                         break;
1749                 default:
1750                         {
1751                                 QPRINTK(qdev, RX_STATUS, DEBUG,
1752                                         "Hit default case, not handled! dropping the packet, opcode = %x.\n",
1753                                         net_rsp->opcode);
1754                         }
1755                 }
1756                 count++;
1757                 ql_update_cq(rx_ring);
1758                 prod = ql_read_sh_reg(rx_ring->prod_idx_sh_reg);
1759                 if (count == budget)
1760                         break;
1761         }
1762         ql_update_buffer_queues(qdev, rx_ring);
1763         ql_write_cq_idx(rx_ring);
1764         return count;
1765 }
1766
1767 static int ql_napi_poll_msix(struct napi_struct *napi, int budget)
1768 {
1769         struct rx_ring *rx_ring = container_of(napi, struct rx_ring, napi);
1770         struct ql_adapter *qdev = rx_ring->qdev;
1771         int work_done = ql_clean_inbound_rx_ring(rx_ring, budget);
1772
1773         QPRINTK(qdev, RX_STATUS, DEBUG, "Enter, NAPI POLL cq_id = %d.\n",
1774                 rx_ring->cq_id);
1775
1776         if (work_done < budget) {
1777                 __napi_complete(napi);
1778                 ql_enable_completion_interrupt(qdev, rx_ring->irq);
1779         }
1780         return work_done;
1781 }
1782
1783 static void ql_vlan_rx_register(struct net_device *ndev, struct vlan_group *grp)
1784 {
1785         struct ql_adapter *qdev = netdev_priv(ndev);
1786
1787         qdev->vlgrp = grp;
1788         if (grp) {
1789                 QPRINTK(qdev, IFUP, DEBUG, "Turning on VLAN in NIC_RCV_CFG.\n");
1790                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK |
1791                            NIC_RCV_CFG_VLAN_MATCH_AND_NON);
1792         } else {
1793                 QPRINTK(qdev, IFUP, DEBUG,
1794                         "Turning off VLAN in NIC_RCV_CFG.\n");
1795                 ql_write32(qdev, NIC_RCV_CFG, NIC_RCV_CFG_VLAN_MASK);
1796         }
1797 }
1798
1799 static void ql_vlan_rx_add_vid(struct net_device *ndev, u16 vid)
1800 {
1801         struct ql_adapter *qdev = netdev_priv(ndev);
1802         u32 enable_bit = MAC_ADDR_E;
1803         int status;
1804
1805         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1806         if (status)
1807                 return;
1808         spin_lock(&qdev->hw_lock);
1809         if (ql_set_mac_addr_reg
1810             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1811                 QPRINTK(qdev, IFUP, ERR, "Failed to init vlan address.\n");
1812         }
1813         spin_unlock(&qdev->hw_lock);
1814         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1815 }
1816
1817 static void ql_vlan_rx_kill_vid(struct net_device *ndev, u16 vid)
1818 {
1819         struct ql_adapter *qdev = netdev_priv(ndev);
1820         u32 enable_bit = 0;
1821         int status;
1822
1823         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
1824         if (status)
1825                 return;
1826
1827         spin_lock(&qdev->hw_lock);
1828         if (ql_set_mac_addr_reg
1829             (qdev, (u8 *) &enable_bit, MAC_ADDR_TYPE_VLAN, vid)) {
1830                 QPRINTK(qdev, IFUP, ERR, "Failed to clear vlan address.\n");
1831         }
1832         spin_unlock(&qdev->hw_lock);
1833         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
1834
1835 }
1836
1837 /* Worker thread to process a given rx_ring that is dedicated
1838  * to outbound completions.
1839  */
1840 static void ql_tx_clean(struct work_struct *work)
1841 {
1842         struct rx_ring *rx_ring =
1843             container_of(work, struct rx_ring, rx_work.work);
1844         ql_clean_outbound_rx_ring(rx_ring);
1845         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1846
1847 }
1848
1849 /* Worker thread to process a given rx_ring that is dedicated
1850  * to inbound completions.
1851  */
1852 static void ql_rx_clean(struct work_struct *work)
1853 {
1854         struct rx_ring *rx_ring =
1855             container_of(work, struct rx_ring, rx_work.work);
1856         ql_clean_inbound_rx_ring(rx_ring, 64);
1857         ql_enable_completion_interrupt(rx_ring->qdev, rx_ring->irq);
1858 }
1859
1860 /* MSI-X Multiple Vector Interrupt Handler for outbound completions. */
1861 static irqreturn_t qlge_msix_tx_isr(int irq, void *dev_id)
1862 {
1863         struct rx_ring *rx_ring = dev_id;
1864         queue_delayed_work_on(rx_ring->cpu, rx_ring->qdev->q_workqueue,
1865                               &rx_ring->rx_work, 0);
1866         return IRQ_HANDLED;
1867 }
1868
1869 /* MSI-X Multiple Vector Interrupt Handler for inbound completions. */
1870 static irqreturn_t qlge_msix_rx_isr(int irq, void *dev_id)
1871 {
1872         struct rx_ring *rx_ring = dev_id;
1873         napi_schedule(&rx_ring->napi);
1874         return IRQ_HANDLED;
1875 }
1876
1877 /* This handles a fatal error, MPI activity, and the default
1878  * rx_ring in an MSI-X multiple vector environment.
1879  * In MSI/Legacy environment it also process the rest of
1880  * the rx_rings.
1881  */
1882 static irqreturn_t qlge_isr(int irq, void *dev_id)
1883 {
1884         struct rx_ring *rx_ring = dev_id;
1885         struct ql_adapter *qdev = rx_ring->qdev;
1886         struct intr_context *intr_context = &qdev->intr_context[0];
1887         u32 var;
1888         int i;
1889         int work_done = 0;
1890
1891         spin_lock(&qdev->hw_lock);
1892         if (atomic_read(&qdev->intr_context[0].irq_cnt)) {
1893                 QPRINTK(qdev, INTR, DEBUG, "Shared Interrupt, Not ours!\n");
1894                 spin_unlock(&qdev->hw_lock);
1895                 return IRQ_NONE;
1896         }
1897         spin_unlock(&qdev->hw_lock);
1898
1899         var = ql_disable_completion_interrupt(qdev, intr_context->intr);
1900
1901         /*
1902          * Check for fatal error.
1903          */
1904         if (var & STS_FE) {
1905                 ql_queue_asic_error(qdev);
1906                 QPRINTK(qdev, INTR, ERR, "Got fatal error, STS = %x.\n", var);
1907                 var = ql_read32(qdev, ERR_STS);
1908                 QPRINTK(qdev, INTR, ERR,
1909                         "Resetting chip. Error Status Register = 0x%x\n", var);
1910                 return IRQ_HANDLED;
1911         }
1912
1913         /*
1914          * Check MPI processor activity.
1915          */
1916         if (var & STS_PI) {
1917                 /*
1918                  * We've got an async event or mailbox completion.
1919                  * Handle it and clear the source of the interrupt.
1920                  */
1921                 QPRINTK(qdev, INTR, ERR, "Got MPI processor interrupt.\n");
1922                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1923                 queue_delayed_work_on(smp_processor_id(), qdev->workqueue,
1924                                       &qdev->mpi_work, 0);
1925                 work_done++;
1926         }
1927
1928         /*
1929          * Check the default queue and wake handler if active.
1930          */
1931         rx_ring = &qdev->rx_ring[0];
1932         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) != rx_ring->cnsmr_idx) {
1933                 QPRINTK(qdev, INTR, INFO, "Waking handler for rx_ring[0].\n");
1934                 ql_disable_completion_interrupt(qdev, intr_context->intr);
1935                 queue_delayed_work_on(smp_processor_id(), qdev->q_workqueue,
1936                                       &rx_ring->rx_work, 0);
1937                 work_done++;
1938         }
1939
1940         if (!test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
1941                 /*
1942                  * Start the DPC for each active queue.
1943                  */
1944                 for (i = 1; i < qdev->rx_ring_count; i++) {
1945                         rx_ring = &qdev->rx_ring[i];
1946                         if (ql_read_sh_reg(rx_ring->prod_idx_sh_reg) !=
1947                             rx_ring->cnsmr_idx) {
1948                                 QPRINTK(qdev, INTR, INFO,
1949                                         "Waking handler for rx_ring[%d].\n", i);
1950                                 ql_disable_completion_interrupt(qdev,
1951                                                                 intr_context->
1952                                                                 intr);
1953                                 if (i < qdev->rss_ring_first_cq_id)
1954                                         queue_delayed_work_on(rx_ring->cpu,
1955                                                               qdev->q_workqueue,
1956                                                               &rx_ring->rx_work,
1957                                                               0);
1958                                 else
1959                                         napi_schedule(&rx_ring->napi);
1960                                 work_done++;
1961                         }
1962                 }
1963         }
1964         ql_enable_completion_interrupt(qdev, intr_context->intr);
1965         return work_done ? IRQ_HANDLED : IRQ_NONE;
1966 }
1967
1968 static int ql_tso(struct sk_buff *skb, struct ob_mac_tso_iocb_req *mac_iocb_ptr)
1969 {
1970
1971         if (skb_is_gso(skb)) {
1972                 int err;
1973                 if (skb_header_cloned(skb)) {
1974                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
1975                         if (err)
1976                                 return err;
1977                 }
1978
1979                 mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
1980                 mac_iocb_ptr->flags3 |= OB_MAC_TSO_IOCB_IC;
1981                 mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
1982                 mac_iocb_ptr->total_hdrs_len =
1983                     cpu_to_le16(skb_transport_offset(skb) + tcp_hdrlen(skb));
1984                 mac_iocb_ptr->net_trans_offset =
1985                     cpu_to_le16(skb_network_offset(skb) |
1986                                 skb_transport_offset(skb)
1987                                 << OB_MAC_TRANSPORT_HDR_SHIFT);
1988                 mac_iocb_ptr->mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
1989                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_LSO;
1990                 if (likely(skb->protocol == htons(ETH_P_IP))) {
1991                         struct iphdr *iph = ip_hdr(skb);
1992                         iph->check = 0;
1993                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
1994                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
1995                                                                  iph->daddr, 0,
1996                                                                  IPPROTO_TCP,
1997                                                                  0);
1998                 } else if (skb->protocol == htons(ETH_P_IPV6)) {
1999                         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP6;
2000                         tcp_hdr(skb)->check =
2001                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
2002                                              &ipv6_hdr(skb)->daddr,
2003                                              0, IPPROTO_TCP, 0);
2004                 }
2005                 return 1;
2006         }
2007         return 0;
2008 }
2009
2010 static void ql_hw_csum_setup(struct sk_buff *skb,
2011                              struct ob_mac_tso_iocb_req *mac_iocb_ptr)
2012 {
2013         int len;
2014         struct iphdr *iph = ip_hdr(skb);
2015         __sum16 *check;
2016         mac_iocb_ptr->opcode = OPCODE_OB_MAC_TSO_IOCB;
2017         mac_iocb_ptr->frame_len = cpu_to_le32((u32) skb->len);
2018         mac_iocb_ptr->net_trans_offset =
2019                 cpu_to_le16(skb_network_offset(skb) |
2020                 skb_transport_offset(skb) << OB_MAC_TRANSPORT_HDR_SHIFT);
2021
2022         mac_iocb_ptr->flags1 |= OB_MAC_TSO_IOCB_IP4;
2023         len = (ntohs(iph->tot_len) - (iph->ihl << 2));
2024         if (likely(iph->protocol == IPPROTO_TCP)) {
2025                 check = &(tcp_hdr(skb)->check);
2026                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_TC;
2027                 mac_iocb_ptr->total_hdrs_len =
2028                     cpu_to_le16(skb_transport_offset(skb) +
2029                                 (tcp_hdr(skb)->doff << 2));
2030         } else {
2031                 check = &(udp_hdr(skb)->check);
2032                 mac_iocb_ptr->flags2 |= OB_MAC_TSO_IOCB_UC;
2033                 mac_iocb_ptr->total_hdrs_len =
2034                     cpu_to_le16(skb_transport_offset(skb) +
2035                                 sizeof(struct udphdr));
2036         }
2037         *check = ~csum_tcpudp_magic(iph->saddr,
2038                                     iph->daddr, len, iph->protocol, 0);
2039 }
2040
2041 static int qlge_send(struct sk_buff *skb, struct net_device *ndev)
2042 {
2043         struct tx_ring_desc *tx_ring_desc;
2044         struct ob_mac_iocb_req *mac_iocb_ptr;
2045         struct ql_adapter *qdev = netdev_priv(ndev);
2046         int tso;
2047         struct tx_ring *tx_ring;
2048         u32 tx_ring_idx = (u32) QL_TXQ_IDX(qdev, skb);
2049
2050         tx_ring = &qdev->tx_ring[tx_ring_idx];
2051
2052         if (unlikely(atomic_read(&tx_ring->tx_count) < 2)) {
2053                 QPRINTK(qdev, TX_QUEUED, INFO,
2054                         "%s: shutting down tx queue %d du to lack of resources.\n",
2055                         __func__, tx_ring_idx);
2056                 netif_stop_queue(ndev);
2057                 atomic_inc(&tx_ring->queue_stopped);
2058                 return NETDEV_TX_BUSY;
2059         }
2060         tx_ring_desc = &tx_ring->q[tx_ring->prod_idx];
2061         mac_iocb_ptr = tx_ring_desc->queue_entry;
2062         memset((void *)mac_iocb_ptr, 0, sizeof(mac_iocb_ptr));
2063
2064         mac_iocb_ptr->opcode = OPCODE_OB_MAC_IOCB;
2065         mac_iocb_ptr->tid = tx_ring_desc->index;
2066         /* We use the upper 32-bits to store the tx queue for this IO.
2067          * When we get the completion we can use it to establish the context.
2068          */
2069         mac_iocb_ptr->txq_idx = tx_ring_idx;
2070         tx_ring_desc->skb = skb;
2071
2072         mac_iocb_ptr->frame_len = cpu_to_le16((u16) skb->len);
2073
2074         if (qdev->vlgrp && vlan_tx_tag_present(skb)) {
2075                 QPRINTK(qdev, TX_QUEUED, DEBUG, "Adding a vlan tag %d.\n",
2076                         vlan_tx_tag_get(skb));
2077                 mac_iocb_ptr->flags3 |= OB_MAC_IOCB_V;
2078                 mac_iocb_ptr->vlan_tci = cpu_to_le16(vlan_tx_tag_get(skb));
2079         }
2080         tso = ql_tso(skb, (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2081         if (tso < 0) {
2082                 dev_kfree_skb_any(skb);
2083                 return NETDEV_TX_OK;
2084         } else if (unlikely(!tso) && (skb->ip_summed == CHECKSUM_PARTIAL)) {
2085                 ql_hw_csum_setup(skb,
2086                                  (struct ob_mac_tso_iocb_req *)mac_iocb_ptr);
2087         }
2088         if (ql_map_send(qdev, mac_iocb_ptr, skb, tx_ring_desc) !=
2089                         NETDEV_TX_OK) {
2090                 QPRINTK(qdev, TX_QUEUED, ERR,
2091                                 "Could not map the segments.\n");
2092                 return NETDEV_TX_BUSY;
2093         }
2094         QL_DUMP_OB_MAC_IOCB(mac_iocb_ptr);
2095         tx_ring->prod_idx++;
2096         if (tx_ring->prod_idx == tx_ring->wq_len)
2097                 tx_ring->prod_idx = 0;
2098         wmb();
2099
2100         ql_write_db_reg(tx_ring->prod_idx, tx_ring->prod_idx_db_reg);
2101         ndev->trans_start = jiffies;
2102         QPRINTK(qdev, TX_QUEUED, DEBUG, "tx queued, slot %d, len %d\n",
2103                 tx_ring->prod_idx, skb->len);
2104
2105         atomic_dec(&tx_ring->tx_count);
2106         return NETDEV_TX_OK;
2107 }
2108
2109 static void ql_free_shadow_space(struct ql_adapter *qdev)
2110 {
2111         if (qdev->rx_ring_shadow_reg_area) {
2112                 pci_free_consistent(qdev->pdev,
2113                                     PAGE_SIZE,
2114                                     qdev->rx_ring_shadow_reg_area,
2115                                     qdev->rx_ring_shadow_reg_dma);
2116                 qdev->rx_ring_shadow_reg_area = NULL;
2117         }
2118         if (qdev->tx_ring_shadow_reg_area) {
2119                 pci_free_consistent(qdev->pdev,
2120                                     PAGE_SIZE,
2121                                     qdev->tx_ring_shadow_reg_area,
2122                                     qdev->tx_ring_shadow_reg_dma);
2123                 qdev->tx_ring_shadow_reg_area = NULL;
2124         }
2125 }
2126
2127 static int ql_alloc_shadow_space(struct ql_adapter *qdev)
2128 {
2129         qdev->rx_ring_shadow_reg_area =
2130             pci_alloc_consistent(qdev->pdev,
2131                                  PAGE_SIZE, &qdev->rx_ring_shadow_reg_dma);
2132         if (qdev->rx_ring_shadow_reg_area == NULL) {
2133                 QPRINTK(qdev, IFUP, ERR,
2134                         "Allocation of RX shadow space failed.\n");
2135                 return -ENOMEM;
2136         }
2137         qdev->tx_ring_shadow_reg_area =
2138             pci_alloc_consistent(qdev->pdev, PAGE_SIZE,
2139                                  &qdev->tx_ring_shadow_reg_dma);
2140         if (qdev->tx_ring_shadow_reg_area == NULL) {
2141                 QPRINTK(qdev, IFUP, ERR,
2142                         "Allocation of TX shadow space failed.\n");
2143                 goto err_wqp_sh_area;
2144         }
2145         return 0;
2146
2147 err_wqp_sh_area:
2148         pci_free_consistent(qdev->pdev,
2149                             PAGE_SIZE,
2150                             qdev->rx_ring_shadow_reg_area,
2151                             qdev->rx_ring_shadow_reg_dma);
2152         return -ENOMEM;
2153 }
2154
2155 static void ql_init_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2156 {
2157         struct tx_ring_desc *tx_ring_desc;
2158         int i;
2159         struct ob_mac_iocb_req *mac_iocb_ptr;
2160
2161         mac_iocb_ptr = tx_ring->wq_base;
2162         tx_ring_desc = tx_ring->q;
2163         for (i = 0; i < tx_ring->wq_len; i++) {
2164                 tx_ring_desc->index = i;
2165                 tx_ring_desc->skb = NULL;
2166                 tx_ring_desc->queue_entry = mac_iocb_ptr;
2167                 mac_iocb_ptr++;
2168                 tx_ring_desc++;
2169         }
2170         atomic_set(&tx_ring->tx_count, tx_ring->wq_len);
2171         atomic_set(&tx_ring->queue_stopped, 0);
2172 }
2173
2174 static void ql_free_tx_resources(struct ql_adapter *qdev,
2175                                  struct tx_ring *tx_ring)
2176 {
2177         if (tx_ring->wq_base) {
2178                 pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2179                                     tx_ring->wq_base, tx_ring->wq_base_dma);
2180                 tx_ring->wq_base = NULL;
2181         }
2182         kfree(tx_ring->q);
2183         tx_ring->q = NULL;
2184 }
2185
2186 static int ql_alloc_tx_resources(struct ql_adapter *qdev,
2187                                  struct tx_ring *tx_ring)
2188 {
2189         tx_ring->wq_base =
2190             pci_alloc_consistent(qdev->pdev, tx_ring->wq_size,
2191                                  &tx_ring->wq_base_dma);
2192
2193         if ((tx_ring->wq_base == NULL)
2194             || tx_ring->wq_base_dma & (tx_ring->wq_size - 1)) {
2195                 QPRINTK(qdev, IFUP, ERR, "tx_ring alloc failed.\n");
2196                 return -ENOMEM;
2197         }
2198         tx_ring->q =
2199             kmalloc(tx_ring->wq_len * sizeof(struct tx_ring_desc), GFP_KERNEL);
2200         if (tx_ring->q == NULL)
2201                 goto err;
2202
2203         return 0;
2204 err:
2205         pci_free_consistent(qdev->pdev, tx_ring->wq_size,
2206                             tx_ring->wq_base, tx_ring->wq_base_dma);
2207         return -ENOMEM;
2208 }
2209
2210 static void ql_free_lbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2211 {
2212         int i;
2213         struct bq_desc *lbq_desc;
2214
2215         for (i = 0; i < rx_ring->lbq_len; i++) {
2216                 lbq_desc = &rx_ring->lbq[i];
2217                 if (lbq_desc->p.lbq_page) {
2218                         pci_unmap_page(qdev->pdev,
2219                                        pci_unmap_addr(lbq_desc, mapaddr),
2220                                        pci_unmap_len(lbq_desc, maplen),
2221                                        PCI_DMA_FROMDEVICE);
2222
2223                         put_page(lbq_desc->p.lbq_page);
2224                         lbq_desc->p.lbq_page = NULL;
2225                 }
2226         }
2227 }
2228
2229 static void ql_free_sbq_buffers(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2230 {
2231         int i;
2232         struct bq_desc *sbq_desc;
2233
2234         for (i = 0; i < rx_ring->sbq_len; i++) {
2235                 sbq_desc = &rx_ring->sbq[i];
2236                 if (sbq_desc == NULL) {
2237                         QPRINTK(qdev, IFUP, ERR, "sbq_desc %d is NULL.\n", i);
2238                         return;
2239                 }
2240                 if (sbq_desc->p.skb) {
2241                         pci_unmap_single(qdev->pdev,
2242                                          pci_unmap_addr(sbq_desc, mapaddr),
2243                                          pci_unmap_len(sbq_desc, maplen),
2244                                          PCI_DMA_FROMDEVICE);
2245                         dev_kfree_skb(sbq_desc->p.skb);
2246                         sbq_desc->p.skb = NULL;
2247                 }
2248         }
2249 }
2250
2251 /* Free all large and small rx buffers associated
2252  * with the completion queues for this device.
2253  */
2254 static void ql_free_rx_buffers(struct ql_adapter *qdev)
2255 {
2256         int i;
2257         struct rx_ring *rx_ring;
2258
2259         for (i = 0; i < qdev->rx_ring_count; i++) {
2260                 rx_ring = &qdev->rx_ring[i];
2261                 if (rx_ring->lbq)
2262                         ql_free_lbq_buffers(qdev, rx_ring);
2263                 if (rx_ring->sbq)
2264                         ql_free_sbq_buffers(qdev, rx_ring);
2265         }
2266 }
2267
2268 static void ql_alloc_rx_buffers(struct ql_adapter *qdev)
2269 {
2270         struct rx_ring *rx_ring;
2271         int i;
2272
2273         for (i = 0; i < qdev->rx_ring_count; i++) {
2274                 rx_ring = &qdev->rx_ring[i];
2275                 if (rx_ring->type != TX_Q)
2276                         ql_update_buffer_queues(qdev, rx_ring);
2277         }
2278 }
2279
2280 static void ql_init_lbq_ring(struct ql_adapter *qdev,
2281                                 struct rx_ring *rx_ring)
2282 {
2283         int i;
2284         struct bq_desc *lbq_desc;
2285         __le64 *bq = rx_ring->lbq_base;
2286
2287         memset(rx_ring->lbq, 0, rx_ring->lbq_len * sizeof(struct bq_desc));
2288         for (i = 0; i < rx_ring->lbq_len; i++) {
2289                 lbq_desc = &rx_ring->lbq[i];
2290                 memset(lbq_desc, 0, sizeof(*lbq_desc));
2291                 lbq_desc->index = i;
2292                 lbq_desc->addr = bq;
2293                 bq++;
2294         }
2295 }
2296
2297 static void ql_init_sbq_ring(struct ql_adapter *qdev,
2298                                 struct rx_ring *rx_ring)
2299 {
2300         int i;
2301         struct bq_desc *sbq_desc;
2302         __le64 *bq = rx_ring->sbq_base;
2303
2304         memset(rx_ring->sbq, 0, rx_ring->sbq_len * sizeof(struct bq_desc));
2305         for (i = 0; i < rx_ring->sbq_len; i++) {
2306                 sbq_desc = &rx_ring->sbq[i];
2307                 memset(sbq_desc, 0, sizeof(*sbq_desc));
2308                 sbq_desc->index = i;
2309                 sbq_desc->addr = bq;
2310                 bq++;
2311         }
2312 }
2313
2314 static void ql_free_rx_resources(struct ql_adapter *qdev,
2315                                  struct rx_ring *rx_ring)
2316 {
2317         /* Free the small buffer queue. */
2318         if (rx_ring->sbq_base) {
2319                 pci_free_consistent(qdev->pdev,
2320                                     rx_ring->sbq_size,
2321                                     rx_ring->sbq_base, rx_ring->sbq_base_dma);
2322                 rx_ring->sbq_base = NULL;
2323         }
2324
2325         /* Free the small buffer queue control blocks. */
2326         kfree(rx_ring->sbq);
2327         rx_ring->sbq = NULL;
2328
2329         /* Free the large buffer queue. */
2330         if (rx_ring->lbq_base) {
2331                 pci_free_consistent(qdev->pdev,
2332                                     rx_ring->lbq_size,
2333                                     rx_ring->lbq_base, rx_ring->lbq_base_dma);
2334                 rx_ring->lbq_base = NULL;
2335         }
2336
2337         /* Free the large buffer queue control blocks. */
2338         kfree(rx_ring->lbq);
2339         rx_ring->lbq = NULL;
2340
2341         /* Free the rx queue. */
2342         if (rx_ring->cq_base) {
2343                 pci_free_consistent(qdev->pdev,
2344                                     rx_ring->cq_size,
2345                                     rx_ring->cq_base, rx_ring->cq_base_dma);
2346                 rx_ring->cq_base = NULL;
2347         }
2348 }
2349
2350 /* Allocate queues and buffers for this completions queue based
2351  * on the values in the parameter structure. */
2352 static int ql_alloc_rx_resources(struct ql_adapter *qdev,
2353                                  struct rx_ring *rx_ring)
2354 {
2355
2356         /*
2357          * Allocate the completion queue for this rx_ring.
2358          */
2359         rx_ring->cq_base =
2360             pci_alloc_consistent(qdev->pdev, rx_ring->cq_size,
2361                                  &rx_ring->cq_base_dma);
2362
2363         if (rx_ring->cq_base == NULL) {
2364                 QPRINTK(qdev, IFUP, ERR, "rx_ring alloc failed.\n");
2365                 return -ENOMEM;
2366         }
2367
2368         if (rx_ring->sbq_len) {
2369                 /*
2370                  * Allocate small buffer queue.
2371                  */
2372                 rx_ring->sbq_base =
2373                     pci_alloc_consistent(qdev->pdev, rx_ring->sbq_size,
2374                                          &rx_ring->sbq_base_dma);
2375
2376                 if (rx_ring->sbq_base == NULL) {
2377                         QPRINTK(qdev, IFUP, ERR,
2378                                 "Small buffer queue allocation failed.\n");
2379                         goto err_mem;
2380                 }
2381
2382                 /*
2383                  * Allocate small buffer queue control blocks.
2384                  */
2385                 rx_ring->sbq =
2386                     kmalloc(rx_ring->sbq_len * sizeof(struct bq_desc),
2387                             GFP_KERNEL);
2388                 if (rx_ring->sbq == NULL) {
2389                         QPRINTK(qdev, IFUP, ERR,
2390                                 "Small buffer queue control block allocation failed.\n");
2391                         goto err_mem;
2392                 }
2393
2394                 ql_init_sbq_ring(qdev, rx_ring);
2395         }
2396
2397         if (rx_ring->lbq_len) {
2398                 /*
2399                  * Allocate large buffer queue.
2400                  */
2401                 rx_ring->lbq_base =
2402                     pci_alloc_consistent(qdev->pdev, rx_ring->lbq_size,
2403                                          &rx_ring->lbq_base_dma);
2404
2405                 if (rx_ring->lbq_base == NULL) {
2406                         QPRINTK(qdev, IFUP, ERR,
2407                                 "Large buffer queue allocation failed.\n");
2408                         goto err_mem;
2409                 }
2410                 /*
2411                  * Allocate large buffer queue control blocks.
2412                  */
2413                 rx_ring->lbq =
2414                     kmalloc(rx_ring->lbq_len * sizeof(struct bq_desc),
2415                             GFP_KERNEL);
2416                 if (rx_ring->lbq == NULL) {
2417                         QPRINTK(qdev, IFUP, ERR,
2418                                 "Large buffer queue control block allocation failed.\n");
2419                         goto err_mem;
2420                 }
2421
2422                 ql_init_lbq_ring(qdev, rx_ring);
2423         }
2424
2425         return 0;
2426
2427 err_mem:
2428         ql_free_rx_resources(qdev, rx_ring);
2429         return -ENOMEM;
2430 }
2431
2432 static void ql_tx_ring_clean(struct ql_adapter *qdev)
2433 {
2434         struct tx_ring *tx_ring;
2435         struct tx_ring_desc *tx_ring_desc;
2436         int i, j;
2437
2438         /*
2439          * Loop through all queues and free
2440          * any resources.
2441          */
2442         for (j = 0; j < qdev->tx_ring_count; j++) {
2443                 tx_ring = &qdev->tx_ring[j];
2444                 for (i = 0; i < tx_ring->wq_len; i++) {
2445                         tx_ring_desc = &tx_ring->q[i];
2446                         if (tx_ring_desc && tx_ring_desc->skb) {
2447                                 QPRINTK(qdev, IFDOWN, ERR,
2448                                 "Freeing lost SKB %p, from queue %d, index %d.\n",
2449                                         tx_ring_desc->skb, j,
2450                                         tx_ring_desc->index);
2451                                 ql_unmap_send(qdev, tx_ring_desc,
2452                                               tx_ring_desc->map_cnt);
2453                                 dev_kfree_skb(tx_ring_desc->skb);
2454                                 tx_ring_desc->skb = NULL;
2455                         }
2456                 }
2457         }
2458 }
2459
2460 static void ql_free_mem_resources(struct ql_adapter *qdev)
2461 {
2462         int i;
2463
2464         for (i = 0; i < qdev->tx_ring_count; i++)
2465                 ql_free_tx_resources(qdev, &qdev->tx_ring[i]);
2466         for (i = 0; i < qdev->rx_ring_count; i++)
2467                 ql_free_rx_resources(qdev, &qdev->rx_ring[i]);
2468         ql_free_shadow_space(qdev);
2469 }
2470
2471 static int ql_alloc_mem_resources(struct ql_adapter *qdev)
2472 {
2473         int i;
2474
2475         /* Allocate space for our shadow registers and such. */
2476         if (ql_alloc_shadow_space(qdev))
2477                 return -ENOMEM;
2478
2479         for (i = 0; i < qdev->rx_ring_count; i++) {
2480                 if (ql_alloc_rx_resources(qdev, &qdev->rx_ring[i]) != 0) {
2481                         QPRINTK(qdev, IFUP, ERR,
2482                                 "RX resource allocation failed.\n");
2483                         goto err_mem;
2484                 }
2485         }
2486         /* Allocate tx queue resources */
2487         for (i = 0; i < qdev->tx_ring_count; i++) {
2488                 if (ql_alloc_tx_resources(qdev, &qdev->tx_ring[i]) != 0) {
2489                         QPRINTK(qdev, IFUP, ERR,
2490                                 "TX resource allocation failed.\n");
2491                         goto err_mem;
2492                 }
2493         }
2494         return 0;
2495
2496 err_mem:
2497         ql_free_mem_resources(qdev);
2498         return -ENOMEM;
2499 }
2500
2501 /* Set up the rx ring control block and pass it to the chip.
2502  * The control block is defined as
2503  * "Completion Queue Initialization Control Block", or cqicb.
2504  */
2505 static int ql_start_rx_ring(struct ql_adapter *qdev, struct rx_ring *rx_ring)
2506 {
2507         struct cqicb *cqicb = &rx_ring->cqicb;
2508         void *shadow_reg = qdev->rx_ring_shadow_reg_area +
2509             (rx_ring->cq_id * sizeof(u64) * 4);
2510         u64 shadow_reg_dma = qdev->rx_ring_shadow_reg_dma +
2511             (rx_ring->cq_id * sizeof(u64) * 4);
2512         void __iomem *doorbell_area =
2513             qdev->doorbell_area + (DB_PAGE_SIZE * (128 + rx_ring->cq_id));
2514         int err = 0;
2515         u16 bq_len;
2516
2517         /* Set up the shadow registers for this ring. */
2518         rx_ring->prod_idx_sh_reg = shadow_reg;
2519         rx_ring->prod_idx_sh_reg_dma = shadow_reg_dma;
2520         shadow_reg += sizeof(u64);
2521         shadow_reg_dma += sizeof(u64);
2522         rx_ring->lbq_base_indirect = shadow_reg;
2523         rx_ring->lbq_base_indirect_dma = shadow_reg_dma;
2524         shadow_reg += sizeof(u64);
2525         shadow_reg_dma += sizeof(u64);
2526         rx_ring->sbq_base_indirect = shadow_reg;
2527         rx_ring->sbq_base_indirect_dma = shadow_reg_dma;
2528
2529         /* PCI doorbell mem area + 0x00 for consumer index register */
2530         rx_ring->cnsmr_idx_db_reg = (u32 __iomem *) doorbell_area;
2531         rx_ring->cnsmr_idx = 0;
2532         rx_ring->curr_entry = rx_ring->cq_base;
2533
2534         /* PCI doorbell mem area + 0x04 for valid register */
2535         rx_ring->valid_db_reg = doorbell_area + 0x04;
2536
2537         /* PCI doorbell mem area + 0x18 for large buffer consumer */
2538         rx_ring->lbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x18);
2539
2540         /* PCI doorbell mem area + 0x1c */
2541         rx_ring->sbq_prod_idx_db_reg = (u32 __iomem *) (doorbell_area + 0x1c);
2542
2543         memset((void *)cqicb, 0, sizeof(struct cqicb));
2544         cqicb->msix_vect = rx_ring->irq;
2545
2546         bq_len = (rx_ring->cq_len == 65536) ? 0 : (u16) rx_ring->cq_len;
2547         cqicb->len = cpu_to_le16(bq_len | LEN_V | LEN_CPP_CONT);
2548
2549         cqicb->addr = cpu_to_le64(rx_ring->cq_base_dma);
2550
2551         cqicb->prod_idx_addr = cpu_to_le64(rx_ring->prod_idx_sh_reg_dma);
2552
2553         /*
2554          * Set up the control block load flags.
2555          */
2556         cqicb->flags = FLAGS_LC |       /* Load queue base address */
2557             FLAGS_LV |          /* Load MSI-X vector */
2558             FLAGS_LI;           /* Load irq delay values */
2559         if (rx_ring->lbq_len) {
2560                 cqicb->flags |= FLAGS_LL;       /* Load lbq values */
2561                 *((u64 *) rx_ring->lbq_base_indirect) = rx_ring->lbq_base_dma;
2562                 cqicb->lbq_addr =
2563                     cpu_to_le64(rx_ring->lbq_base_indirect_dma);
2564                 bq_len = (rx_ring->lbq_buf_size == 65536) ? 0 :
2565                         (u16) rx_ring->lbq_buf_size;
2566                 cqicb->lbq_buf_size = cpu_to_le16(bq_len);
2567                 bq_len = (rx_ring->lbq_len == 65536) ? 0 :
2568                         (u16) rx_ring->lbq_len;
2569                 cqicb->lbq_len = cpu_to_le16(bq_len);
2570                 rx_ring->lbq_prod_idx = 0;
2571                 rx_ring->lbq_curr_idx = 0;
2572                 rx_ring->lbq_clean_idx = 0;
2573                 rx_ring->lbq_free_cnt = rx_ring->lbq_len;
2574         }
2575         if (rx_ring->sbq_len) {
2576                 cqicb->flags |= FLAGS_LS;       /* Load sbq values */
2577                 *((u64 *) rx_ring->sbq_base_indirect) = rx_ring->sbq_base_dma;
2578                 cqicb->sbq_addr =
2579                     cpu_to_le64(rx_ring->sbq_base_indirect_dma);
2580                 cqicb->sbq_buf_size =
2581                     cpu_to_le16(((rx_ring->sbq_buf_size / 2) + 8) & 0xfffffff8);
2582                 bq_len = (rx_ring->sbq_len == 65536) ? 0 :
2583                         (u16) rx_ring->sbq_len;
2584                 cqicb->sbq_len = cpu_to_le16(bq_len);
2585                 rx_ring->sbq_prod_idx = 0;
2586                 rx_ring->sbq_curr_idx = 0;
2587                 rx_ring->sbq_clean_idx = 0;
2588                 rx_ring->sbq_free_cnt = rx_ring->sbq_len;
2589         }
2590         switch (rx_ring->type) {
2591         case TX_Q:
2592                 /* If there's only one interrupt, then we use
2593                  * worker threads to process the outbound
2594                  * completion handling rx_rings. We do this so
2595                  * they can be run on multiple CPUs. There is
2596                  * room to play with this more where we would only
2597                  * run in a worker if there are more than x number
2598                  * of outbound completions on the queue and more
2599                  * than one queue active.  Some threshold that
2600                  * would indicate a benefit in spite of the cost
2601                  * of a context switch.
2602                  * If there's more than one interrupt, then the
2603                  * outbound completions are processed in the ISR.
2604                  */
2605                 if (!test_bit(QL_MSIX_ENABLED, &qdev->flags))
2606                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2607                 else {
2608                         /* With all debug warnings on we see a WARN_ON message
2609                          * when we free the skb in the interrupt context.
2610                          */
2611                         INIT_DELAYED_WORK(&rx_ring->rx_work, ql_tx_clean);
2612                 }
2613                 cqicb->irq_delay = cpu_to_le16(qdev->tx_coalesce_usecs);
2614                 cqicb->pkt_delay = cpu_to_le16(qdev->tx_max_coalesced_frames);
2615                 break;
2616         case DEFAULT_Q:
2617                 INIT_DELAYED_WORK(&rx_ring->rx_work, ql_rx_clean);
2618                 cqicb->irq_delay = 0;
2619                 cqicb->pkt_delay = 0;
2620                 break;
2621         case RX_Q:
2622                 /* Inbound completion handling rx_rings run in
2623                  * separate NAPI contexts.
2624                  */
2625                 netif_napi_add(qdev->ndev, &rx_ring->napi, ql_napi_poll_msix,
2626                                64);
2627                 cqicb->irq_delay = cpu_to_le16(qdev->rx_coalesce_usecs);
2628                 cqicb->pkt_delay = cpu_to_le16(qdev->rx_max_coalesced_frames);
2629                 break;
2630         default:
2631                 QPRINTK(qdev, IFUP, DEBUG, "Invalid rx_ring->type = %d.\n",
2632                         rx_ring->type);
2633         }
2634         QPRINTK(qdev, IFUP, DEBUG, "Initializing rx work queue.\n");
2635         err = ql_write_cfg(qdev, cqicb, sizeof(struct cqicb),
2636                            CFG_LCQ, rx_ring->cq_id);
2637         if (err) {
2638                 QPRINTK(qdev, IFUP, ERR, "Failed to load CQICB.\n");
2639                 return err;
2640         }
2641         return err;
2642 }
2643
2644 static int ql_start_tx_ring(struct ql_adapter *qdev, struct tx_ring *tx_ring)
2645 {
2646         struct wqicb *wqicb = (struct wqicb *)tx_ring;
2647         void __iomem *doorbell_area =
2648             qdev->doorbell_area + (DB_PAGE_SIZE * tx_ring->wq_id);
2649         void *shadow_reg = qdev->tx_ring_shadow_reg_area +
2650             (tx_ring->wq_id * sizeof(u64));
2651         u64 shadow_reg_dma = qdev->tx_ring_shadow_reg_dma +
2652             (tx_ring->wq_id * sizeof(u64));
2653         int err = 0;
2654
2655         /*
2656          * Assign doorbell registers for this tx_ring.
2657          */
2658         /* TX PCI doorbell mem area for tx producer index */
2659         tx_ring->prod_idx_db_reg = (u32 __iomem *) doorbell_area;
2660         tx_ring->prod_idx = 0;
2661         /* TX PCI doorbell mem area + 0x04 */
2662         tx_ring->valid_db_reg = doorbell_area + 0x04;
2663
2664         /*
2665          * Assign shadow registers for this tx_ring.
2666          */
2667         tx_ring->cnsmr_idx_sh_reg = shadow_reg;
2668         tx_ring->cnsmr_idx_sh_reg_dma = shadow_reg_dma;
2669
2670         wqicb->len = cpu_to_le16(tx_ring->wq_len | Q_LEN_V | Q_LEN_CPP_CONT);
2671         wqicb->flags = cpu_to_le16(Q_FLAGS_LC |
2672                                    Q_FLAGS_LB | Q_FLAGS_LI | Q_FLAGS_LO);
2673         wqicb->cq_id_rss = cpu_to_le16(tx_ring->cq_id);
2674         wqicb->rid = 0;
2675         wqicb->addr = cpu_to_le64(tx_ring->wq_base_dma);
2676
2677         wqicb->cnsmr_idx_addr = cpu_to_le64(tx_ring->cnsmr_idx_sh_reg_dma);
2678
2679         ql_init_tx_ring(qdev, tx_ring);
2680
2681         err = ql_write_cfg(qdev, wqicb, sizeof(wqicb), CFG_LRQ,
2682                            (u16) tx_ring->wq_id);
2683         if (err) {
2684                 QPRINTK(qdev, IFUP, ERR, "Failed to load tx_ring.\n");
2685                 return err;
2686         }
2687         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded WQICB.\n");
2688         return err;
2689 }
2690
2691 static void ql_disable_msix(struct ql_adapter *qdev)
2692 {
2693         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2694                 pci_disable_msix(qdev->pdev);
2695                 clear_bit(QL_MSIX_ENABLED, &qdev->flags);
2696                 kfree(qdev->msi_x_entry);
2697                 qdev->msi_x_entry = NULL;
2698         } else if (test_bit(QL_MSI_ENABLED, &qdev->flags)) {
2699                 pci_disable_msi(qdev->pdev);
2700                 clear_bit(QL_MSI_ENABLED, &qdev->flags);
2701         }
2702 }
2703
2704 static void ql_enable_msix(struct ql_adapter *qdev)
2705 {
2706         int i;
2707
2708         qdev->intr_count = 1;
2709         /* Get the MSIX vectors. */
2710         if (irq_type == MSIX_IRQ) {
2711                 /* Try to alloc space for the msix struct,
2712                  * if it fails then go to MSI/legacy.
2713                  */
2714                 qdev->msi_x_entry = kcalloc(qdev->rx_ring_count,
2715                                             sizeof(struct msix_entry),
2716                                             GFP_KERNEL);
2717                 if (!qdev->msi_x_entry) {
2718                         irq_type = MSI_IRQ;
2719                         goto msi;
2720                 }
2721
2722                 for (i = 0; i < qdev->rx_ring_count; i++)
2723                         qdev->msi_x_entry[i].entry = i;
2724
2725                 if (!pci_enable_msix
2726                     (qdev->pdev, qdev->msi_x_entry, qdev->rx_ring_count)) {
2727                         set_bit(QL_MSIX_ENABLED, &qdev->flags);
2728                         qdev->intr_count = qdev->rx_ring_count;
2729                         QPRINTK(qdev, IFUP, DEBUG,
2730                                 "MSI-X Enabled, got %d vectors.\n",
2731                                 qdev->intr_count);
2732                         return;
2733                 } else {
2734                         kfree(qdev->msi_x_entry);
2735                         qdev->msi_x_entry = NULL;
2736                         QPRINTK(qdev, IFUP, WARNING,
2737                                 "MSI-X Enable failed, trying MSI.\n");
2738                         irq_type = MSI_IRQ;
2739                 }
2740         }
2741 msi:
2742         if (irq_type == MSI_IRQ) {
2743                 if (!pci_enable_msi(qdev->pdev)) {
2744                         set_bit(QL_MSI_ENABLED, &qdev->flags);
2745                         QPRINTK(qdev, IFUP, INFO,
2746                                 "Running with MSI interrupts.\n");
2747                         return;
2748                 }
2749         }
2750         irq_type = LEG_IRQ;
2751         QPRINTK(qdev, IFUP, DEBUG, "Running with legacy interrupts.\n");
2752 }
2753
2754 /*
2755  * Here we build the intr_context structures based on
2756  * our rx_ring count and intr vector count.
2757  * The intr_context structure is used to hook each vector
2758  * to possibly different handlers.
2759  */
2760 static void ql_resolve_queues_to_irqs(struct ql_adapter *qdev)
2761 {
2762         int i = 0;
2763         struct intr_context *intr_context = &qdev->intr_context[0];
2764
2765         ql_enable_msix(qdev);
2766
2767         if (likely(test_bit(QL_MSIX_ENABLED, &qdev->flags))) {
2768                 /* Each rx_ring has it's
2769                  * own intr_context since we have separate
2770                  * vectors for each queue.
2771                  * This only true when MSI-X is enabled.
2772                  */
2773                 for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2774                         qdev->rx_ring[i].irq = i;
2775                         intr_context->intr = i;
2776                         intr_context->qdev = qdev;
2777                         /*
2778                          * We set up each vectors enable/disable/read bits so
2779                          * there's no bit/mask calculations in the critical path.
2780                          */
2781                         intr_context->intr_en_mask =
2782                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2783                             INTR_EN_TYPE_ENABLE | INTR_EN_IHD_MASK | INTR_EN_IHD
2784                             | i;
2785                         intr_context->intr_dis_mask =
2786                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2787                             INTR_EN_TYPE_DISABLE | INTR_EN_IHD_MASK |
2788                             INTR_EN_IHD | i;
2789                         intr_context->intr_read_mask =
2790                             INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2791                             INTR_EN_TYPE_READ | INTR_EN_IHD_MASK | INTR_EN_IHD |
2792                             i;
2793
2794                         if (i == 0) {
2795                                 /*
2796                                  * Default queue handles bcast/mcast plus
2797                                  * async events.  Needs buffers.
2798                                  */
2799                                 intr_context->handler = qlge_isr;
2800                                 sprintf(intr_context->name, "%s-default-queue",
2801                                         qdev->ndev->name);
2802                         } else if (i < qdev->rss_ring_first_cq_id) {
2803                                 /*
2804                                  * Outbound queue is for outbound completions only.
2805                                  */
2806                                 intr_context->handler = qlge_msix_tx_isr;
2807                                 sprintf(intr_context->name, "%s-tx-%d",
2808                                         qdev->ndev->name, i);
2809                         } else {
2810                                 /*
2811                                  * Inbound queues handle unicast frames only.
2812                                  */
2813                                 intr_context->handler = qlge_msix_rx_isr;
2814                                 sprintf(intr_context->name, "%s-rx-%d",
2815                                         qdev->ndev->name, i);
2816                         }
2817                 }
2818         } else {
2819                 /*
2820                  * All rx_rings use the same intr_context since
2821                  * there is only one vector.
2822                  */
2823                 intr_context->intr = 0;
2824                 intr_context->qdev = qdev;
2825                 /*
2826                  * We set up each vectors enable/disable/read bits so
2827                  * there's no bit/mask calculations in the critical path.
2828                  */
2829                 intr_context->intr_en_mask =
2830                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_ENABLE;
2831                 intr_context->intr_dis_mask =
2832                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK |
2833                     INTR_EN_TYPE_DISABLE;
2834                 intr_context->intr_read_mask =
2835                     INTR_EN_TYPE_MASK | INTR_EN_INTR_MASK | INTR_EN_TYPE_READ;
2836                 /*
2837                  * Single interrupt means one handler for all rings.
2838                  */
2839                 intr_context->handler = qlge_isr;
2840                 sprintf(intr_context->name, "%s-single_irq", qdev->ndev->name);
2841                 for (i = 0; i < qdev->rx_ring_count; i++)
2842                         qdev->rx_ring[i].irq = 0;
2843         }
2844 }
2845
2846 static void ql_free_irq(struct ql_adapter *qdev)
2847 {
2848         int i;
2849         struct intr_context *intr_context = &qdev->intr_context[0];
2850
2851         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2852                 if (intr_context->hooked) {
2853                         if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2854                                 free_irq(qdev->msi_x_entry[i].vector,
2855                                          &qdev->rx_ring[i]);
2856                                 QPRINTK(qdev, IFDOWN, DEBUG,
2857                                         "freeing msix interrupt %d.\n", i);
2858                         } else {
2859                                 free_irq(qdev->pdev->irq, &qdev->rx_ring[0]);
2860                                 QPRINTK(qdev, IFDOWN, DEBUG,
2861                                         "freeing msi interrupt %d.\n", i);
2862                         }
2863                 }
2864         }
2865         ql_disable_msix(qdev);
2866 }
2867
2868 static int ql_request_irq(struct ql_adapter *qdev)
2869 {
2870         int i;
2871         int status = 0;
2872         struct pci_dev *pdev = qdev->pdev;
2873         struct intr_context *intr_context = &qdev->intr_context[0];
2874
2875         ql_resolve_queues_to_irqs(qdev);
2876
2877         for (i = 0; i < qdev->intr_count; i++, intr_context++) {
2878                 atomic_set(&intr_context->irq_cnt, 0);
2879                 if (test_bit(QL_MSIX_ENABLED, &qdev->flags)) {
2880                         status = request_irq(qdev->msi_x_entry[i].vector,
2881                                              intr_context->handler,
2882                                              0,
2883                                              intr_context->name,
2884                                              &qdev->rx_ring[i]);
2885                         if (status) {
2886                                 QPRINTK(qdev, IFUP, ERR,
2887                                         "Failed request for MSIX interrupt %d.\n",
2888                                         i);
2889                                 goto err_irq;
2890                         } else {
2891                                 QPRINTK(qdev, IFUP, DEBUG,
2892                                         "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2893                                         i,
2894                                         qdev->rx_ring[i].type ==
2895                                         DEFAULT_Q ? "DEFAULT_Q" : "",
2896                                         qdev->rx_ring[i].type ==
2897                                         TX_Q ? "TX_Q" : "",
2898                                         qdev->rx_ring[i].type ==
2899                                         RX_Q ? "RX_Q" : "", intr_context->name);
2900                         }
2901                 } else {
2902                         QPRINTK(qdev, IFUP, DEBUG,
2903                                 "trying msi or legacy interrupts.\n");
2904                         QPRINTK(qdev, IFUP, DEBUG,
2905                                 "%s: irq = %d.\n", __func__, pdev->irq);
2906                         QPRINTK(qdev, IFUP, DEBUG,
2907                                 "%s: context->name = %s.\n", __func__,
2908                                intr_context->name);
2909                         QPRINTK(qdev, IFUP, DEBUG,
2910                                 "%s: dev_id = 0x%p.\n", __func__,
2911                                &qdev->rx_ring[0]);
2912                         status =
2913                             request_irq(pdev->irq, qlge_isr,
2914                                         test_bit(QL_MSI_ENABLED,
2915                                                  &qdev->
2916                                                  flags) ? 0 : IRQF_SHARED,
2917                                         intr_context->name, &qdev->rx_ring[0]);
2918                         if (status)
2919                                 goto err_irq;
2920
2921                         QPRINTK(qdev, IFUP, ERR,
2922                                 "Hooked intr %d, queue type %s%s%s, with name %s.\n",
2923                                 i,
2924                                 qdev->rx_ring[0].type ==
2925                                 DEFAULT_Q ? "DEFAULT_Q" : "",
2926                                 qdev->rx_ring[0].type == TX_Q ? "TX_Q" : "",
2927                                 qdev->rx_ring[0].type == RX_Q ? "RX_Q" : "",
2928                                 intr_context->name);
2929                 }
2930                 intr_context->hooked = 1;
2931         }
2932         return status;
2933 err_irq:
2934         QPRINTK(qdev, IFUP, ERR, "Failed to get the interrupts!!!/n");
2935         ql_free_irq(qdev);
2936         return status;
2937 }
2938
2939 static int ql_start_rss(struct ql_adapter *qdev)
2940 {
2941         struct ricb *ricb = &qdev->ricb;
2942         int status = 0;
2943         int i;
2944         u8 *hash_id = (u8 *) ricb->hash_cq_id;
2945
2946         memset((void *)ricb, 0, sizeof(ricb));
2947
2948         ricb->base_cq = qdev->rss_ring_first_cq_id | RSS_L4K;
2949         ricb->flags =
2950             (RSS_L6K | RSS_LI | RSS_LB | RSS_LM | RSS_RI4 | RSS_RI6 | RSS_RT4 |
2951              RSS_RT6);
2952         ricb->mask = cpu_to_le16(qdev->rss_ring_count - 1);
2953
2954         /*
2955          * Fill out the Indirection Table.
2956          */
2957         for (i = 0; i < 256; i++)
2958                 hash_id[i] = i & (qdev->rss_ring_count - 1);
2959
2960         /*
2961          * Random values for the IPv6 and IPv4 Hash Keys.
2962          */
2963         get_random_bytes((void *)&ricb->ipv6_hash_key[0], 40);
2964         get_random_bytes((void *)&ricb->ipv4_hash_key[0], 16);
2965
2966         QPRINTK(qdev, IFUP, DEBUG, "Initializing RSS.\n");
2967
2968         status = ql_write_cfg(qdev, ricb, sizeof(ricb), CFG_LR, 0);
2969         if (status) {
2970                 QPRINTK(qdev, IFUP, ERR, "Failed to load RICB.\n");
2971                 return status;
2972         }
2973         QPRINTK(qdev, IFUP, DEBUG, "Successfully loaded RICB.\n");
2974         return status;
2975 }
2976
2977 /* Initialize the frame-to-queue routing. */
2978 static int ql_route_initialize(struct ql_adapter *qdev)
2979 {
2980         int status = 0;
2981         int i;
2982
2983         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
2984         if (status)
2985                 return status;
2986
2987         /* Clear all the entries in the routing table. */
2988         for (i = 0; i < 16; i++) {
2989                 status = ql_set_routing_reg(qdev, i, 0, 0);
2990                 if (status) {
2991                         QPRINTK(qdev, IFUP, ERR,
2992                                 "Failed to init routing register for CAM packets.\n");
2993                         goto exit;
2994                 }
2995         }
2996
2997         status = ql_set_routing_reg(qdev, RT_IDX_ALL_ERR_SLOT, RT_IDX_ERR, 1);
2998         if (status) {
2999                 QPRINTK(qdev, IFUP, ERR,
3000                         "Failed to init routing register for error packets.\n");
3001                 goto exit;
3002         }
3003         status = ql_set_routing_reg(qdev, RT_IDX_BCAST_SLOT, RT_IDX_BCAST, 1);
3004         if (status) {
3005                 QPRINTK(qdev, IFUP, ERR,
3006                         "Failed to init routing register for broadcast packets.\n");
3007                 goto exit;
3008         }
3009         /* If we have more than one inbound queue, then turn on RSS in the
3010          * routing block.
3011          */
3012         if (qdev->rss_ring_count > 1) {
3013                 status = ql_set_routing_reg(qdev, RT_IDX_RSS_MATCH_SLOT,
3014                                         RT_IDX_RSS_MATCH, 1);
3015                 if (status) {
3016                         QPRINTK(qdev, IFUP, ERR,
3017                                 "Failed to init routing register for MATCH RSS packets.\n");
3018                         goto exit;
3019                 }
3020         }
3021
3022         status = ql_set_routing_reg(qdev, RT_IDX_CAM_HIT_SLOT,
3023                                     RT_IDX_CAM_HIT, 1);
3024         if (status)
3025                 QPRINTK(qdev, IFUP, ERR,
3026                         "Failed to init routing register for CAM packets.\n");
3027 exit:
3028         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3029         return status;
3030 }
3031
3032 int ql_cam_route_initialize(struct ql_adapter *qdev)
3033 {
3034         int status;
3035
3036         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3037         if (status)
3038                 return status;
3039         status = ql_set_mac_addr_reg(qdev, (u8 *) qdev->ndev->perm_addr,
3040                              MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3041         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3042         if (status) {
3043                 QPRINTK(qdev, IFUP, ERR, "Failed to init mac address.\n");
3044                 return status;
3045         }
3046
3047         status = ql_route_initialize(qdev);
3048         if (status)
3049                 QPRINTK(qdev, IFUP, ERR, "Failed to init routing table.\n");
3050
3051         return status;
3052 }
3053
3054 static int ql_adapter_initialize(struct ql_adapter *qdev)
3055 {
3056         u32 value, mask;
3057         int i;
3058         int status = 0;
3059
3060         /*
3061          * Set up the System register to halt on errors.
3062          */
3063         value = SYS_EFE | SYS_FAE;
3064         mask = value << 16;
3065         ql_write32(qdev, SYS, mask | value);
3066
3067         /* Set the default queue. */
3068         value = NIC_RCV_CFG_DFQ;
3069         mask = NIC_RCV_CFG_DFQ_MASK;
3070         ql_write32(qdev, NIC_RCV_CFG, (mask | value));
3071
3072         /* Set the MPI interrupt to enabled. */
3073         ql_write32(qdev, INTR_MASK, (INTR_MASK_PI << 16) | INTR_MASK_PI);
3074
3075         /* Enable the function, set pagesize, enable error checking. */
3076         value = FSC_FE | FSC_EPC_INBOUND | FSC_EPC_OUTBOUND |
3077             FSC_EC | FSC_VM_PAGE_4K | FSC_SH;
3078
3079         /* Set/clear header splitting. */
3080         mask = FSC_VM_PAGESIZE_MASK |
3081             FSC_DBL_MASK | FSC_DBRST_MASK | (value << 16);
3082         ql_write32(qdev, FSC, mask | value);
3083
3084         ql_write32(qdev, SPLT_HDR, SPLT_HDR_EP |
3085                 min(SMALL_BUFFER_SIZE, MAX_SPLIT_SIZE));
3086
3087         /* Start up the rx queues. */
3088         for (i = 0; i < qdev->rx_ring_count; i++) {
3089                 status = ql_start_rx_ring(qdev, &qdev->rx_ring[i]);
3090                 if (status) {
3091                         QPRINTK(qdev, IFUP, ERR,
3092                                 "Failed to start rx ring[%d].\n", i);
3093                         return status;
3094                 }
3095         }
3096
3097         /* If there is more than one inbound completion queue
3098          * then download a RICB to configure RSS.
3099          */
3100         if (qdev->rss_ring_count > 1) {
3101                 status = ql_start_rss(qdev);
3102                 if (status) {
3103                         QPRINTK(qdev, IFUP, ERR, "Failed to start RSS.\n");
3104                         return status;
3105                 }
3106         }
3107
3108         /* Start up the tx queues. */
3109         for (i = 0; i < qdev->tx_ring_count; i++) {
3110                 status = ql_start_tx_ring(qdev, &qdev->tx_ring[i]);
3111                 if (status) {
3112                         QPRINTK(qdev, IFUP, ERR,
3113                                 "Failed to start tx ring[%d].\n", i);
3114                         return status;
3115                 }
3116         }
3117
3118         /* Initialize the port and set the max framesize. */
3119         status = qdev->nic_ops->port_initialize(qdev);
3120        if (status) {
3121               QPRINTK(qdev, IFUP, ERR, "Failed to start port.\n");
3122               return status;
3123        }
3124
3125         /* Set up the MAC address and frame routing filter. */
3126         status = ql_cam_route_initialize(qdev);
3127         if (status) {
3128                 QPRINTK(qdev, IFUP, ERR,
3129                                 "Failed to init CAM/Routing tables.\n");
3130                 return status;
3131         }
3132
3133         /* Start NAPI for the RSS queues. */
3134         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++) {
3135                 QPRINTK(qdev, IFUP, DEBUG, "Enabling NAPI for rx_ring[%d].\n",
3136                         i);
3137                 napi_enable(&qdev->rx_ring[i].napi);
3138         }
3139
3140         return status;
3141 }
3142
3143 /* Issue soft reset to chip. */
3144 static int ql_adapter_reset(struct ql_adapter *qdev)
3145 {
3146         u32 value;
3147         int status = 0;
3148         unsigned long end_jiffies = jiffies +
3149                 max((unsigned long)1, usecs_to_jiffies(30));
3150
3151         ql_write32(qdev, RST_FO, (RST_FO_FR << 16) | RST_FO_FR);
3152
3153         do {
3154                 value = ql_read32(qdev, RST_FO);
3155                 if ((value & RST_FO_FR) == 0)
3156                         break;
3157                 cpu_relax();
3158         } while (time_before(jiffies, end_jiffies));
3159
3160         if (value & RST_FO_FR) {
3161                 QPRINTK(qdev, IFDOWN, ERR,
3162                         "ETIMEOUT!!! errored out of resetting the chip!\n");
3163                 status = -ETIMEDOUT;
3164         }
3165
3166         return status;
3167 }
3168
3169 static void ql_display_dev_info(struct net_device *ndev)
3170 {
3171         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3172
3173         QPRINTK(qdev, PROBE, INFO,
3174                 "Function #%d, NIC Roll %d, NIC Rev = %d, "
3175                 "XG Roll = %d, XG Rev = %d.\n",
3176                 qdev->func,
3177                 qdev->chip_rev_id & 0x0000000f,
3178                 qdev->chip_rev_id >> 4 & 0x0000000f,
3179                 qdev->chip_rev_id >> 8 & 0x0000000f,
3180                 qdev->chip_rev_id >> 12 & 0x0000000f);
3181         QPRINTK(qdev, PROBE, INFO, "MAC address %pM\n", ndev->dev_addr);
3182 }
3183
3184 static int ql_adapter_down(struct ql_adapter *qdev)
3185 {
3186         struct net_device *ndev = qdev->ndev;
3187         int i, status = 0;
3188         struct rx_ring *rx_ring;
3189
3190         netif_stop_queue(ndev);
3191         netif_carrier_off(ndev);
3192
3193         /* Don't kill the reset worker thread if we
3194          * are in the process of recovery.
3195          */
3196         if (test_bit(QL_ADAPTER_UP, &qdev->flags))
3197                 cancel_delayed_work_sync(&qdev->asic_reset_work);
3198         cancel_delayed_work_sync(&qdev->mpi_reset_work);
3199         cancel_delayed_work_sync(&qdev->mpi_work);
3200         cancel_delayed_work_sync(&qdev->mpi_idc_work);
3201         cancel_delayed_work_sync(&qdev->mpi_port_cfg_work);
3202
3203         /* The default queue at index 0 is always processed in
3204          * a workqueue.
3205          */
3206         cancel_delayed_work_sync(&qdev->rx_ring[0].rx_work);
3207
3208         /* The rest of the rx_rings are processed in
3209          * a workqueue only if it's a single interrupt
3210          * environment (MSI/Legacy).
3211          */
3212         for (i = 1; i < qdev->rx_ring_count; i++) {
3213                 rx_ring = &qdev->rx_ring[i];
3214                 /* Only the RSS rings use NAPI on multi irq
3215                  * environment.  Outbound completion processing
3216                  * is done in interrupt context.
3217                  */
3218                 if (i >= qdev->rss_ring_first_cq_id) {
3219                         napi_disable(&rx_ring->napi);
3220                 } else {
3221                         cancel_delayed_work_sync(&rx_ring->rx_work);
3222                 }
3223         }
3224
3225         clear_bit(QL_ADAPTER_UP, &qdev->flags);
3226
3227         ql_disable_interrupts(qdev);
3228
3229         ql_tx_ring_clean(qdev);
3230
3231         ql_free_rx_buffers(qdev);
3232         spin_lock(&qdev->hw_lock);
3233         status = ql_adapter_reset(qdev);
3234         if (status)
3235                 QPRINTK(qdev, IFDOWN, ERR, "reset(func #%d) FAILED!\n",
3236                         qdev->func);
3237         spin_unlock(&qdev->hw_lock);
3238         return status;
3239 }
3240
3241 static int ql_adapter_up(struct ql_adapter *qdev)
3242 {
3243         int err = 0;
3244
3245         spin_lock(&qdev->hw_lock);
3246         err = ql_adapter_initialize(qdev);
3247         if (err) {
3248                 QPRINTK(qdev, IFUP, INFO, "Unable to initialize adapter.\n");
3249                 spin_unlock(&qdev->hw_lock);
3250                 goto err_init;
3251         }
3252         spin_unlock(&qdev->hw_lock);
3253         set_bit(QL_ADAPTER_UP, &qdev->flags);
3254         ql_alloc_rx_buffers(qdev);
3255         ql_enable_interrupts(qdev);
3256         ql_enable_all_completion_interrupts(qdev);
3257         if ((ql_read32(qdev, STS) & qdev->port_init)) {
3258                 netif_carrier_on(qdev->ndev);
3259                 netif_start_queue(qdev->ndev);
3260         }
3261
3262         return 0;
3263 err_init:
3264         ql_adapter_reset(qdev);
3265         return err;
3266 }
3267
3268 static void ql_release_adapter_resources(struct ql_adapter *qdev)
3269 {
3270         ql_free_mem_resources(qdev);
3271         ql_free_irq(qdev);
3272 }
3273
3274 static int ql_get_adapter_resources(struct ql_adapter *qdev)
3275 {
3276         int status = 0;
3277
3278         if (ql_alloc_mem_resources(qdev)) {
3279                 QPRINTK(qdev, IFUP, ERR, "Unable to  allocate memory.\n");
3280                 return -ENOMEM;
3281         }
3282         status = ql_request_irq(qdev);
3283         if (status)
3284                 goto err_irq;
3285         return status;
3286 err_irq:
3287         ql_free_mem_resources(qdev);
3288         return status;
3289 }
3290
3291 static int qlge_close(struct net_device *ndev)
3292 {
3293         struct ql_adapter *qdev = netdev_priv(ndev);
3294
3295         /*
3296          * Wait for device to recover from a reset.
3297          * (Rarely happens, but possible.)
3298          */
3299         while (!test_bit(QL_ADAPTER_UP, &qdev->flags))
3300                 msleep(1);
3301         ql_adapter_down(qdev);
3302         ql_release_adapter_resources(qdev);
3303         return 0;
3304 }
3305
3306 static int ql_configure_rings(struct ql_adapter *qdev)
3307 {
3308         int i;
3309         struct rx_ring *rx_ring;
3310         struct tx_ring *tx_ring;
3311         int cpu_cnt = num_online_cpus();
3312
3313         /*
3314          * For each processor present we allocate one
3315          * rx_ring for outbound completions, and one
3316          * rx_ring for inbound completions.  Plus there is
3317          * always the one default queue.  For the CPU
3318          * counts we end up with the following rx_rings:
3319          * rx_ring count =
3320          *  one default queue +
3321          *  (CPU count * outbound completion rx_ring) +
3322          *  (CPU count * inbound (RSS) completion rx_ring)
3323          * To keep it simple we limit the total number of
3324          * queues to < 32, so we truncate CPU to 8.
3325          * This limitation can be removed when requested.
3326          */
3327
3328         if (cpu_cnt > MAX_CPUS)
3329                 cpu_cnt = MAX_CPUS;
3330
3331         /*
3332          * rx_ring[0] is always the default queue.
3333          */
3334         /* Allocate outbound completion ring for each CPU. */
3335         qdev->tx_ring_count = cpu_cnt;
3336         /* Allocate inbound completion (RSS) ring for each CPU. */
3337         qdev->rss_ring_count = cpu_cnt;
3338         /* cq_id for the first inbound ring handler. */
3339         qdev->rss_ring_first_cq_id = cpu_cnt + 1;
3340         /*
3341          * qdev->rx_ring_count:
3342          * Total number of rx_rings.  This includes the one
3343          * default queue, a number of outbound completion
3344          * handler rx_rings, and the number of inbound
3345          * completion handler rx_rings.
3346          */
3347         qdev->rx_ring_count = qdev->tx_ring_count + qdev->rss_ring_count + 1;
3348
3349         for (i = 0; i < qdev->tx_ring_count; i++) {
3350                 tx_ring = &qdev->tx_ring[i];
3351                 memset((void *)tx_ring, 0, sizeof(tx_ring));
3352                 tx_ring->qdev = qdev;
3353                 tx_ring->wq_id = i;
3354                 tx_ring->wq_len = qdev->tx_ring_size;
3355                 tx_ring->wq_size =
3356                     tx_ring->wq_len * sizeof(struct ob_mac_iocb_req);
3357
3358                 /*
3359                  * The completion queue ID for the tx rings start
3360                  * immediately after the default Q ID, which is zero.
3361                  */
3362                 tx_ring->cq_id = i + 1;
3363         }
3364
3365         for (i = 0; i < qdev->rx_ring_count; i++) {
3366                 rx_ring = &qdev->rx_ring[i];
3367                 memset((void *)rx_ring, 0, sizeof(rx_ring));
3368                 rx_ring->qdev = qdev;
3369                 rx_ring->cq_id = i;
3370                 rx_ring->cpu = i % cpu_cnt;     /* CPU to run handler on. */
3371                 if (i == 0) {   /* Default queue at index 0. */
3372                         /*
3373                          * Default queue handles bcast/mcast plus
3374                          * async events.  Needs buffers.
3375                          */
3376                         rx_ring->cq_len = qdev->rx_ring_size;
3377                         rx_ring->cq_size =
3378                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3379                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3380                         rx_ring->lbq_size =
3381                             rx_ring->lbq_len * sizeof(__le64);
3382                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3383                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3384                         rx_ring->sbq_size =
3385                             rx_ring->sbq_len * sizeof(__le64);
3386                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3387                         rx_ring->type = DEFAULT_Q;
3388                 } else if (i < qdev->rss_ring_first_cq_id) {
3389                         /*
3390                          * Outbound queue handles outbound completions only.
3391                          */
3392                         /* outbound cq is same size as tx_ring it services. */
3393                         rx_ring->cq_len = qdev->tx_ring_size;
3394                         rx_ring->cq_size =
3395                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3396                         rx_ring->lbq_len = 0;
3397                         rx_ring->lbq_size = 0;
3398                         rx_ring->lbq_buf_size = 0;
3399                         rx_ring->sbq_len = 0;
3400                         rx_ring->sbq_size = 0;
3401                         rx_ring->sbq_buf_size = 0;
3402                         rx_ring->type = TX_Q;
3403                 } else {        /* Inbound completions (RSS) queues */
3404                         /*
3405                          * Inbound queues handle unicast frames only.
3406                          */
3407                         rx_ring->cq_len = qdev->rx_ring_size;
3408                         rx_ring->cq_size =
3409                             rx_ring->cq_len * sizeof(struct ql_net_rsp_iocb);
3410                         rx_ring->lbq_len = NUM_LARGE_BUFFERS;
3411                         rx_ring->lbq_size =
3412                             rx_ring->lbq_len * sizeof(__le64);
3413                         rx_ring->lbq_buf_size = LARGE_BUFFER_SIZE;
3414                         rx_ring->sbq_len = NUM_SMALL_BUFFERS;
3415                         rx_ring->sbq_size =
3416                             rx_ring->sbq_len * sizeof(__le64);
3417                         rx_ring->sbq_buf_size = SMALL_BUFFER_SIZE * 2;
3418                         rx_ring->type = RX_Q;
3419                 }
3420         }
3421         return 0;
3422 }
3423
3424 static int qlge_open(struct net_device *ndev)
3425 {
3426         int err = 0;
3427         struct ql_adapter *qdev = netdev_priv(ndev);
3428
3429         err = ql_configure_rings(qdev);
3430         if (err)
3431                 return err;
3432
3433         err = ql_get_adapter_resources(qdev);
3434         if (err)
3435                 goto error_up;
3436
3437         err = ql_adapter_up(qdev);
3438         if (err)
3439                 goto error_up;
3440
3441         return err;
3442
3443 error_up:
3444         ql_release_adapter_resources(qdev);
3445         return err;
3446 }
3447
3448 static int qlge_change_mtu(struct net_device *ndev, int new_mtu)
3449 {
3450         struct ql_adapter *qdev = netdev_priv(ndev);
3451
3452         if (ndev->mtu == 1500 && new_mtu == 9000) {
3453                 QPRINTK(qdev, IFUP, ERR, "Changing to jumbo MTU.\n");
3454                 queue_delayed_work(qdev->workqueue,
3455                                 &qdev->mpi_port_cfg_work, 0);
3456         } else if (ndev->mtu == 9000 && new_mtu == 1500) {
3457                 QPRINTK(qdev, IFUP, ERR, "Changing to normal MTU.\n");
3458         } else if ((ndev->mtu == 1500 && new_mtu == 1500) ||
3459                    (ndev->mtu == 9000 && new_mtu == 9000)) {
3460                 return 0;
3461         } else
3462                 return -EINVAL;
3463         ndev->mtu = new_mtu;
3464         return 0;
3465 }
3466
3467 static struct net_device_stats *qlge_get_stats(struct net_device
3468                                                *ndev)
3469 {
3470         struct ql_adapter *qdev = netdev_priv(ndev);
3471         return &qdev->stats;
3472 }
3473
3474 static void qlge_set_multicast_list(struct net_device *ndev)
3475 {
3476         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3477         struct dev_mc_list *mc_ptr;
3478         int i, status;
3479
3480         status = ql_sem_spinlock(qdev, SEM_RT_IDX_MASK);
3481         if (status)
3482                 return;
3483         spin_lock(&qdev->hw_lock);
3484         /*
3485          * Set or clear promiscuous mode if a
3486          * transition is taking place.
3487          */
3488         if (ndev->flags & IFF_PROMISC) {
3489                 if (!test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3490                         if (ql_set_routing_reg
3491                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 1)) {
3492                                 QPRINTK(qdev, HW, ERR,
3493                                         "Failed to set promiscous mode.\n");
3494                         } else {
3495                                 set_bit(QL_PROMISCUOUS, &qdev->flags);
3496                         }
3497                 }
3498         } else {
3499                 if (test_bit(QL_PROMISCUOUS, &qdev->flags)) {
3500                         if (ql_set_routing_reg
3501                             (qdev, RT_IDX_PROMISCUOUS_SLOT, RT_IDX_VALID, 0)) {
3502                                 QPRINTK(qdev, HW, ERR,
3503                                         "Failed to clear promiscous mode.\n");
3504                         } else {
3505                                 clear_bit(QL_PROMISCUOUS, &qdev->flags);
3506                         }
3507                 }
3508         }
3509
3510         /*
3511          * Set or clear all multicast mode if a
3512          * transition is taking place.
3513          */
3514         if ((ndev->flags & IFF_ALLMULTI) ||
3515             (ndev->mc_count > MAX_MULTICAST_ENTRIES)) {
3516                 if (!test_bit(QL_ALLMULTI, &qdev->flags)) {
3517                         if (ql_set_routing_reg
3518                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 1)) {
3519                                 QPRINTK(qdev, HW, ERR,
3520                                         "Failed to set all-multi mode.\n");
3521                         } else {
3522                                 set_bit(QL_ALLMULTI, &qdev->flags);
3523                         }
3524                 }
3525         } else {
3526                 if (test_bit(QL_ALLMULTI, &qdev->flags)) {
3527                         if (ql_set_routing_reg
3528                             (qdev, RT_IDX_ALLMULTI_SLOT, RT_IDX_MCAST, 0)) {
3529                                 QPRINTK(qdev, HW, ERR,
3530                                         "Failed to clear all-multi mode.\n");
3531                         } else {
3532                                 clear_bit(QL_ALLMULTI, &qdev->flags);
3533                         }
3534                 }
3535         }
3536
3537         if (ndev->mc_count) {
3538                 status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3539                 if (status)
3540                         goto exit;
3541                 for (i = 0, mc_ptr = ndev->mc_list; mc_ptr;
3542                      i++, mc_ptr = mc_ptr->next)
3543                         if (ql_set_mac_addr_reg(qdev, (u8 *) mc_ptr->dmi_addr,
3544                                                 MAC_ADDR_TYPE_MULTI_MAC, i)) {
3545                                 QPRINTK(qdev, HW, ERR,
3546                                         "Failed to loadmulticast address.\n");
3547                                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3548                                 goto exit;
3549                         }
3550                 ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3551                 if (ql_set_routing_reg
3552                     (qdev, RT_IDX_MCAST_MATCH_SLOT, RT_IDX_MCAST_MATCH, 1)) {
3553                         QPRINTK(qdev, HW, ERR,
3554                                 "Failed to set multicast match mode.\n");
3555                 } else {
3556                         set_bit(QL_ALLMULTI, &qdev->flags);
3557                 }
3558         }
3559 exit:
3560         spin_unlock(&qdev->hw_lock);
3561         ql_sem_unlock(qdev, SEM_RT_IDX_MASK);
3562 }
3563
3564 static int qlge_set_mac_address(struct net_device *ndev, void *p)
3565 {
3566         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3567         struct sockaddr *addr = p;
3568         int status;
3569
3570         if (netif_running(ndev))
3571                 return -EBUSY;
3572
3573         if (!is_valid_ether_addr(addr->sa_data))
3574                 return -EADDRNOTAVAIL;
3575         memcpy(ndev->dev_addr, addr->sa_data, ndev->addr_len);
3576
3577         status = ql_sem_spinlock(qdev, SEM_MAC_ADDR_MASK);
3578         if (status)
3579                 return status;
3580         spin_lock(&qdev->hw_lock);
3581         status = ql_set_mac_addr_reg(qdev, (u8 *) ndev->dev_addr,
3582                         MAC_ADDR_TYPE_CAM_MAC, qdev->func * MAX_CQ);
3583         spin_unlock(&qdev->hw_lock);
3584         if (status)
3585                 QPRINTK(qdev, HW, ERR, "Failed to load MAC address.\n");
3586         ql_sem_unlock(qdev, SEM_MAC_ADDR_MASK);
3587         return status;
3588 }
3589
3590 static void qlge_tx_timeout(struct net_device *ndev)
3591 {
3592         struct ql_adapter *qdev = (struct ql_adapter *)netdev_priv(ndev);
3593         ql_queue_asic_error(qdev);
3594 }
3595
3596 static void ql_asic_reset_work(struct work_struct *work)
3597 {
3598         struct ql_adapter *qdev =
3599             container_of(work, struct ql_adapter, asic_reset_work.work);
3600         int status;
3601
3602         status = ql_adapter_down(qdev);
3603         if (status)
3604                 goto error;
3605
3606         status = ql_adapter_up(qdev);
3607         if (status)
3608                 goto error;
3609
3610         return;
3611 error:
3612         QPRINTK(qdev, IFUP, ALERT,
3613                 "Driver up/down cycle failed, closing device\n");
3614         rtnl_lock();
3615         set_bit(QL_ADAPTER_UP, &qdev->flags);
3616         dev_close(qdev->ndev);
3617         rtnl_unlock();
3618 }
3619
3620 static struct nic_operations qla8012_nic_ops = {
3621         .get_flash              = ql_get_8012_flash_params,
3622         .port_initialize        = ql_8012_port_initialize,
3623 };
3624
3625 static struct nic_operations qla8000_nic_ops = {
3626         .get_flash              = ql_get_8000_flash_params,
3627         .port_initialize        = ql_8000_port_initialize,
3628 };
3629
3630
3631 static void ql_get_board_info(struct ql_adapter *qdev)
3632 {
3633         qdev->func =
3634             (ql_read32(qdev, STS) & STS_FUNC_ID_MASK) >> STS_FUNC_ID_SHIFT;
3635         if (qdev->func) {
3636                 qdev->xg_sem_mask = SEM_XGMAC1_MASK;
3637                 qdev->port_link_up = STS_PL1;
3638                 qdev->port_init = STS_PI1;
3639                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBI;
3640                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC2_MBO;
3641         } else {
3642                 qdev->xg_sem_mask = SEM_XGMAC0_MASK;
3643                 qdev->port_link_up = STS_PL0;
3644                 qdev->port_init = STS_PI0;
3645                 qdev->mailbox_in = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBI;
3646                 qdev->mailbox_out = PROC_ADDR_MPI_RISC | PROC_ADDR_FUNC0_MBO;
3647         }
3648         qdev->chip_rev_id = ql_read32(qdev, REV_ID);
3649         qdev->device_id = qdev->pdev->device;
3650         if (qdev->device_id == QLGE_DEVICE_ID_8012)
3651                 qdev->nic_ops = &qla8012_nic_ops;
3652         else if (qdev->device_id == QLGE_DEVICE_ID_8000)
3653                 qdev->nic_ops = &qla8000_nic_ops;
3654 }
3655
3656 static void ql_release_all(struct pci_dev *pdev)
3657 {
3658         struct net_device *ndev = pci_get_drvdata(pdev);
3659         struct ql_adapter *qdev = netdev_priv(ndev);
3660
3661         if (qdev->workqueue) {
3662                 destroy_workqueue(qdev->workqueue);
3663                 qdev->workqueue = NULL;
3664         }
3665         if (qdev->q_workqueue) {
3666                 destroy_workqueue(qdev->q_workqueue);
3667                 qdev->q_workqueue = NULL;
3668         }
3669         if (qdev->reg_base)
3670                 iounmap(qdev->reg_base);
3671         if (qdev->doorbell_area)
3672                 iounmap(qdev->doorbell_area);
3673         pci_release_regions(pdev);
3674         pci_set_drvdata(pdev, NULL);
3675 }
3676
3677 static int __devinit ql_init_device(struct pci_dev *pdev,
3678                                     struct net_device *ndev, int cards_found)
3679 {
3680         struct ql_adapter *qdev = netdev_priv(ndev);
3681         int pos, err = 0;
3682         u16 val16;
3683
3684         memset((void *)qdev, 0, sizeof(qdev));
3685         err = pci_enable_device(pdev);
3686         if (err) {
3687                 dev_err(&pdev->dev, "PCI device enable failed.\n");
3688                 return err;
3689         }
3690
3691         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
3692         if (pos <= 0) {
3693                 dev_err(&pdev->dev, PFX "Cannot find PCI Express capability, "
3694                         "aborting.\n");
3695                 goto err_out;
3696         } else {
3697                 pci_read_config_word(pdev, pos + PCI_EXP_DEVCTL, &val16);
3698                 val16 &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
3699                 val16 |= (PCI_EXP_DEVCTL_CERE |
3700                           PCI_EXP_DEVCTL_NFERE |
3701                           PCI_EXP_DEVCTL_FERE | PCI_EXP_DEVCTL_URRE);
3702                 pci_write_config_word(pdev, pos + PCI_EXP_DEVCTL, val16);
3703         }
3704
3705         err = pci_request_regions(pdev, DRV_NAME);
3706         if (err) {
3707                 dev_err(&pdev->dev, "PCI region request failed.\n");
3708                 goto err_out;
3709         }
3710
3711         pci_set_master(pdev);
3712         if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3713                 set_bit(QL_DMA64, &qdev->flags);
3714                 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3715         } else {
3716                 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3717                 if (!err)
3718                        err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3719         }
3720
3721         if (err) {
3722                 dev_err(&pdev->dev, "No usable DMA configuration.\n");
3723                 goto err_out;
3724         }
3725
3726         pci_set_drvdata(pdev, ndev);
3727         qdev->reg_base =
3728             ioremap_nocache(pci_resource_start(pdev, 1),
3729                             pci_resource_len(pdev, 1));
3730         if (!qdev->reg_base) {
3731                 dev_err(&pdev->dev, "Register mapping failed.\n");
3732                 err = -ENOMEM;
3733                 goto err_out;
3734         }
3735
3736         qdev->doorbell_area_size = pci_resource_len(pdev, 3);
3737         qdev->doorbell_area =
3738             ioremap_nocache(pci_resource_start(pdev, 3),
3739                             pci_resource_len(pdev, 3));
3740         if (!qdev->doorbell_area) {
3741                 dev_err(&pdev->dev, "Doorbell register mapping failed.\n");
3742                 err = -ENOMEM;
3743                 goto err_out;
3744         }
3745
3746         qdev->ndev = ndev;
3747         qdev->pdev = pdev;
3748         ql_get_board_info(qdev);
3749         qdev->msg_enable = netif_msg_init(debug, default_msg);
3750         spin_lock_init(&qdev->hw_lock);
3751         spin_lock_init(&qdev->stats_lock);
3752
3753         /* make sure the EEPROM is good */
3754         err = qdev->nic_ops->get_flash(qdev);
3755         if (err) {
3756                 dev_err(&pdev->dev, "Invalid FLASH.\n");
3757                 goto err_out;
3758         }
3759
3760         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3761
3762         /* Set up the default ring sizes. */
3763         qdev->tx_ring_size = NUM_TX_RING_ENTRIES;
3764         qdev->rx_ring_size = NUM_RX_RING_ENTRIES;
3765
3766         /* Set up the coalescing parameters. */
3767         qdev->rx_coalesce_usecs = DFLT_COALESCE_WAIT;
3768         qdev->tx_coalesce_usecs = DFLT_COALESCE_WAIT;
3769         qdev->rx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3770         qdev->tx_max_coalesced_frames = DFLT_INTER_FRAME_WAIT;
3771
3772         /*
3773          * Set up the operating parameters.
3774          */
3775         qdev->rx_csum = 1;
3776
3777         qdev->q_workqueue = create_workqueue(ndev->name);
3778         qdev->workqueue = create_singlethread_workqueue(ndev->name);
3779         INIT_DELAYED_WORK(&qdev->asic_reset_work, ql_asic_reset_work);
3780         INIT_DELAYED_WORK(&qdev->mpi_reset_work, ql_mpi_reset_work);
3781         INIT_DELAYED_WORK(&qdev->mpi_work, ql_mpi_work);
3782         INIT_DELAYED_WORK(&qdev->mpi_port_cfg_work, ql_mpi_port_cfg_work);
3783         INIT_DELAYED_WORK(&qdev->mpi_idc_work, ql_mpi_idc_work);
3784         mutex_init(&qdev->mpi_mutex);
3785         init_completion(&qdev->ide_completion);
3786
3787         if (!cards_found) {
3788                 dev_info(&pdev->dev, "%s\n", DRV_STRING);
3789                 dev_info(&pdev->dev, "Driver name: %s, Version: %s.\n",
3790                          DRV_NAME, DRV_VERSION);
3791         }
3792         return 0;
3793 err_out:
3794         ql_release_all(pdev);
3795         pci_disable_device(pdev);
3796         return err;
3797 }
3798
3799
3800 static const struct net_device_ops qlge_netdev_ops = {
3801         .ndo_open               = qlge_open,
3802         .ndo_stop               = qlge_close,
3803         .ndo_start_xmit         = qlge_send,
3804         .ndo_change_mtu         = qlge_change_mtu,
3805         .ndo_get_stats          = qlge_get_stats,
3806         .ndo_set_multicast_list = qlge_set_multicast_list,
3807         .ndo_set_mac_address    = qlge_set_mac_address,
3808         .ndo_validate_addr      = eth_validate_addr,
3809         .ndo_tx_timeout         = qlge_tx_timeout,
3810         .ndo_vlan_rx_register   = ql_vlan_rx_register,
3811         .ndo_vlan_rx_add_vid    = ql_vlan_rx_add_vid,
3812         .ndo_vlan_rx_kill_vid   = ql_vlan_rx_kill_vid,
3813 };
3814
3815 static int __devinit qlge_probe(struct pci_dev *pdev,
3816                                 const struct pci_device_id *pci_entry)
3817 {
3818         struct net_device *ndev = NULL;
3819         struct ql_adapter *qdev = NULL;
3820         static int cards_found = 0;
3821         int err = 0;
3822
3823         ndev = alloc_etherdev(sizeof(struct ql_adapter));
3824         if (!ndev)
3825                 return -ENOMEM;
3826
3827         err = ql_init_device(pdev, ndev, cards_found);
3828         if (err < 0) {
3829                 free_netdev(ndev);
3830                 return err;
3831         }
3832
3833         qdev = netdev_priv(ndev);
3834         SET_NETDEV_DEV(ndev, &pdev->dev);
3835         ndev->features = (0
3836                           | NETIF_F_IP_CSUM
3837                           | NETIF_F_SG
3838                           | NETIF_F_TSO
3839                           | NETIF_F_TSO6
3840                           | NETIF_F_TSO_ECN
3841                           | NETIF_F_HW_VLAN_TX
3842                           | NETIF_F_HW_VLAN_RX | NETIF_F_HW_VLAN_FILTER);
3843
3844         if (test_bit(QL_DMA64, &qdev->flags))
3845                 ndev->features |= NETIF_F_HIGHDMA;
3846
3847         /*
3848          * Set up net_device structure.
3849          */
3850         ndev->tx_queue_len = qdev->tx_ring_size;
3851         ndev->irq = pdev->irq;
3852
3853         ndev->netdev_ops = &qlge_netdev_ops;
3854         SET_ETHTOOL_OPS(ndev, &qlge_ethtool_ops);
3855         ndev->watchdog_timeo = 10 * HZ;
3856
3857         err = register_netdev(ndev);
3858         if (err) {
3859                 dev_err(&pdev->dev, "net device registration failed.\n");
3860                 ql_release_all(pdev);
3861                 pci_disable_device(pdev);
3862                 return err;
3863         }
3864         netif_carrier_off(ndev);
3865         netif_stop_queue(ndev);
3866         ql_display_dev_info(ndev);
3867         cards_found++;
3868         return 0;
3869 }
3870
3871 static void __devexit qlge_remove(struct pci_dev *pdev)
3872 {
3873         struct net_device *ndev = pci_get_drvdata(pdev);
3874         unregister_netdev(ndev);
3875         ql_release_all(pdev);
3876         pci_disable_device(pdev);
3877         free_netdev(ndev);
3878 }
3879
3880 /*
3881  * This callback is called by the PCI subsystem whenever
3882  * a PCI bus error is detected.
3883  */
3884 static pci_ers_result_t qlge_io_error_detected(struct pci_dev *pdev,
3885                                                enum pci_channel_state state)
3886 {
3887         struct net_device *ndev = pci_get_drvdata(pdev);
3888         struct ql_adapter *qdev = netdev_priv(ndev);
3889
3890         if (netif_running(ndev))
3891                 ql_adapter_down(qdev);
3892
3893         pci_disable_device(pdev);
3894
3895         /* Request a slot reset. */
3896         return PCI_ERS_RESULT_NEED_RESET;
3897 }
3898
3899 /*
3900  * This callback is called after the PCI buss has been reset.
3901  * Basically, this tries to restart the card from scratch.
3902  * This is a shortened version of the device probe/discovery code,
3903  * it resembles the first-half of the () routine.
3904  */
3905 static pci_ers_result_t qlge_io_slot_reset(struct pci_dev *pdev)
3906 {
3907         struct net_device *ndev = pci_get_drvdata(pdev);
3908         struct ql_adapter *qdev = netdev_priv(ndev);
3909
3910         if (pci_enable_device(pdev)) {
3911                 QPRINTK(qdev, IFUP, ERR,
3912                         "Cannot re-enable PCI device after reset.\n");
3913                 return PCI_ERS_RESULT_DISCONNECT;
3914         }
3915
3916         pci_set_master(pdev);
3917
3918         netif_carrier_off(ndev);
3919         netif_stop_queue(ndev);
3920         ql_adapter_reset(qdev);
3921
3922         /* Make sure the EEPROM is good */
3923         memcpy(ndev->perm_addr, ndev->dev_addr, ndev->addr_len);
3924
3925         if (!is_valid_ether_addr(ndev->perm_addr)) {
3926                 QPRINTK(qdev, IFUP, ERR, "After reset, invalid MAC address.\n");
3927                 return PCI_ERS_RESULT_DISCONNECT;
3928         }
3929
3930         return PCI_ERS_RESULT_RECOVERED;
3931 }
3932
3933 static void qlge_io_resume(struct pci_dev *pdev)
3934 {
3935         struct net_device *ndev = pci_get_drvdata(pdev);
3936         struct ql_adapter *qdev = netdev_priv(ndev);
3937
3938         pci_set_master(pdev);
3939
3940         if (netif_running(ndev)) {
3941                 if (ql_adapter_up(qdev)) {
3942                         QPRINTK(qdev, IFUP, ERR,
3943                                 "Device initialization failed after reset.\n");
3944                         return;
3945                 }
3946         }
3947
3948         netif_device_attach(ndev);
3949 }
3950
3951 static struct pci_error_handlers qlge_err_handler = {
3952         .error_detected = qlge_io_error_detected,
3953         .slot_reset = qlge_io_slot_reset,
3954         .resume = qlge_io_resume,
3955 };
3956
3957 static int qlge_suspend(struct pci_dev *pdev, pm_message_t state)
3958 {
3959         struct net_device *ndev = pci_get_drvdata(pdev);
3960         struct ql_adapter *qdev = netdev_priv(ndev);
3961         int err, i;
3962
3963         netif_device_detach(ndev);
3964
3965         if (netif_running(ndev)) {
3966                 err = ql_adapter_down(qdev);
3967                 if (!err)
3968                         return err;
3969         }
3970
3971         for (i = qdev->rss_ring_first_cq_id; i < qdev->rx_ring_count; i++)
3972                 netif_napi_del(&qdev->rx_ring[i].napi);
3973
3974         err = pci_save_state(pdev);
3975         if (err)
3976                 return err;
3977
3978         pci_disable_device(pdev);
3979
3980         pci_set_power_state(pdev, pci_choose_state(pdev, state));
3981
3982         return 0;
3983 }
3984
3985 #ifdef CONFIG_PM
3986 static int qlge_resume(struct pci_dev *pdev)
3987 {
3988         struct net_device *ndev = pci_get_drvdata(pdev);
3989         struct ql_adapter *qdev = netdev_priv(ndev);
3990         int err;
3991
3992         pci_set_power_state(pdev, PCI_D0);
3993         pci_restore_state(pdev);
3994         err = pci_enable_device(pdev);
3995         if (err) {
3996                 QPRINTK(qdev, IFUP, ERR, "Cannot enable PCI device from suspend\n");
3997                 return err;
3998         }
3999         pci_set_master(pdev);
4000
4001         pci_enable_wake(pdev, PCI_D3hot, 0);
4002         pci_enable_wake(pdev, PCI_D3cold, 0);
4003
4004         if (netif_running(ndev)) {
4005                 err = ql_adapter_up(qdev);
4006                 if (err)
4007                         return err;
4008         }
4009
4010         netif_device_attach(ndev);
4011
4012         return 0;
4013 }
4014 #endif /* CONFIG_PM */
4015
4016 static void qlge_shutdown(struct pci_dev *pdev)
4017 {
4018         qlge_suspend(pdev, PMSG_SUSPEND);
4019 }
4020
4021 static struct pci_driver qlge_driver = {
4022         .name = DRV_NAME,
4023         .id_table = qlge_pci_tbl,
4024         .probe = qlge_probe,
4025         .remove = __devexit_p(qlge_remove),
4026 #ifdef CONFIG_PM
4027         .suspend = qlge_suspend,
4028         .resume = qlge_resume,
4029 #endif
4030         .shutdown = qlge_shutdown,
4031         .err_handler = &qlge_err_handler
4032 };
4033
4034 static int __init qlge_init_module(void)
4035 {
4036         return pci_register_driver(&qlge_driver);
4037 }
4038
4039 static void __exit qlge_exit(void)
4040 {
4041         pci_unregister_driver(&qlge_driver);
4042 }
4043
4044 module_init(qlge_init_module);
4045 module_exit(qlge_exit);