1 // SPDX-License-Identifier: GPL-2.0+
4 * Elecsys Corporation <www.elecsyscorp.com>
5 * Kevin Smith <kevin.smith@elecsyscorp.com>
9 * Marvell Semiconductor <www.marvell.com>
10 * Prafulla Wadaskar <prafulla@marvell.com>
14 * PHY driver for mv88e61xx ethernet switches.
16 * This driver configures the mv88e61xx for basic use as a PHY. The switch
17 * supports a VLAN configuration that determines how traffic will be routed
18 * between the ports. This driver uses a simple configuration that routes
19 * traffic from each PHY port only to the CPU port, and from the CPU port to
22 * The configuration determines which PHY ports to activate using the
23 * CONFIG_MV88E61XX_PHY_PORTS bitmask. Setting bit 0 will activate port 0, bit
24 * 1 activates port 1, etc. Do not set the bit for the port the CPU is
25 * connected to unless it is connected over a PHY interface (not MII).
27 * This driver was written for and tested on the mv88e6176 with an SGMII
28 * connection. Other configurations should be supported, but some additions or
29 * changes may be required.
41 #define PHY_AUTONEGOTIATE_TIMEOUT 5000
43 #define PORT_MASK(port_count) ((1 << (port_count)) - 1)
45 /* Device addresses */
46 #define DEVADDR_PHY(p) (p)
47 #define DEVADDR_SERDES 0x0F
49 /* SMI indirection registers for multichip addressing mode */
50 #define SMI_CMD_REG 0x00
51 #define SMI_DATA_REG 0x01
53 /* Global registers */
54 #define GLOBAL1_STATUS 0x00
55 #define GLOBAL1_CTRL 0x04
56 #define GLOBAL1_MON_CTRL 0x1A
58 /* Global 2 registers */
59 #define GLOBAL2_REG_PHY_CMD 0x18
60 #define GLOBAL2_REG_PHY_DATA 0x19
63 #define PORT_REG_STATUS 0x00
64 #define PORT_REG_PHYS_CTRL 0x01
65 #define PORT_REG_SWITCH_ID 0x03
66 #define PORT_REG_CTRL 0x04
67 #define PORT_REG_VLAN_MAP 0x06
68 #define PORT_REG_VLAN_ID 0x07
71 #define PHY_REG_CTRL1 0x10
72 #define PHY_REG_STATUS1 0x11
73 #define PHY_REG_PAGE 0x16
75 /* Serdes registers */
76 #define SERDES_REG_CTRL_1 0x10
78 /* Phy page numbers */
79 #define PHY_PAGE_COPPER 0
80 #define PHY_PAGE_SERDES 1
83 #define GLOBAL1_CTRL_SWRESET BIT(15)
85 #define GLOBAL1_MON_CTRL_CPUDEST_SHIFT 4
86 #define GLOBAL1_MON_CTRL_CPUDEST_WIDTH 4
88 #define PORT_REG_STATUS_SPEED_SHIFT 8
89 #define PORT_REG_STATUS_SPEED_10 0
90 #define PORT_REG_STATUS_SPEED_100 1
91 #define PORT_REG_STATUS_SPEED_1000 2
93 #define PORT_REG_STATUS_CMODE_MASK 0xF
94 #define PORT_REG_STATUS_CMODE_100BASE_X 0x8
95 #define PORT_REG_STATUS_CMODE_1000BASE_X 0x9
96 #define PORT_REG_STATUS_CMODE_SGMII 0xa
98 #define PORT_REG_PHYS_CTRL_PCS_AN_EN BIT(10)
99 #define PORT_REG_PHYS_CTRL_PCS_AN_RST BIT(9)
100 #define PORT_REG_PHYS_CTRL_FC_VALUE BIT(7)
101 #define PORT_REG_PHYS_CTRL_FC_FORCE BIT(6)
102 #define PORT_REG_PHYS_CTRL_LINK_VALUE BIT(5)
103 #define PORT_REG_PHYS_CTRL_LINK_FORCE BIT(4)
104 #define PORT_REG_PHYS_CTRL_DUPLEX_VALUE BIT(3)
105 #define PORT_REG_PHYS_CTRL_DUPLEX_FORCE BIT(2)
106 #define PORT_REG_PHYS_CTRL_SPD1000 BIT(1)
107 #define PORT_REG_PHYS_CTRL_SPD100 BIT(0)
108 #define PORT_REG_PHYS_CTRL_SPD_MASK (BIT(1) | BIT(0))
110 #define PORT_REG_CTRL_PSTATE_SHIFT 0
111 #define PORT_REG_CTRL_PSTATE_WIDTH 2
113 #define PORT_REG_VLAN_ID_DEF_VID_SHIFT 0
114 #define PORT_REG_VLAN_ID_DEF_VID_WIDTH 12
116 #define PORT_REG_VLAN_MAP_TABLE_SHIFT 0
117 #define PORT_REG_VLAN_MAP_TABLE_WIDTH 11
119 #define SERDES_REG_CTRL_1_FORCE_LINK BIT(10)
122 #define PORT_REG_CTRL_PSTATE_DISABLED 0
123 #define PORT_REG_CTRL_PSTATE_FORWARD 3
125 #define PHY_REG_CTRL1_ENERGY_DET_OFF 0
126 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE 1
127 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_ONLY 2
128 #define PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT 3
130 /* PHY Status Register */
131 #define PHY_REG_STATUS1_SPEED 0xc000
132 #define PHY_REG_STATUS1_GBIT 0x8000
133 #define PHY_REG_STATUS1_100 0x4000
134 #define PHY_REG_STATUS1_DUPLEX 0x2000
135 #define PHY_REG_STATUS1_SPDDONE 0x0800
136 #define PHY_REG_STATUS1_LINK 0x0400
137 #define PHY_REG_STATUS1_ENERGY 0x0010
140 * Macros for building commands for indirect addressing modes. These are valid
141 * for both the indirect multichip addressing mode and the PHY indirection
142 * required for the writes to any PHY register.
144 #define SMI_BUSY BIT(15)
145 #define SMI_CMD_CLAUSE_22 BIT(12)
146 #define SMI_CMD_CLAUSE_22_OP_READ (2 << 10)
147 #define SMI_CMD_CLAUSE_22_OP_WRITE (1 << 10)
149 #define SMI_CMD_READ (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
150 SMI_CMD_CLAUSE_22_OP_READ)
151 #define SMI_CMD_WRITE (SMI_BUSY | SMI_CMD_CLAUSE_22 | \
152 SMI_CMD_CLAUSE_22_OP_WRITE)
154 #define SMI_CMD_ADDR_SHIFT 5
155 #define SMI_CMD_ADDR_WIDTH 5
156 #define SMI_CMD_REG_SHIFT 0
157 #define SMI_CMD_REG_WIDTH 5
159 /* Check for required macros */
160 #ifndef CONFIG_MV88E61XX_PHY_PORTS
161 #error Define CONFIG_MV88E61XX_PHY_PORTS to indicate which physical ports \
164 #ifndef CONFIG_MV88E61XX_CPU_PORT
165 #error Define CONFIG_MV88E61XX_CPU_PORT to the port the CPU is attached to
169 * These are ports without PHYs that may be wired directly
170 * to other serdes interfaces
172 #ifndef CONFIG_MV88E61XX_FIXED_PORTS
173 #define CONFIG_MV88E61XX_FIXED_PORTS 0
176 /* ID register values for different switch models */
177 #define PORT_SWITCH_ID_6020 0x0200
178 #define PORT_SWITCH_ID_6070 0x0700
179 #define PORT_SWITCH_ID_6071 0x0710
180 #define PORT_SWITCH_ID_6096 0x0980
181 #define PORT_SWITCH_ID_6097 0x0990
182 #define PORT_SWITCH_ID_6172 0x1720
183 #define PORT_SWITCH_ID_6176 0x1760
184 #define PORT_SWITCH_ID_6220 0x2200
185 #define PORT_SWITCH_ID_6240 0x2400
186 #define PORT_SWITCH_ID_6250 0x2500
187 #define PORT_SWITCH_ID_6352 0x3520
189 struct mv88e61xx_phy_priv {
190 struct mii_dev *mdio_bus;
193 int port_count; /* Number of switch ports */
194 int port_reg_base; /* Base of the switch port registers */
195 u16 port_stat_link_mask;/* Bitmask for port link status bits */
196 u16 port_stat_dup_mask; /* Bitmask for port duplex status bits */
197 u8 port_stat_speed_width;/* Width of speed status bitfield */
198 u8 global1; /* Offset of Switch Global 1 registers */
199 u8 global2; /* Offset of Switch Global 2 registers */
200 u8 phy_ctrl1_en_det_shift; /* 'EDet' bit field offset */
201 u8 phy_ctrl1_en_det_width; /* Width of 'EDet' bit field */
202 u8 phy_ctrl1_en_det_ctrl; /* 'EDet' control value */
205 static inline int smi_cmd(int cmd, int addr, int reg)
207 cmd = bitfield_replace(cmd, SMI_CMD_ADDR_SHIFT, SMI_CMD_ADDR_WIDTH,
209 cmd = bitfield_replace(cmd, SMI_CMD_REG_SHIFT, SMI_CMD_REG_WIDTH, reg);
213 static inline int smi_cmd_read(int addr, int reg)
215 return smi_cmd(SMI_CMD_READ, addr, reg);
218 static inline int smi_cmd_write(int addr, int reg)
220 return smi_cmd(SMI_CMD_WRITE, addr, reg);
223 __weak int mv88e61xx_hw_reset(struct phy_device *phydev)
228 /* Wait for the current SMI indirect command to complete */
229 static int mv88e61xx_smi_wait(struct mii_dev *bus, int smi_addr)
235 val = bus->read(bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG);
236 if (val >= 0 && (val & SMI_BUSY) == 0)
242 puts("SMI busy timeout\n");
247 * The mv88e61xx has three types of addresses: the smi bus address, the device
248 * address, and the register address. The smi bus address distinguishes it on
249 * the smi bus from other PHYs or switches. The device address determines
250 * which on-chip register set you are reading/writing (the various PHYs, their
251 * associated ports, or global configuration registers). The register address
252 * is the offset of the register you are reading/writing.
254 * When the mv88e61xx is hardware configured to have address zero, it behaves in
255 * single-chip addressing mode, where it responds to all SMI addresses, using
256 * the smi address as its device address. This obviously only works when this
257 * is the only chip on the SMI bus. This allows the driver to access device
258 * registers without using indirection. When the chip is configured to a
259 * non-zero address, it only responds to that SMI address and requires indirect
260 * writes to access the different device addresses.
262 static int mv88e61xx_reg_read(struct phy_device *phydev, int dev, int reg)
264 struct mv88e61xx_phy_priv *priv = phydev->priv;
265 struct mii_dev *mdio_bus = priv->mdio_bus;
266 int smi_addr = priv->smi_addr;
269 /* In single-chip mode, the device can be addressed directly */
271 return mdio_bus->read(mdio_bus, dev, MDIO_DEVAD_NONE, reg);
273 /* Wait for the bus to become free */
274 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
278 /* Issue the read command */
279 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
280 smi_cmd_read(dev, reg));
284 /* Wait for the read command to complete */
285 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
290 res = mdio_bus->read(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_DATA_REG);
294 return bitfield_extract(res, 0, 16);
297 /* See the comment above mv88e61xx_reg_read */
298 static int mv88e61xx_reg_write(struct phy_device *phydev, int dev, int reg,
301 struct mv88e61xx_phy_priv *priv = phydev->priv;
302 struct mii_dev *mdio_bus = priv->mdio_bus;
303 int smi_addr = priv->smi_addr;
306 /* In single-chip mode, the device can be addressed directly */
308 return mdio_bus->write(mdio_bus, dev, MDIO_DEVAD_NONE, reg,
312 /* Wait for the bus to become free */
313 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
317 /* Set the data to write */
318 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE,
323 /* Issue the write command */
324 res = mdio_bus->write(mdio_bus, smi_addr, MDIO_DEVAD_NONE, SMI_CMD_REG,
325 smi_cmd_write(dev, reg));
329 /* Wait for the write command to complete */
330 res = mv88e61xx_smi_wait(mdio_bus, smi_addr);
337 static int mv88e61xx_phy_wait(struct phy_device *phydev)
339 struct mv88e61xx_phy_priv *priv = phydev->priv;
344 val = mv88e61xx_reg_read(phydev, priv->global2,
345 GLOBAL2_REG_PHY_CMD);
346 if (val >= 0 && (val & SMI_BUSY) == 0)
355 static int mv88e61xx_phy_read_indirect(struct mii_dev *smi_wrapper, int dev,
358 struct mv88e61xx_phy_priv *priv;
359 struct phy_device *phydev;
362 phydev = (struct phy_device *)smi_wrapper->priv;
365 /* Issue command to read */
366 res = mv88e61xx_reg_write(phydev, priv->global2,
368 smi_cmd_read(dev, reg));
370 /* Wait for data to be read */
371 res = mv88e61xx_phy_wait(phydev);
375 /* Read retrieved data */
376 return mv88e61xx_reg_read(phydev, priv->global2,
377 GLOBAL2_REG_PHY_DATA);
380 static int mv88e61xx_phy_write_indirect(struct mii_dev *smi_wrapper, int dev,
381 int devad, int reg, u16 data)
383 struct mv88e61xx_phy_priv *priv;
384 struct phy_device *phydev;
387 phydev = (struct phy_device *)smi_wrapper->priv;
390 /* Set the data to write */
391 res = mv88e61xx_reg_write(phydev, priv->global2,
392 GLOBAL2_REG_PHY_DATA, data);
395 /* Issue the write command */
396 res = mv88e61xx_reg_write(phydev, priv->global2,
398 smi_cmd_write(dev, reg));
402 /* Wait for command to complete */
403 return mv88e61xx_phy_wait(phydev);
406 /* Wrapper function to make calls to phy_read_indirect simpler */
407 static int mv88e61xx_phy_read(struct phy_device *phydev, int phy, int reg)
409 return mv88e61xx_phy_read_indirect(phydev->bus, DEVADDR_PHY(phy),
410 MDIO_DEVAD_NONE, reg);
413 /* Wrapper function to make calls to phy_read_indirect simpler */
414 static int mv88e61xx_phy_write(struct phy_device *phydev, int phy,
417 return mv88e61xx_phy_write_indirect(phydev->bus, DEVADDR_PHY(phy),
418 MDIO_DEVAD_NONE, reg, val);
421 static int mv88e61xx_port_read(struct phy_device *phydev, u8 port, u8 reg)
423 struct mv88e61xx_phy_priv *priv = phydev->priv;
425 return mv88e61xx_reg_read(phydev, priv->port_reg_base + port, reg);
428 static int mv88e61xx_port_write(struct phy_device *phydev, u8 port, u8 reg,
431 struct mv88e61xx_phy_priv *priv = phydev->priv;
433 return mv88e61xx_reg_write(phydev, priv->port_reg_base + port,
437 static int mv88e61xx_set_page(struct phy_device *phydev, u8 phy, u8 page)
439 return mv88e61xx_phy_write(phydev, phy, PHY_REG_PAGE, page);
442 static int mv88e61xx_get_switch_id(struct phy_device *phydev)
446 res = mv88e61xx_port_read(phydev, 0, PORT_REG_SWITCH_ID);
452 static bool mv88e61xx_6352_family(struct phy_device *phydev)
454 struct mv88e61xx_phy_priv *priv = phydev->priv;
457 case PORT_SWITCH_ID_6172:
458 case PORT_SWITCH_ID_6176:
459 case PORT_SWITCH_ID_6240:
460 case PORT_SWITCH_ID_6352:
466 static int mv88e61xx_get_cmode(struct phy_device *phydev, u8 port)
470 res = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
473 return res & PORT_REG_STATUS_CMODE_MASK;
476 static int mv88e61xx_parse_status(struct phy_device *phydev)
479 unsigned int mii_reg;
481 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE, PHY_REG_STATUS1);
483 if ((mii_reg & PHY_REG_STATUS1_LINK) &&
484 !(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
487 puts("Waiting for PHY realtime link");
488 while (!(mii_reg & PHY_REG_STATUS1_SPDDONE)) {
489 /* Timeout reached ? */
490 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
491 puts(" TIMEOUT !\n");
496 if ((i++ % 1000) == 0)
499 mii_reg = phy_read(phydev, MDIO_DEVAD_NONE,
503 udelay(500000); /* another 500 ms (results in faster booting) */
505 if (mii_reg & PHY_REG_STATUS1_LINK)
511 if (mii_reg & PHY_REG_STATUS1_DUPLEX)
512 phydev->duplex = DUPLEX_FULL;
514 phydev->duplex = DUPLEX_HALF;
516 speed = mii_reg & PHY_REG_STATUS1_SPEED;
519 case PHY_REG_STATUS1_GBIT:
520 phydev->speed = SPEED_1000;
522 case PHY_REG_STATUS1_100:
523 phydev->speed = SPEED_100;
526 phydev->speed = SPEED_10;
533 static int mv88e61xx_switch_reset(struct phy_device *phydev)
535 struct mv88e61xx_phy_priv *priv = phydev->priv;
540 /* Disable all ports */
541 for (port = 0; port < priv->port_count; port++) {
542 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
545 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
546 PORT_REG_CTRL_PSTATE_WIDTH,
547 PORT_REG_CTRL_PSTATE_DISABLED);
548 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
553 /* Wait 2 ms for queues to drain */
557 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_CTRL);
560 val |= GLOBAL1_CTRL_SWRESET;
561 val = mv88e61xx_reg_write(phydev, priv->global1,
566 /* Wait up to 1 second for switch reset complete */
567 for (time = 1000; time; time--) {
568 val = mv88e61xx_reg_read(phydev, priv->global1,
570 if (val >= 0 && ((val & GLOBAL1_CTRL_SWRESET) == 0))
580 static int mv88e61xx_serdes_init(struct phy_device *phydev)
584 val = mv88e61xx_set_page(phydev, DEVADDR_SERDES, PHY_PAGE_SERDES);
588 /* Power up serdes module */
589 val = mv88e61xx_phy_read(phydev, DEVADDR_SERDES, MII_BMCR);
592 val &= ~(BMCR_PDOWN);
593 val = mv88e61xx_phy_write(phydev, DEVADDR_SERDES, MII_BMCR, val);
600 static int mv88e61xx_port_enable(struct phy_device *phydev, u8 port)
604 val = mv88e61xx_port_read(phydev, port, PORT_REG_CTRL);
607 val = bitfield_replace(val, PORT_REG_CTRL_PSTATE_SHIFT,
608 PORT_REG_CTRL_PSTATE_WIDTH,
609 PORT_REG_CTRL_PSTATE_FORWARD);
610 val = mv88e61xx_port_write(phydev, port, PORT_REG_CTRL, val);
617 static int mv88e61xx_port_set_vlan(struct phy_device *phydev, u8 port,
622 /* Set VID to port number plus one */
623 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_ID);
626 val = bitfield_replace(val, PORT_REG_VLAN_ID_DEF_VID_SHIFT,
627 PORT_REG_VLAN_ID_DEF_VID_WIDTH,
629 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_ID, val);
634 val = mv88e61xx_port_read(phydev, port, PORT_REG_VLAN_MAP);
637 val = bitfield_replace(val, PORT_REG_VLAN_MAP_TABLE_SHIFT,
638 PORT_REG_VLAN_MAP_TABLE_WIDTH,
640 val = mv88e61xx_port_write(phydev, port, PORT_REG_VLAN_MAP, val);
647 static int mv88e61xx_read_port_config(struct phy_device *phydev, u8 port)
649 struct mv88e61xx_phy_priv *priv = phydev->priv;
654 val = mv88e61xx_port_read(phydev, port, PORT_REG_STATUS);
657 if (!(val & priv->port_stat_link_mask)) {
658 /* Temporarily force link to read port configuration */
662 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
665 val |= (PORT_REG_PHYS_CTRL_LINK_FORCE |
666 PORT_REG_PHYS_CTRL_LINK_VALUE);
667 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
672 /* Wait for status register to reflect forced link */
674 val = mv88e61xx_port_read(phydev, port,
680 if (val & priv->port_stat_link_mask)
690 if (val & priv->port_stat_dup_mask)
691 phydev->duplex = DUPLEX_FULL;
693 phydev->duplex = DUPLEX_HALF;
695 val = bitfield_extract(val, PORT_REG_STATUS_SPEED_SHIFT,
696 priv->port_stat_speed_width);
698 case PORT_REG_STATUS_SPEED_1000:
699 phydev->speed = SPEED_1000;
701 case PORT_REG_STATUS_SPEED_100:
702 phydev->speed = SPEED_100;
705 phydev->speed = SPEED_10;
713 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
716 val &= ~(PORT_REG_PHYS_CTRL_LINK_FORCE |
717 PORT_REG_PHYS_CTRL_LINK_VALUE);
718 val = mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
727 static int mv88e61xx_fixed_port_setup(struct phy_device *phydev, u8 port)
729 struct mv88e61xx_phy_priv *priv = phydev->priv;
732 val = mv88e61xx_port_read(phydev, port, PORT_REG_PHYS_CTRL);
736 val &= ~(PORT_REG_PHYS_CTRL_SPD_MASK |
737 PORT_REG_PHYS_CTRL_FC_VALUE |
738 PORT_REG_PHYS_CTRL_FC_FORCE);
739 val |= PORT_REG_PHYS_CTRL_FC_FORCE |
740 PORT_REG_PHYS_CTRL_DUPLEX_VALUE |
741 PORT_REG_PHYS_CTRL_DUPLEX_FORCE;
743 if (priv->id == PORT_SWITCH_ID_6071) {
744 val |= PORT_REG_PHYS_CTRL_SPD100;
746 val |= PORT_REG_PHYS_CTRL_PCS_AN_EN |
747 PORT_REG_PHYS_CTRL_PCS_AN_RST |
748 PORT_REG_PHYS_CTRL_SPD1000;
751 if (port == CONFIG_MV88E61XX_CPU_PORT)
752 val |= PORT_REG_PHYS_CTRL_LINK_VALUE |
753 PORT_REG_PHYS_CTRL_LINK_FORCE;
755 return mv88e61xx_port_write(phydev, port, PORT_REG_PHYS_CTRL,
759 static int mv88e61xx_set_cpu_port(struct phy_device *phydev)
761 struct mv88e61xx_phy_priv *priv = phydev->priv;
765 val = mv88e61xx_reg_read(phydev, priv->global1, GLOBAL1_MON_CTRL);
768 val = bitfield_replace(val, GLOBAL1_MON_CTRL_CPUDEST_SHIFT,
769 GLOBAL1_MON_CTRL_CPUDEST_WIDTH,
770 CONFIG_MV88E61XX_CPU_PORT);
771 val = mv88e61xx_reg_write(phydev, priv->global1,
772 GLOBAL1_MON_CTRL, val);
776 /* Allow CPU to route to any port */
777 val = PORT_MASK(priv->port_count) & ~(1 << CONFIG_MV88E61XX_CPU_PORT);
778 val = mv88e61xx_port_set_vlan(phydev, CONFIG_MV88E61XX_CPU_PORT, val);
782 /* Enable CPU port */
783 val = mv88e61xx_port_enable(phydev, CONFIG_MV88E61XX_CPU_PORT);
787 val = mv88e61xx_read_port_config(phydev, CONFIG_MV88E61XX_CPU_PORT);
791 /* If CPU is connected to serdes, initialize serdes */
792 if (mv88e61xx_6352_family(phydev)) {
793 val = mv88e61xx_get_cmode(phydev, CONFIG_MV88E61XX_CPU_PORT);
796 if (val == PORT_REG_STATUS_CMODE_100BASE_X ||
797 val == PORT_REG_STATUS_CMODE_1000BASE_X ||
798 val == PORT_REG_STATUS_CMODE_SGMII) {
799 val = mv88e61xx_serdes_init(phydev);
804 val = mv88e61xx_fixed_port_setup(phydev,
805 CONFIG_MV88E61XX_CPU_PORT);
813 static int mv88e61xx_switch_init(struct phy_device *phydev)
821 res = mv88e61xx_switch_reset(phydev);
825 res = mv88e61xx_set_cpu_port(phydev);
834 static int mv88e61xx_phy_enable(struct phy_device *phydev, u8 phy)
838 val = mv88e61xx_phy_read(phydev, phy, MII_BMCR);
841 val &= ~(BMCR_PDOWN);
842 val = mv88e61xx_phy_write(phydev, phy, MII_BMCR, val);
849 static int mv88e61xx_phy_setup(struct phy_device *phydev, u8 phy)
851 struct mv88e61xx_phy_priv *priv = phydev->priv;
855 * Enable energy-detect sensing on PHY, used to determine when a PHY
856 * port is physically connected
858 val = mv88e61xx_phy_read(phydev, phy, PHY_REG_CTRL1);
861 val = bitfield_replace(val, priv->phy_ctrl1_en_det_shift,
862 priv->phy_ctrl1_en_det_width,
863 priv->phy_ctrl1_en_det_ctrl);
864 val = mv88e61xx_phy_write(phydev, phy, PHY_REG_CTRL1, val);
871 static int mv88e61xx_phy_config_port(struct phy_device *phydev, u8 phy)
875 val = mv88e61xx_port_enable(phydev, phy);
879 val = mv88e61xx_port_set_vlan(phydev, phy,
880 1 << CONFIG_MV88E61XX_CPU_PORT);
888 * This function is used to pre-configure the required register
889 * offsets, so that the indirect register access to the PHY registers
890 * is possible. This is necessary to be able to read the PHY ID
891 * while driver probing or in get_phy_id(). The globalN register
892 * offsets must be initialized correctly for a detected switch,
893 * otherwise detection of the PHY ID won't work!
895 static int mv88e61xx_priv_reg_offs_pre_init(struct phy_device *phydev)
897 struct mv88e61xx_phy_priv *priv = phydev->priv;
900 * Initial 'port_reg_base' value must be an offset of existing
901 * port register, then reading the ID should succeed. First, try
902 * to read via port registers with device address 0x10 (88E6096
903 * and compatible switches).
905 priv->port_reg_base = 0x10;
906 priv->id = mv88e61xx_get_switch_id(phydev);
907 if (priv->id != 0xfff0) {
908 priv->global1 = 0x1B;
909 priv->global2 = 0x1C;
914 * Now try via port registers with device address 0x08
915 * (88E6020 and compatible switches).
917 priv->port_reg_base = 0x08;
918 priv->id = mv88e61xx_get_switch_id(phydev);
919 if (priv->id != 0xfff0) {
920 priv->global1 = 0x0F;
921 priv->global2 = 0x07;
925 debug("%s Unknown ID 0x%x\n", __func__, priv->id);
929 static int mv88e61xx_probe(struct phy_device *phydev)
931 struct mii_dev *smi_wrapper;
932 struct mv88e61xx_phy_priv *priv;
935 res = mv88e61xx_hw_reset(phydev);
939 priv = malloc(sizeof(*priv));
943 memset(priv, 0, sizeof(*priv));
946 * This device requires indirect reads/writes to the PHY registers
947 * which the generic PHY code can't handle. Make a wrapper MII device
948 * to handle reads/writes
950 smi_wrapper = mdio_alloc();
957 * Store the mdio bus in the private data, as we are going to replace
958 * the bus with the wrapper bus
960 priv->mdio_bus = phydev->bus;
963 * Store the smi bus address in private data. This lets us use the
964 * phydev addr field for device address instead, as the genphy code
967 priv->smi_addr = phydev->addr;
970 * Store the phy_device in the wrapper mii device. This lets us get it
971 * back when genphy functions call phy_read/phy_write.
973 smi_wrapper->priv = phydev;
974 strncpy(smi_wrapper->name, "indirect mii", sizeof(smi_wrapper->name));
975 smi_wrapper->read = mv88e61xx_phy_read_indirect;
976 smi_wrapper->write = mv88e61xx_phy_write_indirect;
978 /* Replace the bus with the wrapper device */
979 phydev->bus = smi_wrapper;
983 res = mv88e61xx_priv_reg_offs_pre_init(phydev);
987 debug("%s ID 0x%x\n", __func__, priv->id);
990 case PORT_SWITCH_ID_6096:
991 case PORT_SWITCH_ID_6097:
992 case PORT_SWITCH_ID_6172:
993 case PORT_SWITCH_ID_6176:
994 case PORT_SWITCH_ID_6240:
995 case PORT_SWITCH_ID_6352:
996 priv->port_count = 11;
997 priv->port_stat_link_mask = BIT(11);
998 priv->port_stat_dup_mask = BIT(10);
999 priv->port_stat_speed_width = 2;
1000 priv->phy_ctrl1_en_det_shift = 8;
1001 priv->phy_ctrl1_en_det_width = 2;
1002 priv->phy_ctrl1_en_det_ctrl =
1003 PHY_REG_CTRL1_ENERGY_DET_SENSE_XMIT;
1005 case PORT_SWITCH_ID_6020:
1006 case PORT_SWITCH_ID_6070:
1007 case PORT_SWITCH_ID_6071:
1008 case PORT_SWITCH_ID_6220:
1009 case PORT_SWITCH_ID_6250:
1010 priv->port_count = 7;
1011 priv->port_stat_link_mask = BIT(12);
1012 priv->port_stat_dup_mask = BIT(9);
1013 priv->port_stat_speed_width = 1;
1014 priv->phy_ctrl1_en_det_shift = 14;
1015 priv->phy_ctrl1_en_det_width = 1;
1016 priv->phy_ctrl1_en_det_ctrl =
1017 PHY_REG_CTRL1_ENERGY_DET_SENSE_PULSE;
1024 res = mdio_register(smi_wrapper);
1026 printf("Failed to register SMI bus\n");
1031 static int mv88e61xx_phy_config(struct phy_device *phydev)
1033 struct mv88e61xx_phy_priv *priv = phydev->priv;
1038 res = mv88e61xx_switch_init(phydev);
1042 for (i = 0; i < priv->port_count; i++) {
1043 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1046 res = mv88e61xx_phy_enable(phydev, i);
1048 printf("Error enabling PHY %i\n", i);
1051 res = mv88e61xx_phy_setup(phydev, i);
1053 printf("Error setting up PHY %i\n", i);
1056 res = mv88e61xx_phy_config_port(phydev, i);
1058 printf("Error configuring PHY %i\n", i);
1062 res = phy_reset(phydev);
1064 printf("Error resetting PHY %i\n", i);
1067 res = genphy_config_aneg(phydev);
1069 printf("Error setting PHY %i autoneg\n", i);
1073 /* Return success if any PHY succeeds */
1075 } else if ((1 << i) & CONFIG_MV88E61XX_FIXED_PORTS) {
1076 res = mv88e61xx_fixed_port_setup(phydev, i);
1078 printf("Error configuring port %i\n", i);
1087 static int mv88e61xx_phy_is_connected(struct phy_device *phydev)
1091 val = mv88e61xx_phy_read(phydev, phydev->addr, PHY_REG_STATUS1);
1096 * After reset, the energy detect signal remains high for a few seconds
1097 * regardless of whether a cable is connected. This function will
1098 * return false positives during this time.
1100 return (val & PHY_REG_STATUS1_ENERGY) == 0;
1103 static int mv88e61xx_phy_startup(struct phy_device *phydev)
1105 struct mv88e61xx_phy_priv *priv = phydev->priv;
1109 int speed = phydev->speed;
1110 int duplex = phydev->duplex;
1112 for (i = 0; i < priv->port_count; i++) {
1113 if ((1 << i) & CONFIG_MV88E61XX_PHY_PORTS) {
1115 if (!mv88e61xx_phy_is_connected(phydev))
1117 res = genphy_update_link(phydev);
1120 res = mv88e61xx_parse_status(phydev);
1123 link = (link || phydev->link);
1126 phydev->link = link;
1128 /* Restore CPU interface speed and duplex after it was changed for
1130 phydev->speed = speed;
1131 phydev->duplex = duplex;
1136 static struct phy_driver mv88e61xx_driver = {
1137 .name = "Marvell MV88E61xx",
1140 .features = PHY_GBIT_FEATURES,
1141 .probe = mv88e61xx_probe,
1142 .config = mv88e61xx_phy_config,
1143 .startup = mv88e61xx_phy_startup,
1144 .shutdown = &genphy_shutdown,
1147 static struct phy_driver mv88e609x_driver = {
1148 .name = "Marvell MV88E609x",
1151 .features = PHY_GBIT_FEATURES,
1152 .probe = mv88e61xx_probe,
1153 .config = mv88e61xx_phy_config,
1154 .startup = mv88e61xx_phy_startup,
1155 .shutdown = &genphy_shutdown,
1158 static struct phy_driver mv88e6071_driver = {
1159 .name = "Marvell MV88E6071",
1162 .features = PHY_BASIC_FEATURES | SUPPORTED_MII,
1163 .probe = mv88e61xx_probe,
1164 .config = mv88e61xx_phy_config,
1165 .startup = mv88e61xx_phy_startup,
1166 .shutdown = &genphy_shutdown,
1169 int phy_mv88e61xx_init(void)
1171 phy_register(&mv88e61xx_driver);
1172 phy_register(&mv88e609x_driver);
1173 phy_register(&mv88e6071_driver);
1179 * Overload weak get_phy_id definition since we need non-standard functions
1180 * to read PHY registers
1182 int get_phy_id(struct mii_dev *bus, int smi_addr, int devad, u32 *phy_id)
1184 struct phy_device temp_phy;
1185 struct mv88e61xx_phy_priv temp_priv;
1186 struct mii_dev temp_mii;
1190 * Buid temporary data structures that the chip reading code needs to
1193 temp_priv.mdio_bus = bus;
1194 temp_priv.smi_addr = smi_addr;
1195 temp_phy.priv = &temp_priv;
1196 temp_mii.priv = &temp_phy;
1199 * get_phy_id() can be called by framework before mv88e61xx driver
1200 * probing, in this case the global register offsets are not
1201 * initialized yet. Do this initialization here before indirect
1202 * PHY register access.
1204 val = mv88e61xx_priv_reg_offs_pre_init(&temp_phy);
1208 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID1);
1212 *phy_id = val << 16;
1214 val = mv88e61xx_phy_read_indirect(&temp_mii, 0, devad, MII_PHYSID2);
1218 *phy_id |= (val & 0xffff);