2 * Driver for the National Semiconductor DP83640 PHYTER
4 * Copyright (C) 2010 OMICRON electronics GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
20 #include <linux/ethtool.h>
21 #include <linux/kernel.h>
22 #include <linux/list.h>
23 #include <linux/mii.h>
24 #include <linux/module.h>
25 #include <linux/net_tstamp.h>
26 #include <linux/netdevice.h>
27 #include <linux/phy.h>
28 #include <linux/ptp_classify.h>
29 #include <linux/ptp_clock_kernel.h>
31 #include "dp83640_reg.h"
33 #define DP83640_PHY_ID 0x20005ce1
41 #define PSF_EVNT 0x4000
50 /* phyter seems to miss the mark by 16 ns */
51 #define ADJTIME_FIX 16
53 #if defined(__BIG_ENDIAN)
55 #elif defined(__LITTLE_ENDIAN)
56 #define ENDIAN_FLAG PSF_ENDIAN
59 #define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
62 u16 ns_lo; /* ns[15:0] */
63 u16 ns_hi; /* overflow[1:0], ns[29:16] */
64 u16 sec_lo; /* sec[15:0] */
65 u16 sec_hi; /* sec[31:16] */
66 u16 seqid; /* sequenceId[15:0] */
67 u16 msgtype; /* messageType[3:0], hash[11:0] */
71 u16 ns_lo; /* ns[15:0] */
72 u16 ns_hi; /* overflow[1:0], ns[29:16] */
73 u16 sec_lo; /* sec[15:0] */
74 u16 sec_hi; /* sec[31:16] */
78 struct list_head list;
88 struct dp83640_private {
89 struct list_head list;
90 struct dp83640_clock *clock;
91 struct phy_device *phydev;
92 struct work_struct ts_work;
97 /* remember state of cfg0 during calibration */
99 /* remember the last event time stamp */
100 struct phy_txts edata;
101 /* list of rx timestamps */
102 struct list_head rxts;
103 struct list_head rxpool;
104 struct rxts rx_pool_data[MAX_RXTS];
105 /* protects above three fields from concurrent access */
107 /* queues of incoming and outgoing packets */
108 struct sk_buff_head rx_queue;
109 struct sk_buff_head tx_queue;
112 struct dp83640_clock {
113 /* keeps the instance in the 'phyter_clocks' list */
114 struct list_head list;
115 /* we create one clock instance per MII bus */
117 /* protects extended registers from concurrent access */
118 struct mutex extreg_lock;
119 /* remembers which page was last selected */
121 /* our advertised capabilities */
122 struct ptp_clock_info caps;
123 /* protects the three fields below from concurrent access */
124 struct mutex clock_lock;
125 /* the one phyter from which we shall read */
126 struct dp83640_private *chosen;
127 /* list of the other attached phyters, not chosen */
128 struct list_head phylist;
129 /* reference to our PTP hardware clock */
130 struct ptp_clock *ptp_clock;
135 static int chosen_phy = -1;
136 static ushort cal_gpio = 4;
138 module_param(chosen_phy, int, 0444);
139 module_param(cal_gpio, ushort, 0444);
141 MODULE_PARM_DESC(chosen_phy, \
142 "The address of the PHY to use for the ancillary clock features");
143 MODULE_PARM_DESC(cal_gpio, \
144 "Which GPIO line to use for synchronizing multiple PHYs");
146 /* a list of clocks and a mutex to protect it */
147 static LIST_HEAD(phyter_clocks);
148 static DEFINE_MUTEX(phyter_clocks_lock);
150 static void rx_timestamp_work(struct work_struct *work);
152 /* extended register access functions */
154 #define BROADCAST_ADDR 31
156 static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
158 return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
161 /* Caller must hold extreg_lock. */
162 static int ext_read(struct phy_device *phydev, int page, u32 regnum)
164 struct dp83640_private *dp83640 = phydev->priv;
167 if (dp83640->clock->page != page) {
168 broadcast_write(phydev->bus, PAGESEL, page);
169 dp83640->clock->page = page;
171 val = phy_read(phydev, regnum);
176 /* Caller must hold extreg_lock. */
177 static void ext_write(int broadcast, struct phy_device *phydev,
178 int page, u32 regnum, u16 val)
180 struct dp83640_private *dp83640 = phydev->priv;
182 if (dp83640->clock->page != page) {
183 broadcast_write(phydev->bus, PAGESEL, page);
184 dp83640->clock->page = page;
187 broadcast_write(phydev->bus, regnum, val);
189 phy_write(phydev, regnum, val);
192 /* Caller must hold extreg_lock. */
193 static int tdr_write(int bc, struct phy_device *dev,
194 const struct timespec *ts, u16 cmd)
196 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
197 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
198 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
199 ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
201 ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
206 /* convert phy timestamps into driver timestamps */
208 static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
213 sec |= p->sec_hi << 16;
216 rxts->ns |= (p->ns_hi & 0x3fff) << 16;
217 rxts->ns += ((u64)sec) * 1000000000ULL;
218 rxts->seqid = p->seqid;
219 rxts->msgtype = (p->msgtype >> 12) & 0xf;
220 rxts->hash = p->msgtype & 0x0fff;
221 rxts->tmo = jiffies + HZ;
224 static u64 phy2txts(struct phy_txts *p)
230 sec |= p->sec_hi << 16;
233 ns |= (p->ns_hi & 0x3fff) << 16;
234 ns += ((u64)sec) * 1000000000ULL;
239 /* ptp clock methods */
241 static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
243 struct dp83640_clock *clock =
244 container_of(ptp, struct dp83640_clock, caps);
245 struct phy_device *phydev = clock->chosen->phydev;
256 rate = div_u64(rate, 1953125);
258 hi = (rate >> 16) & PTP_RATE_HI_MASK;
264 mutex_lock(&clock->extreg_lock);
266 ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
267 ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
269 mutex_unlock(&clock->extreg_lock);
274 static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
276 struct dp83640_clock *clock =
277 container_of(ptp, struct dp83640_clock, caps);
278 struct phy_device *phydev = clock->chosen->phydev;
282 delta += ADJTIME_FIX;
284 ts = ns_to_timespec(delta);
286 mutex_lock(&clock->extreg_lock);
288 err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
290 mutex_unlock(&clock->extreg_lock);
295 static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
297 struct dp83640_clock *clock =
298 container_of(ptp, struct dp83640_clock, caps);
299 struct phy_device *phydev = clock->chosen->phydev;
302 mutex_lock(&clock->extreg_lock);
304 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
306 val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
307 val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
308 val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
309 val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
311 mutex_unlock(&clock->extreg_lock);
313 ts->tv_nsec = val[0] | (val[1] << 16);
314 ts->tv_sec = val[2] | (val[3] << 16);
319 static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
320 const struct timespec *ts)
322 struct dp83640_clock *clock =
323 container_of(ptp, struct dp83640_clock, caps);
324 struct phy_device *phydev = clock->chosen->phydev;
327 mutex_lock(&clock->extreg_lock);
329 err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
331 mutex_unlock(&clock->extreg_lock);
336 static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
337 struct ptp_clock_request *rq, int on)
339 struct dp83640_clock *clock =
340 container_of(ptp, struct dp83640_clock, caps);
341 struct phy_device *phydev = clock->chosen->phydev;
345 case PTP_CLK_REQ_EXTTS:
346 if (rq->extts.index != 0)
348 evnt = EVNT_WR | (EXT_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
350 evnt |= (EXT_GPIO & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
353 ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
362 static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
363 static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
365 static void enable_status_frames(struct phy_device *phydev, bool on)
370 cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
372 ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
374 ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
375 ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
377 if (!phydev->attached_dev) {
378 pr_warning("dp83640: expected to find an attached netdevice\n");
383 if (dev_mc_add(phydev->attached_dev, status_frame_dst))
384 pr_warning("dp83640: failed to add mc address\n");
386 if (dev_mc_del(phydev->attached_dev, status_frame_dst))
387 pr_warning("dp83640: failed to delete mc address\n");
391 static bool is_status_frame(struct sk_buff *skb, int type)
393 struct ethhdr *h = eth_hdr(skb);
395 if (PTP_CLASS_V2_L2 == type &&
396 !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
402 static int expired(struct rxts *rxts)
404 return time_after(jiffies, rxts->tmo);
407 /* Caller must hold rx_lock. */
408 static void prune_rx_ts(struct dp83640_private *dp83640)
410 struct list_head *this, *next;
413 list_for_each_safe(this, next, &dp83640->rxts) {
414 rxts = list_entry(this, struct rxts, list);
416 list_del_init(&rxts->list);
417 list_add(&rxts->list, &dp83640->rxpool);
422 /* synchronize the phyters so they act as one clock */
424 static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
427 phy_write(phydev, PAGESEL, 0);
428 val = phy_read(phydev, PHYCR2);
433 phy_write(phydev, PHYCR2, val);
434 phy_write(phydev, PAGESEL, init_page);
437 static void recalibrate(struct dp83640_clock *clock)
440 struct phy_txts event_ts;
442 struct list_head *this;
443 struct dp83640_private *tmp;
444 struct phy_device *master = clock->chosen->phydev;
445 u16 cfg0, evnt, ptp_trig, trigger, val;
447 trigger = CAL_TRIGGER;
449 mutex_lock(&clock->extreg_lock);
452 * enable broadcast, disable status frames, enable ptp clock
454 list_for_each(this, &clock->phylist) {
455 tmp = list_entry(this, struct dp83640_private, list);
456 enable_broadcast(tmp->phydev, clock->page, 1);
457 tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
458 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
459 ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
461 enable_broadcast(master, clock->page, 1);
462 cfg0 = ext_read(master, PAGE5, PSF_CFG0);
463 ext_write(0, master, PAGE5, PSF_CFG0, 0);
464 ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
467 * enable an event timestamp
469 evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
470 evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
471 evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
473 list_for_each(this, &clock->phylist) {
474 tmp = list_entry(this, struct dp83640_private, list);
475 ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
477 ext_write(0, master, PAGE5, PTP_EVNT, evnt);
480 * configure a trigger
482 ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
483 ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
484 ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
485 ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
488 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
490 ext_write(0, master, PAGE4, PTP_CTL, val);
495 ext_write(0, master, PAGE4, PTP_CTL, val);
497 /* disable trigger */
498 val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
500 ext_write(0, master, PAGE4, PTP_CTL, val);
503 * read out and correct offsets
505 val = ext_read(master, PAGE4, PTP_STS);
506 pr_info("master PTP_STS 0x%04hx", val);
507 val = ext_read(master, PAGE4, PTP_ESTS);
508 pr_info("master PTP_ESTS 0x%04hx", val);
509 event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
510 event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
511 event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
512 event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
513 now = phy2txts(&event_ts);
515 list_for_each(this, &clock->phylist) {
516 tmp = list_entry(this, struct dp83640_private, list);
517 val = ext_read(tmp->phydev, PAGE4, PTP_STS);
518 pr_info("slave PTP_STS 0x%04hx", val);
519 val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
520 pr_info("slave PTP_ESTS 0x%04hx", val);
521 event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
522 event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
523 event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
524 event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
525 diff = now - (s64) phy2txts(&event_ts);
526 pr_info("slave offset %lld nanoseconds\n", diff);
528 ts = ns_to_timespec(diff);
529 tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
533 * restore status frames
535 list_for_each(this, &clock->phylist) {
536 tmp = list_entry(this, struct dp83640_private, list);
537 ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
539 ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
541 mutex_unlock(&clock->extreg_lock);
544 /* time stamping methods */
546 static void decode_evnt(struct dp83640_private *dp83640,
547 struct phy_txts *phy_txts, u16 ests)
549 struct ptp_clock_event event;
550 int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
552 switch (words) { /* fall through in every case */
554 dp83640->edata.sec_hi = phy_txts->sec_hi;
556 dp83640->edata.sec_lo = phy_txts->sec_lo;
558 dp83640->edata.ns_hi = phy_txts->ns_hi;
560 dp83640->edata.ns_lo = phy_txts->ns_lo;
563 event.type = PTP_CLOCK_EXTTS;
565 event.timestamp = phy2txts(&dp83640->edata);
567 ptp_clock_event(dp83640->clock->ptp_clock, &event);
570 static void decode_rxts(struct dp83640_private *dp83640,
571 struct phy_rxts *phy_rxts)
576 spin_lock_irqsave(&dp83640->rx_lock, flags);
578 prune_rx_ts(dp83640);
580 if (list_empty(&dp83640->rxpool)) {
581 pr_warning("dp83640: rx timestamp pool is empty\n");
584 rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
585 list_del_init(&rxts->list);
586 phy2rxts(phy_rxts, rxts);
587 list_add_tail(&rxts->list, &dp83640->rxts);
589 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
592 static void decode_txts(struct dp83640_private *dp83640,
593 struct phy_txts *phy_txts)
595 struct skb_shared_hwtstamps shhwtstamps;
599 /* We must already have the skb that triggered this. */
601 skb = skb_dequeue(&dp83640->tx_queue);
604 pr_warning("dp83640: have timestamp but tx_queue empty\n");
607 ns = phy2txts(phy_txts);
608 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
609 shhwtstamps.hwtstamp = ns_to_ktime(ns);
610 skb_complete_tx_timestamp(skb, &shhwtstamps);
613 static void decode_status_frame(struct dp83640_private *dp83640,
616 struct phy_rxts *phy_rxts;
617 struct phy_txts *phy_txts;
624 for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
627 ests = type & 0x0fff;
628 type = type & 0xf000;
632 if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
634 phy_rxts = (struct phy_rxts *) ptr;
635 decode_rxts(dp83640, phy_rxts);
636 size = sizeof(*phy_rxts);
638 } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
640 phy_txts = (struct phy_txts *) ptr;
641 decode_txts(dp83640, phy_txts);
642 size = sizeof(*phy_txts);
644 } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) {
646 phy_txts = (struct phy_txts *) ptr;
647 decode_evnt(dp83640, phy_txts, ests);
648 size = sizeof(*phy_txts);
658 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
662 u8 *msgtype, *data = skb_mac_header(skb);
664 /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
667 case PTP_CLASS_V1_IPV4:
668 case PTP_CLASS_V2_IPV4:
669 offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
671 case PTP_CLASS_V1_IPV6:
672 case PTP_CLASS_V2_IPV6:
675 case PTP_CLASS_V2_L2:
678 case PTP_CLASS_V2_VLAN:
679 offset = ETH_HLEN + VLAN_HLEN;
685 if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
688 if (unlikely(type & PTP_CLASS_V1))
689 msgtype = data + offset + OFF_PTP_CONTROL;
691 msgtype = data + offset;
693 seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
695 return (rxts->msgtype == (*msgtype & 0xf) &&
696 rxts->seqid == ntohs(*seqid));
699 static void dp83640_free_clocks(void)
701 struct dp83640_clock *clock;
702 struct list_head *this, *next;
704 mutex_lock(&phyter_clocks_lock);
706 list_for_each_safe(this, next, &phyter_clocks) {
707 clock = list_entry(this, struct dp83640_clock, list);
708 if (!list_empty(&clock->phylist)) {
709 pr_warning("phy list non-empty while unloading");
712 list_del(&clock->list);
713 mutex_destroy(&clock->extreg_lock);
714 mutex_destroy(&clock->clock_lock);
715 put_device(&clock->bus->dev);
719 mutex_unlock(&phyter_clocks_lock);
722 static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
724 INIT_LIST_HEAD(&clock->list);
726 mutex_init(&clock->extreg_lock);
727 mutex_init(&clock->clock_lock);
728 INIT_LIST_HEAD(&clock->phylist);
729 clock->caps.owner = THIS_MODULE;
730 sprintf(clock->caps.name, "dp83640 timer");
731 clock->caps.max_adj = 1953124;
732 clock->caps.n_alarm = 0;
733 clock->caps.n_ext_ts = N_EXT_TS;
734 clock->caps.n_per_out = 0;
736 clock->caps.adjfreq = ptp_dp83640_adjfreq;
737 clock->caps.adjtime = ptp_dp83640_adjtime;
738 clock->caps.gettime = ptp_dp83640_gettime;
739 clock->caps.settime = ptp_dp83640_settime;
740 clock->caps.enable = ptp_dp83640_enable;
742 * Get a reference to this bus instance.
744 get_device(&bus->dev);
747 static int choose_this_phy(struct dp83640_clock *clock,
748 struct phy_device *phydev)
750 if (chosen_phy == -1 && !clock->chosen)
753 if (chosen_phy == phydev->addr)
759 static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
762 mutex_lock(&clock->clock_lock);
767 * Look up and lock a clock by bus instance.
768 * If there is no clock for this bus, then create it first.
770 static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
772 struct dp83640_clock *clock = NULL, *tmp;
773 struct list_head *this;
775 mutex_lock(&phyter_clocks_lock);
777 list_for_each(this, &phyter_clocks) {
778 tmp = list_entry(this, struct dp83640_clock, list);
779 if (tmp->bus == bus) {
787 clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
791 dp83640_clock_init(clock, bus);
792 list_add_tail(&phyter_clocks, &clock->list);
794 mutex_unlock(&phyter_clocks_lock);
796 return dp83640_clock_get(clock);
799 static void dp83640_clock_put(struct dp83640_clock *clock)
801 mutex_unlock(&clock->clock_lock);
804 static int dp83640_probe(struct phy_device *phydev)
806 struct dp83640_clock *clock;
807 struct dp83640_private *dp83640;
808 int err = -ENOMEM, i;
810 if (phydev->addr == BROADCAST_ADDR)
813 clock = dp83640_clock_get_bus(phydev->bus);
817 dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
821 dp83640->phydev = phydev;
822 INIT_WORK(&dp83640->ts_work, rx_timestamp_work);
824 INIT_LIST_HEAD(&dp83640->rxts);
825 INIT_LIST_HEAD(&dp83640->rxpool);
826 for (i = 0; i < MAX_RXTS; i++)
827 list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
829 phydev->priv = dp83640;
831 spin_lock_init(&dp83640->rx_lock);
832 skb_queue_head_init(&dp83640->rx_queue);
833 skb_queue_head_init(&dp83640->tx_queue);
835 dp83640->clock = clock;
837 if (choose_this_phy(clock, phydev)) {
838 clock->chosen = dp83640;
839 clock->ptp_clock = ptp_clock_register(&clock->caps);
840 if (IS_ERR(clock->ptp_clock)) {
841 err = PTR_ERR(clock->ptp_clock);
845 list_add_tail(&dp83640->list, &clock->phylist);
847 if (clock->chosen && !list_empty(&clock->phylist))
850 enable_broadcast(dp83640->phydev, clock->page, 1);
852 dp83640_clock_put(clock);
856 clock->chosen = NULL;
859 dp83640_clock_put(clock);
864 static void dp83640_remove(struct phy_device *phydev)
866 struct dp83640_clock *clock;
867 struct list_head *this, *next;
868 struct dp83640_private *tmp, *dp83640 = phydev->priv;
870 if (phydev->addr == BROADCAST_ADDR)
873 enable_status_frames(phydev, false);
874 cancel_work_sync(&dp83640->ts_work);
876 clock = dp83640_clock_get(dp83640->clock);
878 if (dp83640 == clock->chosen) {
879 ptp_clock_unregister(clock->ptp_clock);
880 clock->chosen = NULL;
882 list_for_each_safe(this, next, &clock->phylist) {
883 tmp = list_entry(this, struct dp83640_private, list);
884 if (tmp == dp83640) {
885 list_del_init(&tmp->list);
891 dp83640_clock_put(clock);
895 static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
897 struct dp83640_private *dp83640 = phydev->priv;
898 struct hwtstamp_config cfg;
901 if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
904 if (cfg.flags) /* reserved for future extensions */
907 switch (cfg.tx_type) {
908 case HWTSTAMP_TX_OFF:
909 dp83640->hwts_tx_en = 0;
912 dp83640->hwts_tx_en = 1;
918 switch (cfg.rx_filter) {
919 case HWTSTAMP_FILTER_NONE:
920 dp83640->hwts_rx_en = 0;
922 dp83640->version = 0;
924 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
925 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
926 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
927 dp83640->hwts_rx_en = 1;
928 dp83640->layer = LAYER4;
929 dp83640->version = 1;
931 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
932 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
933 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
934 dp83640->hwts_rx_en = 1;
935 dp83640->layer = LAYER4;
936 dp83640->version = 2;
938 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
939 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
940 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
941 dp83640->hwts_rx_en = 1;
942 dp83640->layer = LAYER2;
943 dp83640->version = 2;
945 case HWTSTAMP_FILTER_PTP_V2_EVENT:
946 case HWTSTAMP_FILTER_PTP_V2_SYNC:
947 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
948 dp83640->hwts_rx_en = 1;
949 dp83640->layer = LAYER4|LAYER2;
950 dp83640->version = 2;
956 txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
957 rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
959 if (dp83640->layer & LAYER2) {
963 if (dp83640->layer & LAYER4) {
964 txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
965 rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
968 if (dp83640->hwts_tx_en)
971 if (dp83640->hwts_rx_en)
974 mutex_lock(&dp83640->clock->extreg_lock);
976 if (dp83640->hwts_tx_en || dp83640->hwts_rx_en) {
977 enable_status_frames(phydev, true);
978 ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
981 ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
982 ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
984 mutex_unlock(&dp83640->clock->extreg_lock);
986 return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
989 static void rx_timestamp_work(struct work_struct *work)
991 struct dp83640_private *dp83640 =
992 container_of(work, struct dp83640_private, ts_work);
993 struct list_head *this, *next;
995 struct skb_shared_hwtstamps *shhwtstamps;
1000 /* Deliver each deferred packet, with or without a time stamp. */
1002 while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) {
1003 type = SKB_PTP_TYPE(skb);
1004 spin_lock_irqsave(&dp83640->rx_lock, flags);
1005 list_for_each_safe(this, next, &dp83640->rxts) {
1006 rxts = list_entry(this, struct rxts, list);
1007 if (match(skb, type, rxts)) {
1008 shhwtstamps = skb_hwtstamps(skb);
1009 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
1010 shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
1011 list_del_init(&rxts->list);
1012 list_add(&rxts->list, &dp83640->rxpool);
1016 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1020 /* Clear out expired time stamps. */
1022 spin_lock_irqsave(&dp83640->rx_lock, flags);
1023 prune_rx_ts(dp83640);
1024 spin_unlock_irqrestore(&dp83640->rx_lock, flags);
1027 static bool dp83640_rxtstamp(struct phy_device *phydev,
1028 struct sk_buff *skb, int type)
1030 struct dp83640_private *dp83640 = phydev->priv;
1032 if (!dp83640->hwts_rx_en)
1035 if (is_status_frame(skb, type)) {
1036 decode_status_frame(dp83640, skb);
1037 /* Let the stack drop this frame. */
1041 SKB_PTP_TYPE(skb) = type;
1042 skb_queue_tail(&dp83640->rx_queue, skb);
1043 schedule_work(&dp83640->ts_work);
1048 static void dp83640_txtstamp(struct phy_device *phydev,
1049 struct sk_buff *skb, int type)
1051 struct dp83640_private *dp83640 = phydev->priv;
1053 if (!dp83640->hwts_tx_en) {
1057 skb_queue_tail(&dp83640->tx_queue, skb);
1058 schedule_work(&dp83640->ts_work);
1061 static struct phy_driver dp83640_driver = {
1062 .phy_id = DP83640_PHY_ID,
1063 .phy_id_mask = 0xfffffff0,
1064 .name = "NatSemi DP83640",
1065 .features = PHY_BASIC_FEATURES,
1067 .probe = dp83640_probe,
1068 .remove = dp83640_remove,
1069 .config_aneg = genphy_config_aneg,
1070 .read_status = genphy_read_status,
1071 .hwtstamp = dp83640_hwtstamp,
1072 .rxtstamp = dp83640_rxtstamp,
1073 .txtstamp = dp83640_txtstamp,
1074 .driver = {.owner = THIS_MODULE,}
1077 static int __init dp83640_init(void)
1079 return phy_driver_register(&dp83640_driver);
1082 static void __exit dp83640_exit(void)
1084 dp83640_free_clocks();
1085 phy_driver_unregister(&dp83640_driver);
1088 MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
1089 MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
1090 MODULE_LICENSE("GPL");
1092 module_init(dp83640_init);
1093 module_exit(dp83640_exit);
1095 static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
1096 { DP83640_PHY_ID, 0xfffffff0 },
1100 MODULE_DEVICE_TABLE(mdio, dp83640_tbl);