2 * @file IxNpeDlNpeMgrEcRegisters_p.h
4 * @author Intel Corporation
5 * @date 14 December 2001
9 * IXP400 SW Release version 2.0
11 * -- Copyright Notice --
14 * Copyright 2001-2005, Intel Corporation.
15 * All rights reserved.
18 * SPDX-License-Identifier: BSD-3-Clause
20 * -- End of Copyright Notice --
24 #ifndef IXNPEDLNPEMGRECREGISTERS_P_H
25 #define IXNPEDLNPEMGRECREGISTERS_P_H
30 * Base Memory Addresses for accessing NPE registers
33 #define IX_NPEDL_NPE_BASE (IX_OSAL_IXP400_PERIPHERAL_PHYS_BASE)
35 #define IX_NPEDL_NPEA_OFFSET (0x6000) /**< NPE-A register base offset */
36 #define IX_NPEDL_NPEB_OFFSET (0x7000) /**< NPE-B register base offset */
37 #define IX_NPEDL_NPEC_OFFSET (0x8000) /**< NPE-C register base offset */
40 * @def IX_NPEDL_NPEBASEADDRESS_NPEA
41 * @brief Base Memory Address of NPE-A Configuration Bus registers
43 #define IX_NPEDL_NPEBASEADDRESS_NPEA (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEA_OFFSET)
46 * @def IX_NPEDL_NPEBASEADDRESS_NPEB
47 * @brief Base Memory Address of NPE-B Configuration Bus registers
49 #define IX_NPEDL_NPEBASEADDRESS_NPEB (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEB_OFFSET)
52 * @def IX_NPEDL_NPEBASEADDRESS_NPEC
53 * @brief Base Memory Address of NPE-C Configuration Bus registers
55 #define IX_NPEDL_NPEBASEADDRESS_NPEC (IX_NPEDL_NPE_BASE + IX_NPEDL_NPEC_OFFSET)
59 * Instruction Memory Size (in words) for each NPE
63 * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEA
64 * @brief Size (in words) of NPE-A Instruction Memory
66 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEA 4096
69 * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEB
70 * @brief Size (in words) of NPE-B Instruction Memory
72 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEB 2048
75 * @def IX_NPEDL_INS_MEMSIZE_WORDS_NPEC
76 * @brief Size (in words) of NPE-B Instruction Memory
78 #define IX_NPEDL_INS_MEMSIZE_WORDS_NPEC 2048
82 * Data Memory Size (in words) for each NPE
86 * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA
87 * @brief Size (in words) of NPE-A Data Memory
89 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEA 2048
92 * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB
93 * @brief Size (in words) of NPE-B Data Memory
95 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEB 2048
98 * @def IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC
99 * @brief Size (in words) of NPE-C Data Memory
101 #define IX_NPEDL_DATA_MEMSIZE_WORDS_NPEC 2048
105 * Configuration Bus Register offsets (in bytes) from NPE Base Address
109 * @def IX_NPEDL_REG_OFFSET_EXAD
110 * @brief Offset (in bytes) of EXAD (Execution Address) register from NPE Base
113 #define IX_NPEDL_REG_OFFSET_EXAD 0x00000000
116 * @def IX_NPEDL_REG_OFFSET_EXDATA
117 * @brief Offset (in bytes) of EXDATA (Execution Data) register from NPE Base
120 #define IX_NPEDL_REG_OFFSET_EXDATA 0x00000004
123 * @def IX_NPEDL_REG_OFFSET_EXCTL
124 * @brief Offset (in bytes) of EXCTL (Execution Control) register from NPE Base
127 #define IX_NPEDL_REG_OFFSET_EXCTL 0x00000008
130 * @def IX_NPEDL_REG_OFFSET_EXCT
131 * @brief Offset (in bytes) of EXCT (Execution Count) register from NPE Base
134 #define IX_NPEDL_REG_OFFSET_EXCT 0x0000000C
137 * @def IX_NPEDL_REG_OFFSET_AP0
138 * @brief Offset (in bytes) of AP0 (Action Point 0) register from NPE Base
141 #define IX_NPEDL_REG_OFFSET_AP0 0x00000010
144 * @def IX_NPEDL_REG_OFFSET_AP1
145 * @brief Offset (in bytes) of AP1 (Action Point 1) register from NPE Base
148 #define IX_NPEDL_REG_OFFSET_AP1 0x00000014
151 * @def IX_NPEDL_REG_OFFSET_AP2
152 * @brief Offset (in bytes) of AP2 (Action Point 2) register from NPE Base
155 #define IX_NPEDL_REG_OFFSET_AP2 0x00000018
158 * @def IX_NPEDL_REG_OFFSET_AP3
159 * @brief Offset (in bytes) of AP3 (Action Point 3) register from NPE Base
162 #define IX_NPEDL_REG_OFFSET_AP3 0x0000001C
165 * @def IX_NPEDL_REG_OFFSET_WFIFO
166 * @brief Offset (in bytes) of WFIFO (Watchpoint FIFO) register from NPE Base
169 #define IX_NPEDL_REG_OFFSET_WFIFO 0x00000020
172 * @def IX_NPEDL_REG_OFFSET_WC
173 * @brief Offset (in bytes) of WC (Watch Count) register from NPE Base
176 #define IX_NPEDL_REG_OFFSET_WC 0x00000024
179 * @def IX_NPEDL_REG_OFFSET_PROFCT
180 * @brief Offset (in bytes) of PROFCT (Profile Count) register from NPE Base
183 #define IX_NPEDL_REG_OFFSET_PROFCT 0x00000028
186 * @def IX_NPEDL_REG_OFFSET_STAT
187 * @brief Offset (in bytes) of STAT (Messaging Status) register from NPE Base
190 #define IX_NPEDL_REG_OFFSET_STAT 0x0000002C
193 * @def IX_NPEDL_REG_OFFSET_CTL
194 * @brief Offset (in bytes) of CTL (Messaging Control) register from NPE Base
197 #define IX_NPEDL_REG_OFFSET_CTL 0x00000030
200 * @def IX_NPEDL_REG_OFFSET_MBST
201 * @brief Offset (in bytes) of MBST (Mailbox Status) register from NPE Base
204 #define IX_NPEDL_REG_OFFSET_MBST 0x00000034
207 * @def IX_NPEDL_REG_OFFSET_FIFO
208 * @brief Offset (in bytes) of FIFO (messaging in/out FIFO) register from NPE
211 #define IX_NPEDL_REG_OFFSET_FIFO 0x00000038
215 * Non-zero reset values for the Configuration Bus registers
219 * @def IX_NPEDL_REG_RESET_FIFO
220 * @brief Reset value for Mailbox (MBST) register
221 * NOTE that if used, it should be complemented with an NPE intruction
222 * to clear the Mailbox at the NPE side as well
224 #define IX_NPEDL_REG_RESET_MBST 0x0000F0F0
228 * Bit-masks used to read/write particular bits in Configuration Bus registers
232 * @def IX_NPEDL_MASK_WFIFO_VALID
233 * @brief Masks the VALID bit in the WFIFO register
235 #define IX_NPEDL_MASK_WFIFO_VALID 0x80000000
238 * @def IX_NPEDL_MASK_STAT_OFNE
239 * @brief Masks the OFNE bit in the STAT register
241 #define IX_NPEDL_MASK_STAT_OFNE 0x00010000
244 * @def IX_NPEDL_MASK_STAT_IFNE
245 * @brief Masks the IFNE bit in the STAT register
247 #define IX_NPEDL_MASK_STAT_IFNE 0x00080000
251 * EXCTL (Execution Control) Register commands
255 * @def IX_NPEDL_EXCTL_CMD_NPE_STEP
256 * @brief EXCTL Command to Step execution of an NPE Instruction
259 #define IX_NPEDL_EXCTL_CMD_NPE_STEP 0x01
262 * @def IX_NPEDL_EXCTL_CMD_NPE_START
263 * @brief EXCTL Command to Start NPE execution
265 #define IX_NPEDL_EXCTL_CMD_NPE_START 0x02
268 * @def IX_NPEDL_EXCTL_CMD_NPE_STOP
269 * @brief EXCTL Command to Stop NPE execution
271 #define IX_NPEDL_EXCTL_CMD_NPE_STOP 0x03
274 * @def IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE
275 * @brief EXCTL Command to Clear NPE instruction pipeline
277 #define IX_NPEDL_EXCTL_CMD_NPE_CLR_PIPE 0x04
280 * @def IX_NPEDL_EXCTL_CMD_RD_INS_MEM
281 * @brief EXCTL Command to read NPE instruction memory at address in EXAD
282 * register and return value in EXDATA register
284 #define IX_NPEDL_EXCTL_CMD_RD_INS_MEM 0x10
287 * @def IX_NPEDL_EXCTL_CMD_WR_INS_MEM
288 * @brief EXCTL Command to write NPE instruction memory at address in EXAD
289 * register with data in EXDATA register
291 #define IX_NPEDL_EXCTL_CMD_WR_INS_MEM 0x11
294 * @def IX_NPEDL_EXCTL_CMD_RD_DATA_MEM
295 * @brief EXCTL Command to read NPE data memory at address in EXAD
296 * register and return value in EXDATA register
298 #define IX_NPEDL_EXCTL_CMD_RD_DATA_MEM 0x12
301 * @def IX_NPEDL_EXCTL_CMD_WR_DATA_MEM
302 * @brief EXCTL Command to write NPE data memory at address in EXAD
303 * register with data in EXDATA register
305 #define IX_NPEDL_EXCTL_CMD_WR_DATA_MEM 0x13
308 * @def IX_NPEDL_EXCTL_CMD_RD_ECS_REG
309 * @brief EXCTL Command to read Execution Access register at address in EXAD
310 * register and return value in EXDATA register
312 #define IX_NPEDL_EXCTL_CMD_RD_ECS_REG 0x14
315 * @def IX_NPEDL_EXCTL_CMD_WR_ECS_REG
316 * @brief EXCTL Command to write Execution Access register at address in EXAD
317 * register with data in EXDATA register
319 #define IX_NPEDL_EXCTL_CMD_WR_ECS_REG 0x15
322 * @def IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT
323 * @brief EXCTL Command to clear Profile Count register
325 #define IX_NPEDL_EXCTL_CMD_CLR_PROFILE_CNT 0x0C
329 * EXCTL (Execution Control) Register status bit masks
333 * @def IX_NPEDL_EXCTL_STATUS_RUN
334 * @brief Masks the RUN status bit in the EXCTL register
336 #define IX_NPEDL_EXCTL_STATUS_RUN 0x80000000
339 * @def IX_NPEDL_EXCTL_STATUS_STOP
340 * @brief Masks the STOP status bit in the EXCTL register
342 #define IX_NPEDL_EXCTL_STATUS_STOP 0x40000000
345 * @def IX_NPEDL_EXCTL_STATUS_CLEAR
346 * @brief Masks the CLEAR status bit in the EXCTL register
348 #define IX_NPEDL_EXCTL_STATUS_CLEAR 0x20000000
351 * @def IX_NPEDL_EXCTL_STATUS_ECS_K
352 * @brief Masks the K (pipeline Klean) status bit in the EXCTL register
354 #define IX_NPEDL_EXCTL_STATUS_ECS_K 0x00800000
358 * Executing Context Stack (ECS) level registers
362 * @def IX_NPEDL_ECS_BG_CTXT_REG_0
363 * @brief Execution Access register address for register 0 at Backgound
364 * Executing Context Stack level
366 #define IX_NPEDL_ECS_BG_CTXT_REG_0 0x00
369 * @def IX_NPEDL_ECS_BG_CTXT_REG_1
370 * @brief Execution Access register address for register 1 at Backgound
371 * Executing Context Stack level
373 #define IX_NPEDL_ECS_BG_CTXT_REG_1 0x01
376 * @def IX_NPEDL_ECS_BG_CTXT_REG_2
377 * @brief Execution Access register address for register 2 at Backgound
378 * Executing Context Stack level
380 #define IX_NPEDL_ECS_BG_CTXT_REG_2 0x02
383 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0
384 * @brief Execution Access register address for register 0 at Priority 1
385 * Executing Context Stack level
387 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_0 0x04
390 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1
391 * @brief Execution Access register address for register 1 at Priority 1
392 * Executing Context Stack level
394 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_1 0x05
397 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2
398 * @brief Execution Access register address for register 2 at Priority 1
399 * Executing Context Stack level
401 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_2 0x06
404 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0
405 * @brief Execution Access register address for register 0 at Priority 2
406 * Executing Context Stack level
408 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_0 0x08
411 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1
412 * @brief Execution Access register address for register 1 at Priority 2
413 * Executing Context Stack level
415 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_1 0x09
418 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2
419 * @brief Execution Access register address for register 2 at Priority 2
420 * Executing Context Stack level
422 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_2 0x0A
425 * @def IX_NPEDL_ECS_DBG_CTXT_REG_0
426 * @brief Execution Access register address for register 0 at Debug
427 * Executing Context Stack level
429 #define IX_NPEDL_ECS_DBG_CTXT_REG_0 0x0C
432 * @def IX_NPEDL_ECS_DBG_CTXT_REG_1
433 * @brief Execution Access register address for register 1 at Debug
434 * Executing Context Stack level
436 #define IX_NPEDL_ECS_DBG_CTXT_REG_1 0x0D
439 * @def IX_NPEDL_ECS_DBG_CTXT_REG_2
440 * @brief Execution Access register address for register 2 at Debug
441 * Executing Context Stack level
443 #define IX_NPEDL_ECS_DBG_CTXT_REG_2 0x0E
446 * @def IX_NPEDL_ECS_INSTRUCT_REG
447 * @brief Execution Access register address for NPE Instruction Register
449 #define IX_NPEDL_ECS_INSTRUCT_REG 0x11
453 * Execution Access register reset values
457 * @def IX_NPEDL_ECS_BG_CTXT_REG_0_RESET
458 * @brief Reset value for Execution Access Background ECS level register 0
460 #define IX_NPEDL_ECS_BG_CTXT_REG_0_RESET 0xA0000000
463 * @def IX_NPEDL_ECS_BG_CTXT_REG_1_RESET
464 * @brief Reset value for Execution Access Background ECS level register 1
466 #define IX_NPEDL_ECS_BG_CTXT_REG_1_RESET 0x01000000
469 * @def IX_NPEDL_ECS_BG_CTXT_REG_2_RESET
470 * @brief Reset value for Execution Access Background ECS level register 2
472 #define IX_NPEDL_ECS_BG_CTXT_REG_2_RESET 0x00008000
475 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET
476 * @brief Reset value for Execution Access Priority 1 ECS level register 0
478 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_0_RESET 0x20000080
481 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET
482 * @brief Reset value for Execution Access Priority 1 ECS level register 1
484 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_1_RESET 0x01000000
487 * @def IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET
488 * @brief Reset value for Execution Access Priority 1 ECS level register 2
490 #define IX_NPEDL_ECS_PRI_1_CTXT_REG_2_RESET 0x00008000
493 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET
494 * @brief Reset value for Execution Access Priority 2 ECS level register 0
496 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_0_RESET 0x20000080
499 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET
500 * @brief Reset value for Execution Access Priority 2 ECS level register 1
502 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_1_RESET 0x01000000
505 * @def IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET
506 * @brief Reset value for Execution Access Priority 2 ECS level register 2
508 #define IX_NPEDL_ECS_PRI_2_CTXT_REG_2_RESET 0x00008000
511 * @def IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET
512 * @brief Reset value for Execution Access Debug ECS level register 0
514 #define IX_NPEDL_ECS_DBG_CTXT_REG_0_RESET 0x20000000
517 * @def IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET
518 * @brief Reset value for Execution Access Debug ECS level register 1
520 #define IX_NPEDL_ECS_DBG_CTXT_REG_1_RESET 0x00000000
523 * @def IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET
524 * @brief Reset value for Execution Access Debug ECS level register 2
526 #define IX_NPEDL_ECS_DBG_CTXT_REG_2_RESET 0x001E0000
529 * @def IX_NPEDL_ECS_INSTRUCT_REG_RESET
530 * @brief Reset value for Execution Access NPE Instruction Register
532 #define IX_NPEDL_ECS_INSTRUCT_REG_RESET 0x1003C00F
536 * masks used to read/write particular bits in Execution Access registers
540 * @def IX_NPEDL_MASK_ECS_REG_0_ACTIVE
541 * @brief Mask the A (Active) bit in Execution Access Register 0 of all ECS
544 #define IX_NPEDL_MASK_ECS_REG_0_ACTIVE 0x80000000
547 * @def IX_NPEDL_MASK_ECS_REG_0_NEXTPC
548 * @brief Mask the NextPC bits in Execution Access Register 0 of all ECS
549 * levels (except Debug ECS level)
551 #define IX_NPEDL_MASK_ECS_REG_0_NEXTPC 0x1FFF0000
554 * @def IX_NPEDL_MASK_ECS_REG_0_LDUR
555 * @brief Mask the LDUR bits in Execution Access Register 0 of all ECS levels
557 #define IX_NPEDL_MASK_ECS_REG_0_LDUR 0x00000700
560 * @def IX_NPEDL_MASK_ECS_REG_1_CCTXT
561 * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
563 #define IX_NPEDL_MASK_ECS_REG_1_CCTXT 0x000F0000
566 * @def IX_NPEDL_MASK_ECS_REG_1_SELCTXT
567 * @brief Mask the NextPC bits in Execution Access Register 1 of all ECS levels
569 #define IX_NPEDL_MASK_ECS_REG_1_SELCTXT 0x0000000F
572 * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IF
573 * @brief Mask the IF bit in Execution Access Register 2 of Debug ECS level
575 #define IX_NPEDL_MASK_ECS_DBG_REG_2_IF 0x00100000
578 * @def IX_NPEDL_MASK_ECS_DBG_REG_2_IE
579 * @brief Mask the IE bit in Execution Access Register 2 of Debug ECS level
581 #define IX_NPEDL_MASK_ECS_DBG_REG_2_IE 0x00080000
585 * Bit-Offsets from LSB of particular bit-fields in Execution Access registers
589 * @def IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC
590 * @brief LSB-offset of NextPC field in Execution Access Register 0 of all ECS
591 * levels (except Debug ECS level)
593 #define IX_NPEDL_OFFSET_ECS_REG_0_NEXTPC 16
596 * @def IX_NPEDL_OFFSET_ECS_REG_0_LDUR
597 * @brief LSB-offset of LDUR field in Execution Access Register 0 of all ECS
600 #define IX_NPEDL_OFFSET_ECS_REG_0_LDUR 8
603 * @def IX_NPEDL_OFFSET_ECS_REG_1_CCTXT
604 * @brief LSB-offset of CCTXT field in Execution Access Register 1 of all ECS
607 #define IX_NPEDL_OFFSET_ECS_REG_1_CCTXT 16
610 * @def IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT
611 * @brief LSB-offset of SELCTXT field in Execution Access Register 1 of all ECS
614 #define IX_NPEDL_OFFSET_ECS_REG_1_SELCTXT 0
618 * NPE core & co-processor instruction templates to load into NPE Instruction
619 * Register, for read/write of NPE register file registers
623 * @def IX_NPEDL_INSTR_RD_REG_BYTE
624 * @brief NPE Instruction, used to read an 8-bit NPE internal logical register
625 * and return the value in the EXDATA register (aligned to MSB).
626 * NPE Assembler instruction: "mov8 d0, d0 &&& DBG_WrExec"
628 #define IX_NPEDL_INSTR_RD_REG_BYTE 0x0FC00000
631 * @def IX_NPEDL_INSTR_RD_REG_SHORT
632 * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
633 * and return the value in the EXDATA register (aligned to MSB).
634 * NPE Assembler instruction: "mov16 d0, d0 &&& DBG_WrExec"
636 #define IX_NPEDL_INSTR_RD_REG_SHORT 0x0FC08010
639 * @def IX_NPEDL_INSTR_RD_REG_WORD
640 * @brief NPE Instruction, used to read a 16-bit NPE internal logical register
641 * and return the value in the EXDATA register.
642 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_WrExec"
644 #define IX_NPEDL_INSTR_RD_REG_WORD 0x0FC08210
647 * @def IX_NPEDL_INSTR_WR_REG_BYTE
648 * @brief NPE Immediate-Mode Instruction, used to write an 8-bit NPE internal
650 * NPE Assembler instruction: "mov8 d0, #0"
652 #define IX_NPEDL_INSTR_WR_REG_BYTE 0x00004000
655 * @def IX_NPEDL_INSTR_WR_REG_SHORT
656 * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
658 * NPE Assembler instruction: "mov16 d0, #0"
660 #define IX_NPEDL_INSTR_WR_REG_SHORT 0x0000C000
663 * @def IX_NPEDL_INSTR_RD_FIFO
664 * @brief NPE Immediate-Mode Instruction, used to write a 16-bit NPE internal
666 * NPE Assembler instruction: "cprd32 d0 &&& DBG_RdInFIFO"
668 #define IX_NPEDL_INSTR_RD_FIFO 0x0F888220
671 * @def IX_NPEDL_INSTR_RESET_MBOX
672 * @brief NPE Instruction, used to reset Mailbox (MBST) register
673 * NPE Assembler instruction: "mov32 d0, d0 &&& DBG_ClearM"
675 #define IX_NPEDL_INSTR_RESET_MBOX 0x0FAC8210
679 * Bit-offsets from LSB, of particular bit-fields in an NPE instruction
683 * @def IX_NPEDL_OFFSET_INSTR_SRC
684 * @brief LSB-offset to SRC (source operand) field of an NPE Instruction
686 #define IX_NPEDL_OFFSET_INSTR_SRC 4
689 * @def IX_NPEDL_OFFSET_INSTR_DEST
690 * @brief LSB-offset to DEST (destination operand) field of an NPE Instruction
692 #define IX_NPEDL_OFFSET_INSTR_DEST 9
695 * @def IX_NPEDL_OFFSET_INSTR_COPROC
696 * @brief LSB-offset to COPROC (coprocessor instruction) field of an NPE
699 #define IX_NPEDL_OFFSET_INSTR_COPROC 18
703 * masks used to read/write particular bits of an NPE Instruction
707 * @def IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA
708 * @brief Mask the bits of 16-bit data value (least-sig 5 bits) to be used in
709 * SRC field of immediate-mode NPE instruction
711 #define IX_NPEDL_MASK_IMMED_INSTR_SRC_DATA 0x1F
714 * @def IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA
715 * @brief Mask the bits of 16-bit data value (most-sig 11 bits) to be used in
716 * COPROC field of immediate-mode NPE instruction
718 #define IX_NPEDL_MASK_IMMED_INSTR_COPROC_DATA 0xFFE0
721 * @def IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA
722 * @brief LSB offset of the bit-field of 16-bit data value (most-sig 11 bits)
723 * to be used in COPROC field of immediate-mode NPE instruction
725 #define IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA 5
728 * @def IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA
729 * @brief Number of left-shifts required to align most-sig 11 bits of 16-bit
730 * data value into COPROC field of immediate-mode NPE instruction
732 #define IX_NPEDL_DISPLACE_IMMED_INSTR_COPROC_DATA \
733 (IX_NPEDL_OFFSET_INSTR_COPROC - IX_NPEDL_OFFSET_IMMED_INSTR_COPROC_DATA)
736 * @def IX_NPEDL_WR_INSTR_LDUR
737 * @brief LDUR value used with immediate-mode NPE Instructions by the NpeDl
738 * for writing to NPE internal logical registers
740 #define IX_NPEDL_WR_INSTR_LDUR 1
743 * @def IX_NPEDL_RD_INSTR_LDUR
744 * @brief LDUR value used with NON-immediate-mode NPE Instructions by the NpeDl
745 * for reading from NPE internal logical registers
747 #define IX_NPEDL_RD_INSTR_LDUR 0
751 * @enum IxNpeDlCtxtRegNum
752 * @brief Numeric values to identify the NPE internal Context Store registers
756 IX_NPEDL_CTXT_REG_STEVT = 0, /**< identifies STEVT */
757 IX_NPEDL_CTXT_REG_STARTPC, /**< identifies STARTPC */
758 IX_NPEDL_CTXT_REG_REGMAP, /**< identifies REGMAP */
759 IX_NPEDL_CTXT_REG_CINDEX, /**< identifies CINDEX */
760 IX_NPEDL_CTXT_REG_MAX /**< Total number of Context Store registers */
765 * NPE Context Store register logical addresses
769 * @def IX_NPEDL_CTXT_REG_ADDR_STEVT
770 * @brief Logical address of STEVT NPE internal Context Store register
772 #define IX_NPEDL_CTXT_REG_ADDR_STEVT 0x0000001B
775 * @def IX_NPEDL_CTXT_REG_ADDR_STARTPC
776 * @brief Logical address of STARTPC NPE internal Context Store register
778 #define IX_NPEDL_CTXT_REG_ADDR_STARTPC 0x0000001C
781 * @def IX_NPEDL_CTXT_REG_ADDR_REGMAP
782 * @brief Logical address of REGMAP NPE internal Context Store register
784 #define IX_NPEDL_CTXT_REG_ADDR_REGMAP 0x0000001E
787 * @def IX_NPEDL_CTXT_REG_ADDR_CINDEX
788 * @brief Logical address of CINDEX NPE internal Context Store register
790 #define IX_NPEDL_CTXT_REG_ADDR_CINDEX 0x0000001F
794 * NPE Context Store register reset values
798 * @def IX_NPEDL_CTXT_REG_RESET_STEVT
799 * @brief Reset value of STEVT NPE internal Context Store register
800 * (STEVT = off, 0x80)
802 #define IX_NPEDL_CTXT_REG_RESET_STEVT 0x80
805 * @def IX_NPEDL_CTXT_REG_RESET_STARTPC
806 * @brief Reset value of STARTPC NPE internal Context Store register
809 #define IX_NPEDL_CTXT_REG_RESET_STARTPC 0x0000
812 * @def IX_NPEDL_CTXT_REG_RESET_REGMAP
813 * @brief Reset value of REGMAP NPE internal Context Store register
814 * (REGMAP = d0->p0, d8->p2, d16->p4)
816 #define IX_NPEDL_CTXT_REG_RESET_REGMAP 0x0820
819 * @def IX_NPEDL_CTXT_REG_RESET_CINDEX
820 * @brief Reset value of CINDEX NPE internal Context Store register
823 #define IX_NPEDL_CTXT_REG_RESET_CINDEX 0x00
827 * numeric range of context levels available on an NPE
831 * @def IX_NPEDL_CTXT_NUM_MIN
832 * @brief Lowest NPE Context number in range
834 #define IX_NPEDL_CTXT_NUM_MIN 0
837 * @def IX_NPEDL_CTXT_NUM_MAX
838 * @brief Highest NPE Context number in range
840 #define IX_NPEDL_CTXT_NUM_MAX 15
844 * Physical NPE internal registers
848 * @def IX_NPEDL_TOTAL_NUM_PHYS_REG
849 * @brief Number of Physical registers currently supported
850 * Initial NPE implementations will have a 32-word register file.
851 * Later implementations may have a 64-word register file.
853 #define IX_NPEDL_TOTAL_NUM_PHYS_REG 32
856 * @def IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP
857 * @brief LSB-offset of Regmap number in Physical NPE register address, used
858 * for Physical To Logical register address mapping in the NPE
860 #define IX_NPEDL_OFFSET_PHYS_REG_ADDR_REGMAP 1
863 * @def IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR
864 * @brief Mask to extract a logical NPE register address from a physical
865 * register address, used for Physical To Logical address mapping
867 #define IX_NPEDL_MASK_PHYS_REG_ADDR_LOGICAL_ADDR 0x1
869 #endif /* IXNPEDLNPEMGRECREGISTERS_P_H */