2 * Copyright (C) 2003 - 2009 NetXen, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
23 * Contact Information:
27 * Cupertino, CA 95014-0701
31 #include "netxen_nic.h"
33 #define NETXEN_GB_MAC_SOFT_RESET 0x80000000
34 #define NETXEN_GB_MAC_RESET_PROT_BLK 0x000F0000
35 #define NETXEN_GB_MAC_ENABLE_TX_RX 0x00000005
36 #define NETXEN_GB_MAC_PAUSED_FRMS 0x00000020
38 static long phy_lock_timeout = 100000000;
40 static int phy_lock(struct netxen_adapter *adapter)
43 int done = 0, timeout = 0;
46 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM3_LOCK));
49 if (timeout >= phy_lock_timeout) {
56 for (i = 0; i < 20; i++)
61 NXWR32(adapter, NETXEN_PHY_LOCK_ID, PHY_LOCK_DRIVER);
65 static int phy_unlock(struct netxen_adapter *adapter)
67 adapter->pci_read_immediate(adapter, NETXEN_PCIE_REG(PCIE_SEM3_UNLOCK));
73 * netxen_niu_gbe_phy_read - read a register from the GbE PHY via
74 * mii management interface.
76 * Note: The MII management interface goes through port 0.
77 * Individual phys are addressed as follows:
78 * @param phy [15:8] phy id
79 * @param reg [7:0] register number
81 * @returns 0 on success
85 int netxen_niu_gbe_phy_read(struct netxen_adapter *adapter, long reg,
91 long phy = adapter->physical_port;
97 if (phy_lock(adapter) != 0) {
102 * MII mgmt all goes through port 0 MAC interface,
103 * so it cannot be in reset
106 mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
107 if (netxen_gb_get_soft_reset(mac_cfg0)) {
110 netxen_gb_tx_reset_pb(temp);
111 netxen_gb_rx_reset_pb(temp);
112 netxen_gb_tx_reset_mac(temp);
113 netxen_gb_rx_reset_mac(temp);
114 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
120 netxen_gb_mii_mgmt_reg_addr(address, reg);
121 netxen_gb_mii_mgmt_phy_addr(address, phy);
122 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
124 command = 0; /* turn off any prior activity */
125 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
127 /* send read command */
128 netxen_gb_mii_mgmt_set_read_cycle(command);
129 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
134 status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
136 } while ((netxen_get_gb_mii_mgmt_busy(status)
137 || netxen_get_gb_mii_mgmt_notvalid(status))
138 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
140 if (timeout < NETXEN_NIU_PHY_WAITMAX) {
141 *readval = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_STATUS(0));
147 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
154 * netxen_niu_gbe_phy_write - write a register to the GbE PHY via
155 * mii management interface.
157 * Note: The MII management interface goes through port 0.
158 * Individual phys are addressed as follows:
159 * @param phy [15:8] phy id
160 * @param reg [7:0] register number
162 * @returns 0 on success
166 int netxen_niu_gbe_phy_write(struct netxen_adapter *adapter, long reg,
172 long phy = adapter->physical_port;
179 * MII mgmt all goes through port 0 MAC interface, so it
183 mac_cfg0 = NXRD32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0));
184 if (netxen_gb_get_soft_reset(mac_cfg0)) {
187 netxen_gb_tx_reset_pb(temp);
188 netxen_gb_rx_reset_pb(temp);
189 netxen_gb_tx_reset_mac(temp);
190 netxen_gb_rx_reset_mac(temp);
192 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), temp))
197 command = 0; /* turn off any prior activity */
198 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_COMMAND(0), command))
202 netxen_gb_mii_mgmt_reg_addr(address, reg);
203 netxen_gb_mii_mgmt_phy_addr(address, phy);
204 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_ADDR(0), address))
207 if (NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CTRL(0), val))
212 status = NXRD32(adapter, NETXEN_NIU_GB_MII_MGMT_INDICATE(0));
214 } while ((netxen_get_gb_mii_mgmt_busy(status))
215 && (timeout++ < NETXEN_NIU_PHY_WAITMAX));
217 if (timeout < NETXEN_NIU_PHY_WAITMAX)
222 /* restore the state of port 0 MAC in case we tampered with it */
224 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(0), mac_cfg0))
230 int netxen_niu_xgbe_enable_phy_interrupts(struct netxen_adapter *adapter)
232 NXWR32(adapter, NETXEN_NIU_INT_MASK, 0x3f);
236 int netxen_niu_gbe_enable_phy_interrupts(struct netxen_adapter *adapter)
240 netxen_set_phy_int_link_status_changed(enable);
241 netxen_set_phy_int_autoneg_completed(enable);
242 netxen_set_phy_int_speed_changed(enable);
245 netxen_niu_gbe_phy_write(adapter,
246 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE,
253 int netxen_niu_xgbe_disable_phy_interrupts(struct netxen_adapter *adapter)
255 NXWR32(adapter, NETXEN_NIU_INT_MASK, 0x7f);
259 int netxen_niu_gbe_disable_phy_interrupts(struct netxen_adapter *adapter)
263 netxen_niu_gbe_phy_write(adapter,
264 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_ENABLE, 0))
270 static int netxen_niu_gbe_clear_phy_interrupts(struct netxen_adapter *adapter)
274 netxen_niu_gbe_phy_write(adapter,
275 NETXEN_NIU_GB_MII_MGMT_ADDR_INT_STATUS,
283 * netxen_niu_gbe_set_mii_mode- Set 10/100 Mbit Mode for GbE MAC
286 static void netxen_niu_gbe_set_mii_mode(struct netxen_adapter *adapter,
287 int port, long enable)
289 NXWR32(adapter, NETXEN_NIU_MODE, 0x2);
290 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x80000000);
291 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x0000f0025);
292 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 0xf1ff);
293 NXWR32(adapter, NETXEN_NIU_GB0_GMII_MODE + (port << 3), 0);
294 NXWR32(adapter, NETXEN_NIU_GB0_MII_MODE + (port << 3), 1);
295 NXWR32(adapter, (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
296 NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
300 * Do NOT enable flow control until a suitable solution for
301 * shutting down pause frames is found.
303 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x5);
306 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
307 printk(KERN_ERR "ERROR enabling PHY interrupts\n");
308 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
309 printk(KERN_ERR "ERROR clearing PHY interrupts\n");
313 * netxen_niu_gbe_set_gmii_mode- Set GbE Mode for GbE MAC
315 static void netxen_niu_gbe_set_gmii_mode(struct netxen_adapter *adapter,
316 int port, long enable)
318 NXWR32(adapter, NETXEN_NIU_MODE, 0x2);
319 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x80000000);
320 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x0000f0025);
321 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_1(port), 0xf2ff);
322 NXWR32(adapter, NETXEN_NIU_GB0_MII_MODE + (port << 3), 0);
323 NXWR32(adapter, NETXEN_NIU_GB0_GMII_MODE + (port << 3), 1);
324 NXWR32(adapter, (NETXEN_NIU_GB0_HALF_DUPLEX + port * 4), 0);
325 NXWR32(adapter, NETXEN_NIU_GB_MII_MGMT_CONFIG(port), 0x7);
329 * Do NOT enable flow control until a suitable solution for
330 * shutting down pause frames is found.
332 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), 0x5);
335 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
336 printk(KERN_ERR "ERROR enabling PHY interrupts\n");
337 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
338 printk(KERN_ERR "ERROR clearing PHY interrupts\n");
341 int netxen_niu_gbe_init_port(struct netxen_adapter *adapter, int port)
346 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
349 if (adapter->disable_phy_interrupts)
350 adapter->disable_phy_interrupts(adapter);
353 if (0 == netxen_niu_gbe_phy_read(adapter,
354 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS, &status)) {
355 if (netxen_get_phy_link(status)) {
356 if (netxen_get_phy_speed(status) == 2) {
357 netxen_niu_gbe_set_gmii_mode(adapter, port, 1);
358 } else if ((netxen_get_phy_speed(status) == 1)
359 || (netxen_get_phy_speed(status) == 0)) {
360 netxen_niu_gbe_set_mii_mode(adapter, port, 1);
367 * We don't have link. Cable must be unconnected.
368 * Enable phy interrupts so we take action when
372 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
373 NETXEN_GB_MAC_SOFT_RESET);
374 NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port),
375 NETXEN_GB_MAC_RESET_PROT_BLK |
376 NETXEN_GB_MAC_ENABLE_TX_RX |
377 NETXEN_GB_MAC_PAUSED_FRMS);
378 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
380 "ERROR clearing PHY interrupts\n");
381 if (netxen_niu_gbe_enable_phy_interrupts(adapter))
383 "ERROR enabling PHY interrupts\n");
384 if (netxen_niu_gbe_clear_phy_interrupts(adapter))
386 "ERROR clearing PHY interrupts\n");
395 int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
397 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
398 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
399 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
405 /* Disable a GbE interface */
406 int netxen_niu_disable_gbe_port(struct netxen_adapter *adapter)
409 u32 port = adapter->physical_port;
411 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
414 if (port > NETXEN_NIU_MAX_GBE_PORTS)
417 netxen_gb_soft_reset(mac_cfg0);
418 if (NXWR32(adapter, NETXEN_NIU_GB_MAC_CONFIG_0(port), mac_cfg0))
423 /* Disable an XG interface */
424 int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
427 u32 port = adapter->physical_port;
429 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
432 if (port > NETXEN_NIU_MAX_XG_PORTS)
437 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
442 /* Set promiscuous mode for a GbE interface */
443 int netxen_niu_set_promiscuous_mode(struct netxen_adapter *adapter,
447 u32 port = adapter->physical_port;
449 if (port > NETXEN_NIU_MAX_GBE_PORTS)
452 /* save previous contents */
453 reg = NXRD32(adapter, NETXEN_NIU_GB_DROP_WRONGADDR);
454 if (mode == NETXEN_NIU_PROMISC_MODE) {
457 netxen_clear_gb_drop_gb0(reg);
460 netxen_clear_gb_drop_gb1(reg);
463 netxen_clear_gb_drop_gb2(reg);
466 netxen_clear_gb_drop_gb3(reg);
474 netxen_set_gb_drop_gb0(reg);
477 netxen_set_gb_drop_gb1(reg);
480 netxen_set_gb_drop_gb2(reg);
483 netxen_set_gb_drop_gb3(reg);
489 if (NXWR32(adapter, NETXEN_NIU_GB_DROP_WRONGADDR, reg))
494 int netxen_niu_xg_set_promiscuous_mode(struct netxen_adapter *adapter,
498 u32 port = adapter->physical_port;
500 if (port > NETXEN_NIU_MAX_XG_PORTS)
503 reg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
504 if (mode == NETXEN_NIU_PROMISC_MODE)
505 reg = (reg | 0x2000UL);
507 reg = (reg & ~0x2000UL);
509 if (mode == NETXEN_NIU_ALLMULTI_MODE)
510 reg = (reg | 0x1000UL);
512 reg = (reg & ~0x1000UL);
514 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
519 int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
524 u8 phy = adapter->physical_port;
525 u8 phy_count = (adapter->ahw.port_type == NETXEN_NIC_XGBE) ?
526 NETXEN_NIU_MAX_XG_PORTS : NETXEN_NIU_MAX_GBE_PORTS;
528 if (phy >= phy_count)
531 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
532 mac_hi = addr[2] | ((u32)addr[3] << 8) |
533 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
535 if (adapter->ahw.port_type == NETXEN_NIC_XGBE) {
536 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
537 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
539 reg_lo = NETXEN_NIU_GB_STATION_ADDR_1(phy);
540 reg_hi = NETXEN_NIU_GB_STATION_ADDR_0(phy);
543 /* write twice to flush */
544 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
546 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))