2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
41 #include <linux/tcp.h>
42 #include <linux/udp.h>
43 #include <linux/etherdevice.h>
44 #include <linux/delay.h>
45 #include <linux/ethtool.h>
46 #include <linux/platform_device.h>
47 #include <linux/module.h>
48 #include <linux/kernel.h>
49 #include <linux/spinlock.h>
50 #include <linux/workqueue.h>
51 #include <linux/mii.h>
52 #include <linux/mv643xx_eth.h>
54 #include <asm/types.h>
55 #include <asm/system.h>
57 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
58 static char mv643xx_eth_driver_version[] = "1.0";
60 #define MV643XX_ETH_CHECKSUM_OFFLOAD_TX
61 #define MV643XX_ETH_NAPI
62 #define MV643XX_ETH_TX_FAST_REFILL
63 #undef MV643XX_ETH_COAL
65 #define MV643XX_ETH_TX_COAL 100
66 #ifdef MV643XX_ETH_COAL
67 #define MV643XX_ETH_RX_COAL 100
70 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
71 #define MAX_DESCS_PER_SKB (MAX_SKB_FRAGS + 1)
73 #define MAX_DESCS_PER_SKB 1
76 #define ETH_VLAN_HLEN 4
78 #define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
79 #define ETH_WRAPPER_LEN (ETH_HW_IP_ALIGN + ETH_HLEN + \
80 ETH_VLAN_HLEN + ETH_FCS_LEN)
81 #define ETH_RX_SKB_SIZE (dev->mtu + ETH_WRAPPER_LEN + \
82 dma_get_cache_alignment())
85 * Registers shared between all ports.
87 #define PHY_ADDR 0x0000
88 #define SMI_REG 0x0004
89 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
90 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
91 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
92 #define WINDOW_BAR_ENABLE 0x0290
93 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
98 #define PORT_CONFIG(p) (0x0400 + ((p) << 10))
99 #define UNICAST_PROMISCUOUS_MODE 0x00000001
100 #define PORT_CONFIG_EXT(p) (0x0404 + ((p) << 10))
101 #define MAC_ADDR_LOW(p) (0x0414 + ((p) << 10))
102 #define MAC_ADDR_HIGH(p) (0x0418 + ((p) << 10))
103 #define SDMA_CONFIG(p) (0x041c + ((p) << 10))
104 #define PORT_SERIAL_CONTROL(p) (0x043c + ((p) << 10))
105 #define PORT_STATUS(p) (0x0444 + ((p) << 10))
106 #define TX_FIFO_EMPTY 0x00000400
107 #define TXQ_COMMAND(p) (0x0448 + ((p) << 10))
108 #define TX_BW_MTU(p) (0x0458 + ((p) << 10))
109 #define INT_CAUSE(p) (0x0460 + ((p) << 10))
110 #define INT_RX 0x00000804
111 #define INT_EXT 0x00000002
112 #define INT_CAUSE_EXT(p) (0x0464 + ((p) << 10))
113 #define INT_EXT_LINK 0x00100000
114 #define INT_EXT_PHY 0x00010000
115 #define INT_EXT_TX_ERROR_0 0x00000100
116 #define INT_EXT_TX_0 0x00000001
117 #define INT_EXT_TX 0x00000101
118 #define INT_MASK(p) (0x0468 + ((p) << 10))
119 #define INT_MASK_EXT(p) (0x046c + ((p) << 10))
120 #define TX_FIFO_URGENT_THRESHOLD(p) (0x0474 + ((p) << 10))
121 #define RXQ_CURRENT_DESC_PTR(p) (0x060c + ((p) << 10))
122 #define RXQ_COMMAND(p) (0x0680 + ((p) << 10))
123 #define TXQ_CURRENT_DESC_PTR(p) (0x06c0 + ((p) << 10))
124 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
125 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
126 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
127 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
131 * SDMA configuration register.
133 #define RX_BURST_SIZE_4_64BIT (2 << 1)
134 #define BLM_RX_NO_SWAP (1 << 4)
135 #define BLM_TX_NO_SWAP (1 << 5)
136 #define TX_BURST_SIZE_4_64BIT (2 << 22)
138 #if defined(__BIG_ENDIAN)
139 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
140 RX_BURST_SIZE_4_64BIT | \
141 TX_BURST_SIZE_4_64BIT
142 #elif defined(__LITTLE_ENDIAN)
143 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
144 RX_BURST_SIZE_4_64BIT | \
147 TX_BURST_SIZE_4_64BIT
149 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
154 * Port serial control register.
156 #define SET_MII_SPEED_TO_100 (1 << 24)
157 #define SET_GMII_SPEED_TO_1000 (1 << 23)
158 #define SET_FULL_DUPLEX_MODE (1 << 21)
159 #define MAX_RX_PACKET_1522BYTE (1 << 17)
160 #define MAX_RX_PACKET_9700BYTE (5 << 17)
161 #define MAX_RX_PACKET_MASK (7 << 17)
162 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
163 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
164 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
165 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
166 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
167 #define FORCE_LINK_PASS (1 << 1)
168 #define SERIAL_PORT_ENABLE (1 << 0)
170 #define DEFAULT_RX_QUEUE_SIZE 400
171 #define DEFAULT_TX_QUEUE_SIZE 800
174 #define SMI_BUSY 0x10000000 /* 0 - Write, 1 - Read */
175 #define SMI_READ_VALID 0x08000000 /* 0 - Write, 1 - Read */
176 #define SMI_OPCODE_WRITE 0 /* Completion of Read */
177 #define SMI_OPCODE_READ 0x04000000 /* Operation is in progress */
183 #if defined(__BIG_ENDIAN)
185 u16 byte_cnt; /* Descriptor buffer byte count */
186 u16 buf_size; /* Buffer size */
187 u32 cmd_sts; /* Descriptor command status */
188 u32 next_desc_ptr; /* Next descriptor pointer */
189 u32 buf_ptr; /* Descriptor buffer pointer */
193 u16 byte_cnt; /* buffer byte count */
194 u16 l4i_chk; /* CPU provided TCP checksum */
195 u32 cmd_sts; /* Command/status field */
196 u32 next_desc_ptr; /* Pointer to next descriptor */
197 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199 #elif defined(__LITTLE_ENDIAN)
201 u32 cmd_sts; /* Descriptor command status */
202 u16 buf_size; /* Buffer size */
203 u16 byte_cnt; /* Descriptor buffer byte count */
204 u32 buf_ptr; /* Descriptor buffer pointer */
205 u32 next_desc_ptr; /* Next descriptor pointer */
209 u32 cmd_sts; /* Command/status field */
210 u16 l4i_chk; /* CPU provided TCP checksum */
211 u16 byte_cnt; /* buffer byte count */
212 u32 buf_ptr; /* pointer to buffer for this descriptor*/
213 u32 next_desc_ptr; /* Pointer to next descriptor */
216 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
219 /* RX & TX descriptor command */
220 #define BUFFER_OWNED_BY_DMA 0x80000000
222 /* RX & TX descriptor status */
223 #define ERROR_SUMMARY 0x00000001
225 /* RX descriptor status */
226 #define LAYER_4_CHECKSUM_OK 0x40000000
227 #define RX_ENABLE_INTERRUPT 0x20000000
228 #define RX_FIRST_DESC 0x08000000
229 #define RX_LAST_DESC 0x04000000
231 /* TX descriptor command */
232 #define TX_ENABLE_INTERRUPT 0x00800000
233 #define GEN_CRC 0x00400000
234 #define TX_FIRST_DESC 0x00200000
235 #define TX_LAST_DESC 0x00100000
236 #define ZERO_PADDING 0x00080000
237 #define GEN_IP_V4_CHECKSUM 0x00040000
238 #define GEN_TCP_UDP_CHECKSUM 0x00020000
239 #define UDP_FRAME 0x00010000
241 #define TX_IHL_SHIFT 11
244 /* global *******************************************************************/
245 struct mv643xx_eth_shared_private {
248 /* used to protect SMI_REG, which is shared across ports */
257 /* per-port *****************************************************************/
258 struct mib_counters {
259 u64 good_octets_received;
260 u32 bad_octets_received;
261 u32 internal_mac_transmit_err;
262 u32 good_frames_received;
263 u32 bad_frames_received;
264 u32 broadcast_frames_received;
265 u32 multicast_frames_received;
266 u32 frames_64_octets;
267 u32 frames_65_to_127_octets;
268 u32 frames_128_to_255_octets;
269 u32 frames_256_to_511_octets;
270 u32 frames_512_to_1023_octets;
271 u32 frames_1024_to_max_octets;
272 u64 good_octets_sent;
273 u32 good_frames_sent;
274 u32 excessive_collision;
275 u32 multicast_frames_sent;
276 u32 broadcast_frames_sent;
277 u32 unrec_mac_control_received;
279 u32 good_fc_received;
281 u32 undersize_received;
282 u32 fragments_received;
283 u32 oversize_received;
285 u32 mac_receive_error;
291 struct mv643xx_eth_private {
292 struct mv643xx_eth_shared_private *shared;
293 int port_num; /* User Ethernet port number */
295 struct mv643xx_eth_shared_private *shared_smi;
297 u32 rx_sram_addr; /* Base address of rx sram area */
298 u32 rx_sram_size; /* Size of rx sram area */
299 u32 tx_sram_addr; /* Base address of tx sram area */
300 u32 tx_sram_size; /* Size of tx sram area */
302 /* Tx/Rx rings managment indexes fields. For driver use */
304 /* Next available and first returning Rx resource */
305 int rx_curr_desc, rx_used_desc;
307 /* Next available and first returning Tx resource */
308 int tx_curr_desc, tx_used_desc;
310 #ifdef MV643XX_ETH_TX_FAST_REFILL
311 u32 tx_clean_threshold;
314 struct rx_desc *rx_desc_area;
315 dma_addr_t rx_desc_dma;
316 int rx_desc_area_size;
317 struct sk_buff **rx_skb;
319 struct tx_desc *tx_desc_area;
320 dma_addr_t tx_desc_dma;
321 int tx_desc_area_size;
322 struct sk_buff **tx_skb;
324 struct work_struct tx_timeout_task;
326 struct net_device *dev;
327 struct napi_struct napi;
328 struct net_device_stats stats;
329 struct mib_counters mib_counters;
331 /* Size of Tx Ring per queue */
333 /* Number of tx descriptors in use */
335 /* Size of Rx Ring per queue */
337 /* Number of rx descriptors in use */
341 * Used in case RX Ring is empty, which can be caused when
342 * system does not have resources (skb's)
344 struct timer_list timeout;
348 struct mii_if_info mii;
352 /* port register accessors **************************************************/
353 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
355 return readl(mp->shared->base + offset);
358 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
360 writel(data, mp->shared->base + offset);
364 /* rxq/txq helper functions *************************************************/
365 static void mv643xx_eth_port_enable_rx(struct mv643xx_eth_private *mp,
368 wrl(mp, RXQ_COMMAND(mp->port_num), queues);
371 static unsigned int mv643xx_eth_port_disable_rx(struct mv643xx_eth_private *mp)
373 unsigned int port_num = mp->port_num;
376 /* Stop Rx port activity. Check port Rx activity. */
377 queues = rdl(mp, RXQ_COMMAND(port_num)) & 0xFF;
379 /* Issue stop command for active queues only */
380 wrl(mp, RXQ_COMMAND(port_num), (queues << 8));
382 /* Wait for all Rx activity to terminate. */
383 /* Check port cause register that all Rx queues are stopped */
384 while (rdl(mp, RXQ_COMMAND(port_num)) & 0xFF)
391 static void mv643xx_eth_port_enable_tx(struct mv643xx_eth_private *mp,
394 wrl(mp, TXQ_COMMAND(mp->port_num), queues);
397 static unsigned int mv643xx_eth_port_disable_tx(struct mv643xx_eth_private *mp)
399 unsigned int port_num = mp->port_num;
402 /* Stop Tx port activity. Check port Tx activity. */
403 queues = rdl(mp, TXQ_COMMAND(port_num)) & 0xFF;
405 /* Issue stop command for active queues only */
406 wrl(mp, TXQ_COMMAND(port_num), (queues << 8));
408 /* Wait for all Tx activity to terminate. */
409 /* Check port cause register that all Tx queues are stopped */
410 while (rdl(mp, TXQ_COMMAND(port_num)) & 0xFF)
413 /* Wait for Tx FIFO to empty */
414 while (rdl(mp, PORT_STATUS(port_num)) & TX_FIFO_EMPTY)
422 /* rx ***********************************************************************/
423 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev);
425 static void mv643xx_eth_rx_refill_descs(struct net_device *dev)
427 struct mv643xx_eth_private *mp = netdev_priv(dev);
430 spin_lock_irqsave(&mp->lock, flags);
432 while (mp->rx_desc_count < mp->rx_ring_size) {
437 skb = dev_alloc_skb(ETH_RX_SKB_SIZE + dma_get_cache_alignment());
441 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
443 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
446 rx = mp->rx_used_desc;
447 mp->rx_used_desc = (rx + 1) % mp->rx_ring_size;
449 mp->rx_desc_area[rx].buf_ptr = dma_map_single(NULL,
453 mp->rx_desc_area[rx].buf_size = ETH_RX_SKB_SIZE;
454 mp->rx_skb[rx] = skb;
456 mp->rx_desc_area[rx].cmd_sts = BUFFER_OWNED_BY_DMA |
460 skb_reserve(skb, ETH_HW_IP_ALIGN);
463 if (mp->rx_desc_count == 0) {
464 mp->timeout.expires = jiffies + (HZ / 10);
465 add_timer(&mp->timeout);
468 spin_unlock_irqrestore(&mp->lock, flags);
471 static inline void mv643xx_eth_rx_refill_descs_timer_wrapper(unsigned long data)
473 mv643xx_eth_rx_refill_descs((struct net_device *)data);
476 static int mv643xx_eth_receive_queue(struct net_device *dev, int budget)
478 struct mv643xx_eth_private *mp = netdev_priv(dev);
479 struct net_device_stats *stats = &dev->stats;
480 unsigned int received_packets = 0;
482 while (budget-- > 0) {
484 volatile struct rx_desc *rx_desc;
485 unsigned int cmd_sts;
488 spin_lock_irqsave(&mp->lock, flags);
490 rx_desc = &mp->rx_desc_area[mp->rx_curr_desc];
492 cmd_sts = rx_desc->cmd_sts;
493 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
494 spin_unlock_irqrestore(&mp->lock, flags);
499 skb = mp->rx_skb[mp->rx_curr_desc];
500 mp->rx_skb[mp->rx_curr_desc] = NULL;
502 mp->rx_curr_desc = (mp->rx_curr_desc + 1) % mp->rx_ring_size;
504 spin_unlock_irqrestore(&mp->lock, flags);
506 dma_unmap_single(NULL, rx_desc->buf_ptr + ETH_HW_IP_ALIGN,
507 ETH_RX_SKB_SIZE, DMA_FROM_DEVICE);
513 * Note byte count includes 4 byte CRC count
516 stats->rx_bytes += rx_desc->byte_cnt - ETH_HW_IP_ALIGN;
519 * In case received a packet without first / last bits on OR
520 * the error summary bit is on, the packets needs to be dropeed.
522 if (((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
523 (RX_FIRST_DESC | RX_LAST_DESC))
524 || (cmd_sts & ERROR_SUMMARY)) {
526 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
527 (RX_FIRST_DESC | RX_LAST_DESC)) {
530 "%s: Received packet spread "
531 "on multiple descriptors\n",
534 if (cmd_sts & ERROR_SUMMARY)
537 dev_kfree_skb_irq(skb);
540 * The -4 is for the CRC in the trailer of the
543 skb_put(skb, rx_desc->byte_cnt - ETH_HW_IP_ALIGN - 4);
545 if (cmd_sts & LAYER_4_CHECKSUM_OK) {
546 skb->ip_summed = CHECKSUM_UNNECESSARY;
548 (cmd_sts & 0x0007fff8) >> 3);
550 skb->protocol = eth_type_trans(skb, dev);
551 #ifdef MV643XX_ETH_NAPI
552 netif_receive_skb(skb);
557 dev->last_rx = jiffies;
559 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
561 return received_packets;
564 #ifdef MV643XX_ETH_NAPI
565 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
567 struct mv643xx_eth_private *mp = container_of(napi, struct mv643xx_eth_private, napi);
568 struct net_device *dev = mp->dev;
569 unsigned int port_num = mp->port_num;
572 #ifdef MV643XX_ETH_TX_FAST_REFILL
573 if (++mp->tx_clean_threshold > 5) {
574 mv643xx_eth_free_completed_tx_descs(dev);
575 mp->tx_clean_threshold = 0;
580 if ((rdl(mp, RXQ_CURRENT_DESC_PTR(port_num)))
581 != (u32) mp->rx_used_desc)
582 work_done = mv643xx_eth_receive_queue(dev, budget);
584 if (work_done < budget) {
585 netif_rx_complete(dev, napi);
586 wrl(mp, INT_CAUSE(port_num), 0);
587 wrl(mp, INT_CAUSE_EXT(port_num), 0);
588 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
596 /* tx ***********************************************************************/
597 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
602 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
603 fragp = &skb_shinfo(skb)->frags[frag];
604 if (fragp->size <= 8 && fragp->page_offset & 0x7)
610 static int alloc_tx_desc_index(struct mv643xx_eth_private *mp)
614 BUG_ON(mp->tx_desc_count >= mp->tx_ring_size);
616 tx_desc_curr = mp->tx_curr_desc;
617 mp->tx_curr_desc = (tx_desc_curr + 1) % mp->tx_ring_size;
619 BUG_ON(mp->tx_curr_desc == mp->tx_used_desc);
624 static void tx_fill_frag_descs(struct mv643xx_eth_private *mp,
629 struct tx_desc *desc;
631 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
632 skb_frag_t *this_frag = &skb_shinfo(skb)->frags[frag];
634 tx_index = alloc_tx_desc_index(mp);
635 desc = &mp->tx_desc_area[tx_index];
637 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
638 /* Last Frag enables interrupt and frees the skb */
639 if (frag == (skb_shinfo(skb)->nr_frags - 1)) {
640 desc->cmd_sts |= ZERO_PADDING |
643 mp->tx_skb[tx_index] = skb;
645 mp->tx_skb[tx_index] = NULL;
647 desc = &mp->tx_desc_area[tx_index];
649 desc->byte_cnt = this_frag->size;
650 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
651 this_frag->page_offset,
657 static inline __be16 sum16_as_be(__sum16 sum)
659 return (__force __be16)sum;
662 static void tx_submit_descs_for_skb(struct mv643xx_eth_private *mp,
666 struct tx_desc *desc;
669 int nr_frags = skb_shinfo(skb)->nr_frags;
671 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
673 tx_index = alloc_tx_desc_index(mp);
674 desc = &mp->tx_desc_area[tx_index];
677 tx_fill_frag_descs(mp, skb);
679 length = skb_headlen(skb);
680 mp->tx_skb[tx_index] = NULL;
682 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
684 mp->tx_skb[tx_index] = skb;
687 desc->byte_cnt = length;
688 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
690 if (skb->ip_summed == CHECKSUM_PARTIAL) {
691 BUG_ON(skb->protocol != htons(ETH_P_IP));
693 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
695 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
697 switch (ip_hdr(skb)->protocol) {
699 cmd_sts |= UDP_FRAME;
700 desc->l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
703 desc->l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
709 /* Errata BTS #50, IHL must be 5 if no HW checksum */
710 cmd_sts |= 5 << TX_IHL_SHIFT;
714 /* ensure all other descriptors are written before first cmd_sts */
716 desc->cmd_sts = cmd_sts;
718 /* ensure all descriptors are written before poking hardware */
720 mv643xx_eth_port_enable_tx(mp, 1);
722 mp->tx_desc_count += nr_frags + 1;
725 static int mv643xx_eth_start_xmit(struct sk_buff *skb, struct net_device *dev)
727 struct mv643xx_eth_private *mp = netdev_priv(dev);
728 struct net_device_stats *stats = &dev->stats;
731 BUG_ON(netif_queue_stopped(dev));
733 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
735 printk(KERN_DEBUG "%s: failed to linearize tiny "
736 "unaligned fragment\n", dev->name);
737 return NETDEV_TX_BUSY;
740 spin_lock_irqsave(&mp->lock, flags);
742 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB) {
743 printk(KERN_ERR "%s: transmit with queue full\n", dev->name);
744 netif_stop_queue(dev);
745 spin_unlock_irqrestore(&mp->lock, flags);
746 return NETDEV_TX_BUSY;
749 tx_submit_descs_for_skb(mp, skb);
750 stats->tx_bytes += skb->len;
752 dev->trans_start = jiffies;
754 if (mp->tx_ring_size - mp->tx_desc_count < MAX_DESCS_PER_SKB)
755 netif_stop_queue(dev);
757 spin_unlock_irqrestore(&mp->lock, flags);
763 /* mii management interface *************************************************/
764 static int phy_addr_get(struct mv643xx_eth_private *mp);
766 static void read_smi_reg(struct mv643xx_eth_private *mp,
767 unsigned int phy_reg, unsigned int *value)
769 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
770 int phy_addr = phy_addr_get(mp);
774 /* the SMI register is a shared resource */
775 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
777 /* wait for the SMI register to become available */
778 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
780 printk("%s: PHY busy timeout\n", mp->dev->name);
786 writel((phy_addr << 16) | (phy_reg << 21) | SMI_OPCODE_READ, smi_reg);
788 /* now wait for the data to be valid */
789 for (i = 0; !(readl(smi_reg) & SMI_READ_VALID); i++) {
791 printk("%s: PHY read timeout\n", mp->dev->name);
797 *value = readl(smi_reg) & 0xffff;
799 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
802 static void write_smi_reg(struct mv643xx_eth_private *mp,
803 unsigned int phy_reg, unsigned int value)
805 void __iomem *smi_reg = mp->shared_smi->base + SMI_REG;
806 int phy_addr = phy_addr_get(mp);
810 /* the SMI register is a shared resource */
811 spin_lock_irqsave(&mp->shared_smi->phy_lock, flags);
813 /* wait for the SMI register to become available */
814 for (i = 0; readl(smi_reg) & SMI_BUSY; i++) {
816 printk("%s: PHY busy timeout\n", mp->dev->name);
822 writel((phy_addr << 16) | (phy_reg << 21) |
823 SMI_OPCODE_WRITE | (value & 0xffff), smi_reg);
825 spin_unlock_irqrestore(&mp->shared_smi->phy_lock, flags);
829 /* mib counters *************************************************************/
830 static void clear_mib_counters(struct mv643xx_eth_private *mp)
832 unsigned int port_num = mp->port_num;
835 /* Perform dummy reads from MIB counters */
836 for (i = 0; i < 0x80; i += 4)
837 rdl(mp, MIB_COUNTERS(port_num) + i);
840 static inline u32 read_mib(struct mv643xx_eth_private *mp, int offset)
842 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
845 static void update_mib_counters(struct mv643xx_eth_private *mp)
847 struct mib_counters *p = &mp->mib_counters;
849 p->good_octets_received += read_mib(mp, 0x00);
850 p->good_octets_received += (u64)read_mib(mp, 0x04) << 32;
851 p->bad_octets_received += read_mib(mp, 0x08);
852 p->internal_mac_transmit_err += read_mib(mp, 0x0c);
853 p->good_frames_received += read_mib(mp, 0x10);
854 p->bad_frames_received += read_mib(mp, 0x14);
855 p->broadcast_frames_received += read_mib(mp, 0x18);
856 p->multicast_frames_received += read_mib(mp, 0x1c);
857 p->frames_64_octets += read_mib(mp, 0x20);
858 p->frames_65_to_127_octets += read_mib(mp, 0x24);
859 p->frames_128_to_255_octets += read_mib(mp, 0x28);
860 p->frames_256_to_511_octets += read_mib(mp, 0x2c);
861 p->frames_512_to_1023_octets += read_mib(mp, 0x30);
862 p->frames_1024_to_max_octets += read_mib(mp, 0x34);
863 p->good_octets_sent += read_mib(mp, 0x38);
864 p->good_octets_sent += (u64)read_mib(mp, 0x3c) << 32;
865 p->good_frames_sent += read_mib(mp, 0x40);
866 p->excessive_collision += read_mib(mp, 0x44);
867 p->multicast_frames_sent += read_mib(mp, 0x48);
868 p->broadcast_frames_sent += read_mib(mp, 0x4c);
869 p->unrec_mac_control_received += read_mib(mp, 0x50);
870 p->fc_sent += read_mib(mp, 0x54);
871 p->good_fc_received += read_mib(mp, 0x58);
872 p->bad_fc_received += read_mib(mp, 0x5c);
873 p->undersize_received += read_mib(mp, 0x60);
874 p->fragments_received += read_mib(mp, 0x64);
875 p->oversize_received += read_mib(mp, 0x68);
876 p->jabber_received += read_mib(mp, 0x6c);
877 p->mac_receive_error += read_mib(mp, 0x70);
878 p->bad_crc_event += read_mib(mp, 0x74);
879 p->collision += read_mib(mp, 0x78);
880 p->late_collision += read_mib(mp, 0x7c);
884 /* ethtool ******************************************************************/
885 struct mv643xx_eth_stats {
886 char stat_string[ETH_GSTRING_LEN];
891 #define MV643XX_ETH_STAT(m) FIELD_SIZEOF(struct mv643xx_eth_private, m), \
892 offsetof(struct mv643xx_eth_private, m)
894 static const struct mv643xx_eth_stats mv643xx_eth_gstrings_stats[] = {
895 { "rx_packets", MV643XX_ETH_STAT(stats.rx_packets) },
896 { "tx_packets", MV643XX_ETH_STAT(stats.tx_packets) },
897 { "rx_bytes", MV643XX_ETH_STAT(stats.rx_bytes) },
898 { "tx_bytes", MV643XX_ETH_STAT(stats.tx_bytes) },
899 { "rx_errors", MV643XX_ETH_STAT(stats.rx_errors) },
900 { "tx_errors", MV643XX_ETH_STAT(stats.tx_errors) },
901 { "rx_dropped", MV643XX_ETH_STAT(stats.rx_dropped) },
902 { "tx_dropped", MV643XX_ETH_STAT(stats.tx_dropped) },
903 { "good_octets_received", MV643XX_ETH_STAT(mib_counters.good_octets_received) },
904 { "bad_octets_received", MV643XX_ETH_STAT(mib_counters.bad_octets_received) },
905 { "internal_mac_transmit_err", MV643XX_ETH_STAT(mib_counters.internal_mac_transmit_err) },
906 { "good_frames_received", MV643XX_ETH_STAT(mib_counters.good_frames_received) },
907 { "bad_frames_received", MV643XX_ETH_STAT(mib_counters.bad_frames_received) },
908 { "broadcast_frames_received", MV643XX_ETH_STAT(mib_counters.broadcast_frames_received) },
909 { "multicast_frames_received", MV643XX_ETH_STAT(mib_counters.multicast_frames_received) },
910 { "frames_64_octets", MV643XX_ETH_STAT(mib_counters.frames_64_octets) },
911 { "frames_65_to_127_octets", MV643XX_ETH_STAT(mib_counters.frames_65_to_127_octets) },
912 { "frames_128_to_255_octets", MV643XX_ETH_STAT(mib_counters.frames_128_to_255_octets) },
913 { "frames_256_to_511_octets", MV643XX_ETH_STAT(mib_counters.frames_256_to_511_octets) },
914 { "frames_512_to_1023_octets", MV643XX_ETH_STAT(mib_counters.frames_512_to_1023_octets) },
915 { "frames_1024_to_max_octets", MV643XX_ETH_STAT(mib_counters.frames_1024_to_max_octets) },
916 { "good_octets_sent", MV643XX_ETH_STAT(mib_counters.good_octets_sent) },
917 { "good_frames_sent", MV643XX_ETH_STAT(mib_counters.good_frames_sent) },
918 { "excessive_collision", MV643XX_ETH_STAT(mib_counters.excessive_collision) },
919 { "multicast_frames_sent", MV643XX_ETH_STAT(mib_counters.multicast_frames_sent) },
920 { "broadcast_frames_sent", MV643XX_ETH_STAT(mib_counters.broadcast_frames_sent) },
921 { "unrec_mac_control_received", MV643XX_ETH_STAT(mib_counters.unrec_mac_control_received) },
922 { "fc_sent", MV643XX_ETH_STAT(mib_counters.fc_sent) },
923 { "good_fc_received", MV643XX_ETH_STAT(mib_counters.good_fc_received) },
924 { "bad_fc_received", MV643XX_ETH_STAT(mib_counters.bad_fc_received) },
925 { "undersize_received", MV643XX_ETH_STAT(mib_counters.undersize_received) },
926 { "fragments_received", MV643XX_ETH_STAT(mib_counters.fragments_received) },
927 { "oversize_received", MV643XX_ETH_STAT(mib_counters.oversize_received) },
928 { "jabber_received", MV643XX_ETH_STAT(mib_counters.jabber_received) },
929 { "mac_receive_error", MV643XX_ETH_STAT(mib_counters.mac_receive_error) },
930 { "bad_crc_event", MV643XX_ETH_STAT(mib_counters.bad_crc_event) },
931 { "collision", MV643XX_ETH_STAT(mib_counters.collision) },
932 { "late_collision", MV643XX_ETH_STAT(mib_counters.late_collision) },
935 #define MV643XX_ETH_STATS_LEN ARRAY_SIZE(mv643xx_eth_gstrings_stats)
937 static int mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
939 struct mv643xx_eth_private *mp = netdev_priv(dev);
942 spin_lock_irq(&mp->lock);
943 err = mii_ethtool_gset(&mp->mii, cmd);
944 spin_unlock_irq(&mp->lock);
946 /* The PHY may support 1000baseT_Half, but the mv643xx does not */
947 cmd->supported &= ~SUPPORTED_1000baseT_Half;
948 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
953 static int mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
955 struct mv643xx_eth_private *mp = netdev_priv(dev);
958 spin_lock_irq(&mp->lock);
959 err = mii_ethtool_sset(&mp->mii, cmd);
960 spin_unlock_irq(&mp->lock);
965 static void mv643xx_eth_get_drvinfo(struct net_device *netdev,
966 struct ethtool_drvinfo *drvinfo)
968 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
969 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
970 strncpy(drvinfo->fw_version, "N/A", 32);
971 strncpy(drvinfo->bus_info, "mv643xx", 32);
972 drvinfo->n_stats = MV643XX_ETH_STATS_LEN;
975 static int mv643xx_eth_nway_restart(struct net_device *dev)
977 struct mv643xx_eth_private *mp = netdev_priv(dev);
979 return mii_nway_restart(&mp->mii);
982 static u32 mv643xx_eth_get_link(struct net_device *dev)
984 struct mv643xx_eth_private *mp = netdev_priv(dev);
986 return mii_link_ok(&mp->mii);
989 static void mv643xx_eth_get_strings(struct net_device *netdev, uint32_t stringset,
996 for (i=0; i < MV643XX_ETH_STATS_LEN; i++) {
997 memcpy(data + i * ETH_GSTRING_LEN,
998 mv643xx_eth_gstrings_stats[i].stat_string,
1005 static void mv643xx_eth_get_ethtool_stats(struct net_device *netdev,
1006 struct ethtool_stats *stats, uint64_t *data)
1008 struct mv643xx_eth_private *mp = netdev->priv;
1011 update_mib_counters(mp);
1013 for (i = 0; i < MV643XX_ETH_STATS_LEN; i++) {
1014 char *p = (char *)mp+mv643xx_eth_gstrings_stats[i].stat_offset;
1015 data[i] = (mv643xx_eth_gstrings_stats[i].sizeof_stat ==
1016 sizeof(uint64_t)) ? *(uint64_t *)p : *(uint32_t *)p;
1020 static int mv643xx_eth_get_sset_count(struct net_device *netdev, int sset)
1024 return MV643XX_ETH_STATS_LEN;
1030 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1031 .get_settings = mv643xx_eth_get_settings,
1032 .set_settings = mv643xx_eth_set_settings,
1033 .get_drvinfo = mv643xx_eth_get_drvinfo,
1034 .get_link = mv643xx_eth_get_link,
1035 .set_sg = ethtool_op_set_sg,
1036 .get_sset_count = mv643xx_eth_get_sset_count,
1037 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1038 .get_strings = mv643xx_eth_get_strings,
1039 .nway_reset = mv643xx_eth_nway_restart,
1043 /* address handling *********************************************************/
1044 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1046 unsigned int port_num = mp->port_num;
1050 mac_h = rdl(mp, MAC_ADDR_HIGH(port_num));
1051 mac_l = rdl(mp, MAC_ADDR_LOW(port_num));
1053 addr[0] = (mac_h >> 24) & 0xff;
1054 addr[1] = (mac_h >> 16) & 0xff;
1055 addr[2] = (mac_h >> 8) & 0xff;
1056 addr[3] = mac_h & 0xff;
1057 addr[4] = (mac_l >> 8) & 0xff;
1058 addr[5] = mac_l & 0xff;
1061 static void init_mac_tables(struct mv643xx_eth_private *mp)
1063 unsigned int port_num = mp->port_num;
1066 /* Clear DA filter unicast table (Ex_dFUT) */
1067 for (table_index = 0; table_index <= 0xC; table_index += 4)
1068 wrl(mp, UNICAST_TABLE(port_num) + table_index, 0);
1070 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1071 /* Clear DA filter special multicast table (Ex_dFSMT) */
1072 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1073 /* Clear DA filter other multicast table (Ex_dFOMT) */
1074 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1078 static void set_filter_table_entry(struct mv643xx_eth_private *mp,
1079 int table, unsigned char entry)
1081 unsigned int table_reg;
1082 unsigned int tbl_offset;
1083 unsigned int reg_offset;
1085 tbl_offset = (entry / 4) * 4; /* Register offset of DA table entry */
1086 reg_offset = entry % 4; /* Entry offset within the register */
1088 /* Set "accepts frame bit" at specified table entry */
1089 table_reg = rdl(mp, table + tbl_offset);
1090 table_reg |= 0x01 << (8 * reg_offset);
1091 wrl(mp, table + tbl_offset, table_reg);
1094 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1096 unsigned int port_num = mp->port_num;
1101 mac_l = (addr[4] << 8) | (addr[5]);
1102 mac_h = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) |
1105 wrl(mp, MAC_ADDR_LOW(port_num), mac_l);
1106 wrl(mp, MAC_ADDR_HIGH(port_num), mac_h);
1108 /* Accept frames with this address */
1109 table = UNICAST_TABLE(port_num);
1110 set_filter_table_entry(mp, table, addr[5] & 0x0f);
1113 static void mv643xx_eth_update_mac_address(struct net_device *dev)
1115 struct mv643xx_eth_private *mp = netdev_priv(dev);
1117 init_mac_tables(mp);
1118 uc_addr_set(mp, dev->dev_addr);
1121 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1125 for (i = 0; i < 6; i++)
1126 /* +2 is for the offset of the HW addr type */
1127 dev->dev_addr[i] = ((unsigned char *)addr)[i + 2];
1128 mv643xx_eth_update_mac_address(dev);
1132 static void mc_addr(struct mv643xx_eth_private *mp, unsigned char *addr)
1134 unsigned int port_num = mp->port_num;
1137 unsigned char crc_result = 0;
1143 if ((addr[0] == 0x01) && (addr[1] == 0x00) &&
1144 (addr[2] == 0x5E) && (addr[3] == 0x00) && (addr[4] == 0x00)) {
1145 table = SPECIAL_MCAST_TABLE(port_num);
1146 set_filter_table_entry(mp, table, addr[5]);
1150 /* Calculate CRC-8 out of the given address */
1151 mac_h = (addr[0] << 8) | (addr[1]);
1152 mac_l = (addr[2] << 24) | (addr[3] << 16) |
1153 (addr[4] << 8) | (addr[5] << 0);
1155 for (i = 0; i < 32; i++)
1156 mac_array[i] = (mac_l >> i) & 0x1;
1157 for (i = 32; i < 48; i++)
1158 mac_array[i] = (mac_h >> (i - 32)) & 0x1;
1160 crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ mac_array[39] ^
1161 mac_array[35] ^ mac_array[34] ^ mac_array[31] ^ mac_array[30] ^
1162 mac_array[28] ^ mac_array[23] ^ mac_array[21] ^ mac_array[19] ^
1163 mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ mac_array[12] ^
1164 mac_array[8] ^ mac_array[7] ^ mac_array[6] ^ mac_array[0];
1166 crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1167 mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ mac_array[34] ^
1168 mac_array[32] ^ mac_array[30] ^ mac_array[29] ^ mac_array[28] ^
1169 mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ mac_array[21] ^
1170 mac_array[20] ^ mac_array[18] ^ mac_array[17] ^ mac_array[16] ^
1171 mac_array[15] ^ mac_array[14] ^ mac_array[13] ^ mac_array[12] ^
1172 mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ mac_array[0];
1174 crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ mac_array[43] ^
1175 mac_array[42] ^ mac_array[39] ^ mac_array[37] ^ mac_array[34] ^
1176 mac_array[33] ^ mac_array[29] ^ mac_array[28] ^ mac_array[25] ^
1177 mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ mac_array[15] ^
1178 mac_array[13] ^ mac_array[12] ^ mac_array[10] ^ mac_array[8] ^
1179 mac_array[6] ^ mac_array[2] ^ mac_array[1] ^ mac_array[0];
1181 crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ mac_array[43] ^
1182 mac_array[40] ^ mac_array[38] ^ mac_array[35] ^ mac_array[34] ^
1183 mac_array[30] ^ mac_array[29] ^ mac_array[26] ^ mac_array[25] ^
1184 mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ mac_array[14] ^
1185 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[7] ^
1186 mac_array[3] ^ mac_array[2] ^ mac_array[1];
1188 crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ mac_array[41] ^
1189 mac_array[39] ^ mac_array[36] ^ mac_array[35] ^ mac_array[31] ^
1190 mac_array[30] ^ mac_array[27] ^ mac_array[26] ^ mac_array[24] ^
1191 mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ mac_array[14] ^
1192 mac_array[12] ^ mac_array[10] ^ mac_array[8] ^ mac_array[4] ^
1193 mac_array[3] ^ mac_array[2];
1195 crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ mac_array[42] ^
1196 mac_array[40] ^ mac_array[37] ^ mac_array[36] ^ mac_array[32] ^
1197 mac_array[31] ^ mac_array[28] ^ mac_array[27] ^ mac_array[25] ^
1198 mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ mac_array[15] ^
1199 mac_array[13] ^ mac_array[11] ^ mac_array[9] ^ mac_array[5] ^
1200 mac_array[4] ^ mac_array[3];
1202 crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ mac_array[41] ^
1203 mac_array[38] ^ mac_array[37] ^ mac_array[33] ^ mac_array[32] ^
1204 mac_array[29] ^ mac_array[28] ^ mac_array[26] ^ mac_array[21] ^
1205 mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ mac_array[14] ^
1206 mac_array[12] ^ mac_array[10] ^ mac_array[6] ^ mac_array[5] ^
1209 crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ mac_array[39] ^
1210 mac_array[38] ^ mac_array[34] ^ mac_array[33] ^ mac_array[30] ^
1211 mac_array[29] ^ mac_array[27] ^ mac_array[22] ^ mac_array[20] ^
1212 mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ mac_array[13] ^
1213 mac_array[11] ^ mac_array[7] ^ mac_array[6] ^ mac_array[5];
1215 for (i = 0; i < 8; i++)
1216 crc_result = crc_result | (crc[i] << i);
1218 table = OTHER_MCAST_TABLE(port_num);
1219 set_filter_table_entry(mp, table, crc_result);
1222 static void set_multicast_list(struct net_device *dev)
1225 struct dev_mc_list *mc_list;
1228 struct mv643xx_eth_private *mp = netdev_priv(dev);
1229 unsigned int port_num = mp->port_num;
1231 /* If the device is in promiscuous mode or in all multicast mode,
1232 * we will fully populate both multicast tables with accept.
1233 * This is guaranteed to yield a match on all multicast addresses...
1235 if ((dev->flags & IFF_PROMISC) || (dev->flags & IFF_ALLMULTI)) {
1236 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1237 /* Set all entries in DA filter special multicast
1239 * Set for ETH_Q0 for now
1241 * 0 Accept=1, Drop=0
1242 * 3-1 Queue ETH_Q0=0
1245 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0x01010101);
1247 /* Set all entries in DA filter other multicast
1249 * Set for ETH_Q0 for now
1251 * 0 Accept=1, Drop=0
1252 * 3-1 Queue ETH_Q0=0
1255 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0x01010101);
1260 /* We will clear out multicast tables every time we get the list.
1261 * Then add the entire new list...
1263 for (table_index = 0; table_index <= 0xFC; table_index += 4) {
1264 /* Clear DA filter special multicast table (Ex_dFSMT) */
1265 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + table_index, 0);
1267 /* Clear DA filter other multicast table (Ex_dFOMT) */
1268 wrl(mp, OTHER_MCAST_TABLE(port_num) + table_index, 0);
1271 /* Get pointer to net_device multicast list and add each one... */
1272 for (i = 0, mc_list = dev->mc_list;
1273 (i < 256) && (mc_list != NULL) && (i < dev->mc_count);
1274 i++, mc_list = mc_list->next)
1275 if (mc_list->dmi_addrlen == 6)
1276 mc_addr(mp, mc_list->dmi_addr);
1279 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1281 struct mv643xx_eth_private *mp = netdev_priv(dev);
1284 config_reg = rdl(mp, PORT_CONFIG(mp->port_num));
1285 if (dev->flags & IFF_PROMISC)
1286 config_reg |= UNICAST_PROMISCUOUS_MODE;
1288 config_reg &= ~UNICAST_PROMISCUOUS_MODE;
1289 wrl(mp, PORT_CONFIG(mp->port_num), config_reg);
1291 set_multicast_list(dev);
1295 /* rx/tx queue initialisation ***********************************************/
1296 static void ether_init_rx_desc_ring(struct mv643xx_eth_private *mp)
1298 volatile struct rx_desc *p_rx_desc;
1299 int rx_desc_num = mp->rx_ring_size;
1302 /* initialize the next_desc_ptr links in the Rx descriptors ring */
1303 p_rx_desc = (struct rx_desc *)mp->rx_desc_area;
1304 for (i = 0; i < rx_desc_num; i++) {
1305 p_rx_desc[i].next_desc_ptr = mp->rx_desc_dma +
1306 ((i + 1) % rx_desc_num) * sizeof(struct rx_desc);
1309 /* Save Rx desc pointer to driver struct. */
1310 mp->rx_curr_desc = 0;
1311 mp->rx_used_desc = 0;
1313 mp->rx_desc_area_size = rx_desc_num * sizeof(struct rx_desc);
1316 static void mv643xx_eth_free_rx_rings(struct net_device *dev)
1318 struct mv643xx_eth_private *mp = netdev_priv(dev);
1321 /* Stop RX Queues */
1322 mv643xx_eth_port_disable_rx(mp);
1324 /* Free preallocated skb's on RX rings */
1325 for (curr = 0; mp->rx_desc_count && curr < mp->rx_ring_size; curr++) {
1326 if (mp->rx_skb[curr]) {
1327 dev_kfree_skb(mp->rx_skb[curr]);
1328 mp->rx_desc_count--;
1332 if (mp->rx_desc_count)
1334 "%s: Error in freeing Rx Ring. %d skb's still"
1335 " stuck in RX Ring - ignoring them\n", dev->name,
1338 if (mp->rx_sram_size)
1339 iounmap(mp->rx_desc_area);
1341 dma_free_coherent(NULL, mp->rx_desc_area_size,
1342 mp->rx_desc_area, mp->rx_desc_dma);
1345 static void ether_init_tx_desc_ring(struct mv643xx_eth_private *mp)
1347 int tx_desc_num = mp->tx_ring_size;
1348 struct tx_desc *p_tx_desc;
1351 /* Initialize the next_desc_ptr links in the Tx descriptors ring */
1352 p_tx_desc = (struct tx_desc *)mp->tx_desc_area;
1353 for (i = 0; i < tx_desc_num; i++) {
1354 p_tx_desc[i].next_desc_ptr = mp->tx_desc_dma +
1355 ((i + 1) % tx_desc_num) * sizeof(struct tx_desc);
1358 mp->tx_curr_desc = 0;
1359 mp->tx_used_desc = 0;
1361 mp->tx_desc_area_size = tx_desc_num * sizeof(struct tx_desc);
1364 static int mv643xx_eth_free_tx_descs(struct net_device *dev, int force)
1366 struct mv643xx_eth_private *mp = netdev_priv(dev);
1367 struct tx_desc *desc;
1369 struct sk_buff *skb;
1370 unsigned long flags;
1376 while (mp->tx_desc_count > 0) {
1377 spin_lock_irqsave(&mp->lock, flags);
1379 /* tx_desc_count might have changed before acquiring the lock */
1380 if (mp->tx_desc_count <= 0) {
1381 spin_unlock_irqrestore(&mp->lock, flags);
1385 tx_index = mp->tx_used_desc;
1386 desc = &mp->tx_desc_area[tx_index];
1387 cmd_sts = desc->cmd_sts;
1389 if (!force && (cmd_sts & BUFFER_OWNED_BY_DMA)) {
1390 spin_unlock_irqrestore(&mp->lock, flags);
1394 mp->tx_used_desc = (tx_index + 1) % mp->tx_ring_size;
1395 mp->tx_desc_count--;
1397 addr = desc->buf_ptr;
1398 count = desc->byte_cnt;
1399 skb = mp->tx_skb[tx_index];
1401 mp->tx_skb[tx_index] = NULL;
1403 if (cmd_sts & ERROR_SUMMARY) {
1404 printk("%s: Error in TX\n", dev->name);
1405 dev->stats.tx_errors++;
1408 spin_unlock_irqrestore(&mp->lock, flags);
1410 if (cmd_sts & TX_FIRST_DESC)
1411 dma_unmap_single(NULL, addr, count, DMA_TO_DEVICE);
1413 dma_unmap_page(NULL, addr, count, DMA_TO_DEVICE);
1416 dev_kfree_skb_irq(skb);
1424 static void mv643xx_eth_free_completed_tx_descs(struct net_device *dev)
1426 struct mv643xx_eth_private *mp = netdev_priv(dev);
1428 if (mv643xx_eth_free_tx_descs(dev, 0) &&
1429 mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1430 netif_wake_queue(dev);
1433 static void mv643xx_eth_free_all_tx_descs(struct net_device *dev)
1435 mv643xx_eth_free_tx_descs(dev, 1);
1438 static void mv643xx_eth_free_tx_rings(struct net_device *dev)
1440 struct mv643xx_eth_private *mp = netdev_priv(dev);
1442 /* Stop Tx Queues */
1443 mv643xx_eth_port_disable_tx(mp);
1445 /* Free outstanding skb's on TX ring */
1446 mv643xx_eth_free_all_tx_descs(dev);
1448 BUG_ON(mp->tx_used_desc != mp->tx_curr_desc);
1451 if (mp->tx_sram_size)
1452 iounmap(mp->tx_desc_area);
1454 dma_free_coherent(NULL, mp->tx_desc_area_size,
1455 mp->tx_desc_area, mp->tx_desc_dma);
1459 /* netdev ops and related ***************************************************/
1460 static void port_reset(struct mv643xx_eth_private *mp);
1462 static void mv643xx_eth_update_pscr(struct net_device *dev,
1463 struct ethtool_cmd *ecmd)
1465 struct mv643xx_eth_private *mp = netdev_priv(dev);
1466 int port_num = mp->port_num;
1468 unsigned int queues;
1470 o_pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1473 /* clear speed, duplex and rx buffer size fields */
1474 n_pscr &= ~(SET_MII_SPEED_TO_100 |
1475 SET_GMII_SPEED_TO_1000 |
1476 SET_FULL_DUPLEX_MODE |
1477 MAX_RX_PACKET_MASK);
1479 if (ecmd->duplex == DUPLEX_FULL)
1480 n_pscr |= SET_FULL_DUPLEX_MODE;
1482 if (ecmd->speed == SPEED_1000)
1483 n_pscr |= SET_GMII_SPEED_TO_1000 |
1484 MAX_RX_PACKET_9700BYTE;
1486 if (ecmd->speed == SPEED_100)
1487 n_pscr |= SET_MII_SPEED_TO_100;
1488 n_pscr |= MAX_RX_PACKET_1522BYTE;
1491 if (n_pscr != o_pscr) {
1492 if ((o_pscr & SERIAL_PORT_ENABLE) == 0)
1493 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1495 queues = mv643xx_eth_port_disable_tx(mp);
1497 o_pscr &= ~SERIAL_PORT_ENABLE;
1498 wrl(mp, PORT_SERIAL_CONTROL(port_num), o_pscr);
1499 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1500 wrl(mp, PORT_SERIAL_CONTROL(port_num), n_pscr);
1502 mv643xx_eth_port_enable_tx(mp, queues);
1507 static irqreturn_t mv643xx_eth_int_handler(int irq, void *dev_id)
1509 struct net_device *dev = (struct net_device *)dev_id;
1510 struct mv643xx_eth_private *mp = netdev_priv(dev);
1511 u32 int_cause, int_cause_ext = 0;
1512 unsigned int port_num = mp->port_num;
1514 /* Read interrupt cause registers */
1515 int_cause = rdl(mp, INT_CAUSE(port_num)) & (INT_RX | INT_EXT);
1516 if (int_cause & INT_EXT) {
1517 int_cause_ext = rdl(mp, INT_CAUSE_EXT(port_num))
1518 & (INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1519 wrl(mp, INT_CAUSE_EXT(port_num), ~int_cause_ext);
1522 /* PHY status changed */
1523 if (int_cause_ext & (INT_EXT_LINK | INT_EXT_PHY)) {
1524 struct ethtool_cmd cmd;
1526 if (mii_link_ok(&mp->mii)) {
1527 mii_ethtool_gset(&mp->mii, &cmd);
1528 mv643xx_eth_update_pscr(dev, &cmd);
1529 mv643xx_eth_port_enable_tx(mp, 1);
1530 if (!netif_carrier_ok(dev)) {
1531 netif_carrier_on(dev);
1532 if (mp->tx_ring_size - mp->tx_desc_count >=
1534 netif_wake_queue(dev);
1536 } else if (netif_carrier_ok(dev)) {
1537 netif_stop_queue(dev);
1538 netif_carrier_off(dev);
1542 #ifdef MV643XX_ETH_NAPI
1543 if (int_cause & INT_RX) {
1544 /* schedule the NAPI poll routine to maintain port */
1545 wrl(mp, INT_MASK(port_num), 0x00000000);
1547 /* wait for previous write to complete */
1548 rdl(mp, INT_MASK(port_num));
1550 netif_rx_schedule(dev, &mp->napi);
1553 if (int_cause & INT_RX)
1554 mv643xx_eth_receive_queue(dev, INT_MAX);
1556 if (int_cause_ext & INT_EXT_TX)
1557 mv643xx_eth_free_completed_tx_descs(dev);
1560 * If no real interrupt occured, exit.
1561 * This can happen when using gigE interrupt coalescing mechanism.
1563 if ((int_cause == 0x0) && (int_cause_ext == 0x0))
1569 static void phy_reset(struct mv643xx_eth_private *mp)
1571 unsigned int phy_reg_data;
1574 read_smi_reg(mp, 0, &phy_reg_data);
1575 phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */
1576 write_smi_reg(mp, 0, phy_reg_data);
1578 /* wait for PHY to come out of reset */
1581 read_smi_reg(mp, 0, &phy_reg_data);
1582 } while (phy_reg_data & 0x8000);
1585 static void port_start(struct net_device *dev)
1587 struct mv643xx_eth_private *mp = netdev_priv(dev);
1588 unsigned int port_num = mp->port_num;
1589 int tx_curr_desc, rx_curr_desc;
1591 struct ethtool_cmd ethtool_cmd;
1593 /* Assignment of Tx CTRP of given queue */
1594 tx_curr_desc = mp->tx_curr_desc;
1595 wrl(mp, TXQ_CURRENT_DESC_PTR(port_num),
1596 (u32)((struct tx_desc *)mp->tx_desc_dma + tx_curr_desc));
1598 /* Assignment of Rx CRDP of given queue */
1599 rx_curr_desc = mp->rx_curr_desc;
1600 wrl(mp, RXQ_CURRENT_DESC_PTR(port_num),
1601 (u32)((struct rx_desc *)mp->rx_desc_dma + rx_curr_desc));
1603 /* Add the assigned Ethernet address to the port's address table */
1604 uc_addr_set(mp, dev->dev_addr);
1607 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
1608 * frames to RX queue #0.
1610 wrl(mp, PORT_CONFIG(port_num), 0x00000000);
1613 * Treat BPDUs as normal multicasts, and disable partition mode.
1615 wrl(mp, PORT_CONFIG_EXT(port_num), 0x00000000);
1617 pscr = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1619 pscr &= ~(SERIAL_PORT_ENABLE | FORCE_LINK_PASS);
1620 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1622 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL |
1623 DISABLE_AUTO_NEG_SPEED_GMII |
1624 DISABLE_AUTO_NEG_FOR_DUPLEX |
1625 DO_NOT_FORCE_LINK_FAIL |
1626 SERIAL_PORT_CONTROL_RESERVED;
1628 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1630 pscr |= SERIAL_PORT_ENABLE;
1631 wrl(mp, PORT_SERIAL_CONTROL(port_num), pscr);
1633 /* Assign port SDMA configuration */
1634 wrl(mp, SDMA_CONFIG(port_num), PORT_SDMA_CONFIG_DEFAULT_VALUE);
1636 /* Enable port Rx. */
1637 mv643xx_eth_port_enable_rx(mp, 1);
1639 /* Disable port bandwidth limits by clearing MTU register */
1640 wrl(mp, TX_BW_MTU(port_num), 0);
1642 /* save phy settings across reset */
1643 mv643xx_eth_get_settings(dev, ðtool_cmd);
1645 mv643xx_eth_set_settings(dev, ðtool_cmd);
1648 #ifdef MV643XX_ETH_COAL
1649 static unsigned int set_rx_coal(struct mv643xx_eth_private *mp,
1652 unsigned int port_num = mp->port_num;
1653 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1655 /* Set RX Coalescing mechanism */
1656 wrl(mp, SDMA_CONFIG(port_num),
1657 ((coal & 0x3fff) << 8) |
1658 (rdl(mp, SDMA_CONFIG(port_num))
1665 static unsigned int set_tx_coal(struct mv643xx_eth_private *mp,
1668 unsigned int coal = ((mp->shared->t_clk / 1000000) * delay) / 64;
1670 /* Set TX Coalescing mechanism */
1671 wrl(mp, TX_FIFO_URGENT_THRESHOLD(mp->port_num), coal << 4);
1676 static void port_init(struct mv643xx_eth_private *mp)
1680 init_mac_tables(mp);
1683 static int mv643xx_eth_open(struct net_device *dev)
1685 struct mv643xx_eth_private *mp = netdev_priv(dev);
1686 unsigned int port_num = mp->port_num;
1690 /* Clear any pending ethernet port interrupts */
1691 wrl(mp, INT_CAUSE(port_num), 0);
1692 wrl(mp, INT_CAUSE_EXT(port_num), 0);
1693 /* wait for previous write to complete */
1694 rdl(mp, INT_CAUSE_EXT(port_num));
1696 err = request_irq(dev->irq, mv643xx_eth_int_handler,
1697 IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, dev);
1699 printk(KERN_ERR "%s: Can not assign IRQ\n", dev->name);
1705 memset(&mp->timeout, 0, sizeof(struct timer_list));
1706 mp->timeout.function = mv643xx_eth_rx_refill_descs_timer_wrapper;
1707 mp->timeout.data = (unsigned long)dev;
1709 /* Allocate RX and TX skb rings */
1710 mp->rx_skb = kmalloc(sizeof(*mp->rx_skb) * mp->rx_ring_size,
1713 printk(KERN_ERR "%s: Cannot allocate Rx skb ring\n", dev->name);
1717 mp->tx_skb = kmalloc(sizeof(*mp->tx_skb) * mp->tx_ring_size,
1720 printk(KERN_ERR "%s: Cannot allocate Tx skb ring\n", dev->name);
1722 goto out_free_rx_skb;
1725 /* Allocate TX ring */
1726 mp->tx_desc_count = 0;
1727 size = mp->tx_ring_size * sizeof(struct tx_desc);
1728 mp->tx_desc_area_size = size;
1730 if (mp->tx_sram_size) {
1731 mp->tx_desc_area = ioremap(mp->tx_sram_addr,
1733 mp->tx_desc_dma = mp->tx_sram_addr;
1735 mp->tx_desc_area = dma_alloc_coherent(NULL, size,
1739 if (!mp->tx_desc_area) {
1740 printk(KERN_ERR "%s: Cannot allocate Tx Ring (size %d bytes)\n",
1743 goto out_free_tx_skb;
1745 BUG_ON((u32) mp->tx_desc_area & 0xf); /* check 16-byte alignment */
1746 memset((void *)mp->tx_desc_area, 0, mp->tx_desc_area_size);
1748 ether_init_tx_desc_ring(mp);
1750 /* Allocate RX ring */
1751 mp->rx_desc_count = 0;
1752 size = mp->rx_ring_size * sizeof(struct rx_desc);
1753 mp->rx_desc_area_size = size;
1755 if (mp->rx_sram_size) {
1756 mp->rx_desc_area = ioremap(mp->rx_sram_addr,
1758 mp->rx_desc_dma = mp->rx_sram_addr;
1760 mp->rx_desc_area = dma_alloc_coherent(NULL, size,
1764 if (!mp->rx_desc_area) {
1765 printk(KERN_ERR "%s: Cannot allocate Rx ring (size %d bytes)\n",
1767 printk(KERN_ERR "%s: Freeing previously allocated TX queues...",
1769 if (mp->rx_sram_size)
1770 iounmap(mp->tx_desc_area);
1772 dma_free_coherent(NULL, mp->tx_desc_area_size,
1773 mp->tx_desc_area, mp->tx_desc_dma);
1775 goto out_free_tx_skb;
1777 memset((void *)mp->rx_desc_area, 0, size);
1779 ether_init_rx_desc_ring(mp);
1781 mv643xx_eth_rx_refill_descs(dev); /* Fill RX ring with skb's */
1783 #ifdef MV643XX_ETH_NAPI
1784 napi_enable(&mp->napi);
1789 /* Interrupt Coalescing */
1791 #ifdef MV643XX_ETH_COAL
1792 mp->rx_int_coal = set_rx_coal(mp, MV643XX_ETH_RX_COAL);
1795 mp->tx_int_coal = set_tx_coal(mp, MV643XX_ETH_TX_COAL);
1797 /* Unmask phy and link status changes interrupts */
1798 wrl(mp, INT_MASK_EXT(port_num), INT_EXT_LINK | INT_EXT_PHY | INT_EXT_TX);
1800 /* Unmask RX buffer and TX end interrupt */
1801 wrl(mp, INT_MASK(port_num), INT_RX | INT_EXT);
1810 free_irq(dev->irq, dev);
1815 static void port_reset(struct mv643xx_eth_private *mp)
1817 unsigned int port_num = mp->port_num;
1818 unsigned int reg_data;
1820 mv643xx_eth_port_disable_tx(mp);
1821 mv643xx_eth_port_disable_rx(mp);
1823 /* Clear all MIB counters */
1824 clear_mib_counters(mp);
1826 /* Reset the Enable bit in the Configuration Register */
1827 reg_data = rdl(mp, PORT_SERIAL_CONTROL(port_num));
1828 reg_data &= ~(SERIAL_PORT_ENABLE |
1829 DO_NOT_FORCE_LINK_FAIL |
1831 wrl(mp, PORT_SERIAL_CONTROL(port_num), reg_data);
1834 static int mv643xx_eth_stop(struct net_device *dev)
1836 struct mv643xx_eth_private *mp = netdev_priv(dev);
1837 unsigned int port_num = mp->port_num;
1839 /* Mask all interrupts on ethernet port */
1840 wrl(mp, INT_MASK(port_num), 0x00000000);
1841 /* wait for previous write to complete */
1842 rdl(mp, INT_MASK(port_num));
1844 #ifdef MV643XX_ETH_NAPI
1845 napi_disable(&mp->napi);
1847 netif_carrier_off(dev);
1848 netif_stop_queue(dev);
1852 mv643xx_eth_free_tx_rings(dev);
1853 mv643xx_eth_free_rx_rings(dev);
1855 free_irq(dev->irq, dev);
1860 static int mv643xx_eth_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1862 struct mv643xx_eth_private *mp = netdev_priv(dev);
1864 return generic_mii_ioctl(&mp->mii, if_mii(ifr), cmd, NULL);
1867 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
1869 if ((new_mtu > 9500) || (new_mtu < 64))
1873 if (!netif_running(dev))
1877 * Stop and then re-open the interface. This will allocate RX
1878 * skbs of the new MTU.
1879 * There is a possible danger that the open will not succeed,
1880 * due to memory being full, which might fail the open function.
1882 mv643xx_eth_stop(dev);
1883 if (mv643xx_eth_open(dev)) {
1884 printk(KERN_ERR "%s: Fatal error on opening device\n",
1891 static void mv643xx_eth_tx_timeout_task(struct work_struct *ugly)
1893 struct mv643xx_eth_private *mp = container_of(ugly, struct mv643xx_eth_private,
1895 struct net_device *dev = mp->dev;
1897 if (!netif_running(dev))
1900 netif_stop_queue(dev);
1905 if (mp->tx_ring_size - mp->tx_desc_count >= MAX_DESCS_PER_SKB)
1906 netif_wake_queue(dev);
1909 static void mv643xx_eth_tx_timeout(struct net_device *dev)
1911 struct mv643xx_eth_private *mp = netdev_priv(dev);
1913 printk(KERN_INFO "%s: TX timeout ", dev->name);
1915 /* Do the reset outside of interrupt context */
1916 schedule_work(&mp->tx_timeout_task);
1919 #ifdef CONFIG_NET_POLL_CONTROLLER
1920 static void mv643xx_eth_netpoll(struct net_device *netdev)
1922 struct mv643xx_eth_private *mp = netdev_priv(netdev);
1923 int port_num = mp->port_num;
1925 wrl(mp, INT_MASK(port_num), 0x00000000);
1926 /* wait for previous write to complete */
1927 rdl(mp, INT_MASK(port_num));
1929 mv643xx_eth_int_handler(netdev->irq, netdev);
1931 wrl(mp, INT_MASK(port_num), INT_RX | INT_CAUSE_EXT);
1935 static int mv643xx_eth_mdio_read(struct net_device *dev, int phy_id, int location)
1937 struct mv643xx_eth_private *mp = netdev_priv(dev);
1940 read_smi_reg(mp, location, &val);
1944 static void mv643xx_eth_mdio_write(struct net_device *dev, int phy_id, int location, int val)
1946 struct mv643xx_eth_private *mp = netdev_priv(dev);
1947 write_smi_reg(mp, location, val);
1951 /* platform glue ************************************************************/
1953 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
1954 struct mbus_dram_target_info *dram)
1956 void __iomem *base = msp->base;
1961 for (i = 0; i < 6; i++) {
1962 writel(0, base + WINDOW_BASE(i));
1963 writel(0, base + WINDOW_SIZE(i));
1965 writel(0, base + WINDOW_REMAP_HIGH(i));
1971 for (i = 0; i < dram->num_cs; i++) {
1972 struct mbus_dram_window *cs = dram->cs + i;
1974 writel((cs->base & 0xffff0000) |
1975 (cs->mbus_attr << 8) |
1976 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
1977 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
1979 win_enable &= ~(1 << i);
1980 win_protect |= 3 << (2 * i);
1983 writel(win_enable, base + WINDOW_BAR_ENABLE);
1984 msp->win_protect = win_protect;
1987 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
1989 static int mv643xx_eth_version_printed = 0;
1990 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
1991 struct mv643xx_eth_shared_private *msp;
1992 struct resource *res;
1995 if (!mv643xx_eth_version_printed++)
1996 printk(KERN_NOTICE "MV-643xx 10/100/1000 Ethernet Driver\n");
1999 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2004 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2007 memset(msp, 0, sizeof(*msp));
2009 msp->base = ioremap(res->start, res->end - res->start + 1);
2010 if (msp->base == NULL)
2013 spin_lock_init(&msp->phy_lock);
2014 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2016 platform_set_drvdata(pdev, msp);
2019 * (Re-)program MBUS remapping windows if we are asked to.
2021 if (pd != NULL && pd->dram != NULL)
2022 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2032 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2034 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2042 static struct platform_driver mv643xx_eth_shared_driver = {
2043 .probe = mv643xx_eth_shared_probe,
2044 .remove = mv643xx_eth_shared_remove,
2046 .name = MV643XX_ETH_SHARED_NAME,
2047 .owner = THIS_MODULE,
2051 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2054 int addr_shift = 5 * mp->port_num;
2056 reg_data = rdl(mp, PHY_ADDR);
2057 reg_data &= ~(0x1f << addr_shift);
2058 reg_data |= (phy_addr & 0x1f) << addr_shift;
2059 wrl(mp, PHY_ADDR, reg_data);
2062 static int phy_addr_get(struct mv643xx_eth_private *mp)
2064 unsigned int reg_data;
2066 reg_data = rdl(mp, PHY_ADDR);
2068 return ((reg_data >> (5 * mp->port_num)) & 0x1f);
2071 static int phy_detect(struct mv643xx_eth_private *mp)
2073 unsigned int phy_reg_data0;
2076 read_smi_reg(mp, 0, &phy_reg_data0);
2077 auto_neg = phy_reg_data0 & 0x1000;
2078 phy_reg_data0 ^= 0x1000; /* invert auto_neg */
2079 write_smi_reg(mp, 0, phy_reg_data0);
2081 read_smi_reg(mp, 0, &phy_reg_data0);
2082 if ((phy_reg_data0 & 0x1000) == auto_neg)
2083 return -ENODEV; /* change didn't take */
2085 phy_reg_data0 ^= 0x1000;
2086 write_smi_reg(mp, 0, phy_reg_data0);
2090 static void mv643xx_init_ethtool_cmd(struct net_device *dev, int phy_address,
2091 int speed, int duplex,
2092 struct ethtool_cmd *cmd)
2094 struct mv643xx_eth_private *mp = netdev_priv(dev);
2096 memset(cmd, 0, sizeof(*cmd));
2098 cmd->port = PORT_MII;
2099 cmd->transceiver = XCVR_INTERNAL;
2100 cmd->phy_address = phy_address;
2103 cmd->autoneg = AUTONEG_ENABLE;
2104 /* mii lib checks, but doesn't use speed on AUTONEG_ENABLE */
2105 cmd->speed = SPEED_100;
2106 cmd->advertising = ADVERTISED_10baseT_Half |
2107 ADVERTISED_10baseT_Full |
2108 ADVERTISED_100baseT_Half |
2109 ADVERTISED_100baseT_Full;
2110 if (mp->mii.supports_gmii)
2111 cmd->advertising |= ADVERTISED_1000baseT_Full;
2113 cmd->autoneg = AUTONEG_DISABLE;
2115 cmd->duplex = duplex;
2119 static int mv643xx_eth_probe(struct platform_device *pdev)
2121 struct mv643xx_eth_platform_data *pd;
2123 struct mv643xx_eth_private *mp;
2124 struct net_device *dev;
2126 struct resource *res;
2128 struct ethtool_cmd cmd;
2129 int duplex = DUPLEX_HALF;
2130 int speed = 0; /* default to auto-negotiation */
2131 DECLARE_MAC_BUF(mac);
2133 pd = pdev->dev.platform_data;
2135 printk(KERN_ERR "No mv643xx_eth_platform_data\n");
2139 if (pd->shared == NULL) {
2140 printk(KERN_ERR "No mv643xx_eth_platform_data->shared\n");
2144 dev = alloc_etherdev(sizeof(struct mv643xx_eth_private));
2148 platform_set_drvdata(pdev, dev);
2150 mp = netdev_priv(dev);
2152 #ifdef MV643XX_ETH_NAPI
2153 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 64);
2156 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2158 dev->irq = res->start;
2160 dev->open = mv643xx_eth_open;
2161 dev->stop = mv643xx_eth_stop;
2162 dev->hard_start_xmit = mv643xx_eth_start_xmit;
2163 dev->set_mac_address = mv643xx_eth_set_mac_address;
2164 dev->set_multicast_list = mv643xx_eth_set_rx_mode;
2166 /* No need to Tx Timeout */
2167 dev->tx_timeout = mv643xx_eth_tx_timeout;
2169 #ifdef CONFIG_NET_POLL_CONTROLLER
2170 dev->poll_controller = mv643xx_eth_netpoll;
2173 dev->watchdog_timeo = 2 * HZ;
2175 dev->change_mtu = mv643xx_eth_change_mtu;
2176 dev->do_ioctl = mv643xx_eth_do_ioctl;
2177 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2179 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2180 #ifdef MAX_SKB_FRAGS
2182 * Zero copy can only work if we use Discovery II memory. Else, we will
2183 * have to map the buffers to ISA memory which is only 16 MB
2185 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2189 /* Configure the timeout task */
2190 INIT_WORK(&mp->tx_timeout_task, mv643xx_eth_tx_timeout_task);
2192 spin_lock_init(&mp->lock);
2194 mp->shared = platform_get_drvdata(pd->shared);
2195 port_num = mp->port_num = pd->port_number;
2197 if (mp->shared->win_protect)
2198 wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
2200 mp->shared_smi = mp->shared;
2201 if (pd->shared_smi != NULL)
2202 mp->shared_smi = platform_get_drvdata(pd->shared_smi);
2204 /* set default config values */
2205 uc_addr_get(mp, dev->dev_addr);
2206 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2207 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2209 if (is_valid_ether_addr(pd->mac_addr))
2210 memcpy(dev->dev_addr, pd->mac_addr, 6);
2212 if (pd->phy_addr || pd->force_phy_addr)
2213 phy_addr_set(mp, pd->phy_addr);
2215 if (pd->rx_queue_size)
2216 mp->rx_ring_size = pd->rx_queue_size;
2218 if (pd->tx_queue_size)
2219 mp->tx_ring_size = pd->tx_queue_size;
2221 if (pd->tx_sram_size) {
2222 mp->tx_sram_size = pd->tx_sram_size;
2223 mp->tx_sram_addr = pd->tx_sram_addr;
2226 if (pd->rx_sram_size) {
2227 mp->rx_sram_size = pd->rx_sram_size;
2228 mp->rx_sram_addr = pd->rx_sram_addr;
2231 duplex = pd->duplex;
2234 /* Hook up MII support for ethtool */
2236 mp->mii.mdio_read = mv643xx_eth_mdio_read;
2237 mp->mii.mdio_write = mv643xx_eth_mdio_write;
2238 mp->mii.phy_id = phy_addr_get(mp);
2239 mp->mii.phy_id_mask = 0x3f;
2240 mp->mii.reg_num_mask = 0x1f;
2242 err = phy_detect(mp);
2244 pr_debug("%s: No PHY detected at addr %d\n",
2245 dev->name, phy_addr_get(mp));
2250 mp->mii.supports_gmii = mii_check_gmii_support(&mp->mii);
2251 mv643xx_init_ethtool_cmd(dev, mp->mii.phy_id, speed, duplex, &cmd);
2252 mv643xx_eth_update_pscr(dev, &cmd);
2253 mv643xx_eth_set_settings(dev, &cmd);
2255 SET_NETDEV_DEV(dev, &pdev->dev);
2256 err = register_netdev(dev);
2262 "%s: port %d with MAC address %s\n",
2263 dev->name, port_num, print_mac(mac, p));
2265 if (dev->features & NETIF_F_SG)
2266 printk(KERN_NOTICE "%s: Scatter Gather Enabled\n", dev->name);
2268 if (dev->features & NETIF_F_IP_CSUM)
2269 printk(KERN_NOTICE "%s: TX TCP/IP Checksumming Supported\n",
2272 #ifdef MV643XX_ETH_CHECKSUM_OFFLOAD_TX
2273 printk(KERN_NOTICE "%s: RX TCP/UDP Checksum Offload ON \n", dev->name);
2276 #ifdef MV643XX_ETH_COAL
2277 printk(KERN_NOTICE "%s: TX and RX Interrupt Coalescing ON \n",
2281 #ifdef MV643XX_ETH_NAPI
2282 printk(KERN_NOTICE "%s: RX NAPI Enabled \n", dev->name);
2285 if (mp->tx_sram_size > 0)
2286 printk(KERN_NOTICE "%s: Using SRAM\n", dev->name);
2296 static int mv643xx_eth_remove(struct platform_device *pdev)
2298 struct net_device *dev = platform_get_drvdata(pdev);
2300 unregister_netdev(dev);
2301 flush_scheduled_work();
2304 platform_set_drvdata(pdev, NULL);
2308 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2310 struct net_device *dev = platform_get_drvdata(pdev);
2311 struct mv643xx_eth_private *mp = netdev_priv(dev);
2312 unsigned int port_num = mp->port_num;
2314 /* Mask all interrupts on ethernet port */
2315 wrl(mp, INT_MASK(port_num), 0);
2316 rdl(mp, INT_MASK(port_num));
2321 static struct platform_driver mv643xx_eth_driver = {
2322 .probe = mv643xx_eth_probe,
2323 .remove = mv643xx_eth_remove,
2324 .shutdown = mv643xx_eth_shutdown,
2326 .name = MV643XX_ETH_NAME,
2327 .owner = THIS_MODULE,
2331 static int __init mv643xx_eth_init_module(void)
2335 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2337 rc = platform_driver_register(&mv643xx_eth_driver);
2339 platform_driver_unregister(&mv643xx_eth_shared_driver);
2344 static void __exit mv643xx_eth_cleanup_module(void)
2346 platform_driver_unregister(&mv643xx_eth_driver);
2347 platform_driver_unregister(&mv643xx_eth_shared_driver);
2350 module_init(mv643xx_eth_init_module);
2351 module_exit(mv643xx_eth_cleanup_module);
2353 MODULE_LICENSE("GPL");
2354 MODULE_AUTHOR( "Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, Manish Lachwani"
2355 " and Dale Farnsworth");
2356 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2357 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);
2358 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);