2 * Driver for Marvell Discovery (MV643XX) and Marvell Orion ethernet ports
3 * Copyright (C) 2002 Matthew Dharm <mdharm@momenco.com>
5 * Based on the 64360 driver from:
6 * Copyright (C) 2002 Rabeeh Khoury <rabeeh@galileo.co.il>
7 * Rabeeh Khoury <rabeeh@marvell.com>
9 * Copyright (C) 2003 PMC-Sierra, Inc.,
10 * written by Manish Lachwani
12 * Copyright (C) 2003 Ralf Baechle <ralf@linux-mips.org>
14 * Copyright (C) 2004-2006 MontaVista Software, Inc.
15 * Dale Farnsworth <dale@farnsworth.org>
17 * Copyright (C) 2004 Steven J. Hill <sjhill1@rockwellcollins.com>
18 * <sjhill@realitydiluted.com>
20 * Copyright (C) 2007-2008 Marvell Semiconductor
21 * Lennert Buytenhek <buytenh@marvell.com>
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version 2
26 * of the License, or (at your option) any later version.
28 * This program is distributed in the hope that it will be useful,
29 * but WITHOUT ANY WARRANTY; without even the implied warranty of
30 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
31 * GNU General Public License for more details.
33 * You should have received a copy of the GNU General Public License
34 * along with this program; if not, write to the Free Software
35 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
38 #include <linux/init.h>
39 #include <linux/dma-mapping.h>
42 #include <linux/tcp.h>
43 #include <linux/udp.h>
44 #include <linux/etherdevice.h>
45 #include <linux/delay.h>
46 #include <linux/ethtool.h>
47 #include <linux/platform_device.h>
48 #include <linux/module.h>
49 #include <linux/kernel.h>
50 #include <linux/spinlock.h>
51 #include <linux/workqueue.h>
52 #include <linux/phy.h>
53 #include <linux/mv643xx_eth.h>
55 #include <linux/types.h>
56 #include <asm/system.h>
58 static char mv643xx_eth_driver_name[] = "mv643xx_eth";
59 static char mv643xx_eth_driver_version[] = "1.4";
63 * Registers shared between all ports.
65 #define PHY_ADDR 0x0000
66 #define SMI_REG 0x0004
67 #define SMI_BUSY 0x10000000
68 #define SMI_READ_VALID 0x08000000
69 #define SMI_OPCODE_READ 0x04000000
70 #define SMI_OPCODE_WRITE 0x00000000
71 #define ERR_INT_CAUSE 0x0080
72 #define ERR_INT_SMI_DONE 0x00000010
73 #define ERR_INT_MASK 0x0084
74 #define WINDOW_BASE(w) (0x0200 + ((w) << 3))
75 #define WINDOW_SIZE(w) (0x0204 + ((w) << 3))
76 #define WINDOW_REMAP_HIGH(w) (0x0280 + ((w) << 2))
77 #define WINDOW_BAR_ENABLE 0x0290
78 #define WINDOW_PROTECT(w) (0x0294 + ((w) << 4))
81 * Main per-port registers. These live at offset 0x0400 for
82 * port #0, 0x0800 for port #1, and 0x0c00 for port #2.
84 #define PORT_CONFIG 0x0000
85 #define UNICAST_PROMISCUOUS_MODE 0x00000001
86 #define PORT_CONFIG_EXT 0x0004
87 #define MAC_ADDR_LOW 0x0014
88 #define MAC_ADDR_HIGH 0x0018
89 #define SDMA_CONFIG 0x001c
90 #define PORT_SERIAL_CONTROL 0x003c
91 #define PORT_STATUS 0x0044
92 #define TX_FIFO_EMPTY 0x00000400
93 #define TX_IN_PROGRESS 0x00000080
94 #define PORT_SPEED_MASK 0x00000030
95 #define PORT_SPEED_1000 0x00000010
96 #define PORT_SPEED_100 0x00000020
97 #define PORT_SPEED_10 0x00000000
98 #define FLOW_CONTROL_ENABLED 0x00000008
99 #define FULL_DUPLEX 0x00000004
100 #define LINK_UP 0x00000002
101 #define TXQ_COMMAND 0x0048
102 #define TXQ_FIX_PRIO_CONF 0x004c
103 #define TX_BW_RATE 0x0050
104 #define TX_BW_MTU 0x0058
105 #define TX_BW_BURST 0x005c
106 #define INT_CAUSE 0x0060
107 #define INT_TX_END 0x07f80000
108 #define INT_RX 0x000003fc
109 #define INT_EXT 0x00000002
110 #define INT_CAUSE_EXT 0x0064
111 #define INT_EXT_LINK_PHY 0x00110000
112 #define INT_EXT_TX 0x000000ff
113 #define INT_MASK 0x0068
114 #define INT_MASK_EXT 0x006c
115 #define TX_FIFO_URGENT_THRESHOLD 0x0074
116 #define TXQ_FIX_PRIO_CONF_MOVED 0x00dc
117 #define TX_BW_RATE_MOVED 0x00e0
118 #define TX_BW_MTU_MOVED 0x00e8
119 #define TX_BW_BURST_MOVED 0x00ec
120 #define RXQ_CURRENT_DESC_PTR(q) (0x020c + ((q) << 4))
121 #define RXQ_COMMAND 0x0280
122 #define TXQ_CURRENT_DESC_PTR(q) (0x02c0 + ((q) << 2))
123 #define TXQ_BW_TOKENS(q) (0x0300 + ((q) << 4))
124 #define TXQ_BW_CONF(q) (0x0304 + ((q) << 4))
125 #define TXQ_BW_WRR_CONF(q) (0x0308 + ((q) << 4))
128 * Misc per-port registers.
130 #define MIB_COUNTERS(p) (0x1000 + ((p) << 7))
131 #define SPECIAL_MCAST_TABLE(p) (0x1400 + ((p) << 10))
132 #define OTHER_MCAST_TABLE(p) (0x1500 + ((p) << 10))
133 #define UNICAST_TABLE(p) (0x1600 + ((p) << 10))
137 * SDMA configuration register.
139 #define RX_BURST_SIZE_4_64BIT (2 << 1)
140 #define RX_BURST_SIZE_16_64BIT (4 << 1)
141 #define BLM_RX_NO_SWAP (1 << 4)
142 #define BLM_TX_NO_SWAP (1 << 5)
143 #define TX_BURST_SIZE_4_64BIT (2 << 22)
144 #define TX_BURST_SIZE_16_64BIT (4 << 22)
146 #if defined(__BIG_ENDIAN)
147 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
148 (RX_BURST_SIZE_4_64BIT | \
149 TX_BURST_SIZE_4_64BIT)
150 #elif defined(__LITTLE_ENDIAN)
151 #define PORT_SDMA_CONFIG_DEFAULT_VALUE \
152 (RX_BURST_SIZE_4_64BIT | \
155 TX_BURST_SIZE_4_64BIT)
157 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
162 * Port serial control register.
164 #define SET_MII_SPEED_TO_100 (1 << 24)
165 #define SET_GMII_SPEED_TO_1000 (1 << 23)
166 #define SET_FULL_DUPLEX_MODE (1 << 21)
167 #define MAX_RX_PACKET_9700BYTE (5 << 17)
168 #define DISABLE_AUTO_NEG_SPEED_GMII (1 << 13)
169 #define DO_NOT_FORCE_LINK_FAIL (1 << 10)
170 #define SERIAL_PORT_CONTROL_RESERVED (1 << 9)
171 #define DISABLE_AUTO_NEG_FOR_FLOW_CTRL (1 << 3)
172 #define DISABLE_AUTO_NEG_FOR_DUPLEX (1 << 2)
173 #define FORCE_LINK_PASS (1 << 1)
174 #define SERIAL_PORT_ENABLE (1 << 0)
176 #define DEFAULT_RX_QUEUE_SIZE 128
177 #define DEFAULT_TX_QUEUE_SIZE 256
183 #if defined(__BIG_ENDIAN)
185 u16 byte_cnt; /* Descriptor buffer byte count */
186 u16 buf_size; /* Buffer size */
187 u32 cmd_sts; /* Descriptor command status */
188 u32 next_desc_ptr; /* Next descriptor pointer */
189 u32 buf_ptr; /* Descriptor buffer pointer */
193 u16 byte_cnt; /* buffer byte count */
194 u16 l4i_chk; /* CPU provided TCP checksum */
195 u32 cmd_sts; /* Command/status field */
196 u32 next_desc_ptr; /* Pointer to next descriptor */
197 u32 buf_ptr; /* pointer to buffer for this descriptor*/
199 #elif defined(__LITTLE_ENDIAN)
201 u32 cmd_sts; /* Descriptor command status */
202 u16 buf_size; /* Buffer size */
203 u16 byte_cnt; /* Descriptor buffer byte count */
204 u32 buf_ptr; /* Descriptor buffer pointer */
205 u32 next_desc_ptr; /* Next descriptor pointer */
209 u32 cmd_sts; /* Command/status field */
210 u16 l4i_chk; /* CPU provided TCP checksum */
211 u16 byte_cnt; /* buffer byte count */
212 u32 buf_ptr; /* pointer to buffer for this descriptor*/
213 u32 next_desc_ptr; /* Pointer to next descriptor */
216 #error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
219 /* RX & TX descriptor command */
220 #define BUFFER_OWNED_BY_DMA 0x80000000
222 /* RX & TX descriptor status */
223 #define ERROR_SUMMARY 0x00000001
225 /* RX descriptor status */
226 #define LAYER_4_CHECKSUM_OK 0x40000000
227 #define RX_ENABLE_INTERRUPT 0x20000000
228 #define RX_FIRST_DESC 0x08000000
229 #define RX_LAST_DESC 0x04000000
231 /* TX descriptor command */
232 #define TX_ENABLE_INTERRUPT 0x00800000
233 #define GEN_CRC 0x00400000
234 #define TX_FIRST_DESC 0x00200000
235 #define TX_LAST_DESC 0x00100000
236 #define ZERO_PADDING 0x00080000
237 #define GEN_IP_V4_CHECKSUM 0x00040000
238 #define GEN_TCP_UDP_CHECKSUM 0x00020000
239 #define UDP_FRAME 0x00010000
240 #define MAC_HDR_EXTRA_4_BYTES 0x00008000
241 #define MAC_HDR_EXTRA_8_BYTES 0x00000200
243 #define TX_IHL_SHIFT 11
246 /* global *******************************************************************/
247 struct mv643xx_eth_shared_private {
249 * Ethernet controller base address.
254 * Points at the right SMI instance to use.
256 struct mv643xx_eth_shared_private *smi;
259 * Provides access to local SMI interface.
261 struct mii_bus *smi_bus;
264 * If we have access to the error interrupt pin (which is
265 * somewhat misnamed as it not only reflects internal errors
266 * but also reflects SMI completion), use that to wait for
267 * SMI access completion instead of polling the SMI busy bit.
270 wait_queue_head_t smi_busy_wait;
273 * Per-port MBUS window access register value.
278 * Hardware-specific parameters.
281 int extended_rx_coal_limit;
285 #define TX_BW_CONTROL_ABSENT 0
286 #define TX_BW_CONTROL_OLD_LAYOUT 1
287 #define TX_BW_CONTROL_NEW_LAYOUT 2
289 static int mv643xx_eth_open(struct net_device *dev);
290 static int mv643xx_eth_stop(struct net_device *dev);
293 /* per-port *****************************************************************/
294 struct mib_counters {
295 u64 good_octets_received;
296 u32 bad_octets_received;
297 u32 internal_mac_transmit_err;
298 u32 good_frames_received;
299 u32 bad_frames_received;
300 u32 broadcast_frames_received;
301 u32 multicast_frames_received;
302 u32 frames_64_octets;
303 u32 frames_65_to_127_octets;
304 u32 frames_128_to_255_octets;
305 u32 frames_256_to_511_octets;
306 u32 frames_512_to_1023_octets;
307 u32 frames_1024_to_max_octets;
308 u64 good_octets_sent;
309 u32 good_frames_sent;
310 u32 excessive_collision;
311 u32 multicast_frames_sent;
312 u32 broadcast_frames_sent;
313 u32 unrec_mac_control_received;
315 u32 good_fc_received;
317 u32 undersize_received;
318 u32 fragments_received;
319 u32 oversize_received;
321 u32 mac_receive_error;
336 struct rx_desc *rx_desc_area;
337 dma_addr_t rx_desc_dma;
338 int rx_desc_area_size;
339 struct sk_buff **rx_skb;
351 struct tx_desc *tx_desc_area;
352 dma_addr_t tx_desc_dma;
353 int tx_desc_area_size;
355 struct sk_buff_head tx_skb;
357 unsigned long tx_packets;
358 unsigned long tx_bytes;
359 unsigned long tx_dropped;
362 struct mv643xx_eth_private {
363 struct mv643xx_eth_shared_private *shared;
367 struct net_device *dev;
369 struct phy_device *phy;
371 struct timer_list mib_counters_timer;
372 spinlock_t mib_counters_lock;
373 struct mib_counters mib_counters;
375 struct work_struct tx_timeout_task;
377 struct napi_struct napi;
386 struct sk_buff_head rx_recycle;
392 unsigned long rx_desc_sram_addr;
393 int rx_desc_sram_size;
395 struct timer_list rx_oom;
396 struct rx_queue rxq[8];
402 unsigned long tx_desc_sram_addr;
403 int tx_desc_sram_size;
405 struct tx_queue txq[8];
409 /* port register accessors **************************************************/
410 static inline u32 rdl(struct mv643xx_eth_private *mp, int offset)
412 return readl(mp->shared->base + offset);
415 static inline u32 rdlp(struct mv643xx_eth_private *mp, int offset)
417 return readl(mp->base + offset);
420 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data)
422 writel(data, mp->shared->base + offset);
425 static inline void wrlp(struct mv643xx_eth_private *mp, int offset, u32 data)
427 writel(data, mp->base + offset);
431 /* rxq/txq helper functions *************************************************/
432 static struct mv643xx_eth_private *rxq_to_mp(struct rx_queue *rxq)
434 return container_of(rxq, struct mv643xx_eth_private, rxq[rxq->index]);
437 static struct mv643xx_eth_private *txq_to_mp(struct tx_queue *txq)
439 return container_of(txq, struct mv643xx_eth_private, txq[txq->index]);
442 static void rxq_enable(struct rx_queue *rxq)
444 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
445 wrlp(mp, RXQ_COMMAND, 1 << rxq->index);
448 static void rxq_disable(struct rx_queue *rxq)
450 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
451 u8 mask = 1 << rxq->index;
453 wrlp(mp, RXQ_COMMAND, mask << 8);
454 while (rdlp(mp, RXQ_COMMAND) & mask)
458 static void txq_reset_hw_ptr(struct tx_queue *txq)
460 struct mv643xx_eth_private *mp = txq_to_mp(txq);
463 addr = (u32)txq->tx_desc_dma;
464 addr += txq->tx_curr_desc * sizeof(struct tx_desc);
465 wrlp(mp, TXQ_CURRENT_DESC_PTR(txq->index), addr);
468 static void txq_enable(struct tx_queue *txq)
470 struct mv643xx_eth_private *mp = txq_to_mp(txq);
471 wrlp(mp, TXQ_COMMAND, 1 << txq->index);
474 static void txq_disable(struct tx_queue *txq)
476 struct mv643xx_eth_private *mp = txq_to_mp(txq);
477 u8 mask = 1 << txq->index;
479 wrlp(mp, TXQ_COMMAND, mask << 8);
480 while (rdlp(mp, TXQ_COMMAND) & mask)
484 static void txq_maybe_wake(struct tx_queue *txq)
486 struct mv643xx_eth_private *mp = txq_to_mp(txq);
487 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
489 if (netif_tx_queue_stopped(nq)) {
490 __netif_tx_lock(nq, smp_processor_id());
491 if (txq->tx_ring_size - txq->tx_desc_count >= MAX_SKB_FRAGS + 1)
492 netif_tx_wake_queue(nq);
493 __netif_tx_unlock(nq);
498 /* rx napi ******************************************************************/
499 static int rxq_process(struct rx_queue *rxq, int budget)
501 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
502 struct net_device_stats *stats = &mp->dev->stats;
506 while (rx < budget && rxq->rx_desc_count) {
507 struct rx_desc *rx_desc;
508 unsigned int cmd_sts;
512 rx_desc = &rxq->rx_desc_area[rxq->rx_curr_desc];
514 cmd_sts = rx_desc->cmd_sts;
515 if (cmd_sts & BUFFER_OWNED_BY_DMA)
519 skb = rxq->rx_skb[rxq->rx_curr_desc];
520 rxq->rx_skb[rxq->rx_curr_desc] = NULL;
523 if (rxq->rx_curr_desc == rxq->rx_ring_size)
524 rxq->rx_curr_desc = 0;
526 dma_unmap_single(NULL, rx_desc->buf_ptr,
527 rx_desc->buf_size, DMA_FROM_DEVICE);
528 rxq->rx_desc_count--;
531 mp->work_rx_refill |= 1 << rxq->index;
533 byte_cnt = rx_desc->byte_cnt;
538 * Note that the descriptor byte count includes 2 dummy
539 * bytes automatically inserted by the hardware at the
540 * start of the packet (which we don't count), and a 4
541 * byte CRC at the end of the packet (which we do count).
544 stats->rx_bytes += byte_cnt - 2;
547 * In case we received a packet without first / last bits
548 * on, or the error summary bit is set, the packet needs
551 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC | ERROR_SUMMARY))
552 != (RX_FIRST_DESC | RX_LAST_DESC))
556 * The -4 is for the CRC in the trailer of the
559 skb_put(skb, byte_cnt - 2 - 4);
561 if (cmd_sts & LAYER_4_CHECKSUM_OK)
562 skb->ip_summed = CHECKSUM_UNNECESSARY;
563 skb->protocol = eth_type_trans(skb, mp->dev);
564 netif_receive_skb(skb);
571 if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
572 (RX_FIRST_DESC | RX_LAST_DESC)) {
574 dev_printk(KERN_ERR, &mp->dev->dev,
575 "received packet spanning "
576 "multiple descriptors\n");
579 if (cmd_sts & ERROR_SUMMARY)
586 mp->work_rx &= ~(1 << rxq->index);
591 static int rxq_refill(struct rx_queue *rxq, int budget)
593 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
597 while (refilled < budget && rxq->rx_desc_count < rxq->rx_ring_size) {
601 struct rx_desc *rx_desc;
603 skb = __skb_dequeue(&mp->rx_recycle);
605 skb = dev_alloc_skb(mp->skb_size +
606 dma_get_cache_alignment() - 1);
609 mp->work_rx_oom |= 1 << rxq->index;
613 unaligned = (u32)skb->data & (dma_get_cache_alignment() - 1);
615 skb_reserve(skb, dma_get_cache_alignment() - unaligned);
618 rxq->rx_desc_count++;
620 rx = rxq->rx_used_desc++;
621 if (rxq->rx_used_desc == rxq->rx_ring_size)
622 rxq->rx_used_desc = 0;
624 rx_desc = rxq->rx_desc_area + rx;
626 rx_desc->buf_ptr = dma_map_single(NULL, skb->data,
627 mp->skb_size, DMA_FROM_DEVICE);
628 rx_desc->buf_size = mp->skb_size;
629 rxq->rx_skb[rx] = skb;
631 rx_desc->cmd_sts = BUFFER_OWNED_BY_DMA | RX_ENABLE_INTERRUPT;
635 * The hardware automatically prepends 2 bytes of
636 * dummy data to each received packet, so that the
637 * IP header ends up 16-byte aligned.
642 if (refilled < budget)
643 mp->work_rx_refill &= ~(1 << rxq->index);
650 /* tx ***********************************************************************/
651 static inline unsigned int has_tiny_unaligned_frags(struct sk_buff *skb)
655 for (frag = 0; frag < skb_shinfo(skb)->nr_frags; frag++) {
656 skb_frag_t *fragp = &skb_shinfo(skb)->frags[frag];
657 if (fragp->size <= 8 && fragp->page_offset & 7)
664 static void txq_submit_frag_skb(struct tx_queue *txq, struct sk_buff *skb)
666 int nr_frags = skb_shinfo(skb)->nr_frags;
669 for (frag = 0; frag < nr_frags; frag++) {
670 skb_frag_t *this_frag;
672 struct tx_desc *desc;
674 this_frag = &skb_shinfo(skb)->frags[frag];
675 tx_index = txq->tx_curr_desc++;
676 if (txq->tx_curr_desc == txq->tx_ring_size)
677 txq->tx_curr_desc = 0;
678 desc = &txq->tx_desc_area[tx_index];
681 * The last fragment will generate an interrupt
682 * which will free the skb on TX completion.
684 if (frag == nr_frags - 1) {
685 desc->cmd_sts = BUFFER_OWNED_BY_DMA |
686 ZERO_PADDING | TX_LAST_DESC |
689 desc->cmd_sts = BUFFER_OWNED_BY_DMA;
693 desc->byte_cnt = this_frag->size;
694 desc->buf_ptr = dma_map_page(NULL, this_frag->page,
695 this_frag->page_offset,
701 static inline __be16 sum16_as_be(__sum16 sum)
703 return (__force __be16)sum;
706 static int txq_submit_skb(struct tx_queue *txq, struct sk_buff *skb)
708 struct mv643xx_eth_private *mp = txq_to_mp(txq);
709 int nr_frags = skb_shinfo(skb)->nr_frags;
711 struct tx_desc *desc;
716 cmd_sts = TX_FIRST_DESC | GEN_CRC | BUFFER_OWNED_BY_DMA;
719 if (skb->ip_summed == CHECKSUM_PARTIAL) {
722 BUG_ON(skb->protocol != htons(ETH_P_IP) &&
723 skb->protocol != htons(ETH_P_8021Q));
725 tag_bytes = (void *)ip_hdr(skb) - (void *)skb->data - ETH_HLEN;
726 if (unlikely(tag_bytes & ~12)) {
727 if (skb_checksum_help(skb) == 0)
734 cmd_sts |= MAC_HDR_EXTRA_4_BYTES;
736 cmd_sts |= MAC_HDR_EXTRA_8_BYTES;
738 cmd_sts |= GEN_TCP_UDP_CHECKSUM |
740 ip_hdr(skb)->ihl << TX_IHL_SHIFT;
742 switch (ip_hdr(skb)->protocol) {
744 cmd_sts |= UDP_FRAME;
745 l4i_chk = ntohs(sum16_as_be(udp_hdr(skb)->check));
748 l4i_chk = ntohs(sum16_as_be(tcp_hdr(skb)->check));
755 /* Errata BTS #50, IHL must be 5 if no HW checksum */
756 cmd_sts |= 5 << TX_IHL_SHIFT;
759 tx_index = txq->tx_curr_desc++;
760 if (txq->tx_curr_desc == txq->tx_ring_size)
761 txq->tx_curr_desc = 0;
762 desc = &txq->tx_desc_area[tx_index];
765 txq_submit_frag_skb(txq, skb);
766 length = skb_headlen(skb);
768 cmd_sts |= ZERO_PADDING | TX_LAST_DESC | TX_ENABLE_INTERRUPT;
772 desc->l4i_chk = l4i_chk;
773 desc->byte_cnt = length;
774 desc->buf_ptr = dma_map_single(NULL, skb->data, length, DMA_TO_DEVICE);
776 __skb_queue_tail(&txq->tx_skb, skb);
778 /* ensure all other descriptors are written before first cmd_sts */
780 desc->cmd_sts = cmd_sts;
782 /* clear TX_END status */
783 mp->work_tx_end &= ~(1 << txq->index);
785 /* ensure all descriptors are written before poking hardware */
789 txq->tx_desc_count += nr_frags + 1;
794 static int mv643xx_eth_xmit(struct sk_buff *skb, struct net_device *dev)
796 struct mv643xx_eth_private *mp = netdev_priv(dev);
798 struct tx_queue *txq;
799 struct netdev_queue *nq;
801 queue = skb_get_queue_mapping(skb);
802 txq = mp->txq + queue;
803 nq = netdev_get_tx_queue(dev, queue);
805 if (has_tiny_unaligned_frags(skb) && __skb_linearize(skb)) {
807 dev_printk(KERN_DEBUG, &dev->dev,
808 "failed to linearize skb with tiny "
809 "unaligned fragment\n");
810 return NETDEV_TX_BUSY;
813 if (txq->tx_ring_size - txq->tx_desc_count < MAX_SKB_FRAGS + 1) {
815 dev_printk(KERN_ERR, &dev->dev, "tx queue full?!\n");
820 if (!txq_submit_skb(txq, skb)) {
823 txq->tx_bytes += skb->len;
825 dev->trans_start = jiffies;
827 entries_left = txq->tx_ring_size - txq->tx_desc_count;
828 if (entries_left < MAX_SKB_FRAGS + 1)
829 netif_tx_stop_queue(nq);
836 /* tx napi ******************************************************************/
837 static void txq_kick(struct tx_queue *txq)
839 struct mv643xx_eth_private *mp = txq_to_mp(txq);
840 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
844 __netif_tx_lock(nq, smp_processor_id());
846 if (rdlp(mp, TXQ_COMMAND) & (1 << txq->index))
849 hw_desc_ptr = rdlp(mp, TXQ_CURRENT_DESC_PTR(txq->index));
850 expected_ptr = (u32)txq->tx_desc_dma +
851 txq->tx_curr_desc * sizeof(struct tx_desc);
853 if (hw_desc_ptr != expected_ptr)
857 __netif_tx_unlock(nq);
859 mp->work_tx_end &= ~(1 << txq->index);
862 static int txq_reclaim(struct tx_queue *txq, int budget, int force)
864 struct mv643xx_eth_private *mp = txq_to_mp(txq);
865 struct netdev_queue *nq = netdev_get_tx_queue(mp->dev, txq->index);
868 __netif_tx_lock(nq, smp_processor_id());
871 while (reclaimed < budget && txq->tx_desc_count > 0) {
873 struct tx_desc *desc;
877 tx_index = txq->tx_used_desc;
878 desc = &txq->tx_desc_area[tx_index];
879 cmd_sts = desc->cmd_sts;
881 if (cmd_sts & BUFFER_OWNED_BY_DMA) {
884 desc->cmd_sts = cmd_sts & ~BUFFER_OWNED_BY_DMA;
887 txq->tx_used_desc = tx_index + 1;
888 if (txq->tx_used_desc == txq->tx_ring_size)
889 txq->tx_used_desc = 0;
892 txq->tx_desc_count--;
895 if (cmd_sts & TX_LAST_DESC)
896 skb = __skb_dequeue(&txq->tx_skb);
898 if (cmd_sts & ERROR_SUMMARY) {
899 dev_printk(KERN_INFO, &mp->dev->dev, "tx error\n");
900 mp->dev->stats.tx_errors++;
903 if (cmd_sts & TX_FIRST_DESC) {
904 dma_unmap_single(NULL, desc->buf_ptr,
905 desc->byte_cnt, DMA_TO_DEVICE);
907 dma_unmap_page(NULL, desc->buf_ptr,
908 desc->byte_cnt, DMA_TO_DEVICE);
912 if (skb_queue_len(&mp->rx_recycle) <
914 skb_recycle_check(skb, mp->skb_size +
915 dma_get_cache_alignment() - 1))
916 __skb_queue_head(&mp->rx_recycle, skb);
922 __netif_tx_unlock(nq);
924 if (reclaimed < budget)
925 mp->work_tx &= ~(1 << txq->index);
931 /* tx rate control **********************************************************/
933 * Set total maximum TX rate (shared by all TX queues for this port)
934 * to 'rate' bits per second, with a maximum burst of 'burst' bytes.
936 static void tx_set_rate(struct mv643xx_eth_private *mp, int rate, int burst)
942 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
943 if (token_rate > 1023)
946 mtu = (mp->dev->mtu + 255) >> 8;
950 bucket_size = (burst + 255) >> 8;
951 if (bucket_size > 65535)
954 switch (mp->shared->tx_bw_control) {
955 case TX_BW_CONTROL_OLD_LAYOUT:
956 wrlp(mp, TX_BW_RATE, token_rate);
957 wrlp(mp, TX_BW_MTU, mtu);
958 wrlp(mp, TX_BW_BURST, bucket_size);
960 case TX_BW_CONTROL_NEW_LAYOUT:
961 wrlp(mp, TX_BW_RATE_MOVED, token_rate);
962 wrlp(mp, TX_BW_MTU_MOVED, mtu);
963 wrlp(mp, TX_BW_BURST_MOVED, bucket_size);
968 static void txq_set_rate(struct tx_queue *txq, int rate, int burst)
970 struct mv643xx_eth_private *mp = txq_to_mp(txq);
974 token_rate = ((rate / 1000) * 64) / (mp->shared->t_clk / 1000);
975 if (token_rate > 1023)
978 bucket_size = (burst + 255) >> 8;
979 if (bucket_size > 65535)
982 wrlp(mp, TXQ_BW_TOKENS(txq->index), token_rate << 14);
983 wrlp(mp, TXQ_BW_CONF(txq->index), (bucket_size << 10) | token_rate);
986 static void txq_set_fixed_prio_mode(struct tx_queue *txq)
988 struct mv643xx_eth_private *mp = txq_to_mp(txq);
993 * Turn on fixed priority mode.
996 switch (mp->shared->tx_bw_control) {
997 case TX_BW_CONTROL_OLD_LAYOUT:
998 off = TXQ_FIX_PRIO_CONF;
1000 case TX_BW_CONTROL_NEW_LAYOUT:
1001 off = TXQ_FIX_PRIO_CONF_MOVED;
1006 val = rdlp(mp, off);
1007 val |= 1 << txq->index;
1012 static void txq_set_wrr(struct tx_queue *txq, int weight)
1014 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1019 * Turn off fixed priority mode.
1022 switch (mp->shared->tx_bw_control) {
1023 case TX_BW_CONTROL_OLD_LAYOUT:
1024 off = TXQ_FIX_PRIO_CONF;
1026 case TX_BW_CONTROL_NEW_LAYOUT:
1027 off = TXQ_FIX_PRIO_CONF_MOVED;
1032 val = rdlp(mp, off);
1033 val &= ~(1 << txq->index);
1037 * Configure WRR weight for this queue.
1040 val = rdlp(mp, off);
1041 val = (val & ~0xff) | (weight & 0xff);
1042 wrlp(mp, TXQ_BW_WRR_CONF(txq->index), val);
1047 /* mii management interface *************************************************/
1048 static irqreturn_t mv643xx_eth_err_irq(int irq, void *dev_id)
1050 struct mv643xx_eth_shared_private *msp = dev_id;
1052 if (readl(msp->base + ERR_INT_CAUSE) & ERR_INT_SMI_DONE) {
1053 writel(~ERR_INT_SMI_DONE, msp->base + ERR_INT_CAUSE);
1054 wake_up(&msp->smi_busy_wait);
1061 static int smi_is_done(struct mv643xx_eth_shared_private *msp)
1063 return !(readl(msp->base + SMI_REG) & SMI_BUSY);
1066 static int smi_wait_ready(struct mv643xx_eth_shared_private *msp)
1068 if (msp->err_interrupt == NO_IRQ) {
1071 for (i = 0; !smi_is_done(msp); i++) {
1080 if (!smi_is_done(msp)) {
1081 wait_event_timeout(msp->smi_busy_wait, smi_is_done(msp),
1082 msecs_to_jiffies(100));
1083 if (!smi_is_done(msp))
1090 static int smi_bus_read(struct mii_bus *bus, int addr, int reg)
1092 struct mv643xx_eth_shared_private *msp = bus->priv;
1093 void __iomem *smi_reg = msp->base + SMI_REG;
1096 if (smi_wait_ready(msp)) {
1097 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1101 writel(SMI_OPCODE_READ | (reg << 21) | (addr << 16), smi_reg);
1103 if (smi_wait_ready(msp)) {
1104 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1108 ret = readl(smi_reg);
1109 if (!(ret & SMI_READ_VALID)) {
1110 printk(KERN_WARNING "mv643xx_eth: SMI bus read not valid\n");
1114 return ret & 0xffff;
1117 static int smi_bus_write(struct mii_bus *bus, int addr, int reg, u16 val)
1119 struct mv643xx_eth_shared_private *msp = bus->priv;
1120 void __iomem *smi_reg = msp->base + SMI_REG;
1122 if (smi_wait_ready(msp)) {
1123 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1127 writel(SMI_OPCODE_WRITE | (reg << 21) |
1128 (addr << 16) | (val & 0xffff), smi_reg);
1130 if (smi_wait_ready(msp)) {
1131 printk(KERN_WARNING "mv643xx_eth: SMI bus busy timeout\n");
1139 /* statistics ***************************************************************/
1140 static struct net_device_stats *mv643xx_eth_get_stats(struct net_device *dev)
1142 struct mv643xx_eth_private *mp = netdev_priv(dev);
1143 struct net_device_stats *stats = &dev->stats;
1144 unsigned long tx_packets = 0;
1145 unsigned long tx_bytes = 0;
1146 unsigned long tx_dropped = 0;
1149 for (i = 0; i < mp->txq_count; i++) {
1150 struct tx_queue *txq = mp->txq + i;
1152 tx_packets += txq->tx_packets;
1153 tx_bytes += txq->tx_bytes;
1154 tx_dropped += txq->tx_dropped;
1157 stats->tx_packets = tx_packets;
1158 stats->tx_bytes = tx_bytes;
1159 stats->tx_dropped = tx_dropped;
1164 static inline u32 mib_read(struct mv643xx_eth_private *mp, int offset)
1166 return rdl(mp, MIB_COUNTERS(mp->port_num) + offset);
1169 static void mib_counters_clear(struct mv643xx_eth_private *mp)
1173 for (i = 0; i < 0x80; i += 4)
1177 static void mib_counters_update(struct mv643xx_eth_private *mp)
1179 struct mib_counters *p = &mp->mib_counters;
1181 spin_lock(&mp->mib_counters_lock);
1182 p->good_octets_received += mib_read(mp, 0x00);
1183 p->good_octets_received += (u64)mib_read(mp, 0x04) << 32;
1184 p->bad_octets_received += mib_read(mp, 0x08);
1185 p->internal_mac_transmit_err += mib_read(mp, 0x0c);
1186 p->good_frames_received += mib_read(mp, 0x10);
1187 p->bad_frames_received += mib_read(mp, 0x14);
1188 p->broadcast_frames_received += mib_read(mp, 0x18);
1189 p->multicast_frames_received += mib_read(mp, 0x1c);
1190 p->frames_64_octets += mib_read(mp, 0x20);
1191 p->frames_65_to_127_octets += mib_read(mp, 0x24);
1192 p->frames_128_to_255_octets += mib_read(mp, 0x28);
1193 p->frames_256_to_511_octets += mib_read(mp, 0x2c);
1194 p->frames_512_to_1023_octets += mib_read(mp, 0x30);
1195 p->frames_1024_to_max_octets += mib_read(mp, 0x34);
1196 p->good_octets_sent += mib_read(mp, 0x38);
1197 p->good_octets_sent += (u64)mib_read(mp, 0x3c) << 32;
1198 p->good_frames_sent += mib_read(mp, 0x40);
1199 p->excessive_collision += mib_read(mp, 0x44);
1200 p->multicast_frames_sent += mib_read(mp, 0x48);
1201 p->broadcast_frames_sent += mib_read(mp, 0x4c);
1202 p->unrec_mac_control_received += mib_read(mp, 0x50);
1203 p->fc_sent += mib_read(mp, 0x54);
1204 p->good_fc_received += mib_read(mp, 0x58);
1205 p->bad_fc_received += mib_read(mp, 0x5c);
1206 p->undersize_received += mib_read(mp, 0x60);
1207 p->fragments_received += mib_read(mp, 0x64);
1208 p->oversize_received += mib_read(mp, 0x68);
1209 p->jabber_received += mib_read(mp, 0x6c);
1210 p->mac_receive_error += mib_read(mp, 0x70);
1211 p->bad_crc_event += mib_read(mp, 0x74);
1212 p->collision += mib_read(mp, 0x78);
1213 p->late_collision += mib_read(mp, 0x7c);
1214 spin_unlock(&mp->mib_counters_lock);
1216 mod_timer(&mp->mib_counters_timer, jiffies + 30 * HZ);
1219 static void mib_counters_timer_wrapper(unsigned long _mp)
1221 struct mv643xx_eth_private *mp = (void *)_mp;
1223 mib_counters_update(mp);
1227 /* interrupt coalescing *****************************************************/
1229 * Hardware coalescing parameters are set in units of 64 t_clk
1232 * coal_delay_in_usec = 64000000 * register_value / t_clk_rate
1234 * register_value = coal_delay_in_usec * t_clk_rate / 64000000
1236 * In the ->set*() methods, we round the computed register value
1237 * to the nearest integer.
1239 static unsigned int get_rx_coal(struct mv643xx_eth_private *mp)
1241 u32 val = rdlp(mp, SDMA_CONFIG);
1244 if (mp->shared->extended_rx_coal_limit)
1245 temp = ((val & 0x02000000) >> 10) | ((val & 0x003fff80) >> 7);
1247 temp = (val & 0x003fff00) >> 8;
1250 do_div(temp, mp->shared->t_clk);
1252 return (unsigned int)temp;
1255 static void set_rx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1260 temp = (u64)usec * mp->shared->t_clk;
1262 do_div(temp, 64000000);
1264 val = rdlp(mp, SDMA_CONFIG);
1265 if (mp->shared->extended_rx_coal_limit) {
1269 val |= (temp & 0x8000) << 10;
1270 val |= (temp & 0x7fff) << 7;
1275 val |= (temp & 0x3fff) << 8;
1277 wrlp(mp, SDMA_CONFIG, val);
1280 static unsigned int get_tx_coal(struct mv643xx_eth_private *mp)
1284 temp = (rdlp(mp, TX_FIFO_URGENT_THRESHOLD) & 0x3fff0) >> 4;
1286 do_div(temp, mp->shared->t_clk);
1288 return (unsigned int)temp;
1291 static void set_tx_coal(struct mv643xx_eth_private *mp, unsigned int usec)
1295 temp = (u64)usec * mp->shared->t_clk;
1297 do_div(temp, 64000000);
1302 wrlp(mp, TX_FIFO_URGENT_THRESHOLD, temp << 4);
1306 /* ethtool ******************************************************************/
1307 struct mv643xx_eth_stats {
1308 char stat_string[ETH_GSTRING_LEN];
1315 { #m, FIELD_SIZEOF(struct net_device_stats, m), \
1316 offsetof(struct net_device, stats.m), -1 }
1318 #define MIBSTAT(m) \
1319 { #m, FIELD_SIZEOF(struct mib_counters, m), \
1320 -1, offsetof(struct mv643xx_eth_private, mib_counters.m) }
1322 static const struct mv643xx_eth_stats mv643xx_eth_stats[] = {
1331 MIBSTAT(good_octets_received),
1332 MIBSTAT(bad_octets_received),
1333 MIBSTAT(internal_mac_transmit_err),
1334 MIBSTAT(good_frames_received),
1335 MIBSTAT(bad_frames_received),
1336 MIBSTAT(broadcast_frames_received),
1337 MIBSTAT(multicast_frames_received),
1338 MIBSTAT(frames_64_octets),
1339 MIBSTAT(frames_65_to_127_octets),
1340 MIBSTAT(frames_128_to_255_octets),
1341 MIBSTAT(frames_256_to_511_octets),
1342 MIBSTAT(frames_512_to_1023_octets),
1343 MIBSTAT(frames_1024_to_max_octets),
1344 MIBSTAT(good_octets_sent),
1345 MIBSTAT(good_frames_sent),
1346 MIBSTAT(excessive_collision),
1347 MIBSTAT(multicast_frames_sent),
1348 MIBSTAT(broadcast_frames_sent),
1349 MIBSTAT(unrec_mac_control_received),
1351 MIBSTAT(good_fc_received),
1352 MIBSTAT(bad_fc_received),
1353 MIBSTAT(undersize_received),
1354 MIBSTAT(fragments_received),
1355 MIBSTAT(oversize_received),
1356 MIBSTAT(jabber_received),
1357 MIBSTAT(mac_receive_error),
1358 MIBSTAT(bad_crc_event),
1360 MIBSTAT(late_collision),
1364 mv643xx_eth_get_settings_phy(struct mv643xx_eth_private *mp,
1365 struct ethtool_cmd *cmd)
1369 err = phy_read_status(mp->phy);
1371 err = phy_ethtool_gset(mp->phy, cmd);
1374 * The MAC does not support 1000baseT_Half.
1376 cmd->supported &= ~SUPPORTED_1000baseT_Half;
1377 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1383 mv643xx_eth_get_settings_phyless(struct mv643xx_eth_private *mp,
1384 struct ethtool_cmd *cmd)
1388 port_status = rdlp(mp, PORT_STATUS);
1390 cmd->supported = SUPPORTED_MII;
1391 cmd->advertising = ADVERTISED_MII;
1392 switch (port_status & PORT_SPEED_MASK) {
1394 cmd->speed = SPEED_10;
1396 case PORT_SPEED_100:
1397 cmd->speed = SPEED_100;
1399 case PORT_SPEED_1000:
1400 cmd->speed = SPEED_1000;
1406 cmd->duplex = (port_status & FULL_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
1407 cmd->port = PORT_MII;
1408 cmd->phy_address = 0;
1409 cmd->transceiver = XCVR_INTERNAL;
1410 cmd->autoneg = AUTONEG_DISABLE;
1418 mv643xx_eth_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1420 struct mv643xx_eth_private *mp = netdev_priv(dev);
1422 if (mp->phy != NULL)
1423 return mv643xx_eth_get_settings_phy(mp, cmd);
1425 return mv643xx_eth_get_settings_phyless(mp, cmd);
1429 mv643xx_eth_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
1431 struct mv643xx_eth_private *mp = netdev_priv(dev);
1433 if (mp->phy == NULL)
1437 * The MAC does not support 1000baseT_Half.
1439 cmd->advertising &= ~ADVERTISED_1000baseT_Half;
1441 return phy_ethtool_sset(mp->phy, cmd);
1444 static void mv643xx_eth_get_drvinfo(struct net_device *dev,
1445 struct ethtool_drvinfo *drvinfo)
1447 strncpy(drvinfo->driver, mv643xx_eth_driver_name, 32);
1448 strncpy(drvinfo->version, mv643xx_eth_driver_version, 32);
1449 strncpy(drvinfo->fw_version, "N/A", 32);
1450 strncpy(drvinfo->bus_info, "platform", 32);
1451 drvinfo->n_stats = ARRAY_SIZE(mv643xx_eth_stats);
1454 static int mv643xx_eth_nway_reset(struct net_device *dev)
1456 struct mv643xx_eth_private *mp = netdev_priv(dev);
1458 if (mp->phy == NULL)
1461 return genphy_restart_aneg(mp->phy);
1464 static u32 mv643xx_eth_get_link(struct net_device *dev)
1466 return !!netif_carrier_ok(dev);
1470 mv643xx_eth_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1472 struct mv643xx_eth_private *mp = netdev_priv(dev);
1474 ec->rx_coalesce_usecs = get_rx_coal(mp);
1475 ec->tx_coalesce_usecs = get_tx_coal(mp);
1481 mv643xx_eth_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1483 struct mv643xx_eth_private *mp = netdev_priv(dev);
1485 set_rx_coal(mp, ec->rx_coalesce_usecs);
1486 set_tx_coal(mp, ec->tx_coalesce_usecs);
1492 mv643xx_eth_get_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1494 struct mv643xx_eth_private *mp = netdev_priv(dev);
1496 er->rx_max_pending = 4096;
1497 er->tx_max_pending = 4096;
1498 er->rx_mini_max_pending = 0;
1499 er->rx_jumbo_max_pending = 0;
1501 er->rx_pending = mp->rx_ring_size;
1502 er->tx_pending = mp->tx_ring_size;
1503 er->rx_mini_pending = 0;
1504 er->rx_jumbo_pending = 0;
1508 mv643xx_eth_set_ringparam(struct net_device *dev, struct ethtool_ringparam *er)
1510 struct mv643xx_eth_private *mp = netdev_priv(dev);
1512 if (er->rx_mini_pending || er->rx_jumbo_pending)
1515 mp->rx_ring_size = er->rx_pending < 4096 ? er->rx_pending : 4096;
1516 mp->tx_ring_size = er->tx_pending < 4096 ? er->tx_pending : 4096;
1518 if (netif_running(dev)) {
1519 mv643xx_eth_stop(dev);
1520 if (mv643xx_eth_open(dev)) {
1521 dev_printk(KERN_ERR, &dev->dev,
1522 "fatal error on re-opening device after "
1523 "ring param change\n");
1532 mv643xx_eth_get_rx_csum(struct net_device *dev)
1534 struct mv643xx_eth_private *mp = netdev_priv(dev);
1536 return !!(rdlp(mp, PORT_CONFIG) & 0x02000000);
1540 mv643xx_eth_set_rx_csum(struct net_device *dev, u32 rx_csum)
1542 struct mv643xx_eth_private *mp = netdev_priv(dev);
1544 wrlp(mp, PORT_CONFIG, rx_csum ? 0x02000000 : 0x00000000);
1549 static void mv643xx_eth_get_strings(struct net_device *dev,
1550 uint32_t stringset, uint8_t *data)
1554 if (stringset == ETH_SS_STATS) {
1555 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1556 memcpy(data + i * ETH_GSTRING_LEN,
1557 mv643xx_eth_stats[i].stat_string,
1563 static void mv643xx_eth_get_ethtool_stats(struct net_device *dev,
1564 struct ethtool_stats *stats,
1567 struct mv643xx_eth_private *mp = netdev_priv(dev);
1570 mv643xx_eth_get_stats(dev);
1571 mib_counters_update(mp);
1573 for (i = 0; i < ARRAY_SIZE(mv643xx_eth_stats); i++) {
1574 const struct mv643xx_eth_stats *stat;
1577 stat = mv643xx_eth_stats + i;
1579 if (stat->netdev_off >= 0)
1580 p = ((void *)mp->dev) + stat->netdev_off;
1582 p = ((void *)mp) + stat->mp_off;
1584 data[i] = (stat->sizeof_stat == 8) ?
1585 *(uint64_t *)p : *(uint32_t *)p;
1589 static int mv643xx_eth_get_sset_count(struct net_device *dev, int sset)
1591 if (sset == ETH_SS_STATS)
1592 return ARRAY_SIZE(mv643xx_eth_stats);
1597 static const struct ethtool_ops mv643xx_eth_ethtool_ops = {
1598 .get_settings = mv643xx_eth_get_settings,
1599 .set_settings = mv643xx_eth_set_settings,
1600 .get_drvinfo = mv643xx_eth_get_drvinfo,
1601 .nway_reset = mv643xx_eth_nway_reset,
1602 .get_link = mv643xx_eth_get_link,
1603 .get_coalesce = mv643xx_eth_get_coalesce,
1604 .set_coalesce = mv643xx_eth_set_coalesce,
1605 .get_ringparam = mv643xx_eth_get_ringparam,
1606 .set_ringparam = mv643xx_eth_set_ringparam,
1607 .get_rx_csum = mv643xx_eth_get_rx_csum,
1608 .set_rx_csum = mv643xx_eth_set_rx_csum,
1609 .set_sg = ethtool_op_set_sg,
1610 .get_strings = mv643xx_eth_get_strings,
1611 .get_ethtool_stats = mv643xx_eth_get_ethtool_stats,
1612 .get_sset_count = mv643xx_eth_get_sset_count,
1616 /* address handling *********************************************************/
1617 static void uc_addr_get(struct mv643xx_eth_private *mp, unsigned char *addr)
1619 unsigned int mac_h = rdlp(mp, MAC_ADDR_HIGH);
1620 unsigned int mac_l = rdlp(mp, MAC_ADDR_LOW);
1622 addr[0] = (mac_h >> 24) & 0xff;
1623 addr[1] = (mac_h >> 16) & 0xff;
1624 addr[2] = (mac_h >> 8) & 0xff;
1625 addr[3] = mac_h & 0xff;
1626 addr[4] = (mac_l >> 8) & 0xff;
1627 addr[5] = mac_l & 0xff;
1630 static void uc_addr_set(struct mv643xx_eth_private *mp, unsigned char *addr)
1632 wrlp(mp, MAC_ADDR_HIGH,
1633 (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3]);
1634 wrlp(mp, MAC_ADDR_LOW, (addr[4] << 8) | addr[5]);
1637 static u32 uc_addr_filter_mask(struct net_device *dev)
1639 struct dev_addr_list *uc_ptr;
1642 if (dev->flags & IFF_PROMISC)
1645 nibbles = 1 << (dev->dev_addr[5] & 0x0f);
1646 for (uc_ptr = dev->uc_list; uc_ptr != NULL; uc_ptr = uc_ptr->next) {
1647 if (memcmp(dev->dev_addr, uc_ptr->da_addr, 5))
1649 if ((dev->dev_addr[5] ^ uc_ptr->da_addr[5]) & 0xf0)
1652 nibbles |= 1 << (uc_ptr->da_addr[5] & 0x0f);
1658 static void mv643xx_eth_program_unicast_filter(struct net_device *dev)
1660 struct mv643xx_eth_private *mp = netdev_priv(dev);
1665 uc_addr_set(mp, dev->dev_addr);
1667 port_config = rdlp(mp, PORT_CONFIG);
1668 nibbles = uc_addr_filter_mask(dev);
1670 port_config |= UNICAST_PROMISCUOUS_MODE;
1671 wrlp(mp, PORT_CONFIG, port_config);
1675 for (i = 0; i < 16; i += 4) {
1676 int off = UNICAST_TABLE(mp->port_num) + i;
1693 port_config &= ~UNICAST_PROMISCUOUS_MODE;
1694 wrlp(mp, PORT_CONFIG, port_config);
1697 static int addr_crc(unsigned char *addr)
1702 for (i = 0; i < 6; i++) {
1705 crc = (crc ^ addr[i]) << 8;
1706 for (j = 7; j >= 0; j--) {
1707 if (crc & (0x100 << j))
1715 static void mv643xx_eth_program_multicast_filter(struct net_device *dev)
1717 struct mv643xx_eth_private *mp = netdev_priv(dev);
1720 struct dev_addr_list *addr;
1723 if (dev->flags & (IFF_PROMISC | IFF_ALLMULTI)) {
1729 port_num = mp->port_num;
1730 accept = 0x01010101;
1731 for (i = 0; i < 0x100; i += 4) {
1732 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept);
1733 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept);
1738 mc_spec = kmalloc(0x200, GFP_KERNEL);
1739 if (mc_spec == NULL)
1741 mc_other = mc_spec + (0x100 >> 2);
1743 memset(mc_spec, 0, 0x100);
1744 memset(mc_other, 0, 0x100);
1746 for (addr = dev->mc_list; addr != NULL; addr = addr->next) {
1747 u8 *a = addr->da_addr;
1751 if (memcmp(a, "\x01\x00\x5e\x00\x00", 5) == 0) {
1756 entry = addr_crc(a);
1759 table[entry >> 2] |= 1 << (8 * (entry & 3));
1762 for (i = 0; i < 0x100; i += 4) {
1763 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1764 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
1770 static void mv643xx_eth_set_rx_mode(struct net_device *dev)
1772 mv643xx_eth_program_unicast_filter(dev);
1773 mv643xx_eth_program_multicast_filter(dev);
1776 static int mv643xx_eth_set_mac_address(struct net_device *dev, void *addr)
1778 struct sockaddr *sa = addr;
1780 memcpy(dev->dev_addr, sa->sa_data, ETH_ALEN);
1782 netif_addr_lock_bh(dev);
1783 mv643xx_eth_program_unicast_filter(dev);
1784 netif_addr_unlock_bh(dev);
1790 /* rx/tx queue initialisation ***********************************************/
1791 static int rxq_init(struct mv643xx_eth_private *mp, int index)
1793 struct rx_queue *rxq = mp->rxq + index;
1794 struct rx_desc *rx_desc;
1800 rxq->rx_ring_size = mp->rx_ring_size;
1802 rxq->rx_desc_count = 0;
1803 rxq->rx_curr_desc = 0;
1804 rxq->rx_used_desc = 0;
1806 size = rxq->rx_ring_size * sizeof(struct rx_desc);
1808 if (index == 0 && size <= mp->rx_desc_sram_size) {
1809 rxq->rx_desc_area = ioremap(mp->rx_desc_sram_addr,
1810 mp->rx_desc_sram_size);
1811 rxq->rx_desc_dma = mp->rx_desc_sram_addr;
1813 rxq->rx_desc_area = dma_alloc_coherent(NULL, size,
1818 if (rxq->rx_desc_area == NULL) {
1819 dev_printk(KERN_ERR, &mp->dev->dev,
1820 "can't allocate rx ring (%d bytes)\n", size);
1823 memset(rxq->rx_desc_area, 0, size);
1825 rxq->rx_desc_area_size = size;
1826 rxq->rx_skb = kmalloc(rxq->rx_ring_size * sizeof(*rxq->rx_skb),
1828 if (rxq->rx_skb == NULL) {
1829 dev_printk(KERN_ERR, &mp->dev->dev,
1830 "can't allocate rx skb ring\n");
1834 rx_desc = (struct rx_desc *)rxq->rx_desc_area;
1835 for (i = 0; i < rxq->rx_ring_size; i++) {
1839 if (nexti == rxq->rx_ring_size)
1842 rx_desc[i].next_desc_ptr = rxq->rx_desc_dma +
1843 nexti * sizeof(struct rx_desc);
1850 if (index == 0 && size <= mp->rx_desc_sram_size)
1851 iounmap(rxq->rx_desc_area);
1853 dma_free_coherent(NULL, size,
1861 static void rxq_deinit(struct rx_queue *rxq)
1863 struct mv643xx_eth_private *mp = rxq_to_mp(rxq);
1868 for (i = 0; i < rxq->rx_ring_size; i++) {
1869 if (rxq->rx_skb[i]) {
1870 dev_kfree_skb(rxq->rx_skb[i]);
1871 rxq->rx_desc_count--;
1875 if (rxq->rx_desc_count) {
1876 dev_printk(KERN_ERR, &mp->dev->dev,
1877 "error freeing rx ring -- %d skbs stuck\n",
1878 rxq->rx_desc_count);
1881 if (rxq->index == 0 &&
1882 rxq->rx_desc_area_size <= mp->rx_desc_sram_size)
1883 iounmap(rxq->rx_desc_area);
1885 dma_free_coherent(NULL, rxq->rx_desc_area_size,
1886 rxq->rx_desc_area, rxq->rx_desc_dma);
1891 static int txq_init(struct mv643xx_eth_private *mp, int index)
1893 struct tx_queue *txq = mp->txq + index;
1894 struct tx_desc *tx_desc;
1900 txq->tx_ring_size = mp->tx_ring_size;
1902 txq->tx_desc_count = 0;
1903 txq->tx_curr_desc = 0;
1904 txq->tx_used_desc = 0;
1906 size = txq->tx_ring_size * sizeof(struct tx_desc);
1908 if (index == 0 && size <= mp->tx_desc_sram_size) {
1909 txq->tx_desc_area = ioremap(mp->tx_desc_sram_addr,
1910 mp->tx_desc_sram_size);
1911 txq->tx_desc_dma = mp->tx_desc_sram_addr;
1913 txq->tx_desc_area = dma_alloc_coherent(NULL, size,
1918 if (txq->tx_desc_area == NULL) {
1919 dev_printk(KERN_ERR, &mp->dev->dev,
1920 "can't allocate tx ring (%d bytes)\n", size);
1923 memset(txq->tx_desc_area, 0, size);
1925 txq->tx_desc_area_size = size;
1927 tx_desc = (struct tx_desc *)txq->tx_desc_area;
1928 for (i = 0; i < txq->tx_ring_size; i++) {
1929 struct tx_desc *txd = tx_desc + i;
1933 if (nexti == txq->tx_ring_size)
1937 txd->next_desc_ptr = txq->tx_desc_dma +
1938 nexti * sizeof(struct tx_desc);
1941 skb_queue_head_init(&txq->tx_skb);
1946 static void txq_deinit(struct tx_queue *txq)
1948 struct mv643xx_eth_private *mp = txq_to_mp(txq);
1951 txq_reclaim(txq, txq->tx_ring_size, 1);
1953 BUG_ON(txq->tx_used_desc != txq->tx_curr_desc);
1955 if (txq->index == 0 &&
1956 txq->tx_desc_area_size <= mp->tx_desc_sram_size)
1957 iounmap(txq->tx_desc_area);
1959 dma_free_coherent(NULL, txq->tx_desc_area_size,
1960 txq->tx_desc_area, txq->tx_desc_dma);
1964 /* netdev ops and related ***************************************************/
1965 static int mv643xx_eth_collect_events(struct mv643xx_eth_private *mp)
1970 int_cause = rdlp(mp, INT_CAUSE) & (INT_TX_END | INT_RX | INT_EXT);
1975 if (int_cause & INT_EXT)
1976 int_cause_ext = rdlp(mp, INT_CAUSE_EXT);
1978 int_cause &= INT_TX_END | INT_RX;
1980 wrlp(mp, INT_CAUSE, ~int_cause);
1981 mp->work_tx_end |= ((int_cause & INT_TX_END) >> 19) &
1982 ~(rdlp(mp, TXQ_COMMAND) & 0xff);
1983 mp->work_rx |= (int_cause & INT_RX) >> 2;
1986 int_cause_ext &= INT_EXT_LINK_PHY | INT_EXT_TX;
1987 if (int_cause_ext) {
1988 wrlp(mp, INT_CAUSE_EXT, ~int_cause_ext);
1989 if (int_cause_ext & INT_EXT_LINK_PHY)
1991 mp->work_tx |= int_cause_ext & INT_EXT_TX;
1997 static irqreturn_t mv643xx_eth_irq(int irq, void *dev_id)
1999 struct net_device *dev = (struct net_device *)dev_id;
2000 struct mv643xx_eth_private *mp = netdev_priv(dev);
2002 if (unlikely(!mv643xx_eth_collect_events(mp)))
2005 wrlp(mp, INT_MASK, 0);
2006 napi_schedule(&mp->napi);
2011 static void handle_link_event(struct mv643xx_eth_private *mp)
2013 struct net_device *dev = mp->dev;
2019 port_status = rdlp(mp, PORT_STATUS);
2020 if (!(port_status & LINK_UP)) {
2021 if (netif_carrier_ok(dev)) {
2024 printk(KERN_INFO "%s: link down\n", dev->name);
2026 netif_carrier_off(dev);
2028 for (i = 0; i < mp->txq_count; i++) {
2029 struct tx_queue *txq = mp->txq + i;
2031 txq_reclaim(txq, txq->tx_ring_size, 1);
2032 txq_reset_hw_ptr(txq);
2038 switch (port_status & PORT_SPEED_MASK) {
2042 case PORT_SPEED_100:
2045 case PORT_SPEED_1000:
2052 duplex = (port_status & FULL_DUPLEX) ? 1 : 0;
2053 fc = (port_status & FLOW_CONTROL_ENABLED) ? 1 : 0;
2055 printk(KERN_INFO "%s: link up, %d Mb/s, %s duplex, "
2056 "flow control %sabled\n", dev->name,
2057 speed, duplex ? "full" : "half",
2060 if (!netif_carrier_ok(dev))
2061 netif_carrier_on(dev);
2064 static int mv643xx_eth_poll(struct napi_struct *napi, int budget)
2066 struct mv643xx_eth_private *mp;
2069 mp = container_of(napi, struct mv643xx_eth_private, napi);
2071 mp->work_rx_refill |= mp->work_rx_oom;
2072 mp->work_rx_oom = 0;
2075 while (work_done < budget) {
2080 if (mp->work_link) {
2082 handle_link_event(mp);
2086 queue_mask = mp->work_tx | mp->work_tx_end |
2087 mp->work_rx | mp->work_rx_refill;
2089 if (mv643xx_eth_collect_events(mp))
2094 queue = fls(queue_mask) - 1;
2095 queue_mask = 1 << queue;
2097 work_tbd = budget - work_done;
2101 if (mp->work_tx_end & queue_mask) {
2102 txq_kick(mp->txq + queue);
2103 } else if (mp->work_tx & queue_mask) {
2104 work_done += txq_reclaim(mp->txq + queue, work_tbd, 0);
2105 txq_maybe_wake(mp->txq + queue);
2106 } else if (mp->work_rx & queue_mask) {
2107 work_done += rxq_process(mp->rxq + queue, work_tbd);
2108 } else if (mp->work_rx_refill & queue_mask) {
2109 work_done += rxq_refill(mp->rxq + queue, work_tbd);
2115 if (work_done < budget) {
2116 if (mp->work_rx_oom)
2117 mod_timer(&mp->rx_oom, jiffies + (HZ / 10));
2118 napi_complete(napi);
2119 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2125 static inline void oom_timer_wrapper(unsigned long data)
2127 struct mv643xx_eth_private *mp = (void *)data;
2129 napi_schedule(&mp->napi);
2132 static void phy_reset(struct mv643xx_eth_private *mp)
2136 data = phy_read(mp->phy, MII_BMCR);
2141 if (phy_write(mp->phy, MII_BMCR, data) < 0)
2145 data = phy_read(mp->phy, MII_BMCR);
2146 } while (data >= 0 && data & BMCR_RESET);
2149 static void port_start(struct mv643xx_eth_private *mp)
2155 * Perform PHY reset, if there is a PHY.
2157 if (mp->phy != NULL) {
2158 struct ethtool_cmd cmd;
2160 mv643xx_eth_get_settings(mp->dev, &cmd);
2162 mv643xx_eth_set_settings(mp->dev, &cmd);
2166 * Configure basic link parameters.
2168 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2170 pscr |= SERIAL_PORT_ENABLE;
2171 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2173 pscr |= DO_NOT_FORCE_LINK_FAIL;
2174 if (mp->phy == NULL)
2175 pscr |= FORCE_LINK_PASS;
2176 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2178 wrlp(mp, SDMA_CONFIG, PORT_SDMA_CONFIG_DEFAULT_VALUE);
2181 * Configure TX path and queues.
2183 tx_set_rate(mp, 1000000000, 16777216);
2184 for (i = 0; i < mp->txq_count; i++) {
2185 struct tx_queue *txq = mp->txq + i;
2187 txq_reset_hw_ptr(txq);
2188 txq_set_rate(txq, 1000000000, 16777216);
2189 txq_set_fixed_prio_mode(txq);
2193 * Add configured unicast address to address filter table.
2195 mv643xx_eth_program_unicast_filter(mp->dev);
2198 * Receive all unmatched unicast, TCP, UDP, BPDU and broadcast
2199 * frames to RX queue #0, and include the pseudo-header when
2200 * calculating receive checksums.
2202 wrlp(mp, PORT_CONFIG, 0x02000000);
2205 * Treat BPDUs as normal multicasts, and disable partition mode.
2207 wrlp(mp, PORT_CONFIG_EXT, 0x00000000);
2210 * Enable the receive queues.
2212 for (i = 0; i < mp->rxq_count; i++) {
2213 struct rx_queue *rxq = mp->rxq + i;
2216 addr = (u32)rxq->rx_desc_dma;
2217 addr += rxq->rx_curr_desc * sizeof(struct rx_desc);
2218 wrlp(mp, RXQ_CURRENT_DESC_PTR(i), addr);
2224 static void mv643xx_eth_recalc_skb_size(struct mv643xx_eth_private *mp)
2229 * Reserve 2+14 bytes for an ethernet header (the hardware
2230 * automatically prepends 2 bytes of dummy data to each
2231 * received packet), 16 bytes for up to four VLAN tags, and
2232 * 4 bytes for the trailing FCS -- 36 bytes total.
2234 skb_size = mp->dev->mtu + 36;
2237 * Make sure that the skb size is a multiple of 8 bytes, as
2238 * the lower three bits of the receive descriptor's buffer
2239 * size field are ignored by the hardware.
2241 mp->skb_size = (skb_size + 7) & ~7;
2244 static int mv643xx_eth_open(struct net_device *dev)
2246 struct mv643xx_eth_private *mp = netdev_priv(dev);
2250 wrlp(mp, INT_CAUSE, 0);
2251 wrlp(mp, INT_CAUSE_EXT, 0);
2252 rdlp(mp, INT_CAUSE_EXT);
2254 err = request_irq(dev->irq, mv643xx_eth_irq,
2255 IRQF_SHARED, dev->name, dev);
2257 dev_printk(KERN_ERR, &dev->dev, "can't assign irq\n");
2261 mv643xx_eth_recalc_skb_size(mp);
2263 napi_enable(&mp->napi);
2265 skb_queue_head_init(&mp->rx_recycle);
2267 for (i = 0; i < mp->rxq_count; i++) {
2268 err = rxq_init(mp, i);
2271 rxq_deinit(mp->rxq + i);
2275 rxq_refill(mp->rxq + i, INT_MAX);
2278 if (mp->work_rx_oom) {
2279 mp->rx_oom.expires = jiffies + (HZ / 10);
2280 add_timer(&mp->rx_oom);
2283 for (i = 0; i < mp->txq_count; i++) {
2284 err = txq_init(mp, i);
2287 txq_deinit(mp->txq + i);
2292 netif_carrier_off(dev);
2299 wrlp(mp, INT_MASK_EXT, INT_EXT_LINK_PHY | INT_EXT_TX);
2300 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2306 for (i = 0; i < mp->rxq_count; i++)
2307 rxq_deinit(mp->rxq + i);
2309 free_irq(dev->irq, dev);
2314 static void port_reset(struct mv643xx_eth_private *mp)
2319 for (i = 0; i < mp->rxq_count; i++)
2320 rxq_disable(mp->rxq + i);
2321 for (i = 0; i < mp->txq_count; i++)
2322 txq_disable(mp->txq + i);
2325 u32 ps = rdlp(mp, PORT_STATUS);
2327 if ((ps & (TX_IN_PROGRESS | TX_FIFO_EMPTY)) == TX_FIFO_EMPTY)
2332 /* Reset the Enable bit in the Configuration Register */
2333 data = rdlp(mp, PORT_SERIAL_CONTROL);
2334 data &= ~(SERIAL_PORT_ENABLE |
2335 DO_NOT_FORCE_LINK_FAIL |
2337 wrlp(mp, PORT_SERIAL_CONTROL, data);
2340 static int mv643xx_eth_stop(struct net_device *dev)
2342 struct mv643xx_eth_private *mp = netdev_priv(dev);
2345 wrlp(mp, INT_MASK_EXT, 0x00000000);
2346 wrlp(mp, INT_MASK, 0x00000000);
2349 del_timer_sync(&mp->mib_counters_timer);
2351 napi_disable(&mp->napi);
2353 del_timer_sync(&mp->rx_oom);
2355 netif_carrier_off(dev);
2357 free_irq(dev->irq, dev);
2360 mv643xx_eth_get_stats(dev);
2361 mib_counters_update(mp);
2363 skb_queue_purge(&mp->rx_recycle);
2365 for (i = 0; i < mp->rxq_count; i++)
2366 rxq_deinit(mp->rxq + i);
2367 for (i = 0; i < mp->txq_count; i++)
2368 txq_deinit(mp->txq + i);
2373 static int mv643xx_eth_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2375 struct mv643xx_eth_private *mp = netdev_priv(dev);
2377 if (mp->phy != NULL)
2378 return phy_mii_ioctl(mp->phy, if_mii(ifr), cmd);
2383 static int mv643xx_eth_change_mtu(struct net_device *dev, int new_mtu)
2385 struct mv643xx_eth_private *mp = netdev_priv(dev);
2387 if (new_mtu < 64 || new_mtu > 9500)
2391 mv643xx_eth_recalc_skb_size(mp);
2392 tx_set_rate(mp, 1000000000, 16777216);
2394 if (!netif_running(dev))
2398 * Stop and then re-open the interface. This will allocate RX
2399 * skbs of the new MTU.
2400 * There is a possible danger that the open will not succeed,
2401 * due to memory being full.
2403 mv643xx_eth_stop(dev);
2404 if (mv643xx_eth_open(dev)) {
2405 dev_printk(KERN_ERR, &dev->dev,
2406 "fatal error on re-opening device after "
2413 static void tx_timeout_task(struct work_struct *ugly)
2415 struct mv643xx_eth_private *mp;
2417 mp = container_of(ugly, struct mv643xx_eth_private, tx_timeout_task);
2418 if (netif_running(mp->dev)) {
2419 netif_tx_stop_all_queues(mp->dev);
2422 netif_tx_wake_all_queues(mp->dev);
2426 static void mv643xx_eth_tx_timeout(struct net_device *dev)
2428 struct mv643xx_eth_private *mp = netdev_priv(dev);
2430 dev_printk(KERN_INFO, &dev->dev, "tx timeout\n");
2432 schedule_work(&mp->tx_timeout_task);
2435 #ifdef CONFIG_NET_POLL_CONTROLLER
2436 static void mv643xx_eth_netpoll(struct net_device *dev)
2438 struct mv643xx_eth_private *mp = netdev_priv(dev);
2440 wrlp(mp, INT_MASK, 0x00000000);
2443 mv643xx_eth_irq(dev->irq, dev);
2445 wrlp(mp, INT_MASK, INT_TX_END | INT_RX | INT_EXT);
2450 /* platform glue ************************************************************/
2452 mv643xx_eth_conf_mbus_windows(struct mv643xx_eth_shared_private *msp,
2453 struct mbus_dram_target_info *dram)
2455 void __iomem *base = msp->base;
2460 for (i = 0; i < 6; i++) {
2461 writel(0, base + WINDOW_BASE(i));
2462 writel(0, base + WINDOW_SIZE(i));
2464 writel(0, base + WINDOW_REMAP_HIGH(i));
2470 for (i = 0; i < dram->num_cs; i++) {
2471 struct mbus_dram_window *cs = dram->cs + i;
2473 writel((cs->base & 0xffff0000) |
2474 (cs->mbus_attr << 8) |
2475 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
2476 writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
2478 win_enable &= ~(1 << i);
2479 win_protect |= 3 << (2 * i);
2482 writel(win_enable, base + WINDOW_BAR_ENABLE);
2483 msp->win_protect = win_protect;
2486 static void infer_hw_params(struct mv643xx_eth_shared_private *msp)
2489 * Check whether we have a 14-bit coal limit field in bits
2490 * [21:8], or a 16-bit coal limit in bits [25,21:7] of the
2491 * SDMA config register.
2493 writel(0x02000000, msp->base + 0x0400 + SDMA_CONFIG);
2494 if (readl(msp->base + 0x0400 + SDMA_CONFIG) & 0x02000000)
2495 msp->extended_rx_coal_limit = 1;
2497 msp->extended_rx_coal_limit = 0;
2500 * Check whether the MAC supports TX rate control, and if
2501 * yes, whether its associated registers are in the old or
2504 writel(1, msp->base + 0x0400 + TX_BW_MTU_MOVED);
2505 if (readl(msp->base + 0x0400 + TX_BW_MTU_MOVED) & 1) {
2506 msp->tx_bw_control = TX_BW_CONTROL_NEW_LAYOUT;
2508 writel(7, msp->base + 0x0400 + TX_BW_RATE);
2509 if (readl(msp->base + 0x0400 + TX_BW_RATE) & 7)
2510 msp->tx_bw_control = TX_BW_CONTROL_OLD_LAYOUT;
2512 msp->tx_bw_control = TX_BW_CONTROL_ABSENT;
2516 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
2518 static int mv643xx_eth_version_printed;
2519 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2520 struct mv643xx_eth_shared_private *msp;
2521 struct resource *res;
2524 if (!mv643xx_eth_version_printed++)
2525 printk(KERN_NOTICE "MV-643xx 10/100/1000 ethernet "
2526 "driver version %s\n", mv643xx_eth_driver_version);
2529 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2534 msp = kmalloc(sizeof(*msp), GFP_KERNEL);
2537 memset(msp, 0, sizeof(*msp));
2539 msp->base = ioremap(res->start, res->end - res->start + 1);
2540 if (msp->base == NULL)
2544 * Set up and register SMI bus.
2546 if (pd == NULL || pd->shared_smi == NULL) {
2547 msp->smi_bus = mdiobus_alloc();
2548 if (msp->smi_bus == NULL)
2551 msp->smi_bus->priv = msp;
2552 msp->smi_bus->name = "mv643xx_eth smi";
2553 msp->smi_bus->read = smi_bus_read;
2554 msp->smi_bus->write = smi_bus_write,
2555 snprintf(msp->smi_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
2556 msp->smi_bus->parent = &pdev->dev;
2557 msp->smi_bus->phy_mask = 0xffffffff;
2558 if (mdiobus_register(msp->smi_bus) < 0)
2559 goto out_free_mii_bus;
2562 msp->smi = platform_get_drvdata(pd->shared_smi);
2565 msp->err_interrupt = NO_IRQ;
2566 init_waitqueue_head(&msp->smi_busy_wait);
2569 * Check whether the error interrupt is hooked up.
2571 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2575 err = request_irq(res->start, mv643xx_eth_err_irq,
2576 IRQF_SHARED, "mv643xx_eth", msp);
2578 writel(ERR_INT_SMI_DONE, msp->base + ERR_INT_MASK);
2579 msp->err_interrupt = res->start;
2584 * (Re-)program MBUS remapping windows if we are asked to.
2586 if (pd != NULL && pd->dram != NULL)
2587 mv643xx_eth_conf_mbus_windows(msp, pd->dram);
2590 * Detect hardware parameters.
2592 msp->t_clk = (pd != NULL && pd->t_clk != 0) ? pd->t_clk : 133000000;
2593 infer_hw_params(msp);
2595 platform_set_drvdata(pdev, msp);
2600 mdiobus_free(msp->smi_bus);
2609 static int mv643xx_eth_shared_remove(struct platform_device *pdev)
2611 struct mv643xx_eth_shared_private *msp = platform_get_drvdata(pdev);
2612 struct mv643xx_eth_shared_platform_data *pd = pdev->dev.platform_data;
2614 if (pd == NULL || pd->shared_smi == NULL) {
2615 mdiobus_unregister(msp->smi_bus);
2616 mdiobus_free(msp->smi_bus);
2618 if (msp->err_interrupt != NO_IRQ)
2619 free_irq(msp->err_interrupt, msp);
2626 static struct platform_driver mv643xx_eth_shared_driver = {
2627 .probe = mv643xx_eth_shared_probe,
2628 .remove = mv643xx_eth_shared_remove,
2630 .name = MV643XX_ETH_SHARED_NAME,
2631 .owner = THIS_MODULE,
2635 static void phy_addr_set(struct mv643xx_eth_private *mp, int phy_addr)
2637 int addr_shift = 5 * mp->port_num;
2640 data = rdl(mp, PHY_ADDR);
2641 data &= ~(0x1f << addr_shift);
2642 data |= (phy_addr & 0x1f) << addr_shift;
2643 wrl(mp, PHY_ADDR, data);
2646 static int phy_addr_get(struct mv643xx_eth_private *mp)
2650 data = rdl(mp, PHY_ADDR);
2652 return (data >> (5 * mp->port_num)) & 0x1f;
2655 static void set_params(struct mv643xx_eth_private *mp,
2656 struct mv643xx_eth_platform_data *pd)
2658 struct net_device *dev = mp->dev;
2660 if (is_valid_ether_addr(pd->mac_addr))
2661 memcpy(dev->dev_addr, pd->mac_addr, 6);
2663 uc_addr_get(mp, dev->dev_addr);
2665 mp->rx_ring_size = DEFAULT_RX_QUEUE_SIZE;
2666 if (pd->rx_queue_size)
2667 mp->rx_ring_size = pd->rx_queue_size;
2668 mp->rx_desc_sram_addr = pd->rx_sram_addr;
2669 mp->rx_desc_sram_size = pd->rx_sram_size;
2671 mp->rxq_count = pd->rx_queue_count ? : 1;
2673 mp->tx_ring_size = DEFAULT_TX_QUEUE_SIZE;
2674 if (pd->tx_queue_size)
2675 mp->tx_ring_size = pd->tx_queue_size;
2676 mp->tx_desc_sram_addr = pd->tx_sram_addr;
2677 mp->tx_desc_sram_size = pd->tx_sram_size;
2679 mp->txq_count = pd->tx_queue_count ? : 1;
2682 static struct phy_device *phy_scan(struct mv643xx_eth_private *mp,
2685 struct mii_bus *bus = mp->shared->smi->smi_bus;
2686 struct phy_device *phydev;
2691 if (phy_addr == MV643XX_ETH_PHY_ADDR_DEFAULT) {
2692 start = phy_addr_get(mp) & 0x1f;
2695 start = phy_addr & 0x1f;
2700 for (i = 0; i < num; i++) {
2701 int addr = (start + i) & 0x1f;
2703 if (bus->phy_map[addr] == NULL)
2704 mdiobus_scan(bus, addr);
2706 if (phydev == NULL) {
2707 phydev = bus->phy_map[addr];
2709 phy_addr_set(mp, addr);
2716 static void phy_init(struct mv643xx_eth_private *mp, int speed, int duplex)
2718 struct phy_device *phy = mp->phy;
2722 phy_attach(mp->dev, dev_name(&phy->dev), 0, PHY_INTERFACE_MODE_GMII);
2725 phy->autoneg = AUTONEG_ENABLE;
2728 phy->advertising = phy->supported | ADVERTISED_Autoneg;
2730 phy->autoneg = AUTONEG_DISABLE;
2731 phy->advertising = 0;
2733 phy->duplex = duplex;
2735 phy_start_aneg(phy);
2738 static void init_pscr(struct mv643xx_eth_private *mp, int speed, int duplex)
2742 pscr = rdlp(mp, PORT_SERIAL_CONTROL);
2743 if (pscr & SERIAL_PORT_ENABLE) {
2744 pscr &= ~SERIAL_PORT_ENABLE;
2745 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2748 pscr = MAX_RX_PACKET_9700BYTE | SERIAL_PORT_CONTROL_RESERVED;
2749 if (mp->phy == NULL) {
2750 pscr |= DISABLE_AUTO_NEG_SPEED_GMII;
2751 if (speed == SPEED_1000)
2752 pscr |= SET_GMII_SPEED_TO_1000;
2753 else if (speed == SPEED_100)
2754 pscr |= SET_MII_SPEED_TO_100;
2756 pscr |= DISABLE_AUTO_NEG_FOR_FLOW_CTRL;
2758 pscr |= DISABLE_AUTO_NEG_FOR_DUPLEX;
2759 if (duplex == DUPLEX_FULL)
2760 pscr |= SET_FULL_DUPLEX_MODE;
2763 wrlp(mp, PORT_SERIAL_CONTROL, pscr);
2766 static int mv643xx_eth_probe(struct platform_device *pdev)
2768 struct mv643xx_eth_platform_data *pd;
2769 struct mv643xx_eth_private *mp;
2770 struct net_device *dev;
2771 struct resource *res;
2774 pd = pdev->dev.platform_data;
2776 dev_printk(KERN_ERR, &pdev->dev,
2777 "no mv643xx_eth_platform_data\n");
2781 if (pd->shared == NULL) {
2782 dev_printk(KERN_ERR, &pdev->dev,
2783 "no mv643xx_eth_platform_data->shared\n");
2787 dev = alloc_etherdev_mq(sizeof(struct mv643xx_eth_private), 8);
2791 mp = netdev_priv(dev);
2792 platform_set_drvdata(pdev, mp);
2794 mp->shared = platform_get_drvdata(pd->shared);
2795 mp->base = mp->shared->base + 0x0400 + (pd->port_number << 10);
2796 mp->port_num = pd->port_number;
2801 dev->real_num_tx_queues = mp->txq_count;
2803 if (pd->phy_addr != MV643XX_ETH_PHY_NONE)
2804 mp->phy = phy_scan(mp, pd->phy_addr);
2806 if (mp->phy != NULL)
2807 phy_init(mp, pd->speed, pd->duplex);
2809 SET_ETHTOOL_OPS(dev, &mv643xx_eth_ethtool_ops);
2811 init_pscr(mp, pd->speed, pd->duplex);
2814 mib_counters_clear(mp);
2816 init_timer(&mp->mib_counters_timer);
2817 mp->mib_counters_timer.data = (unsigned long)mp;
2818 mp->mib_counters_timer.function = mib_counters_timer_wrapper;
2819 mp->mib_counters_timer.expires = jiffies + 30 * HZ;
2820 add_timer(&mp->mib_counters_timer);
2822 spin_lock_init(&mp->mib_counters_lock);
2824 INIT_WORK(&mp->tx_timeout_task, tx_timeout_task);
2826 netif_napi_add(dev, &mp->napi, mv643xx_eth_poll, 128);
2828 init_timer(&mp->rx_oom);
2829 mp->rx_oom.data = (unsigned long)mp;
2830 mp->rx_oom.function = oom_timer_wrapper;
2833 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2835 dev->irq = res->start;
2837 dev->get_stats = mv643xx_eth_get_stats;
2838 dev->hard_start_xmit = mv643xx_eth_xmit;
2839 dev->open = mv643xx_eth_open;
2840 dev->stop = mv643xx_eth_stop;
2841 dev->set_rx_mode = mv643xx_eth_set_rx_mode;
2842 dev->set_mac_address = mv643xx_eth_set_mac_address;
2843 dev->do_ioctl = mv643xx_eth_ioctl;
2844 dev->change_mtu = mv643xx_eth_change_mtu;
2845 dev->tx_timeout = mv643xx_eth_tx_timeout;
2846 #ifdef CONFIG_NET_POLL_CONTROLLER
2847 dev->poll_controller = mv643xx_eth_netpoll;
2849 dev->watchdog_timeo = 2 * HZ;
2852 dev->features = NETIF_F_SG | NETIF_F_IP_CSUM;
2853 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM;
2855 SET_NETDEV_DEV(dev, &pdev->dev);
2857 if (mp->shared->win_protect)
2858 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect);
2860 err = register_netdev(dev);
2864 dev_printk(KERN_NOTICE, &dev->dev, "port %d with MAC address %pM\n",
2865 mp->port_num, dev->dev_addr);
2867 if (mp->tx_desc_sram_size > 0)
2868 dev_printk(KERN_NOTICE, &dev->dev, "configured with sram\n");
2878 static int mv643xx_eth_remove(struct platform_device *pdev)
2880 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2882 unregister_netdev(mp->dev);
2883 if (mp->phy != NULL)
2884 phy_detach(mp->phy);
2885 flush_scheduled_work();
2886 free_netdev(mp->dev);
2888 platform_set_drvdata(pdev, NULL);
2893 static void mv643xx_eth_shutdown(struct platform_device *pdev)
2895 struct mv643xx_eth_private *mp = platform_get_drvdata(pdev);
2897 /* Mask all interrupts on ethernet port */
2898 wrlp(mp, INT_MASK, 0);
2901 if (netif_running(mp->dev))
2905 static struct platform_driver mv643xx_eth_driver = {
2906 .probe = mv643xx_eth_probe,
2907 .remove = mv643xx_eth_remove,
2908 .shutdown = mv643xx_eth_shutdown,
2910 .name = MV643XX_ETH_NAME,
2911 .owner = THIS_MODULE,
2915 static int __init mv643xx_eth_init_module(void)
2919 rc = platform_driver_register(&mv643xx_eth_shared_driver);
2921 rc = platform_driver_register(&mv643xx_eth_driver);
2923 platform_driver_unregister(&mv643xx_eth_shared_driver);
2928 module_init(mv643xx_eth_init_module);
2930 static void __exit mv643xx_eth_cleanup_module(void)
2932 platform_driver_unregister(&mv643xx_eth_driver);
2933 platform_driver_unregister(&mv643xx_eth_shared_driver);
2935 module_exit(mv643xx_eth_cleanup_module);
2937 MODULE_AUTHOR("Rabeeh Khoury, Assaf Hoffman, Matthew Dharm, "
2938 "Manish Lachwani, Dale Farnsworth and Lennert Buytenhek");
2939 MODULE_DESCRIPTION("Ethernet driver for Marvell MV643XX");
2940 MODULE_LICENSE("GPL");
2941 MODULE_ALIAS("platform:" MV643XX_ETH_SHARED_NAME);
2942 MODULE_ALIAS("platform:" MV643XX_ETH_NAME);