2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Sun Microsystems, Inc. All rights reserved.
4 * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/module.h>
37 #include <linux/init.h>
38 #include <linux/errno.h>
39 #include <linux/pci.h>
40 #include <linux/dma-mapping.h>
41 #include <linux/slab.h>
43 #include <linux/mlx4/device.h>
44 #include <linux/mlx4/doorbell.h>
50 MODULE_AUTHOR("Roland Dreier");
51 MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
52 MODULE_LICENSE("Dual BSD/GPL");
53 MODULE_VERSION(DRV_VERSION);
55 struct workqueue_struct *mlx4_wq;
57 #ifdef CONFIG_MLX4_DEBUG
59 int mlx4_debug_level = 0;
60 module_param_named(debug_level, mlx4_debug_level, int, 0644);
61 MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
63 #endif /* CONFIG_MLX4_DEBUG */
68 module_param(msi_x, int, 0444);
69 MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
71 #else /* CONFIG_PCI_MSI */
75 #endif /* CONFIG_PCI_MSI */
77 static char mlx4_version[] __devinitdata =
78 DRV_NAME ": Mellanox ConnectX core driver v"
79 DRV_VERSION " (" DRV_RELDATE ")\n";
81 static struct mlx4_profile default_profile = {
84 .rdmarc_per_qp = 1 << 4,
91 static int log_num_mac = 2;
92 module_param_named(log_num_mac, log_num_mac, int, 0444);
93 MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
95 static int log_num_vlan;
96 module_param_named(log_num_vlan, log_num_vlan, int, 0444);
97 MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
100 module_param_named(use_prio, use_prio, bool, 0444);
101 MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports "
104 static int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
105 module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
106 MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-5)");
108 int mlx4_check_port_params(struct mlx4_dev *dev,
109 enum mlx4_port_type *port_type)
113 for (i = 0; i < dev->caps.num_ports - 1; i++) {
114 if (port_type[i] != port_type[i + 1]) {
115 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
116 mlx4_err(dev, "Only same port types supported "
117 "on this HCA, aborting.\n");
120 if (port_type[i] == MLX4_PORT_TYPE_ETH &&
121 port_type[i + 1] == MLX4_PORT_TYPE_IB)
126 for (i = 0; i < dev->caps.num_ports; i++) {
127 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
128 mlx4_err(dev, "Requested port type for port %d is not "
129 "supported on this HCA\n", i + 1);
136 static void mlx4_set_port_mask(struct mlx4_dev *dev)
140 dev->caps.port_mask = 0;
141 for (i = 1; i <= dev->caps.num_ports; ++i)
142 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_IB)
143 dev->caps.port_mask |= 1 << (i - 1);
145 static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
150 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
152 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
156 if (dev_cap->min_page_sz > PAGE_SIZE) {
157 mlx4_err(dev, "HCA minimum page size of %d bigger than "
158 "kernel PAGE_SIZE of %ld, aborting.\n",
159 dev_cap->min_page_sz, PAGE_SIZE);
162 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
163 mlx4_err(dev, "HCA has %d ports, but we only support %d, "
165 dev_cap->num_ports, MLX4_MAX_PORTS);
169 if (dev_cap->uar_size > pci_resource_len(dev->pdev, 2)) {
170 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than "
171 "PCI resource 2 size of 0x%llx, aborting.\n",
173 (unsigned long long) pci_resource_len(dev->pdev, 2));
177 dev->caps.num_ports = dev_cap->num_ports;
178 for (i = 1; i <= dev->caps.num_ports; ++i) {
179 dev->caps.vl_cap[i] = dev_cap->max_vl[i];
180 dev->caps.ib_mtu_cap[i] = dev_cap->ib_mtu[i];
181 dev->caps.gid_table_len[i] = dev_cap->max_gids[i];
182 dev->caps.pkey_table_len[i] = dev_cap->max_pkeys[i];
183 dev->caps.port_width_cap[i] = dev_cap->max_port_width[i];
184 dev->caps.eth_mtu_cap[i] = dev_cap->eth_mtu[i];
185 dev->caps.def_mac[i] = dev_cap->def_mac[i];
186 dev->caps.supported_type[i] = dev_cap->supported_port_types[i];
189 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
190 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
191 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
192 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
193 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
194 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
195 dev->caps.max_wqes = dev_cap->max_qp_sz;
196 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
197 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
198 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
199 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
200 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
201 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
202 dev->caps.num_qp_per_mgm = MLX4_QP_PER_MGM;
204 * Subtract 1 from the limit because we need to allocate a
205 * spare CQE so the HCA HW can tell the difference between an
206 * empty CQ and a full CQ.
208 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
209 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
210 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
211 dev->caps.mtts_per_seg = 1 << log_mtts_per_seg;
212 dev->caps.reserved_mtts = DIV_ROUND_UP(dev_cap->reserved_mtts,
213 dev->caps.mtts_per_seg);
214 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
215 dev->caps.reserved_uars = dev_cap->reserved_uars;
216 dev->caps.reserved_pds = dev_cap->reserved_pds;
217 dev->caps.mtt_entry_sz = dev->caps.mtts_per_seg * dev_cap->mtt_entry_sz;
218 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
219 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
220 dev->caps.flags = dev_cap->flags;
221 dev->caps.bmme_flags = dev_cap->bmme_flags;
222 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
223 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
224 dev->caps.loopback_support = dev_cap->loopback_support;
225 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
227 dev->caps.log_num_macs = log_num_mac;
228 dev->caps.log_num_vlans = log_num_vlan;
229 dev->caps.log_num_prios = use_prio ? 3 : 0;
231 for (i = 1; i <= dev->caps.num_ports; ++i) {
232 if (dev->caps.supported_type[i] != MLX4_PORT_TYPE_ETH)
233 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
235 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
236 dev->caps.possible_type[i] = dev->caps.port_type[i];
237 mlx4_priv(dev)->sense.sense_allowed[i] =
238 dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO;
240 if (dev->caps.log_num_macs > dev_cap->log_max_macs[i]) {
241 dev->caps.log_num_macs = dev_cap->log_max_macs[i];
242 mlx4_warn(dev, "Requested number of MACs is too much "
243 "for port %d, reducing to %d.\n",
244 i, 1 << dev->caps.log_num_macs);
246 if (dev->caps.log_num_vlans > dev_cap->log_max_vlans[i]) {
247 dev->caps.log_num_vlans = dev_cap->log_max_vlans[i];
248 mlx4_warn(dev, "Requested number of VLANs is too much "
249 "for port %d, reducing to %d.\n",
250 i, 1 << dev->caps.log_num_vlans);
254 mlx4_set_port_mask(dev);
256 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
257 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
258 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
259 (1 << dev->caps.log_num_macs) *
260 (1 << dev->caps.log_num_vlans) *
261 (1 << dev->caps.log_num_prios) *
263 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
265 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
266 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
267 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
268 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
274 * Change the port configuration of the device.
275 * Every user of this function must hold the port mutex.
277 int mlx4_change_port_types(struct mlx4_dev *dev,
278 enum mlx4_port_type *port_types)
284 for (port = 0; port < dev->caps.num_ports; port++) {
285 /* Change the port type only if the new type is different
286 * from the current, and not set to Auto */
287 if (port_types[port] != dev->caps.port_type[port + 1]) {
289 dev->caps.port_type[port + 1] = port_types[port];
293 mlx4_unregister_device(dev);
294 for (port = 1; port <= dev->caps.num_ports; port++) {
295 mlx4_CLOSE_PORT(dev, port);
296 err = mlx4_SET_PORT(dev, port);
298 mlx4_err(dev, "Failed to set port %d, "
303 mlx4_set_port_mask(dev);
304 err = mlx4_register_device(dev);
311 static ssize_t show_port_type(struct device *dev,
312 struct device_attribute *attr,
315 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
317 struct mlx4_dev *mdev = info->dev;
321 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
323 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
324 sprintf(buf, "auto (%s)\n", type);
326 sprintf(buf, "%s\n", type);
331 static ssize_t set_port_type(struct device *dev,
332 struct device_attribute *attr,
333 const char *buf, size_t count)
335 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
337 struct mlx4_dev *mdev = info->dev;
338 struct mlx4_priv *priv = mlx4_priv(mdev);
339 enum mlx4_port_type types[MLX4_MAX_PORTS];
340 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
344 if (!strcmp(buf, "ib\n"))
345 info->tmp_type = MLX4_PORT_TYPE_IB;
346 else if (!strcmp(buf, "eth\n"))
347 info->tmp_type = MLX4_PORT_TYPE_ETH;
348 else if (!strcmp(buf, "auto\n"))
349 info->tmp_type = MLX4_PORT_TYPE_AUTO;
351 mlx4_err(mdev, "%s is not supported port type\n", buf);
355 mlx4_stop_sense(mdev);
356 mutex_lock(&priv->port_mutex);
357 /* Possible type is always the one that was delivered */
358 mdev->caps.possible_type[info->port] = info->tmp_type;
360 for (i = 0; i < mdev->caps.num_ports; i++) {
361 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
362 mdev->caps.possible_type[i+1];
363 if (types[i] == MLX4_PORT_TYPE_AUTO)
364 types[i] = mdev->caps.port_type[i+1];
367 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
368 for (i = 1; i <= mdev->caps.num_ports; i++) {
369 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
370 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
376 mlx4_err(mdev, "Auto sensing is not supported on this HCA. "
377 "Set only 'eth' or 'ib' for both ports "
378 "(should be the same)\n");
382 mlx4_do_sense_ports(mdev, new_types, types);
384 err = mlx4_check_port_params(mdev, new_types);
388 /* We are about to apply the changes after the configuration
389 * was verified, no need to remember the temporary types
391 for (i = 0; i < mdev->caps.num_ports; i++)
392 priv->port[i + 1].tmp_type = 0;
394 err = mlx4_change_port_types(mdev, new_types);
397 mlx4_start_sense(mdev);
398 mutex_unlock(&priv->port_mutex);
399 return err ? err : count;
402 static int mlx4_load_fw(struct mlx4_dev *dev)
404 struct mlx4_priv *priv = mlx4_priv(dev);
407 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
408 GFP_HIGHUSER | __GFP_NOWARN, 0);
409 if (!priv->fw.fw_icm) {
410 mlx4_err(dev, "Couldn't allocate FW area, aborting.\n");
414 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
416 mlx4_err(dev, "MAP_FA command failed, aborting.\n");
420 err = mlx4_RUN_FW(dev);
422 mlx4_err(dev, "RUN_FW command failed, aborting.\n");
432 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
436 static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
439 struct mlx4_priv *priv = mlx4_priv(dev);
442 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
444 ((u64) (MLX4_CMPT_TYPE_QP *
445 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
446 cmpt_entry_sz, dev->caps.num_qps,
447 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
452 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
454 ((u64) (MLX4_CMPT_TYPE_SRQ *
455 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
456 cmpt_entry_sz, dev->caps.num_srqs,
457 dev->caps.reserved_srqs, 0, 0);
461 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
463 ((u64) (MLX4_CMPT_TYPE_CQ *
464 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
465 cmpt_entry_sz, dev->caps.num_cqs,
466 dev->caps.reserved_cqs, 0, 0);
470 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
472 ((u64) (MLX4_CMPT_TYPE_EQ *
473 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
475 dev->caps.num_eqs, dev->caps.num_eqs, 0, 0);
482 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
485 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
488 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
494 static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
495 struct mlx4_init_hca_param *init_hca, u64 icm_size)
497 struct mlx4_priv *priv = mlx4_priv(dev);
501 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
503 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting.\n");
507 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory.\n",
508 (unsigned long long) icm_size >> 10,
509 (unsigned long long) aux_pages << 2);
511 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
512 GFP_HIGHUSER | __GFP_NOWARN, 0);
513 if (!priv->fw.aux_icm) {
514 mlx4_err(dev, "Couldn't allocate aux memory, aborting.\n");
518 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
520 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting.\n");
524 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
526 mlx4_err(dev, "Failed to map cMPT context memory, aborting.\n");
530 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
531 init_hca->eqc_base, dev_cap->eqc_entry_sz,
532 dev->caps.num_eqs, dev->caps.num_eqs,
535 mlx4_err(dev, "Failed to map EQ context memory, aborting.\n");
540 * Reserved MTT entries must be aligned up to a cacheline
541 * boundary, since the FW will write to them, while the driver
542 * writes to all other MTT entries. (The variable
543 * dev->caps.mtt_entry_sz below is really the MTT segment
544 * size, not the raw entry size)
546 dev->caps.reserved_mtts =
547 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
548 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
550 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
552 dev->caps.mtt_entry_sz,
553 dev->caps.num_mtt_segs,
554 dev->caps.reserved_mtts, 1, 0);
556 mlx4_err(dev, "Failed to map MTT context memory, aborting.\n");
560 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
562 dev_cap->dmpt_entry_sz,
564 dev->caps.reserved_mrws, 1, 1);
566 mlx4_err(dev, "Failed to map dMPT context memory, aborting.\n");
570 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
572 dev_cap->qpc_entry_sz,
574 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
577 mlx4_err(dev, "Failed to map QP context memory, aborting.\n");
581 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
583 dev_cap->aux_entry_sz,
585 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
588 mlx4_err(dev, "Failed to map AUXC context memory, aborting.\n");
592 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
594 dev_cap->altc_entry_sz,
596 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
599 mlx4_err(dev, "Failed to map ALTC context memory, aborting.\n");
603 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
604 init_hca->rdmarc_base,
605 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
607 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
610 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
614 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
616 dev_cap->cqc_entry_sz,
618 dev->caps.reserved_cqs, 0, 0);
620 mlx4_err(dev, "Failed to map CQ context memory, aborting.\n");
621 goto err_unmap_rdmarc;
624 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
626 dev_cap->srq_entry_sz,
628 dev->caps.reserved_srqs, 0, 0);
630 mlx4_err(dev, "Failed to map SRQ context memory, aborting.\n");
635 * It's not strictly required, but for simplicity just map the
636 * whole multicast group table now. The table isn't very big
637 * and it's a lot easier than trying to track ref counts.
639 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
640 init_hca->mc_base, MLX4_MGM_ENTRY_SIZE,
641 dev->caps.num_mgms + dev->caps.num_amgms,
642 dev->caps.num_mgms + dev->caps.num_amgms,
645 mlx4_err(dev, "Failed to map MCG context memory, aborting.\n");
652 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
655 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
658 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
661 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
664 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
667 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
670 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
673 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
676 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
679 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
680 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
681 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
682 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
685 mlx4_UNMAP_ICM_AUX(dev);
688 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
693 static void mlx4_free_icms(struct mlx4_dev *dev)
695 struct mlx4_priv *priv = mlx4_priv(dev);
697 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
698 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
699 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
700 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
701 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
702 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
703 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
704 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
705 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
706 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
707 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
708 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
709 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
710 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
712 mlx4_UNMAP_ICM_AUX(dev);
713 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
716 static void mlx4_close_hca(struct mlx4_dev *dev)
718 mlx4_CLOSE_HCA(dev, 0);
721 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
724 static int mlx4_init_hca(struct mlx4_dev *dev)
726 struct mlx4_priv *priv = mlx4_priv(dev);
727 struct mlx4_adapter adapter;
728 struct mlx4_dev_cap dev_cap;
729 struct mlx4_mod_stat_cfg mlx4_cfg;
730 struct mlx4_profile profile;
731 struct mlx4_init_hca_param init_hca;
735 err = mlx4_QUERY_FW(dev);
738 mlx4_info(dev, "non-primary physical function, skipping.\n");
740 mlx4_err(dev, "QUERY_FW command failed, aborting.\n");
744 err = mlx4_load_fw(dev);
746 mlx4_err(dev, "Failed to start FW, aborting.\n");
750 mlx4_cfg.log_pg_sz_m = 1;
751 mlx4_cfg.log_pg_sz = 0;
752 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
754 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
756 err = mlx4_dev_cap(dev, &dev_cap);
758 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
762 profile = default_profile;
764 icm_size = mlx4_make_profile(dev, &profile, &dev_cap, &init_hca);
765 if ((long long) icm_size < 0) {
770 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
772 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
776 err = mlx4_INIT_HCA(dev, &init_hca);
778 mlx4_err(dev, "INIT_HCA command failed, aborting.\n");
782 err = mlx4_QUERY_ADAPTER(dev, &adapter);
784 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting.\n");
788 priv->eq_table.inta_pin = adapter.inta_pin;
789 memcpy(dev->board_id, adapter.board_id, sizeof dev->board_id);
794 mlx4_CLOSE_HCA(dev, 0);
801 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
806 static int mlx4_setup_hca(struct mlx4_dev *dev)
808 struct mlx4_priv *priv = mlx4_priv(dev);
811 __be32 ib_port_default_caps;
813 err = mlx4_init_uar_table(dev);
815 mlx4_err(dev, "Failed to initialize "
816 "user access region table, aborting.\n");
820 err = mlx4_uar_alloc(dev, &priv->driver_uar);
822 mlx4_err(dev, "Failed to allocate driver access region, "
824 goto err_uar_table_free;
827 priv->kar = ioremap(priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
829 mlx4_err(dev, "Couldn't map kernel access region, "
835 err = mlx4_init_pd_table(dev);
837 mlx4_err(dev, "Failed to initialize "
838 "protection domain table, aborting.\n");
842 err = mlx4_init_mr_table(dev);
844 mlx4_err(dev, "Failed to initialize "
845 "memory region table, aborting.\n");
846 goto err_pd_table_free;
849 err = mlx4_init_eq_table(dev);
851 mlx4_err(dev, "Failed to initialize "
852 "event queue table, aborting.\n");
853 goto err_mr_table_free;
856 err = mlx4_cmd_use_events(dev);
858 mlx4_err(dev, "Failed to switch to event-driven "
859 "firmware commands, aborting.\n");
860 goto err_eq_table_free;
865 if (dev->flags & MLX4_FLAG_MSI_X) {
866 mlx4_warn(dev, "NOP command failed to generate MSI-X "
867 "interrupt IRQ %d).\n",
868 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
869 mlx4_warn(dev, "Trying again without MSI-X.\n");
871 mlx4_err(dev, "NOP command failed to generate interrupt "
872 "(IRQ %d), aborting.\n",
873 priv->eq_table.eq[dev->caps.num_comp_vectors].irq);
874 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
880 mlx4_dbg(dev, "NOP command IRQ test passed\n");
882 err = mlx4_init_cq_table(dev);
884 mlx4_err(dev, "Failed to initialize "
885 "completion queue table, aborting.\n");
889 err = mlx4_init_srq_table(dev);
891 mlx4_err(dev, "Failed to initialize "
892 "shared receive queue table, aborting.\n");
893 goto err_cq_table_free;
896 err = mlx4_init_qp_table(dev);
898 mlx4_err(dev, "Failed to initialize "
899 "queue pair table, aborting.\n");
900 goto err_srq_table_free;
903 err = mlx4_init_mcg_table(dev);
905 mlx4_err(dev, "Failed to initialize "
906 "multicast group table, aborting.\n");
907 goto err_qp_table_free;
910 for (port = 1; port <= dev->caps.num_ports; port++) {
911 ib_port_default_caps = 0;
912 err = mlx4_get_port_ib_caps(dev, port, &ib_port_default_caps);
914 mlx4_warn(dev, "failed to get port %d default "
915 "ib capabilities (%d). Continuing with "
916 "caps = 0\n", port, err);
917 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
918 err = mlx4_SET_PORT(dev, port);
920 mlx4_err(dev, "Failed to set port %d, aborting\n",
922 goto err_mcg_table_free;
929 mlx4_cleanup_mcg_table(dev);
932 mlx4_cleanup_qp_table(dev);
935 mlx4_cleanup_srq_table(dev);
938 mlx4_cleanup_cq_table(dev);
941 mlx4_cmd_use_polling(dev);
944 mlx4_cleanup_eq_table(dev);
947 mlx4_cleanup_mr_table(dev);
950 mlx4_cleanup_pd_table(dev);
956 mlx4_uar_free(dev, &priv->driver_uar);
959 mlx4_cleanup_uar_table(dev);
963 static void mlx4_enable_msi_x(struct mlx4_dev *dev)
965 struct mlx4_priv *priv = mlx4_priv(dev);
966 struct msix_entry *entries;
972 nreq = min_t(int, dev->caps.num_eqs - dev->caps.reserved_eqs,
973 num_possible_cpus() + 1);
974 entries = kcalloc(nreq, sizeof *entries, GFP_KERNEL);
978 for (i = 0; i < nreq; ++i)
979 entries[i].entry = i;
982 err = pci_enable_msix(dev->pdev, entries, nreq);
984 /* Try again if at least 2 vectors are available */
986 mlx4_info(dev, "Requested %d vectors, "
987 "but only %d MSI-X vectors available, "
988 "trying again\n", nreq, err);
996 dev->caps.num_comp_vectors = nreq - 1;
997 for (i = 0; i < nreq; ++i)
998 priv->eq_table.eq[i].irq = entries[i].vector;
1000 dev->flags |= MLX4_FLAG_MSI_X;
1007 dev->caps.num_comp_vectors = 1;
1009 for (i = 0; i < 2; ++i)
1010 priv->eq_table.eq[i].irq = dev->pdev->irq;
1013 static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
1015 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
1020 mlx4_init_mac_table(dev, &info->mac_table);
1021 mlx4_init_vlan_table(dev, &info->vlan_table);
1023 sprintf(info->dev_name, "mlx4_port%d", port);
1024 info->port_attr.attr.name = info->dev_name;
1025 info->port_attr.attr.mode = S_IRUGO | S_IWUSR;
1026 info->port_attr.show = show_port_type;
1027 info->port_attr.store = set_port_type;
1028 sysfs_attr_init(&info->port_attr.attr);
1030 err = device_create_file(&dev->pdev->dev, &info->port_attr);
1032 mlx4_err(dev, "Failed to create file for port %d\n", port);
1039 static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
1044 device_remove_file(&info->dev->pdev->dev, &info->port_attr);
1047 static int __mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
1049 struct mlx4_priv *priv;
1050 struct mlx4_dev *dev;
1054 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
1056 err = pci_enable_device(pdev);
1058 dev_err(&pdev->dev, "Cannot enable PCI device, "
1064 * Check for BARs. We expect 0: 1MB
1066 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM) ||
1067 pci_resource_len(pdev, 0) != 1 << 20) {
1068 dev_err(&pdev->dev, "Missing DCS, aborting.\n");
1070 goto err_disable_pdev;
1072 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
1073 dev_err(&pdev->dev, "Missing UAR, aborting.\n");
1075 goto err_disable_pdev;
1078 err = pci_request_regions(pdev, DRV_NAME);
1080 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
1081 goto err_disable_pdev;
1084 pci_set_master(pdev);
1086 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
1088 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask.\n");
1089 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1091 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting.\n");
1092 goto err_release_regions;
1095 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1097 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit "
1098 "consistent PCI DMA mask.\n");
1099 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1101 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, "
1103 goto err_release_regions;
1107 priv = kzalloc(sizeof *priv, GFP_KERNEL);
1109 dev_err(&pdev->dev, "Device struct alloc failed, "
1112 goto err_release_regions;
1117 INIT_LIST_HEAD(&priv->ctx_list);
1118 spin_lock_init(&priv->ctx_lock);
1120 mutex_init(&priv->port_mutex);
1122 INIT_LIST_HEAD(&priv->pgdir_list);
1123 mutex_init(&priv->pgdir_mutex);
1126 * Now reset the HCA before we touch the PCI capabilities or
1127 * attempt a firmware command, since a boot ROM may have left
1128 * the HCA in an undefined state.
1130 err = mlx4_reset(dev);
1132 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
1136 if (mlx4_cmd_init(dev)) {
1137 mlx4_err(dev, "Failed to init command interface, aborting.\n");
1141 err = mlx4_init_hca(dev);
1145 err = mlx4_alloc_eq_table(dev);
1149 mlx4_enable_msi_x(dev);
1151 err = mlx4_setup_hca(dev);
1152 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X)) {
1153 dev->flags &= ~MLX4_FLAG_MSI_X;
1154 pci_disable_msix(pdev);
1155 err = mlx4_setup_hca(dev);
1161 for (port = 1; port <= dev->caps.num_ports; port++) {
1162 err = mlx4_init_port_info(dev, port);
1167 err = mlx4_register_device(dev);
1171 mlx4_sense_init(dev);
1172 mlx4_start_sense(dev);
1174 pci_set_drvdata(pdev, dev);
1179 for (--port; port >= 1; --port)
1180 mlx4_cleanup_port_info(&priv->port[port]);
1182 mlx4_cleanup_mcg_table(dev);
1183 mlx4_cleanup_qp_table(dev);
1184 mlx4_cleanup_srq_table(dev);
1185 mlx4_cleanup_cq_table(dev);
1186 mlx4_cmd_use_polling(dev);
1187 mlx4_cleanup_eq_table(dev);
1188 mlx4_cleanup_mr_table(dev);
1189 mlx4_cleanup_pd_table(dev);
1190 mlx4_cleanup_uar_table(dev);
1193 mlx4_free_eq_table(dev);
1196 if (dev->flags & MLX4_FLAG_MSI_X)
1197 pci_disable_msix(pdev);
1199 mlx4_close_hca(dev);
1202 mlx4_cmd_cleanup(dev);
1207 err_release_regions:
1208 pci_release_regions(pdev);
1211 pci_disable_device(pdev);
1212 pci_set_drvdata(pdev, NULL);
1216 static int __devinit mlx4_init_one(struct pci_dev *pdev,
1217 const struct pci_device_id *id)
1219 printk_once(KERN_INFO "%s", mlx4_version);
1221 return __mlx4_init_one(pdev, id);
1224 static void mlx4_remove_one(struct pci_dev *pdev)
1226 struct mlx4_dev *dev = pci_get_drvdata(pdev);
1227 struct mlx4_priv *priv = mlx4_priv(dev);
1231 mlx4_stop_sense(dev);
1232 mlx4_unregister_device(dev);
1234 for (p = 1; p <= dev->caps.num_ports; p++) {
1235 mlx4_cleanup_port_info(&priv->port[p]);
1236 mlx4_CLOSE_PORT(dev, p);
1239 mlx4_cleanup_mcg_table(dev);
1240 mlx4_cleanup_qp_table(dev);
1241 mlx4_cleanup_srq_table(dev);
1242 mlx4_cleanup_cq_table(dev);
1243 mlx4_cmd_use_polling(dev);
1244 mlx4_cleanup_eq_table(dev);
1245 mlx4_cleanup_mr_table(dev);
1246 mlx4_cleanup_pd_table(dev);
1249 mlx4_uar_free(dev, &priv->driver_uar);
1250 mlx4_cleanup_uar_table(dev);
1251 mlx4_free_eq_table(dev);
1252 mlx4_close_hca(dev);
1253 mlx4_cmd_cleanup(dev);
1255 if (dev->flags & MLX4_FLAG_MSI_X)
1256 pci_disable_msix(pdev);
1259 pci_release_regions(pdev);
1260 pci_disable_device(pdev);
1261 pci_set_drvdata(pdev, NULL);
1265 int mlx4_restart_one(struct pci_dev *pdev)
1267 mlx4_remove_one(pdev);
1268 return __mlx4_init_one(pdev, NULL);
1271 static DEFINE_PCI_DEVICE_TABLE(mlx4_pci_table) = {
1272 { PCI_VDEVICE(MELLANOX, 0x6340) }, /* MT25408 "Hermon" SDR */
1273 { PCI_VDEVICE(MELLANOX, 0x634a) }, /* MT25408 "Hermon" DDR */
1274 { PCI_VDEVICE(MELLANOX, 0x6354) }, /* MT25408 "Hermon" QDR */
1275 { PCI_VDEVICE(MELLANOX, 0x6732) }, /* MT25408 "Hermon" DDR PCIe gen2 */
1276 { PCI_VDEVICE(MELLANOX, 0x673c) }, /* MT25408 "Hermon" QDR PCIe gen2 */
1277 { PCI_VDEVICE(MELLANOX, 0x6368) }, /* MT25408 "Hermon" EN 10GigE */
1278 { PCI_VDEVICE(MELLANOX, 0x6750) }, /* MT25408 "Hermon" EN 10GigE PCIe gen2 */
1279 { PCI_VDEVICE(MELLANOX, 0x6372) }, /* MT25458 ConnectX EN 10GBASE-T 10GigE */
1280 { PCI_VDEVICE(MELLANOX, 0x675a) }, /* MT25458 ConnectX EN 10GBASE-T+Gen2 10GigE */
1281 { PCI_VDEVICE(MELLANOX, 0x6764) }, /* MT26468 ConnectX EN 10GigE PCIe gen2*/
1282 { PCI_VDEVICE(MELLANOX, 0x6746) }, /* MT26438 ConnectX EN 40GigE PCIe gen2 5GT/s */
1283 { PCI_VDEVICE(MELLANOX, 0x676e) }, /* MT26478 ConnectX2 40GigE PCIe gen2 */
1287 MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
1289 static struct pci_driver mlx4_driver = {
1291 .id_table = mlx4_pci_table,
1292 .probe = mlx4_init_one,
1293 .remove = __devexit_p(mlx4_remove_one)
1296 static int __init mlx4_verify_params(void)
1298 if ((log_num_mac < 0) || (log_num_mac > 7)) {
1299 pr_warning("mlx4_core: bad num_mac: %d\n", log_num_mac);
1303 if ((log_num_vlan < 0) || (log_num_vlan > 7)) {
1304 pr_warning("mlx4_core: bad num_vlan: %d\n", log_num_vlan);
1308 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 5)) {
1309 pr_warning("mlx4_core: bad log_mtts_per_seg: %d\n", log_mtts_per_seg);
1316 static int __init mlx4_init(void)
1320 if (mlx4_verify_params())
1325 mlx4_wq = create_singlethread_workqueue("mlx4");
1329 ret = pci_register_driver(&mlx4_driver);
1330 return ret < 0 ? ret : 0;
1333 static void __exit mlx4_cleanup(void)
1335 pci_unregister_driver(&mlx4_driver);
1336 destroy_workqueue(mlx4_wq);
1339 module_init(mlx4_init);
1340 module_exit(mlx4_cleanup);