2 * Driver for Xilinx TEMAC Ethernet device
4 * Copyright (c) 2008 Nissin Systems Co., Ltd., Yoshio Kashiwagi
5 * Copyright (c) 2005-2008 DLA Systems, David H. Lynch Jr. <dhlii@dlasys.net>
6 * Copyright (c) 2008-2009 Secret Lab Technologies Ltd.
8 * This is a driver for the Xilinx ll_temac ipcore which is often used
9 * in the Virtex and Spartan series of chips.
12 * - The ll_temac hardware uses indirect access for many of the TEMAC
13 * registers, include the MDIO bus. However, indirect access to MDIO
14 * registers take considerably more clock cycles than to TEMAC registers.
15 * MDIO accesses are long, so threads doing them should probably sleep
16 * rather than busywait. However, since only one indirect access can be
17 * in progress at any given time, that means that *all* indirect accesses
18 * could end up sleeping (to wait for an MDIO access to complete).
19 * Fortunately none of the indirect accesses are on the 'hot' path for tx
20 * or rx, so this should be okay.
23 * - Factor out locallink DMA code into separate driver
24 * - Fix multicast assignment.
25 * - Fix support for hardware checksumming.
26 * - Testing. Lots and lots of testing.
30 #include <linux/delay.h>
31 #include <linux/etherdevice.h>
32 #include <linux/init.h>
33 #include <linux/mii.h>
34 #include <linux/module.h>
35 #include <linux/mutex.h>
36 #include <linux/netdevice.h>
38 #include <linux/of_device.h>
39 #include <linux/of_mdio.h>
40 #include <linux/of_platform.h>
41 #include <linux/of_address.h>
42 #include <linux/skbuff.h>
43 #include <linux/spinlock.h>
44 #include <linux/tcp.h> /* needed for sizeof(tcphdr) */
45 #include <linux/udp.h> /* needed for sizeof(udphdr) */
46 #include <linux/phy.h>
50 #include <linux/slab.h>
51 #include <linux/interrupt.h>
58 /* ---------------------------------------------------------------------
59 * Low level register access functions
62 u32 temac_ior(struct temac_local *lp, int offset)
64 return in_be32((u32 *)(lp->regs + offset));
67 void temac_iow(struct temac_local *lp, int offset, u32 value)
69 out_be32((u32 *) (lp->regs + offset), value);
72 int temac_indirect_busywait(struct temac_local *lp)
74 long end = jiffies + 2;
76 while (!(temac_ior(lp, XTE_RDY0_OFFSET) & XTE_RDY0_HARD_ACS_RDY_MASK)) {
77 if (end - jiffies <= 0) {
89 * lp->indirect_mutex must be held when calling this function
91 u32 temac_indirect_in32(struct temac_local *lp, int reg)
95 if (temac_indirect_busywait(lp))
97 temac_iow(lp, XTE_CTL0_OFFSET, reg);
98 if (temac_indirect_busywait(lp))
100 val = temac_ior(lp, XTE_LSW0_OFFSET);
106 * temac_indirect_out32
108 * lp->indirect_mutex must be held when calling this function
110 void temac_indirect_out32(struct temac_local *lp, int reg, u32 value)
112 if (temac_indirect_busywait(lp))
114 temac_iow(lp, XTE_LSW0_OFFSET, value);
115 temac_iow(lp, XTE_CTL0_OFFSET, CNTLREG_WRITE_ENABLE_MASK | reg);
119 * temac_dma_in32 - Memory mapped DMA read, this function expects a
120 * register input that is based on DCR word addresses which
121 * are then converted to memory mapped byte addresses
123 static u32 temac_dma_in32(struct temac_local *lp, int reg)
125 return in_be32((u32 *)(lp->sdma_regs + (reg << 2)));
129 * temac_dma_out32 - Memory mapped DMA read, this function expects a
130 * register input that is based on DCR word addresses which
131 * are then converted to memory mapped byte addresses
133 static void temac_dma_out32(struct temac_local *lp, int reg, u32 value)
135 out_be32((u32 *)(lp->sdma_regs + (reg << 2)), value);
138 /* DMA register access functions can be DCR based or memory mapped.
139 * The PowerPC 440 is DCR based, the PowerPC 405 and MicroBlaze are both
142 #ifdef CONFIG_PPC_DCR
145 * temac_dma_dcr_in32 - DCR based DMA read
147 static u32 temac_dma_dcr_in(struct temac_local *lp, int reg)
149 return dcr_read(lp->sdma_dcrs, reg);
153 * temac_dma_dcr_out32 - DCR based DMA write
155 static void temac_dma_dcr_out(struct temac_local *lp, int reg, u32 value)
157 dcr_write(lp->sdma_dcrs, reg, value);
161 * temac_dcr_setup - If the DMA is DCR based, then setup the address and
164 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
165 struct device_node *np)
169 /* setup the dcr address mapping if it's in the device tree */
171 dcrs = dcr_resource_start(np, 0);
173 lp->sdma_dcrs = dcr_map(np, dcrs, dcr_resource_len(np, 0));
174 lp->dma_in = temac_dma_dcr_in;
175 lp->dma_out = temac_dma_dcr_out;
176 dev_dbg(&op->dev, "DCR base: %x\n", dcrs);
179 /* no DCR in the device tree, indicate a failure */
186 * temac_dcr_setup - This is a stub for when DCR is not supported,
187 * such as with MicroBlaze
189 static int temac_dcr_setup(struct temac_local *lp, struct platform_device *op,
190 struct device_node *np)
198 * * temac_dma_bd_release - Release buffer descriptor rings
200 static void temac_dma_bd_release(struct net_device *ndev)
202 struct temac_local *lp = netdev_priv(ndev);
205 for (i = 0; i < RX_BD_NUM; i++) {
209 dma_unmap_single(ndev->dev.parent, lp->rx_bd_v[i].phys,
210 XTE_MAX_JUMBO_FRAME_SIZE, DMA_FROM_DEVICE);
211 dev_kfree_skb(lp->rx_skb[i]);
215 dma_free_coherent(ndev->dev.parent,
216 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
217 lp->rx_bd_v, lp->rx_bd_p);
219 dma_free_coherent(ndev->dev.parent,
220 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
221 lp->tx_bd_v, lp->tx_bd_p);
227 * temac_dma_bd_init - Setup buffer descriptor rings
229 static int temac_dma_bd_init(struct net_device *ndev)
231 struct temac_local *lp = netdev_priv(ndev);
235 lp->rx_skb = kzalloc(sizeof(*lp->rx_skb) * RX_BD_NUM, GFP_KERNEL);
238 "can't allocate memory for DMA RX buffer\n");
241 /* allocate the tx and rx ring buffer descriptors. */
242 /* returns a virtual address and a physical address. */
243 lp->tx_bd_v = dma_alloc_coherent(ndev->dev.parent,
244 sizeof(*lp->tx_bd_v) * TX_BD_NUM,
245 &lp->tx_bd_p, GFP_KERNEL);
248 "unable to allocate DMA TX buffer descriptors");
251 lp->rx_bd_v = dma_alloc_coherent(ndev->dev.parent,
252 sizeof(*lp->rx_bd_v) * RX_BD_NUM,
253 &lp->rx_bd_p, GFP_KERNEL);
256 "unable to allocate DMA RX buffer descriptors");
260 memset(lp->tx_bd_v, 0, sizeof(*lp->tx_bd_v) * TX_BD_NUM);
261 for (i = 0; i < TX_BD_NUM; i++) {
262 lp->tx_bd_v[i].next = lp->tx_bd_p +
263 sizeof(*lp->tx_bd_v) * ((i + 1) % TX_BD_NUM);
266 memset(lp->rx_bd_v, 0, sizeof(*lp->rx_bd_v) * RX_BD_NUM);
267 for (i = 0; i < RX_BD_NUM; i++) {
268 lp->rx_bd_v[i].next = lp->rx_bd_p +
269 sizeof(*lp->rx_bd_v) * ((i + 1) % RX_BD_NUM);
271 skb = netdev_alloc_skb_ip_align(ndev,
272 XTE_MAX_JUMBO_FRAME_SIZE);
275 dev_err(&ndev->dev, "alloc_skb error %d\n", i);
279 /* returns physical address of skb->data */
280 lp->rx_bd_v[i].phys = dma_map_single(ndev->dev.parent,
282 XTE_MAX_JUMBO_FRAME_SIZE,
284 lp->rx_bd_v[i].len = XTE_MAX_JUMBO_FRAME_SIZE;
285 lp->rx_bd_v[i].app0 = STS_CTRL_APP0_IRQONEND;
288 lp->dma_out(lp, TX_CHNL_CTRL, 0x10220400 |
290 CHNL_CTRL_IRQ_DLY_EN |
291 CHNL_CTRL_IRQ_COAL_EN);
294 lp->dma_out(lp, RX_CHNL_CTRL, 0xff070000 |
296 CHNL_CTRL_IRQ_DLY_EN |
297 CHNL_CTRL_IRQ_COAL_EN |
301 lp->dma_out(lp, RX_CURDESC_PTR, lp->rx_bd_p);
302 lp->dma_out(lp, RX_TAILDESC_PTR,
303 lp->rx_bd_p + (sizeof(*lp->rx_bd_v) * (RX_BD_NUM - 1)));
304 lp->dma_out(lp, TX_CURDESC_PTR, lp->tx_bd_p);
309 temac_dma_bd_release(ndev);
313 /* ---------------------------------------------------------------------
317 static int temac_set_mac_address(struct net_device *ndev, void *address)
319 struct temac_local *lp = netdev_priv(ndev);
322 memcpy(ndev->dev_addr, address, ETH_ALEN);
324 if (!is_valid_ether_addr(ndev->dev_addr))
325 random_ether_addr(ndev->dev_addr);
327 /* set up unicast MAC address filter set its mac address */
328 mutex_lock(&lp->indirect_mutex);
329 temac_indirect_out32(lp, XTE_UAW0_OFFSET,
330 (ndev->dev_addr[0]) |
331 (ndev->dev_addr[1] << 8) |
332 (ndev->dev_addr[2] << 16) |
333 (ndev->dev_addr[3] << 24));
334 /* There are reserved bits in EUAW1
335 * so don't affect them Set MAC bits [47:32] in EUAW1 */
336 temac_indirect_out32(lp, XTE_UAW1_OFFSET,
337 (ndev->dev_addr[4] & 0x000000ff) |
338 (ndev->dev_addr[5] << 8));
339 mutex_unlock(&lp->indirect_mutex);
344 static int netdev_set_mac_address(struct net_device *ndev, void *p)
346 struct sockaddr *addr = p;
348 return temac_set_mac_address(ndev, addr->sa_data);
351 static void temac_set_multicast_list(struct net_device *ndev)
353 struct temac_local *lp = netdev_priv(ndev);
354 u32 multi_addr_msw, multi_addr_lsw, val;
357 mutex_lock(&lp->indirect_mutex);
358 if (ndev->flags & (IFF_ALLMULTI | IFF_PROMISC) ||
359 netdev_mc_count(ndev) > MULTICAST_CAM_TABLE_NUM) {
361 * We must make the kernel realise we had to move
362 * into promisc mode or we start all out war on
363 * the cable. If it was a promisc request the
364 * flag is already set. If not we assert it.
366 ndev->flags |= IFF_PROMISC;
367 temac_indirect_out32(lp, XTE_AFM_OFFSET, XTE_AFM_EPPRM_MASK);
368 dev_info(&ndev->dev, "Promiscuous mode enabled.\n");
369 } else if (!netdev_mc_empty(ndev)) {
370 struct netdev_hw_addr *ha;
373 netdev_for_each_mc_addr(ha, ndev) {
374 if (i >= MULTICAST_CAM_TABLE_NUM)
376 multi_addr_msw = ((ha->addr[3] << 24) |
377 (ha->addr[2] << 16) |
380 temac_indirect_out32(lp, XTE_MAW0_OFFSET,
382 multi_addr_lsw = ((ha->addr[5] << 8) |
383 (ha->addr[4]) | (i << 16));
384 temac_indirect_out32(lp, XTE_MAW1_OFFSET,
389 val = temac_indirect_in32(lp, XTE_AFM_OFFSET);
390 temac_indirect_out32(lp, XTE_AFM_OFFSET,
391 val & ~XTE_AFM_EPPRM_MASK);
392 temac_indirect_out32(lp, XTE_MAW0_OFFSET, 0);
393 temac_indirect_out32(lp, XTE_MAW1_OFFSET, 0);
394 dev_info(&ndev->dev, "Promiscuous mode disabled.\n");
396 mutex_unlock(&lp->indirect_mutex);
399 struct temac_option {
405 } temac_options[] = {
406 /* Turn on jumbo packet support for both Rx and Tx */
408 .opt = XTE_OPTION_JUMBO,
409 .reg = XTE_TXC_OFFSET,
410 .m_or = XTE_TXC_TXJMBO_MASK,
413 .opt = XTE_OPTION_JUMBO,
414 .reg = XTE_RXC1_OFFSET,
415 .m_or =XTE_RXC1_RXJMBO_MASK,
417 /* Turn on VLAN packet support for both Rx and Tx */
419 .opt = XTE_OPTION_VLAN,
420 .reg = XTE_TXC_OFFSET,
421 .m_or =XTE_TXC_TXVLAN_MASK,
424 .opt = XTE_OPTION_VLAN,
425 .reg = XTE_RXC1_OFFSET,
426 .m_or =XTE_RXC1_RXVLAN_MASK,
428 /* Turn on FCS stripping on receive packets */
430 .opt = XTE_OPTION_FCS_STRIP,
431 .reg = XTE_RXC1_OFFSET,
432 .m_or =XTE_RXC1_RXFCS_MASK,
434 /* Turn on FCS insertion on transmit packets */
436 .opt = XTE_OPTION_FCS_INSERT,
437 .reg = XTE_TXC_OFFSET,
438 .m_or =XTE_TXC_TXFCS_MASK,
440 /* Turn on length/type field checking on receive packets */
442 .opt = XTE_OPTION_LENTYPE_ERR,
443 .reg = XTE_RXC1_OFFSET,
444 .m_or =XTE_RXC1_RXLT_MASK,
446 /* Turn on flow control */
448 .opt = XTE_OPTION_FLOW_CONTROL,
449 .reg = XTE_FCC_OFFSET,
450 .m_or =XTE_FCC_RXFLO_MASK,
452 /* Turn on flow control */
454 .opt = XTE_OPTION_FLOW_CONTROL,
455 .reg = XTE_FCC_OFFSET,
456 .m_or =XTE_FCC_TXFLO_MASK,
458 /* Turn on promiscuous frame filtering (all frames are received ) */
460 .opt = XTE_OPTION_PROMISC,
461 .reg = XTE_AFM_OFFSET,
462 .m_or =XTE_AFM_EPPRM_MASK,
464 /* Enable transmitter if not already enabled */
466 .opt = XTE_OPTION_TXEN,
467 .reg = XTE_TXC_OFFSET,
468 .m_or =XTE_TXC_TXEN_MASK,
470 /* Enable receiver? */
472 .opt = XTE_OPTION_RXEN,
473 .reg = XTE_RXC1_OFFSET,
474 .m_or =XTE_RXC1_RXEN_MASK,
482 static u32 temac_setoptions(struct net_device *ndev, u32 options)
484 struct temac_local *lp = netdev_priv(ndev);
485 struct temac_option *tp = &temac_options[0];
488 mutex_lock(&lp->indirect_mutex);
490 reg = temac_indirect_in32(lp, tp->reg) & ~tp->m_or;
491 if (options & tp->opt)
493 temac_indirect_out32(lp, tp->reg, reg);
496 lp->options |= options;
497 mutex_unlock(&lp->indirect_mutex);
502 /* Initialize temac */
503 static void temac_device_reset(struct net_device *ndev)
505 struct temac_local *lp = netdev_priv(ndev);
509 /* Perform a software reset */
511 /* 0x300 host enable bit ? */
512 /* reset PHY through control register ?:1 */
514 dev_dbg(&ndev->dev, "%s()\n", __func__);
516 mutex_lock(&lp->indirect_mutex);
517 /* Reset the receiver and wait for it to finish reset */
518 temac_indirect_out32(lp, XTE_RXC1_OFFSET, XTE_RXC1_RXRST_MASK);
520 while (temac_indirect_in32(lp, XTE_RXC1_OFFSET) & XTE_RXC1_RXRST_MASK) {
522 if (--timeout == 0) {
524 "temac_device_reset RX reset timeout!!\n");
529 /* Reset the transmitter and wait for it to finish reset */
530 temac_indirect_out32(lp, XTE_TXC_OFFSET, XTE_TXC_TXRST_MASK);
532 while (temac_indirect_in32(lp, XTE_TXC_OFFSET) & XTE_TXC_TXRST_MASK) {
534 if (--timeout == 0) {
536 "temac_device_reset TX reset timeout!!\n");
541 /* Disable the receiver */
542 val = temac_indirect_in32(lp, XTE_RXC1_OFFSET);
543 temac_indirect_out32(lp, XTE_RXC1_OFFSET, val & ~XTE_RXC1_RXEN_MASK);
545 /* Reset Local Link (DMA) */
546 lp->dma_out(lp, DMA_CONTROL_REG, DMA_CONTROL_RST);
548 while (lp->dma_in(lp, DMA_CONTROL_REG) & DMA_CONTROL_RST) {
550 if (--timeout == 0) {
552 "temac_device_reset DMA reset timeout!!\n");
556 lp->dma_out(lp, DMA_CONTROL_REG, DMA_TAIL_ENABLE);
558 if (temac_dma_bd_init(ndev)) {
560 "temac_device_reset descriptor allocation failed\n");
563 temac_indirect_out32(lp, XTE_RXC0_OFFSET, 0);
564 temac_indirect_out32(lp, XTE_RXC1_OFFSET, 0);
565 temac_indirect_out32(lp, XTE_TXC_OFFSET, 0);
566 temac_indirect_out32(lp, XTE_FCC_OFFSET, XTE_FCC_RXFLO_MASK);
568 mutex_unlock(&lp->indirect_mutex);
570 /* Sync default options with HW
571 * but leave receiver and transmitter disabled. */
572 temac_setoptions(ndev,
573 lp->options & ~(XTE_OPTION_TXEN | XTE_OPTION_RXEN));
575 temac_set_mac_address(ndev, NULL);
577 /* Set address filter table */
578 temac_set_multicast_list(ndev);
579 if (temac_setoptions(ndev, lp->options))
580 dev_err(&ndev->dev, "Error setting TEMAC options\n");
582 /* Init Driver variable */
583 ndev->trans_start = jiffies; /* prevent tx timeout */
586 void temac_adjust_link(struct net_device *ndev)
588 struct temac_local *lp = netdev_priv(ndev);
589 struct phy_device *phy = lp->phy_dev;
593 /* hash together the state values to decide if something has changed */
594 link_state = phy->speed | (phy->duplex << 1) | phy->link;
596 mutex_lock(&lp->indirect_mutex);
597 if (lp->last_link != link_state) {
598 mii_speed = temac_indirect_in32(lp, XTE_EMCFG_OFFSET);
599 mii_speed &= ~XTE_EMCFG_LINKSPD_MASK;
601 switch (phy->speed) {
602 case SPEED_1000: mii_speed |= XTE_EMCFG_LINKSPD_1000; break;
603 case SPEED_100: mii_speed |= XTE_EMCFG_LINKSPD_100; break;
604 case SPEED_10: mii_speed |= XTE_EMCFG_LINKSPD_10; break;
607 /* Write new speed setting out to TEMAC */
608 temac_indirect_out32(lp, XTE_EMCFG_OFFSET, mii_speed);
609 lp->last_link = link_state;
610 phy_print_status(phy);
612 mutex_unlock(&lp->indirect_mutex);
615 static void temac_start_xmit_done(struct net_device *ndev)
617 struct temac_local *lp = netdev_priv(ndev);
618 struct cdmac_bd *cur_p;
619 unsigned int stat = 0;
621 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
624 while (stat & STS_CTRL_APP0_CMPLT) {
625 dma_unmap_single(ndev->dev.parent, cur_p->phys, cur_p->len,
628 dev_kfree_skb_irq((struct sk_buff *)cur_p->app4);
635 ndev->stats.tx_packets++;
636 ndev->stats.tx_bytes += cur_p->len;
639 if (lp->tx_bd_ci >= TX_BD_NUM)
642 cur_p = &lp->tx_bd_v[lp->tx_bd_ci];
646 netif_wake_queue(ndev);
649 static inline int temac_check_tx_bd_space(struct temac_local *lp, int num_frag)
651 struct cdmac_bd *cur_p;
654 tail = lp->tx_bd_tail;
655 cur_p = &lp->tx_bd_v[tail];
659 return NETDEV_TX_BUSY;
662 if (tail >= TX_BD_NUM)
665 cur_p = &lp->tx_bd_v[tail];
667 } while (num_frag >= 0);
672 static int temac_start_xmit(struct sk_buff *skb, struct net_device *ndev)
674 struct temac_local *lp = netdev_priv(ndev);
675 struct cdmac_bd *cur_p;
676 dma_addr_t start_p, tail_p;
678 unsigned long num_frag;
681 num_frag = skb_shinfo(skb)->nr_frags;
682 frag = &skb_shinfo(skb)->frags[0];
683 start_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
684 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
686 if (temac_check_tx_bd_space(lp, num_frag)) {
687 if (!netif_queue_stopped(ndev)) {
688 netif_stop_queue(ndev);
689 return NETDEV_TX_BUSY;
691 return NETDEV_TX_BUSY;
695 if (skb->ip_summed == CHECKSUM_PARTIAL) {
696 unsigned int csum_start_off = skb_checksum_start_offset(skb);
697 unsigned int csum_index_off = csum_start_off + skb->csum_offset;
699 cur_p->app0 |= 1; /* TX Checksum Enabled */
700 cur_p->app1 = (csum_start_off << 16) | csum_index_off;
701 cur_p->app2 = 0; /* initial checksum seed */
704 cur_p->app0 |= STS_CTRL_APP0_SOP;
705 cur_p->len = skb_headlen(skb);
706 cur_p->phys = dma_map_single(ndev->dev.parent, skb->data, skb->len,
708 cur_p->app4 = (unsigned long)skb;
710 for (ii = 0; ii < num_frag; ii++) {
712 if (lp->tx_bd_tail >= TX_BD_NUM)
715 cur_p = &lp->tx_bd_v[lp->tx_bd_tail];
716 cur_p->phys = dma_map_single(ndev->dev.parent,
717 (void *)page_address(frag->page) +
719 frag->size, DMA_TO_DEVICE);
720 cur_p->len = frag->size;
724 cur_p->app0 |= STS_CTRL_APP0_EOP;
726 tail_p = lp->tx_bd_p + sizeof(*lp->tx_bd_v) * lp->tx_bd_tail;
728 if (lp->tx_bd_tail >= TX_BD_NUM)
731 skb_tx_timestamp(skb);
733 /* Kick off the transfer */
734 lp->dma_out(lp, TX_TAILDESC_PTR, tail_p); /* DMA start */
740 static void ll_temac_recv(struct net_device *ndev)
742 struct temac_local *lp = netdev_priv(ndev);
743 struct sk_buff *skb, *new_skb;
745 struct cdmac_bd *cur_p;
750 spin_lock_irqsave(&lp->rx_lock, flags);
752 tail_p = lp->rx_bd_p + sizeof(*lp->rx_bd_v) * lp->rx_bd_ci;
753 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
755 bdstat = cur_p->app0;
756 while ((bdstat & STS_CTRL_APP0_CMPLT)) {
758 skb = lp->rx_skb[lp->rx_bd_ci];
759 length = cur_p->app4 & 0x3FFF;
761 dma_unmap_single(ndev->dev.parent, cur_p->phys, length,
764 skb_put(skb, length);
766 skb->protocol = eth_type_trans(skb, ndev);
767 skb_checksum_none_assert(skb);
769 /* if we're doing rx csum offload, set it up */
770 if (((lp->temac_features & TEMAC_FEATURE_RX_CSUM) != 0) &&
771 (skb->protocol == __constant_htons(ETH_P_IP)) &&
774 skb->csum = cur_p->app3 & 0xFFFF;
775 skb->ip_summed = CHECKSUM_COMPLETE;
778 if (!skb_defer_rx_timestamp(skb))
781 ndev->stats.rx_packets++;
782 ndev->stats.rx_bytes += length;
784 new_skb = netdev_alloc_skb_ip_align(ndev,
785 XTE_MAX_JUMBO_FRAME_SIZE);
788 dev_err(&ndev->dev, "no memory for new sk_buff\n");
789 spin_unlock_irqrestore(&lp->rx_lock, flags);
793 cur_p->app0 = STS_CTRL_APP0_IRQONEND;
794 cur_p->phys = dma_map_single(ndev->dev.parent, new_skb->data,
795 XTE_MAX_JUMBO_FRAME_SIZE,
797 cur_p->len = XTE_MAX_JUMBO_FRAME_SIZE;
798 lp->rx_skb[lp->rx_bd_ci] = new_skb;
801 if (lp->rx_bd_ci >= RX_BD_NUM)
804 cur_p = &lp->rx_bd_v[lp->rx_bd_ci];
805 bdstat = cur_p->app0;
807 lp->dma_out(lp, RX_TAILDESC_PTR, tail_p);
809 spin_unlock_irqrestore(&lp->rx_lock, flags);
812 static irqreturn_t ll_temac_tx_irq(int irq, void *_ndev)
814 struct net_device *ndev = _ndev;
815 struct temac_local *lp = netdev_priv(ndev);
818 status = lp->dma_in(lp, TX_IRQ_REG);
819 lp->dma_out(lp, TX_IRQ_REG, status);
821 if (status & (IRQ_COAL | IRQ_DLY))
822 temac_start_xmit_done(lp->ndev);
824 dev_err(&ndev->dev, "DMA error 0x%x\n", status);
829 static irqreturn_t ll_temac_rx_irq(int irq, void *_ndev)
831 struct net_device *ndev = _ndev;
832 struct temac_local *lp = netdev_priv(ndev);
835 /* Read and clear the status registers */
836 status = lp->dma_in(lp, RX_IRQ_REG);
837 lp->dma_out(lp, RX_IRQ_REG, status);
839 if (status & (IRQ_COAL | IRQ_DLY))
840 ll_temac_recv(lp->ndev);
845 static int temac_open(struct net_device *ndev)
847 struct temac_local *lp = netdev_priv(ndev);
850 dev_dbg(&ndev->dev, "temac_open()\n");
853 lp->phy_dev = of_phy_connect(lp->ndev, lp->phy_node,
854 temac_adjust_link, 0, 0);
856 dev_err(lp->dev, "of_phy_connect() failed\n");
860 phy_start(lp->phy_dev);
863 rc = request_irq(lp->tx_irq, ll_temac_tx_irq, 0, ndev->name, ndev);
866 rc = request_irq(lp->rx_irq, ll_temac_rx_irq, 0, ndev->name, ndev);
870 temac_device_reset(ndev);
874 free_irq(lp->tx_irq, ndev);
877 phy_disconnect(lp->phy_dev);
879 dev_err(lp->dev, "request_irq() failed\n");
883 static int temac_stop(struct net_device *ndev)
885 struct temac_local *lp = netdev_priv(ndev);
887 dev_dbg(&ndev->dev, "temac_close()\n");
889 free_irq(lp->tx_irq, ndev);
890 free_irq(lp->rx_irq, ndev);
893 phy_disconnect(lp->phy_dev);
896 temac_dma_bd_release(ndev);
901 #ifdef CONFIG_NET_POLL_CONTROLLER
903 temac_poll_controller(struct net_device *ndev)
905 struct temac_local *lp = netdev_priv(ndev);
907 disable_irq(lp->tx_irq);
908 disable_irq(lp->rx_irq);
910 ll_temac_rx_irq(lp->tx_irq, ndev);
911 ll_temac_tx_irq(lp->rx_irq, ndev);
913 enable_irq(lp->tx_irq);
914 enable_irq(lp->rx_irq);
918 static const struct net_device_ops temac_netdev_ops = {
919 .ndo_open = temac_open,
920 .ndo_stop = temac_stop,
921 .ndo_start_xmit = temac_start_xmit,
922 .ndo_set_mac_address = netdev_set_mac_address,
923 .ndo_validate_addr = eth_validate_addr,
924 //.ndo_set_multicast_list = temac_set_multicast_list,
925 #ifdef CONFIG_NET_POLL_CONTROLLER
926 .ndo_poll_controller = temac_poll_controller,
930 /* ---------------------------------------------------------------------
931 * SYSFS device attributes
933 static ssize_t temac_show_llink_regs(struct device *dev,
934 struct device_attribute *attr, char *buf)
936 struct net_device *ndev = dev_get_drvdata(dev);
937 struct temac_local *lp = netdev_priv(ndev);
940 for (i = 0; i < 0x11; i++)
941 len += sprintf(buf + len, "%.8x%s", lp->dma_in(lp, i),
942 (i % 8) == 7 ? "\n" : " ");
943 len += sprintf(buf + len, "\n");
948 static DEVICE_ATTR(llink_regs, 0440, temac_show_llink_regs, NULL);
950 static struct attribute *temac_device_attrs[] = {
951 &dev_attr_llink_regs.attr,
955 static const struct attribute_group temac_attr_group = {
956 .attrs = temac_device_attrs,
959 static int __devinit temac_of_probe(struct platform_device *op)
961 struct device_node *np;
962 struct temac_local *lp;
963 struct net_device *ndev;
968 /* Init network device structure */
969 ndev = alloc_etherdev(sizeof(*lp));
971 dev_err(&op->dev, "could not allocate device.\n");
975 dev_set_drvdata(&op->dev, ndev);
976 SET_NETDEV_DEV(ndev, &op->dev);
977 ndev->flags &= ~IFF_MULTICAST; /* clear multicast */
978 ndev->features = NETIF_F_SG | NETIF_F_FRAGLIST;
979 ndev->netdev_ops = &temac_netdev_ops;
981 ndev->features |= NETIF_F_IP_CSUM; /* Can checksum TCP/UDP over IPv4. */
982 ndev->features |= NETIF_F_HW_CSUM; /* Can checksum all the packets. */
983 ndev->features |= NETIF_F_IPV6_CSUM; /* Can checksum IPV6 TCP/UDP */
984 ndev->features |= NETIF_F_HIGHDMA; /* Can DMA to high memory. */
985 ndev->features |= NETIF_F_HW_VLAN_TX; /* Transmit VLAN hw accel */
986 ndev->features |= NETIF_F_HW_VLAN_RX; /* Receive VLAN hw acceleration */
987 ndev->features |= NETIF_F_HW_VLAN_FILTER; /* Receive VLAN filtering */
988 ndev->features |= NETIF_F_VLAN_CHALLENGED; /* cannot handle VLAN pkts */
989 ndev->features |= NETIF_F_GSO; /* Enable software GSO. */
990 ndev->features |= NETIF_F_MULTI_QUEUE; /* Has multiple TX/RX queues */
991 ndev->features |= NETIF_F_LRO; /* large receive offload */
994 /* setup temac private info structure */
995 lp = netdev_priv(ndev);
998 lp->options = XTE_OPTION_DEFAULTS;
999 spin_lock_init(&lp->rx_lock);
1000 mutex_init(&lp->indirect_mutex);
1002 /* map device registers */
1003 lp->regs = of_iomap(op->dev.of_node, 0);
1005 dev_err(&op->dev, "could not map temac regs.\n");
1009 /* Setup checksum offload, but default to off if not specified */
1010 lp->temac_features = 0;
1011 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,txcsum", NULL);
1012 if (p && be32_to_cpu(*p)) {
1013 lp->temac_features |= TEMAC_FEATURE_TX_CSUM;
1014 /* Can checksum TCP/UDP over IPv4. */
1015 ndev->features |= NETIF_F_IP_CSUM;
1017 p = (__be32 *)of_get_property(op->dev.of_node, "xlnx,rxcsum", NULL);
1018 if (p && be32_to_cpu(*p))
1019 lp->temac_features |= TEMAC_FEATURE_RX_CSUM;
1021 /* Find the DMA node, map the DMA registers, and decode the DMA IRQs */
1022 np = of_parse_phandle(op->dev.of_node, "llink-connected", 0);
1024 dev_err(&op->dev, "could not find DMA node\n");
1028 /* Setup the DMA register accesses, could be DCR or memory mapped */
1029 if (temac_dcr_setup(lp, op, np)) {
1031 /* no DCR in the device tree, try non-DCR */
1032 lp->sdma_regs = of_iomap(np, 0);
1033 if (lp->sdma_regs) {
1034 lp->dma_in = temac_dma_in32;
1035 lp->dma_out = temac_dma_out32;
1036 dev_dbg(&op->dev, "MEM base: %p\n", lp->sdma_regs);
1038 dev_err(&op->dev, "unable to map DMA registers\n");
1044 lp->rx_irq = irq_of_parse_and_map(np, 0);
1045 lp->tx_irq = irq_of_parse_and_map(np, 1);
1047 of_node_put(np); /* Finished with the DMA node; drop the reference */
1049 if ((lp->rx_irq == NO_IRQ) || (lp->tx_irq == NO_IRQ)) {
1050 dev_err(&op->dev, "could not determine irqs\n");
1056 /* Retrieve the MAC address */
1057 addr = of_get_property(op->dev.of_node, "local-mac-address", &size);
1058 if ((!addr) || (size != 6)) {
1059 dev_err(&op->dev, "could not find MAC address\n");
1063 temac_set_mac_address(ndev, (void *)addr);
1065 rc = temac_mdio_setup(lp, op->dev.of_node);
1067 dev_warn(&op->dev, "error registering MDIO bus\n");
1069 lp->phy_node = of_parse_phandle(op->dev.of_node, "phy-handle", 0);
1071 dev_dbg(lp->dev, "using PHY node %s (%p)\n", np->full_name, np);
1073 /* Add the device attributes */
1074 rc = sysfs_create_group(&lp->dev->kobj, &temac_attr_group);
1076 dev_err(lp->dev, "Error creating sysfs files\n");
1080 rc = register_netdev(lp->ndev);
1082 dev_err(lp->dev, "register_netdev() error (%i)\n", rc);
1083 goto err_register_ndev;
1089 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1092 iounmap(lp->sdma_regs);
1101 static int __devexit temac_of_remove(struct platform_device *op)
1103 struct net_device *ndev = dev_get_drvdata(&op->dev);
1104 struct temac_local *lp = netdev_priv(ndev);
1106 temac_mdio_teardown(lp);
1107 unregister_netdev(ndev);
1108 sysfs_remove_group(&lp->dev->kobj, &temac_attr_group);
1110 of_node_put(lp->phy_node);
1111 lp->phy_node = NULL;
1112 dev_set_drvdata(&op->dev, NULL);
1115 iounmap(lp->sdma_regs);
1120 static struct of_device_id temac_of_match[] __devinitdata = {
1121 { .compatible = "xlnx,xps-ll-temac-1.01.b", },
1122 { .compatible = "xlnx,xps-ll-temac-2.00.a", },
1123 { .compatible = "xlnx,xps-ll-temac-2.02.a", },
1124 { .compatible = "xlnx,xps-ll-temac-2.03.a", },
1127 MODULE_DEVICE_TABLE(of, temac_of_match);
1129 static struct platform_driver temac_of_driver = {
1130 .probe = temac_of_probe,
1131 .remove = __devexit_p(temac_of_remove),
1133 .owner = THIS_MODULE,
1134 .name = "xilinx_temac",
1135 .of_match_table = temac_of_match,
1139 static int __init temac_init(void)
1141 return platform_driver_register(&temac_of_driver);
1143 module_init(temac_init);
1145 static void __exit temac_exit(void)
1147 platform_driver_unregister(&temac_of_driver);
1149 module_exit(temac_exit);
1151 MODULE_DESCRIPTION("Xilinx LL_TEMAC Ethernet driver");
1152 MODULE_AUTHOR("Yoshio Kashiwagi");
1153 MODULE_LICENSE("GPL");