drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2009 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/ip.h>
  36 #include <linux/tcp.h>
  37 #include <linux/pkt_sched.h>
  38 #include <linux/ipv6.h>
  39 #include <net/checksum.h>
  40 #include <net/ip6_checksum.h>
  41 #include <linux/ethtool.h>
  42 #include <linux/if_vlan.h>
  43 #include <scsi/fc/fc_fcoe.h>
  44
  45 #include "ixgbe.h"
  46 #include "ixgbe_common.h"
  47
  48 char ixgbe_driver_name[] = "ixgbe";
  49 static const char ixgbe_driver_string[] =
  50                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  51
  52 #define DRV_VERSION "2.0.37-k2"
  53 const char ixgbe_driver_version[] = DRV_VERSION;
  54 static char ixgbe_copyright[] = "Copyright (c) 1999-2009 Intel Corporation.";
  55
  56 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  57         [board_82598] = &ixgbe_82598_info,
  58         [board_82599] = &ixgbe_82599_info,
  59 };
  60
  61 /* ixgbe_pci_tbl - PCI Device ID Table
  62  *
  63  * Wildcard entries (PCI_ANY_ID) should come last
  64  * Last entry must be all 0s
  65  *
  66  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  67  *   Class, Class Mask, private data (not used) }
  68  */
  69 static struct pci_device_id ixgbe_pci_tbl[] = {
  70         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  71          board_82598 },
  72         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  73          board_82598 },
  74         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  75          board_82598 },
  76         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  77          board_82598 },
  78         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  79          board_82598 },
  80         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  81          board_82598 },
  82         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  83          board_82598 },
  84         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  85          board_82598 },
  86         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  87          board_82598 },
  88         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
  89          board_82598 },
  90         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
  91          board_82598 },
  92         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
  93          board_82598 },
  94         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
  95          board_82599 },
  96         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
  97          board_82599 },
  98         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
  99          board_82599 },
 100         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 101          board_82599 },
 102
 103         /* required last entry */
 104         {0, }
 105 };
 106 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 107
 108 #ifdef CONFIG_IXGBE_DCA
 109 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 110                             void *p);
 111 static struct notifier_block dca_notifier = {
 112         .notifier_call = ixgbe_notify_dca,
 113         .next          = NULL,
 114         .priority      = 0
 115 };
 116 #endif
 117
 118 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 119 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 120 MODULE_LICENSE("GPL");
 121 MODULE_VERSION(DRV_VERSION);
 122
 123 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 124
 125 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 126 {
 127         u32 ctrl_ext;
 128
 129         /* Let firmware take over control of h/w */
 130         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 131         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 132                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 133 }
 134
 135 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 136 {
 137         u32 ctrl_ext;
 138
 139         /* Let firmware know the driver has taken over */
 140         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 141         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 142                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 143 }
 144
 145 /*
 146  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 147  * @adapter: pointer to adapter struct
 148  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 149  * @queue: queue to map the corresponding interrupt to
 150  * @msix_vector: the vector to map to the corresponding queue
 151  *
 152  */
 153 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 154                            u8 queue, u8 msix_vector)
 155 {
 156         u32 ivar, index;
 157         struct ixgbe_hw *hw = &adapter->hw;
 158         switch (hw->mac.type) {
 159         case ixgbe_mac_82598EB:
 160                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 161                 if (direction == -1)
 162                         direction = 0;
 163                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 164                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 165                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 166                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 167                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 168                 break;
 169         case ixgbe_mac_82599EB:
 170                 if (direction == -1) {
 171                         /* other causes */
 172                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 173                         index = ((queue & 1) * 8);
 174                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 175                         ivar &= ~(0xFF << index);
 176                         ivar |= (msix_vector << index);
 177                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 178                         break;
 179                 } else {
 180                         /* tx or rx causes */
 181                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 182                         index = ((16 * (queue & 1)) + (8 * direction));
 183                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 184                         ivar &= ~(0xFF << index);
 185                         ivar |= (msix_vector << index);
 186                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 187                         break;
 188                 }
 189         default:
 190                 break;
 191         }
 192 }
 193
 194 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 195                                           u64 qmask)
 196 {
 197         u32 mask;
 198
 199         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 200                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 201                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 202         } else {
 203                 mask = (qmask & 0xFFFFFFFF);
 204                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 205                 mask = (qmask >> 32);
 206                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 207         }
 208 }
 209
 210 static void ixgbe_unmap_and_free_tx_resource(struct ixgbe_adapter *adapter,
 211                                              struct ixgbe_tx_buffer
 212                                              *tx_buffer_info)
 213 {
 214         tx_buffer_info->dma = 0;
 215         if (tx_buffer_info->skb) {
 216                 skb_dma_unmap(&adapter->pdev->dev, tx_buffer_info->skb,
 217                               DMA_TO_DEVICE);
 218                 dev_kfree_skb_any(tx_buffer_info->skb);
 219                 tx_buffer_info->skb = NULL;
 220         }
 221         tx_buffer_info->time_stamp = 0;
 222         /* tx_buffer_info must be completely set up in the transmit path */
 223 }
 224
 225 static inline bool ixgbe_check_tx_hang(struct ixgbe_adapter *adapter,
 226                                        struct ixgbe_ring *tx_ring,
 227                                        unsigned int eop)
 228 {
 229         struct ixgbe_hw *hw = &adapter->hw;
 230
 231         /* Detect a transmit hang in hardware, this serializes the
 232          * check with the clearing of time_stamp and movement of eop */
 233         adapter->detect_tx_hung = false;
 234         if (tx_ring->tx_buffer_info[eop].time_stamp &&
 235             time_after(jiffies, tx_ring->tx_buffer_info[eop].time_stamp + HZ) &&
 236             !(IXGBE_READ_REG(&adapter->hw, IXGBE_TFCS) & IXGBE_TFCS_TXOFF)) {
 237                 /* detected Tx unit hang */
 238                 union ixgbe_adv_tx_desc *tx_desc;
 239                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 240                 DPRINTK(DRV, ERR, "Detected Tx Unit Hang\n"
 241                         "  Tx Queue             <%d>\n"
 242                         "  TDH, TDT             <%x>, <%x>\n"
 243                         "  next_to_use          <%x>\n"
 244                         "  next_to_clean        <%x>\n"
 245                         "tx_buffer_info[next_to_clean]\n"
 246                         "  time_stamp           <%lx>\n"
 247                         "  jiffies              <%lx>\n",
 248                         tx_ring->queue_index,
 249                         IXGBE_READ_REG(hw, tx_ring->head),
 250                         IXGBE_READ_REG(hw, tx_ring->tail),
 251                         tx_ring->next_to_use, eop,
 252                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 253                 return true;
 254         }
 255
 256         return false;
 257 }
 258
 259 #define IXGBE_MAX_TXD_PWR       14
 260 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 261
 262 /* Tx Descriptors needed, worst case */
 263 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 264                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 265 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 266         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 267
 268 static void ixgbe_tx_timeout(struct net_device *netdev);
 269
 270 /**
 271  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 272  * @q_vector: structure containing interrupt and ring information
 273  * @tx_ring: tx ring to clean
 274  **/
 275 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 276                                struct ixgbe_ring *tx_ring)
 277 {
 278         struct ixgbe_adapter *adapter = q_vector->adapter;
 279         struct net_device *netdev = adapter->netdev;
 280         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 281         struct ixgbe_tx_buffer *tx_buffer_info;
 282         unsigned int i, eop, count = 0;
 283         unsigned int total_bytes = 0, total_packets = 0;
 284
 285         i = tx_ring->next_to_clean;
 286         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 287         eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 288
 289         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 290                (count < tx_ring->work_limit)) {
 291                 bool cleaned = false;
 292                 for ( ; !cleaned; count++) {
 293                         struct sk_buff *skb;
 294                         tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
 295                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 296                         cleaned = (i == eop);
 297                         skb = tx_buffer_info->skb;
 298
 299                         if (cleaned && skb) {
 300                                 unsigned int segs, bytecount;
 301                                 unsigned int hlen = skb_headlen(skb);
 302
 303                                 /* gso_segs is currently only valid for tcp */
 304                                 segs = skb_shinfo(skb)->gso_segs ?: 1;
 305 #ifdef IXGBE_FCOE
 306                                 /* adjust for FCoE Sequence Offload */
 307                                 if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
 308                                     && (skb->protocol == htons(ETH_P_FCOE)) &&
 309                                     skb_is_gso(skb)) {
 310                                         hlen = skb_transport_offset(skb) +
 311                                                 sizeof(struct fc_frame_header) +
 312                                                 sizeof(struct fcoe_crc_eof);
 313                                         segs = DIV_ROUND_UP(skb->len - hlen,
 314                                                 skb_shinfo(skb)->gso_size);
 315                                 }
 316 #endif /* IXGBE_FCOE */
 317                                 /* multiply data chunks by size of headers */
 318                                 bytecount = ((segs - 1) * hlen) + skb->len;
 319                                 total_packets += segs;
 320                                 total_bytes += bytecount;
 321                         }
 322
 323                         ixgbe_unmap_and_free_tx_resource(adapter,
 324                                                          tx_buffer_info);
 325
 326                         tx_desc->wb.status = 0;
 327
 328                         i++;
 329                         if (i == tx_ring->count)
 330                                 i = 0;
 331                 }
 332
 333                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 334                 eop_desc = IXGBE_TX_DESC_ADV(*tx_ring, eop);
 335         }
 336
 337         tx_ring->next_to_clean = i;
 338
 339 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 340         if (unlikely(count && netif_carrier_ok(netdev) &&
 341                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 342                 /* Make sure that anybody stopping the queue after this
 343                  * sees the new next_to_clean.
 344                  */
 345                 smp_mb();
 346                 if (__netif_subqueue_stopped(netdev, tx_ring->queue_index) &&
 347                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 348                         netif_wake_subqueue(netdev, tx_ring->queue_index);
 349                         ++adapter->restart_queue;
 350                 }
 351         }
 352
 353         if (adapter->detect_tx_hung) {
 354                 if (ixgbe_check_tx_hang(adapter, tx_ring, i)) {
 355                         /* schedule immediate reset if we believe we hung */
 356                         DPRINTK(PROBE, INFO,
 357                                 "tx hang %d detected, resetting adapter\n",
 358                                 adapter->tx_timeout_count + 1);
 359                         ixgbe_tx_timeout(adapter->netdev);
 360                 }
 361         }
 362
 363         /* re-arm the interrupt */
 364         if (count >= tx_ring->work_limit)
 365                 ixgbe_irq_rearm_queues(adapter, ((u64)1 << q_vector->v_idx));
 366
 367         tx_ring->total_bytes += total_bytes;
 368         tx_ring->total_packets += total_packets;
 369         tx_ring->stats.packets += total_packets;
 370         tx_ring->stats.bytes += total_bytes;
 371         adapter->net_stats.tx_bytes += total_bytes;
 372         adapter->net_stats.tx_packets += total_packets;
 373         return (count < tx_ring->work_limit);
 374 }
 375
 376 #ifdef CONFIG_IXGBE_DCA
 377 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 378                                 struct ixgbe_ring *rx_ring)
 379 {
 380         u32 rxctrl;
 381         int cpu = get_cpu();
 382         int q = rx_ring - adapter->rx_ring;
 383
 384         if (rx_ring->cpu != cpu) {
 385                 rxctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q));
 386                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 387                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 388                         rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 389                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 390                         rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 391                         rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 392                                    IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 393                 }
 394                 rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 395                 rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 396                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 397                 rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_WRO_EN |
 398                             IXGBE_DCA_RXCTRL_DESC_HSRO_EN);
 399                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_RXCTRL(q), rxctrl);
 400                 rx_ring->cpu = cpu;
 401         }
 402         put_cpu();
 403 }
 404
 405 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 406                                 struct ixgbe_ring *tx_ring)
 407 {
 408         u32 txctrl;
 409         int cpu = get_cpu();
 410         int q = tx_ring - adapter->tx_ring;
 411
 412         if (tx_ring->cpu != cpu) {
 413                 txctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q));
 414                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
 415                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 416                         txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 417                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
 418                         txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 419                         txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 420                                    IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 421                 }
 422                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 423                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_TXCTRL(q), txctrl);
 424                 tx_ring->cpu = cpu;
 425         }
 426         put_cpu();
 427 }
 428
 429 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 430 {
 431         int i;
 432
 433         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 434                 return;
 435
 436         /* always use CB2 mode, difference is masked in the CB driver */
 437         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
 438
 439         for (i = 0; i < adapter->num_tx_queues; i++) {
 440                 adapter->tx_ring[i].cpu = -1;
 441                 ixgbe_update_tx_dca(adapter, &adapter->tx_ring[i]);
 442         }
 443         for (i = 0; i < adapter->num_rx_queues; i++) {
 444                 adapter->rx_ring[i].cpu = -1;
 445                 ixgbe_update_rx_dca(adapter, &adapter->rx_ring[i]);
 446         }
 447 }
 448
 449 static int __ixgbe_notify_dca(struct device *dev, void *data)
 450 {
 451         struct net_device *netdev = dev_get_drvdata(dev);
 452         struct ixgbe_adapter *adapter = netdev_priv(netdev);
 453         unsigned long event = *(unsigned long *)data;
 454
 455         switch (event) {
 456         case DCA_PROVIDER_ADD:
 457                 /* if we're already enabled, don't do it again */
 458                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
 459                         break;
 460                 if (dca_add_requester(dev) == 0) {
 461                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
 462                         ixgbe_setup_dca(adapter);
 463                         break;
 464                 }
 465                 /* Fall Through since DCA is disabled. */
 466         case DCA_PROVIDER_REMOVE:
 467                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
 468                         dca_remove_requester(dev);
 469                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
 470                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
 471                 }
 472                 break;
 473         }
 474
 475         return 0;
 476 }
 477
 478 #endif /* CONFIG_IXGBE_DCA */
 479 /**
 480  * ixgbe_receive_skb - Send a completed packet up the stack
 481  * @adapter: board private structure
 482  * @skb: packet to send up
 483  * @status: hardware indication of status of receive
 484  * @rx_ring: rx descriptor ring (for a specific queue) to setup
 485  * @rx_desc: rx descriptor
 486  **/
 487 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
 488                               struct sk_buff *skb, u8 status,
 489                               struct ixgbe_ring *ring,
 490                               union ixgbe_adv_rx_desc *rx_desc)
 491 {
 492         struct ixgbe_adapter *adapter = q_vector->adapter;
 493         struct napi_struct *napi = &q_vector->napi;
 494         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
 495         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
 496
 497         skb_record_rx_queue(skb, ring->queue_index);
 498         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL)) {
 499                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 500                         vlan_gro_receive(napi, adapter->vlgrp, tag, skb);
 501                 else
 502                         napi_gro_receive(napi, skb);
 503         } else {
 504                 if (adapter->vlgrp && is_vlan && (tag & VLAN_VID_MASK))
 505                         vlan_hwaccel_rx(skb, adapter->vlgrp, tag);
 506                 else
 507                         netif_rx(skb);
 508         }
 509 }
 510
 511 /**
 512  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
 513  * @adapter: address of board private structure
 514  * @status_err: hardware indication of status of receive
 515  * @skb: skb currently being received and modified
 516  **/
 517 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
 518                                      union ixgbe_adv_rx_desc *rx_desc,
 519                                      struct sk_buff *skb)
 520 {
 521         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
 522
 523         skb->ip_summed = CHECKSUM_NONE;
 524
 525         /* Rx csum disabled */
 526         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
 527                 return;
 528
 529         /* if IP and error */
 530         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
 531             (status_err & IXGBE_RXDADV_ERR_IPE)) {
 532                 adapter->hw_csum_rx_error++;
 533                 return;
 534         }
 535
 536         if (!(status_err & IXGBE_RXD_STAT_L4CS))
 537                 return;
 538
 539         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
 540                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 541
 542                 /*
 543                  * 82599 errata, UDP frames with a 0 checksum can be marked as
 544                  * checksum errors.
 545                  */
 546                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
 547                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
 548                         return;
 549
 550                 adapter->hw_csum_rx_error++;
 551                 return;
 552         }
 553
 554         /* It must be a TCP or UDP packet with a valid checksum */
 555         skb->ip_summed = CHECKSUM_UNNECESSARY;
 556         adapter->hw_csum_rx_good++;
 557 }
 558
 559 static inline void ixgbe_release_rx_desc(struct ixgbe_hw *hw,
 560                                          struct ixgbe_ring *rx_ring, u32 val)
 561 {
 562         /*
 563          * Force memory writes to complete before letting h/w
 564          * know there are new descriptors to fetch.  (Only
 565          * applicable for weak-ordered memory model archs,
 566          * such as IA-64).
 567          */
 568         wmb();
 569         IXGBE_WRITE_REG(hw, IXGBE_RDT(rx_ring->reg_idx), val);
 570 }
 571
 572 /**
 573  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
 574  * @adapter: address of board private structure
 575  **/
 576 static void ixgbe_alloc_rx_buffers(struct ixgbe_adapter *adapter,
 577                                    struct ixgbe_ring *rx_ring,
 578                                    int cleaned_count)
 579 {
 580         struct pci_dev *pdev = adapter->pdev;
 581         union ixgbe_adv_rx_desc *rx_desc;
 582         struct ixgbe_rx_buffer *bi;
 583         unsigned int i;
 584
 585         i = rx_ring->next_to_use;
 586         bi = &rx_ring->rx_buffer_info[i];
 587
 588         while (cleaned_count--) {
 589                 rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 590
 591                 if (!bi->page_dma &&
 592                     (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED)) {
 593                         if (!bi->page) {
 594                                 bi->page = alloc_page(GFP_ATOMIC);
 595                                 if (!bi->page) {
 596                                         adapter->alloc_rx_page_failed++;
 597                                         goto no_buffers;
 598                                 }
 599                                 bi->page_offset = 0;
 600                         } else {
 601                                 /* use a half page if we're re-using */
 602                                 bi->page_offset ^= (PAGE_SIZE / 2);
 603                         }
 604
 605                         bi->page_dma = pci_map_page(pdev, bi->page,
 606                                                     bi->page_offset,
 607                                                     (PAGE_SIZE / 2),
 608                                                     PCI_DMA_FROMDEVICE);
 609                 }
 610
 611                 if (!bi->skb) {
 612                         struct sk_buff *skb;
 613                         skb = netdev_alloc_skb(adapter->netdev,
 614                                                (rx_ring->rx_buf_len +
 615                                                 NET_IP_ALIGN));
 616
 617                         if (!skb) {
 618                                 adapter->alloc_rx_buff_failed++;
 619                                 goto no_buffers;
 620                         }
 621
 622                         /*
 623                          * Make buffer alignment 2 beyond a 16 byte boundary
 624                          * this will result in a 16 byte aligned IP header after
 625                          * the 14 byte MAC header is removed
 626                          */
 627                         skb_reserve(skb, NET_IP_ALIGN);
 628
 629                         bi->skb = skb;
 630                         bi->dma = pci_map_single(pdev, skb->data,
 631                                                  rx_ring->rx_buf_len,
 632                                                  PCI_DMA_FROMDEVICE);
 633                 }
 634                 /* Refresh the desc even if buffer_addrs didn't change because
 635                  * each write-back erases this info. */
 636                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 637                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
 638                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
 639                 } else {
 640                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
 641                 }
 642
 643                 i++;
 644                 if (i == rx_ring->count)
 645                         i = 0;
 646                 bi = &rx_ring->rx_buffer_info[i];
 647         }
 648
 649 no_buffers:
 650         if (rx_ring->next_to_use != i) {
 651                 rx_ring->next_to_use = i;
 652                 if (i-- == 0)
 653                         i = (rx_ring->count - 1);
 654
 655                 ixgbe_release_rx_desc(&adapter->hw, rx_ring, i);
 656         }
 657 }
 658
 659 static inline u16 ixgbe_get_hdr_info(union ixgbe_adv_rx_desc *rx_desc)
 660 {
 661         return rx_desc->wb.lower.lo_dword.hs_rss.hdr_info;
 662 }
 663
 664 static inline u16 ixgbe_get_pkt_info(union ixgbe_adv_rx_desc *rx_desc)
 665 {
 666         return rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
 667 }
 668
 669 static inline u32 ixgbe_get_rsc_count(union ixgbe_adv_rx_desc *rx_desc)
 670 {
 671         return (le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
 672                 IXGBE_RXDADV_RSCCNT_MASK) >>
 673                 IXGBE_RXDADV_RSCCNT_SHIFT;
 674 }
 675
 676 /**
 677  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
 678  * @skb: pointer to the last skb in the rsc queue
 679  *
 680  * This function changes a queue full of hw rsc buffers into a completed
 681  * packet.  It uses the ->prev pointers to find the first packet and then
 682  * turns it into the frag list owner.
 683  **/
 684 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
 685 {
 686         unsigned int frag_list_size = 0;
 687
 688         while (skb->prev) {
 689                 struct sk_buff *prev = skb->prev;
 690                 frag_list_size += skb->len;
 691                 skb->prev = NULL;
 692                 skb = prev;
 693         }
 694
 695         skb_shinfo(skb)->frag_list = skb->next;
 696         skb->next = NULL;
 697         skb->len += frag_list_size;
 698         skb->data_len += frag_list_size;
 699         skb->truesize += frag_list_size;
 700         return skb;
 701 }
 702
 703 static bool ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
 704                                struct ixgbe_ring *rx_ring,
 705                                int *work_done, int work_to_do)
 706 {
 707         struct ixgbe_adapter *adapter = q_vector->adapter;
 708         struct pci_dev *pdev = adapter->pdev;
 709         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
 710         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
 711         struct sk_buff *skb;
 712         unsigned int i, rsc_count = 0;
 713         u32 len, staterr;
 714         u16 hdr_info;
 715         bool cleaned = false;
 716         int cleaned_count = 0;
 717         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
 718 #ifdef IXGBE_FCOE
 719         int ddp_bytes = 0;
 720 #endif /* IXGBE_FCOE */
 721
 722         i = rx_ring->next_to_clean;
 723         rx_desc = IXGBE_RX_DESC_ADV(*rx_ring, i);
 724         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 725         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 726
 727         while (staterr & IXGBE_RXD_STAT_DD) {
 728                 u32 upper_len = 0;
 729                 if (*work_done >= work_to_do)
 730                         break;
 731                 (*work_done)++;
 732
 733                 if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 734                         hdr_info = le16_to_cpu(ixgbe_get_hdr_info(rx_desc));
 735                         len = (hdr_info & IXGBE_RXDADV_HDRBUFLEN_MASK) >>
 736                                IXGBE_RXDADV_HDRBUFLEN_SHIFT;
 737                         if (hdr_info & IXGBE_RXDADV_SPH)
 738                                 adapter->rx_hdr_split++;
 739                         if (len > IXGBE_RX_HDR_SIZE)
 740                                 len = IXGBE_RX_HDR_SIZE;
 741                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
 742                 } else {
 743                         len = le16_to_cpu(rx_desc->wb.upper.length);
 744                 }
 745
 746                 cleaned = true;
 747                 skb = rx_buffer_info->skb;
 748                 prefetch(skb->data - NET_IP_ALIGN);
 749                 rx_buffer_info->skb = NULL;
 750
 751                 if (rx_buffer_info->dma) {
 752                         pci_unmap_single(pdev, rx_buffer_info->dma,
 753                                          rx_ring->rx_buf_len,
 754                                          PCI_DMA_FROMDEVICE);
 755                         rx_buffer_info->dma = 0;
 756                         skb_put(skb, len);
 757                 }
 758
 759                 if (upper_len) {
 760                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
 761                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
 762                         rx_buffer_info->page_dma = 0;
 763                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
 764                                            rx_buffer_info->page,
 765                                            rx_buffer_info->page_offset,
 766                                            upper_len);
 767
 768                         if ((rx_ring->rx_buf_len > (PAGE_SIZE / 2)) ||
 769                             (page_count(rx_buffer_info->page) != 1))
 770                                 rx_buffer_info->page = NULL;
 771                         else
 772                                 get_page(rx_buffer_info->page);
 773
 774                         skb->len += upper_len;
 775                         skb->data_len += upper_len;
 776                         skb->truesize += upper_len;
 777                 }
 778
 779                 i++;
 780                 if (i == rx_ring->count)
 781                         i = 0;
 782
 783                 next_rxd = IXGBE_RX_DESC_ADV(*rx_ring, i);
 784                 prefetch(next_rxd);
 785                 cleaned_count++;
 786
 787                 if (adapter->flags2 & IXGBE_FLAG2_RSC_CAPABLE)
 788                         rsc_count = ixgbe_get_rsc_count(rx_desc);
 789
 790                 if (rsc_count) {
 791                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
 792                                      IXGBE_RXDADV_NEXTP_SHIFT;
 793                         next_buffer = &rx_ring->rx_buffer_info[nextp];
 794                         rx_ring->rsc_count += (rsc_count - 1);
 795                 } else {
 796                         next_buffer = &rx_ring->rx_buffer_info[i];
 797                 }
 798
 799                 if (staterr & IXGBE_RXD_STAT_EOP) {
 800                         if (skb->prev)
 801                                 skb = ixgbe_transform_rsc_queue(skb);
 802                         rx_ring->stats.packets++;
 803                         rx_ring->stats.bytes += skb->len;
 804                 } else {
 805                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
 806                                 rx_buffer_info->skb = next_buffer->skb;
 807                                 rx_buffer_info->dma = next_buffer->dma;
 808                                 next_buffer->skb = skb;
 809                                 next_buffer->dma = 0;
 810                         } else {
 811                                 skb->next = next_buffer->skb;
 812                                 skb->next->prev = skb;
 813                         }
 814                         adapter->non_eop_descs++;
 815                         goto next_desc;
 816                 }
 817
 818                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
 819                         dev_kfree_skb_irq(skb);
 820                         goto next_desc;
 821                 }
 822
 823                 ixgbe_rx_checksum(adapter, rx_desc, skb);
 824
 825                 /* probably a little skewed due to removing CRC */
 826                 total_rx_bytes += skb->len;
 827                 total_rx_packets++;
 828
 829                 skb->protocol = eth_type_trans(skb, adapter->netdev);
 830 #ifdef IXGBE_FCOE
 831                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
 832                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
 833                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
 834                         if (!ddp_bytes)
 835                                 goto next_desc;
 836                 }
 837 #endif /* IXGBE_FCOE */
 838                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
 839
 840 next_desc:
 841                 rx_desc->wb.upper.status_error = 0;
 842
 843                 /* return some buffers to hardware, one at a time is too slow */
 844                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
 845                         ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 846                         cleaned_count = 0;
 847                 }
 848
 849                 /* use prefetched values */
 850                 rx_desc = next_rxd;
 851                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
 852
 853                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 854         }
 855
 856         rx_ring->next_to_clean = i;
 857         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
 858
 859         if (cleaned_count)
 860                 ixgbe_alloc_rx_buffers(adapter, rx_ring, cleaned_count);
 861
 862 #ifdef IXGBE_FCOE
 863         /* include DDPed FCoE data */
 864         if (ddp_bytes > 0) {
 865                 unsigned int mss;
 866
 867                 mss = adapter->netdev->mtu - sizeof(struct fcoe_hdr) -
 868                         sizeof(struct fc_frame_header) -
 869                         sizeof(struct fcoe_crc_eof);
 870                 if (mss > 512)
 871                         mss &= ~511;
 872                 total_rx_bytes += ddp_bytes;
 873                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
 874         }
 875 #endif /* IXGBE_FCOE */
 876
 877         rx_ring->total_packets += total_rx_packets;
 878         rx_ring->total_bytes += total_rx_bytes;
 879         adapter->net_stats.rx_bytes += total_rx_bytes;
 880         adapter->net_stats.rx_packets += total_rx_packets;
 881
 882         return cleaned;
 883 }
 884
 885 static int ixgbe_clean_rxonly(struct napi_struct *, int);
 886 /**
 887  * ixgbe_configure_msix - Configure MSI-X hardware
 888  * @adapter: board private structure
 889  *
 890  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
 891  * interrupts.
 892  **/
 893 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
 894 {
 895         struct ixgbe_q_vector *q_vector;
 896         int i, j, q_vectors, v_idx, r_idx;
 897         u32 mask;
 898
 899         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
 900
 901         /*
 902          * Populate the IVAR table and set the ITR values to the
 903          * corresponding register.
 904          */
 905         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
 906                 q_vector = adapter->q_vector[v_idx];
 907                 /* XXX for_each_bit(...) */
 908                 r_idx = find_first_bit(q_vector->rxr_idx,
 909                                        adapter->num_rx_queues);
 910
 911                 for (i = 0; i < q_vector->rxr_count; i++) {
 912                         j = adapter->rx_ring[r_idx].reg_idx;
 913                         ixgbe_set_ivar(adapter, 0, j, v_idx);
 914                         r_idx = find_next_bit(q_vector->rxr_idx,
 915                                               adapter->num_rx_queues,
 916                                               r_idx + 1);
 917                 }
 918                 r_idx = find_first_bit(q_vector->txr_idx,
 919                                        adapter->num_tx_queues);
 920
 921                 for (i = 0; i < q_vector->txr_count; i++) {
 922                         j = adapter->tx_ring[r_idx].reg_idx;
 923                         ixgbe_set_ivar(adapter, 1, j, v_idx);
 924                         r_idx = find_next_bit(q_vector->txr_idx,
 925                                               adapter->num_tx_queues,
 926                                               r_idx + 1);
 927                 }
 928
 929                 /* if this is a tx only vector halve the interrupt rate */
 930                 if (q_vector->txr_count && !q_vector->rxr_count)
 931                         q_vector->eitr = (adapter->eitr_param >> 1);
 932                 else if (q_vector->rxr_count)
 933                         /* rx only */
 934                         q_vector->eitr = adapter->eitr_param;
 935
 936                 ixgbe_write_eitr(q_vector);
 937         }
 938
 939         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
 940                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
 941                                v_idx);
 942         else if (adapter->hw.mac.type == ixgbe_mac_82599EB)
 943                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
 944         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
 945
 946         /* set up to autoclear timer, and the vectors */
 947         mask = IXGBE_EIMS_ENABLE_MASK;
 948         mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
 949         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
 950 }
 951
 952 enum latency_range {
 953         lowest_latency = 0,
 954         low_latency = 1,
 955         bulk_latency = 2,
 956         latency_invalid = 255
 957 };
 958
 959 /**
 960  * ixgbe_update_itr - update the dynamic ITR value based on statistics
 961  * @adapter: pointer to adapter
 962  * @eitr: eitr setting (ints per sec) to give last timeslice
 963  * @itr_setting: current throttle rate in ints/second
 964  * @packets: the number of packets during this measurement interval
 965  * @bytes: the number of bytes during this measurement interval
 966  *
 967  *      Stores a new ITR value based on packets and byte
 968  *      counts during the last interrupt.  The advantage of per interrupt
 969  *      computation is faster updates and more accurate ITR for the current
 970  *      traffic pattern.  Constants in this function were computed
 971  *      based on theoretical maximum wire speed and thresholds were set based
 972  *      on testing data as well as attempting to minimize response time
 973  *      while increasing bulk throughput.
 974  *      this functionality is controlled by the InterruptThrottleRate module
 975  *      parameter (see ixgbe_param.c)
 976  **/
 977 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
 978                            u32 eitr, u8 itr_setting,
 979                            int packets, int bytes)
 980 {
 981         unsigned int retval = itr_setting;
 982         u32 timepassed_us;
 983         u64 bytes_perint;
 984
 985         if (packets == 0)
 986                 goto update_itr_done;
 987
 988
 989         /* simple throttlerate management
 990          *    0-20MB/s lowest (100000 ints/s)
 991          *   20-100MB/s low   (20000 ints/s)
 992          *  100-1249MB/s bulk (8000 ints/s)
 993          */
 994         /* what was last interrupt timeslice? */
 995         timepassed_us = 1000000/eitr;
 996         bytes_perint = bytes / timepassed_us; /* bytes/usec */
 997
 998         switch (itr_setting) {
 999         case lowest_latency:
1000                 if (bytes_perint > adapter->eitr_low)
1001                         retval = low_latency;
1002                 break;
1003         case low_latency:
1004                 if (bytes_perint > adapter->eitr_high)
1005                         retval = bulk_latency;
1006                 else if (bytes_perint <= adapter->eitr_low)
1007                         retval = lowest_latency;
1008                 break;
1009         case bulk_latency:
1010                 if (bytes_perint <= adapter->eitr_high)
1011                         retval = low_latency;
1012                 break;
1013         }
1014
1015 update_itr_done:
1016         return retval;
1017 }
1018
1019 /**
1020  * ixgbe_write_eitr - write EITR register in hardware specific way
1021  * @q_vector: structure containing interrupt and ring information
1022  *
1023  * This function is made to be called by ethtool and by the driver
1024  * when it needs to update EITR registers at runtime.  Hardware
1025  * specific quirks/differences are taken care of here.
1026  */
1027 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1028 {
1029         struct ixgbe_adapter *adapter = q_vector->adapter;
1030         struct ixgbe_hw *hw = &adapter->hw;
1031         int v_idx = q_vector->v_idx;
1032         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1033
1034         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1035                 /* must write high and low 16 bits to reset counter */
1036                 itr_reg |= (itr_reg << 16);
1037         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1038                 /*
1039                  * set the WDIS bit to not clear the timer bits and cause an
1040                  * immediate assertion of the interrupt
1041                  */
1042                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1043         }
1044         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1045 }
1046
1047 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1048 {
1049         struct ixgbe_adapter *adapter = q_vector->adapter;
1050         u32 new_itr;
1051         u8 current_itr, ret_itr;
1052         int i, r_idx;
1053         struct ixgbe_ring *rx_ring, *tx_ring;
1054
1055         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1056         for (i = 0; i < q_vector->txr_count; i++) {
1057                 tx_ring = &(adapter->tx_ring[r_idx]);
1058                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1059                                            q_vector->tx_itr,
1060                                            tx_ring->total_packets,
1061                                            tx_ring->total_bytes);
1062                 /* if the result for this queue would decrease interrupt
1063                  * rate for this vector then use that result */
1064                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1065                                     q_vector->tx_itr - 1 : ret_itr);
1066                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1067                                       r_idx + 1);
1068         }
1069
1070         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1071         for (i = 0; i < q_vector->rxr_count; i++) {
1072                 rx_ring = &(adapter->rx_ring[r_idx]);
1073                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1074                                            q_vector->rx_itr,
1075                                            rx_ring->total_packets,
1076                                            rx_ring->total_bytes);
1077                 /* if the result for this queue would decrease interrupt
1078                  * rate for this vector then use that result */
1079                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1080                                     q_vector->rx_itr - 1 : ret_itr);
1081                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1082                                       r_idx + 1);
1083         }
1084
1085         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1086
1087         switch (current_itr) {
1088         /* counts and packets in update_itr are dependent on these numbers */
1089         case lowest_latency:
1090                 new_itr = 100000;
1091                 break;
1092         case low_latency:
1093                 new_itr = 20000; /* aka hwitr = ~200 */
1094                 break;
1095         case bulk_latency:
1096         default:
1097                 new_itr = 8000;
1098                 break;
1099         }
1100
1101         if (new_itr != q_vector->eitr) {
1102                 /* do an exponential smoothing */
1103                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1104
1105                 /* save the algorithm value here, not the smoothed one */
1106                 q_vector->eitr = new_itr;
1107
1108                 ixgbe_write_eitr(q_vector);
1109         }
1110
1111         return;
1112 }
1113
1114 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1115 {
1116         struct ixgbe_hw *hw = &adapter->hw;
1117
1118         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1119             (eicr & IXGBE_EICR_GPI_SDP1)) {
1120                 DPRINTK(PROBE, CRIT, "Fan has stopped, replace the adapter\n");
1121                 /* write to clear the interrupt */
1122                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1123         }
1124 }
1125
1126 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1127 {
1128         struct ixgbe_hw *hw = &adapter->hw;
1129
1130         if (eicr & IXGBE_EICR_GPI_SDP1) {
1131                 /* Clear the interrupt */
1132                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1133                 schedule_work(&adapter->multispeed_fiber_task);
1134         } else if (eicr & IXGBE_EICR_GPI_SDP2) {
1135                 /* Clear the interrupt */
1136                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1137                 schedule_work(&adapter->sfp_config_module_task);
1138         } else {
1139                 /* Interrupt isn't for us... */
1140                 return;
1141         }
1142 }
1143
1144 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1145 {
1146         struct ixgbe_hw *hw = &adapter->hw;
1147
1148         adapter->lsc_int++;
1149         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1150         adapter->link_check_timeout = jiffies;
1151         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1152                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1153                 schedule_work(&adapter->watchdog_task);
1154         }
1155 }
1156
1157 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1158 {
1159         struct net_device *netdev = data;
1160         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1161         struct ixgbe_hw *hw = &adapter->hw;
1162         u32 eicr;
1163
1164         /*
1165          * Workaround for Silicon errata.  Use clear-by-write instead
1166          * of clear-by-read.  Reading with EICS will return the
1167          * interrupt causes without clearing, which later be done
1168          * with the write to EICR.
1169          */
1170         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1171         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1172
1173         if (eicr & IXGBE_EICR_LSC)
1174                 ixgbe_check_lsc(adapter);
1175
1176         if (hw->mac.type == ixgbe_mac_82598EB)
1177                 ixgbe_check_fan_failure(adapter, eicr);
1178
1179         if (hw->mac.type == ixgbe_mac_82599EB) {
1180                 ixgbe_check_sfp_event(adapter, eicr);
1181
1182                 /* Handle Flow Director Full threshold interrupt */
1183                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1184                         int i;
1185                         IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_FLOW_DIR);
1186                         /* Disable transmits before FDIR Re-initialization */
1187                         netif_tx_stop_all_queues(netdev);
1188                         for (i = 0; i < adapter->num_tx_queues; i++) {
1189                                 struct ixgbe_ring *tx_ring =
1190                                                            &adapter->tx_ring[i];
1191                                 if (test_and_clear_bit(__IXGBE_FDIR_INIT_DONE,
1192                                                        &tx_ring->reinit_state))
1193                                         schedule_work(&adapter->fdir_reinit_task);
1194                         }
1195                 }
1196         }
1197         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1198                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_OTHER);
1199
1200         return IRQ_HANDLED;
1201 }
1202
1203 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1204                                            u64 qmask)
1205 {
1206         u32 mask;
1207
1208         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1209                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1210                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1211         } else {
1212                 mask = (qmask & 0xFFFFFFFF);
1213                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(0), mask);
1214                 mask = (qmask >> 32);
1215                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS_EX(1), mask);
1216         }
1217         /* skip the flush */
1218 }
1219
1220 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1221                                             u64 qmask)
1222 {
1223         u32 mask;
1224
1225         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1226                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1227                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, mask);
1228         } else {
1229                 mask = (qmask & 0xFFFFFFFF);
1230                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), mask);
1231                 mask = (qmask >> 32);
1232                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), mask);
1233         }
1234         /* skip the flush */
1235 }
1236
1237 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
1238 {
1239         struct ixgbe_q_vector *q_vector = data;
1240         struct ixgbe_adapter  *adapter = q_vector->adapter;
1241         struct ixgbe_ring     *tx_ring;
1242         int i, r_idx;
1243
1244         if (!q_vector->txr_count)
1245                 return IRQ_HANDLED;
1246
1247         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1248         for (i = 0; i < q_vector->txr_count; i++) {
1249                 tx_ring = &(adapter->tx_ring[r_idx]);
1250                 tx_ring->total_bytes = 0;
1251                 tx_ring->total_packets = 0;
1252                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1253                                       r_idx + 1);
1254         }
1255
1256         /* disable interrupts on this vector only */
1257         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1258         napi_schedule(&q_vector->napi);
1259
1260         return IRQ_HANDLED;
1261 }
1262
1263 /**
1264  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
1265  * @irq: unused
1266  * @data: pointer to our q_vector struct for this interrupt vector
1267  **/
1268 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
1269 {
1270         struct ixgbe_q_vector *q_vector = data;
1271         struct ixgbe_adapter  *adapter = q_vector->adapter;
1272         struct ixgbe_ring  *rx_ring;
1273         int r_idx;
1274         int i;
1275
1276         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1277         for (i = 0;  i < q_vector->rxr_count; i++) {
1278                 rx_ring = &(adapter->rx_ring[r_idx]);
1279                 rx_ring->total_bytes = 0;
1280                 rx_ring->total_packets = 0;
1281                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1282                                       r_idx + 1);
1283         }
1284
1285         if (!q_vector->rxr_count)
1286                 return IRQ_HANDLED;
1287
1288         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1289         rx_ring = &(adapter->rx_ring[r_idx]);
1290         /* disable interrupts on this vector only */
1291         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1292         napi_schedule(&q_vector->napi);
1293
1294         return IRQ_HANDLED;
1295 }
1296
1297 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
1298 {
1299         struct ixgbe_q_vector *q_vector = data;
1300         struct ixgbe_adapter  *adapter = q_vector->adapter;
1301         struct ixgbe_ring  *ring;
1302         int r_idx;
1303         int i;
1304
1305         if (!q_vector->txr_count && !q_vector->rxr_count)
1306                 return IRQ_HANDLED;
1307
1308         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1309         for (i = 0; i < q_vector->txr_count; i++) {
1310                 ring = &(adapter->tx_ring[r_idx]);
1311                 ring->total_bytes = 0;
1312                 ring->total_packets = 0;
1313                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1314                                       r_idx + 1);
1315         }
1316
1317         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1318         for (i = 0; i < q_vector->rxr_count; i++) {
1319                 ring = &(adapter->rx_ring[r_idx]);
1320                 ring->total_bytes = 0;
1321                 ring->total_packets = 0;
1322                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1323                                       r_idx + 1);
1324         }
1325
1326         /* disable interrupts on this vector only */
1327         ixgbe_irq_disable_queues(adapter, ((u64)1 << q_vector->v_idx));
1328         napi_schedule(&q_vector->napi);
1329
1330         return IRQ_HANDLED;
1331 }
1332
1333 /**
1334  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
1335  * @napi: napi struct with our devices info in it
1336  * @budget: amount of work driver is allowed to do this pass, in packets
1337  *
1338  * This function is optimized for cleaning one queue only on a single
1339  * q_vector!!!
1340  **/
1341 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
1342 {
1343         struct ixgbe_q_vector *q_vector =
1344                                container_of(napi, struct ixgbe_q_vector, napi);
1345         struct ixgbe_adapter *adapter = q_vector->adapter;
1346         struct ixgbe_ring *rx_ring = NULL;
1347         int work_done = 0;
1348         long r_idx;
1349
1350         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1351         rx_ring = &(adapter->rx_ring[r_idx]);
1352 #ifdef CONFIG_IXGBE_DCA
1353         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1354                 ixgbe_update_rx_dca(adapter, rx_ring);
1355 #endif
1356
1357         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
1358
1359         /* If all Rx work done, exit the polling mode */
1360         if (work_done < budget) {
1361                 napi_complete(napi);
1362                 if (adapter->itr_setting & 1)
1363                         ixgbe_set_itr_msix(q_vector);
1364                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1365                         ixgbe_irq_enable_queues(adapter,
1366                                                 ((u64)1 << q_vector->v_idx));
1367         }
1368
1369         return work_done;
1370 }
1371
1372 /**
1373  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
1374  * @napi: napi struct with our devices info in it
1375  * @budget: amount of work driver is allowed to do this pass, in packets
1376  *
1377  * This function will clean more than one rx queue associated with a
1378  * q_vector.
1379  **/
1380 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
1381 {
1382         struct ixgbe_q_vector *q_vector =
1383                                container_of(napi, struct ixgbe_q_vector, napi);
1384         struct ixgbe_adapter *adapter = q_vector->adapter;
1385         struct ixgbe_ring *ring = NULL;
1386         int work_done = 0, i;
1387         long r_idx;
1388         bool tx_clean_complete = true;
1389
1390         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1391         for (i = 0; i < q_vector->txr_count; i++) {
1392                 ring = &(adapter->tx_ring[r_idx]);
1393 #ifdef CONFIG_IXGBE_DCA
1394                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1395                         ixgbe_update_tx_dca(adapter, ring);
1396 #endif
1397                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
1398                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1399                                       r_idx + 1);
1400         }
1401
1402         /* attempt to distribute budget to each queue fairly, but don't allow
1403          * the budget to go below 1 because we'll exit polling */
1404         budget /= (q_vector->rxr_count ?: 1);
1405         budget = max(budget, 1);
1406         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1407         for (i = 0; i < q_vector->rxr_count; i++) {
1408                 ring = &(adapter->rx_ring[r_idx]);
1409 #ifdef CONFIG_IXGBE_DCA
1410                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1411                         ixgbe_update_rx_dca(adapter, ring);
1412 #endif
1413                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
1414                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1415                                       r_idx + 1);
1416         }
1417
1418         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1419         ring = &(adapter->rx_ring[r_idx]);
1420         /* If all Rx work done, exit the polling mode */
1421         if (work_done < budget) {
1422                 napi_complete(napi);
1423                 if (adapter->itr_setting & 1)
1424                         ixgbe_set_itr_msix(q_vector);
1425                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1426                         ixgbe_irq_enable_queues(adapter,
1427                                                 ((u64)1 << q_vector->v_idx));
1428                 return 0;
1429         }
1430
1431         return work_done;
1432 }
1433
1434 /**
1435  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
1436  * @napi: napi struct with our devices info in it
1437  * @budget: amount of work driver is allowed to do this pass, in packets
1438  *
1439  * This function is optimized for cleaning one queue only on a single
1440  * q_vector!!!
1441  **/
1442 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
1443 {
1444         struct ixgbe_q_vector *q_vector =
1445                                container_of(napi, struct ixgbe_q_vector, napi);
1446         struct ixgbe_adapter *adapter = q_vector->adapter;
1447         struct ixgbe_ring *tx_ring = NULL;
1448         int work_done = 0;
1449         long r_idx;
1450
1451         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1452         tx_ring = &(adapter->tx_ring[r_idx]);
1453 #ifdef CONFIG_IXGBE_DCA
1454         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1455                 ixgbe_update_tx_dca(adapter, tx_ring);
1456 #endif
1457
1458         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
1459                 work_done = budget;
1460
1461         /* If all Rx work done, exit the polling mode */
1462         if (work_done < budget) {
1463                 napi_complete(napi);
1464                 if (adapter->itr_setting & 1)
1465                         ixgbe_set_itr_msix(q_vector);
1466                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
1467                         ixgbe_irq_enable_queues(adapter, ((u64)1 << q_vector->v_idx));
1468         }
1469
1470         return work_done;
1471 }
1472
1473 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
1474                                      int r_idx)
1475 {
1476         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1477
1478         set_bit(r_idx, q_vector->rxr_idx);
1479         q_vector->rxr_count++;
1480 }
1481
1482 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
1483                                      int t_idx)
1484 {
1485         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
1486
1487         set_bit(t_idx, q_vector->txr_idx);
1488         q_vector->txr_count++;
1489 }
1490
1491 /**
1492  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
1493  * @adapter: board private structure to initialize
1494  * @vectors: allotted vector count for descriptor rings
1495  *
1496  * This function maps descriptor rings to the queue-specific vectors
1497  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
1498  * one vector per ring/queue, but on a constrained vector budget, we
1499  * group the rings as "efficiently" as possible.  You would add new
1500  * mapping configurations in here.
1501  **/
1502 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter,
1503                                       int vectors)
1504 {
1505         int v_start = 0;
1506         int rxr_idx = 0, txr_idx = 0;
1507         int rxr_remaining = adapter->num_rx_queues;
1508         int txr_remaining = adapter->num_tx_queues;
1509         int i, j;
1510         int rqpv, tqpv;
1511         int err = 0;
1512
1513         /* No mapping required if MSI-X is disabled. */
1514         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
1515                 goto out;
1516
1517         /*
1518          * The ideal configuration...
1519          * We have enough vectors to map one per queue.
1520          */
1521         if (vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
1522                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
1523                         map_vector_to_rxq(adapter, v_start, rxr_idx);
1524
1525                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
1526                         map_vector_to_txq(adapter, v_start, txr_idx);
1527
1528                 goto out;
1529         }
1530
1531         /*
1532          * If we don't have enough vectors for a 1-to-1
1533          * mapping, we'll have to group them so there are
1534          * multiple queues per vector.
1535          */
1536         /* Re-adjusting *qpv takes care of the remainder. */
1537         for (i = v_start; i < vectors; i++) {
1538                 rqpv = DIV_ROUND_UP(rxr_remaining, vectors - i);
1539                 for (j = 0; j < rqpv; j++) {
1540                         map_vector_to_rxq(adapter, i, rxr_idx);
1541                         rxr_idx++;
1542                         rxr_remaining--;
1543                 }
1544         }
1545         for (i = v_start; i < vectors; i++) {
1546                 tqpv = DIV_ROUND_UP(txr_remaining, vectors - i);
1547                 for (j = 0; j < tqpv; j++) {
1548                         map_vector_to_txq(adapter, i, txr_idx);
1549                         txr_idx++;
1550                         txr_remaining--;
1551                 }
1552         }
1553
1554 out:
1555         return err;
1556 }
1557
1558 /**
1559  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
1560  * @adapter: board private structure
1561  *
1562  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
1563  * interrupts from the kernel.
1564  **/
1565 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
1566 {
1567         struct net_device *netdev = adapter->netdev;
1568         irqreturn_t (*handler)(int, void *);
1569         int i, vector, q_vectors, err;
1570         int ri=0, ti=0;
1571
1572         /* Decrement for Other and TCP Timer vectors */
1573         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1574
1575         /* Map the Tx/Rx rings to the vectors we were allotted. */
1576         err = ixgbe_map_rings_to_vectors(adapter, q_vectors);
1577         if (err)
1578                 goto out;
1579
1580 #define SET_HANDLER(_v) ((!(_v)->rxr_count) ? &ixgbe_msix_clean_tx : \
1581                          (!(_v)->txr_count) ? &ixgbe_msix_clean_rx : \
1582                          &ixgbe_msix_clean_many)
1583         for (vector = 0; vector < q_vectors; vector++) {
1584                 handler = SET_HANDLER(adapter->q_vector[vector]);
1585
1586                 if(handler == &ixgbe_msix_clean_rx) {
1587                         sprintf(adapter->name[vector], "%s-%s-%d",
1588                                 netdev->name, "rx", ri++);
1589                 }
1590                 else if(handler == &ixgbe_msix_clean_tx) {
1591                         sprintf(adapter->name[vector], "%s-%s-%d",
1592                                 netdev->name, "tx", ti++);
1593                 }
1594                 else
1595                         sprintf(adapter->name[vector], "%s-%s-%d",
1596                                 netdev->name, "TxRx", vector);
1597
1598                 err = request_irq(adapter->msix_entries[vector].vector,
1599                                   handler, 0, adapter->name[vector],
1600                                   adapter->q_vector[vector]);
1601                 if (err) {
1602                         DPRINTK(PROBE, ERR,
1603                                 "request_irq failed for MSIX interrupt "
1604                                 "Error: %d\n", err);
1605                         goto free_queue_irqs;
1606                 }
1607         }
1608
1609         sprintf(adapter->name[vector], "%s:lsc", netdev->name);
1610         err = request_irq(adapter->msix_entries[vector].vector,
1611                           &ixgbe_msix_lsc, 0, adapter->name[vector], netdev);
1612         if (err) {
1613                 DPRINTK(PROBE, ERR,
1614                         "request_irq for msix_lsc failed: %d\n", err);
1615                 goto free_queue_irqs;
1616         }
1617
1618         return 0;
1619
1620 free_queue_irqs:
1621         for (i = vector - 1; i >= 0; i--)
1622                 free_irq(adapter->msix_entries[--vector].vector,
1623                          adapter->q_vector[i]);
1624         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
1625         pci_disable_msix(adapter->pdev);
1626         kfree(adapter->msix_entries);
1627         adapter->msix_entries = NULL;
1628 out:
1629         return err;
1630 }
1631
1632 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
1633 {
1634         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1635         u8 current_itr;
1636         u32 new_itr = q_vector->eitr;
1637         struct ixgbe_ring *rx_ring = &adapter->rx_ring[0];
1638         struct ixgbe_ring *tx_ring = &adapter->tx_ring[0];
1639
1640         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
1641                                             q_vector->tx_itr,
1642                                             tx_ring->total_packets,
1643                                             tx_ring->total_bytes);
1644         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
1645                                             q_vector->rx_itr,
1646                                             rx_ring->total_packets,
1647                                             rx_ring->total_bytes);
1648
1649         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1650
1651         switch (current_itr) {
1652         /* counts and packets in update_itr are dependent on these numbers */
1653         case lowest_latency:
1654                 new_itr = 100000;
1655                 break;
1656         case low_latency:
1657                 new_itr = 20000; /* aka hwitr = ~200 */
1658                 break;
1659         case bulk_latency:
1660                 new_itr = 8000;
1661                 break;
1662         default:
1663                 break;
1664         }
1665
1666         if (new_itr != q_vector->eitr) {
1667                 /* do an exponential smoothing */
1668                 new_itr = ((q_vector->eitr * 90)/100) + ((new_itr * 10)/100);
1669
1670                 /* save the algorithm value here, not the smoothed one */
1671                 q_vector->eitr = new_itr;
1672
1673                 ixgbe_write_eitr(q_vector);
1674         }
1675
1676         return;
1677 }
1678
1679 /**
1680  * ixgbe_irq_enable - Enable default interrupt generation settings
1681  * @adapter: board private structure
1682  **/
1683 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter)
1684 {
1685         u32 mask;
1686
1687         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
1688         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
1689                 mask |= IXGBE_EIMS_GPI_SDP1;
1690         if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
1691                 mask |= IXGBE_EIMS_ECC;
1692                 mask |= IXGBE_EIMS_GPI_SDP1;
1693                 mask |= IXGBE_EIMS_GPI_SDP2;
1694         }
1695         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
1696             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
1697                 mask |= IXGBE_EIMS_FLOW_DIR;
1698
1699         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
1700         ixgbe_irq_enable_queues(adapter, ~0);
1701         IXGBE_WRITE_FLUSH(&adapter->hw);
1702 }
1703
1704 /**
1705  * ixgbe_intr - legacy mode Interrupt Handler
1706  * @irq: interrupt number
1707  * @data: pointer to a network interface device structure
1708  **/
1709 static irqreturn_t ixgbe_intr(int irq, void *data)
1710 {
1711         struct net_device *netdev = data;
1712         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1713         struct ixgbe_hw *hw = &adapter->hw;
1714         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
1715         u32 eicr;
1716
1717         /*
1718          * Workaround for silicon errata.  Mask the interrupts
1719          * before the read of EICR.
1720          */
1721         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
1722
1723         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
1724          * therefore no explict interrupt disable is necessary */
1725         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
1726         if (!eicr) {
1727                 /* shared interrupt alert!
1728                  * make sure interrupts are enabled because the read will
1729                  * have disabled interrupts due to EIAM */
1730                 ixgbe_irq_enable(adapter);
1731                 return IRQ_NONE;        /* Not our interrupt */
1732         }
1733
1734         if (eicr & IXGBE_EICR_LSC)
1735                 ixgbe_check_lsc(adapter);
1736
1737         if (hw->mac.type == ixgbe_mac_82599EB)
1738                 ixgbe_check_sfp_event(adapter, eicr);
1739
1740         ixgbe_check_fan_failure(adapter, eicr);
1741
1742         if (napi_schedule_prep(&(q_vector->napi))) {
1743                 adapter->tx_ring[0].total_packets = 0;
1744                 adapter->tx_ring[0].total_bytes = 0;
1745                 adapter->rx_ring[0].total_packets = 0;
1746                 adapter->rx_ring[0].total_bytes = 0;
1747                 /* would disable interrupts here but EIAM disabled it */
1748                 __napi_schedule(&(q_vector->napi));
1749         }
1750
1751         return IRQ_HANDLED;
1752 }
1753
1754 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
1755 {
1756         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1757
1758         for (i = 0; i < q_vectors; i++) {
1759                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
1760                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
1761                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
1762                 q_vector->rxr_count = 0;
1763                 q_vector->txr_count = 0;
1764         }
1765 }
1766
1767 /**
1768  * ixgbe_request_irq - initialize interrupts
1769  * @adapter: board private structure
1770  *
1771  * Attempts to configure interrupts using the best available
1772  * capabilities of the hardware and kernel.
1773  **/
1774 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
1775 {
1776         struct net_device *netdev = adapter->netdev;
1777         int err;
1778
1779         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1780                 err = ixgbe_request_msix_irqs(adapter);
1781         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
1782                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, 0,
1783                                   netdev->name, netdev);
1784         } else {
1785                 err = request_irq(adapter->pdev->irq, &ixgbe_intr, IRQF_SHARED,
1786                                   netdev->name, netdev);
1787         }
1788
1789         if (err)
1790                 DPRINTK(PROBE, ERR, "request_irq failed, Error %d\n", err);
1791
1792         return err;
1793 }
1794
1795 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
1796 {
1797         struct net_device *netdev = adapter->netdev;
1798
1799         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1800                 int i, q_vectors;
1801
1802                 q_vectors = adapter->num_msix_vectors;
1803
1804                 i = q_vectors - 1;
1805                 free_irq(adapter->msix_entries[i].vector, netdev);
1806
1807                 i--;
1808                 for (; i >= 0; i--) {
1809                         free_irq(adapter->msix_entries[i].vector,
1810                                  adapter->q_vector[i]);
1811                 }
1812
1813                 ixgbe_reset_q_vectors(adapter);
1814         } else {
1815                 free_irq(adapter->pdev->irq, netdev);
1816         }
1817 }
1818
1819 /**
1820  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
1821  * @adapter: board private structure
1822  **/
1823 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
1824 {
1825         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1826                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
1827         } else {
1828                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
1829                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
1830                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
1831         }
1832         IXGBE_WRITE_FLUSH(&adapter->hw);
1833         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
1834                 int i;
1835                 for (i = 0; i < adapter->num_msix_vectors; i++)
1836                         synchronize_irq(adapter->msix_entries[i].vector);
1837         } else {
1838                 synchronize_irq(adapter->pdev->irq);
1839         }
1840 }
1841
1842 /**
1843  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
1844  *
1845  **/
1846 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
1847 {
1848         struct ixgbe_hw *hw = &adapter->hw;
1849
1850         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
1851                         EITR_INTS_PER_SEC_TO_REG(adapter->eitr_param));
1852
1853         ixgbe_set_ivar(adapter, 0, 0, 0);
1854         ixgbe_set_ivar(adapter, 1, 0, 0);
1855
1856         map_vector_to_rxq(adapter, 0, 0);
1857         map_vector_to_txq(adapter, 0, 0);
1858
1859         DPRINTK(HW, INFO, "Legacy interrupt IVAR setup done\n");
1860 }
1861
1862 /**
1863  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
1864  * @adapter: board private structure
1865  *
1866  * Configure the Tx unit of the MAC after a reset.
1867  **/
1868 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
1869 {
1870         u64 tdba;
1871         struct ixgbe_hw *hw = &adapter->hw;
1872         u32 i, j, tdlen, txctrl;
1873
1874         /* Setup the HW Tx Head and Tail descriptor pointers */
1875         for (i = 0; i < adapter->num_tx_queues; i++) {
1876                 struct ixgbe_ring *ring = &adapter->tx_ring[i];
1877                 j = ring->reg_idx;
1878                 tdba = ring->dma;
1879                 tdlen = ring->count * sizeof(union ixgbe_adv_tx_desc);
1880                 IXGBE_WRITE_REG(hw, IXGBE_TDBAL(j),
1881                                 (tdba & DMA_BIT_MASK(32)));
1882                 IXGBE_WRITE_REG(hw, IXGBE_TDBAH(j), (tdba >> 32));
1883                 IXGBE_WRITE_REG(hw, IXGBE_TDLEN(j), tdlen);
1884                 IXGBE_WRITE_REG(hw, IXGBE_TDH(j), 0);
1885                 IXGBE_WRITE_REG(hw, IXGBE_TDT(j), 0);
1886                 adapter->tx_ring[i].head = IXGBE_TDH(j);
1887                 adapter->tx_ring[i].tail = IXGBE_TDT(j);
1888                 /* Disable Tx Head Writeback RO bit, since this hoses
1889                  * bookkeeping if things aren't delivered in order.
1890                  */
1891                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(j));
1892                 txctrl &= ~IXGBE_DCA_TXCTRL_TX_WB_RO_EN;
1893                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(j), txctrl);
1894         }
1895         if (hw->mac.type == ixgbe_mac_82599EB) {
1896                 /* We enable 8 traffic classes, DCB only */
1897                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
1898                         IXGBE_WRITE_REG(hw, IXGBE_MTQC, (IXGBE_MTQC_RT_ENA |
1899                                         IXGBE_MTQC_8TC_8TQ));
1900         }
1901 }
1902
1903 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
1904
1905 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
1906                                    struct ixgbe_ring *rx_ring)
1907 {
1908         u32 srrctl;
1909         int index;
1910         struct ixgbe_ring_feature *feature = adapter->ring_feature;
1911
1912         index = rx_ring->reg_idx;
1913         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
1914                 unsigned long mask;
1915                 mask = (unsigned long) feature[RING_F_RSS].mask;
1916                 index = index & mask;
1917         }
1918         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(index));
1919
1920         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
1921         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
1922
1923         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
1924                   IXGBE_SRRCTL_BSIZEHDR_MASK;
1925
1926         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
1927 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
1928                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1929 #else
1930                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1931 #endif
1932                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
1933         } else {
1934                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
1935                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
1936                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
1937         }
1938
1939         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(index), srrctl);
1940 }
1941
1942 static u32 ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
1943 {
1944         u32 mrqc = 0;
1945         int mask;
1946
1947         if (!(adapter->hw.mac.type == ixgbe_mac_82599EB))
1948                 return mrqc;
1949
1950         mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
1951 #ifdef CONFIG_IXGBE_DCB
1952                                  | IXGBE_FLAG_DCB_ENABLED
1953 #endif
1954                                 );
1955
1956         switch (mask) {
1957         case (IXGBE_FLAG_RSS_ENABLED):
1958                 mrqc = IXGBE_MRQC_RSSEN;
1959                 break;
1960 #ifdef CONFIG_IXGBE_DCB
1961         case (IXGBE_FLAG_DCB_ENABLED):
1962                 mrqc = IXGBE_MRQC_RT8TCEN;
1963                 break;
1964 #endif /* CONFIG_IXGBE_DCB */
1965         default:
1966                 break;
1967         }
1968
1969         return mrqc;
1970 }
1971
1972 /**
1973  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
1974  * @adapter: board private structure
1975  *
1976  * Configure the Rx unit of the MAC after a reset.
1977  **/
1978 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
1979 {
1980         u64 rdba;
1981         struct ixgbe_hw *hw = &adapter->hw;
1982         struct ixgbe_ring *rx_ring;
1983         struct net_device *netdev = adapter->netdev;
1984         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
1985         int i, j;
1986         u32 rdlen, rxctrl, rxcsum;
1987         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
1988                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
1989                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
1990         u32 fctrl, hlreg0;
1991         u32 reta = 0, mrqc = 0;
1992         u32 rdrxctl;
1993         u32 rscctrl;
1994         int rx_buf_len;
1995
1996         /* Decide whether to use packet split mode or not */
1997         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
1998
1999         /* Set the RX buffer length according to the mode */
2000         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
2001                 rx_buf_len = IXGBE_RX_HDR_SIZE;
2002                 if (hw->mac.type == ixgbe_mac_82599EB) {
2003                         /* PSRTYPE must be initialized in 82599 */
2004                         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
2005                                       IXGBE_PSRTYPE_UDPHDR |
2006                                       IXGBE_PSRTYPE_IPV4HDR |
2007                                       IXGBE_PSRTYPE_IPV6HDR |
2008                                       IXGBE_PSRTYPE_L2HDR;
2009                         IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(0), psrtype);
2010                 }
2011         } else {
2012                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
2013                     (netdev->mtu <= ETH_DATA_LEN))
2014                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
2015                 else
2016                         rx_buf_len = ALIGN(max_frame, 1024);
2017         }
2018
2019         fctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_FCTRL);
2020         fctrl |= IXGBE_FCTRL_BAM;
2021         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
2022         fctrl |= IXGBE_FCTRL_PMCF;
2023         IXGBE_WRITE_REG(&adapter->hw, IXGBE_FCTRL, fctrl);
2024
2025         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
2026         if (adapter->netdev->mtu <= ETH_DATA_LEN)
2027                 hlreg0 &= ~IXGBE_HLREG0_JUMBOEN;
2028         else
2029                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2030 #ifdef IXGBE_FCOE
2031         if (netdev->features & NETIF_F_FCOE_MTU)
2032                 hlreg0 |= IXGBE_HLREG0_JUMBOEN;
2033 #endif
2034         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
2035
2036         rdlen = adapter->rx_ring[0].count * sizeof(union ixgbe_adv_rx_desc);
2037         /* disable receives while setting up the descriptors */
2038         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2039         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2040
2041         /*
2042          * Setup the HW Rx Head and Tail Descriptor Pointers and
2043          * the Base and Length of the Rx Descriptor Ring
2044          */
2045         for (i = 0; i < adapter->num_rx_queues; i++) {
2046                 rx_ring = &adapter->rx_ring[i];
2047                 rdba = rx_ring->dma;
2048                 j = rx_ring->reg_idx;
2049                 IXGBE_WRITE_REG(hw, IXGBE_RDBAL(j), (rdba & DMA_BIT_MASK(32)));
2050                 IXGBE_WRITE_REG(hw, IXGBE_RDBAH(j), (rdba >> 32));
2051                 IXGBE_WRITE_REG(hw, IXGBE_RDLEN(j), rdlen);
2052                 IXGBE_WRITE_REG(hw, IXGBE_RDH(j), 0);
2053                 IXGBE_WRITE_REG(hw, IXGBE_RDT(j), 0);
2054                 rx_ring->head = IXGBE_RDH(j);
2055                 rx_ring->tail = IXGBE_RDT(j);
2056                 rx_ring->rx_buf_len = rx_buf_len;
2057
2058                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
2059                         rx_ring->flags |= IXGBE_RING_RX_PS_ENABLED;
2060                 else
2061                         rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2062
2063 #ifdef IXGBE_FCOE
2064                 if (netdev->features & NETIF_F_FCOE_MTU) {
2065                         struct ixgbe_ring_feature *f;
2066                         f = &adapter->ring_feature[RING_F_FCOE];
2067                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
2068                                 rx_ring->flags &= ~IXGBE_RING_RX_PS_ENABLED;
2069                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
2070                                         rx_ring->rx_buf_len =
2071                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
2072                         }
2073                 }
2074
2075 #endif /* IXGBE_FCOE */
2076                 ixgbe_configure_srrctl(adapter, rx_ring);
2077         }
2078
2079         if (hw->mac.type == ixgbe_mac_82598EB) {
2080                 /*
2081                  * For VMDq support of different descriptor types or
2082                  * buffer sizes through the use of multiple SRRCTL
2083                  * registers, RDRXCTL.MVMEN must be set to 1
2084                  *
2085                  * also, the manual doesn't mention it clearly but DCA hints
2086                  * will only use queue 0's tags unless this bit is set.  Side
2087                  * effects of setting this bit are only that SRRCTL must be
2088                  * fully programmed [0..15]
2089                  */
2090                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2091                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
2092                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2093         }
2094
2095         /* Program MRQC for the distribution of queues */
2096         mrqc = ixgbe_setup_mrqc(adapter);
2097
2098         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
2099                 /* Fill out redirection table */
2100                 for (i = 0, j = 0; i < 128; i++, j++) {
2101                         if (j == adapter->ring_feature[RING_F_RSS].indices)
2102                                 j = 0;
2103                         /* reta = 4-byte sliding window of
2104                          * 0x00..(indices-1)(indices-1)00..etc. */
2105                         reta = (reta << 8) | (j * 0x11);
2106                         if ((i & 3) == 3)
2107                                 IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2108                 }
2109
2110                 /* Fill out hash function seeds */
2111                 for (i = 0; i < 10; i++)
2112                         IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2113
2114                 if (hw->mac.type == ixgbe_mac_82598EB)
2115                         mrqc |= IXGBE_MRQC_RSSEN;
2116                     /* Perform hash on these packet types */
2117                 mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2118                       | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2119                       | IXGBE_MRQC_RSS_FIELD_IPV4_UDP
2120                       | IXGBE_MRQC_RSS_FIELD_IPV6
2121                       | IXGBE_MRQC_RSS_FIELD_IPV6_TCP
2122                       | IXGBE_MRQC_RSS_FIELD_IPV6_UDP;
2123         }
2124         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2125
2126         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2127
2128         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED ||
2129             adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED) {
2130                 /* Disable indicating checksum in descriptor, enables
2131                  * RSS hash */
2132                 rxcsum |= IXGBE_RXCSUM_PCSD;
2133         }
2134         if (!(rxcsum & IXGBE_RXCSUM_PCSD)) {
2135                 /* Enable IPv4 payload checksum for UDP fragments
2136                  * if PCSD is not set */
2137                 rxcsum |= IXGBE_RXCSUM_IPPCSE;
2138         }
2139
2140         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2141
2142         if (hw->mac.type == ixgbe_mac_82599EB) {
2143                 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
2144                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
2145                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
2146                 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
2147         }
2148
2149         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
2150                 /* Enable 82599 HW-RSC */
2151                 for (i = 0; i < adapter->num_rx_queues; i++) {
2152                         rx_ring = &adapter->rx_ring[i];
2153                         j = rx_ring->reg_idx;
2154                         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(j));
2155                         rscctrl |= IXGBE_RSCCTL_RSCEN;
2156                         /*
2157                          * we must limit the number of descriptors so that the
2158                          * total size of max desc * buf_len is not greater
2159                          * than 65535
2160                          */
2161                         if (rx_ring->flags & IXGBE_RING_RX_PS_ENABLED) {
2162 #if (MAX_SKB_FRAGS > 16)
2163                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2164 #elif (MAX_SKB_FRAGS > 8)
2165                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2166 #elif (MAX_SKB_FRAGS > 4)
2167                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2168 #else
2169                                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2170 #endif
2171                         } else {
2172                                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2173                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2174                                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2175                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2176                                 else
2177                                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2178                         }
2179                         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(j), rscctrl);
2180                 }
2181                 /* Disable RSC for ACK packets */
2182                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
2183                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
2184         }
2185 }
2186
2187 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
2188 {
2189         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2190         struct ixgbe_hw *hw = &adapter->hw;
2191
2192         /* add VID to filter table */
2193         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, true);
2194 }
2195
2196 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
2197 {
2198         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2199         struct ixgbe_hw *hw = &adapter->hw;
2200
2201         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2202                 ixgbe_irq_disable(adapter);
2203
2204         vlan_group_set_device(adapter->vlgrp, vid, NULL);
2205
2206         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2207                 ixgbe_irq_enable(adapter);
2208
2209         /* remove VID from filter table */
2210         hw->mac.ops.set_vfta(&adapter->hw, vid, 0, false);
2211 }
2212
2213 static void ixgbe_vlan_rx_register(struct net_device *netdev,
2214                                    struct vlan_group *grp)
2215 {
2216         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2217         u32 ctrl;
2218         int i, j;
2219
2220         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2221                 ixgbe_irq_disable(adapter);
2222         adapter->vlgrp = grp;
2223
2224         /*
2225          * For a DCB driver, always enable VLAN tag stripping so we can
2226          * still receive traffic from a DCB-enabled host even if we're
2227          * not in DCB mode.
2228          */
2229         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2230         if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
2231                 ctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2232                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2233                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2234         } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
2235                 ctrl |= IXGBE_VLNCTRL_VFE;
2236                 /* enable VLAN tag insert/strip */
2237                 ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_VLNCTRL);
2238                 ctrl &= ~IXGBE_VLNCTRL_CFIEN;
2239                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_VLNCTRL, ctrl);
2240                 for (i = 0; i < adapter->num_rx_queues; i++) {
2241                         j = adapter->rx_ring[i].reg_idx;
2242                         ctrl = IXGBE_READ_REG(&adapter->hw, IXGBE_RXDCTL(j));
2243                         ctrl |= IXGBE_RXDCTL_VME;
2244                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_RXDCTL(j), ctrl);
2245                 }
2246         }
2247         ixgbe_vlan_rx_add_vid(netdev, 0);
2248
2249         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2250                 ixgbe_irq_enable(adapter);
2251 }
2252
2253 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
2254 {
2255         ixgbe_vlan_rx_register(adapter->netdev, adapter->vlgrp);
2256
2257         if (adapter->vlgrp) {
2258                 u16 vid;
2259                 for (vid = 0; vid < VLAN_GROUP_ARRAY_LEN; vid++) {
2260                         if (!vlan_group_get_device(adapter->vlgrp, vid))
2261                                 continue;
2262                         ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
2263                 }
2264         }
2265 }
2266
2267 static u8 *ixgbe_addr_list_itr(struct ixgbe_hw *hw, u8 **mc_addr_ptr, u32 *vmdq)
2268 {
2269         struct dev_mc_list *mc_ptr;
2270         u8 *addr = *mc_addr_ptr;
2271         *vmdq = 0;
2272
2273         mc_ptr = container_of(addr, struct dev_mc_list, dmi_addr[0]);
2274         if (mc_ptr->next)
2275                 *mc_addr_ptr = mc_ptr->next->dmi_addr;
2276         else
2277                 *mc_addr_ptr = NULL;
2278
2279         return addr;
2280 }
2281
2282 /**
2283  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
2284  * @netdev: network interface device structure
2285  *
2286  * The set_rx_method entry point is called whenever the unicast/multicast
2287  * address list or the network interface flags are updated.  This routine is
2288  * responsible for configuring the hardware for proper unicast, multicast and
2289  * promiscuous mode.
2290  **/
2291 static void ixgbe_set_rx_mode(struct net_device *netdev)
2292 {
2293         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2294         struct ixgbe_hw *hw = &adapter->hw;
2295         u32 fctrl, vlnctrl;
2296         u8 *addr_list = NULL;
2297         int addr_count = 0;
2298
2299         /* Check for Promiscuous and All Multicast modes */
2300
2301         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
2302         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2303
2304         if (netdev->flags & IFF_PROMISC) {
2305                 hw->addr_ctrl.user_set_promisc = 1;
2306                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2307                 vlnctrl &= ~IXGBE_VLNCTRL_VFE;
2308         } else {
2309                 if (netdev->flags & IFF_ALLMULTI) {
2310                         fctrl |= IXGBE_FCTRL_MPE;
2311                         fctrl &= ~IXGBE_FCTRL_UPE;
2312                 } else {
2313                         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
2314                 }
2315                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2316                 hw->addr_ctrl.user_set_promisc = 0;
2317         }
2318
2319         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
2320         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2321
2322         /* reprogram secondary unicast list */
2323         hw->mac.ops.update_uc_addr_list(hw, &netdev->uc.list);
2324
2325         /* reprogram multicast list */
2326         addr_count = netdev->mc_count;
2327         if (addr_count)
2328                 addr_list = netdev->mc_list->dmi_addr;
2329         hw->mac.ops.update_mc_addr_list(hw, addr_list, addr_count,
2330                                         ixgbe_addr_list_itr);
2331 }
2332
2333 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
2334 {
2335         int q_idx;
2336         struct ixgbe_q_vector *q_vector;
2337         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2338
2339         /* legacy and MSI only use one vector */
2340         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2341                 q_vectors = 1;
2342
2343         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2344                 struct napi_struct *napi;
2345                 q_vector = adapter->q_vector[q_idx];
2346                 napi = &q_vector->napi;
2347                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2348                         if (!q_vector->rxr_count || !q_vector->txr_count) {
2349                                 if (q_vector->txr_count == 1)
2350                                         napi->poll = &ixgbe_clean_txonly;
2351                                 else if (q_vector->rxr_count == 1)
2352                                         napi->poll = &ixgbe_clean_rxonly;
2353                         }
2354                 }
2355
2356                 napi_enable(napi);
2357         }
2358 }
2359
2360 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
2361 {
2362         int q_idx;
2363         struct ixgbe_q_vector *q_vector;
2364         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2365
2366         /* legacy and MSI only use one vector */
2367         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2368                 q_vectors = 1;
2369
2370         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
2371                 q_vector = adapter->q_vector[q_idx];
2372                 napi_disable(&q_vector->napi);
2373         }
2374 }
2375
2376 #ifdef CONFIG_IXGBE_DCB
2377 /*
2378  * ixgbe_configure_dcb - Configure DCB hardware
2379  * @adapter: ixgbe adapter struct
2380  *
2381  * This is called by the driver on open to configure the DCB hardware.
2382  * This is also called by the gennetlink interface when reconfiguring
2383  * the DCB state.
2384  */
2385 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
2386 {
2387         struct ixgbe_hw *hw = &adapter->hw;
2388         u32 txdctl, vlnctrl;
2389         int i, j;
2390
2391         ixgbe_dcb_check_config(&adapter->dcb_cfg);
2392         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_TX_CONFIG);
2393         ixgbe_dcb_calculate_tc_credits(&adapter->dcb_cfg, DCB_RX_CONFIG);
2394
2395         /* reconfigure the hardware */
2396         ixgbe_dcb_hw_config(&adapter->hw, &adapter->dcb_cfg);
2397
2398         for (i = 0; i < adapter->num_tx_queues; i++) {
2399                 j = adapter->tx_ring[i].reg_idx;
2400                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2401                 /* PThresh workaround for Tx hang with DFP enabled. */
2402                 txdctl |= 32;
2403                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2404         }
2405         /* Enable VLAN tag insert/strip */
2406         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
2407         if (hw->mac.type == ixgbe_mac_82598EB) {
2408                 vlnctrl |= IXGBE_VLNCTRL_VME | IXGBE_VLNCTRL_VFE;
2409                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2410                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2411         } else if (hw->mac.type == ixgbe_mac_82599EB) {
2412                 vlnctrl |= IXGBE_VLNCTRL_VFE;
2413                 vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
2414                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
2415                 for (i = 0; i < adapter->num_rx_queues; i++) {
2416                         j = adapter->rx_ring[i].reg_idx;
2417                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2418                         vlnctrl |= IXGBE_RXDCTL_VME;
2419                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
2420                 }
2421         }
2422         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
2423 }
2424
2425 #endif
2426 static void ixgbe_configure(struct ixgbe_adapter *adapter)
2427 {
2428         struct net_device *netdev = adapter->netdev;
2429         struct ixgbe_hw *hw = &adapter->hw;
2430         int i;
2431
2432         ixgbe_set_rx_mode(netdev);
2433
2434         ixgbe_restore_vlan(adapter);
2435 #ifdef CONFIG_IXGBE_DCB
2436         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2437                 netif_set_gso_max_size(netdev, 32768);
2438                 ixgbe_configure_dcb(adapter);
2439         } else {
2440                 netif_set_gso_max_size(netdev, 65536);
2441         }
2442 #else
2443         netif_set_gso_max_size(netdev, 65536);
2444 #endif
2445
2446 #ifdef IXGBE_FCOE
2447         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
2448                 ixgbe_configure_fcoe(adapter);
2449
2450 #endif /* IXGBE_FCOE */
2451         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
2452                 for (i = 0; i < adapter->num_tx_queues; i++)
2453                         adapter->tx_ring[i].atr_sample_rate =
2454                                                        adapter->atr_sample_rate;
2455                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
2456         } else if (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE) {
2457                 ixgbe_init_fdir_perfect_82599(hw, adapter->fdir_pballoc);
2458         }
2459
2460         ixgbe_configure_tx(adapter);
2461         ixgbe_configure_rx(adapter);
2462         for (i = 0; i < adapter->num_rx_queues; i++)
2463                 ixgbe_alloc_rx_buffers(adapter, &adapter->rx_ring[i],
2464                                        (adapter->rx_ring[i].count - 1));
2465 }
2466
2467 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
2468 {
2469         switch (hw->phy.type) {
2470         case ixgbe_phy_sfp_avago:
2471         case ixgbe_phy_sfp_ftl:
2472         case ixgbe_phy_sfp_intel:
2473         case ixgbe_phy_sfp_unknown:
2474         case ixgbe_phy_tw_tyco:
2475         case ixgbe_phy_tw_unknown:
2476                 return true;
2477         default:
2478                 return false;
2479         }
2480 }
2481
2482 /**
2483  * ixgbe_sfp_link_config - set up SFP+ link
2484  * @adapter: pointer to private adapter struct
2485  **/
2486 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
2487 {
2488         struct ixgbe_hw *hw = &adapter->hw;
2489
2490                 if (hw->phy.multispeed_fiber) {
2491                         /*
2492                          * In multispeed fiber setups, the device may not have
2493                          * had a physical connection when the driver loaded.
2494                          * If that's the case, the initial link configuration
2495                          * couldn't get the MAC into 10G or 1G mode, so we'll
2496                          * never have a link status change interrupt fire.
2497                          * We need to try and force an autonegotiation
2498                          * session, then bring up link.
2499                          */
2500                         hw->mac.ops.setup_sfp(hw);
2501                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
2502                                 schedule_work(&adapter->multispeed_fiber_task);
2503                 } else {
2504                         /*
2505                          * Direct Attach Cu and non-multispeed fiber modules
2506                          * still need to be configured properly prior to
2507                          * attempting link.
2508                          */
2509                         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_MOD_TASK))
2510                                 schedule_work(&adapter->sfp_config_module_task);
2511                 }
2512 }
2513
2514 /**
2515  * ixgbe_non_sfp_link_config - set up non-SFP+ link
2516  * @hw: pointer to private hardware struct
2517  *
2518  * Returns 0 on success, negative on failure
2519  **/
2520 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
2521 {
2522         u32 autoneg;
2523         bool negotiation, link_up = false;
2524         u32 ret = IXGBE_ERR_LINK_SETUP;
2525
2526         if (hw->mac.ops.check_link)
2527                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
2528
2529         if (ret)
2530                 goto link_cfg_out;
2531
2532         if (hw->mac.ops.get_link_capabilities)
2533                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
2534         if (ret)
2535                 goto link_cfg_out;
2536
2537         if (hw->mac.ops.setup_link)
2538                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
2539 link_cfg_out:
2540         return ret;
2541 }
2542
2543 #define IXGBE_MAX_RX_DESC_POLL 10
2544 static inline void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
2545                                               int rxr)
2546 {
2547         int j = adapter->rx_ring[rxr].reg_idx;
2548         int k;
2549
2550         for (k = 0; k < IXGBE_MAX_RX_DESC_POLL; k++) {
2551                 if (IXGBE_READ_REG(&adapter->hw,
2552                                    IXGBE_RXDCTL(j)) & IXGBE_RXDCTL_ENABLE)
2553                         break;
2554                 else
2555                         msleep(1);
2556         }
2557         if (k >= IXGBE_MAX_RX_DESC_POLL) {
2558                 DPRINTK(DRV, ERR, "RXDCTL.ENABLE on Rx queue %d "
2559                         "not set within the polling period\n", rxr);
2560         }
2561         ixgbe_release_rx_desc(&adapter->hw, &adapter->rx_ring[rxr],
2562                               (adapter->rx_ring[rxr].count - 1));
2563 }
2564
2565 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
2566 {
2567         struct net_device *netdev = adapter->netdev;
2568         struct ixgbe_hw *hw = &adapter->hw;
2569         int i, j = 0;
2570         int num_rx_rings = adapter->num_rx_queues;
2571         int err;
2572         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
2573         u32 txdctl, rxdctl, mhadd;
2574         u32 dmatxctl;
2575         u32 gpie;
2576
2577         ixgbe_get_hw_control(adapter);
2578
2579         if ((adapter->flags & IXGBE_FLAG_MSIX_ENABLED) ||
2580             (adapter->flags & IXGBE_FLAG_MSI_ENABLED)) {
2581                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2582                         gpie = (IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_EIAME |
2583                                 IXGBE_GPIE_PBA_SUPPORT | IXGBE_GPIE_OCD);
2584                 } else {
2585                         /* MSI only */
2586                         gpie = 0;
2587                 }
2588                 /* XXX: to interrupt immediately for EICS writes, enable this */
2589                 /* gpie |= IXGBE_GPIE_EIMEN; */
2590                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2591         }
2592
2593         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
2594                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
2595                  * specifically only auto mask tx and rx interrupts */
2596                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
2597         }
2598
2599         /* Enable fan failure interrupt if media type is copper */
2600         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2601                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2602                 gpie |= IXGBE_SDP1_GPIEN;
2603                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2604         }
2605
2606         if (hw->mac.type == ixgbe_mac_82599EB) {
2607                 gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
2608                 gpie |= IXGBE_SDP1_GPIEN;
2609                 gpie |= IXGBE_SDP2_GPIEN;
2610                 IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
2611         }
2612
2613 #ifdef IXGBE_FCOE
2614         /* adjust max frame to be able to do baby jumbo for FCoE */
2615         if ((netdev->features & NETIF_F_FCOE_MTU) &&
2616             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
2617                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
2618
2619 #endif /* IXGBE_FCOE */
2620         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
2621         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
2622                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
2623                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
2624
2625                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
2626         }
2627
2628         for (i = 0; i < adapter->num_tx_queues; i++) {
2629                 j = adapter->tx_ring[i].reg_idx;
2630                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2631                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2632                 txdctl |= (8 << 16);
2633                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2634         }
2635
2636         if (hw->mac.type == ixgbe_mac_82599EB) {
2637                 /* DMATXCTL.EN must be set after all Tx queue config is done */
2638                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2639                 dmatxctl |= IXGBE_DMATXCTL_TE;
2640                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2641         }
2642         for (i = 0; i < adapter->num_tx_queues; i++) {
2643                 j = adapter->tx_ring[i].reg_idx;
2644                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2645                 txdctl |= IXGBE_TXDCTL_ENABLE;
2646                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j), txdctl);
2647         }
2648
2649         for (i = 0; i < num_rx_rings; i++) {
2650                 j = adapter->rx_ring[i].reg_idx;
2651                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
2652                 /* enable PTHRESH=32 descriptors (half the internal cache)
2653                  * and HTHRESH=0 descriptors (to minimize latency on fetch),
2654                  * this also removes a pesky rx_no_buffer_count increment */
2655                 rxdctl |= 0x0020;
2656                 rxdctl |= IXGBE_RXDCTL_ENABLE;
2657                 IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), rxdctl);
2658                 if (hw->mac.type == ixgbe_mac_82599EB)
2659                         ixgbe_rx_desc_queue_enable(adapter, i);
2660         }
2661         /* enable all receives */
2662         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2663         if (hw->mac.type == ixgbe_mac_82598EB)
2664                 rxdctl |= (IXGBE_RXCTRL_DMBYPS | IXGBE_RXCTRL_RXEN);
2665         else
2666                 rxdctl |= IXGBE_RXCTRL_RXEN;
2667         hw->mac.ops.enable_rx_dma(hw, rxdctl);
2668
2669         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
2670                 ixgbe_configure_msix(adapter);
2671         else
2672                 ixgbe_configure_msi_and_legacy(adapter);
2673
2674         clear_bit(__IXGBE_DOWN, &adapter->state);
2675         ixgbe_napi_enable_all(adapter);
2676
2677         /* clear any pending interrupts, may auto mask */
2678         IXGBE_READ_REG(hw, IXGBE_EICR);
2679
2680         ixgbe_irq_enable(adapter);
2681
2682         /*
2683          * If this adapter has a fan, check to see if we had a failure
2684          * before we enabled the interrupt.
2685          */
2686         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
2687                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
2688                 if (esdp & IXGBE_ESDP_SDP1)
2689                         DPRINTK(DRV, CRIT,
2690                                 "Fan has stopped, replace the adapter\n");
2691         }
2692
2693         /*
2694          * For hot-pluggable SFP+ devices, a new SFP+ module may have
2695          * arrived before interrupts were enabled but after probe.  Such
2696          * devices wouldn't have their type identified yet. We need to
2697          * kick off the SFP+ module setup first, then try to bring up link.
2698          * If we're not hot-pluggable SFP+, we just need to configure link
2699          * and bring it up.
2700          */
2701         if (hw->phy.type == ixgbe_phy_unknown) {
2702                 err = hw->phy.ops.identify(hw);
2703                 if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
2704                         /*
2705                          * Take the device down and schedule the sfp tasklet
2706                          * which will unregister_netdev and log it.
2707                          */
2708                         ixgbe_down(adapter);
2709                         schedule_work(&adapter->sfp_config_module_task);
2710                         return err;
2711                 }
2712         }
2713
2714         if (ixgbe_is_sfp(hw)) {
2715                 ixgbe_sfp_link_config(adapter);
2716         } else {
2717                 err = ixgbe_non_sfp_link_config(hw);
2718                 if (err)
2719                         DPRINTK(PROBE, ERR, "link_config FAILED %d\n", err);
2720         }
2721
2722         for (i = 0; i < adapter->num_tx_queues; i++)
2723                 set_bit(__IXGBE_FDIR_INIT_DONE,
2724                         &(adapter->tx_ring[i].reinit_state));
2725
2726         /* enable transmits */
2727         netif_tx_start_all_queues(netdev);
2728
2729         /* bring the link up in the watchdog, this could race with our first
2730          * link up interrupt but shouldn't be a problem */
2731         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
2732         adapter->link_check_timeout = jiffies;
2733         mod_timer(&adapter->watchdog_timer, jiffies);
2734         return 0;
2735 }
2736
2737 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
2738 {
2739         WARN_ON(in_interrupt());
2740         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
2741                 msleep(1);
2742         ixgbe_down(adapter);
2743         ixgbe_up(adapter);
2744         clear_bit(__IXGBE_RESETTING, &adapter->state);
2745 }
2746
2747 int ixgbe_up(struct ixgbe_adapter *adapter)
2748 {
2749         /* hardware has been reset, we need to reload some things */
2750         ixgbe_configure(adapter);
2751
2752         return ixgbe_up_complete(adapter);
2753 }
2754
2755 void ixgbe_reset(struct ixgbe_adapter *adapter)
2756 {
2757         struct ixgbe_hw *hw = &adapter->hw;
2758         int err;
2759
2760         err = hw->mac.ops.init_hw(hw);
2761         switch (err) {
2762         case 0:
2763         case IXGBE_ERR_SFP_NOT_PRESENT:
2764                 break;
2765         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
2766                 dev_err(&adapter->pdev->dev, "master disable timed out\n");
2767                 break;
2768         case IXGBE_ERR_EEPROM_VERSION:
2769                 /* We are running on a pre-production device, log a warning */
2770                 dev_warn(&adapter->pdev->dev, "This device is a pre-production "
2771                          "adapter/LOM.  Please be aware there may be issues "
2772                          "associated with your hardware.  If you are "
2773                          "experiencing problems please contact your Intel or "
2774                          "hardware representative who provided you with this "
2775                          "hardware.\n");
2776                 break;
2777         default:
2778                 dev_err(&adapter->pdev->dev, "Hardware Error: %d\n", err);
2779         }
2780
2781         /* reprogram the RAR[0] in case user changed it. */
2782         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
2783 }
2784
2785 /**
2786  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
2787  * @adapter: board private structure
2788  * @rx_ring: ring to free buffers from
2789  **/
2790 static void ixgbe_clean_rx_ring(struct ixgbe_adapter *adapter,
2791                                 struct ixgbe_ring *rx_ring)
2792 {
2793         struct pci_dev *pdev = adapter->pdev;
2794         unsigned long size;
2795         unsigned int i;
2796
2797         /* Free all the Rx ring sk_buffs */
2798
2799         for (i = 0; i < rx_ring->count; i++) {
2800                 struct ixgbe_rx_buffer *rx_buffer_info;
2801
2802                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
2803                 if (rx_buffer_info->dma) {
2804                         pci_unmap_single(pdev, rx_buffer_info->dma,
2805                                          rx_ring->rx_buf_len,
2806                                          PCI_DMA_FROMDEVICE);
2807                         rx_buffer_info->dma = 0;
2808                 }
2809                 if (rx_buffer_info->skb) {
2810                         struct sk_buff *skb = rx_buffer_info->skb;
2811                         rx_buffer_info->skb = NULL;
2812                         do {
2813                                 struct sk_buff *this = skb;
2814                                 skb = skb->prev;
2815                                 dev_kfree_skb(this);
2816                         } while (skb);
2817                 }
2818                 if (!rx_buffer_info->page)
2819                         continue;
2820                 if (rx_buffer_info->page_dma) {
2821                         pci_unmap_page(pdev, rx_buffer_info->page_dma,
2822                                        PAGE_SIZE / 2, PCI_DMA_FROMDEVICE);
2823                         rx_buffer_info->page_dma = 0;
2824                 }
2825                 put_page(rx_buffer_info->page);
2826                 rx_buffer_info->page = NULL;
2827                 rx_buffer_info->page_offset = 0;
2828         }
2829
2830         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
2831         memset(rx_ring->rx_buffer_info, 0, size);
2832
2833         /* Zero out the descriptor ring */
2834         memset(rx_ring->desc, 0, rx_ring->size);
2835
2836         rx_ring->next_to_clean = 0;
2837         rx_ring->next_to_use = 0;
2838
2839         if (rx_ring->head)
2840                 writel(0, adapter->hw.hw_addr + rx_ring->head);
2841         if (rx_ring->tail)
2842                 writel(0, adapter->hw.hw_addr + rx_ring->tail);
2843 }
2844
2845 /**
2846  * ixgbe_clean_tx_ring - Free Tx Buffers
2847  * @adapter: board private structure
2848  * @tx_ring: ring to be cleaned
2849  **/
2850 static void ixgbe_clean_tx_ring(struct ixgbe_adapter *adapter,
2851                                 struct ixgbe_ring *tx_ring)
2852 {
2853         struct ixgbe_tx_buffer *tx_buffer_info;
2854         unsigned long size;
2855         unsigned int i;
2856
2857         /* Free all the Tx ring sk_buffs */
2858
2859         for (i = 0; i < tx_ring->count; i++) {
2860                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
2861                 ixgbe_unmap_and_free_tx_resource(adapter, tx_buffer_info);
2862         }
2863
2864         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
2865         memset(tx_ring->tx_buffer_info, 0, size);
2866
2867         /* Zero out the descriptor ring */
2868         memset(tx_ring->desc, 0, tx_ring->size);
2869
2870         tx_ring->next_to_use = 0;
2871         tx_ring->next_to_clean = 0;
2872
2873         if (tx_ring->head)
2874                 writel(0, adapter->hw.hw_addr + tx_ring->head);
2875         if (tx_ring->tail)
2876                 writel(0, adapter->hw.hw_addr + tx_ring->tail);
2877 }
2878
2879 /**
2880  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
2881  * @adapter: board private structure
2882  **/
2883 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
2884 {
2885         int i;
2886
2887         for (i = 0; i < adapter->num_rx_queues; i++)
2888                 ixgbe_clean_rx_ring(adapter, &adapter->rx_ring[i]);
2889 }
2890
2891 /**
2892  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
2893  * @adapter: board private structure
2894  **/
2895 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
2896 {
2897         int i;
2898
2899         for (i = 0; i < adapter->num_tx_queues; i++)
2900                 ixgbe_clean_tx_ring(adapter, &adapter->tx_ring[i]);
2901 }
2902
2903 void ixgbe_down(struct ixgbe_adapter *adapter)
2904 {
2905         struct net_device *netdev = adapter->netdev;
2906         struct ixgbe_hw *hw = &adapter->hw;
2907         u32 rxctrl;
2908         u32 txdctl;
2909         int i, j;
2910
2911         /* signal that we are down to the interrupt handler */
2912         set_bit(__IXGBE_DOWN, &adapter->state);
2913
2914         /* disable receives */
2915         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
2916         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
2917
2918         netif_tx_disable(netdev);
2919
2920         IXGBE_WRITE_FLUSH(hw);
2921         msleep(10);
2922
2923         netif_tx_stop_all_queues(netdev);
2924
2925         ixgbe_irq_disable(adapter);
2926
2927         ixgbe_napi_disable_all(adapter);
2928
2929         del_timer_sync(&adapter->watchdog_timer);
2930         cancel_work_sync(&adapter->watchdog_task);
2931
2932         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
2933             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
2934                 cancel_work_sync(&adapter->fdir_reinit_task);
2935
2936         /* disable transmits in the hardware now that interrupts are off */
2937         for (i = 0; i < adapter->num_tx_queues; i++) {
2938                 j = adapter->tx_ring[i].reg_idx;
2939                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(j));
2940                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(j),
2941                                 (txdctl & ~IXGBE_TXDCTL_ENABLE));
2942         }
2943         /* Disable the Tx DMA engine on 82599 */
2944         if (hw->mac.type == ixgbe_mac_82599EB)
2945                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
2946                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
2947                                  ~IXGBE_DMATXCTL_TE));
2948
2949         netif_carrier_off(netdev);
2950
2951         if (!pci_channel_offline(adapter->pdev))
2952                 ixgbe_reset(adapter);
2953         ixgbe_clean_all_tx_rings(adapter);
2954         ixgbe_clean_all_rx_rings(adapter);
2955
2956 #ifdef CONFIG_IXGBE_DCA
2957         /* since we reset the hardware DCA settings were cleared */
2958         ixgbe_setup_dca(adapter);
2959 #endif
2960 }
2961
2962 /**
2963  * ixgbe_poll - NAPI Rx polling callback
2964  * @napi: structure for representing this polling device
2965  * @budget: how many packets driver is allowed to clean
2966  *
2967  * This function is used for legacy and MSI, NAPI mode
2968  **/
2969 static int ixgbe_poll(struct napi_struct *napi, int budget)
2970 {
2971         struct ixgbe_q_vector *q_vector =
2972                                 container_of(napi, struct ixgbe_q_vector, napi);
2973         struct ixgbe_adapter *adapter = q_vector->adapter;
2974         int tx_clean_complete, work_done = 0;
2975
2976 #ifdef CONFIG_IXGBE_DCA
2977         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
2978                 ixgbe_update_tx_dca(adapter, adapter->tx_ring);
2979                 ixgbe_update_rx_dca(adapter, adapter->rx_ring);
2980         }
2981 #endif
2982
2983         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring);
2984         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring, &work_done, budget);
2985
2986         if (!tx_clean_complete)
2987                 work_done = budget;
2988
2989         /* If budget not fully consumed, exit the polling mode */
2990         if (work_done < budget) {
2991                 napi_complete(napi);
2992                 if (adapter->itr_setting & 1)
2993                         ixgbe_set_itr(adapter);
2994                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2995                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
2996         }
2997         return work_done;
2998 }
2999
3000 /**
3001  * ixgbe_tx_timeout - Respond to a Tx Hang
3002  * @netdev: network interface device structure
3003  **/
3004 static void ixgbe_tx_timeout(struct net_device *netdev)
3005 {
3006         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3007
3008         /* Do the reset outside of interrupt context */
3009         schedule_work(&adapter->reset_task);
3010 }
3011
3012 static void ixgbe_reset_task(struct work_struct *work)
3013 {
3014         struct ixgbe_adapter *adapter;
3015         adapter = container_of(work, struct ixgbe_adapter, reset_task);
3016
3017         /* If we're already down or resetting, just bail */
3018         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
3019             test_bit(__IXGBE_RESETTING, &adapter->state))
3020                 return;
3021
3022         adapter->tx_timeout_count++;
3023
3024         ixgbe_reinit_locked(adapter);
3025 }
3026
3027 #ifdef CONFIG_IXGBE_DCB
3028 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
3029 {
3030         bool ret = false;
3031         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_DCB];
3032
3033         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED))
3034                 return ret;
3035
3036         f->mask = 0x7 << 3;
3037         adapter->num_rx_queues = f->indices;
3038         adapter->num_tx_queues = f->indices;
3039         ret = true;
3040
3041         return ret;
3042 }
3043 #endif
3044
3045 /**
3046  * ixgbe_set_rss_queues: Allocate queues for RSS
3047  * @adapter: board private structure to initialize
3048  *
3049  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
3050  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
3051  *
3052  **/
3053 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
3054 {
3055         bool ret = false;
3056         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
3057
3058         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3059                 f->mask = 0xF;
3060                 adapter->num_rx_queues = f->indices;
3061                 adapter->num_tx_queues = f->indices;
3062                 ret = true;
3063         } else {
3064                 ret = false;
3065         }
3066
3067         return ret;
3068 }
3069
3070 /**
3071  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
3072  * @adapter: board private structure to initialize
3073  *
3074  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
3075  * to the original CPU that initiated the Tx session.  This runs in addition
3076  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
3077  * Rx load across CPUs using RSS.
3078  *
3079  **/
3080 static bool inline ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
3081 {
3082         bool ret = false;
3083         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
3084
3085         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
3086         f_fdir->mask = 0;
3087
3088         /* Flow Director must have RSS enabled */
3089         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3090             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3091              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)))) {
3092                 adapter->num_tx_queues = f_fdir->indices;
3093                 adapter->num_rx_queues = f_fdir->indices;
3094                 ret = true;
3095         } else {
3096                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3097                 adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3098         }
3099         return ret;
3100 }
3101
3102 #ifdef IXGBE_FCOE
3103 /**
3104  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
3105  * @adapter: board private structure to initialize
3106  *
3107  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
3108  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
3109  * rx queues out of the max number of rx queues, instead, it is used as the
3110  * index of the first rx queue used by FCoE.
3111  *
3112  **/
3113 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
3114 {
3115         bool ret = false;
3116         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3117
3118         f->indices = min((int)num_online_cpus(), f->indices);
3119         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3120                 adapter->num_rx_queues = 1;
3121                 adapter->num_tx_queues = 1;
3122 #ifdef CONFIG_IXGBE_DCB
3123                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3124                         DPRINTK(PROBE, INFO, "FCoE enabled with DCB \n");
3125                         ixgbe_set_dcb_queues(adapter);
3126                 }
3127 #endif
3128                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3129                         DPRINTK(PROBE, INFO, "FCoE enabled with RSS \n");
3130                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3131                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3132                                 ixgbe_set_fdir_queues(adapter);
3133                         else
3134                                 ixgbe_set_rss_queues(adapter);
3135                 }
3136                 /* adding FCoE rx rings to the end */
3137                 f->mask = adapter->num_rx_queues;
3138                 adapter->num_rx_queues += f->indices;
3139                 adapter->num_tx_queues += f->indices;
3140
3141                 ret = true;
3142         }
3143
3144         return ret;
3145 }
3146
3147 #endif /* IXGBE_FCOE */
3148 /*
3149  * ixgbe_set_num_queues: Allocate queues for device, feature dependant
3150  * @adapter: board private structure to initialize
3151  *
3152  * This is the top level queue allocation routine.  The order here is very
3153  * important, starting with the "most" number of features turned on at once,
3154  * and ending with the smallest set of features.  This way large combinations
3155  * can be allocated if they're turned on, and smaller combinations are the
3156  * fallthrough conditions.
3157  *
3158  **/
3159 static void ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
3160 {
3161 #ifdef IXGBE_FCOE
3162         if (ixgbe_set_fcoe_queues(adapter))
3163                 goto done;
3164
3165 #endif /* IXGBE_FCOE */
3166 #ifdef CONFIG_IXGBE_DCB
3167         if (ixgbe_set_dcb_queues(adapter))
3168                 goto done;
3169
3170 #endif
3171         if (ixgbe_set_fdir_queues(adapter))
3172                 goto done;
3173
3174         if (ixgbe_set_rss_queues(adapter))
3175                 goto done;
3176
3177         /* fallback to base case */
3178         adapter->num_rx_queues = 1;
3179         adapter->num_tx_queues = 1;
3180
3181 done:
3182         /* Notify the stack of the (possibly) reduced Tx Queue count. */
3183         adapter->netdev->real_num_tx_queues = adapter->num_tx_queues;
3184 }
3185
3186 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
3187                                        int vectors)
3188 {
3189         int err, vector_threshold;
3190
3191         /* We'll want at least 3 (vector_threshold):
3192          * 1) TxQ[0] Cleanup
3193          * 2) RxQ[0] Cleanup
3194          * 3) Other (Link Status Change, etc.)
3195          * 4) TCP Timer (optional)
3196          */
3197         vector_threshold = MIN_MSIX_COUNT;
3198
3199         /* The more we get, the more we will assign to Tx/Rx Cleanup
3200          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
3201          * Right now, we simply care about how many we'll get; we'll
3202          * set them up later while requesting irq's.
3203          */
3204         while (vectors >= vector_threshold) {
3205                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
3206                                       vectors);
3207                 if (!err) /* Success in acquiring all requested vectors. */
3208                         break;
3209                 else if (err < 0)
3210                         vectors = 0; /* Nasty failure, quit now */
3211                 else /* err == number of vectors we should try again with */
3212                         vectors = err;
3213         }
3214
3215         if (vectors < vector_threshold) {
3216                 /* Can't allocate enough MSI-X interrupts?  Oh well.
3217                  * This just means we'll go with either a single MSI
3218                  * vector or fall back to legacy interrupts.
3219                  */
3220                 DPRINTK(HW, DEBUG, "Unable to allocate MSI-X interrupts\n");
3221                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3222                 kfree(adapter->msix_entries);
3223                 adapter->msix_entries = NULL;
3224         } else {
3225                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
3226                 /*
3227                  * Adjust for only the vectors we'll use, which is minimum
3228                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
3229                  * vectors we were allocated.
3230                  */
3231                 adapter->num_msix_vectors = min(vectors,
3232                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
3233         }
3234 }
3235
3236 /**
3237  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
3238  * @adapter: board private structure to initialize
3239  *
3240  * Cache the descriptor ring offsets for RSS to the assigned rings.
3241  *
3242  **/
3243 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
3244 {
3245         int i;
3246         bool ret = false;
3247
3248         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3249                 for (i = 0; i < adapter->num_rx_queues; i++)
3250                         adapter->rx_ring[i].reg_idx = i;
3251                 for (i = 0; i < adapter->num_tx_queues; i++)
3252                         adapter->tx_ring[i].reg_idx = i;
3253                 ret = true;
3254         } else {
3255                 ret = false;
3256         }
3257
3258         return ret;
3259 }
3260
3261 #ifdef CONFIG_IXGBE_DCB
3262 /**
3263  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
3264  * @adapter: board private structure to initialize
3265  *
3266  * Cache the descriptor ring offsets for DCB to the assigned rings.
3267  *
3268  **/
3269 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
3270 {
3271         int i;
3272         bool ret = false;
3273         int dcb_i = adapter->ring_feature[RING_F_DCB].indices;
3274
3275         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3276                 if (adapter->hw.mac.type == ixgbe_mac_82598EB) {
3277                         /* the number of queues is assumed to be symmetric */
3278                         for (i = 0; i < dcb_i; i++) {
3279                                 adapter->rx_ring[i].reg_idx = i << 3;
3280                                 adapter->tx_ring[i].reg_idx = i << 2;
3281                         }
3282                         ret = true;
3283                 } else if (adapter->hw.mac.type == ixgbe_mac_82599EB) {
3284                         if (dcb_i == 8) {
3285                                 /*
3286                                  * Tx TC0 starts at: descriptor queue 0
3287                                  * Tx TC1 starts at: descriptor queue 32
3288                                  * Tx TC2 starts at: descriptor queue 64
3289                                  * Tx TC3 starts at: descriptor queue 80
3290                                  * Tx TC4 starts at: descriptor queue 96
3291                                  * Tx TC5 starts at: descriptor queue 104
3292                                  * Tx TC6 starts at: descriptor queue 112
3293                                  * Tx TC7 starts at: descriptor queue 120
3294                                  *
3295                                  * Rx TC0-TC7 are offset by 16 queues each
3296                                  */
3297                                 for (i = 0; i < 3; i++) {
3298                                         adapter->tx_ring[i].reg_idx = i << 5;
3299                                         adapter->rx_ring[i].reg_idx = i << 4;
3300                                 }
3301                                 for ( ; i < 5; i++) {
3302                                         adapter->tx_ring[i].reg_idx =
3303                                                                  ((i + 2) << 4);
3304                                         adapter->rx_ring[i].reg_idx = i << 4;
3305                                 }
3306                                 for ( ; i < dcb_i; i++) {
3307                                         adapter->tx_ring[i].reg_idx =
3308                                                                  ((i + 8) << 3);
3309                                         adapter->rx_ring[i].reg_idx = i << 4;
3310                                 }
3311
3312                                 ret = true;
3313                         } else if (dcb_i == 4) {
3314                                 /*
3315                                  * Tx TC0 starts at: descriptor queue 0
3316                                  * Tx TC1 starts at: descriptor queue 64
3317                                  * Tx TC2 starts at: descriptor queue 96
3318                                  * Tx TC3 starts at: descriptor queue 112
3319                                  *
3320                                  * Rx TC0-TC3 are offset by 32 queues each
3321                                  */
3322                                 adapter->tx_ring[0].reg_idx = 0;
3323                                 adapter->tx_ring[1].reg_idx = 64;
3324                                 adapter->tx_ring[2].reg_idx = 96;
3325                                 adapter->tx_ring[3].reg_idx = 112;
3326                                 for (i = 0 ; i < dcb_i; i++)
3327                                         adapter->rx_ring[i].reg_idx = i << 5;
3328
3329                                 ret = true;
3330                         } else {
3331                                 ret = false;
3332                         }
3333                 } else {
3334                         ret = false;
3335                 }
3336         } else {
3337                 ret = false;
3338         }
3339
3340         return ret;
3341 }
3342 #endif
3343
3344 /**
3345  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
3346  * @adapter: board private structure to initialize
3347  *
3348  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
3349  *
3350  **/
3351 static bool inline ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
3352 {
3353         int i;
3354         bool ret = false;
3355
3356         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED &&
3357             ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3358              (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))) {
3359                 for (i = 0; i < adapter->num_rx_queues; i++)
3360                         adapter->rx_ring[i].reg_idx = i;
3361                 for (i = 0; i < adapter->num_tx_queues; i++)
3362                         adapter->tx_ring[i].reg_idx = i;
3363                 ret = true;
3364         }
3365
3366         return ret;
3367 }
3368
3369 #ifdef IXGBE_FCOE
3370 /**
3371  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
3372  * @adapter: board private structure to initialize
3373  *
3374  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
3375  *
3376  */
3377 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
3378 {
3379         int i, fcoe_rx_i = 0, fcoe_tx_i = 0;
3380         bool ret = false;
3381         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
3382
3383         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
3384 #ifdef CONFIG_IXGBE_DCB
3385                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
3386                         struct ixgbe_fcoe *fcoe = &adapter->fcoe;
3387
3388                         ixgbe_cache_ring_dcb(adapter);
3389                         /* find out queues in TC for FCoE */
3390                         fcoe_rx_i = adapter->rx_ring[fcoe->tc].reg_idx + 1;
3391                         fcoe_tx_i = adapter->tx_ring[fcoe->tc].reg_idx + 1;
3392                         /*
3393                          * In 82599, the number of Tx queues for each traffic
3394                          * class for both 8-TC and 4-TC modes are:
3395                          * TCs  : TC0 TC1 TC2 TC3 TC4 TC5 TC6 TC7
3396                          * 8 TCs:  32  32  16  16   8   8   8   8
3397                          * 4 TCs:  64  64  32  32
3398                          * We have max 8 queues for FCoE, where 8 the is
3399                          * FCoE redirection table size. If TC for FCoE is
3400                          * less than or equal to TC3, we have enough queues
3401                          * to add max of 8 queues for FCoE, so we start FCoE
3402                          * tx descriptor from the next one, i.e., reg_idx + 1.
3403                          * If TC for FCoE is above TC3, implying 8 TC mode,
3404                          * and we need 8 for FCoE, we have to take all queues
3405                          * in that traffic class for FCoE.
3406                          */
3407                         if ((f->indices == IXGBE_FCRETA_SIZE) && (fcoe->tc > 3))
3408                                 fcoe_tx_i--;
3409                 }
3410 #endif /* CONFIG_IXGBE_DCB */
3411                 if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
3412                         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) ||
3413                             (adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE))
3414                                 ixgbe_cache_ring_fdir(adapter);
3415                         else
3416                                 ixgbe_cache_ring_rss(adapter);
3417
3418                         fcoe_rx_i = f->mask;
3419                         fcoe_tx_i = f->mask;
3420                 }
3421                 for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
3422                         adapter->rx_ring[f->mask + i].reg_idx = fcoe_rx_i;
3423                         adapter->tx_ring[f->mask + i].reg_idx = fcoe_tx_i;
3424                 }
3425                 ret = true;
3426         }
3427         return ret;
3428 }
3429
3430 #endif /* IXGBE_FCOE */
3431 /**
3432  * ixgbe_cache_ring_register - Descriptor ring to register mapping
3433  * @adapter: board private structure to initialize
3434  *
3435  * Once we know the feature-set enabled for the device, we'll cache
3436  * the register offset the descriptor ring is assigned to.
3437  *
3438  * Note, the order the various feature calls is important.  It must start with
3439  * the "most" features enabled at the same time, then trickle down to the
3440  * least amount of features turned on at once.
3441  **/
3442 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
3443 {
3444         /* start with default case */
3445         adapter->rx_ring[0].reg_idx = 0;
3446         adapter->tx_ring[0].reg_idx = 0;
3447
3448 #ifdef IXGBE_FCOE
3449         if (ixgbe_cache_ring_fcoe(adapter))
3450                 return;
3451
3452 #endif /* IXGBE_FCOE */
3453 #ifdef CONFIG_IXGBE_DCB
3454         if (ixgbe_cache_ring_dcb(adapter))
3455                 return;
3456
3457 #endif
3458         if (ixgbe_cache_ring_fdir(adapter))
3459                 return;
3460
3461         if (ixgbe_cache_ring_rss(adapter))
3462                 return;
3463 }
3464
3465 /**
3466  * ixgbe_alloc_queues - Allocate memory for all rings
3467  * @adapter: board private structure to initialize
3468  *
3469  * We allocate one ring per queue at run-time since we don't know the
3470  * number of queues at compile-time.  The polling_netdev array is
3471  * intended for Multiqueue, but should work fine with a single queue.
3472  **/
3473 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
3474 {
3475         int i;
3476
3477         adapter->tx_ring = kcalloc(adapter->num_tx_queues,
3478                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3479         if (!adapter->tx_ring)
3480                 goto err_tx_ring_allocation;
3481
3482         adapter->rx_ring = kcalloc(adapter->num_rx_queues,
3483                                    sizeof(struct ixgbe_ring), GFP_KERNEL);
3484         if (!adapter->rx_ring)
3485                 goto err_rx_ring_allocation;
3486
3487         for (i = 0; i < adapter->num_tx_queues; i++) {
3488                 adapter->tx_ring[i].count = adapter->tx_ring_count;
3489                 adapter->tx_ring[i].queue_index = i;
3490         }
3491
3492         for (i = 0; i < adapter->num_rx_queues; i++) {
3493                 adapter->rx_ring[i].count = adapter->rx_ring_count;
3494                 adapter->rx_ring[i].queue_index = i;
3495         }
3496
3497         ixgbe_cache_ring_register(adapter);
3498
3499         return 0;
3500
3501 err_rx_ring_allocation:
3502         kfree(adapter->tx_ring);
3503 err_tx_ring_allocation:
3504         return -ENOMEM;
3505 }
3506
3507 /**
3508  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
3509  * @adapter: board private structure to initialize
3510  *
3511  * Attempt to configure the interrupts using the best available
3512  * capabilities of the hardware and the kernel.
3513  **/
3514 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
3515 {
3516         struct ixgbe_hw *hw = &adapter->hw;
3517         int err = 0;
3518         int vector, v_budget;
3519
3520         /*
3521          * It's easy to be greedy for MSI-X vectors, but it really
3522          * doesn't do us much good if we have a lot more vectors
3523          * than CPU's.  So let's be conservative and only ask for
3524          * (roughly) twice the number of vectors as there are CPU's.
3525          */
3526         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
3527                        (int)(num_online_cpus() * 2)) + NON_Q_VECTORS;
3528
3529         /*
3530          * At the same time, hardware can only support a maximum of
3531          * hw.mac->max_msix_vectors vectors.  With features
3532          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
3533          * descriptor queues supported by our device.  Thus, we cap it off in
3534          * those rare cases where the cpu count also exceeds our vector limit.
3535          */
3536         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
3537
3538         /* A failure in MSI-X entry allocation isn't fatal, but it does
3539          * mean we disable MSI-X capabilities of the adapter. */
3540         adapter->msix_entries = kcalloc(v_budget,
3541                                         sizeof(struct msix_entry), GFP_KERNEL);
3542         if (adapter->msix_entries) {
3543                 for (vector = 0; vector < v_budget; vector++)
3544                         adapter->msix_entries[vector].entry = vector;
3545
3546                 ixgbe_acquire_msix_vectors(adapter, v_budget);
3547
3548                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3549                         goto out;
3550         }
3551
3552         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
3553         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
3554         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
3555         adapter->flags &= ~IXGBE_FLAG_FDIR_PERFECT_CAPABLE;
3556         adapter->atr_sample_rate = 0;
3557         ixgbe_set_num_queues(adapter);
3558
3559         err = pci_enable_msi(adapter->pdev);
3560         if (!err) {
3561                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
3562         } else {
3563                 DPRINTK(HW, DEBUG, "Unable to allocate MSI interrupt, "
3564                         "falling back to legacy.  Error: %d\n", err);
3565                 /* reset err */
3566                 err = 0;
3567         }
3568
3569 out:
3570         return err;
3571 }
3572
3573 /**
3574  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
3575  * @adapter: board private structure to initialize
3576  *
3577  * We allocate one q_vector per queue interrupt.  If allocation fails we
3578  * return -ENOMEM.
3579  **/
3580 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
3581 {
3582         int q_idx, num_q_vectors;
3583         struct ixgbe_q_vector *q_vector;
3584         int napi_vectors;
3585         int (*poll)(struct napi_struct *, int);
3586
3587         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3588                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3589                 napi_vectors = adapter->num_rx_queues;
3590                 poll = &ixgbe_clean_rxtx_many;
3591         } else {
3592                 num_q_vectors = 1;
3593                 napi_vectors = 1;
3594                 poll = &ixgbe_poll;
3595         }
3596
3597         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3598                 q_vector = kzalloc(sizeof(struct ixgbe_q_vector), GFP_KERNEL);
3599                 if (!q_vector)
3600                         goto err_out;
3601                 q_vector->adapter = adapter;
3602                 q_vector->eitr = adapter->eitr_param;
3603                 q_vector->v_idx = q_idx;
3604                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
3605                 adapter->q_vector[q_idx] = q_vector;
3606         }
3607
3608         return 0;
3609
3610 err_out:
3611         while (q_idx) {
3612                 q_idx--;
3613                 q_vector = adapter->q_vector[q_idx];
3614                 netif_napi_del(&q_vector->napi);
3615                 kfree(q_vector);
3616                 adapter->q_vector[q_idx] = NULL;
3617         }
3618         return -ENOMEM;
3619 }
3620
3621 /**
3622  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
3623  * @adapter: board private structure to initialize
3624  *
3625  * This function frees the memory allocated to the q_vectors.  In addition if
3626  * NAPI is enabled it will delete any references to the NAPI struct prior
3627  * to freeing the q_vector.
3628  **/
3629 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
3630 {
3631         int q_idx, num_q_vectors;
3632
3633         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3634                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3635         else
3636                 num_q_vectors = 1;
3637
3638         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
3639                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
3640                 adapter->q_vector[q_idx] = NULL;
3641                 netif_napi_del(&q_vector->napi);
3642                 kfree(q_vector);
3643         }
3644 }
3645
3646 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
3647 {
3648         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3649                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
3650                 pci_disable_msix(adapter->pdev);
3651                 kfree(adapter->msix_entries);
3652                 adapter->msix_entries = NULL;
3653         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
3654                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
3655                 pci_disable_msi(adapter->pdev);
3656         }
3657         return;
3658 }
3659
3660 /**
3661  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
3662  * @adapter: board private structure to initialize
3663  *
3664  * We determine which interrupt scheme to use based on...
3665  * - Kernel support (MSI, MSI-X)
3666  *   - which can be user-defined (via MODULE_PARAM)
3667  * - Hardware queue count (num_*_queues)
3668  *   - defined by miscellaneous hardware support/features (RSS, etc.)
3669  **/
3670 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
3671 {
3672         int err;
3673
3674         /* Number of supported queues */
3675         ixgbe_set_num_queues(adapter);
3676
3677         err = ixgbe_set_interrupt_capability(adapter);
3678         if (err) {
3679                 DPRINTK(PROBE, ERR, "Unable to setup interrupt capabilities\n");
3680                 goto err_set_interrupt;
3681         }
3682
3683         err = ixgbe_alloc_q_vectors(adapter);
3684         if (err) {
3685                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queue "
3686                         "vectors\n");
3687                 goto err_alloc_q_vectors;
3688         }
3689
3690         err = ixgbe_alloc_queues(adapter);
3691         if (err) {
3692                 DPRINTK(PROBE, ERR, "Unable to allocate memory for queues\n");
3693                 goto err_alloc_queues;
3694         }
3695
3696         DPRINTK(DRV, INFO, "Multiqueue %s: Rx Queue count = %u, "
3697                 "Tx Queue count = %u\n",
3698                 (adapter->num_rx_queues > 1) ? "Enabled" :
3699                 "Disabled", adapter->num_rx_queues, adapter->num_tx_queues);
3700
3701         set_bit(__IXGBE_DOWN, &adapter->state);
3702
3703         return 0;
3704
3705 err_alloc_queues:
3706         ixgbe_free_q_vectors(adapter);
3707 err_alloc_q_vectors:
3708         ixgbe_reset_interrupt_capability(adapter);
3709 err_set_interrupt:
3710         return err;
3711 }
3712
3713 /**
3714  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
3715  * @adapter: board private structure to clear interrupt scheme on
3716  *
3717  * We go through and clear interrupt specific resources and reset the structure
3718  * to pre-load conditions
3719  **/
3720 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
3721 {
3722         kfree(adapter->tx_ring);
3723         kfree(adapter->rx_ring);
3724         adapter->tx_ring = NULL;
3725         adapter->rx_ring = NULL;
3726
3727         ixgbe_free_q_vectors(adapter);
3728         ixgbe_reset_interrupt_capability(adapter);
3729 }
3730
3731 /**
3732  * ixgbe_sfp_timer - worker thread to find a missing module
3733  * @data: pointer to our adapter struct
3734  **/
3735 static void ixgbe_sfp_timer(unsigned long data)
3736 {
3737         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
3738
3739         /*
3740          * Do the sfp_timer outside of interrupt context due to the
3741          * delays that sfp+ detection requires
3742          */
3743         schedule_work(&adapter->sfp_task);
3744 }
3745
3746 /**
3747  * ixgbe_sfp_task - worker thread to find a missing module
3748  * @work: pointer to work_struct containing our data
3749  **/
3750 static void ixgbe_sfp_task(struct work_struct *work)
3751 {
3752         struct ixgbe_adapter *adapter = container_of(work,
3753                                                      struct ixgbe_adapter,
3754                                                      sfp_task);
3755         struct ixgbe_hw *hw = &adapter->hw;
3756
3757         if ((hw->phy.type == ixgbe_phy_nl) &&
3758             (hw->phy.sfp_type == ixgbe_sfp_type_not_present)) {
3759                 s32 ret = hw->phy.ops.identify_sfp(hw);
3760                 if (ret == IXGBE_ERR_SFP_NOT_PRESENT)
3761                         goto reschedule;
3762                 ret = hw->phy.ops.reset(hw);
3763                 if (ret == IXGBE_ERR_SFP_NOT_SUPPORTED) {
3764                         dev_err(&adapter->pdev->dev, "failed to initialize "
3765                                 "because an unsupported SFP+ module type "
3766                                 "was detected.\n"
3767                                 "Reload the driver after installing a "
3768                                 "supported module.\n");
3769                         unregister_netdev(adapter->netdev);
3770                 } else {
3771                         DPRINTK(PROBE, INFO, "detected SFP+: %d\n",
3772                                 hw->phy.sfp_type);
3773                 }
3774                 /* don't need this routine any more */
3775                 clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
3776         }
3777         return;
3778 reschedule:
3779         if (test_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state))
3780                 mod_timer(&adapter->sfp_timer,
3781                           round_jiffies(jiffies + (2 * HZ)));
3782 }
3783
3784 /**
3785  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
3786  * @adapter: board private structure to initialize
3787  *
3788  * ixgbe_sw_init initializes the Adapter private data structure.
3789  * Fields are initialized based on PCI device information and
3790  * OS network device settings (MTU size).
3791  **/
3792 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
3793 {
3794         struct ixgbe_hw *hw = &adapter->hw;
3795         struct pci_dev *pdev = adapter->pdev;
3796         unsigned int rss;
3797 #ifdef CONFIG_IXGBE_DCB
3798         int j;
3799         struct tc_configuration *tc;
3800 #endif
3801
3802         /* PCI config space info */
3803
3804         hw->vendor_id = pdev->vendor;
3805         hw->device_id = pdev->device;
3806         hw->revision_id = pdev->revision;
3807         hw->subsystem_vendor_id = pdev->subsystem_vendor;
3808         hw->subsystem_device_id = pdev->subsystem_device;
3809
3810         /* Set capability flags */
3811         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
3812         adapter->ring_feature[RING_F_RSS].indices = rss;
3813         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
3814         adapter->ring_feature[RING_F_DCB].indices = IXGBE_MAX_DCB_INDICES;
3815         if (hw->mac.type == ixgbe_mac_82598EB) {
3816                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
3817                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
3818                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
3819         } else if (hw->mac.type == ixgbe_mac_82599EB) {
3820                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
3821                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
3822                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
3823                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
3824                 adapter->ring_feature[RING_F_FDIR].indices =
3825                                                          IXGBE_MAX_FDIR_INDICES;
3826                 adapter->atr_sample_rate = 20;
3827                 adapter->fdir_pballoc = 0;
3828 #ifdef IXGBE_FCOE
3829                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
3830                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
3831                 adapter->ring_feature[RING_F_FCOE].indices = 0;
3832                 /* Default traffic class to use for FCoE */
3833                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
3834 #endif /* IXGBE_FCOE */
3835         }
3836
3837 #ifdef CONFIG_IXGBE_DCB
3838         /* Configure DCB traffic classes */
3839         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
3840                 tc = &adapter->dcb_cfg.tc_config[j];
3841                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
3842                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
3843                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
3844                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
3845                 tc->dcb_pfc = pfc_disabled;
3846         }
3847         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
3848         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
3849         adapter->dcb_cfg.rx_pba_cfg = pba_equal;
3850         adapter->dcb_cfg.pfc_mode_enable = false;
3851         adapter->dcb_cfg.round_robin_enable = false;
3852         adapter->dcb_set_bitmap = 0x00;
3853         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
3854                            adapter->ring_feature[RING_F_DCB].indices);
3855
3856 #endif
3857
3858         /* default flow control settings */
3859         hw->fc.requested_mode = ixgbe_fc_full;
3860         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
3861 #ifdef CONFIG_DCB
3862         adapter->last_lfc_mode = hw->fc.current_mode;
3863 #endif
3864         hw->fc.high_water = IXGBE_DEFAULT_FCRTH;
3865         hw->fc.low_water = IXGBE_DEFAULT_FCRTL;
3866         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
3867         hw->fc.send_xon = true;
3868         hw->fc.disable_fc_autoneg = false;
3869
3870         /* enable itr by default in dynamic mode */
3871         adapter->itr_setting = 1;
3872         adapter->eitr_param = 20000;
3873
3874         /* set defaults for eitr in MegaBytes */
3875         adapter->eitr_low = 10;
3876         adapter->eitr_high = 20;
3877
3878         /* set default ring sizes */
3879         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
3880         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
3881
3882         /* initialize eeprom parameters */
3883         if (ixgbe_init_eeprom_params_generic(hw)) {
3884                 dev_err(&pdev->dev, "EEPROM initialization failed\n");
3885                 return -EIO;
3886         }
3887
3888         /* enable rx csum by default */
3889         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
3890
3891         set_bit(__IXGBE_DOWN, &adapter->state);
3892
3893         return 0;
3894 }
3895
3896 /**
3897  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
3898  * @adapter: board private structure
3899  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
3900  *
3901  * Return 0 on success, negative on failure
3902  **/
3903 int ixgbe_setup_tx_resources(struct ixgbe_adapter *adapter,
3904                              struct ixgbe_ring *tx_ring)
3905 {
3906         struct pci_dev *pdev = adapter->pdev;
3907         int size;
3908
3909         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
3910         tx_ring->tx_buffer_info = vmalloc(size);
3911         if (!tx_ring->tx_buffer_info)
3912                 goto err;
3913         memset(tx_ring->tx_buffer_info, 0, size);
3914
3915         /* round up to nearest 4K */
3916         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
3917         tx_ring->size = ALIGN(tx_ring->size, 4096);
3918
3919         tx_ring->desc = pci_alloc_consistent(pdev, tx_ring->size,
3920                                              &tx_ring->dma);
3921         if (!tx_ring->desc)
3922                 goto err;
3923
3924         tx_ring->next_to_use = 0;
3925         tx_ring->next_to_clean = 0;
3926         tx_ring->work_limit = tx_ring->count;
3927         return 0;
3928
3929 err:
3930         vfree(tx_ring->tx_buffer_info);
3931         tx_ring->tx_buffer_info = NULL;
3932         DPRINTK(PROBE, ERR, "Unable to allocate memory for the transmit "
3933                             "descriptor ring\n");
3934         return -ENOMEM;
3935 }
3936
3937 /**
3938  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
3939  * @adapter: board private structure
3940  *
3941  * If this function returns with an error, then it's possible one or
3942  * more of the rings is populated (while the rest are not).  It is the
3943  * callers duty to clean those orphaned rings.
3944  *
3945  * Return 0 on success, negative on failure
3946  **/
3947 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
3948 {
3949         int i, err = 0;
3950
3951         for (i = 0; i < adapter->num_tx_queues; i++) {
3952                 err = ixgbe_setup_tx_resources(adapter, &adapter->tx_ring[i]);
3953                 if (!err)
3954                         continue;
3955                 DPRINTK(PROBE, ERR, "Allocation for Tx Queue %u failed\n", i);
3956                 break;
3957         }
3958
3959         return err;
3960 }
3961
3962 /**
3963  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
3964  * @adapter: board private structure
3965  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
3966  *
3967  * Returns 0 on success, negative on failure
3968  **/
3969 int ixgbe_setup_rx_resources(struct ixgbe_adapter *adapter,
3970                              struct ixgbe_ring *rx_ring)
3971 {
3972         struct pci_dev *pdev = adapter->pdev;
3973         int size;
3974
3975         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
3976         rx_ring->rx_buffer_info = vmalloc(size);
3977         if (!rx_ring->rx_buffer_info) {
3978                 DPRINTK(PROBE, ERR,
3979                         "vmalloc allocation failed for the rx desc ring\n");
3980                 goto alloc_failed;
3981         }
3982         memset(rx_ring->rx_buffer_info, 0, size);
3983
3984         /* Round up to nearest 4K */
3985         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
3986         rx_ring->size = ALIGN(rx_ring->size, 4096);
3987
3988         rx_ring->desc = pci_alloc_consistent(pdev, rx_ring->size, &rx_ring->dma);
3989
3990         if (!rx_ring->desc) {
3991                 DPRINTK(PROBE, ERR,
3992                         "Memory allocation failed for the rx desc ring\n");
3993                 vfree(rx_ring->rx_buffer_info);
3994                 goto alloc_failed;
3995         }
3996
3997         rx_ring->next_to_clean = 0;
3998         rx_ring->next_to_use = 0;
3999
4000         return 0;
4001
4002 alloc_failed:
4003         return -ENOMEM;
4004 }
4005
4006 /**
4007  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
4008  * @adapter: board private structure
4009  *
4010  * If this function returns with an error, then it's possible one or
4011  * more of the rings is populated (while the rest are not).  It is the
4012  * callers duty to clean those orphaned rings.
4013  *
4014  * Return 0 on success, negative on failure
4015  **/
4016
4017 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
4018 {
4019         int i, err = 0;
4020
4021         for (i = 0; i < adapter->num_rx_queues; i++) {
4022                 err = ixgbe_setup_rx_resources(adapter, &adapter->rx_ring[i]);
4023                 if (!err)
4024                         continue;
4025                 DPRINTK(PROBE, ERR, "Allocation for Rx Queue %u failed\n", i);
4026                 break;
4027         }
4028
4029         return err;
4030 }
4031
4032 /**
4033  * ixgbe_free_tx_resources - Free Tx Resources per Queue
4034  * @adapter: board private structure
4035  * @tx_ring: Tx descriptor ring for a specific queue
4036  *
4037  * Free all transmit software resources
4038  **/
4039 void ixgbe_free_tx_resources(struct ixgbe_adapter *adapter,
4040                              struct ixgbe_ring *tx_ring)
4041 {
4042         struct pci_dev *pdev = adapter->pdev;
4043
4044         ixgbe_clean_tx_ring(adapter, tx_ring);
4045
4046         vfree(tx_ring->tx_buffer_info);
4047         tx_ring->tx_buffer_info = NULL;
4048
4049         pci_free_consistent(pdev, tx_ring->size, tx_ring->desc, tx_ring->dma);
4050
4051         tx_ring->desc = NULL;
4052 }
4053
4054 /**
4055  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
4056  * @adapter: board private structure
4057  *
4058  * Free all transmit software resources
4059  **/
4060 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
4061 {
4062         int i;
4063
4064         for (i = 0; i < adapter->num_tx_queues; i++)
4065                 if (adapter->tx_ring[i].desc)
4066                         ixgbe_free_tx_resources(adapter, &adapter->tx_ring[i]);
4067 }
4068
4069 /**
4070  * ixgbe_free_rx_resources - Free Rx Resources
4071  * @adapter: board private structure
4072  * @rx_ring: ring to clean the resources from
4073  *
4074  * Free all receive software resources
4075  **/
4076 void ixgbe_free_rx_resources(struct ixgbe_adapter *adapter,
4077                              struct ixgbe_ring *rx_ring)
4078 {
4079         struct pci_dev *pdev = adapter->pdev;
4080
4081         ixgbe_clean_rx_ring(adapter, rx_ring);
4082
4083         vfree(rx_ring->rx_buffer_info);
4084         rx_ring->rx_buffer_info = NULL;
4085
4086         pci_free_consistent(pdev, rx_ring->size, rx_ring->desc, rx_ring->dma);
4087
4088         rx_ring->desc = NULL;
4089 }
4090
4091 /**
4092  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
4093  * @adapter: board private structure
4094  *
4095  * Free all receive software resources
4096  **/
4097 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
4098 {
4099         int i;
4100
4101         for (i = 0; i < adapter->num_rx_queues; i++)
4102                 if (adapter->rx_ring[i].desc)
4103                         ixgbe_free_rx_resources(adapter, &adapter->rx_ring[i]);
4104 }
4105
4106 /**
4107  * ixgbe_change_mtu - Change the Maximum Transfer Unit
4108  * @netdev: network interface device structure
4109  * @new_mtu: new value for maximum frame size
4110  *
4111  * Returns 0 on success, negative on failure
4112  **/
4113 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
4114 {
4115         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4116         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
4117
4118         /* MTU < 68 is an error and causes problems on some kernels */
4119         if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
4120                 return -EINVAL;
4121
4122         DPRINTK(PROBE, INFO, "changing MTU from %d to %d\n",
4123                 netdev->mtu, new_mtu);
4124         /* must set new MTU before calling down or up */
4125         netdev->mtu = new_mtu;
4126
4127         if (netif_running(netdev))
4128                 ixgbe_reinit_locked(adapter);
4129
4130         return 0;
4131 }
4132
4133 /**
4134  * ixgbe_open - Called when a network interface is made active
4135  * @netdev: network interface device structure
4136  *
4137  * Returns 0 on success, negative value on failure
4138  *
4139  * The open entry point is called when a network interface is made
4140  * active by the system (IFF_UP).  At this point all resources needed
4141  * for transmit and receive operations are allocated, the interrupt
4142  * handler is registered with the OS, the watchdog timer is started,
4143  * and the stack is notified that the interface is ready.
4144  **/
4145 static int ixgbe_open(struct net_device *netdev)
4146 {
4147         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4148         int err;
4149
4150         /* disallow open during test */
4151         if (test_bit(__IXGBE_TESTING, &adapter->state))
4152                 return -EBUSY;
4153
4154         netif_carrier_off(netdev);
4155
4156         /* allocate transmit descriptors */
4157         err = ixgbe_setup_all_tx_resources(adapter);
4158         if (err)
4159                 goto err_setup_tx;
4160
4161         /* allocate receive descriptors */
4162         err = ixgbe_setup_all_rx_resources(adapter);
4163         if (err)
4164                 goto err_setup_rx;
4165
4166         ixgbe_configure(adapter);
4167
4168         err = ixgbe_request_irq(adapter);
4169         if (err)
4170                 goto err_req_irq;
4171
4172         err = ixgbe_up_complete(adapter);
4173         if (err)
4174                 goto err_up;
4175
4176         netif_tx_start_all_queues(netdev);
4177
4178         return 0;
4179
4180 err_up:
4181         ixgbe_release_hw_control(adapter);
4182         ixgbe_free_irq(adapter);
4183 err_req_irq:
4184 err_setup_rx:
4185         ixgbe_free_all_rx_resources(adapter);
4186 err_setup_tx:
4187         ixgbe_free_all_tx_resources(adapter);
4188         ixgbe_reset(adapter);
4189
4190         return err;
4191 }
4192
4193 /**
4194  * ixgbe_close - Disables a network interface
4195  * @netdev: network interface device structure
4196  *
4197  * Returns 0, this is not allowed to fail
4198  *
4199  * The close entry point is called when an interface is de-activated
4200  * by the OS.  The hardware is still under the drivers control, but
4201  * needs to be disabled.  A global MAC reset is issued to stop the
4202  * hardware, and all transmit and receive resources are freed.
4203  **/
4204 static int ixgbe_close(struct net_device *netdev)
4205 {
4206         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4207
4208         ixgbe_down(adapter);
4209         ixgbe_free_irq(adapter);
4210
4211         ixgbe_free_all_tx_resources(adapter);
4212         ixgbe_free_all_rx_resources(adapter);
4213
4214         ixgbe_release_hw_control(adapter);
4215
4216         return 0;
4217 }
4218
4219 #ifdef CONFIG_PM
4220 static int ixgbe_resume(struct pci_dev *pdev)
4221 {
4222         struct net_device *netdev = pci_get_drvdata(pdev);
4223         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4224         u32 err;
4225
4226         pci_set_power_state(pdev, PCI_D0);
4227         pci_restore_state(pdev);
4228
4229         err = pci_enable_device_mem(pdev);
4230         if (err) {
4231                 printk(KERN_ERR "ixgbe: Cannot enable PCI device from "
4232                                 "suspend\n");
4233                 return err;
4234         }
4235         pci_set_master(pdev);
4236
4237         pci_wake_from_d3(pdev, false);
4238
4239         err = ixgbe_init_interrupt_scheme(adapter);
4240         if (err) {
4241                 printk(KERN_ERR "ixgbe: Cannot initialize interrupts for "
4242                                 "device\n");
4243                 return err;
4244         }
4245
4246         ixgbe_reset(adapter);
4247
4248         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
4249
4250         if (netif_running(netdev)) {
4251                 err = ixgbe_open(adapter->netdev);
4252                 if (err)
4253                         return err;
4254         }
4255
4256         netif_device_attach(netdev);
4257
4258         return 0;
4259 }
4260 #endif /* CONFIG_PM */
4261
4262 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
4263 {
4264         struct net_device *netdev = pci_get_drvdata(pdev);
4265         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4266         struct ixgbe_hw *hw = &adapter->hw;
4267         u32 ctrl, fctrl;
4268         u32 wufc = adapter->wol;
4269 #ifdef CONFIG_PM
4270         int retval = 0;
4271 #endif
4272
4273         netif_device_detach(netdev);
4274
4275         if (netif_running(netdev)) {
4276                 ixgbe_down(adapter);
4277                 ixgbe_free_irq(adapter);
4278                 ixgbe_free_all_tx_resources(adapter);
4279                 ixgbe_free_all_rx_resources(adapter);
4280         }
4281         ixgbe_clear_interrupt_scheme(adapter);
4282
4283 #ifdef CONFIG_PM
4284         retval = pci_save_state(pdev);
4285         if (retval)
4286                 return retval;
4287
4288 #endif
4289         if (wufc) {
4290                 ixgbe_set_rx_mode(netdev);
4291
4292                 /* turn on all-multi mode if wake on multicast is enabled */
4293                 if (wufc & IXGBE_WUFC_MC) {
4294                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4295                         fctrl |= IXGBE_FCTRL_MPE;
4296                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
4297                 }
4298
4299                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
4300                 ctrl |= IXGBE_CTRL_GIO_DIS;
4301                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
4302
4303                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
4304         } else {
4305                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
4306                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
4307         }
4308
4309         if (wufc && hw->mac.type == ixgbe_mac_82599EB)
4310                 pci_wake_from_d3(pdev, true);
4311         else
4312                 pci_wake_from_d3(pdev, false);
4313
4314         *enable_wake = !!wufc;
4315
4316         ixgbe_release_hw_control(adapter);
4317
4318         pci_disable_device(pdev);
4319
4320         return 0;
4321 }
4322
4323 #ifdef CONFIG_PM
4324 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
4325 {
4326         int retval;
4327         bool wake;
4328
4329         retval = __ixgbe_shutdown(pdev, &wake);
4330         if (retval)
4331                 return retval;
4332
4333         if (wake) {
4334                 pci_prepare_to_sleep(pdev);
4335         } else {
4336                 pci_wake_from_d3(pdev, false);
4337                 pci_set_power_state(pdev, PCI_D3hot);
4338         }
4339
4340         return 0;
4341 }
4342 #endif /* CONFIG_PM */
4343
4344 static void ixgbe_shutdown(struct pci_dev *pdev)
4345 {
4346         bool wake;
4347
4348         __ixgbe_shutdown(pdev, &wake);
4349
4350         if (system_state == SYSTEM_POWER_OFF) {
4351                 pci_wake_from_d3(pdev, wake);
4352                 pci_set_power_state(pdev, PCI_D3hot);
4353         }
4354 }
4355
4356 /**
4357  * ixgbe_update_stats - Update the board statistics counters.
4358  * @adapter: board private structure
4359  **/
4360 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
4361 {
4362         struct ixgbe_hw *hw = &adapter->hw;
4363         u64 total_mpc = 0;
4364         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
4365
4366         if (hw->mac.type == ixgbe_mac_82599EB) {
4367                 u64 rsc_count = 0;
4368                 for (i = 0; i < 16; i++)
4369                         adapter->hw_rx_no_dma_resources +=
4370                                              IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4371                 for (i = 0; i < adapter->num_rx_queues; i++)
4372                         rsc_count += adapter->rx_ring[i].rsc_count;
4373                 adapter->rsc_count = rsc_count;
4374         }
4375
4376         adapter->stats.crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
4377         for (i = 0; i < 8; i++) {
4378                 /* for packet buffers not used, the register should read 0 */
4379                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
4380                 missed_rx += mpc;
4381                 adapter->stats.mpc[i] += mpc;
4382                 total_mpc += adapter->stats.mpc[i];
4383                 if (hw->mac.type == ixgbe_mac_82598EB)
4384                         adapter->stats.rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
4385                 adapter->stats.qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
4386                 adapter->stats.qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
4387                 adapter->stats.qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
4388                 adapter->stats.qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
4389                 if (hw->mac.type == ixgbe_mac_82599EB) {
4390                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4391                                                             IXGBE_PXONRXCNT(i));
4392                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4393                                                            IXGBE_PXOFFRXCNT(i));
4394                         adapter->stats.qprdc[i] += IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
4395                 } else {
4396                         adapter->stats.pxonrxc[i] += IXGBE_READ_REG(hw,
4397                                                               IXGBE_PXONRXC(i));
4398                         adapter->stats.pxoffrxc[i] += IXGBE_READ_REG(hw,
4399                                                              IXGBE_PXOFFRXC(i));
4400                 }
4401                 adapter->stats.pxontxc[i] += IXGBE_READ_REG(hw,
4402                                                             IXGBE_PXONTXC(i));
4403                 adapter->stats.pxofftxc[i] += IXGBE_READ_REG(hw,
4404                                                              IXGBE_PXOFFTXC(i));
4405         }
4406         adapter->stats.gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
4407         /* work around hardware counting issue */
4408         adapter->stats.gprc -= missed_rx;
4409
4410         /* 82598 hardware only has a 32 bit counter in the high register */
4411         if (hw->mac.type == ixgbe_mac_82599EB) {
4412                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
4413                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
4414                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
4415                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
4416                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORL);
4417                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
4418                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
4419                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
4420                 adapter->stats.fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
4421                 adapter->stats.fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
4422 #ifdef IXGBE_FCOE
4423                 adapter->stats.fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
4424                 adapter->stats.fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
4425                 adapter->stats.fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
4426                 adapter->stats.fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
4427                 adapter->stats.fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
4428                 adapter->stats.fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
4429 #endif /* IXGBE_FCOE */
4430         } else {
4431                 adapter->stats.lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
4432                 adapter->stats.lxoffrxc += IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
4433                 adapter->stats.gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
4434                 adapter->stats.gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
4435                 adapter->stats.tor += IXGBE_READ_REG(hw, IXGBE_TORH);
4436         }
4437         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
4438         adapter->stats.bprc += bprc;
4439         adapter->stats.mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
4440         if (hw->mac.type == ixgbe_mac_82598EB)
4441                 adapter->stats.mprc -= bprc;
4442         adapter->stats.roc += IXGBE_READ_REG(hw, IXGBE_ROC);
4443         adapter->stats.prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
4444         adapter->stats.prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
4445         adapter->stats.prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
4446         adapter->stats.prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
4447         adapter->stats.prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
4448         adapter->stats.prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
4449         adapter->stats.rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
4450         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
4451         adapter->stats.lxontxc += lxon;
4452         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
4453         adapter->stats.lxofftxc += lxoff;
4454         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4455         adapter->stats.gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
4456         adapter->stats.mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
4457         /*
4458          * 82598 errata - tx of flow control packets is included in tx counters
4459          */
4460         xon_off_tot = lxon + lxoff;
4461         adapter->stats.gptc -= xon_off_tot;
4462         adapter->stats.mptc -= xon_off_tot;
4463         adapter->stats.gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
4464         adapter->stats.ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
4465         adapter->stats.rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
4466         adapter->stats.rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
4467         adapter->stats.tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
4468         adapter->stats.ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
4469         adapter->stats.ptc64 -= xon_off_tot;
4470         adapter->stats.ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
4471         adapter->stats.ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
4472         adapter->stats.ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
4473         adapter->stats.ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
4474         adapter->stats.ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
4475         adapter->stats.bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
4476
4477         /* Fill out the OS statistics structure */
4478         adapter->net_stats.multicast = adapter->stats.mprc;
4479
4480         /* Rx Errors */
4481         adapter->net_stats.rx_errors = adapter->stats.crcerrs +
4482                                        adapter->stats.rlec;
4483         adapter->net_stats.rx_dropped = 0;
4484         adapter->net_stats.rx_length_errors = adapter->stats.rlec;
4485         adapter->net_stats.rx_crc_errors = adapter->stats.crcerrs;
4486         adapter->net_stats.rx_missed_errors = total_mpc;
4487 }
4488
4489 /**
4490  * ixgbe_watchdog - Timer Call-back
4491  * @data: pointer to adapter cast into an unsigned long
4492  **/
4493 static void ixgbe_watchdog(unsigned long data)
4494 {
4495         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
4496         struct ixgbe_hw *hw = &adapter->hw;
4497         u64 eics = 0;
4498         int i;
4499
4500         /*
4501          *  Do the watchdog outside of interrupt context due to the lovely
4502          * delays that some of the newer hardware requires
4503          */
4504
4505         if (test_bit(__IXGBE_DOWN, &adapter->state))
4506                 goto watchdog_short_circuit;
4507
4508         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
4509                 /*
4510                  * for legacy and MSI interrupts don't set any bits
4511                  * that are enabled for EIAM, because this operation
4512                  * would set *both* EIMS and EICS for any bit in EIAM
4513                  */
4514                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
4515                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
4516                 goto watchdog_reschedule;
4517         }
4518
4519         /* get one bit for every active tx/rx interrupt vector */
4520         for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
4521                 struct ixgbe_q_vector *qv = adapter->q_vector[i];
4522                 if (qv->rxr_count || qv->txr_count)
4523                         eics |= ((u64)1 << i);
4524         }
4525
4526         /* Cause software interrupt to ensure rx rings are cleaned */
4527         ixgbe_irq_rearm_queues(adapter, eics);
4528
4529 watchdog_reschedule:
4530         /* Reset the timer */
4531         mod_timer(&adapter->watchdog_timer, round_jiffies(jiffies + 2 * HZ));
4532
4533 watchdog_short_circuit:
4534         schedule_work(&adapter->watchdog_task);
4535 }
4536
4537 /**
4538  * ixgbe_multispeed_fiber_task - worker thread to configure multispeed fiber
4539  * @work: pointer to work_struct containing our data
4540  **/
4541 static void ixgbe_multispeed_fiber_task(struct work_struct *work)
4542 {
4543         struct ixgbe_adapter *adapter = container_of(work,
4544                                                      struct ixgbe_adapter,
4545                                                      multispeed_fiber_task);
4546         struct ixgbe_hw *hw = &adapter->hw;
4547         u32 autoneg;
4548         bool negotiation;
4549
4550         adapter->flags |= IXGBE_FLAG_IN_SFP_LINK_TASK;
4551         autoneg = hw->phy.autoneg_advertised;
4552         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
4553                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
4554         if (hw->mac.ops.setup_link)
4555                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
4556         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
4557         adapter->flags &= ~IXGBE_FLAG_IN_SFP_LINK_TASK;
4558 }
4559
4560 /**
4561  * ixgbe_sfp_config_module_task - worker thread to configure a new SFP+ module
4562  * @work: pointer to work_struct containing our data
4563  **/
4564 static void ixgbe_sfp_config_module_task(struct work_struct *work)
4565 {
4566         struct ixgbe_adapter *adapter = container_of(work,
4567                                                      struct ixgbe_adapter,
4568                                                      sfp_config_module_task);
4569         struct ixgbe_hw *hw = &adapter->hw;
4570         u32 err;
4571
4572         adapter->flags |= IXGBE_FLAG_IN_SFP_MOD_TASK;
4573
4574         /* Time for electrical oscillations to settle down */
4575         msleep(100);
4576         err = hw->phy.ops.identify_sfp(hw);
4577
4578         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
4579                 dev_err(&adapter->pdev->dev, "failed to initialize because "
4580                         "an unsupported SFP+ module type was detected.\n"
4581                         "Reload the driver after installing a supported "
4582                         "module.\n");
4583                 unregister_netdev(adapter->netdev);
4584                 return;
4585         }
4586         hw->mac.ops.setup_sfp(hw);
4587
4588         if (!(adapter->flags & IXGBE_FLAG_IN_SFP_LINK_TASK))
4589                 /* This will also work for DA Twinax connections */
4590                 schedule_work(&adapter->multispeed_fiber_task);
4591         adapter->flags &= ~IXGBE_FLAG_IN_SFP_MOD_TASK;
4592 }
4593
4594 /**
4595  * ixgbe_fdir_reinit_task - worker thread to reinit FDIR filter table
4596  * @work: pointer to work_struct containing our data
4597  **/
4598 static void ixgbe_fdir_reinit_task(struct work_struct *work)
4599 {
4600         struct ixgbe_adapter *adapter = container_of(work,
4601                                                      struct ixgbe_adapter,
4602                                                      fdir_reinit_task);
4603         struct ixgbe_hw *hw = &adapter->hw;
4604         int i;
4605
4606         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
4607                 for (i = 0; i < adapter->num_tx_queues; i++)
4608                         set_bit(__IXGBE_FDIR_INIT_DONE,
4609                                 &(adapter->tx_ring[i].reinit_state));
4610         } else {
4611                 DPRINTK(PROBE, ERR, "failed to finish FDIR re-initialization, "
4612                         "ignored adding FDIR ATR filters \n");
4613         }
4614         /* Done FDIR Re-initialization, enable transmits */
4615         netif_tx_start_all_queues(adapter->netdev);
4616 }
4617
4618 /**
4619  * ixgbe_watchdog_task - worker thread to bring link up
4620  * @work: pointer to work_struct containing our data
4621  **/
4622 static void ixgbe_watchdog_task(struct work_struct *work)
4623 {
4624         struct ixgbe_adapter *adapter = container_of(work,
4625                                                      struct ixgbe_adapter,
4626                                                      watchdog_task);
4627         struct net_device *netdev = adapter->netdev;
4628         struct ixgbe_hw *hw = &adapter->hw;
4629         u32 link_speed = adapter->link_speed;
4630         bool link_up = adapter->link_up;
4631         int i;
4632         struct ixgbe_ring *tx_ring;
4633         int some_tx_pending = 0;
4634
4635         adapter->flags |= IXGBE_FLAG_IN_WATCHDOG_TASK;
4636
4637         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE) {
4638                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
4639                 if (link_up) {
4640 #ifdef CONFIG_DCB
4641                         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
4642                                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
4643                                         hw->mac.ops.fc_enable(hw, i);
4644                         } else {
4645                                 hw->mac.ops.fc_enable(hw, 0);
4646                         }
4647 #else
4648                         hw->mac.ops.fc_enable(hw, 0);
4649 #endif
4650                 }
4651
4652                 if (link_up ||
4653                     time_after(jiffies, (adapter->link_check_timeout +
4654                                          IXGBE_TRY_LINK_TIMEOUT))) {
4655                         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4656                         IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
4657                 }
4658                 adapter->link_up = link_up;
4659                 adapter->link_speed = link_speed;
4660         }
4661
4662         if (link_up) {
4663                 if (!netif_carrier_ok(netdev)) {
4664                         bool flow_rx, flow_tx;
4665
4666                         if (hw->mac.type == ixgbe_mac_82599EB) {
4667                                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
4668                                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
4669                                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
4670                                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
4671                         } else {
4672                                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
4673                                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
4674                                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
4675                                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
4676                         }
4677
4678                         printk(KERN_INFO "ixgbe: %s NIC Link is Up %s, "
4679                                "Flow Control: %s\n",
4680                                netdev->name,
4681                                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
4682                                 "10 Gbps" :
4683                                 (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
4684                                  "1 Gbps" : "unknown speed")),
4685                                ((flow_rx && flow_tx) ? "RX/TX" :
4686                                 (flow_rx ? "RX" :
4687                                 (flow_tx ? "TX" : "None"))));
4688
4689                         netif_carrier_on(netdev);
4690                 } else {
4691                         /* Force detection of hung controller */
4692                         adapter->detect_tx_hung = true;
4693                 }
4694         } else {
4695                 adapter->link_up = false;
4696                 adapter->link_speed = 0;
4697                 if (netif_carrier_ok(netdev)) {
4698                         printk(KERN_INFO "ixgbe: %s NIC Link is Down\n",
4699                                netdev->name);
4700                         netif_carrier_off(netdev);
4701                 }
4702         }
4703
4704         if (!netif_carrier_ok(netdev)) {
4705                 for (i = 0; i < adapter->num_tx_queues; i++) {
4706                         tx_ring = &adapter->tx_ring[i];
4707                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
4708                                 some_tx_pending = 1;
4709                                 break;
4710                         }
4711                 }
4712
4713                 if (some_tx_pending) {
4714                         /* We've lost link, so the controller stops DMA,
4715                          * but we've got queued Tx work that's never going
4716                          * to get done, so reset controller to flush Tx.
4717                          * (Do the reset outside of interrupt context).
4718                          */
4719                          schedule_work(&adapter->reset_task);
4720                 }
4721         }
4722
4723         ixgbe_update_stats(adapter);
4724         adapter->flags &= ~IXGBE_FLAG_IN_WATCHDOG_TASK;
4725 }
4726
4727 static int ixgbe_tso(struct ixgbe_adapter *adapter,
4728                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
4729                      u32 tx_flags, u8 *hdr_len)
4730 {
4731         struct ixgbe_adv_tx_context_desc *context_desc;
4732         unsigned int i;
4733         int err;
4734         struct ixgbe_tx_buffer *tx_buffer_info;
4735         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
4736         u32 mss_l4len_idx, l4len;
4737
4738         if (skb_is_gso(skb)) {
4739                 if (skb_header_cloned(skb)) {
4740                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
4741                         if (err)
4742                                 return err;
4743                 }
4744                 l4len = tcp_hdrlen(skb);
4745                 *hdr_len += l4len;
4746
4747                 if (skb->protocol == htons(ETH_P_IP)) {
4748                         struct iphdr *iph = ip_hdr(skb);
4749                         iph->tot_len = 0;
4750                         iph->check = 0;
4751                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
4752                                                                  iph->daddr, 0,
4753                                                                  IPPROTO_TCP,
4754                                                                  0);
4755                         adapter->hw_tso_ctxt++;
4756                 } else if (skb_shinfo(skb)->gso_type == SKB_GSO_TCPV6) {
4757                         ipv6_hdr(skb)->payload_len = 0;
4758                         tcp_hdr(skb)->check =
4759                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
4760                                              &ipv6_hdr(skb)->daddr,
4761                                              0, IPPROTO_TCP, 0);
4762                         adapter->hw_tso6_ctxt++;
4763                 }
4764
4765                 i = tx_ring->next_to_use;
4766
4767                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4768                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4769
4770                 /* VLAN MACLEN IPLEN */
4771                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4772                         vlan_macip_lens |=
4773                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4774                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
4775                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4776                 *hdr_len += skb_network_offset(skb);
4777                 vlan_macip_lens |=
4778                     (skb_transport_header(skb) - skb_network_header(skb));
4779                 *hdr_len +=
4780                     (skb_transport_header(skb) - skb_network_header(skb));
4781                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4782                 context_desc->seqnum_seed = 0;
4783
4784                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4785                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
4786                                    IXGBE_ADVTXD_DTYP_CTXT);
4787
4788                 if (skb->protocol == htons(ETH_P_IP))
4789                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4790                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
4791                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4792
4793                 /* MSS L4LEN IDX */
4794                 mss_l4len_idx =
4795                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
4796                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
4797                 /* use index 1 for TSO */
4798                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
4799                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
4800
4801                 tx_buffer_info->time_stamp = jiffies;
4802                 tx_buffer_info->next_to_watch = i;
4803
4804                 i++;
4805                 if (i == tx_ring->count)
4806                         i = 0;
4807                 tx_ring->next_to_use = i;
4808
4809                 return true;
4810         }
4811         return false;
4812 }
4813
4814 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
4815                           struct ixgbe_ring *tx_ring,
4816                           struct sk_buff *skb, u32 tx_flags)
4817 {
4818         struct ixgbe_adv_tx_context_desc *context_desc;
4819         unsigned int i;
4820         struct ixgbe_tx_buffer *tx_buffer_info;
4821         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
4822
4823         if (skb->ip_summed == CHECKSUM_PARTIAL ||
4824             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
4825                 i = tx_ring->next_to_use;
4826                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4827                 context_desc = IXGBE_TX_CTXTDESC_ADV(*tx_ring, i);
4828
4829                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4830                         vlan_macip_lens |=
4831                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
4832                 vlan_macip_lens |= (skb_network_offset(skb) <<
4833                                     IXGBE_ADVTXD_MACLEN_SHIFT);
4834                 if (skb->ip_summed == CHECKSUM_PARTIAL)
4835                         vlan_macip_lens |= (skb_transport_header(skb) -
4836                                             skb_network_header(skb));
4837
4838                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
4839                 context_desc->seqnum_seed = 0;
4840
4841                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
4842                                     IXGBE_ADVTXD_DTYP_CTXT);
4843
4844                 if (skb->ip_summed == CHECKSUM_PARTIAL) {
4845                         switch (skb->protocol) {
4846                         case cpu_to_be16(ETH_P_IP):
4847                                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
4848                                 if (ip_hdr(skb)->protocol == IPPROTO_TCP)
4849                                         type_tucmd_mlhl |=
4850                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4851                                 else if (ip_hdr(skb)->protocol == IPPROTO_SCTP)
4852                                         type_tucmd_mlhl |=
4853                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4854                                 break;
4855                         case cpu_to_be16(ETH_P_IPV6):
4856                                 /* XXX what about other V6 headers?? */
4857                                 if (ipv6_hdr(skb)->nexthdr == IPPROTO_TCP)
4858                                         type_tucmd_mlhl |=
4859                                                 IXGBE_ADVTXD_TUCMD_L4T_TCP;
4860                                 else if (ipv6_hdr(skb)->nexthdr == IPPROTO_SCTP)
4861                                         type_tucmd_mlhl |=
4862                                                 IXGBE_ADVTXD_TUCMD_L4T_SCTP;
4863                                 break;
4864                         default:
4865                                 if (unlikely(net_ratelimit())) {
4866                                         DPRINTK(PROBE, WARNING,
4867                                          "partial checksum but proto=%x!\n",
4868                                          skb->protocol);
4869                                 }
4870                                 break;
4871                         }
4872                 }
4873
4874                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
4875                 /* use index zero for tx checksum offload */
4876                 context_desc->mss_l4len_idx = 0;
4877
4878                 tx_buffer_info->time_stamp = jiffies;
4879                 tx_buffer_info->next_to_watch = i;
4880
4881                 adapter->hw_csum_tx_good++;
4882                 i++;
4883                 if (i == tx_ring->count)
4884                         i = 0;
4885                 tx_ring->next_to_use = i;
4886
4887                 return true;
4888         }
4889
4890         return false;
4891 }
4892
4893 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
4894                         struct ixgbe_ring *tx_ring,
4895                         struct sk_buff *skb, u32 tx_flags,
4896                         unsigned int first)
4897 {
4898         struct ixgbe_tx_buffer *tx_buffer_info;
4899         unsigned int len;
4900         unsigned int total = skb->len;
4901         unsigned int offset = 0, size, count = 0, i;
4902         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
4903         unsigned int f;
4904         dma_addr_t *map;
4905
4906         i = tx_ring->next_to_use;
4907
4908         if (skb_dma_map(&adapter->pdev->dev, skb, DMA_TO_DEVICE)) {
4909                 dev_err(&adapter->pdev->dev, "TX DMA map failed\n");
4910                 return 0;
4911         }
4912
4913         map = skb_shinfo(skb)->dma_maps;
4914
4915         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
4916                 /* excluding fcoe_crc_eof for FCoE */
4917                 total -= sizeof(struct fcoe_crc_eof);
4918
4919         len = min(skb_headlen(skb), total);
4920         while (len) {
4921                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4922                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4923
4924                 tx_buffer_info->length = size;
4925                 tx_buffer_info->dma = skb_shinfo(skb)->dma_head + offset;
4926                 tx_buffer_info->time_stamp = jiffies;
4927                 tx_buffer_info->next_to_watch = i;
4928
4929                 len -= size;
4930                 total -= size;
4931                 offset += size;
4932                 count++;
4933
4934                 if (len) {
4935                         i++;
4936                         if (i == tx_ring->count)
4937                                 i = 0;
4938                 }
4939         }
4940
4941         for (f = 0; f < nr_frags; f++) {
4942                 struct skb_frag_struct *frag;
4943
4944                 frag = &skb_shinfo(skb)->frags[f];
4945                 len = min((unsigned int)frag->size, total);
4946                 offset = 0;
4947
4948                 while (len) {
4949                         i++;
4950                         if (i == tx_ring->count)
4951                                 i = 0;
4952
4953                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
4954                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
4955
4956                         tx_buffer_info->length = size;
4957                         tx_buffer_info->dma = map[f] + offset;
4958                         tx_buffer_info->time_stamp = jiffies;
4959                         tx_buffer_info->next_to_watch = i;
4960
4961                         len -= size;
4962                         total -= size;
4963                         offset += size;
4964                         count++;
4965                 }
4966                 if (total == 0)
4967                         break;
4968         }
4969
4970         tx_ring->tx_buffer_info[i].skb = skb;
4971         tx_ring->tx_buffer_info[first].next_to_watch = i;
4972
4973         return count;
4974 }
4975
4976 static void ixgbe_tx_queue(struct ixgbe_adapter *adapter,
4977                            struct ixgbe_ring *tx_ring,
4978                            int tx_flags, int count, u32 paylen, u8 hdr_len)
4979 {
4980         union ixgbe_adv_tx_desc *tx_desc = NULL;
4981         struct ixgbe_tx_buffer *tx_buffer_info;
4982         u32 olinfo_status = 0, cmd_type_len = 0;
4983         unsigned int i;
4984         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
4985
4986         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
4987
4988         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
4989
4990         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
4991                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
4992
4993         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
4994                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
4995
4996                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
4997                                  IXGBE_ADVTXD_POPTS_SHIFT;
4998
4999                 /* use index 1 context for tso */
5000                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5001                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
5002                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
5003                                          IXGBE_ADVTXD_POPTS_SHIFT;
5004
5005         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
5006                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
5007                                  IXGBE_ADVTXD_POPTS_SHIFT;
5008
5009         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5010                 olinfo_status |= IXGBE_ADVTXD_CC;
5011                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
5012                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
5013                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
5014         }
5015
5016         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
5017
5018         i = tx_ring->next_to_use;
5019         while (count--) {
5020                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
5021                 tx_desc = IXGBE_TX_DESC_ADV(*tx_ring, i);
5022                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
5023                 tx_desc->read.cmd_type_len =
5024                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
5025                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
5026                 i++;
5027                 if (i == tx_ring->count)
5028                         i = 0;
5029         }
5030
5031         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
5032
5033         /*
5034          * Force memory writes to complete before letting h/w
5035          * know there are new descriptors to fetch.  (Only
5036          * applicable for weak-ordered memory model archs,
5037          * such as IA-64).
5038          */
5039         wmb();
5040
5041         tx_ring->next_to_use = i;
5042         writel(i, adapter->hw.hw_addr + tx_ring->tail);
5043 }
5044
5045 static void ixgbe_atr(struct ixgbe_adapter *adapter, struct sk_buff *skb,
5046                       int queue, u32 tx_flags)
5047 {
5048         /* Right now, we support IPv4 only */
5049         struct ixgbe_atr_input atr_input;
5050         struct tcphdr *th;
5051         struct udphdr *uh;
5052         struct iphdr *iph = ip_hdr(skb);
5053         struct ethhdr *eth = (struct ethhdr *)skb->data;
5054         u16 vlan_id, src_port, dst_port, flex_bytes;
5055         u32 src_ipv4_addr, dst_ipv4_addr;
5056         u8 l4type = 0;
5057
5058         /* check if we're UDP or TCP */
5059         if (iph->protocol == IPPROTO_TCP) {
5060                 th = tcp_hdr(skb);
5061                 src_port = th->source;
5062                 dst_port = th->dest;
5063                 l4type |= IXGBE_ATR_L4TYPE_TCP;
5064                 /* l4type IPv4 type is 0, no need to assign */
5065         } else if(iph->protocol == IPPROTO_UDP) {
5066                 uh = udp_hdr(skb);
5067                 src_port = uh->source;
5068                 dst_port = uh->dest;
5069                 l4type |= IXGBE_ATR_L4TYPE_UDP;
5070                 /* l4type IPv4 type is 0, no need to assign */
5071         } else {
5072                 /* Unsupported L4 header, just bail here */
5073                 return;
5074         }
5075
5076         memset(&atr_input, 0, sizeof(struct ixgbe_atr_input));
5077
5078         vlan_id = (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK) >>
5079                    IXGBE_TX_FLAGS_VLAN_SHIFT;
5080         src_ipv4_addr = iph->saddr;
5081         dst_ipv4_addr = iph->daddr;
5082         flex_bytes = eth->h_proto;
5083
5084         ixgbe_atr_set_vlan_id_82599(&atr_input, vlan_id);
5085         ixgbe_atr_set_src_port_82599(&atr_input, dst_port);
5086         ixgbe_atr_set_dst_port_82599(&atr_input, src_port);
5087         ixgbe_atr_set_flex_byte_82599(&atr_input, flex_bytes);
5088         ixgbe_atr_set_l4type_82599(&atr_input, l4type);
5089         /* src and dst are inverted, think how the receiver sees them */
5090         ixgbe_atr_set_src_ipv4_82599(&atr_input, dst_ipv4_addr);
5091         ixgbe_atr_set_dst_ipv4_82599(&atr_input, src_ipv4_addr);
5092
5093         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
5094         ixgbe_fdir_add_signature_filter_82599(&adapter->hw, &atr_input, queue);
5095 }
5096
5097 static int __ixgbe_maybe_stop_tx(struct net_device *netdev,
5098                                  struct ixgbe_ring *tx_ring, int size)
5099 {
5100         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5101
5102         netif_stop_subqueue(netdev, tx_ring->queue_index);
5103         /* Herbert's original patch had:
5104          *  smp_mb__after_netif_stop_queue();
5105          * but since that doesn't exist yet, just open code it. */
5106         smp_mb();
5107
5108         /* We need to check again in a case another CPU has just
5109          * made room available. */
5110         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
5111                 return -EBUSY;
5112
5113         /* A reprieve! - use start_queue because it doesn't call schedule */
5114         netif_start_subqueue(netdev, tx_ring->queue_index);
5115         ++adapter->restart_queue;
5116         return 0;
5117 }
5118
5119 static int ixgbe_maybe_stop_tx(struct net_device *netdev,
5120                               struct ixgbe_ring *tx_ring, int size)
5121 {
5122         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
5123                 return 0;
5124         return __ixgbe_maybe_stop_tx(netdev, tx_ring, size);
5125 }
5126
5127 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
5128 {
5129         struct ixgbe_adapter *adapter = netdev_priv(dev);
5130
5131         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
5132                 return smp_processor_id();
5133
5134         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5135                 return (skb->vlan_tci & IXGBE_TX_FLAGS_VLAN_PRIO_MASK) >> 13;
5136
5137         return skb_tx_hash(dev, skb);
5138 }
5139
5140 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb,
5141                                     struct net_device *netdev)
5142 {
5143         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5144         struct ixgbe_ring *tx_ring;
5145         unsigned int first;
5146         unsigned int tx_flags = 0;
5147         u8 hdr_len = 0;
5148         int r_idx = 0, tso;
5149         int count = 0;
5150         unsigned int f;
5151
5152         if (adapter->vlgrp && vlan_tx_tag_present(skb)) {
5153                 tx_flags |= vlan_tx_tag_get(skb);
5154                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5155                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
5156                         tx_flags |= (skb->queue_mapping << 13);
5157                 }
5158                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5159                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
5160         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5161                 if (skb->priority != TC_PRIO_CONTROL) {
5162                         tx_flags |= (skb->queue_mapping << 13);
5163                         tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
5164                         tx_flags |= IXGBE_TX_FLAGS_VLAN;
5165                 } else {
5166                         skb->queue_mapping =
5167                                 adapter->ring_feature[RING_F_DCB].indices-1;
5168                 }
5169         }
5170
5171         r_idx = skb->queue_mapping;
5172         tx_ring = &adapter->tx_ring[r_idx];
5173
5174         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
5175             (skb->protocol == htons(ETH_P_FCOE))) {
5176                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
5177 #ifdef IXGBE_FCOE
5178                 r_idx = smp_processor_id();
5179                 r_idx &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
5180                 r_idx += adapter->ring_feature[RING_F_FCOE].mask;
5181                 tx_ring = &adapter->tx_ring[r_idx];
5182 #endif
5183         }
5184         /* four things can cause us to need a context descriptor */
5185         if (skb_is_gso(skb) ||
5186             (skb->ip_summed == CHECKSUM_PARTIAL) ||
5187             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
5188             (tx_flags & IXGBE_TX_FLAGS_FCOE))
5189                 count++;
5190
5191         count += TXD_USE_COUNT(skb_headlen(skb));
5192         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
5193                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
5194
5195         if (ixgbe_maybe_stop_tx(netdev, tx_ring, count)) {
5196                 adapter->tx_busy++;
5197                 return NETDEV_TX_BUSY;
5198         }
5199
5200         first = tx_ring->next_to_use;
5201         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
5202 #ifdef IXGBE_FCOE
5203                 /* setup tx offload for FCoE */
5204                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5205                 if (tso < 0) {
5206                         dev_kfree_skb_any(skb);
5207                         return NETDEV_TX_OK;
5208                 }
5209                 if (tso)
5210                         tx_flags |= IXGBE_TX_FLAGS_FSO;
5211 #endif /* IXGBE_FCOE */
5212         } else {
5213                 if (skb->protocol == htons(ETH_P_IP))
5214                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
5215                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len);
5216                 if (tso < 0) {
5217                         dev_kfree_skb_any(skb);
5218                         return NETDEV_TX_OK;
5219                 }
5220
5221                 if (tso)
5222                         tx_flags |= IXGBE_TX_FLAGS_TSO;
5223                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags) &&
5224                          (skb->ip_summed == CHECKSUM_PARTIAL))
5225                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
5226         }
5227
5228         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first);
5229         if (count) {
5230                 /* add the ATR filter if ATR is on */
5231                 if (tx_ring->atr_sample_rate) {
5232                         ++tx_ring->atr_count;
5233                         if ((tx_ring->atr_count >= tx_ring->atr_sample_rate) &&
5234                              test_bit(__IXGBE_FDIR_INIT_DONE,
5235                                       &tx_ring->reinit_state)) {
5236                                 ixgbe_atr(adapter, skb, tx_ring->queue_index,
5237                                           tx_flags);
5238                                 tx_ring->atr_count = 0;
5239                         }
5240                 }
5241                 ixgbe_tx_queue(adapter, tx_ring, tx_flags, count, skb->len,
5242                                hdr_len);
5243                 ixgbe_maybe_stop_tx(netdev, tx_ring, DESC_NEEDED);
5244
5245         } else {
5246                 dev_kfree_skb_any(skb);
5247                 tx_ring->tx_buffer_info[first].time_stamp = 0;
5248                 tx_ring->next_to_use = first;
5249         }
5250
5251         return NETDEV_TX_OK;
5252 }
5253
5254 /**
5255  * ixgbe_get_stats - Get System Network Statistics
5256  * @netdev: network interface device structure
5257  *
5258  * Returns the address of the device statistics structure.
5259  * The statistics are actually updated from the timer callback.
5260  **/
5261 static struct net_device_stats *ixgbe_get_stats(struct net_device *netdev)
5262 {
5263         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5264
5265         /* only return the current stats */
5266         return &adapter->net_stats;
5267 }
5268
5269 /**
5270  * ixgbe_set_mac - Change the Ethernet Address of the NIC
5271  * @netdev: network interface device structure
5272  * @p: pointer to an address structure
5273  *
5274  * Returns 0 on success, negative on failure
5275  **/
5276 static int ixgbe_set_mac(struct net_device *netdev, void *p)
5277 {
5278         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5279         struct ixgbe_hw *hw = &adapter->hw;
5280         struct sockaddr *addr = p;
5281
5282         if (!is_valid_ether_addr(addr->sa_data))
5283                 return -EADDRNOTAVAIL;
5284
5285         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
5286         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
5287
5288         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, 0, IXGBE_RAH_AV);
5289
5290         return 0;
5291 }
5292
5293 static int
5294 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
5295 {
5296         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5297         struct ixgbe_hw *hw = &adapter->hw;
5298         u16 value;
5299         int rc;
5300
5301         if (prtad != hw->phy.mdio.prtad)
5302                 return -EINVAL;
5303         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
5304         if (!rc)
5305                 rc = value;
5306         return rc;
5307 }
5308
5309 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
5310                             u16 addr, u16 value)
5311 {
5312         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5313         struct ixgbe_hw *hw = &adapter->hw;
5314
5315         if (prtad != hw->phy.mdio.prtad)
5316                 return -EINVAL;
5317         return hw->phy.ops.write_reg(hw, addr, devad, value);
5318 }
5319
5320 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
5321 {
5322         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5323
5324         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
5325 }
5326
5327 /**
5328  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
5329  * netdev->dev_addrs
5330  * @netdev: network interface device structure
5331  *
5332  * Returns non-zero on failure
5333  **/
5334 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
5335 {
5336         int err = 0;
5337         struct ixgbe_adapter *adapter = netdev_priv(dev);
5338         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5339
5340         if (is_valid_ether_addr(mac->san_addr)) {
5341                 rtnl_lock();
5342                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5343                 rtnl_unlock();
5344         }
5345         return err;
5346 }
5347
5348 /**
5349  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
5350  * netdev->dev_addrs
5351  * @netdev: network interface device structure
5352  *
5353  * Returns non-zero on failure
5354  **/
5355 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
5356 {
5357         int err = 0;
5358         struct ixgbe_adapter *adapter = netdev_priv(dev);
5359         struct ixgbe_mac_info *mac = &adapter->hw.mac;
5360
5361         if (is_valid_ether_addr(mac->san_addr)) {
5362                 rtnl_lock();
5363                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
5364                 rtnl_unlock();
5365         }
5366         return err;
5367 }
5368
5369 #ifdef CONFIG_NET_POLL_CONTROLLER
5370 /*
5371  * Polling 'interrupt' - used by things like netconsole to send skbs
5372  * without having to re-enable interrupts. It's not called while
5373  * the interrupt routine is executing.
5374  */
5375 static void ixgbe_netpoll(struct net_device *netdev)
5376 {
5377         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5378         int i;
5379
5380         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
5381         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
5382                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
5383                 for (i = 0; i < num_q_vectors; i++) {
5384                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
5385                         ixgbe_msix_clean_many(0, q_vector);
5386                 }
5387         } else {
5388                 ixgbe_intr(adapter->pdev->irq, netdev);
5389         }
5390         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
5391 }
5392 #endif
5393
5394 static const struct net_device_ops ixgbe_netdev_ops = {
5395         .ndo_open               = ixgbe_open,
5396         .ndo_stop               = ixgbe_close,
5397         .ndo_start_xmit         = ixgbe_xmit_frame,
5398         .ndo_select_queue       = ixgbe_select_queue,
5399         .ndo_get_stats          = ixgbe_get_stats,
5400         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
5401         .ndo_set_multicast_list = ixgbe_set_rx_mode,
5402         .ndo_validate_addr      = eth_validate_addr,
5403         .ndo_set_mac_address    = ixgbe_set_mac,
5404         .ndo_change_mtu         = ixgbe_change_mtu,
5405         .ndo_tx_timeout         = ixgbe_tx_timeout,
5406         .ndo_vlan_rx_register   = ixgbe_vlan_rx_register,
5407         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
5408         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
5409         .ndo_do_ioctl           = ixgbe_ioctl,
5410 #ifdef CONFIG_NET_POLL_CONTROLLER
5411         .ndo_poll_controller    = ixgbe_netpoll,
5412 #endif
5413 #ifdef IXGBE_FCOE
5414         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
5415         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
5416         .ndo_fcoe_enable = ixgbe_fcoe_enable,
5417         .ndo_fcoe_disable = ixgbe_fcoe_disable,
5418 #endif /* IXGBE_FCOE */
5419 };
5420
5421 /**
5422  * ixgbe_probe - Device Initialization Routine
5423  * @pdev: PCI device information struct
5424  * @ent: entry in ixgbe_pci_tbl
5425  *
5426  * Returns 0 on success, negative on failure
5427  *
5428  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
5429  * The OS initialization, configuring of the adapter private structure,
5430  * and a hardware reset occur.
5431  **/
5432 static int __devinit ixgbe_probe(struct pci_dev *pdev,
5433                                  const struct pci_device_id *ent)
5434 {
5435         struct net_device *netdev;
5436         struct ixgbe_adapter *adapter = NULL;
5437         struct ixgbe_hw *hw;
5438         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
5439         static int cards_found;
5440         int i, err, pci_using_dac;
5441 #ifdef IXGBE_FCOE
5442         u16 device_caps;
5443 #endif
5444         u32 part_num, eec;
5445
5446         err = pci_enable_device_mem(pdev);
5447         if (err)
5448                 return err;
5449
5450         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
5451             !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
5452                 pci_using_dac = 1;
5453         } else {
5454                 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
5455                 if (err) {
5456                         err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5457                         if (err) {
5458                                 dev_err(&pdev->dev, "No usable DMA "
5459                                         "configuration, aborting\n");
5460                                 goto err_dma;
5461                         }
5462                 }
5463                 pci_using_dac = 0;
5464         }
5465
5466         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
5467                                            IORESOURCE_MEM), ixgbe_driver_name);
5468         if (err) {
5469                 dev_err(&pdev->dev,
5470                         "pci_request_selected_regions failed 0x%x\n", err);
5471                 goto err_pci_reg;
5472         }
5473
5474         err = pci_enable_pcie_error_reporting(pdev);
5475         if (err) {
5476                 dev_err(&pdev->dev, "pci_enable_pcie_error_reporting failed "
5477                                     "0x%x\n", err);
5478                 /* non-fatal, continue */
5479         }
5480
5481         pci_set_master(pdev);
5482         pci_save_state(pdev);
5483
5484         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), MAX_TX_QUEUES);
5485         if (!netdev) {
5486                 err = -ENOMEM;
5487                 goto err_alloc_etherdev;
5488         }
5489
5490         SET_NETDEV_DEV(netdev, &pdev->dev);
5491
5492         pci_set_drvdata(pdev, netdev);
5493         adapter = netdev_priv(netdev);
5494
5495         adapter->netdev = netdev;
5496         adapter->pdev = pdev;
5497         hw = &adapter->hw;
5498         hw->back = adapter;
5499         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
5500
5501         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
5502                               pci_resource_len(pdev, 0));
5503         if (!hw->hw_addr) {
5504                 err = -EIO;
5505                 goto err_ioremap;
5506         }
5507
5508         for (i = 1; i <= 5; i++) {
5509                 if (pci_resource_len(pdev, i) == 0)
5510                         continue;
5511         }
5512
5513         netdev->netdev_ops = &ixgbe_netdev_ops;
5514         ixgbe_set_ethtool_ops(netdev);
5515         netdev->watchdog_timeo = 5 * HZ;
5516         strcpy(netdev->name, pci_name(pdev));
5517
5518         adapter->bd_number = cards_found;
5519
5520         /* Setup hw api */
5521         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
5522         hw->mac.type  = ii->mac;
5523
5524         /* EEPROM */
5525         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
5526         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
5527         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
5528         if (!(eec & (1 << 8)))
5529                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
5530
5531         /* PHY */
5532         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
5533         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
5534         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
5535         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
5536         hw->phy.mdio.mmds = 0;
5537         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
5538         hw->phy.mdio.dev = netdev;
5539         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
5540         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
5541
5542         /* set up this timer and work struct before calling get_invariants
5543          * which might start the timer
5544          */
5545         init_timer(&adapter->sfp_timer);
5546         adapter->sfp_timer.function = &ixgbe_sfp_timer;
5547         adapter->sfp_timer.data = (unsigned long) adapter;
5548
5549         INIT_WORK(&adapter->sfp_task, ixgbe_sfp_task);
5550
5551         /* multispeed fiber has its own tasklet, called from GPI SDP1 context */
5552         INIT_WORK(&adapter->multispeed_fiber_task, ixgbe_multispeed_fiber_task);
5553
5554         /* a new SFP+ module arrival, called from GPI SDP2 context */
5555         INIT_WORK(&adapter->sfp_config_module_task,
5556                   ixgbe_sfp_config_module_task);
5557
5558         ii->get_invariants(hw);
5559
5560         /* setup the private structure */
5561         err = ixgbe_sw_init(adapter);
5562         if (err)
5563                 goto err_sw_init;
5564
5565         /*
5566          * If there is a fan on this device and it has failed log the
5567          * failure.
5568          */
5569         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
5570                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
5571                 if (esdp & IXGBE_ESDP_SDP1)
5572                         DPRINTK(PROBE, CRIT,
5573                                 "Fan has stopped, replace the adapter\n");
5574         }
5575
5576         /* reset_hw fills in the perm_addr as well */
5577         err = hw->mac.ops.reset_hw(hw);
5578         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
5579             hw->mac.type == ixgbe_mac_82598EB) {
5580                 /*
5581                  * Start a kernel thread to watch for a module to arrive.
5582                  * Only do this for 82598, since 82599 will generate
5583                  * interrupts on module arrival.
5584                  */
5585                 set_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5586                 mod_timer(&adapter->sfp_timer,
5587                           round_jiffies(jiffies + (2 * HZ)));
5588                 err = 0;
5589         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
5590                 dev_err(&adapter->pdev->dev, "failed to initialize because "
5591                         "an unsupported SFP+ module type was detected.\n"
5592                         "Reload the driver after installing a supported "
5593                         "module.\n");
5594                 goto err_sw_init;
5595         } else if (err) {
5596                 dev_err(&adapter->pdev->dev, "HW Init failed: %d\n", err);
5597                 goto err_sw_init;
5598         }
5599
5600         netdev->features = NETIF_F_SG |
5601                            NETIF_F_IP_CSUM |
5602                            NETIF_F_HW_VLAN_TX |
5603                            NETIF_F_HW_VLAN_RX |
5604                            NETIF_F_HW_VLAN_FILTER;
5605
5606         netdev->features |= NETIF_F_IPV6_CSUM;
5607         netdev->features |= NETIF_F_TSO;
5608         netdev->features |= NETIF_F_TSO6;
5609         netdev->features |= NETIF_F_GRO;
5610
5611         if (adapter->hw.mac.type == ixgbe_mac_82599EB)
5612                 netdev->features |= NETIF_F_SCTP_CSUM;
5613
5614         netdev->vlan_features |= NETIF_F_TSO;
5615         netdev->vlan_features |= NETIF_F_TSO6;
5616         netdev->vlan_features |= NETIF_F_IP_CSUM;
5617         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
5618         netdev->vlan_features |= NETIF_F_SG;
5619
5620         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED)
5621                 adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
5622
5623 #ifdef CONFIG_IXGBE_DCB
5624         netdev->dcbnl_ops = &dcbnl_ops;
5625 #endif
5626
5627 #ifdef IXGBE_FCOE
5628         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
5629                 if (hw->mac.ops.get_device_caps) {
5630                         hw->mac.ops.get_device_caps(hw, &device_caps);
5631                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
5632                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
5633                 }
5634         }
5635 #endif /* IXGBE_FCOE */
5636         if (pci_using_dac)
5637                 netdev->features |= NETIF_F_HIGHDMA;
5638
5639         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
5640                 netdev->features |= NETIF_F_LRO;
5641
5642         /* make sure the EEPROM is good */
5643         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
5644                 dev_err(&pdev->dev, "The EEPROM Checksum Is Not Valid\n");
5645                 err = -EIO;
5646                 goto err_eeprom;
5647         }
5648
5649         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
5650         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
5651
5652         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
5653                 dev_err(&pdev->dev, "invalid MAC address\n");
5654                 err = -EIO;
5655                 goto err_eeprom;
5656         }
5657
5658         init_timer(&adapter->watchdog_timer);
5659         adapter->watchdog_timer.function = &ixgbe_watchdog;
5660         adapter->watchdog_timer.data = (unsigned long)adapter;
5661
5662         INIT_WORK(&adapter->reset_task, ixgbe_reset_task);
5663         INIT_WORK(&adapter->watchdog_task, ixgbe_watchdog_task);
5664
5665         err = ixgbe_init_interrupt_scheme(adapter);
5666         if (err)
5667                 goto err_sw_init;
5668
5669         switch (pdev->device) {
5670         case IXGBE_DEV_ID_82599_KX4:
5671                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
5672                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
5673                 /* Enable ACPI wakeup in GRC */
5674                 IXGBE_WRITE_REG(hw, IXGBE_GRC,
5675                              (IXGBE_READ_REG(hw, IXGBE_GRC) & ~IXGBE_GRC_APME));
5676                 break;
5677         default:
5678                 adapter->wol = 0;
5679                 break;
5680         }
5681         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
5682
5683         /* pick up the PCI bus settings for reporting later */
5684         hw->mac.ops.get_bus_info(hw);
5685
5686         /* print bus type/speed/width info */
5687         dev_info(&pdev->dev, "(PCI Express:%s:%s) %pM\n",
5688                 ((hw->bus.speed == ixgbe_bus_speed_5000) ? "5.0Gb/s":
5689                  (hw->bus.speed == ixgbe_bus_speed_2500) ? "2.5Gb/s":"Unknown"),
5690                 ((hw->bus.width == ixgbe_bus_width_pcie_x8) ? "Width x8" :
5691                  (hw->bus.width == ixgbe_bus_width_pcie_x4) ? "Width x4" :
5692                  (hw->bus.width == ixgbe_bus_width_pcie_x1) ? "Width x1" :
5693                  "Unknown"),
5694                 netdev->dev_addr);
5695         ixgbe_read_pba_num_generic(hw, &part_num);
5696         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
5697                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, SFP+: %d, PBA No: %06x-%03x\n",
5698                          hw->mac.type, hw->phy.type, hw->phy.sfp_type,
5699                          (part_num >> 8), (part_num & 0xff));
5700         else
5701                 dev_info(&pdev->dev, "MAC: %d, PHY: %d, PBA No: %06x-%03x\n",
5702                          hw->mac.type, hw->phy.type,
5703                          (part_num >> 8), (part_num & 0xff));
5704
5705         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
5706                 dev_warn(&pdev->dev, "PCI-Express bandwidth available for "
5707                          "this card is not sufficient for optimal "
5708                          "performance.\n");
5709                 dev_warn(&pdev->dev, "For optimal performance a x8 "
5710                          "PCI-Express slot is required.\n");
5711         }
5712
5713         /* save off EEPROM version number */
5714         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
5715
5716         /* reset the hardware with the new settings */
5717         err = hw->mac.ops.start_hw(hw);
5718
5719         if (err == IXGBE_ERR_EEPROM_VERSION) {
5720                 /* We are running on a pre-production device, log a warning */
5721                 dev_warn(&pdev->dev, "This device is a pre-production "
5722                          "adapter/LOM.  Please be aware there may be issues "
5723                          "associated with your hardware.  If you are "
5724                          "experiencing problems please contact your Intel or "
5725                          "hardware representative who provided you with this "
5726                          "hardware.\n");
5727         }
5728         strcpy(netdev->name, "eth%d");
5729         err = register_netdev(netdev);
5730         if (err)
5731                 goto err_register;
5732
5733         /* carrier off reporting is important to ethtool even BEFORE open */
5734         netif_carrier_off(netdev);
5735
5736         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5737             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5738                 INIT_WORK(&adapter->fdir_reinit_task, ixgbe_fdir_reinit_task);
5739
5740 #ifdef CONFIG_IXGBE_DCA
5741         if (dca_add_requester(&pdev->dev) == 0) {
5742                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
5743                 ixgbe_setup_dca(adapter);
5744         }
5745 #endif
5746         /* add san mac addr to netdev */
5747         ixgbe_add_sanmac_netdev(netdev);
5748
5749         dev_info(&pdev->dev, "Intel(R) 10 Gigabit Network Connection\n");
5750         cards_found++;
5751         return 0;
5752
5753 err_register:
5754         ixgbe_release_hw_control(adapter);
5755         ixgbe_clear_interrupt_scheme(adapter);
5756 err_sw_init:
5757 err_eeprom:
5758         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5759         del_timer_sync(&adapter->sfp_timer);
5760         cancel_work_sync(&adapter->sfp_task);
5761         cancel_work_sync(&adapter->multispeed_fiber_task);
5762         cancel_work_sync(&adapter->sfp_config_module_task);
5763         iounmap(hw->hw_addr);
5764 err_ioremap:
5765         free_netdev(netdev);
5766 err_alloc_etherdev:
5767         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5768                                      IORESOURCE_MEM));
5769 err_pci_reg:
5770 err_dma:
5771         pci_disable_device(pdev);
5772         return err;
5773 }
5774
5775 /**
5776  * ixgbe_remove - Device Removal Routine
5777  * @pdev: PCI device information struct
5778  *
5779  * ixgbe_remove is called by the PCI subsystem to alert the driver
5780  * that it should release a PCI device.  The could be caused by a
5781  * Hot-Plug event, or because the driver is going to be removed from
5782  * memory.
5783  **/
5784 static void __devexit ixgbe_remove(struct pci_dev *pdev)
5785 {
5786         struct net_device *netdev = pci_get_drvdata(pdev);
5787         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5788         int err;
5789
5790         set_bit(__IXGBE_DOWN, &adapter->state);
5791         /* clear the module not found bit to make sure the worker won't
5792          * reschedule
5793          */
5794         clear_bit(__IXGBE_SFP_MODULE_NOT_FOUND, &adapter->state);
5795         del_timer_sync(&adapter->watchdog_timer);
5796
5797         del_timer_sync(&adapter->sfp_timer);
5798         cancel_work_sync(&adapter->watchdog_task);
5799         cancel_work_sync(&adapter->sfp_task);
5800         cancel_work_sync(&adapter->multispeed_fiber_task);
5801         cancel_work_sync(&adapter->sfp_config_module_task);
5802         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
5803             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
5804                 cancel_work_sync(&adapter->fdir_reinit_task);
5805         flush_scheduled_work();
5806
5807 #ifdef CONFIG_IXGBE_DCA
5808         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
5809                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
5810                 dca_remove_requester(&pdev->dev);
5811                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
5812         }
5813
5814 #endif
5815 #ifdef IXGBE_FCOE
5816         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
5817                 ixgbe_cleanup_fcoe(adapter);
5818
5819 #endif /* IXGBE_FCOE */
5820
5821         /* remove the added san mac */
5822         ixgbe_del_sanmac_netdev(netdev);
5823
5824         if (netdev->reg_state == NETREG_REGISTERED)
5825                 unregister_netdev(netdev);
5826
5827         ixgbe_clear_interrupt_scheme(adapter);
5828
5829         ixgbe_release_hw_control(adapter);
5830
5831         iounmap(adapter->hw.hw_addr);
5832         pci_release_selected_regions(pdev, pci_select_bars(pdev,
5833                                      IORESOURCE_MEM));
5834
5835         DPRINTK(PROBE, INFO, "complete\n");
5836
5837         free_netdev(netdev);
5838
5839         err = pci_disable_pcie_error_reporting(pdev);
5840         if (err)
5841                 dev_err(&pdev->dev,
5842                         "pci_disable_pcie_error_reporting failed 0x%x\n", err);
5843
5844         pci_disable_device(pdev);
5845 }
5846
5847 /**
5848  * ixgbe_io_error_detected - called when PCI error is detected
5849  * @pdev: Pointer to PCI device
5850  * @state: The current pci connection state
5851  *
5852  * This function is called after a PCI bus error affecting
5853  * this device has been detected.
5854  */
5855 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
5856                                                 pci_channel_state_t state)
5857 {
5858         struct net_device *netdev = pci_get_drvdata(pdev);
5859         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5860
5861         netif_device_detach(netdev);
5862
5863         if (state == pci_channel_io_perm_failure)
5864                 return PCI_ERS_RESULT_DISCONNECT;
5865
5866         if (netif_running(netdev))
5867                 ixgbe_down(adapter);
5868         pci_disable_device(pdev);
5869
5870         /* Request a slot reset. */
5871         return PCI_ERS_RESULT_NEED_RESET;
5872 }
5873
5874 /**
5875  * ixgbe_io_slot_reset - called after the pci bus has been reset.
5876  * @pdev: Pointer to PCI device
5877  *
5878  * Restart the card from scratch, as if from a cold-boot.
5879  */
5880 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
5881 {
5882         struct net_device *netdev = pci_get_drvdata(pdev);
5883         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5884         pci_ers_result_t result;
5885         int err;
5886
5887         if (pci_enable_device_mem(pdev)) {
5888                 DPRINTK(PROBE, ERR,
5889                         "Cannot re-enable PCI device after reset.\n");
5890                 result = PCI_ERS_RESULT_DISCONNECT;
5891         } else {
5892                 pci_set_master(pdev);
5893                 pci_restore_state(pdev);
5894
5895                 pci_wake_from_d3(pdev, false);
5896
5897                 ixgbe_reset(adapter);
5898                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5899                 result = PCI_ERS_RESULT_RECOVERED;
5900         }
5901
5902         err = pci_cleanup_aer_uncorrect_error_status(pdev);
5903         if (err) {
5904                 dev_err(&pdev->dev,
5905                   "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n", err);
5906                 /* non-fatal, continue */
5907         }
5908
5909         return result;
5910 }
5911
5912 /**
5913  * ixgbe_io_resume - called when traffic can start flowing again.
5914  * @pdev: Pointer to PCI device
5915  *
5916  * This callback is called when the error recovery driver tells us that
5917  * its OK to resume normal operation.
5918  */
5919 static void ixgbe_io_resume(struct pci_dev *pdev)
5920 {
5921         struct net_device *netdev = pci_get_drvdata(pdev);
5922         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5923
5924         if (netif_running(netdev)) {
5925                 if (ixgbe_up(adapter)) {
5926                         DPRINTK(PROBE, INFO, "ixgbe_up failed after reset\n");
5927                         return;
5928                 }
5929         }
5930
5931         netif_device_attach(netdev);
5932 }
5933
5934 static struct pci_error_handlers ixgbe_err_handler = {
5935         .error_detected = ixgbe_io_error_detected,
5936         .slot_reset = ixgbe_io_slot_reset,
5937         .resume = ixgbe_io_resume,
5938 };
5939
5940 static struct pci_driver ixgbe_driver = {
5941         .name     = ixgbe_driver_name,
5942         .id_table = ixgbe_pci_tbl,
5943         .probe    = ixgbe_probe,
5944         .remove   = __devexit_p(ixgbe_remove),
5945 #ifdef CONFIG_PM
5946         .suspend  = ixgbe_suspend,
5947         .resume   = ixgbe_resume,
5948 #endif
5949         .shutdown = ixgbe_shutdown,
5950         .err_handler = &ixgbe_err_handler
5951 };
5952
5953 /**
5954  * ixgbe_init_module - Driver Registration Routine
5955  *
5956  * ixgbe_init_module is the first routine called when the driver is
5957  * loaded. All it does is register with the PCI subsystem.
5958  **/
5959 static int __init ixgbe_init_module(void)
5960 {
5961         int ret;
5962         printk(KERN_INFO "%s: %s - version %s\n", ixgbe_driver_name,
5963                ixgbe_driver_string, ixgbe_driver_version);
5964
5965         printk(KERN_INFO "%s: %s\n", ixgbe_driver_name, ixgbe_copyright);
5966
5967 #ifdef CONFIG_IXGBE_DCA
5968         dca_register_notify(&dca_notifier);
5969 #endif
5970
5971         ret = pci_register_driver(&ixgbe_driver);
5972         return ret;
5973 }
5974
5975 module_init(ixgbe_init_module);
5976
5977 /**
5978  * ixgbe_exit_module - Driver Exit Cleanup Routine
5979  *
5980  * ixgbe_exit_module is called just before the driver is removed
5981  * from memory.
5982  **/
5983 static void __exit ixgbe_exit_module(void)
5984 {
5985 #ifdef CONFIG_IXGBE_DCA
5986         dca_unregister_notify(&dca_notifier);
5987 #endif
5988         pci_unregister_driver(&ixgbe_driver);
5989 }
5990
5991 #ifdef CONFIG_IXGBE_DCA
5992 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
5993                             void *p)
5994 {
5995         int ret_val;
5996
5997         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
5998                                          __ixgbe_notify_dca);
5999
6000         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
6001 }
6002
6003 #endif /* CONFIG_IXGBE_DCA */
6004 #ifdef DEBUG
6005 /**
6006  * ixgbe_get_hw_dev_name - return device name string
6007  * used by hardware layer to print debugging information
6008  **/
6009 char *ixgbe_get_hw_dev_name(struct ixgbe_hw *hw)
6010 {
6011         struct ixgbe_adapter *adapter = hw->back;
6012         return adapter->netdev->name;
6013 }
6014
6015 #endif
6016 module_exit(ixgbe_exit_module);
6017
6018 /* ixgbe_main.c */