drivers/net/ixgbe/ixgbe_main.c

   1 /*******************************************************************************
   2
   3   Intel 10 Gigabit PCI Express Linux driver
   4   Copyright(c) 1999 - 2011 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22   Contact Information:
  23   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
  24   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  25
  26 *******************************************************************************/
  27
  28 #include <linux/types.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/netdevice.h>
  32 #include <linux/vmalloc.h>
  33 #include <linux/string.h>
  34 #include <linux/in.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/ip.h>
  37 #include <linux/tcp.h>
  38 #include <linux/pkt_sched.h>
  39 #include <linux/ipv6.h>
  40 #include <linux/slab.h>
  41 #include <net/checksum.h>
  42 #include <net/ip6_checksum.h>
  43 #include <linux/ethtool.h>
  44 #include <linux/if_vlan.h>
  45 #include <linux/prefetch.h>
  46 #include <scsi/fc/fc_fcoe.h>
  47
  48 #include "ixgbe.h"
  49 #include "ixgbe_common.h"
  50 #include "ixgbe_dcb_82599.h"
  51 #include "ixgbe_sriov.h"
  52
  53 char ixgbe_driver_name[] = "ixgbe";
  54 static const char ixgbe_driver_string[] =
  55                               "Intel(R) 10 Gigabit PCI Express Network Driver";
  56 #define MAJ 3
  57 #define MIN 3
  58 #define BUILD 8
  59 #define KFIX 2
  60 #define DRV_VERSION __stringify(MAJ) "." __stringify(MIN) "." \
  61         __stringify(BUILD) "-k" __stringify(KFIX)
  62 const char ixgbe_driver_version[] = DRV_VERSION;
  63 static const char ixgbe_copyright[] =
  64                                 "Copyright (c) 1999-2011 Intel Corporation.";
  65
  66 static const struct ixgbe_info *ixgbe_info_tbl[] = {
  67         [board_82598] = &ixgbe_82598_info,
  68         [board_82599] = &ixgbe_82599_info,
  69         [board_X540] = &ixgbe_X540_info,
  70 };
  71
  72 /* ixgbe_pci_tbl - PCI Device ID Table
  73  *
  74  * Wildcard entries (PCI_ANY_ID) should come last
  75  * Last entry must be all 0s
  76  *
  77  * { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
  78  *   Class, Class Mask, private data (not used) }
  79  */
  80 static DEFINE_PCI_DEVICE_TABLE(ixgbe_pci_tbl) = {
  81         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598),
  82          board_82598 },
  83         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_DUAL_PORT),
  84          board_82598 },
  85         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AF_SINGLE_PORT),
  86          board_82598 },
  87         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT),
  88          board_82598 },
  89         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598AT2),
  90          board_82598 },
  91         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_CX4),
  92          board_82598 },
  93         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_CX4_DUAL_PORT),
  94          board_82598 },
  95         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_DA_DUAL_PORT),
  96          board_82598 },
  97         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM),
  98          board_82598 },
  99         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_XF_LR),
 100          board_82598 },
 101         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598EB_SFP_LOM),
 102          board_82598 },
 103         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82598_BX),
 104          board_82598 },
 105         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4),
 106          board_82599 },
 107         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_XAUI_LOM),
 108          board_82599 },
 109         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KR),
 110          board_82599 },
 111         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP),
 112          board_82599 },
 113         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_EM),
 114          board_82599 },
 115         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_KX4_MEZZ),
 116          board_82599 },
 117         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_CX4),
 118          board_82599 },
 119         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_BACKPLANE_FCOE),
 120          board_82599 },
 121         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_FCOE),
 122          board_82599 },
 123         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_T3_LOM),
 124          board_82599 },
 125         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_COMBO_BACKPLANE),
 126          board_82599 },
 127         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_X540T),
 128          board_X540 },
 129         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_SFP_SF2),
 130          board_82599 },
 131         {PCI_VDEVICE(INTEL, IXGBE_DEV_ID_82599_LS),
 132          board_82599 },
 133
 134         /* required last entry */
 135         {0, }
 136 };
 137 MODULE_DEVICE_TABLE(pci, ixgbe_pci_tbl);
 138
 139 #ifdef CONFIG_IXGBE_DCA
 140 static int ixgbe_notify_dca(struct notifier_block *, unsigned long event,
 141                             void *p);
 142 static struct notifier_block dca_notifier = {
 143         .notifier_call = ixgbe_notify_dca,
 144         .next          = NULL,
 145         .priority      = 0
 146 };
 147 #endif
 148
 149 #ifdef CONFIG_PCI_IOV
 150 static unsigned int max_vfs;
 151 module_param(max_vfs, uint, 0);
 152 MODULE_PARM_DESC(max_vfs,
 153                  "Maximum number of virtual functions to allocate per physical function");
 154 #endif /* CONFIG_PCI_IOV */
 155
 156 MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
 157 MODULE_DESCRIPTION("Intel(R) 10 Gigabit PCI Express Network Driver");
 158 MODULE_LICENSE("GPL");
 159 MODULE_VERSION(DRV_VERSION);
 160
 161 #define DEFAULT_DEBUG_LEVEL_SHIFT 3
 162
 163 static inline void ixgbe_disable_sriov(struct ixgbe_adapter *adapter)
 164 {
 165         struct ixgbe_hw *hw = &adapter->hw;
 166         u32 gcr;
 167         u32 gpie;
 168         u32 vmdctl;
 169
 170 #ifdef CONFIG_PCI_IOV
 171         /* disable iov and allow time for transactions to clear */
 172         pci_disable_sriov(adapter->pdev);
 173 #endif
 174
 175         /* turn off device IOV mode */
 176         gcr = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
 177         gcr &= ~(IXGBE_GCR_EXT_SRIOV);
 178         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr);
 179         gpie = IXGBE_READ_REG(hw, IXGBE_GPIE);
 180         gpie &= ~IXGBE_GPIE_VTMODE_MASK;
 181         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
 182
 183         /* set default pool back to 0 */
 184         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
 185         vmdctl &= ~IXGBE_VT_CTL_POOL_MASK;
 186         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl);
 187
 188         /* take a breather then clean up driver data */
 189         msleep(100);
 190
 191         kfree(adapter->vfinfo);
 192         adapter->vfinfo = NULL;
 193
 194         adapter->num_vfs = 0;
 195         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
 196 }
 197
 198 static void ixgbe_service_event_schedule(struct ixgbe_adapter *adapter)
 199 {
 200         if (!test_bit(__IXGBE_DOWN, &adapter->state) &&
 201             !test_and_set_bit(__IXGBE_SERVICE_SCHED, &adapter->state))
 202                 schedule_work(&adapter->service_task);
 203 }
 204
 205 static void ixgbe_service_event_complete(struct ixgbe_adapter *adapter)
 206 {
 207         BUG_ON(!test_bit(__IXGBE_SERVICE_SCHED, &adapter->state));
 208
 209         /* flush memory to make sure state is correct before next watchog */
 210         smp_mb__before_clear_bit();
 211         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
 212 }
 213
 214 struct ixgbe_reg_info {
 215         u32 ofs;
 216         char *name;
 217 };
 218
 219 static const struct ixgbe_reg_info ixgbe_reg_info_tbl[] = {
 220
 221         /* General Registers */
 222         {IXGBE_CTRL, "CTRL"},
 223         {IXGBE_STATUS, "STATUS"},
 224         {IXGBE_CTRL_EXT, "CTRL_EXT"},
 225
 226         /* Interrupt Registers */
 227         {IXGBE_EICR, "EICR"},
 228
 229         /* RX Registers */
 230         {IXGBE_SRRCTL(0), "SRRCTL"},
 231         {IXGBE_DCA_RXCTRL(0), "DRXCTL"},
 232         {IXGBE_RDLEN(0), "RDLEN"},
 233         {IXGBE_RDH(0), "RDH"},
 234         {IXGBE_RDT(0), "RDT"},
 235         {IXGBE_RXDCTL(0), "RXDCTL"},
 236         {IXGBE_RDBAL(0), "RDBAL"},
 237         {IXGBE_RDBAH(0), "RDBAH"},
 238
 239         /* TX Registers */
 240         {IXGBE_TDBAL(0), "TDBAL"},
 241         {IXGBE_TDBAH(0), "TDBAH"},
 242         {IXGBE_TDLEN(0), "TDLEN"},
 243         {IXGBE_TDH(0), "TDH"},
 244         {IXGBE_TDT(0), "TDT"},
 245         {IXGBE_TXDCTL(0), "TXDCTL"},
 246
 247         /* List Terminator */
 248         {}
 249 };
 250
 251
 252 /*
 253  * ixgbe_regdump - register printout routine
 254  */
 255 static void ixgbe_regdump(struct ixgbe_hw *hw, struct ixgbe_reg_info *reginfo)
 256 {
 257         int i = 0, j = 0;
 258         char rname[16];
 259         u32 regs[64];
 260
 261         switch (reginfo->ofs) {
 262         case IXGBE_SRRCTL(0):
 263                 for (i = 0; i < 64; i++)
 264                         regs[i] = IXGBE_READ_REG(hw, IXGBE_SRRCTL(i));
 265                 break;
 266         case IXGBE_DCA_RXCTRL(0):
 267                 for (i = 0; i < 64; i++)
 268                         regs[i] = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(i));
 269                 break;
 270         case IXGBE_RDLEN(0):
 271                 for (i = 0; i < 64; i++)
 272                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDLEN(i));
 273                 break;
 274         case IXGBE_RDH(0):
 275                 for (i = 0; i < 64; i++)
 276                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDH(i));
 277                 break;
 278         case IXGBE_RDT(0):
 279                 for (i = 0; i < 64; i++)
 280                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDT(i));
 281                 break;
 282         case IXGBE_RXDCTL(0):
 283                 for (i = 0; i < 64; i++)
 284                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RXDCTL(i));
 285                 break;
 286         case IXGBE_RDBAL(0):
 287                 for (i = 0; i < 64; i++)
 288                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAL(i));
 289                 break;
 290         case IXGBE_RDBAH(0):
 291                 for (i = 0; i < 64; i++)
 292                         regs[i] = IXGBE_READ_REG(hw, IXGBE_RDBAH(i));
 293                 break;
 294         case IXGBE_TDBAL(0):
 295                 for (i = 0; i < 64; i++)
 296                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAL(i));
 297                 break;
 298         case IXGBE_TDBAH(0):
 299                 for (i = 0; i < 64; i++)
 300                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDBAH(i));
 301                 break;
 302         case IXGBE_TDLEN(0):
 303                 for (i = 0; i < 64; i++)
 304                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDLEN(i));
 305                 break;
 306         case IXGBE_TDH(0):
 307                 for (i = 0; i < 64; i++)
 308                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDH(i));
 309                 break;
 310         case IXGBE_TDT(0):
 311                 for (i = 0; i < 64; i++)
 312                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TDT(i));
 313                 break;
 314         case IXGBE_TXDCTL(0):
 315                 for (i = 0; i < 64; i++)
 316                         regs[i] = IXGBE_READ_REG(hw, IXGBE_TXDCTL(i));
 317                 break;
 318         default:
 319                 pr_info("%-15s %08x\n", reginfo->name,
 320                         IXGBE_READ_REG(hw, reginfo->ofs));
 321                 return;
 322         }
 323
 324         for (i = 0; i < 8; i++) {
 325                 snprintf(rname, 16, "%s[%d-%d]", reginfo->name, i*8, i*8+7);
 326                 pr_err("%-15s", rname);
 327                 for (j = 0; j < 8; j++)
 328                         pr_cont(" %08x", regs[i*8+j]);
 329                 pr_cont("\n");
 330         }
 331
 332 }
 333
 334 /*
 335  * ixgbe_dump - Print registers, tx-rings and rx-rings
 336  */
 337 static void ixgbe_dump(struct ixgbe_adapter *adapter)
 338 {
 339         struct net_device *netdev = adapter->netdev;
 340         struct ixgbe_hw *hw = &adapter->hw;
 341         struct ixgbe_reg_info *reginfo;
 342         int n = 0;
 343         struct ixgbe_ring *tx_ring;
 344         struct ixgbe_tx_buffer *tx_buffer_info;
 345         union ixgbe_adv_tx_desc *tx_desc;
 346         struct my_u0 { u64 a; u64 b; } *u0;
 347         struct ixgbe_ring *rx_ring;
 348         union ixgbe_adv_rx_desc *rx_desc;
 349         struct ixgbe_rx_buffer *rx_buffer_info;
 350         u32 staterr;
 351         int i = 0;
 352
 353         if (!netif_msg_hw(adapter))
 354                 return;
 355
 356         /* Print netdevice Info */
 357         if (netdev) {
 358                 dev_info(&adapter->pdev->dev, "Net device Info\n");
 359                 pr_info("Device Name     state            "
 360                         "trans_start      last_rx\n");
 361                 pr_info("%-15s %016lX %016lX %016lX\n",
 362                         netdev->name,
 363                         netdev->state,
 364                         netdev->trans_start,
 365                         netdev->last_rx);
 366         }
 367
 368         /* Print Registers */
 369         dev_info(&adapter->pdev->dev, "Register Dump\n");
 370         pr_info(" Register Name   Value\n");
 371         for (reginfo = (struct ixgbe_reg_info *)ixgbe_reg_info_tbl;
 372              reginfo->name; reginfo++) {
 373                 ixgbe_regdump(hw, reginfo);
 374         }
 375
 376         /* Print TX Ring Summary */
 377         if (!netdev || !netif_running(netdev))
 378                 goto exit;
 379
 380         dev_info(&adapter->pdev->dev, "TX Rings Summary\n");
 381         pr_info("Queue [NTU] [NTC] [bi(ntc)->dma  ] leng ntw timestamp\n");
 382         for (n = 0; n < adapter->num_tx_queues; n++) {
 383                 tx_ring = adapter->tx_ring[n];
 384                 tx_buffer_info =
 385                         &tx_ring->tx_buffer_info[tx_ring->next_to_clean];
 386                 pr_info(" %5d %5X %5X %016llX %04X %3X %016llX\n",
 387                            n, tx_ring->next_to_use, tx_ring->next_to_clean,
 388                            (u64)tx_buffer_info->dma,
 389                            tx_buffer_info->length,
 390                            tx_buffer_info->next_to_watch,
 391                            (u64)tx_buffer_info->time_stamp);
 392         }
 393
 394         /* Print TX Rings */
 395         if (!netif_msg_tx_done(adapter))
 396                 goto rx_ring_summary;
 397
 398         dev_info(&adapter->pdev->dev, "TX Rings Dump\n");
 399
 400         /* Transmit Descriptor Formats
 401          *
 402          * Advanced Transmit Descriptor
 403          *   +--------------------------------------------------------------+
 404          * 0 |         Buffer Address [63:0]                                |
 405          *   +--------------------------------------------------------------+
 406          * 8 |  PAYLEN  | PORTS  | IDX | STA | DCMD  |DTYP |  RSV |  DTALEN |
 407          *   +--------------------------------------------------------------+
 408          *   63       46 45    40 39 36 35 32 31   24 23 20 19              0
 409          */
 410
 411         for (n = 0; n < adapter->num_tx_queues; n++) {
 412                 tx_ring = adapter->tx_ring[n];
 413                 pr_info("------------------------------------\n");
 414                 pr_info("TX QUEUE INDEX = %d\n", tx_ring->queue_index);
 415                 pr_info("------------------------------------\n");
 416                 pr_info("T [desc]     [address 63:0  ] "
 417                         "[PlPOIdStDDt Ln] [bi->dma       ] "
 418                         "leng  ntw timestamp        bi->skb\n");
 419
 420                 for (i = 0; tx_ring->desc && (i < tx_ring->count); i++) {
 421                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 422                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 423                         u0 = (struct my_u0 *)tx_desc;
 424                         pr_info("T [0x%03X]    %016llX %016llX %016llX"
 425                                 " %04X  %3X %016llX %p", i,
 426                                 le64_to_cpu(u0->a),
 427                                 le64_to_cpu(u0->b),
 428                                 (u64)tx_buffer_info->dma,
 429                                 tx_buffer_info->length,
 430                                 tx_buffer_info->next_to_watch,
 431                                 (u64)tx_buffer_info->time_stamp,
 432                                 tx_buffer_info->skb);
 433                         if (i == tx_ring->next_to_use &&
 434                                 i == tx_ring->next_to_clean)
 435                                 pr_cont(" NTC/U\n");
 436                         else if (i == tx_ring->next_to_use)
 437                                 pr_cont(" NTU\n");
 438                         else if (i == tx_ring->next_to_clean)
 439                                 pr_cont(" NTC\n");
 440                         else
 441                                 pr_cont("\n");
 442
 443                         if (netif_msg_pktdata(adapter) &&
 444                                 tx_buffer_info->dma != 0)
 445                                 print_hex_dump(KERN_INFO, "",
 446                                         DUMP_PREFIX_ADDRESS, 16, 1,
 447                                         phys_to_virt(tx_buffer_info->dma),
 448                                         tx_buffer_info->length, true);
 449                 }
 450         }
 451
 452         /* Print RX Rings Summary */
 453 rx_ring_summary:
 454         dev_info(&adapter->pdev->dev, "RX Rings Summary\n");
 455         pr_info("Queue [NTU] [NTC]\n");
 456         for (n = 0; n < adapter->num_rx_queues; n++) {
 457                 rx_ring = adapter->rx_ring[n];
 458                 pr_info("%5d %5X %5X\n",
 459                         n, rx_ring->next_to_use, rx_ring->next_to_clean);
 460         }
 461
 462         /* Print RX Rings */
 463         if (!netif_msg_rx_status(adapter))
 464                 goto exit;
 465
 466         dev_info(&adapter->pdev->dev, "RX Rings Dump\n");
 467
 468         /* Advanced Receive Descriptor (Read) Format
 469          *    63                                           1        0
 470          *    +-----------------------------------------------------+
 471          *  0 |       Packet Buffer Address [63:1]           |A0/NSE|
 472          *    +----------------------------------------------+------+
 473          *  8 |       Header Buffer Address [63:1]           |  DD  |
 474          *    +-----------------------------------------------------+
 475          *
 476          *
 477          * Advanced Receive Descriptor (Write-Back) Format
 478          *
 479          *   63       48 47    32 31  30      21 20 16 15   4 3     0
 480          *   +------------------------------------------------------+
 481          * 0 | Packet     IP     |SPH| HDR_LEN   | RSV|Packet|  RSS |
 482          *   | Checksum   Ident  |   |           |    | Type | Type |
 483          *   +------------------------------------------------------+
 484          * 8 | VLAN Tag | Length | Extended Error | Extended Status |
 485          *   +------------------------------------------------------+
 486          *   63       48 47    32 31            20 19               0
 487          */
 488         for (n = 0; n < adapter->num_rx_queues; n++) {
 489                 rx_ring = adapter->rx_ring[n];
 490                 pr_info("------------------------------------\n");
 491                 pr_info("RX QUEUE INDEX = %d\n", rx_ring->queue_index);
 492                 pr_info("------------------------------------\n");
 493                 pr_info("R  [desc]      [ PktBuf     A0] "
 494                         "[  HeadBuf   DD] [bi->dma       ] [bi->skb] "
 495                         "<-- Adv Rx Read format\n");
 496                 pr_info("RWB[desc]      [PcsmIpSHl PtRs] "
 497                         "[vl er S cks ln] ---------------- [bi->skb] "
 498                         "<-- Adv Rx Write-Back format\n");
 499
 500                 for (i = 0; i < rx_ring->count; i++) {
 501                         rx_buffer_info = &rx_ring->rx_buffer_info[i];
 502                         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
 503                         u0 = (struct my_u0 *)rx_desc;
 504                         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
 505                         if (staterr & IXGBE_RXD_STAT_DD) {
 506                                 /* Descriptor Done */
 507                                 pr_info("RWB[0x%03X]     %016llX "
 508                                         "%016llX ---------------- %p", i,
 509                                         le64_to_cpu(u0->a),
 510                                         le64_to_cpu(u0->b),
 511                                         rx_buffer_info->skb);
 512                         } else {
 513                                 pr_info("R  [0x%03X]     %016llX "
 514                                         "%016llX %016llX %p", i,
 515                                         le64_to_cpu(u0->a),
 516                                         le64_to_cpu(u0->b),
 517                                         (u64)rx_buffer_info->dma,
 518                                         rx_buffer_info->skb);
 519
 520                                 if (netif_msg_pktdata(adapter)) {
 521                                         print_hex_dump(KERN_INFO, "",
 522                                            DUMP_PREFIX_ADDRESS, 16, 1,
 523                                            phys_to_virt(rx_buffer_info->dma),
 524                                            rx_ring->rx_buf_len, true);
 525
 526                                         if (rx_ring->rx_buf_len
 527                                                 < IXGBE_RXBUFFER_2048)
 528                                                 print_hex_dump(KERN_INFO, "",
 529                                                   DUMP_PREFIX_ADDRESS, 16, 1,
 530                                                   phys_to_virt(
 531                                                     rx_buffer_info->page_dma +
 532                                                     rx_buffer_info->page_offset
 533                                                   ),
 534                                                   PAGE_SIZE/2, true);
 535                                 }
 536                         }
 537
 538                         if (i == rx_ring->next_to_use)
 539                                 pr_cont(" NTU\n");
 540                         else if (i == rx_ring->next_to_clean)
 541                                 pr_cont(" NTC\n");
 542                         else
 543                                 pr_cont("\n");
 544
 545                 }
 546         }
 547
 548 exit:
 549         return;
 550 }
 551
 552 static void ixgbe_release_hw_control(struct ixgbe_adapter *adapter)
 553 {
 554         u32 ctrl_ext;
 555
 556         /* Let firmware take over control of h/w */
 557         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 558         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 559                         ctrl_ext & ~IXGBE_CTRL_EXT_DRV_LOAD);
 560 }
 561
 562 static void ixgbe_get_hw_control(struct ixgbe_adapter *adapter)
 563 {
 564         u32 ctrl_ext;
 565
 566         /* Let firmware know the driver has taken over */
 567         ctrl_ext = IXGBE_READ_REG(&adapter->hw, IXGBE_CTRL_EXT);
 568         IXGBE_WRITE_REG(&adapter->hw, IXGBE_CTRL_EXT,
 569                         ctrl_ext | IXGBE_CTRL_EXT_DRV_LOAD);
 570 }
 571
 572 /*
 573  * ixgbe_set_ivar - set the IVAR registers, mapping interrupt causes to vectors
 574  * @adapter: pointer to adapter struct
 575  * @direction: 0 for Rx, 1 for Tx, -1 for other causes
 576  * @queue: queue to map the corresponding interrupt to
 577  * @msix_vector: the vector to map to the corresponding queue
 578  *
 579  */
 580 static void ixgbe_set_ivar(struct ixgbe_adapter *adapter, s8 direction,
 581                            u8 queue, u8 msix_vector)
 582 {
 583         u32 ivar, index;
 584         struct ixgbe_hw *hw = &adapter->hw;
 585         switch (hw->mac.type) {
 586         case ixgbe_mac_82598EB:
 587                 msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 588                 if (direction == -1)
 589                         direction = 0;
 590                 index = (((direction * 64) + queue) >> 2) & 0x1F;
 591                 ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(index));
 592                 ivar &= ~(0xFF << (8 * (queue & 0x3)));
 593                 ivar |= (msix_vector << (8 * (queue & 0x3)));
 594                 IXGBE_WRITE_REG(hw, IXGBE_IVAR(index), ivar);
 595                 break;
 596         case ixgbe_mac_82599EB:
 597         case ixgbe_mac_X540:
 598                 if (direction == -1) {
 599                         /* other causes */
 600                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 601                         index = ((queue & 1) * 8);
 602                         ivar = IXGBE_READ_REG(&adapter->hw, IXGBE_IVAR_MISC);
 603                         ivar &= ~(0xFF << index);
 604                         ivar |= (msix_vector << index);
 605                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_IVAR_MISC, ivar);
 606                         break;
 607                 } else {
 608                         /* tx or rx causes */
 609                         msix_vector |= IXGBE_IVAR_ALLOC_VAL;
 610                         index = ((16 * (queue & 1)) + (8 * direction));
 611                         ivar = IXGBE_READ_REG(hw, IXGBE_IVAR(queue >> 1));
 612                         ivar &= ~(0xFF << index);
 613                         ivar |= (msix_vector << index);
 614                         IXGBE_WRITE_REG(hw, IXGBE_IVAR(queue >> 1), ivar);
 615                         break;
 616                 }
 617         default:
 618                 break;
 619         }
 620 }
 621
 622 static inline void ixgbe_irq_rearm_queues(struct ixgbe_adapter *adapter,
 623                                           u64 qmask)
 624 {
 625         u32 mask;
 626
 627         switch (adapter->hw.mac.type) {
 628         case ixgbe_mac_82598EB:
 629                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
 630                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS, mask);
 631                 break;
 632         case ixgbe_mac_82599EB:
 633         case ixgbe_mac_X540:
 634                 mask = (qmask & 0xFFFFFFFF);
 635                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(0), mask);
 636                 mask = (qmask >> 32);
 637                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EICS_EX(1), mask);
 638                 break;
 639         default:
 640                 break;
 641         }
 642 }
 643
 644 void ixgbe_unmap_and_free_tx_resource(struct ixgbe_ring *tx_ring,
 645                                       struct ixgbe_tx_buffer *tx_buffer_info)
 646 {
 647         if (tx_buffer_info->dma) {
 648                 if (tx_buffer_info->mapped_as_page)
 649                         dma_unmap_page(tx_ring->dev,
 650                                        tx_buffer_info->dma,
 651                                        tx_buffer_info->length,
 652                                        DMA_TO_DEVICE);
 653                 else
 654                         dma_unmap_single(tx_ring->dev,
 655                                          tx_buffer_info->dma,
 656                                          tx_buffer_info->length,
 657                                          DMA_TO_DEVICE);
 658                 tx_buffer_info->dma = 0;
 659         }
 660         if (tx_buffer_info->skb) {
 661                 dev_kfree_skb_any(tx_buffer_info->skb);
 662                 tx_buffer_info->skb = NULL;
 663         }
 664         tx_buffer_info->time_stamp = 0;
 665         /* tx_buffer_info must be completely set up in the transmit path */
 666 }
 667
 668 static void ixgbe_update_xoff_received(struct ixgbe_adapter *adapter)
 669 {
 670         struct ixgbe_hw *hw = &adapter->hw;
 671         struct ixgbe_hw_stats *hwstats = &adapter->stats;
 672         u32 data = 0;
 673         u32 xoff[8] = {0};
 674         int i;
 675
 676         if ((hw->fc.current_mode == ixgbe_fc_full) ||
 677             (hw->fc.current_mode == ixgbe_fc_rx_pause)) {
 678                 switch (hw->mac.type) {
 679                 case ixgbe_mac_82598EB:
 680                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXC);
 681                         break;
 682                 default:
 683                         data = IXGBE_READ_REG(hw, IXGBE_LXOFFRXCNT);
 684                 }
 685                 hwstats->lxoffrxc += data;
 686
 687                 /* refill credits (no tx hang) if we received xoff */
 688                 if (!data)
 689                         return;
 690
 691                 for (i = 0; i < adapter->num_tx_queues; i++)
 692                         clear_bit(__IXGBE_HANG_CHECK_ARMED,
 693                                   &adapter->tx_ring[i]->state);
 694                 return;
 695         } else if (!(adapter->dcb_cfg.pfc_mode_enable))
 696                 return;
 697
 698         /* update stats for each tc, only valid with PFC enabled */
 699         for (i = 0; i < MAX_TX_PACKET_BUFFERS; i++) {
 700                 switch (hw->mac.type) {
 701                 case ixgbe_mac_82598EB:
 702                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXC(i));
 703                         break;
 704                 default:
 705                         xoff[i] = IXGBE_READ_REG(hw, IXGBE_PXOFFRXCNT(i));
 706                 }
 707                 hwstats->pxoffrxc[i] += xoff[i];
 708         }
 709
 710         /* disarm tx queues that have received xoff frames */
 711         for (i = 0; i < adapter->num_tx_queues; i++) {
 712                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
 713                 u8 tc = tx_ring->dcb_tc;
 714
 715                 if (xoff[tc])
 716                         clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 717         }
 718 }
 719
 720 static u64 ixgbe_get_tx_completed(struct ixgbe_ring *ring)
 721 {
 722         return ring->tx_stats.completed;
 723 }
 724
 725 static u64 ixgbe_get_tx_pending(struct ixgbe_ring *ring)
 726 {
 727         struct ixgbe_adapter *adapter = netdev_priv(ring->netdev);
 728         struct ixgbe_hw *hw = &adapter->hw;
 729
 730         u32 head = IXGBE_READ_REG(hw, IXGBE_TDH(ring->reg_idx));
 731         u32 tail = IXGBE_READ_REG(hw, IXGBE_TDT(ring->reg_idx));
 732
 733         if (head != tail)
 734                 return (head < tail) ?
 735                         tail - head : (tail + ring->count - head);
 736
 737         return 0;
 738 }
 739
 740 static inline bool ixgbe_check_tx_hang(struct ixgbe_ring *tx_ring)
 741 {
 742         u32 tx_done = ixgbe_get_tx_completed(tx_ring);
 743         u32 tx_done_old = tx_ring->tx_stats.tx_done_old;
 744         u32 tx_pending = ixgbe_get_tx_pending(tx_ring);
 745         bool ret = false;
 746
 747         clear_check_for_tx_hang(tx_ring);
 748
 749         /*
 750          * Check for a hung queue, but be thorough. This verifies
 751          * that a transmit has been completed since the previous
 752          * check AND there is at least one packet pending. The
 753          * ARMED bit is set to indicate a potential hang. The
 754          * bit is cleared if a pause frame is received to remove
 755          * false hang detection due to PFC or 802.3x frames. By
 756          * requiring this to fail twice we avoid races with
 757          * pfc clearing the ARMED bit and conditions where we
 758          * run the check_tx_hang logic with a transmit completion
 759          * pending but without time to complete it yet.
 760          */
 761         if ((tx_done_old == tx_done) && tx_pending) {
 762                 /* make sure it is true for two checks in a row */
 763                 ret = test_and_set_bit(__IXGBE_HANG_CHECK_ARMED,
 764                                        &tx_ring->state);
 765         } else {
 766                 /* update completed stats and continue */
 767                 tx_ring->tx_stats.tx_done_old = tx_done;
 768                 /* reset the countdown */
 769                 clear_bit(__IXGBE_HANG_CHECK_ARMED, &tx_ring->state);
 770         }
 771
 772         return ret;
 773 }
 774
 775 #define IXGBE_MAX_TXD_PWR       14
 776 #define IXGBE_MAX_DATA_PER_TXD  (1 << IXGBE_MAX_TXD_PWR)
 777
 778 /* Tx Descriptors needed, worst case */
 779 #define TXD_USE_COUNT(S) (((S) >> IXGBE_MAX_TXD_PWR) + \
 780                          (((S) & (IXGBE_MAX_DATA_PER_TXD - 1)) ? 1 : 0))
 781 #define DESC_NEEDED (TXD_USE_COUNT(IXGBE_MAX_DATA_PER_TXD) /* skb->data */ + \
 782         MAX_SKB_FRAGS * TXD_USE_COUNT(PAGE_SIZE) + 1) /* for context */
 783
 784 /**
 785  * ixgbe_tx_timeout_reset - initiate reset due to Tx timeout
 786  * @adapter: driver private struct
 787  **/
 788 static void ixgbe_tx_timeout_reset(struct ixgbe_adapter *adapter)
 789 {
 790
 791         /* Do the reset outside of interrupt context */
 792         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
 793                 adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
 794                 ixgbe_service_event_schedule(adapter);
 795         }
 796 }
 797
 798 /**
 799  * ixgbe_clean_tx_irq - Reclaim resources after transmit completes
 800  * @q_vector: structure containing interrupt and ring information
 801  * @tx_ring: tx ring to clean
 802  **/
 803 static bool ixgbe_clean_tx_irq(struct ixgbe_q_vector *q_vector,
 804                                struct ixgbe_ring *tx_ring)
 805 {
 806         struct ixgbe_adapter *adapter = q_vector->adapter;
 807         union ixgbe_adv_tx_desc *tx_desc, *eop_desc;
 808         struct ixgbe_tx_buffer *tx_buffer_info;
 809         unsigned int total_bytes = 0, total_packets = 0;
 810         u16 i, eop, count = 0;
 811
 812         i = tx_ring->next_to_clean;
 813         eop = tx_ring->tx_buffer_info[i].next_to_watch;
 814         eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 815
 816         while ((eop_desc->wb.status & cpu_to_le32(IXGBE_TXD_STAT_DD)) &&
 817                (count < tx_ring->work_limit)) {
 818                 bool cleaned = false;
 819                 rmb(); /* read buffer_info after eop_desc */
 820                 for ( ; !cleaned; count++) {
 821                         tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
 822                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
 823
 824                         tx_desc->wb.status = 0;
 825                         cleaned = (i == eop);
 826
 827                         i++;
 828                         if (i == tx_ring->count)
 829                                 i = 0;
 830
 831                         if (cleaned && tx_buffer_info->skb) {
 832                                 total_bytes += tx_buffer_info->bytecount;
 833                                 total_packets += tx_buffer_info->gso_segs;
 834                         }
 835
 836                         ixgbe_unmap_and_free_tx_resource(tx_ring,
 837                                                          tx_buffer_info);
 838                 }
 839
 840                 tx_ring->tx_stats.completed++;
 841                 eop = tx_ring->tx_buffer_info[i].next_to_watch;
 842                 eop_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 843         }
 844
 845         tx_ring->next_to_clean = i;
 846         tx_ring->total_bytes += total_bytes;
 847         tx_ring->total_packets += total_packets;
 848         u64_stats_update_begin(&tx_ring->syncp);
 849         tx_ring->stats.packets += total_packets;
 850         tx_ring->stats.bytes += total_bytes;
 851         u64_stats_update_end(&tx_ring->syncp);
 852
 853         if (check_for_tx_hang(tx_ring) && ixgbe_check_tx_hang(tx_ring)) {
 854                 /* schedule immediate reset if we believe we hung */
 855                 struct ixgbe_hw *hw = &adapter->hw;
 856                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, eop);
 857                 e_err(drv, "Detected Tx Unit Hang\n"
 858                         "  Tx Queue             <%d>\n"
 859                         "  TDH, TDT             <%x>, <%x>\n"
 860                         "  next_to_use          <%x>\n"
 861                         "  next_to_clean        <%x>\n"
 862                         "tx_buffer_info[next_to_clean]\n"
 863                         "  time_stamp           <%lx>\n"
 864                         "  jiffies              <%lx>\n",
 865                         tx_ring->queue_index,
 866                         IXGBE_READ_REG(hw, IXGBE_TDH(tx_ring->reg_idx)),
 867                         IXGBE_READ_REG(hw, IXGBE_TDT(tx_ring->reg_idx)),
 868                         tx_ring->next_to_use, eop,
 869                         tx_ring->tx_buffer_info[eop].time_stamp, jiffies);
 870
 871                 netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
 872
 873                 e_info(probe,
 874                        "tx hang %d detected on queue %d, resetting adapter\n",
 875                         adapter->tx_timeout_count + 1, tx_ring->queue_index);
 876
 877                 /* schedule immediate reset if we believe we hung */
 878                 ixgbe_tx_timeout_reset(adapter);
 879
 880                 /* the adapter is about to reset, no point in enabling stuff */
 881                 return true;
 882         }
 883
 884 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
 885         if (unlikely(count && netif_carrier_ok(tx_ring->netdev) &&
 886                      (IXGBE_DESC_UNUSED(tx_ring) >= TX_WAKE_THRESHOLD))) {
 887                 /* Make sure that anybody stopping the queue after this
 888                  * sees the new next_to_clean.
 889                  */
 890                 smp_mb();
 891                 if (__netif_subqueue_stopped(tx_ring->netdev, tx_ring->queue_index) &&
 892                     !test_bit(__IXGBE_DOWN, &adapter->state)) {
 893                         netif_wake_subqueue(tx_ring->netdev, tx_ring->queue_index);
 894                         ++tx_ring->tx_stats.restart_queue;
 895                 }
 896         }
 897
 898         return count < tx_ring->work_limit;
 899 }
 900
 901 #ifdef CONFIG_IXGBE_DCA
 902 static void ixgbe_update_rx_dca(struct ixgbe_adapter *adapter,
 903                                 struct ixgbe_ring *rx_ring,
 904                                 int cpu)
 905 {
 906         struct ixgbe_hw *hw = &adapter->hw;
 907         u32 rxctrl;
 908         u8 reg_idx = rx_ring->reg_idx;
 909
 910         rxctrl = IXGBE_READ_REG(hw, IXGBE_DCA_RXCTRL(reg_idx));
 911         switch (hw->mac.type) {
 912         case ixgbe_mac_82598EB:
 913                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK;
 914                 rxctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 915                 break;
 916         case ixgbe_mac_82599EB:
 917         case ixgbe_mac_X540:
 918                 rxctrl &= ~IXGBE_DCA_RXCTRL_CPUID_MASK_82599;
 919                 rxctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 920                            IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599);
 921                 break;
 922         default:
 923                 break;
 924         }
 925         rxctrl |= IXGBE_DCA_RXCTRL_DESC_DCA_EN;
 926         rxctrl |= IXGBE_DCA_RXCTRL_HEAD_DCA_EN;
 927         rxctrl &= ~(IXGBE_DCA_RXCTRL_DESC_RRO_EN);
 928         IXGBE_WRITE_REG(hw, IXGBE_DCA_RXCTRL(reg_idx), rxctrl);
 929 }
 930
 931 static void ixgbe_update_tx_dca(struct ixgbe_adapter *adapter,
 932                                 struct ixgbe_ring *tx_ring,
 933                                 int cpu)
 934 {
 935         struct ixgbe_hw *hw = &adapter->hw;
 936         u32 txctrl;
 937         u8 reg_idx = tx_ring->reg_idx;
 938
 939         switch (hw->mac.type) {
 940         case ixgbe_mac_82598EB:
 941                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL(reg_idx));
 942                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK;
 943                 txctrl |= dca3_get_tag(&adapter->pdev->dev, cpu);
 944                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 945                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL(reg_idx), txctrl);
 946                 break;
 947         case ixgbe_mac_82599EB:
 948         case ixgbe_mac_X540:
 949                 txctrl = IXGBE_READ_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx));
 950                 txctrl &= ~IXGBE_DCA_TXCTRL_CPUID_MASK_82599;
 951                 txctrl |= (dca3_get_tag(&adapter->pdev->dev, cpu) <<
 952                            IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599);
 953                 txctrl |= IXGBE_DCA_TXCTRL_DESC_DCA_EN;
 954                 IXGBE_WRITE_REG(hw, IXGBE_DCA_TXCTRL_82599(reg_idx), txctrl);
 955                 break;
 956         default:
 957                 break;
 958         }
 959 }
 960
 961 static void ixgbe_update_dca(struct ixgbe_q_vector *q_vector)
 962 {
 963         struct ixgbe_adapter *adapter = q_vector->adapter;
 964         int cpu = get_cpu();
 965         long r_idx;
 966         int i;
 967
 968         if (q_vector->cpu == cpu)
 969                 goto out_no_update;
 970
 971         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
 972         for (i = 0; i < q_vector->txr_count; i++) {
 973                 ixgbe_update_tx_dca(adapter, adapter->tx_ring[r_idx], cpu);
 974                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
 975                                       r_idx + 1);
 976         }
 977
 978         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
 979         for (i = 0; i < q_vector->rxr_count; i++) {
 980                 ixgbe_update_rx_dca(adapter, adapter->rx_ring[r_idx], cpu);
 981                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
 982                                       r_idx + 1);
 983         }
 984
 985         q_vector->cpu = cpu;
 986 out_no_update:
 987         put_cpu();
 988 }
 989
 990 static void ixgbe_setup_dca(struct ixgbe_adapter *adapter)
 991 {
 992         int num_q_vectors;
 993         int i;
 994
 995         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
 996                 return;
 997
 998         /* always use CB2 mode, difference is masked in the CB driver */
 999         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 2);
1000
1001         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
1002                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1003         else
1004                 num_q_vectors = 1;
1005
1006         for (i = 0; i < num_q_vectors; i++) {
1007                 adapter->q_vector[i]->cpu = -1;
1008                 ixgbe_update_dca(adapter->q_vector[i]);
1009         }
1010 }
1011
1012 static int __ixgbe_notify_dca(struct device *dev, void *data)
1013 {
1014         struct ixgbe_adapter *adapter = dev_get_drvdata(dev);
1015         unsigned long event = *(unsigned long *)data;
1016
1017         if (!(adapter->flags & IXGBE_FLAG_DCA_ENABLED))
1018                 return 0;
1019
1020         switch (event) {
1021         case DCA_PROVIDER_ADD:
1022                 /* if we're already enabled, don't do it again */
1023                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
1024                         break;
1025                 if (dca_add_requester(dev) == 0) {
1026                         adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
1027                         ixgbe_setup_dca(adapter);
1028                         break;
1029                 }
1030                 /* Fall Through since DCA is disabled. */
1031         case DCA_PROVIDER_REMOVE:
1032                 if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
1033                         dca_remove_requester(dev);
1034                         adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
1035                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
1036                 }
1037                 break;
1038         }
1039
1040         return 0;
1041 }
1042 #endif /* CONFIG_IXGBE_DCA */
1043
1044 static inline void ixgbe_rx_hash(union ixgbe_adv_rx_desc *rx_desc,
1045                                  struct sk_buff *skb)
1046 {
1047         skb->rxhash = le32_to_cpu(rx_desc->wb.lower.hi_dword.rss);
1048 }
1049
1050 /**
1051  * ixgbe_receive_skb - Send a completed packet up the stack
1052  * @adapter: board private structure
1053  * @skb: packet to send up
1054  * @status: hardware indication of status of receive
1055  * @rx_ring: rx descriptor ring (for a specific queue) to setup
1056  * @rx_desc: rx descriptor
1057  **/
1058 static void ixgbe_receive_skb(struct ixgbe_q_vector *q_vector,
1059                               struct sk_buff *skb, u8 status,
1060                               struct ixgbe_ring *ring,
1061                               union ixgbe_adv_rx_desc *rx_desc)
1062 {
1063         struct ixgbe_adapter *adapter = q_vector->adapter;
1064         struct napi_struct *napi = &q_vector->napi;
1065         bool is_vlan = (status & IXGBE_RXD_STAT_VP);
1066         u16 tag = le16_to_cpu(rx_desc->wb.upper.vlan);
1067
1068         if (is_vlan && (tag & VLAN_VID_MASK))
1069                 __vlan_hwaccel_put_tag(skb, tag);
1070
1071         if (!(adapter->flags & IXGBE_FLAG_IN_NETPOLL))
1072                 napi_gro_receive(napi, skb);
1073         else
1074                 netif_rx(skb);
1075 }
1076
1077 /**
1078  * ixgbe_rx_checksum - indicate in skb if hw indicated a good cksum
1079  * @adapter: address of board private structure
1080  * @status_err: hardware indication of status of receive
1081  * @skb: skb currently being received and modified
1082  **/
1083 static inline void ixgbe_rx_checksum(struct ixgbe_adapter *adapter,
1084                                      union ixgbe_adv_rx_desc *rx_desc,
1085                                      struct sk_buff *skb)
1086 {
1087         u32 status_err = le32_to_cpu(rx_desc->wb.upper.status_error);
1088
1089         skb_checksum_none_assert(skb);
1090
1091         /* Rx csum disabled */
1092         if (!(adapter->flags & IXGBE_FLAG_RX_CSUM_ENABLED))
1093                 return;
1094
1095         /* if IP and error */
1096         if ((status_err & IXGBE_RXD_STAT_IPCS) &&
1097             (status_err & IXGBE_RXDADV_ERR_IPE)) {
1098                 adapter->hw_csum_rx_error++;
1099                 return;
1100         }
1101
1102         if (!(status_err & IXGBE_RXD_STAT_L4CS))
1103                 return;
1104
1105         if (status_err & IXGBE_RXDADV_ERR_TCPE) {
1106                 u16 pkt_info = rx_desc->wb.lower.lo_dword.hs_rss.pkt_info;
1107
1108                 /*
1109                  * 82599 errata, UDP frames with a 0 checksum can be marked as
1110                  * checksum errors.
1111                  */
1112                 if ((pkt_info & IXGBE_RXDADV_PKTTYPE_UDP) &&
1113                     (adapter->hw.mac.type == ixgbe_mac_82599EB))
1114                         return;
1115
1116                 adapter->hw_csum_rx_error++;
1117                 return;
1118         }
1119
1120         /* It must be a TCP or UDP packet with a valid checksum */
1121         skb->ip_summed = CHECKSUM_UNNECESSARY;
1122 }
1123
1124 static inline void ixgbe_release_rx_desc(struct ixgbe_ring *rx_ring, u32 val)
1125 {
1126         /*
1127          * Force memory writes to complete before letting h/w
1128          * know there are new descriptors to fetch.  (Only
1129          * applicable for weak-ordered memory model archs,
1130          * such as IA-64).
1131          */
1132         wmb();
1133         writel(val, rx_ring->tail);
1134 }
1135
1136 /**
1137  * ixgbe_alloc_rx_buffers - Replace used receive buffers; packet split
1138  * @rx_ring: ring to place buffers on
1139  * @cleaned_count: number of buffers to replace
1140  **/
1141 void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
1142 {
1143         union ixgbe_adv_rx_desc *rx_desc;
1144         struct ixgbe_rx_buffer *bi;
1145         struct sk_buff *skb;
1146         u16 i = rx_ring->next_to_use;
1147
1148         /* do nothing if no valid netdev defined */
1149         if (!rx_ring->netdev)
1150                 return;
1151
1152         while (cleaned_count--) {
1153                 rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1154                 bi = &rx_ring->rx_buffer_info[i];
1155                 skb = bi->skb;
1156
1157                 if (!skb) {
1158                         skb = netdev_alloc_skb_ip_align(rx_ring->netdev,
1159                                                         rx_ring->rx_buf_len);
1160                         if (!skb) {
1161                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1162                                 goto no_buffers;
1163                         }
1164                         /* initialize queue mapping */
1165                         skb_record_rx_queue(skb, rx_ring->queue_index);
1166                         bi->skb = skb;
1167                 }
1168
1169                 if (!bi->dma) {
1170                         bi->dma = dma_map_single(rx_ring->dev,
1171                                                  skb->data,
1172                                                  rx_ring->rx_buf_len,
1173                                                  DMA_FROM_DEVICE);
1174                         if (dma_mapping_error(rx_ring->dev, bi->dma)) {
1175                                 rx_ring->rx_stats.alloc_rx_buff_failed++;
1176                                 bi->dma = 0;
1177                                 goto no_buffers;
1178                         }
1179                 }
1180
1181                 if (ring_is_ps_enabled(rx_ring)) {
1182                         if (!bi->page) {
1183                                 bi->page = netdev_alloc_page(rx_ring->netdev);
1184                                 if (!bi->page) {
1185                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1186                                         goto no_buffers;
1187                                 }
1188                         }
1189
1190                         if (!bi->page_dma) {
1191                                 /* use a half page if we're re-using */
1192                                 bi->page_offset ^= PAGE_SIZE / 2;
1193                                 bi->page_dma = dma_map_page(rx_ring->dev,
1194                                                             bi->page,
1195                                                             bi->page_offset,
1196                                                             PAGE_SIZE / 2,
1197                                                             DMA_FROM_DEVICE);
1198                                 if (dma_mapping_error(rx_ring->dev,
1199                                                       bi->page_dma)) {
1200                                         rx_ring->rx_stats.alloc_rx_page_failed++;
1201                                         bi->page_dma = 0;
1202                                         goto no_buffers;
1203                                 }
1204                         }
1205
1206                         /* Refresh the desc even if buffer_addrs didn't change
1207                          * because each write-back erases this info. */
1208                         rx_desc->read.pkt_addr = cpu_to_le64(bi->page_dma);
1209                         rx_desc->read.hdr_addr = cpu_to_le64(bi->dma);
1210                 } else {
1211                         rx_desc->read.pkt_addr = cpu_to_le64(bi->dma);
1212                         rx_desc->read.hdr_addr = 0;
1213                 }
1214
1215                 i++;
1216                 if (i == rx_ring->count)
1217                         i = 0;
1218         }
1219
1220 no_buffers:
1221         if (rx_ring->next_to_use != i) {
1222                 rx_ring->next_to_use = i;
1223                 ixgbe_release_rx_desc(rx_ring, i);
1224         }
1225 }
1226
1227 static inline u16 ixgbe_get_hlen(union ixgbe_adv_rx_desc *rx_desc)
1228 {
1229         /* HW will not DMA in data larger than the given buffer, even if it
1230          * parses the (NFS, of course) header to be larger.  In that case, it
1231          * fills the header buffer and spills the rest into the page.
1232          */
1233         u16 hdr_info = le16_to_cpu(rx_desc->wb.lower.lo_dword.hs_rss.hdr_info);
1234         u16 hlen = (hdr_info &  IXGBE_RXDADV_HDRBUFLEN_MASK) >>
1235                     IXGBE_RXDADV_HDRBUFLEN_SHIFT;
1236         if (hlen > IXGBE_RX_HDR_SIZE)
1237                 hlen = IXGBE_RX_HDR_SIZE;
1238         return hlen;
1239 }
1240
1241 /**
1242  * ixgbe_transform_rsc_queue - change rsc queue into a full packet
1243  * @skb: pointer to the last skb in the rsc queue
1244  *
1245  * This function changes a queue full of hw rsc buffers into a completed
1246  * packet.  It uses the ->prev pointers to find the first packet and then
1247  * turns it into the frag list owner.
1248  **/
1249 static inline struct sk_buff *ixgbe_transform_rsc_queue(struct sk_buff *skb)
1250 {
1251         unsigned int frag_list_size = 0;
1252         unsigned int skb_cnt = 1;
1253
1254         while (skb->prev) {
1255                 struct sk_buff *prev = skb->prev;
1256                 frag_list_size += skb->len;
1257                 skb->prev = NULL;
1258                 skb = prev;
1259                 skb_cnt++;
1260         }
1261
1262         skb_shinfo(skb)->frag_list = skb->next;
1263         skb->next = NULL;
1264         skb->len += frag_list_size;
1265         skb->data_len += frag_list_size;
1266         skb->truesize += frag_list_size;
1267         IXGBE_RSC_CB(skb)->skb_cnt = skb_cnt;
1268
1269         return skb;
1270 }
1271
1272 static inline bool ixgbe_get_rsc_state(union ixgbe_adv_rx_desc *rx_desc)
1273 {
1274         return !!(le32_to_cpu(rx_desc->wb.lower.lo_dword.data) &
1275                 IXGBE_RXDADV_RSCCNT_MASK);
1276 }
1277
1278 static void ixgbe_clean_rx_irq(struct ixgbe_q_vector *q_vector,
1279                                struct ixgbe_ring *rx_ring,
1280                                int *work_done, int work_to_do)
1281 {
1282         struct ixgbe_adapter *adapter = q_vector->adapter;
1283         union ixgbe_adv_rx_desc *rx_desc, *next_rxd;
1284         struct ixgbe_rx_buffer *rx_buffer_info, *next_buffer;
1285         struct sk_buff *skb;
1286         unsigned int total_rx_bytes = 0, total_rx_packets = 0;
1287         const int current_node = numa_node_id();
1288 #ifdef IXGBE_FCOE
1289         int ddp_bytes = 0;
1290 #endif /* IXGBE_FCOE */
1291         u32 staterr;
1292         u16 i;
1293         u16 cleaned_count = 0;
1294         bool pkt_is_rsc = false;
1295
1296         i = rx_ring->next_to_clean;
1297         rx_desc = IXGBE_RX_DESC_ADV(rx_ring, i);
1298         staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1299
1300         while (staterr & IXGBE_RXD_STAT_DD) {
1301                 u32 upper_len = 0;
1302
1303                 rmb(); /* read descriptor and rx_buffer_info after status DD */
1304
1305                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
1306
1307                 skb = rx_buffer_info->skb;
1308                 rx_buffer_info->skb = NULL;
1309                 prefetch(skb->data);
1310
1311                 if (ring_is_rsc_enabled(rx_ring))
1312                         pkt_is_rsc = ixgbe_get_rsc_state(rx_desc);
1313
1314                 /* if this is a skb from previous receive DMA will be 0 */
1315                 if (rx_buffer_info->dma) {
1316                         u16 hlen;
1317                         if (pkt_is_rsc &&
1318                             !(staterr & IXGBE_RXD_STAT_EOP) &&
1319                             !skb->prev) {
1320                                 /*
1321                                  * When HWRSC is enabled, delay unmapping
1322                                  * of the first packet. It carries the
1323                                  * header information, HW may still
1324                                  * access the header after the writeback.
1325                                  * Only unmap it when EOP is reached
1326                                  */
1327                                 IXGBE_RSC_CB(skb)->delay_unmap = true;
1328                                 IXGBE_RSC_CB(skb)->dma = rx_buffer_info->dma;
1329                         } else {
1330                                 dma_unmap_single(rx_ring->dev,
1331                                                  rx_buffer_info->dma,
1332                                                  rx_ring->rx_buf_len,
1333                                                  DMA_FROM_DEVICE);
1334                         }
1335                         rx_buffer_info->dma = 0;
1336
1337                         if (ring_is_ps_enabled(rx_ring)) {
1338                                 hlen = ixgbe_get_hlen(rx_desc);
1339                                 upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1340                         } else {
1341                                 hlen = le16_to_cpu(rx_desc->wb.upper.length);
1342                         }
1343
1344                         skb_put(skb, hlen);
1345                 } else {
1346                         /* assume packet split since header is unmapped */
1347                         upper_len = le16_to_cpu(rx_desc->wb.upper.length);
1348                 }
1349
1350                 if (upper_len) {
1351                         dma_unmap_page(rx_ring->dev,
1352                                        rx_buffer_info->page_dma,
1353                                        PAGE_SIZE / 2,
1354                                        DMA_FROM_DEVICE);
1355                         rx_buffer_info->page_dma = 0;
1356                         skb_fill_page_desc(skb, skb_shinfo(skb)->nr_frags,
1357                                            rx_buffer_info->page,
1358                                            rx_buffer_info->page_offset,
1359                                            upper_len);
1360
1361                         if ((page_count(rx_buffer_info->page) == 1) &&
1362                             (page_to_nid(rx_buffer_info->page) == current_node))
1363                                 get_page(rx_buffer_info->page);
1364                         else
1365                                 rx_buffer_info->page = NULL;
1366
1367                         skb->len += upper_len;
1368                         skb->data_len += upper_len;
1369                         skb->truesize += upper_len;
1370                 }
1371
1372                 i++;
1373                 if (i == rx_ring->count)
1374                         i = 0;
1375
1376                 next_rxd = IXGBE_RX_DESC_ADV(rx_ring, i);
1377                 prefetch(next_rxd);
1378                 cleaned_count++;
1379
1380                 if (pkt_is_rsc) {
1381                         u32 nextp = (staterr & IXGBE_RXDADV_NEXTP_MASK) >>
1382                                      IXGBE_RXDADV_NEXTP_SHIFT;
1383                         next_buffer = &rx_ring->rx_buffer_info[nextp];
1384                 } else {
1385                         next_buffer = &rx_ring->rx_buffer_info[i];
1386                 }
1387
1388                 if (!(staterr & IXGBE_RXD_STAT_EOP)) {
1389                         if (ring_is_ps_enabled(rx_ring)) {
1390                                 rx_buffer_info->skb = next_buffer->skb;
1391                                 rx_buffer_info->dma = next_buffer->dma;
1392                                 next_buffer->skb = skb;
1393                                 next_buffer->dma = 0;
1394                         } else {
1395                                 skb->next = next_buffer->skb;
1396                                 skb->next->prev = skb;
1397                         }
1398                         rx_ring->rx_stats.non_eop_descs++;
1399                         goto next_desc;
1400                 }
1401
1402                 if (skb->prev) {
1403                         skb = ixgbe_transform_rsc_queue(skb);
1404                         /* if we got here without RSC the packet is invalid */
1405                         if (!pkt_is_rsc) {
1406                                 __pskb_trim(skb, 0);
1407                                 rx_buffer_info->skb = skb;
1408                                 goto next_desc;
1409                         }
1410                 }
1411
1412                 if (ring_is_rsc_enabled(rx_ring)) {
1413                         if (IXGBE_RSC_CB(skb)->delay_unmap) {
1414                                 dma_unmap_single(rx_ring->dev,
1415                                                  IXGBE_RSC_CB(skb)->dma,
1416                                                  rx_ring->rx_buf_len,
1417                                                  DMA_FROM_DEVICE);
1418                                 IXGBE_RSC_CB(skb)->dma = 0;
1419                                 IXGBE_RSC_CB(skb)->delay_unmap = false;
1420                         }
1421                 }
1422                 if (pkt_is_rsc) {
1423                         if (ring_is_ps_enabled(rx_ring))
1424                                 rx_ring->rx_stats.rsc_count +=
1425                                         skb_shinfo(skb)->nr_frags;
1426                         else
1427                                 rx_ring->rx_stats.rsc_count +=
1428                                         IXGBE_RSC_CB(skb)->skb_cnt;
1429                         rx_ring->rx_stats.rsc_flush++;
1430                 }
1431
1432                 /* ERR_MASK will only have valid bits if EOP set */
1433                 if (staterr & IXGBE_RXDADV_ERR_FRAME_ERR_MASK) {
1434                         /* trim packet back to size 0 and recycle it */
1435                         __pskb_trim(skb, 0);
1436                         rx_buffer_info->skb = skb;
1437                         goto next_desc;
1438                 }
1439
1440                 ixgbe_rx_checksum(adapter, rx_desc, skb);
1441                 if (adapter->netdev->features & NETIF_F_RXHASH)
1442                         ixgbe_rx_hash(rx_desc, skb);
1443
1444                 /* probably a little skewed due to removing CRC */
1445                 total_rx_bytes += skb->len;
1446                 total_rx_packets++;
1447
1448                 skb->protocol = eth_type_trans(skb, rx_ring->netdev);
1449 #ifdef IXGBE_FCOE
1450                 /* if ddp, not passing to ULD unless for FCP_RSP or error */
1451                 if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
1452                         ddp_bytes = ixgbe_fcoe_ddp(adapter, rx_desc, skb);
1453                         if (!ddp_bytes)
1454                                 goto next_desc;
1455                 }
1456 #endif /* IXGBE_FCOE */
1457                 ixgbe_receive_skb(q_vector, skb, staterr, rx_ring, rx_desc);
1458
1459 next_desc:
1460                 rx_desc->wb.upper.status_error = 0;
1461
1462                 (*work_done)++;
1463                 if (*work_done >= work_to_do)
1464                         break;
1465
1466                 /* return some buffers to hardware, one at a time is too slow */
1467                 if (cleaned_count >= IXGBE_RX_BUFFER_WRITE) {
1468                         ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1469                         cleaned_count = 0;
1470                 }
1471
1472                 /* use prefetched values */
1473                 rx_desc = next_rxd;
1474                 staterr = le32_to_cpu(rx_desc->wb.upper.status_error);
1475         }
1476
1477         rx_ring->next_to_clean = i;
1478         cleaned_count = IXGBE_DESC_UNUSED(rx_ring);
1479
1480         if (cleaned_count)
1481                 ixgbe_alloc_rx_buffers(rx_ring, cleaned_count);
1482
1483 #ifdef IXGBE_FCOE
1484         /* include DDPed FCoE data */
1485         if (ddp_bytes > 0) {
1486                 unsigned int mss;
1487
1488                 mss = rx_ring->netdev->mtu - sizeof(struct fcoe_hdr) -
1489                         sizeof(struct fc_frame_header) -
1490                         sizeof(struct fcoe_crc_eof);
1491                 if (mss > 512)
1492                         mss &= ~511;
1493                 total_rx_bytes += ddp_bytes;
1494                 total_rx_packets += DIV_ROUND_UP(ddp_bytes, mss);
1495         }
1496 #endif /* IXGBE_FCOE */
1497
1498         rx_ring->total_packets += total_rx_packets;
1499         rx_ring->total_bytes += total_rx_bytes;
1500         u64_stats_update_begin(&rx_ring->syncp);
1501         rx_ring->stats.packets += total_rx_packets;
1502         rx_ring->stats.bytes += total_rx_bytes;
1503         u64_stats_update_end(&rx_ring->syncp);
1504 }
1505
1506 static int ixgbe_clean_rxonly(struct napi_struct *, int);
1507 /**
1508  * ixgbe_configure_msix - Configure MSI-X hardware
1509  * @adapter: board private structure
1510  *
1511  * ixgbe_configure_msix sets up the hardware to properly generate MSI-X
1512  * interrupts.
1513  **/
1514 static void ixgbe_configure_msix(struct ixgbe_adapter *adapter)
1515 {
1516         struct ixgbe_q_vector *q_vector;
1517         int i, q_vectors, v_idx, r_idx;
1518         u32 mask;
1519
1520         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
1521
1522         /*
1523          * Populate the IVAR table and set the ITR values to the
1524          * corresponding register.
1525          */
1526         for (v_idx = 0; v_idx < q_vectors; v_idx++) {
1527                 q_vector = adapter->q_vector[v_idx];
1528                 /* XXX for_each_set_bit(...) */
1529                 r_idx = find_first_bit(q_vector->rxr_idx,
1530                                        adapter->num_rx_queues);
1531
1532                 for (i = 0; i < q_vector->rxr_count; i++) {
1533                         u8 reg_idx = adapter->rx_ring[r_idx]->reg_idx;
1534                         ixgbe_set_ivar(adapter, 0, reg_idx, v_idx);
1535                         r_idx = find_next_bit(q_vector->rxr_idx,
1536                                               adapter->num_rx_queues,
1537                                               r_idx + 1);
1538                 }
1539                 r_idx = find_first_bit(q_vector->txr_idx,
1540                                        adapter->num_tx_queues);
1541
1542                 for (i = 0; i < q_vector->txr_count; i++) {
1543                         u8 reg_idx = adapter->tx_ring[r_idx]->reg_idx;
1544                         ixgbe_set_ivar(adapter, 1, reg_idx, v_idx);
1545                         r_idx = find_next_bit(q_vector->txr_idx,
1546                                               adapter->num_tx_queues,
1547                                               r_idx + 1);
1548                 }
1549
1550                 if (q_vector->txr_count && !q_vector->rxr_count)
1551                         /* tx only */
1552                         q_vector->eitr = adapter->tx_eitr_param;
1553                 else if (q_vector->rxr_count)
1554                         /* rx or mixed */
1555                         q_vector->eitr = adapter->rx_eitr_param;
1556
1557                 ixgbe_write_eitr(q_vector);
1558                 /* If ATR is enabled, set interrupt affinity */
1559                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
1560                         /*
1561                          * Allocate the affinity_hint cpumask, assign the mask
1562                          * for this vector, and set our affinity_hint for
1563                          * this irq.
1564                          */
1565                         if (!alloc_cpumask_var(&q_vector->affinity_mask,
1566                                                GFP_KERNEL))
1567                                 return;
1568                         cpumask_set_cpu(v_idx, q_vector->affinity_mask);
1569                         irq_set_affinity_hint(adapter->msix_entries[v_idx].vector,
1570                                               q_vector->affinity_mask);
1571                 }
1572         }
1573
1574         switch (adapter->hw.mac.type) {
1575         case ixgbe_mac_82598EB:
1576                 ixgbe_set_ivar(adapter, -1, IXGBE_IVAR_OTHER_CAUSES_INDEX,
1577                                v_idx);
1578                 break;
1579         case ixgbe_mac_82599EB:
1580         case ixgbe_mac_X540:
1581                 ixgbe_set_ivar(adapter, -1, 1, v_idx);
1582                 break;
1583
1584         default:
1585                 break;
1586         }
1587         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITR(v_idx), 1950);
1588
1589         /* set up to autoclear timer, and the vectors */
1590         mask = IXGBE_EIMS_ENABLE_MASK;
1591         if (adapter->num_vfs)
1592                 mask &= ~(IXGBE_EIMS_OTHER |
1593                           IXGBE_EIMS_MAILBOX |
1594                           IXGBE_EIMS_LSC);
1595         else
1596                 mask &= ~(IXGBE_EIMS_OTHER | IXGBE_EIMS_LSC);
1597         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIAC, mask);
1598 }
1599
1600 enum latency_range {
1601         lowest_latency = 0,
1602         low_latency = 1,
1603         bulk_latency = 2,
1604         latency_invalid = 255
1605 };
1606
1607 /**
1608  * ixgbe_update_itr - update the dynamic ITR value based on statistics
1609  * @adapter: pointer to adapter
1610  * @eitr: eitr setting (ints per sec) to give last timeslice
1611  * @itr_setting: current throttle rate in ints/second
1612  * @packets: the number of packets during this measurement interval
1613  * @bytes: the number of bytes during this measurement interval
1614  *
1615  *      Stores a new ITR value based on packets and byte
1616  *      counts during the last interrupt.  The advantage of per interrupt
1617  *      computation is faster updates and more accurate ITR for the current
1618  *      traffic pattern.  Constants in this function were computed
1619  *      based on theoretical maximum wire speed and thresholds were set based
1620  *      on testing data as well as attempting to minimize response time
1621  *      while increasing bulk throughput.
1622  *      this functionality is controlled by the InterruptThrottleRate module
1623  *      parameter (see ixgbe_param.c)
1624  **/
1625 static u8 ixgbe_update_itr(struct ixgbe_adapter *adapter,
1626                            u32 eitr, u8 itr_setting,
1627                            int packets, int bytes)
1628 {
1629         unsigned int retval = itr_setting;
1630         u32 timepassed_us;
1631         u64 bytes_perint;
1632
1633         if (packets == 0)
1634                 goto update_itr_done;
1635
1636
1637         /* simple throttlerate management
1638          *    0-20MB/s lowest (100000 ints/s)
1639          *   20-100MB/s low   (20000 ints/s)
1640          *  100-1249MB/s bulk (8000 ints/s)
1641          */
1642         /* what was last interrupt timeslice? */
1643         timepassed_us = 1000000/eitr;
1644         bytes_perint = bytes / timepassed_us; /* bytes/usec */
1645
1646         switch (itr_setting) {
1647         case lowest_latency:
1648                 if (bytes_perint > adapter->eitr_low)
1649                         retval = low_latency;
1650                 break;
1651         case low_latency:
1652                 if (bytes_perint > adapter->eitr_high)
1653                         retval = bulk_latency;
1654                 else if (bytes_perint <= adapter->eitr_low)
1655                         retval = lowest_latency;
1656                 break;
1657         case bulk_latency:
1658                 if (bytes_perint <= adapter->eitr_high)
1659                         retval = low_latency;
1660                 break;
1661         }
1662
1663 update_itr_done:
1664         return retval;
1665 }
1666
1667 /**
1668  * ixgbe_write_eitr - write EITR register in hardware specific way
1669  * @q_vector: structure containing interrupt and ring information
1670  *
1671  * This function is made to be called by ethtool and by the driver
1672  * when it needs to update EITR registers at runtime.  Hardware
1673  * specific quirks/differences are taken care of here.
1674  */
1675 void ixgbe_write_eitr(struct ixgbe_q_vector *q_vector)
1676 {
1677         struct ixgbe_adapter *adapter = q_vector->adapter;
1678         struct ixgbe_hw *hw = &adapter->hw;
1679         int v_idx = q_vector->v_idx;
1680         u32 itr_reg = EITR_INTS_PER_SEC_TO_REG(q_vector->eitr);
1681
1682         switch (adapter->hw.mac.type) {
1683         case ixgbe_mac_82598EB:
1684                 /* must write high and low 16 bits to reset counter */
1685                 itr_reg |= (itr_reg << 16);
1686                 break;
1687         case ixgbe_mac_82599EB:
1688         case ixgbe_mac_X540:
1689                 /*
1690                  * 82599 and X540 can support a value of zero, so allow it for
1691                  * max interrupt rate, but there is an errata where it can
1692                  * not be zero with RSC
1693                  */
1694                 if (itr_reg == 8 &&
1695                     !(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED))
1696                         itr_reg = 0;
1697
1698                 /*
1699                  * set the WDIS bit to not clear the timer bits and cause an
1700                  * immediate assertion of the interrupt
1701                  */
1702                 itr_reg |= IXGBE_EITR_CNT_WDIS;
1703                 break;
1704         default:
1705                 break;
1706         }
1707         IXGBE_WRITE_REG(hw, IXGBE_EITR(v_idx), itr_reg);
1708 }
1709
1710 static void ixgbe_set_itr_msix(struct ixgbe_q_vector *q_vector)
1711 {
1712         struct ixgbe_adapter *adapter = q_vector->adapter;
1713         int i, r_idx;
1714         u32 new_itr;
1715         u8 current_itr, ret_itr;
1716
1717         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
1718         for (i = 0; i < q_vector->txr_count; i++) {
1719                 struct ixgbe_ring *tx_ring = adapter->tx_ring[r_idx];
1720                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1721                                            q_vector->tx_itr,
1722                                            tx_ring->total_packets,
1723                                            tx_ring->total_bytes);
1724                 /* if the result for this queue would decrease interrupt
1725                  * rate for this vector then use that result */
1726                 q_vector->tx_itr = ((q_vector->tx_itr > ret_itr) ?
1727                                     q_vector->tx_itr - 1 : ret_itr);
1728                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
1729                                       r_idx + 1);
1730         }
1731
1732         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
1733         for (i = 0; i < q_vector->rxr_count; i++) {
1734                 struct ixgbe_ring *rx_ring = adapter->rx_ring[r_idx];
1735                 ret_itr = ixgbe_update_itr(adapter, q_vector->eitr,
1736                                            q_vector->rx_itr,
1737                                            rx_ring->total_packets,
1738                                            rx_ring->total_bytes);
1739                 /* if the result for this queue would decrease interrupt
1740                  * rate for this vector then use that result */
1741                 q_vector->rx_itr = ((q_vector->rx_itr > ret_itr) ?
1742                                     q_vector->rx_itr - 1 : ret_itr);
1743                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
1744                                       r_idx + 1);
1745         }
1746
1747         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
1748
1749         switch (current_itr) {
1750         /* counts and packets in update_itr are dependent on these numbers */
1751         case lowest_latency:
1752                 new_itr = 100000;
1753                 break;
1754         case low_latency:
1755                 new_itr = 20000; /* aka hwitr = ~200 */
1756                 break;
1757         case bulk_latency:
1758         default:
1759                 new_itr = 8000;
1760                 break;
1761         }
1762
1763         if (new_itr != q_vector->eitr) {
1764                 /* do an exponential smoothing */
1765                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
1766
1767                 /* save the algorithm value here, not the smoothed one */
1768                 q_vector->eitr = new_itr;
1769
1770                 ixgbe_write_eitr(q_vector);
1771         }
1772 }
1773
1774 /**
1775  * ixgbe_check_overtemp_subtask - check for over tempurature
1776  * @adapter: pointer to adapter
1777  **/
1778 static void ixgbe_check_overtemp_subtask(struct ixgbe_adapter *adapter)
1779 {
1780         struct ixgbe_hw *hw = &adapter->hw;
1781         u32 eicr = adapter->interrupt_event;
1782
1783         if (test_bit(__IXGBE_DOWN, &adapter->state))
1784                 return;
1785
1786         if (!(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1787             !(adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_EVENT))
1788                 return;
1789
1790         adapter->flags2 &= ~IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1791
1792         switch (hw->device_id) {
1793         case IXGBE_DEV_ID_82599_T3_LOM:
1794                 /*
1795                  * Since the warning interrupt is for both ports
1796                  * we don't have to check if:
1797                  *  - This interrupt wasn't for our port.
1798                  *  - We may have missed the interrupt so always have to
1799                  *    check if we  got a LSC
1800                  */
1801                 if (!(eicr & IXGBE_EICR_GPI_SDP0) &&
1802                     !(eicr & IXGBE_EICR_LSC))
1803                         return;
1804
1805                 if (!(eicr & IXGBE_EICR_LSC) && hw->mac.ops.check_link) {
1806                         u32 autoneg;
1807                         bool link_up = false;
1808
1809                         hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
1810
1811                         if (link_up)
1812                                 return;
1813                 }
1814
1815                 /* Check if this is not due to overtemp */
1816                 if (hw->phy.ops.check_overtemp(hw) != IXGBE_ERR_OVERTEMP)
1817                         return;
1818
1819                 break;
1820         default:
1821                 if (!(eicr & IXGBE_EICR_GPI_SDP0))
1822                         return;
1823                 break;
1824         }
1825         e_crit(drv,
1826                "Network adapter has been stopped because it has over heated. "
1827                "Restart the computer. If the problem persists, "
1828                "power off the system and replace the adapter\n");
1829
1830         adapter->interrupt_event = 0;
1831 }
1832
1833 static void ixgbe_check_fan_failure(struct ixgbe_adapter *adapter, u32 eicr)
1834 {
1835         struct ixgbe_hw *hw = &adapter->hw;
1836
1837         if ((adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) &&
1838             (eicr & IXGBE_EICR_GPI_SDP1)) {
1839                 e_crit(probe, "Fan has stopped, replace the adapter\n");
1840                 /* write to clear the interrupt */
1841                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1842         }
1843 }
1844
1845 static void ixgbe_check_sfp_event(struct ixgbe_adapter *adapter, u32 eicr)
1846 {
1847         struct ixgbe_hw *hw = &adapter->hw;
1848
1849         if (eicr & IXGBE_EICR_GPI_SDP2) {
1850                 /* Clear the interrupt */
1851                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP2);
1852                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1853                         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
1854                         ixgbe_service_event_schedule(adapter);
1855                 }
1856         }
1857
1858         if (eicr & IXGBE_EICR_GPI_SDP1) {
1859                 /* Clear the interrupt */
1860                 IXGBE_WRITE_REG(hw, IXGBE_EICR, IXGBE_EICR_GPI_SDP1);
1861                 if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1862                         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
1863                         ixgbe_service_event_schedule(adapter);
1864                 }
1865         }
1866 }
1867
1868 static void ixgbe_check_lsc(struct ixgbe_adapter *adapter)
1869 {
1870         struct ixgbe_hw *hw = &adapter->hw;
1871
1872         adapter->lsc_int++;
1873         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
1874         adapter->link_check_timeout = jiffies;
1875         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1876                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_LSC);
1877                 IXGBE_WRITE_FLUSH(hw);
1878                 ixgbe_service_event_schedule(adapter);
1879         }
1880 }
1881
1882 static irqreturn_t ixgbe_msix_lsc(int irq, void *data)
1883 {
1884         struct net_device *netdev = data;
1885         struct ixgbe_adapter *adapter = netdev_priv(netdev);
1886         struct ixgbe_hw *hw = &adapter->hw;
1887         u32 eicr;
1888
1889         /*
1890          * Workaround for Silicon errata.  Use clear-by-write instead
1891          * of clear-by-read.  Reading with EICS will return the
1892          * interrupt causes without clearing, which later be done
1893          * with the write to EICR.
1894          */
1895         eicr = IXGBE_READ_REG(hw, IXGBE_EICS);
1896         IXGBE_WRITE_REG(hw, IXGBE_EICR, eicr);
1897
1898         if (eicr & IXGBE_EICR_LSC)
1899                 ixgbe_check_lsc(adapter);
1900
1901         if (eicr & IXGBE_EICR_MAILBOX)
1902                 ixgbe_msg_task(adapter);
1903
1904         switch (hw->mac.type) {
1905         case ixgbe_mac_82599EB:
1906         case ixgbe_mac_X540:
1907                 /* Handle Flow Director Full threshold interrupt */
1908                 if (eicr & IXGBE_EICR_FLOW_DIR) {
1909                         int reinit_count = 0;
1910                         int i;
1911                         for (i = 0; i < adapter->num_tx_queues; i++) {
1912                                 struct ixgbe_ring *ring = adapter->tx_ring[i];
1913                                 if (test_and_clear_bit(__IXGBE_TX_FDIR_INIT_DONE,
1914                                                        &ring->state))
1915                                         reinit_count++;
1916                         }
1917                         if (reinit_count) {
1918                                 /* no more flow director interrupts until after init */
1919                                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_EIMC_FLOW_DIR);
1920                                 eicr &= ~IXGBE_EICR_FLOW_DIR;
1921                                 adapter->flags2 |= IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
1922                                 ixgbe_service_event_schedule(adapter);
1923                         }
1924                 }
1925                 ixgbe_check_sfp_event(adapter, eicr);
1926                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
1927                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
1928                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
1929                                 adapter->interrupt_event = eicr;
1930                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
1931                                 ixgbe_service_event_schedule(adapter);
1932                         }
1933                 }
1934                 break;
1935         default:
1936                 break;
1937         }
1938
1939         ixgbe_check_fan_failure(adapter, eicr);
1940
1941         /* re-enable the original interrupt state, no lsc, no queues */
1942         if (!test_bit(__IXGBE_DOWN, &adapter->state))
1943                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, eicr &
1944                                 ~(IXGBE_EIMS_LSC | IXGBE_EIMS_RTX_QUEUE));
1945
1946         return IRQ_HANDLED;
1947 }
1948
1949 static inline void ixgbe_irq_enable_queues(struct ixgbe_adapter *adapter,
1950                                            u64 qmask)
1951 {
1952         u32 mask;
1953         struct ixgbe_hw *hw = &adapter->hw;
1954
1955         switch (hw->mac.type) {
1956         case ixgbe_mac_82598EB:
1957                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1958                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, mask);
1959                 break;
1960         case ixgbe_mac_82599EB:
1961         case ixgbe_mac_X540:
1962                 mask = (qmask & 0xFFFFFFFF);
1963                 if (mask)
1964                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(0), mask);
1965                 mask = (qmask >> 32);
1966                 if (mask)
1967                         IXGBE_WRITE_REG(hw, IXGBE_EIMS_EX(1), mask);
1968                 break;
1969         default:
1970                 break;
1971         }
1972         /* skip the flush */
1973 }
1974
1975 static inline void ixgbe_irq_disable_queues(struct ixgbe_adapter *adapter,
1976                                             u64 qmask)
1977 {
1978         u32 mask;
1979         struct ixgbe_hw *hw = &adapter->hw;
1980
1981         switch (hw->mac.type) {
1982         case ixgbe_mac_82598EB:
1983                 mask = (IXGBE_EIMS_RTX_QUEUE & qmask);
1984                 IXGBE_WRITE_REG(hw, IXGBE_EIMC, mask);
1985                 break;
1986         case ixgbe_mac_82599EB:
1987         case ixgbe_mac_X540:
1988                 mask = (qmask & 0xFFFFFFFF);
1989                 if (mask)
1990                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(0), mask);
1991                 mask = (qmask >> 32);
1992                 if (mask)
1993                         IXGBE_WRITE_REG(hw, IXGBE_EIMC_EX(1), mask);
1994                 break;
1995         default:
1996                 break;
1997         }
1998         /* skip the flush */
1999 }
2000
2001 static irqreturn_t ixgbe_msix_clean_tx(int irq, void *data)
2002 {
2003         struct ixgbe_q_vector *q_vector = data;
2004         struct ixgbe_adapter  *adapter = q_vector->adapter;
2005         struct ixgbe_ring     *tx_ring;
2006         int i, r_idx;
2007
2008         if (!q_vector->txr_count)
2009                 return IRQ_HANDLED;
2010
2011         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2012         for (i = 0; i < q_vector->txr_count; i++) {
2013                 tx_ring = adapter->tx_ring[r_idx];
2014                 tx_ring->total_bytes = 0;
2015                 tx_ring->total_packets = 0;
2016                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2017                                       r_idx + 1);
2018         }
2019
2020         /* EIAM disabled interrupts (on this vector) for us */
2021         napi_schedule(&q_vector->napi);
2022
2023         return IRQ_HANDLED;
2024 }
2025
2026 /**
2027  * ixgbe_msix_clean_rx - single unshared vector rx clean (all queues)
2028  * @irq: unused
2029  * @data: pointer to our q_vector struct for this interrupt vector
2030  **/
2031 static irqreturn_t ixgbe_msix_clean_rx(int irq, void *data)
2032 {
2033         struct ixgbe_q_vector *q_vector = data;
2034         struct ixgbe_adapter  *adapter = q_vector->adapter;
2035         struct ixgbe_ring  *rx_ring;
2036         int r_idx;
2037         int i;
2038
2039 #ifdef CONFIG_IXGBE_DCA
2040         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2041                 ixgbe_update_dca(q_vector);
2042 #endif
2043
2044         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2045         for (i = 0; i < q_vector->rxr_count; i++) {
2046                 rx_ring = adapter->rx_ring[r_idx];
2047                 rx_ring->total_bytes = 0;
2048                 rx_ring->total_packets = 0;
2049                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2050                                       r_idx + 1);
2051         }
2052
2053         if (!q_vector->rxr_count)
2054                 return IRQ_HANDLED;
2055
2056         /* EIAM disabled interrupts (on this vector) for us */
2057         napi_schedule(&q_vector->napi);
2058
2059         return IRQ_HANDLED;
2060 }
2061
2062 static irqreturn_t ixgbe_msix_clean_many(int irq, void *data)
2063 {
2064         struct ixgbe_q_vector *q_vector = data;
2065         struct ixgbe_adapter  *adapter = q_vector->adapter;
2066         struct ixgbe_ring  *ring;
2067         int r_idx;
2068         int i;
2069
2070         if (!q_vector->txr_count && !q_vector->rxr_count)
2071                 return IRQ_HANDLED;
2072
2073         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2074         for (i = 0; i < q_vector->txr_count; i++) {
2075                 ring = adapter->tx_ring[r_idx];
2076                 ring->total_bytes = 0;
2077                 ring->total_packets = 0;
2078                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2079                                       r_idx + 1);
2080         }
2081
2082         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2083         for (i = 0; i < q_vector->rxr_count; i++) {
2084                 ring = adapter->rx_ring[r_idx];
2085                 ring->total_bytes = 0;
2086                 ring->total_packets = 0;
2087                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2088                                       r_idx + 1);
2089         }
2090
2091         /* EIAM disabled interrupts (on this vector) for us */
2092         napi_schedule(&q_vector->napi);
2093
2094         return IRQ_HANDLED;
2095 }
2096
2097 /**
2098  * ixgbe_clean_rxonly - msix (aka one shot) rx clean routine
2099  * @napi: napi struct with our devices info in it
2100  * @budget: amount of work driver is allowed to do this pass, in packets
2101  *
2102  * This function is optimized for cleaning one queue only on a single
2103  * q_vector!!!
2104  **/
2105 static int ixgbe_clean_rxonly(struct napi_struct *napi, int budget)
2106 {
2107         struct ixgbe_q_vector *q_vector =
2108                                container_of(napi, struct ixgbe_q_vector, napi);
2109         struct ixgbe_adapter *adapter = q_vector->adapter;
2110         struct ixgbe_ring *rx_ring = NULL;
2111         int work_done = 0;
2112         long r_idx;
2113
2114 #ifdef CONFIG_IXGBE_DCA
2115         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2116                 ixgbe_update_dca(q_vector);
2117 #endif
2118
2119         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2120         rx_ring = adapter->rx_ring[r_idx];
2121
2122         ixgbe_clean_rx_irq(q_vector, rx_ring, &work_done, budget);
2123
2124         /* If all Rx work done, exit the polling mode */
2125         if (work_done < budget) {
2126                 napi_complete(napi);
2127                 if (adapter->rx_itr_setting & 1)
2128                         ixgbe_set_itr_msix(q_vector);
2129                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2130                         ixgbe_irq_enable_queues(adapter,
2131                                                 ((u64)1 << q_vector->v_idx));
2132         }
2133
2134         return work_done;
2135 }
2136
2137 /**
2138  * ixgbe_clean_rxtx_many - msix (aka one shot) rx clean routine
2139  * @napi: napi struct with our devices info in it
2140  * @budget: amount of work driver is allowed to do this pass, in packets
2141  *
2142  * This function will clean more than one rx queue associated with a
2143  * q_vector.
2144  **/
2145 static int ixgbe_clean_rxtx_many(struct napi_struct *napi, int budget)
2146 {
2147         struct ixgbe_q_vector *q_vector =
2148                                container_of(napi, struct ixgbe_q_vector, napi);
2149         struct ixgbe_adapter *adapter = q_vector->adapter;
2150         struct ixgbe_ring *ring = NULL;
2151         int work_done = 0, i;
2152         long r_idx;
2153         bool tx_clean_complete = true;
2154
2155 #ifdef CONFIG_IXGBE_DCA
2156         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2157                 ixgbe_update_dca(q_vector);
2158 #endif
2159
2160         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2161         for (i = 0; i < q_vector->txr_count; i++) {
2162                 ring = adapter->tx_ring[r_idx];
2163                 tx_clean_complete &= ixgbe_clean_tx_irq(q_vector, ring);
2164                 r_idx = find_next_bit(q_vector->txr_idx, adapter->num_tx_queues,
2165                                       r_idx + 1);
2166         }
2167
2168         /* attempt to distribute budget to each queue fairly, but don't allow
2169          * the budget to go below 1 because we'll exit polling */
2170         budget /= (q_vector->rxr_count ?: 1);
2171         budget = max(budget, 1);
2172         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2173         for (i = 0; i < q_vector->rxr_count; i++) {
2174                 ring = adapter->rx_ring[r_idx];
2175                 ixgbe_clean_rx_irq(q_vector, ring, &work_done, budget);
2176                 r_idx = find_next_bit(q_vector->rxr_idx, adapter->num_rx_queues,
2177                                       r_idx + 1);
2178         }
2179
2180         r_idx = find_first_bit(q_vector->rxr_idx, adapter->num_rx_queues);
2181         ring = adapter->rx_ring[r_idx];
2182         /* If all Rx work done, exit the polling mode */
2183         if (work_done < budget) {
2184                 napi_complete(napi);
2185                 if (adapter->rx_itr_setting & 1)
2186                         ixgbe_set_itr_msix(q_vector);
2187                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2188                         ixgbe_irq_enable_queues(adapter,
2189                                                 ((u64)1 << q_vector->v_idx));
2190                 return 0;
2191         }
2192
2193         return work_done;
2194 }
2195
2196 /**
2197  * ixgbe_clean_txonly - msix (aka one shot) tx clean routine
2198  * @napi: napi struct with our devices info in it
2199  * @budget: amount of work driver is allowed to do this pass, in packets
2200  *
2201  * This function is optimized for cleaning one queue only on a single
2202  * q_vector!!!
2203  **/
2204 static int ixgbe_clean_txonly(struct napi_struct *napi, int budget)
2205 {
2206         struct ixgbe_q_vector *q_vector =
2207                                container_of(napi, struct ixgbe_q_vector, napi);
2208         struct ixgbe_adapter *adapter = q_vector->adapter;
2209         struct ixgbe_ring *tx_ring = NULL;
2210         int work_done = 0;
2211         long r_idx;
2212
2213 #ifdef CONFIG_IXGBE_DCA
2214         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
2215                 ixgbe_update_dca(q_vector);
2216 #endif
2217
2218         r_idx = find_first_bit(q_vector->txr_idx, adapter->num_tx_queues);
2219         tx_ring = adapter->tx_ring[r_idx];
2220
2221         if (!ixgbe_clean_tx_irq(q_vector, tx_ring))
2222                 work_done = budget;
2223
2224         /* If all Tx work done, exit the polling mode */
2225         if (work_done < budget) {
2226                 napi_complete(napi);
2227                 if (adapter->tx_itr_setting & 1)
2228                         ixgbe_set_itr_msix(q_vector);
2229                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2230                         ixgbe_irq_enable_queues(adapter,
2231                                                 ((u64)1 << q_vector->v_idx));
2232         }
2233
2234         return work_done;
2235 }
2236
2237 static inline void map_vector_to_rxq(struct ixgbe_adapter *a, int v_idx,
2238                                      int r_idx)
2239 {
2240         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2241         struct ixgbe_ring *rx_ring = a->rx_ring[r_idx];
2242
2243         set_bit(r_idx, q_vector->rxr_idx);
2244         q_vector->rxr_count++;
2245         rx_ring->q_vector = q_vector;
2246 }
2247
2248 static inline void map_vector_to_txq(struct ixgbe_adapter *a, int v_idx,
2249                                      int t_idx)
2250 {
2251         struct ixgbe_q_vector *q_vector = a->q_vector[v_idx];
2252         struct ixgbe_ring *tx_ring = a->tx_ring[t_idx];
2253
2254         set_bit(t_idx, q_vector->txr_idx);
2255         q_vector->txr_count++;
2256         tx_ring->q_vector = q_vector;
2257 }
2258
2259 /**
2260  * ixgbe_map_rings_to_vectors - Maps descriptor rings to vectors
2261  * @adapter: board private structure to initialize
2262  *
2263  * This function maps descriptor rings to the queue-specific vectors
2264  * we were allotted through the MSI-X enabling code.  Ideally, we'd have
2265  * one vector per ring/queue, but on a constrained vector budget, we
2266  * group the rings as "efficiently" as possible.  You would add new
2267  * mapping configurations in here.
2268  **/
2269 static int ixgbe_map_rings_to_vectors(struct ixgbe_adapter *adapter)
2270 {
2271         int q_vectors;
2272         int v_start = 0;
2273         int rxr_idx = 0, txr_idx = 0;
2274         int rxr_remaining = adapter->num_rx_queues;
2275         int txr_remaining = adapter->num_tx_queues;
2276         int i, j;
2277         int rqpv, tqpv;
2278         int err = 0;
2279
2280         /* No mapping required if MSI-X is disabled. */
2281         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
2282                 goto out;
2283
2284         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2285
2286         /*
2287          * The ideal configuration...
2288          * We have enough vectors to map one per queue.
2289          */
2290         if (q_vectors == adapter->num_rx_queues + adapter->num_tx_queues) {
2291                 for (; rxr_idx < rxr_remaining; v_start++, rxr_idx++)
2292                         map_vector_to_rxq(adapter, v_start, rxr_idx);
2293
2294                 for (; txr_idx < txr_remaining; v_start++, txr_idx++)
2295                         map_vector_to_txq(adapter, v_start, txr_idx);
2296
2297                 goto out;
2298         }
2299
2300         /*
2301          * If we don't have enough vectors for a 1-to-1
2302          * mapping, we'll have to group them so there are
2303          * multiple queues per vector.
2304          */
2305         /* Re-adjusting *qpv takes care of the remainder. */
2306         for (i = v_start; i < q_vectors; i++) {
2307                 rqpv = DIV_ROUND_UP(rxr_remaining, q_vectors - i);
2308                 for (j = 0; j < rqpv; j++) {
2309                         map_vector_to_rxq(adapter, i, rxr_idx);
2310                         rxr_idx++;
2311                         rxr_remaining--;
2312                 }
2313                 tqpv = DIV_ROUND_UP(txr_remaining, q_vectors - i);
2314                 for (j = 0; j < tqpv; j++) {
2315                         map_vector_to_txq(adapter, i, txr_idx);
2316                         txr_idx++;
2317                         txr_remaining--;
2318                 }
2319         }
2320 out:
2321         return err;
2322 }
2323
2324 /**
2325  * ixgbe_request_msix_irqs - Initialize MSI-X interrupts
2326  * @adapter: board private structure
2327  *
2328  * ixgbe_request_msix_irqs allocates MSI-X vectors and requests
2329  * interrupts from the kernel.
2330  **/
2331 static int ixgbe_request_msix_irqs(struct ixgbe_adapter *adapter)
2332 {
2333         struct net_device *netdev = adapter->netdev;
2334         irqreturn_t (*handler)(int, void *);
2335         int i, vector, q_vectors, err;
2336         int ri = 0, ti = 0;
2337
2338         /* Decrement for Other and TCP Timer vectors */
2339         q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2340
2341         err = ixgbe_map_rings_to_vectors(adapter);
2342         if (err)
2343                 return err;
2344
2345 #define SET_HANDLER(_v) (((_v)->rxr_count && (_v)->txr_count)        \
2346                                           ? &ixgbe_msix_clean_many : \
2347                           (_v)->rxr_count ? &ixgbe_msix_clean_rx   : \
2348                           (_v)->txr_count ? &ixgbe_msix_clean_tx   : \
2349                           NULL)
2350         for (vector = 0; vector < q_vectors; vector++) {
2351                 struct ixgbe_q_vector *q_vector = adapter->q_vector[vector];
2352                 handler = SET_HANDLER(q_vector);
2353
2354                 if (handler == &ixgbe_msix_clean_rx) {
2355                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2356                                  "%s-%s-%d", netdev->name, "rx", ri++);
2357                 } else if (handler == &ixgbe_msix_clean_tx) {
2358                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2359                                  "%s-%s-%d", netdev->name, "tx", ti++);
2360                 } else if (handler == &ixgbe_msix_clean_many) {
2361                         snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2362                                  "%s-%s-%d", netdev->name, "TxRx", ri++);
2363                         ti++;
2364                 } else {
2365                         /* skip this unused q_vector */
2366                         continue;
2367                 }
2368                 err = request_irq(adapter->msix_entries[vector].vector,
2369                                   handler, 0, q_vector->name,
2370                                   q_vector);
2371                 if (err) {
2372                         e_err(probe, "request_irq failed for MSIX interrupt "
2373                               "Error: %d\n", err);
2374                         goto free_queue_irqs;
2375                 }
2376         }
2377
2378         sprintf(adapter->lsc_int_name, "%s:lsc", netdev->name);
2379         err = request_irq(adapter->msix_entries[vector].vector,
2380                           ixgbe_msix_lsc, 0, adapter->lsc_int_name, netdev);
2381         if (err) {
2382                 e_err(probe, "request_irq for msix_lsc failed: %d\n", err);
2383                 goto free_queue_irqs;
2384         }
2385
2386         return 0;
2387
2388 free_queue_irqs:
2389         for (i = vector - 1; i >= 0; i--)
2390                 free_irq(adapter->msix_entries[--vector].vector,
2391                          adapter->q_vector[i]);
2392         adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
2393         pci_disable_msix(adapter->pdev);
2394         kfree(adapter->msix_entries);
2395         adapter->msix_entries = NULL;
2396         return err;
2397 }
2398
2399 static void ixgbe_set_itr(struct ixgbe_adapter *adapter)
2400 {
2401         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2402         struct ixgbe_ring *rx_ring = adapter->rx_ring[0];
2403         struct ixgbe_ring *tx_ring = adapter->tx_ring[0];
2404         u32 new_itr = q_vector->eitr;
2405         u8 current_itr;
2406
2407         q_vector->tx_itr = ixgbe_update_itr(adapter, new_itr,
2408                                             q_vector->tx_itr,
2409                                             tx_ring->total_packets,
2410                                             tx_ring->total_bytes);
2411         q_vector->rx_itr = ixgbe_update_itr(adapter, new_itr,
2412                                             q_vector->rx_itr,
2413                                             rx_ring->total_packets,
2414                                             rx_ring->total_bytes);
2415
2416         current_itr = max(q_vector->rx_itr, q_vector->tx_itr);
2417
2418         switch (current_itr) {
2419         /* counts and packets in update_itr are dependent on these numbers */
2420         case lowest_latency:
2421                 new_itr = 100000;
2422                 break;
2423         case low_latency:
2424                 new_itr = 20000; /* aka hwitr = ~200 */
2425                 break;
2426         case bulk_latency:
2427                 new_itr = 8000;
2428                 break;
2429         default:
2430                 break;
2431         }
2432
2433         if (new_itr != q_vector->eitr) {
2434                 /* do an exponential smoothing */
2435                 new_itr = ((q_vector->eitr * 9) + new_itr)/10;
2436
2437                 /* save the algorithm value here */
2438                 q_vector->eitr = new_itr;
2439
2440                 ixgbe_write_eitr(q_vector);
2441         }
2442 }
2443
2444 /**
2445  * ixgbe_irq_enable - Enable default interrupt generation settings
2446  * @adapter: board private structure
2447  **/
2448 static inline void ixgbe_irq_enable(struct ixgbe_adapter *adapter, bool queues,
2449                                     bool flush)
2450 {
2451         u32 mask;
2452
2453         mask = (IXGBE_EIMS_ENABLE_MASK & ~IXGBE_EIMS_RTX_QUEUE);
2454         if (adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE)
2455                 mask |= IXGBE_EIMS_GPI_SDP0;
2456         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
2457                 mask |= IXGBE_EIMS_GPI_SDP1;
2458         switch (adapter->hw.mac.type) {
2459         case ixgbe_mac_82599EB:
2460         case ixgbe_mac_X540:
2461                 mask |= IXGBE_EIMS_ECC;
2462                 mask |= IXGBE_EIMS_GPI_SDP1;
2463                 mask |= IXGBE_EIMS_GPI_SDP2;
2464                 if (adapter->num_vfs)
2465                         mask |= IXGBE_EIMS_MAILBOX;
2466                 break;
2467         default:
2468                 break;
2469         }
2470         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
2471                 mask |= IXGBE_EIMS_FLOW_DIR;
2472
2473         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMS, mask);
2474         if (queues)
2475                 ixgbe_irq_enable_queues(adapter, ~0);
2476         if (flush)
2477                 IXGBE_WRITE_FLUSH(&adapter->hw);
2478
2479         if (adapter->num_vfs > 32) {
2480                 u32 eitrsel = (1 << (adapter->num_vfs - 32)) - 1;
2481                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, eitrsel);
2482         }
2483 }
2484
2485 /**
2486  * ixgbe_intr - legacy mode Interrupt Handler
2487  * @irq: interrupt number
2488  * @data: pointer to a network interface device structure
2489  **/
2490 static irqreturn_t ixgbe_intr(int irq, void *data)
2491 {
2492         struct net_device *netdev = data;
2493         struct ixgbe_adapter *adapter = netdev_priv(netdev);
2494         struct ixgbe_hw *hw = &adapter->hw;
2495         struct ixgbe_q_vector *q_vector = adapter->q_vector[0];
2496         u32 eicr;
2497
2498         /*
2499          * Workaround for silicon errata on 82598.  Mask the interrupts
2500          * before the read of EICR.
2501          */
2502         IXGBE_WRITE_REG(hw, IXGBE_EIMC, IXGBE_IRQ_CLEAR_MASK);
2503
2504         /* for NAPI, using EIAM to auto-mask tx/rx interrupt bits on read
2505          * therefore no explict interrupt disable is necessary */
2506         eicr = IXGBE_READ_REG(hw, IXGBE_EICR);
2507         if (!eicr) {
2508                 /*
2509                  * shared interrupt alert!
2510                  * make sure interrupts are enabled because the read will
2511                  * have disabled interrupts due to EIAM
2512                  * finish the workaround of silicon errata on 82598.  Unmask
2513                  * the interrupt that we masked before the EICR read.
2514                  */
2515                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
2516                         ixgbe_irq_enable(adapter, true, true);
2517                 return IRQ_NONE;        /* Not our interrupt */
2518         }
2519
2520         if (eicr & IXGBE_EICR_LSC)
2521                 ixgbe_check_lsc(adapter);
2522
2523         switch (hw->mac.type) {
2524         case ixgbe_mac_82599EB:
2525                 ixgbe_check_sfp_event(adapter, eicr);
2526                 if ((adapter->flags2 & IXGBE_FLAG2_TEMP_SENSOR_CAPABLE) &&
2527                     ((eicr & IXGBE_EICR_GPI_SDP0) || (eicr & IXGBE_EICR_LSC))) {
2528                         if (!test_bit(__IXGBE_DOWN, &adapter->state)) {
2529                                 adapter->interrupt_event = eicr;
2530                                 adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_EVENT;
2531                                 ixgbe_service_event_schedule(adapter);
2532                         }
2533                 }
2534                 break;
2535         default:
2536                 break;
2537         }
2538
2539         ixgbe_check_fan_failure(adapter, eicr);
2540
2541         if (napi_schedule_prep(&(q_vector->napi))) {
2542                 adapter->tx_ring[0]->total_packets = 0;
2543                 adapter->tx_ring[0]->total_bytes = 0;
2544                 adapter->rx_ring[0]->total_packets = 0;
2545                 adapter->rx_ring[0]->total_bytes = 0;
2546                 /* would disable interrupts here but EIAM disabled it */
2547                 __napi_schedule(&(q_vector->napi));
2548         }
2549
2550         /*
2551          * re-enable link(maybe) and non-queue interrupts, no flush.
2552          * ixgbe_poll will re-enable the queue interrupts
2553          */
2554
2555         if (!test_bit(__IXGBE_DOWN, &adapter->state))
2556                 ixgbe_irq_enable(adapter, false, false);
2557
2558         return IRQ_HANDLED;
2559 }
2560
2561 static inline void ixgbe_reset_q_vectors(struct ixgbe_adapter *adapter)
2562 {
2563         int i, q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
2564
2565         for (i = 0; i < q_vectors; i++) {
2566                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
2567                 bitmap_zero(q_vector->rxr_idx, MAX_RX_QUEUES);
2568                 bitmap_zero(q_vector->txr_idx, MAX_TX_QUEUES);
2569                 q_vector->rxr_count = 0;
2570                 q_vector->txr_count = 0;
2571         }
2572 }
2573
2574 /**
2575  * ixgbe_request_irq - initialize interrupts
2576  * @adapter: board private structure
2577  *
2578  * Attempts to configure interrupts using the best available
2579  * capabilities of the hardware and kernel.
2580  **/
2581 static int ixgbe_request_irq(struct ixgbe_adapter *adapter)
2582 {
2583         struct net_device *netdev = adapter->netdev;
2584         int err;
2585
2586         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2587                 err = ixgbe_request_msix_irqs(adapter);
2588         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
2589                 err = request_irq(adapter->pdev->irq, ixgbe_intr, 0,
2590                                   netdev->name, netdev);
2591         } else {
2592                 err = request_irq(adapter->pdev->irq, ixgbe_intr, IRQF_SHARED,
2593                                   netdev->name, netdev);
2594         }
2595
2596         if (err)
2597                 e_err(probe, "request_irq failed, Error %d\n", err);
2598
2599         return err;
2600 }
2601
2602 static void ixgbe_free_irq(struct ixgbe_adapter *adapter)
2603 {
2604         struct net_device *netdev = adapter->netdev;
2605
2606         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2607                 int i, q_vectors;
2608
2609                 q_vectors = adapter->num_msix_vectors;
2610
2611                 i = q_vectors - 1;
2612                 free_irq(adapter->msix_entries[i].vector, netdev);
2613
2614                 i--;
2615                 for (; i >= 0; i--) {
2616                         /* free only the irqs that were actually requested */
2617                         if (!adapter->q_vector[i]->rxr_count &&
2618                             !adapter->q_vector[i]->txr_count)
2619                                 continue;
2620
2621                         free_irq(adapter->msix_entries[i].vector,
2622                                  adapter->q_vector[i]);
2623                 }
2624
2625                 ixgbe_reset_q_vectors(adapter);
2626         } else {
2627                 free_irq(adapter->pdev->irq, netdev);
2628         }
2629 }
2630
2631 /**
2632  * ixgbe_irq_disable - Mask off interrupt generation on the NIC
2633  * @adapter: board private structure
2634  **/
2635 static inline void ixgbe_irq_disable(struct ixgbe_adapter *adapter)
2636 {
2637         switch (adapter->hw.mac.type) {
2638         case ixgbe_mac_82598EB:
2639                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, ~0);
2640                 break;
2641         case ixgbe_mac_82599EB:
2642         case ixgbe_mac_X540:
2643                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC, 0xFFFF0000);
2644                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(0), ~0);
2645                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_EIMC_EX(1), ~0);
2646                 if (adapter->num_vfs > 32)
2647                         IXGBE_WRITE_REG(&adapter->hw, IXGBE_EITRSEL, 0);
2648                 break;
2649         default:
2650                 break;
2651         }
2652         IXGBE_WRITE_FLUSH(&adapter->hw);
2653         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
2654                 int i;
2655                 for (i = 0; i < adapter->num_msix_vectors; i++)
2656                         synchronize_irq(adapter->msix_entries[i].vector);
2657         } else {
2658                 synchronize_irq(adapter->pdev->irq);
2659         }
2660 }
2661
2662 /**
2663  * ixgbe_configure_msi_and_legacy - Initialize PIN (INTA...) and MSI interrupts
2664  *
2665  **/
2666 static void ixgbe_configure_msi_and_legacy(struct ixgbe_adapter *adapter)
2667 {
2668         struct ixgbe_hw *hw = &adapter->hw;
2669
2670         IXGBE_WRITE_REG(hw, IXGBE_EITR(0),
2671                         EITR_INTS_PER_SEC_TO_REG(adapter->rx_eitr_param));
2672
2673         ixgbe_set_ivar(adapter, 0, 0, 0);
2674         ixgbe_set_ivar(adapter, 1, 0, 0);
2675
2676         map_vector_to_rxq(adapter, 0, 0);
2677         map_vector_to_txq(adapter, 0, 0);
2678
2679         e_info(hw, "Legacy interrupt IVAR setup done\n");
2680 }
2681
2682 /**
2683  * ixgbe_configure_tx_ring - Configure 8259x Tx ring after Reset
2684  * @adapter: board private structure
2685  * @ring: structure containing ring specific data
2686  *
2687  * Configure the Tx descriptor ring after a reset.
2688  **/
2689 void ixgbe_configure_tx_ring(struct ixgbe_adapter *adapter,
2690                              struct ixgbe_ring *ring)
2691 {
2692         struct ixgbe_hw *hw = &adapter->hw;
2693         u64 tdba = ring->dma;
2694         int wait_loop = 10;
2695         u32 txdctl;
2696         u8 reg_idx = ring->reg_idx;
2697
2698         /* disable queue to avoid issues while updating state */
2699         txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2700         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx),
2701                         txdctl & ~IXGBE_TXDCTL_ENABLE);
2702         IXGBE_WRITE_FLUSH(hw);
2703
2704         IXGBE_WRITE_REG(hw, IXGBE_TDBAL(reg_idx),
2705                         (tdba & DMA_BIT_MASK(32)));
2706         IXGBE_WRITE_REG(hw, IXGBE_TDBAH(reg_idx), (tdba >> 32));
2707         IXGBE_WRITE_REG(hw, IXGBE_TDLEN(reg_idx),
2708                         ring->count * sizeof(union ixgbe_adv_tx_desc));
2709         IXGBE_WRITE_REG(hw, IXGBE_TDH(reg_idx), 0);
2710         IXGBE_WRITE_REG(hw, IXGBE_TDT(reg_idx), 0);
2711         ring->tail = hw->hw_addr + IXGBE_TDT(reg_idx);
2712
2713         /* configure fetching thresholds */
2714         if (adapter->rx_itr_setting == 0) {
2715                 /* cannot set wthresh when itr==0 */
2716                 txdctl &= ~0x007F0000;
2717         } else {
2718                 /* enable WTHRESH=8 descriptors, to encourage burst writeback */
2719                 txdctl |= (8 << 16);
2720         }
2721         if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
2722                 /* PThresh workaround for Tx hang with DFP enabled. */
2723                 txdctl |= 32;
2724         }
2725
2726         /* reinitialize flowdirector state */
2727         if ((adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) &&
2728             adapter->atr_sample_rate) {
2729                 ring->atr_sample_rate = adapter->atr_sample_rate;
2730                 ring->atr_count = 0;
2731                 set_bit(__IXGBE_TX_FDIR_INIT_DONE, &ring->state);
2732         } else {
2733                 ring->atr_sample_rate = 0;
2734         }
2735
2736         clear_bit(__IXGBE_HANG_CHECK_ARMED, &ring->state);
2737
2738         /* enable queue */
2739         txdctl |= IXGBE_TXDCTL_ENABLE;
2740         IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), txdctl);
2741
2742         /* TXDCTL.EN will return 0 on 82598 if link is down, so skip it */
2743         if (hw->mac.type == ixgbe_mac_82598EB &&
2744             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
2745                 return;
2746
2747         /* poll to verify queue is enabled */
2748         do {
2749                 usleep_range(1000, 2000);
2750                 txdctl = IXGBE_READ_REG(hw, IXGBE_TXDCTL(reg_idx));
2751         } while (--wait_loop && !(txdctl & IXGBE_TXDCTL_ENABLE));
2752         if (!wait_loop)
2753                 e_err(drv, "Could not enable Tx Queue %d\n", reg_idx);
2754 }
2755
2756 static void ixgbe_setup_mtqc(struct ixgbe_adapter *adapter)
2757 {
2758         struct ixgbe_hw *hw = &adapter->hw;
2759         u32 rttdcs;
2760         u32 reg;
2761         u8 tcs = netdev_get_num_tc(adapter->netdev);
2762
2763         if (hw->mac.type == ixgbe_mac_82598EB)
2764                 return;
2765
2766         /* disable the arbiter while setting MTQC */
2767         rttdcs = IXGBE_READ_REG(hw, IXGBE_RTTDCS);
2768         rttdcs |= IXGBE_RTTDCS_ARBDIS;
2769         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2770
2771         /* set transmit pool layout */
2772         switch (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
2773         case (IXGBE_FLAG_SRIOV_ENABLED):
2774                 IXGBE_WRITE_REG(hw, IXGBE_MTQC,
2775                                 (IXGBE_MTQC_VT_ENA | IXGBE_MTQC_64VF));
2776                 break;
2777         default:
2778                 if (!tcs)
2779                         reg = IXGBE_MTQC_64Q_1PB;
2780                 else if (tcs <= 4)
2781                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_4TC_4TQ;
2782                 else
2783                         reg = IXGBE_MTQC_RT_ENA | IXGBE_MTQC_8TC_8TQ;
2784
2785                 IXGBE_WRITE_REG(hw, IXGBE_MTQC, reg);
2786
2787                 /* Enable Security TX Buffer IFG for multiple pb */
2788                 if (tcs) {
2789                         reg = IXGBE_READ_REG(hw, IXGBE_SECTXMINIFG);
2790                         reg |= IXGBE_SECTX_DCB;
2791                         IXGBE_WRITE_REG(hw, IXGBE_SECTXMINIFG, reg);
2792                 }
2793                 break;
2794         }
2795
2796         /* re-enable the arbiter */
2797         rttdcs &= ~IXGBE_RTTDCS_ARBDIS;
2798         IXGBE_WRITE_REG(hw, IXGBE_RTTDCS, rttdcs);
2799 }
2800
2801 /**
2802  * ixgbe_configure_tx - Configure 8259x Transmit Unit after Reset
2803  * @adapter: board private structure
2804  *
2805  * Configure the Tx unit of the MAC after a reset.
2806  **/
2807 static void ixgbe_configure_tx(struct ixgbe_adapter *adapter)
2808 {
2809         struct ixgbe_hw *hw = &adapter->hw;
2810         u32 dmatxctl;
2811         u32 i;
2812
2813         ixgbe_setup_mtqc(adapter);
2814
2815         if (hw->mac.type != ixgbe_mac_82598EB) {
2816                 /* DMATXCTL.EN must be before Tx queues are enabled */
2817                 dmatxctl = IXGBE_READ_REG(hw, IXGBE_DMATXCTL);
2818                 dmatxctl |= IXGBE_DMATXCTL_TE;
2819                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, dmatxctl);
2820         }
2821
2822         /* Setup the HW Tx Head and Tail descriptor pointers */
2823         for (i = 0; i < adapter->num_tx_queues; i++)
2824                 ixgbe_configure_tx_ring(adapter, adapter->tx_ring[i]);
2825 }
2826
2827 #define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2
2828
2829 static void ixgbe_configure_srrctl(struct ixgbe_adapter *adapter,
2830                                    struct ixgbe_ring *rx_ring)
2831 {
2832         u32 srrctl;
2833         u8 reg_idx = rx_ring->reg_idx;
2834
2835         switch (adapter->hw.mac.type) {
2836         case ixgbe_mac_82598EB: {
2837                 struct ixgbe_ring_feature *feature = adapter->ring_feature;
2838                 const int mask = feature[RING_F_RSS].mask;
2839                 reg_idx = reg_idx & mask;
2840         }
2841                 break;
2842         case ixgbe_mac_82599EB:
2843         case ixgbe_mac_X540:
2844         default:
2845                 break;
2846         }
2847
2848         srrctl = IXGBE_READ_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx));
2849
2850         srrctl &= ~IXGBE_SRRCTL_BSIZEHDR_MASK;
2851         srrctl &= ~IXGBE_SRRCTL_BSIZEPKT_MASK;
2852         if (adapter->num_vfs)
2853                 srrctl |= IXGBE_SRRCTL_DROP_EN;
2854
2855         srrctl |= (IXGBE_RX_HDR_SIZE << IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT) &
2856                   IXGBE_SRRCTL_BSIZEHDR_MASK;
2857
2858         if (ring_is_ps_enabled(rx_ring)) {
2859 #if (PAGE_SIZE / 2) > IXGBE_MAX_RXBUFFER
2860                 srrctl |= IXGBE_MAX_RXBUFFER >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2861 #else
2862                 srrctl |= (PAGE_SIZE / 2) >> IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2863 #endif
2864                 srrctl |= IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2865         } else {
2866                 srrctl |= ALIGN(rx_ring->rx_buf_len, 1024) >>
2867                           IXGBE_SRRCTL_BSIZEPKT_SHIFT;
2868                 srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF;
2869         }
2870
2871         IXGBE_WRITE_REG(&adapter->hw, IXGBE_SRRCTL(reg_idx), srrctl);
2872 }
2873
2874 static void ixgbe_setup_mrqc(struct ixgbe_adapter *adapter)
2875 {
2876         struct ixgbe_hw *hw = &adapter->hw;
2877         static const u32 seed[10] = { 0xE291D73D, 0x1805EC6C, 0x2A94B30D,
2878                           0xA54F2BEC, 0xEA49AF7C, 0xE214AD3D, 0xB855AABE,
2879                           0x6A3E67EA, 0x14364D17, 0x3BED200D};
2880         u32 mrqc = 0, reta = 0;
2881         u32 rxcsum;
2882         int i, j;
2883         u8 tcs = netdev_get_num_tc(adapter->netdev);
2884         int maxq = adapter->ring_feature[RING_F_RSS].indices;
2885
2886         if (tcs)
2887                 maxq = min(maxq, adapter->num_tx_queues / tcs);
2888
2889         /* Fill out hash function seeds */
2890         for (i = 0; i < 10; i++)
2891                 IXGBE_WRITE_REG(hw, IXGBE_RSSRK(i), seed[i]);
2892
2893         /* Fill out redirection table */
2894         for (i = 0, j = 0; i < 128; i++, j++) {
2895                 if (j == maxq)
2896                         j = 0;
2897                 /* reta = 4-byte sliding window of
2898                  * 0x00..(indices-1)(indices-1)00..etc. */
2899                 reta = (reta << 8) | (j * 0x11);
2900                 if ((i & 3) == 3)
2901                         IXGBE_WRITE_REG(hw, IXGBE_RETA(i >> 2), reta);
2902         }
2903
2904         /* Disable indicating checksum in descriptor, enables RSS hash */
2905         rxcsum = IXGBE_READ_REG(hw, IXGBE_RXCSUM);
2906         rxcsum |= IXGBE_RXCSUM_PCSD;
2907         IXGBE_WRITE_REG(hw, IXGBE_RXCSUM, rxcsum);
2908
2909         if (adapter->hw.mac.type == ixgbe_mac_82598EB &&
2910             (adapter->flags & IXGBE_FLAG_RSS_ENABLED)) {
2911                 mrqc = IXGBE_MRQC_RSSEN;
2912         } else {
2913                 int mask = adapter->flags & (IXGBE_FLAG_RSS_ENABLED
2914                                              | IXGBE_FLAG_SRIOV_ENABLED);
2915
2916                 switch (mask) {
2917                 case (IXGBE_FLAG_RSS_ENABLED):
2918                         if (!tcs)
2919                                 mrqc = IXGBE_MRQC_RSSEN;
2920                         else if (tcs <= 4)
2921                                 mrqc = IXGBE_MRQC_RTRSS4TCEN;
2922                         else
2923                                 mrqc = IXGBE_MRQC_RTRSS8TCEN;
2924                         break;
2925                 case (IXGBE_FLAG_SRIOV_ENABLED):
2926                         mrqc = IXGBE_MRQC_VMDQEN;
2927                         break;
2928                 default:
2929                         break;
2930                 }
2931         }
2932
2933         /* Perform hash on these packet types */
2934         mrqc |= IXGBE_MRQC_RSS_FIELD_IPV4
2935               | IXGBE_MRQC_RSS_FIELD_IPV4_TCP
2936               | IXGBE_MRQC_RSS_FIELD_IPV6
2937               | IXGBE_MRQC_RSS_FIELD_IPV6_TCP;
2938
2939         IXGBE_WRITE_REG(hw, IXGBE_MRQC, mrqc);
2940 }
2941
2942 /**
2943  * ixgbe_clear_rscctl - disable RSC for the indicated ring
2944  * @adapter: address of board private structure
2945  * @ring: structure containing ring specific data
2946  **/
2947 void ixgbe_clear_rscctl(struct ixgbe_adapter *adapter,
2948                         struct ixgbe_ring *ring)
2949 {
2950         struct ixgbe_hw *hw = &adapter->hw;
2951         u32 rscctrl;
2952         u8 reg_idx = ring->reg_idx;
2953
2954         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2955         rscctrl &= ~IXGBE_RSCCTL_RSCEN;
2956         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
2957 }
2958
2959 /**
2960  * ixgbe_configure_rscctl - enable RSC for the indicated ring
2961  * @adapter:    address of board private structure
2962  * @index:      index of ring to set
2963  **/
2964 void ixgbe_configure_rscctl(struct ixgbe_adapter *adapter,
2965                                    struct ixgbe_ring *ring)
2966 {
2967         struct ixgbe_hw *hw = &adapter->hw;
2968         u32 rscctrl;
2969         int rx_buf_len;
2970         u8 reg_idx = ring->reg_idx;
2971
2972         if (!ring_is_rsc_enabled(ring))
2973                 return;
2974
2975         rx_buf_len = ring->rx_buf_len;
2976         rscctrl = IXGBE_READ_REG(hw, IXGBE_RSCCTL(reg_idx));
2977         rscctrl |= IXGBE_RSCCTL_RSCEN;
2978         /*
2979          * we must limit the number of descriptors so that the
2980          * total size of max desc * buf_len is not greater
2981          * than 65535
2982          */
2983         if (ring_is_ps_enabled(ring)) {
2984 #if (MAX_SKB_FRAGS > 16)
2985                 rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2986 #elif (MAX_SKB_FRAGS > 8)
2987                 rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2988 #elif (MAX_SKB_FRAGS > 4)
2989                 rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
2990 #else
2991                 rscctrl |= IXGBE_RSCCTL_MAXDESC_1;
2992 #endif
2993         } else {
2994                 if (rx_buf_len < IXGBE_RXBUFFER_4096)
2995                         rscctrl |= IXGBE_RSCCTL_MAXDESC_16;
2996                 else if (rx_buf_len < IXGBE_RXBUFFER_8192)
2997                         rscctrl |= IXGBE_RSCCTL_MAXDESC_8;
2998                 else
2999                         rscctrl |= IXGBE_RSCCTL_MAXDESC_4;
3000         }
3001         IXGBE_WRITE_REG(hw, IXGBE_RSCCTL(reg_idx), rscctrl);
3002 }
3003
3004 /**
3005  *  ixgbe_set_uta - Set unicast filter table address
3006  *  @adapter: board private structure
3007  *
3008  *  The unicast table address is a register array of 32-bit registers.
3009  *  The table is meant to be used in a way similar to how the MTA is used
3010  *  however due to certain limitations in the hardware it is necessary to
3011  *  set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
3012  *  enable bit to allow vlan tag stripping when promiscuous mode is enabled
3013  **/
3014 static void ixgbe_set_uta(struct ixgbe_adapter *adapter)
3015 {
3016         struct ixgbe_hw *hw = &adapter->hw;
3017         int i;
3018
3019         /* The UTA table only exists on 82599 hardware and newer */
3020         if (hw->mac.type < ixgbe_mac_82599EB)
3021                 return;
3022
3023         /* we only need to do this if VMDq is enabled */
3024         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3025                 return;
3026
3027         for (i = 0; i < 128; i++)
3028                 IXGBE_WRITE_REG(hw, IXGBE_UTA(i), ~0);
3029 }
3030
3031 #define IXGBE_MAX_RX_DESC_POLL 10
3032 static void ixgbe_rx_desc_queue_enable(struct ixgbe_adapter *adapter,
3033                                        struct ixgbe_ring *ring)
3034 {
3035         struct ixgbe_hw *hw = &adapter->hw;
3036         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3037         u32 rxdctl;
3038         u8 reg_idx = ring->reg_idx;
3039
3040         /* RXDCTL.EN will return 0 on 82598 if link is down, so skip it */
3041         if (hw->mac.type == ixgbe_mac_82598EB &&
3042             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3043                 return;
3044
3045         do {
3046                 usleep_range(1000, 2000);
3047                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3048         } while (--wait_loop && !(rxdctl & IXGBE_RXDCTL_ENABLE));
3049
3050         if (!wait_loop) {
3051                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not set within "
3052                       "the polling period\n", reg_idx);
3053         }
3054 }
3055
3056 void ixgbe_disable_rx_queue(struct ixgbe_adapter *adapter,
3057                             struct ixgbe_ring *ring)
3058 {
3059         struct ixgbe_hw *hw = &adapter->hw;
3060         int wait_loop = IXGBE_MAX_RX_DESC_POLL;
3061         u32 rxdctl;
3062         u8 reg_idx = ring->reg_idx;
3063
3064         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3065         rxdctl &= ~IXGBE_RXDCTL_ENABLE;
3066
3067         /* write value back with RXDCTL.ENABLE bit cleared */
3068         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3069
3070         if (hw->mac.type == ixgbe_mac_82598EB &&
3071             !(IXGBE_READ_REG(hw, IXGBE_LINKS) & IXGBE_LINKS_UP))
3072                 return;
3073
3074         /* the hardware may take up to 100us to really disable the rx queue */
3075         do {
3076                 udelay(10);
3077                 rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3078         } while (--wait_loop && (rxdctl & IXGBE_RXDCTL_ENABLE));
3079
3080         if (!wait_loop) {
3081                 e_err(drv, "RXDCTL.ENABLE on Rx queue %d not cleared within "
3082                       "the polling period\n", reg_idx);
3083         }
3084 }
3085
3086 void ixgbe_configure_rx_ring(struct ixgbe_adapter *adapter,
3087                              struct ixgbe_ring *ring)
3088 {
3089         struct ixgbe_hw *hw = &adapter->hw;
3090         u64 rdba = ring->dma;
3091         u32 rxdctl;
3092         u8 reg_idx = ring->reg_idx;
3093
3094         /* disable queue to avoid issues while updating state */
3095         rxdctl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(reg_idx));
3096         ixgbe_disable_rx_queue(adapter, ring);
3097
3098         IXGBE_WRITE_REG(hw, IXGBE_RDBAL(reg_idx), (rdba & DMA_BIT_MASK(32)));
3099         IXGBE_WRITE_REG(hw, IXGBE_RDBAH(reg_idx), (rdba >> 32));
3100         IXGBE_WRITE_REG(hw, IXGBE_RDLEN(reg_idx),
3101                         ring->count * sizeof(union ixgbe_adv_rx_desc));
3102         IXGBE_WRITE_REG(hw, IXGBE_RDH(reg_idx), 0);
3103         IXGBE_WRITE_REG(hw, IXGBE_RDT(reg_idx), 0);
3104         ring->tail = hw->hw_addr + IXGBE_RDT(reg_idx);
3105
3106         ixgbe_configure_srrctl(adapter, ring);
3107         ixgbe_configure_rscctl(adapter, ring);
3108
3109         /* If operating in IOV mode set RLPML for X540 */
3110         if ((adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) &&
3111             hw->mac.type == ixgbe_mac_X540) {
3112                 rxdctl &= ~IXGBE_RXDCTL_RLPMLMASK;
3113                 rxdctl |= ((ring->netdev->mtu + ETH_HLEN +
3114                             ETH_FCS_LEN + VLAN_HLEN) | IXGBE_RXDCTL_RLPML_EN);
3115         }
3116
3117         if (hw->mac.type == ixgbe_mac_82598EB) {
3118                 /*
3119                  * enable cache line friendly hardware writes:
3120                  * PTHRESH=32 descriptors (half the internal cache),
3121                  * this also removes ugly rx_no_buffer_count increment
3122                  * HTHRESH=4 descriptors (to minimize latency on fetch)
3123                  * WTHRESH=8 burst writeback up to two cache lines
3124                  */
3125                 rxdctl &= ~0x3FFFFF;
3126                 rxdctl |=  0x080420;
3127         }
3128
3129         /* enable receive descriptor ring */
3130         rxdctl |= IXGBE_RXDCTL_ENABLE;
3131         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(reg_idx), rxdctl);
3132
3133         ixgbe_rx_desc_queue_enable(adapter, ring);
3134         ixgbe_alloc_rx_buffers(ring, IXGBE_DESC_UNUSED(ring));
3135 }
3136
3137 static void ixgbe_setup_psrtype(struct ixgbe_adapter *adapter)
3138 {
3139         struct ixgbe_hw *hw = &adapter->hw;
3140         int p;
3141
3142         /* PSRTYPE must be initialized in non 82598 adapters */
3143         u32 psrtype = IXGBE_PSRTYPE_TCPHDR |
3144                       IXGBE_PSRTYPE_UDPHDR |
3145                       IXGBE_PSRTYPE_IPV4HDR |
3146                       IXGBE_PSRTYPE_L2HDR |
3147                       IXGBE_PSRTYPE_IPV6HDR;
3148
3149         if (hw->mac.type == ixgbe_mac_82598EB)
3150                 return;
3151
3152         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED)
3153                 psrtype |= (adapter->num_rx_queues_per_pool << 29);
3154
3155         for (p = 0; p < adapter->num_rx_pools; p++)
3156                 IXGBE_WRITE_REG(hw, IXGBE_PSRTYPE(adapter->num_vfs + p),
3157                                 psrtype);
3158 }
3159
3160 static void ixgbe_configure_virtualization(struct ixgbe_adapter *adapter)
3161 {
3162         struct ixgbe_hw *hw = &adapter->hw;
3163         u32 gcr_ext;
3164         u32 vt_reg_bits;
3165         u32 reg_offset, vf_shift;
3166         u32 vmdctl;
3167
3168         if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
3169                 return;
3170
3171         vmdctl = IXGBE_READ_REG(hw, IXGBE_VT_CTL);
3172         vt_reg_bits = IXGBE_VMD_CTL_VMDQ_EN | IXGBE_VT_CTL_REPLEN;
3173         vt_reg_bits |= (adapter->num_vfs << IXGBE_VT_CTL_POOL_SHIFT);
3174         IXGBE_WRITE_REG(hw, IXGBE_VT_CTL, vmdctl | vt_reg_bits);
3175
3176         vf_shift = adapter->num_vfs % 32;
3177         reg_offset = (adapter->num_vfs > 32) ? 1 : 0;
3178
3179         /* Enable only the PF's pool for Tx/Rx */
3180         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset), (1 << vf_shift));
3181         IXGBE_WRITE_REG(hw, IXGBE_VFRE(reg_offset ^ 1), 0);
3182         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset), (1 << vf_shift));
3183         IXGBE_WRITE_REG(hw, IXGBE_VFTE(reg_offset ^ 1), 0);
3184         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3185
3186         /* Map PF MAC address in RAR Entry 0 to first pool following VFs */
3187         hw->mac.ops.set_vmdq(hw, 0, adapter->num_vfs);
3188
3189         /*
3190          * Set up VF register offsets for selected VT Mode,
3191          * i.e. 32 or 64 VFs for SR-IOV
3192          */
3193         gcr_ext = IXGBE_READ_REG(hw, IXGBE_GCR_EXT);
3194         gcr_ext |= IXGBE_GCR_EXT_MSIX_EN;
3195         gcr_ext |= IXGBE_GCR_EXT_VT_MODE_64;
3196         IXGBE_WRITE_REG(hw, IXGBE_GCR_EXT, gcr_ext);
3197
3198         /* enable Tx loopback for VF/PF communication */
3199         IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, IXGBE_PFDTXGSWC_VT_LBEN);
3200         /* Enable MAC Anti-Spoofing */
3201         hw->mac.ops.set_mac_anti_spoofing(hw,
3202                                           (adapter->antispoofing_enabled =
3203                                            (adapter->num_vfs != 0)),
3204                                           adapter->num_vfs);
3205 }
3206
3207 static void ixgbe_set_rx_buffer_len(struct ixgbe_adapter *adapter)
3208 {
3209         struct ixgbe_hw *hw = &adapter->hw;
3210         struct net_device *netdev = adapter->netdev;
3211         int max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3212         int rx_buf_len;
3213         struct ixgbe_ring *rx_ring;
3214         int i;
3215         u32 mhadd, hlreg0;
3216
3217         /* Decide whether to use packet split mode or not */
3218         /* On by default */
3219         adapter->flags |= IXGBE_FLAG_RX_PS_ENABLED;
3220
3221         /* Do not use packet split if we're in SR-IOV Mode */
3222         if (adapter->num_vfs)
3223                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3224
3225         /* Disable packet split due to 82599 erratum #45 */
3226         if (hw->mac.type == ixgbe_mac_82599EB)
3227                 adapter->flags &= ~IXGBE_FLAG_RX_PS_ENABLED;
3228
3229         /* Set the RX buffer length according to the mode */
3230         if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED) {
3231                 rx_buf_len = IXGBE_RX_HDR_SIZE;
3232         } else {
3233                 if (!(adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) &&
3234                     (netdev->mtu <= ETH_DATA_LEN))
3235                         rx_buf_len = MAXIMUM_ETHERNET_VLAN_SIZE;
3236                 else
3237                         rx_buf_len = ALIGN(max_frame + VLAN_HLEN, 1024);
3238         }
3239
3240 #ifdef IXGBE_FCOE
3241         /* adjust max frame to be able to do baby jumbo for FCoE */
3242         if ((adapter->flags & IXGBE_FLAG_FCOE_ENABLED) &&
3243             (max_frame < IXGBE_FCOE_JUMBO_FRAME_SIZE))
3244                 max_frame = IXGBE_FCOE_JUMBO_FRAME_SIZE;
3245
3246 #endif /* IXGBE_FCOE */
3247         mhadd = IXGBE_READ_REG(hw, IXGBE_MHADD);
3248         if (max_frame != (mhadd >> IXGBE_MHADD_MFS_SHIFT)) {
3249                 mhadd &= ~IXGBE_MHADD_MFS_MASK;
3250                 mhadd |= max_frame << IXGBE_MHADD_MFS_SHIFT;
3251
3252                 IXGBE_WRITE_REG(hw, IXGBE_MHADD, mhadd);
3253         }
3254
3255         hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0);
3256         /* set jumbo enable since MHADD.MFS is keeping size locked at max_frame */
3257         hlreg0 |= IXGBE_HLREG0_JUMBOEN;
3258         IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0);
3259
3260         /*
3261          * Setup the HW Rx Head and Tail Descriptor Pointers and
3262          * the Base and Length of the Rx Descriptor Ring
3263          */
3264         for (i = 0; i < adapter->num_rx_queues; i++) {
3265                 rx_ring = adapter->rx_ring[i];
3266                 rx_ring->rx_buf_len = rx_buf_len;
3267
3268                 if (adapter->flags & IXGBE_FLAG_RX_PS_ENABLED)
3269                         set_ring_ps_enabled(rx_ring);
3270                 else
3271                         clear_ring_ps_enabled(rx_ring);
3272
3273                 if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
3274                         set_ring_rsc_enabled(rx_ring);
3275                 else
3276                         clear_ring_rsc_enabled(rx_ring);
3277
3278 #ifdef IXGBE_FCOE
3279                 if (netdev->features & NETIF_F_FCOE_MTU) {
3280                         struct ixgbe_ring_feature *f;
3281                         f = &adapter->ring_feature[RING_F_FCOE];
3282                         if ((i >= f->mask) && (i < f->mask + f->indices)) {
3283                                 clear_ring_ps_enabled(rx_ring);
3284                                 if (rx_buf_len < IXGBE_FCOE_JUMBO_FRAME_SIZE)
3285                                         rx_ring->rx_buf_len =
3286                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3287                         } else if (!ring_is_rsc_enabled(rx_ring) &&
3288                                    !ring_is_ps_enabled(rx_ring)) {
3289                                 rx_ring->rx_buf_len =
3290                                                 IXGBE_FCOE_JUMBO_FRAME_SIZE;
3291                         }
3292                 }
3293 #endif /* IXGBE_FCOE */
3294         }
3295 }
3296
3297 static void ixgbe_setup_rdrxctl(struct ixgbe_adapter *adapter)
3298 {
3299         struct ixgbe_hw *hw = &adapter->hw;
3300         u32 rdrxctl = IXGBE_READ_REG(hw, IXGBE_RDRXCTL);
3301
3302         switch (hw->mac.type) {
3303         case ixgbe_mac_82598EB:
3304                 /*
3305                  * For VMDq support of different descriptor types or
3306                  * buffer sizes through the use of multiple SRRCTL
3307                  * registers, RDRXCTL.MVMEN must be set to 1
3308                  *
3309                  * also, the manual doesn't mention it clearly but DCA hints
3310                  * will only use queue 0's tags unless this bit is set.  Side
3311                  * effects of setting this bit are only that SRRCTL must be
3312                  * fully programmed [0..15]
3313                  */
3314                 rdrxctl |= IXGBE_RDRXCTL_MVMEN;
3315                 break;
3316         case ixgbe_mac_82599EB:
3317         case ixgbe_mac_X540:
3318                 /* Disable RSC for ACK packets */
3319                 IXGBE_WRITE_REG(hw, IXGBE_RSCDBU,
3320                    (IXGBE_RSCDBU_RSCACKDIS | IXGBE_READ_REG(hw, IXGBE_RSCDBU)));
3321                 rdrxctl &= ~IXGBE_RDRXCTL_RSCFRSTSIZE;
3322                 /* hardware requires some bits to be set by default */
3323                 rdrxctl |= (IXGBE_RDRXCTL_RSCACKC | IXGBE_RDRXCTL_FCOE_WRFIX);
3324                 rdrxctl |= IXGBE_RDRXCTL_CRCSTRIP;
3325                 break;
3326         default:
3327                 /* We should do nothing since we don't know this hardware */
3328                 return;
3329         }
3330
3331         IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, rdrxctl);
3332 }
3333
3334 /**
3335  * ixgbe_configure_rx - Configure 8259x Receive Unit after Reset
3336  * @adapter: board private structure
3337  *
3338  * Configure the Rx unit of the MAC after a reset.
3339  **/
3340 static void ixgbe_configure_rx(struct ixgbe_adapter *adapter)
3341 {
3342         struct ixgbe_hw *hw = &adapter->hw;
3343         int i;
3344         u32 rxctrl;
3345
3346         /* disable receives while setting up the descriptors */
3347         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
3348         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
3349
3350         ixgbe_setup_psrtype(adapter);
3351         ixgbe_setup_rdrxctl(adapter);
3352
3353         /* Program registers for the distribution of queues */
3354         ixgbe_setup_mrqc(adapter);
3355
3356         ixgbe_set_uta(adapter);
3357
3358         /* set_rx_buffer_len must be called before ring initialization */
3359         ixgbe_set_rx_buffer_len(adapter);
3360
3361         /*
3362          * Setup the HW Rx Head and Tail Descriptor Pointers and
3363          * the Base and Length of the Rx Descriptor Ring
3364          */
3365         for (i = 0; i < adapter->num_rx_queues; i++)
3366                 ixgbe_configure_rx_ring(adapter, adapter->rx_ring[i]);
3367
3368         /* disable drop enable for 82598 parts */
3369         if (hw->mac.type == ixgbe_mac_82598EB)
3370                 rxctrl |= IXGBE_RXCTRL_DMBYPS;
3371
3372         /* enable all receives */
3373         rxctrl |= IXGBE_RXCTRL_RXEN;
3374         hw->mac.ops.enable_rx_dma(hw, rxctrl);
3375 }
3376
3377 static void ixgbe_vlan_rx_add_vid(struct net_device *netdev, u16 vid)
3378 {
3379         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3380         struct ixgbe_hw *hw = &adapter->hw;
3381         int pool_ndx = adapter->num_vfs;
3382
3383         /* add VID to filter table */
3384         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, true);
3385         set_bit(vid, adapter->active_vlans);
3386 }
3387
3388 static void ixgbe_vlan_rx_kill_vid(struct net_device *netdev, u16 vid)
3389 {
3390         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3391         struct ixgbe_hw *hw = &adapter->hw;
3392         int pool_ndx = adapter->num_vfs;
3393
3394         /* remove VID from filter table */
3395         hw->mac.ops.set_vfta(&adapter->hw, vid, pool_ndx, false);
3396         clear_bit(vid, adapter->active_vlans);
3397 }
3398
3399 /**
3400  * ixgbe_vlan_filter_disable - helper to disable hw vlan filtering
3401  * @adapter: driver data
3402  */
3403 static void ixgbe_vlan_filter_disable(struct ixgbe_adapter *adapter)
3404 {
3405         struct ixgbe_hw *hw = &adapter->hw;
3406         u32 vlnctrl;
3407
3408         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3409         vlnctrl &= ~(IXGBE_VLNCTRL_VFE | IXGBE_VLNCTRL_CFIEN);
3410         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3411 }
3412
3413 /**
3414  * ixgbe_vlan_filter_enable - helper to enable hw vlan filtering
3415  * @adapter: driver data
3416  */
3417 static void ixgbe_vlan_filter_enable(struct ixgbe_adapter *adapter)
3418 {
3419         struct ixgbe_hw *hw = &adapter->hw;
3420         u32 vlnctrl;
3421
3422         vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3423         vlnctrl |= IXGBE_VLNCTRL_VFE;
3424         vlnctrl &= ~IXGBE_VLNCTRL_CFIEN;
3425         IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3426 }
3427
3428 /**
3429  * ixgbe_vlan_strip_disable - helper to disable hw vlan stripping
3430  * @adapter: driver data
3431  */
3432 static void ixgbe_vlan_strip_disable(struct ixgbe_adapter *adapter)
3433 {
3434         struct ixgbe_hw *hw = &adapter->hw;
3435         u32 vlnctrl;
3436         int i, j;
3437
3438         switch (hw->mac.type) {
3439         case ixgbe_mac_82598EB:
3440                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3441                 vlnctrl &= ~IXGBE_VLNCTRL_VME;
3442                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3443                 break;
3444         case ixgbe_mac_82599EB:
3445         case ixgbe_mac_X540:
3446                 for (i = 0; i < adapter->num_rx_queues; i++) {
3447                         j = adapter->rx_ring[i]->reg_idx;
3448                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3449                         vlnctrl &= ~IXGBE_RXDCTL_VME;
3450                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3451                 }
3452                 break;
3453         default:
3454                 break;
3455         }
3456 }
3457
3458 /**
3459  * ixgbe_vlan_strip_enable - helper to enable hw vlan stripping
3460  * @adapter: driver data
3461  */
3462 static void ixgbe_vlan_strip_enable(struct ixgbe_adapter *adapter)
3463 {
3464         struct ixgbe_hw *hw = &adapter->hw;
3465         u32 vlnctrl;
3466         int i, j;
3467
3468         switch (hw->mac.type) {
3469         case ixgbe_mac_82598EB:
3470                 vlnctrl = IXGBE_READ_REG(hw, IXGBE_VLNCTRL);
3471                 vlnctrl |= IXGBE_VLNCTRL_VME;
3472                 IXGBE_WRITE_REG(hw, IXGBE_VLNCTRL, vlnctrl);
3473                 break;
3474         case ixgbe_mac_82599EB:
3475         case ixgbe_mac_X540:
3476                 for (i = 0; i < adapter->num_rx_queues; i++) {
3477                         j = adapter->rx_ring[i]->reg_idx;
3478                         vlnctrl = IXGBE_READ_REG(hw, IXGBE_RXDCTL(j));
3479                         vlnctrl |= IXGBE_RXDCTL_VME;
3480                         IXGBE_WRITE_REG(hw, IXGBE_RXDCTL(j), vlnctrl);
3481                 }
3482                 break;
3483         default:
3484                 break;
3485         }
3486 }
3487
3488 static void ixgbe_restore_vlan(struct ixgbe_adapter *adapter)
3489 {
3490         u16 vid;
3491
3492         ixgbe_vlan_rx_add_vid(adapter->netdev, 0);
3493
3494         for_each_set_bit(vid, adapter->active_vlans, VLAN_N_VID)
3495                 ixgbe_vlan_rx_add_vid(adapter->netdev, vid);
3496 }
3497
3498 /**
3499  * ixgbe_write_uc_addr_list - write unicast addresses to RAR table
3500  * @netdev: network interface device structure
3501  *
3502  * Writes unicast address list to the RAR table.
3503  * Returns: -ENOMEM on failure/insufficient address space
3504  *                0 on no addresses written
3505  *                X on writing X addresses to the RAR table
3506  **/
3507 static int ixgbe_write_uc_addr_list(struct net_device *netdev)
3508 {
3509         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3510         struct ixgbe_hw *hw = &adapter->hw;
3511         unsigned int vfn = adapter->num_vfs;
3512         unsigned int rar_entries = IXGBE_MAX_PF_MACVLANS;
3513         int count = 0;
3514
3515         /* return ENOMEM indicating insufficient memory for addresses */
3516         if (netdev_uc_count(netdev) > rar_entries)
3517                 return -ENOMEM;
3518
3519         if (!netdev_uc_empty(netdev) && rar_entries) {
3520                 struct netdev_hw_addr *ha;
3521                 /* return error if we do not support writing to RAR table */
3522                 if (!hw->mac.ops.set_rar)
3523                         return -ENOMEM;
3524
3525                 netdev_for_each_uc_addr(ha, netdev) {
3526                         if (!rar_entries)
3527                                 break;
3528                         hw->mac.ops.set_rar(hw, rar_entries--, ha->addr,
3529                                             vfn, IXGBE_RAH_AV);
3530                         count++;
3531                 }
3532         }
3533         /* write the addresses in reverse order to avoid write combining */
3534         for (; rar_entries > 0 ; rar_entries--)
3535                 hw->mac.ops.clear_rar(hw, rar_entries);
3536
3537         return count;
3538 }
3539
3540 /**
3541  * ixgbe_set_rx_mode - Unicast, Multicast and Promiscuous mode set
3542  * @netdev: network interface device structure
3543  *
3544  * The set_rx_method entry point is called whenever the unicast/multicast
3545  * address list or the network interface flags are updated.  This routine is
3546  * responsible for configuring the hardware for proper unicast, multicast and
3547  * promiscuous mode.
3548  **/
3549 void ixgbe_set_rx_mode(struct net_device *netdev)
3550 {
3551         struct ixgbe_adapter *adapter = netdev_priv(netdev);
3552         struct ixgbe_hw *hw = &adapter->hw;
3553         u32 fctrl, vmolr = IXGBE_VMOLR_BAM | IXGBE_VMOLR_AUPE;
3554         int count;
3555
3556         /* Check for Promiscuous and All Multicast modes */
3557
3558         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
3559
3560         /* set all bits that we expect to always be set */
3561         fctrl |= IXGBE_FCTRL_BAM;
3562         fctrl |= IXGBE_FCTRL_DPF; /* discard pause frames when FC enabled */
3563         fctrl |= IXGBE_FCTRL_PMCF;
3564
3565         /* clear the bits we are changing the status of */
3566         fctrl &= ~(IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3567
3568         if (netdev->flags & IFF_PROMISC) {
3569                 hw->addr_ctrl.user_set_promisc = true;
3570                 fctrl |= (IXGBE_FCTRL_UPE | IXGBE_FCTRL_MPE);
3571                 vmolr |= (IXGBE_VMOLR_ROPE | IXGBE_VMOLR_MPE);
3572                 /* don't hardware filter vlans in promisc mode */
3573                 ixgbe_vlan_filter_disable(adapter);
3574         } else {
3575                 if (netdev->flags & IFF_ALLMULTI) {
3576                         fctrl |= IXGBE_FCTRL_MPE;
3577                         vmolr |= IXGBE_VMOLR_MPE;
3578                 } else {
3579                         /*
3580                          * Write addresses to the MTA, if the attempt fails
3581                          * then we should just turn on promiscuous mode so
3582                          * that we can at least receive multicast traffic
3583                          */
3584                         hw->mac.ops.update_mc_addr_list(hw, netdev);
3585                         vmolr |= IXGBE_VMOLR_ROMPE;
3586                 }
3587                 ixgbe_vlan_filter_enable(adapter);
3588                 hw->addr_ctrl.user_set_promisc = false;
3589                 /*
3590                  * Write addresses to available RAR registers, if there is not
3591                  * sufficient space to store all the addresses then enable
3592                  * unicast promiscuous mode
3593                  */
3594                 count = ixgbe_write_uc_addr_list(netdev);
3595                 if (count < 0) {
3596                         fctrl |= IXGBE_FCTRL_UPE;
3597                         vmolr |= IXGBE_VMOLR_ROPE;
3598                 }
3599         }
3600
3601         if (adapter->num_vfs) {
3602                 ixgbe_restore_vf_multicasts(adapter);
3603                 vmolr |= IXGBE_READ_REG(hw, IXGBE_VMOLR(adapter->num_vfs)) &
3604                          ~(IXGBE_VMOLR_MPE | IXGBE_VMOLR_ROMPE |
3605                            IXGBE_VMOLR_ROPE);
3606                 IXGBE_WRITE_REG(hw, IXGBE_VMOLR(adapter->num_vfs), vmolr);
3607         }
3608
3609         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
3610
3611         if (netdev->features & NETIF_F_HW_VLAN_RX)
3612                 ixgbe_vlan_strip_enable(adapter);
3613         else
3614                 ixgbe_vlan_strip_disable(adapter);
3615 }
3616
3617 static void ixgbe_napi_enable_all(struct ixgbe_adapter *adapter)
3618 {
3619         int q_idx;
3620         struct ixgbe_q_vector *q_vector;
3621         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3622
3623         /* legacy and MSI only use one vector */
3624         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3625                 q_vectors = 1;
3626
3627         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3628                 struct napi_struct *napi;
3629                 q_vector = adapter->q_vector[q_idx];
3630                 napi = &q_vector->napi;
3631                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3632                         if (!q_vector->rxr_count || !q_vector->txr_count) {
3633                                 if (q_vector->txr_count == 1)
3634                                         napi->poll = &ixgbe_clean_txonly;
3635                                 else if (q_vector->rxr_count == 1)
3636                                         napi->poll = &ixgbe_clean_rxonly;
3637                         }
3638                 }
3639
3640                 napi_enable(napi);
3641         }
3642 }
3643
3644 static void ixgbe_napi_disable_all(struct ixgbe_adapter *adapter)
3645 {
3646         int q_idx;
3647         struct ixgbe_q_vector *q_vector;
3648         int q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
3649
3650         /* legacy and MSI only use one vector */
3651         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED))
3652                 q_vectors = 1;
3653
3654         for (q_idx = 0; q_idx < q_vectors; q_idx++) {
3655                 q_vector = adapter->q_vector[q_idx];
3656                 napi_disable(&q_vector->napi);
3657         }
3658 }
3659
3660 #ifdef CONFIG_IXGBE_DCB
3661 /*
3662  * ixgbe_configure_dcb - Configure DCB hardware
3663  * @adapter: ixgbe adapter struct
3664  *
3665  * This is called by the driver on open to configure the DCB hardware.
3666  * This is also called by the gennetlink interface when reconfiguring
3667  * the DCB state.
3668  */
3669 static void ixgbe_configure_dcb(struct ixgbe_adapter *adapter)
3670 {
3671         struct ixgbe_hw *hw = &adapter->hw;
3672         int max_frame = adapter->netdev->mtu + ETH_HLEN + ETH_FCS_LEN;
3673
3674         if (!(adapter->flags & IXGBE_FLAG_DCB_ENABLED)) {
3675                 if (hw->mac.type == ixgbe_mac_82598EB)
3676                         netif_set_gso_max_size(adapter->netdev, 65536);
3677                 return;
3678         }
3679
3680         if (hw->mac.type == ixgbe_mac_82598EB)
3681                 netif_set_gso_max_size(adapter->netdev, 32768);
3682
3683
3684         /* Enable VLAN tag insert/strip */
3685         adapter->netdev->features |= NETIF_F_HW_VLAN_RX;
3686
3687         hw->mac.ops.set_vfta(&adapter->hw, 0, 0, true);
3688
3689         /* reconfigure the hardware */
3690         if (adapter->dcbx_cap & DCB_CAP_DCBX_VER_CEE) {
3691 #ifdef CONFIG_FCOE
3692                 if (adapter->netdev->features & NETIF_F_FCOE_MTU)
3693                         max_frame = max(max_frame, IXGBE_FCOE_JUMBO_FRAME_SIZE);
3694 #endif
3695                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3696                                                 DCB_TX_CONFIG);
3697                 ixgbe_dcb_calculate_tc_credits(hw, &adapter->dcb_cfg, max_frame,
3698                                                 DCB_RX_CONFIG);
3699                 ixgbe_dcb_hw_config(hw, &adapter->dcb_cfg);
3700         } else {
3701                 struct net_device *dev = adapter->netdev;
3702
3703                 if (adapter->ixgbe_ieee_ets)
3704                         dev->dcbnl_ops->ieee_setets(dev,
3705                                                     adapter->ixgbe_ieee_ets);
3706                 if (adapter->ixgbe_ieee_pfc)
3707                         dev->dcbnl_ops->ieee_setpfc(dev,
3708                                                     adapter->ixgbe_ieee_pfc);
3709         }
3710
3711         /* Enable RSS Hash per TC */
3712         if (hw->mac.type != ixgbe_mac_82598EB) {
3713                 int i;
3714                 u32 reg = 0;
3715
3716                 for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
3717                         u8 msb = 0;
3718                         u8 cnt = adapter->netdev->tc_to_txq[i].count;
3719
3720                         while (cnt >>= 1)
3721                                 msb++;
3722
3723                         reg |= msb << IXGBE_RQTC_SHIFT_TC(i);
3724                 }
3725                 IXGBE_WRITE_REG(hw, IXGBE_RQTC, reg);
3726         }
3727 }
3728
3729 #endif
3730
3731 static void ixgbe_configure_pb(struct ixgbe_adapter *adapter)
3732 {
3733         int hdrm = 0;
3734         int num_tc = netdev_get_num_tc(adapter->netdev);
3735         struct ixgbe_hw *hw = &adapter->hw;
3736
3737         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE ||
3738             adapter->flags & IXGBE_FLAG_FDIR_PERFECT_CAPABLE)
3739                 hdrm = 64 << adapter->fdir_pballoc;
3740
3741         hw->mac.ops.set_rxpba(&adapter->hw, num_tc, hdrm, PBA_STRATEGY_EQUAL);
3742 }
3743
3744 static void ixgbe_configure(struct ixgbe_adapter *adapter)
3745 {
3746         struct net_device *netdev = adapter->netdev;
3747         struct ixgbe_hw *hw = &adapter->hw;
3748         int i;
3749
3750         ixgbe_configure_pb(adapter);
3751 #ifdef CONFIG_IXGBE_DCB
3752         ixgbe_configure_dcb(adapter);
3753 #endif
3754
3755         ixgbe_set_rx_mode(netdev);
3756         ixgbe_restore_vlan(adapter);
3757
3758 #ifdef IXGBE_FCOE
3759         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
3760                 ixgbe_configure_fcoe(adapter);
3761
3762 #endif /* IXGBE_FCOE */
3763         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
3764                 for (i = 0; i < adapter->num_tx_queues; i++)
3765                         adapter->tx_ring[i]->atr_sample_rate =
3766                                                        adapter->atr_sample_rate;
3767                 ixgbe_init_fdir_signature_82599(hw, adapter->fdir_pballoc);
3768         }
3769         ixgbe_configure_virtualization(adapter);
3770
3771         ixgbe_configure_tx(adapter);
3772         ixgbe_configure_rx(adapter);
3773 }
3774
3775 static inline bool ixgbe_is_sfp(struct ixgbe_hw *hw)
3776 {
3777         switch (hw->phy.type) {
3778         case ixgbe_phy_sfp_avago:
3779         case ixgbe_phy_sfp_ftl:
3780         case ixgbe_phy_sfp_intel:
3781         case ixgbe_phy_sfp_unknown:
3782         case ixgbe_phy_sfp_passive_tyco:
3783         case ixgbe_phy_sfp_passive_unknown:
3784         case ixgbe_phy_sfp_active_unknown:
3785         case ixgbe_phy_sfp_ftl_active:
3786                 return true;
3787         default:
3788                 return false;
3789         }
3790 }
3791
3792 /**
3793  * ixgbe_sfp_link_config - set up SFP+ link
3794  * @adapter: pointer to private adapter struct
3795  **/
3796 static void ixgbe_sfp_link_config(struct ixgbe_adapter *adapter)
3797 {
3798         /*
3799          * We are assuming the worst case scenerio here, and that
3800          * is that an SFP was inserted/removed after the reset
3801          * but before SFP detection was enabled.  As such the best
3802          * solution is to just start searching as soon as we start
3803          */
3804         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
3805                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
3806
3807         adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
3808 }
3809
3810 /**
3811  * ixgbe_non_sfp_link_config - set up non-SFP+ link
3812  * @hw: pointer to private hardware struct
3813  *
3814  * Returns 0 on success, negative on failure
3815  **/
3816 static int ixgbe_non_sfp_link_config(struct ixgbe_hw *hw)
3817 {
3818         u32 autoneg;
3819         bool negotiation, link_up = false;
3820         u32 ret = IXGBE_ERR_LINK_SETUP;
3821
3822         if (hw->mac.ops.check_link)
3823                 ret = hw->mac.ops.check_link(hw, &autoneg, &link_up, false);
3824
3825         if (ret)
3826                 goto link_cfg_out;
3827
3828         autoneg = hw->phy.autoneg_advertised;
3829         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
3830                 ret = hw->mac.ops.get_link_capabilities(hw, &autoneg,
3831                                                         &negotiation);
3832         if (ret)
3833                 goto link_cfg_out;
3834
3835         if (hw->mac.ops.setup_link)
3836                 ret = hw->mac.ops.setup_link(hw, autoneg, negotiation, link_up);
3837 link_cfg_out:
3838         return ret;
3839 }
3840
3841 static void ixgbe_setup_gpie(struct ixgbe_adapter *adapter)
3842 {
3843         struct ixgbe_hw *hw = &adapter->hw;
3844         u32 gpie = 0;
3845
3846         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
3847                 gpie = IXGBE_GPIE_MSIX_MODE | IXGBE_GPIE_PBA_SUPPORT |
3848                        IXGBE_GPIE_OCD;
3849                 gpie |= IXGBE_GPIE_EIAME;
3850                 /*
3851                  * use EIAM to auto-mask when MSI-X interrupt is asserted
3852                  * this saves a register write for every interrupt
3853                  */
3854                 switch (hw->mac.type) {
3855                 case ixgbe_mac_82598EB:
3856                         IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3857                         break;
3858                 case ixgbe_mac_82599EB:
3859                 case ixgbe_mac_X540:
3860                 default:
3861                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(0), 0xFFFFFFFF);
3862                         IXGBE_WRITE_REG(hw, IXGBE_EIAM_EX(1), 0xFFFFFFFF);
3863                         break;
3864                 }
3865         } else {
3866                 /* legacy interrupts, use EIAM to auto-mask when reading EICR,
3867                  * specifically only auto mask tx and rx interrupts */
3868                 IXGBE_WRITE_REG(hw, IXGBE_EIAM, IXGBE_EICS_RTX_QUEUE);
3869         }
3870
3871         /* XXX: to interrupt immediately for EICS writes, enable this */
3872         /* gpie |= IXGBE_GPIE_EIMEN; */
3873
3874         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
3875                 gpie &= ~IXGBE_GPIE_VTMODE_MASK;
3876                 gpie |= IXGBE_GPIE_VTMODE_64;
3877         }
3878
3879         /* Enable fan failure interrupt */
3880         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE)
3881                 gpie |= IXGBE_SDP1_GPIEN;
3882
3883         if (hw->mac.type == ixgbe_mac_82599EB) {
3884                 gpie |= IXGBE_SDP1_GPIEN;
3885                 gpie |= IXGBE_SDP2_GPIEN;
3886         }
3887
3888         IXGBE_WRITE_REG(hw, IXGBE_GPIE, gpie);
3889 }
3890
3891 static int ixgbe_up_complete(struct ixgbe_adapter *adapter)
3892 {
3893         struct ixgbe_hw *hw = &adapter->hw;
3894         int err;
3895         u32 ctrl_ext;
3896
3897         ixgbe_get_hw_control(adapter);
3898         ixgbe_setup_gpie(adapter);
3899
3900         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
3901                 ixgbe_configure_msix(adapter);
3902         else
3903                 ixgbe_configure_msi_and_legacy(adapter);
3904
3905         /* enable the optics for both mult-speed fiber and 82599 SFP+ fiber */
3906         if (hw->mac.ops.enable_tx_laser &&
3907             ((hw->phy.multispeed_fiber) ||
3908              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
3909               (hw->mac.type == ixgbe_mac_82599EB))))
3910                 hw->mac.ops.enable_tx_laser(hw);
3911
3912         clear_bit(__IXGBE_DOWN, &adapter->state);
3913         ixgbe_napi_enable_all(adapter);
3914
3915         if (ixgbe_is_sfp(hw)) {
3916                 ixgbe_sfp_link_config(adapter);
3917         } else {
3918                 err = ixgbe_non_sfp_link_config(hw);
3919                 if (err)
3920                         e_err(probe, "link_config FAILED %d\n", err);
3921         }
3922
3923         /* clear any pending interrupts, may auto mask */
3924         IXGBE_READ_REG(hw, IXGBE_EICR);
3925         ixgbe_irq_enable(adapter, true, true);
3926
3927         /*
3928          * If this adapter has a fan, check to see if we had a failure
3929          * before we enabled the interrupt.
3930          */
3931         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
3932                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
3933                 if (esdp & IXGBE_ESDP_SDP1)
3934                         e_crit(drv, "Fan has stopped, replace the adapter\n");
3935         }
3936
3937         /* enable transmits */
3938         netif_tx_start_all_queues(adapter->netdev);
3939
3940         /* bring the link up in the watchdog, this could race with our first
3941          * link up interrupt but shouldn't be a problem */
3942         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
3943         adapter->link_check_timeout = jiffies;
3944         mod_timer(&adapter->service_timer, jiffies);
3945
3946         /* Set PF Reset Done bit so PF/VF Mail Ops can work */
3947         ctrl_ext = IXGBE_READ_REG(hw, IXGBE_CTRL_EXT);
3948         ctrl_ext |= IXGBE_CTRL_EXT_PFRSTD;
3949         IXGBE_WRITE_REG(hw, IXGBE_CTRL_EXT, ctrl_ext);
3950
3951         return 0;
3952 }
3953
3954 void ixgbe_reinit_locked(struct ixgbe_adapter *adapter)
3955 {
3956         WARN_ON(in_interrupt());
3957         /* put off any impending NetWatchDogTimeout */
3958         adapter->netdev->trans_start = jiffies;
3959
3960         while (test_and_set_bit(__IXGBE_RESETTING, &adapter->state))
3961                 usleep_range(1000, 2000);
3962         ixgbe_down(adapter);
3963         /*
3964          * If SR-IOV enabled then wait a bit before bringing the adapter
3965          * back up to give the VFs time to respond to the reset.  The
3966          * two second wait is based upon the watchdog timer cycle in
3967          * the VF driver.
3968          */
3969         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
3970                 msleep(2000);
3971         ixgbe_up(adapter);
3972         clear_bit(__IXGBE_RESETTING, &adapter->state);
3973 }
3974
3975 int ixgbe_up(struct ixgbe_adapter *adapter)
3976 {
3977         /* hardware has been reset, we need to reload some things */
3978         ixgbe_configure(adapter);
3979
3980         return ixgbe_up_complete(adapter);
3981 }
3982
3983 void ixgbe_reset(struct ixgbe_adapter *adapter)
3984 {
3985         struct ixgbe_hw *hw = &adapter->hw;
3986         int err;
3987
3988         /* lock SFP init bit to prevent race conditions with the watchdog */
3989         while (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
3990                 usleep_range(1000, 2000);
3991
3992         /* clear all SFP and link config related flags while holding SFP_INIT */
3993         adapter->flags2 &= ~(IXGBE_FLAG2_SEARCH_FOR_SFP |
3994                              IXGBE_FLAG2_SFP_NEEDS_RESET);
3995         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
3996
3997         err = hw->mac.ops.init_hw(hw);
3998         switch (err) {
3999         case 0:
4000         case IXGBE_ERR_SFP_NOT_PRESENT:
4001         case IXGBE_ERR_SFP_NOT_SUPPORTED:
4002                 break;
4003         case IXGBE_ERR_MASTER_REQUESTS_PENDING:
4004                 e_dev_err("master disable timed out\n");
4005                 break;
4006         case IXGBE_ERR_EEPROM_VERSION:
4007                 /* We are running on a pre-production device, log a warning */
4008                 e_dev_warn("This device is a pre-production adapter/LOM. "
4009                            "Please be aware there may be issuesassociated with "
4010                            "your hardware.  If you are experiencing problems "
4011                            "please contact your Intel or hardware "
4012                            "representative who provided you with this "
4013                            "hardware.\n");
4014                 break;
4015         default:
4016                 e_dev_err("Hardware Error: %d\n", err);
4017         }
4018
4019         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
4020
4021         /* reprogram the RAR[0] in case user changed it. */
4022         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
4023                             IXGBE_RAH_AV);
4024 }
4025
4026 /**
4027  * ixgbe_clean_rx_ring - Free Rx Buffers per Queue
4028  * @rx_ring: ring to free buffers from
4029  **/
4030 static void ixgbe_clean_rx_ring(struct ixgbe_ring *rx_ring)
4031 {
4032         struct device *dev = rx_ring->dev;
4033         unsigned long size;
4034         u16 i;
4035
4036         /* ring already cleared, nothing to do */
4037         if (!rx_ring->rx_buffer_info)
4038                 return;
4039
4040         /* Free all the Rx ring sk_buffs */
4041         for (i = 0; i < rx_ring->count; i++) {
4042                 struct ixgbe_rx_buffer *rx_buffer_info;
4043
4044                 rx_buffer_info = &rx_ring->rx_buffer_info[i];
4045                 if (rx_buffer_info->dma) {
4046                         dma_unmap_single(rx_ring->dev, rx_buffer_info->dma,
4047                                          rx_ring->rx_buf_len,
4048                                          DMA_FROM_DEVICE);
4049                         rx_buffer_info->dma = 0;
4050                 }
4051                 if (rx_buffer_info->skb) {
4052                         struct sk_buff *skb = rx_buffer_info->skb;
4053                         rx_buffer_info->skb = NULL;
4054                         do {
4055                                 struct sk_buff *this = skb;
4056                                 if (IXGBE_RSC_CB(this)->delay_unmap) {
4057                                         dma_unmap_single(dev,
4058                                                          IXGBE_RSC_CB(this)->dma,
4059                                                          rx_ring->rx_buf_len,
4060                                                          DMA_FROM_DEVICE);
4061                                         IXGBE_RSC_CB(this)->dma = 0;
4062                                         IXGBE_RSC_CB(skb)->delay_unmap = false;
4063                                 }
4064                                 skb = skb->prev;
4065                                 dev_kfree_skb(this);
4066                         } while (skb);
4067                 }
4068                 if (!rx_buffer_info->page)
4069                         continue;
4070                 if (rx_buffer_info->page_dma) {
4071                         dma_unmap_page(dev, rx_buffer_info->page_dma,
4072                                        PAGE_SIZE / 2, DMA_FROM_DEVICE);
4073                         rx_buffer_info->page_dma = 0;
4074                 }
4075                 put_page(rx_buffer_info->page);
4076                 rx_buffer_info->page = NULL;
4077                 rx_buffer_info->page_offset = 0;
4078         }
4079
4080         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
4081         memset(rx_ring->rx_buffer_info, 0, size);
4082
4083         /* Zero out the descriptor ring */
4084         memset(rx_ring->desc, 0, rx_ring->size);
4085
4086         rx_ring->next_to_clean = 0;
4087         rx_ring->next_to_use = 0;
4088 }
4089
4090 /**
4091  * ixgbe_clean_tx_ring - Free Tx Buffers
4092  * @tx_ring: ring to be cleaned
4093  **/
4094 static void ixgbe_clean_tx_ring(struct ixgbe_ring *tx_ring)
4095 {
4096         struct ixgbe_tx_buffer *tx_buffer_info;
4097         unsigned long size;
4098         u16 i;
4099
4100         /* ring already cleared, nothing to do */
4101         if (!tx_ring->tx_buffer_info)
4102                 return;
4103
4104         /* Free all the Tx ring sk_buffs */
4105         for (i = 0; i < tx_ring->count; i++) {
4106                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
4107                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
4108         }
4109
4110         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
4111         memset(tx_ring->tx_buffer_info, 0, size);
4112
4113         /* Zero out the descriptor ring */
4114         memset(tx_ring->desc, 0, tx_ring->size);
4115
4116         tx_ring->next_to_use = 0;
4117         tx_ring->next_to_clean = 0;
4118 }
4119
4120 /**
4121  * ixgbe_clean_all_rx_rings - Free Rx Buffers for all queues
4122  * @adapter: board private structure
4123  **/
4124 static void ixgbe_clean_all_rx_rings(struct ixgbe_adapter *adapter)
4125 {
4126         int i;
4127
4128         for (i = 0; i < adapter->num_rx_queues; i++)
4129                 ixgbe_clean_rx_ring(adapter->rx_ring[i]);
4130 }
4131
4132 /**
4133  * ixgbe_clean_all_tx_rings - Free Tx Buffers for all queues
4134  * @adapter: board private structure
4135  **/
4136 static void ixgbe_clean_all_tx_rings(struct ixgbe_adapter *adapter)
4137 {
4138         int i;
4139
4140         for (i = 0; i < adapter->num_tx_queues; i++)
4141                 ixgbe_clean_tx_ring(adapter->tx_ring[i]);
4142 }
4143
4144 void ixgbe_down(struct ixgbe_adapter *adapter)
4145 {
4146         struct net_device *netdev = adapter->netdev;
4147         struct ixgbe_hw *hw = &adapter->hw;
4148         u32 rxctrl;
4149         int i;
4150         int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4151
4152         /* signal that we are down to the interrupt handler */
4153         set_bit(__IXGBE_DOWN, &adapter->state);
4154
4155         /* disable receives */
4156         rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL);
4157         IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl & ~IXGBE_RXCTRL_RXEN);
4158
4159         /* disable all enabled rx queues */
4160         for (i = 0; i < adapter->num_rx_queues; i++)
4161                 /* this call also flushes the previous write */
4162                 ixgbe_disable_rx_queue(adapter, adapter->rx_ring[i]);
4163
4164         usleep_range(10000, 20000);
4165
4166         netif_tx_stop_all_queues(netdev);
4167
4168         /* call carrier off first to avoid false dev_watchdog timeouts */
4169         netif_carrier_off(netdev);
4170         netif_tx_disable(netdev);
4171
4172         ixgbe_irq_disable(adapter);
4173
4174         ixgbe_napi_disable_all(adapter);
4175
4176         adapter->flags2 &= ~(IXGBE_FLAG2_FDIR_REQUIRES_REINIT |
4177                              IXGBE_FLAG2_RESET_REQUESTED);
4178         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
4179
4180         del_timer_sync(&adapter->service_timer);
4181
4182         /* disable receive for all VFs and wait one second */
4183         if (adapter->num_vfs) {
4184                 /* ping all the active vfs to let them know we are going down */
4185                 ixgbe_ping_all_vfs(adapter);
4186
4187                 /* Disable all VFTE/VFRE TX/RX */
4188                 ixgbe_disable_tx_rx(adapter);
4189
4190                 /* Mark all the VFs as inactive */
4191                 for (i = 0 ; i < adapter->num_vfs; i++)
4192                         adapter->vfinfo[i].clear_to_send = 0;
4193         }
4194
4195         /* Cleanup the affinity_hint CPU mask memory and callback */
4196         for (i = 0; i < num_q_vectors; i++) {
4197                 struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
4198                 /* clear the affinity_mask in the IRQ descriptor */
4199                 irq_set_affinity_hint(adapter->msix_entries[i]. vector, NULL);
4200                 /* release the CPU mask memory */
4201                 free_cpumask_var(q_vector->affinity_mask);
4202         }
4203
4204         /* disable transmits in the hardware now that interrupts are off */
4205         for (i = 0; i < adapter->num_tx_queues; i++) {
4206                 u8 reg_idx = adapter->tx_ring[i]->reg_idx;
4207                 IXGBE_WRITE_REG(hw, IXGBE_TXDCTL(reg_idx), IXGBE_TXDCTL_SWFLSH);
4208         }
4209
4210         /* Disable the Tx DMA engine on 82599 and X540 */
4211         switch (hw->mac.type) {
4212         case ixgbe_mac_82599EB:
4213         case ixgbe_mac_X540:
4214                 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL,
4215                                 (IXGBE_READ_REG(hw, IXGBE_DMATXCTL) &
4216                                  ~IXGBE_DMATXCTL_TE));
4217                 break;
4218         default:
4219                 break;
4220         }
4221
4222         if (!pci_channel_offline(adapter->pdev))
4223                 ixgbe_reset(adapter);
4224
4225         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
4226         if (hw->mac.ops.disable_tx_laser &&
4227             ((hw->phy.multispeed_fiber) ||
4228              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
4229               (hw->mac.type == ixgbe_mac_82599EB))))
4230                 hw->mac.ops.disable_tx_laser(hw);
4231
4232         ixgbe_clean_all_tx_rings(adapter);
4233         ixgbe_clean_all_rx_rings(adapter);
4234
4235 #ifdef CONFIG_IXGBE_DCA
4236         /* since we reset the hardware DCA settings were cleared */
4237         ixgbe_setup_dca(adapter);
4238 #endif
4239 }
4240
4241 /**
4242  * ixgbe_poll - NAPI Rx polling callback
4243  * @napi: structure for representing this polling device
4244  * @budget: how many packets driver is allowed to clean
4245  *
4246  * This function is used for legacy and MSI, NAPI mode
4247  **/
4248 static int ixgbe_poll(struct napi_struct *napi, int budget)
4249 {
4250         struct ixgbe_q_vector *q_vector =
4251                                 container_of(napi, struct ixgbe_q_vector, napi);
4252         struct ixgbe_adapter *adapter = q_vector->adapter;
4253         int tx_clean_complete, work_done = 0;
4254
4255 #ifdef CONFIG_IXGBE_DCA
4256         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED)
4257                 ixgbe_update_dca(q_vector);
4258 #endif
4259
4260         tx_clean_complete = ixgbe_clean_tx_irq(q_vector, adapter->tx_ring[0]);
4261         ixgbe_clean_rx_irq(q_vector, adapter->rx_ring[0], &work_done, budget);
4262
4263         if (!tx_clean_complete)
4264                 work_done = budget;
4265
4266         /* If budget not fully consumed, exit the polling mode */
4267         if (work_done < budget) {
4268                 napi_complete(napi);
4269                 if (adapter->rx_itr_setting & 1)
4270                         ixgbe_set_itr(adapter);
4271                 if (!test_bit(__IXGBE_DOWN, &adapter->state))
4272                         ixgbe_irq_enable_queues(adapter, IXGBE_EIMS_RTX_QUEUE);
4273         }
4274         return work_done;
4275 }
4276
4277 /**
4278  * ixgbe_tx_timeout - Respond to a Tx Hang
4279  * @netdev: network interface device structure
4280  **/
4281 static void ixgbe_tx_timeout(struct net_device *netdev)
4282 {
4283         struct ixgbe_adapter *adapter = netdev_priv(netdev);
4284
4285         /* Do the reset outside of interrupt context */
4286         ixgbe_tx_timeout_reset(adapter);
4287 }
4288
4289 /**
4290  * ixgbe_set_rss_queues: Allocate queues for RSS
4291  * @adapter: board private structure to initialize
4292  *
4293  * This is our "base" multiqueue mode.  RSS (Receive Side Scaling) will try
4294  * to allocate one Rx queue per CPU, and if available, one Tx queue per CPU.
4295  *
4296  **/
4297 static inline bool ixgbe_set_rss_queues(struct ixgbe_adapter *adapter)
4298 {
4299         bool ret = false;
4300         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_RSS];
4301
4302         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4303                 f->mask = 0xF;
4304                 adapter->num_rx_queues = f->indices;
4305                 adapter->num_tx_queues = f->indices;
4306                 ret = true;
4307         } else {
4308                 ret = false;
4309         }
4310
4311         return ret;
4312 }
4313
4314 /**
4315  * ixgbe_set_fdir_queues: Allocate queues for Flow Director
4316  * @adapter: board private structure to initialize
4317  *
4318  * Flow Director is an advanced Rx filter, attempting to get Rx flows back
4319  * to the original CPU that initiated the Tx session.  This runs in addition
4320  * to RSS, so if a packet doesn't match an FDIR filter, we can still spread the
4321  * Rx load across CPUs using RSS.
4322  *
4323  **/
4324 static inline bool ixgbe_set_fdir_queues(struct ixgbe_adapter *adapter)
4325 {
4326         bool ret = false;
4327         struct ixgbe_ring_feature *f_fdir = &adapter->ring_feature[RING_F_FDIR];
4328
4329         f_fdir->indices = min((int)num_online_cpus(), f_fdir->indices);
4330         f_fdir->mask = 0;
4331
4332         /* Flow Director must have RSS enabled */
4333         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4334             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4335                 adapter->num_tx_queues = f_fdir->indices;
4336                 adapter->num_rx_queues = f_fdir->indices;
4337                 ret = true;
4338         } else {
4339                 adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4340         }
4341         return ret;
4342 }
4343
4344 #ifdef IXGBE_FCOE
4345 /**
4346  * ixgbe_set_fcoe_queues: Allocate queues for Fiber Channel over Ethernet (FCoE)
4347  * @adapter: board private structure to initialize
4348  *
4349  * FCoE RX FCRETA can use up to 8 rx queues for up to 8 different exchanges.
4350  * The ring feature mask is not used as a mask for FCoE, as it can take any 8
4351  * rx queues out of the max number of rx queues, instead, it is used as the
4352  * index of the first rx queue used by FCoE.
4353  *
4354  **/
4355 static inline bool ixgbe_set_fcoe_queues(struct ixgbe_adapter *adapter)
4356 {
4357         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4358
4359         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4360                 return false;
4361
4362         f->indices = min((int)num_online_cpus(), f->indices);
4363
4364         adapter->num_rx_queues = 1;
4365         adapter->num_tx_queues = 1;
4366
4367         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4368                 e_info(probe, "FCoE enabled with RSS\n");
4369                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4370                         ixgbe_set_fdir_queues(adapter);
4371                 else
4372                         ixgbe_set_rss_queues(adapter);
4373         }
4374
4375         /* adding FCoE rx rings to the end */
4376         f->mask = adapter->num_rx_queues;
4377         adapter->num_rx_queues += f->indices;
4378         adapter->num_tx_queues += f->indices;
4379
4380         return true;
4381 }
4382 #endif /* IXGBE_FCOE */
4383
4384 /* Artificial max queue cap per traffic class in DCB mode */
4385 #define DCB_QUEUE_CAP 8
4386
4387 #ifdef CONFIG_IXGBE_DCB
4388 static inline bool ixgbe_set_dcb_queues(struct ixgbe_adapter *adapter)
4389 {
4390         int per_tc_q, q, i, offset = 0;
4391         struct net_device *dev = adapter->netdev;
4392         int tcs = netdev_get_num_tc(dev);
4393
4394         if (!tcs)
4395                 return false;
4396
4397         /* Map queue offset and counts onto allocated tx queues */
4398         per_tc_q = min(dev->num_tx_queues / tcs, (unsigned int)DCB_QUEUE_CAP);
4399         q = min((int)num_online_cpus(), per_tc_q);
4400
4401         for (i = 0; i < tcs; i++) {
4402                 netdev_set_prio_tc_map(dev, i, i);
4403                 netdev_set_tc_queue(dev, i, q, offset);
4404                 offset += q;
4405         }
4406
4407         adapter->num_tx_queues = q * tcs;
4408         adapter->num_rx_queues = q * tcs;
4409
4410 #ifdef IXGBE_FCOE
4411         /* FCoE enabled queues require special configuration indexed
4412          * by feature specific indices and mask. Here we map FCoE
4413          * indices onto the DCB queue pairs allowing FCoE to own
4414          * configuration later.
4415          */
4416         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED) {
4417                 int tc;
4418                 struct ixgbe_ring_feature *f =
4419                                         &adapter->ring_feature[RING_F_FCOE];
4420
4421                 tc = netdev_get_prio_tc_map(dev, adapter->fcoe.up);
4422                 f->indices = dev->tc_to_txq[tc].count;
4423                 f->mask = dev->tc_to_txq[tc].offset;
4424         }
4425 #endif
4426
4427         return true;
4428 }
4429 #endif
4430
4431 /**
4432  * ixgbe_set_sriov_queues: Allocate queues for IOV use
4433  * @adapter: board private structure to initialize
4434  *
4435  * IOV doesn't actually use anything, so just NAK the
4436  * request for now and let the other queue routines
4437  * figure out what to do.
4438  */
4439 static inline bool ixgbe_set_sriov_queues(struct ixgbe_adapter *adapter)
4440 {
4441         return false;
4442 }
4443
4444 /*
4445  * ixgbe_set_num_queues: Allocate queues for device, feature dependent
4446  * @adapter: board private structure to initialize
4447  *
4448  * This is the top level queue allocation routine.  The order here is very
4449  * important, starting with the "most" number of features turned on at once,
4450  * and ending with the smallest set of features.  This way large combinations
4451  * can be allocated if they're turned on, and smaller combinations are the
4452  * fallthrough conditions.
4453  *
4454  **/
4455 static int ixgbe_set_num_queues(struct ixgbe_adapter *adapter)
4456 {
4457         /* Start with base case */
4458         adapter->num_rx_queues = 1;
4459         adapter->num_tx_queues = 1;
4460         adapter->num_rx_pools = adapter->num_rx_queues;
4461         adapter->num_rx_queues_per_pool = 1;
4462
4463         if (ixgbe_set_sriov_queues(adapter))
4464                 goto done;
4465
4466 #ifdef CONFIG_IXGBE_DCB
4467         if (ixgbe_set_dcb_queues(adapter))
4468                 goto done;
4469
4470 #endif
4471 #ifdef IXGBE_FCOE
4472         if (ixgbe_set_fcoe_queues(adapter))
4473                 goto done;
4474
4475 #endif /* IXGBE_FCOE */
4476         if (ixgbe_set_fdir_queues(adapter))
4477                 goto done;
4478
4479         if (ixgbe_set_rss_queues(adapter))
4480                 goto done;
4481
4482         /* fallback to base case */
4483         adapter->num_rx_queues = 1;
4484         adapter->num_tx_queues = 1;
4485
4486 done:
4487         /* Notify the stack of the (possibly) reduced queue counts. */
4488         netif_set_real_num_tx_queues(adapter->netdev, adapter->num_tx_queues);
4489         return netif_set_real_num_rx_queues(adapter->netdev,
4490                                             adapter->num_rx_queues);
4491 }
4492
4493 static void ixgbe_acquire_msix_vectors(struct ixgbe_adapter *adapter,
4494                                        int vectors)
4495 {
4496         int err, vector_threshold;
4497
4498         /* We'll want at least 3 (vector_threshold):
4499          * 1) TxQ[0] Cleanup
4500          * 2) RxQ[0] Cleanup
4501          * 3) Other (Link Status Change, etc.)
4502          * 4) TCP Timer (optional)
4503          */
4504         vector_threshold = MIN_MSIX_COUNT;
4505
4506         /* The more we get, the more we will assign to Tx/Rx Cleanup
4507          * for the separate queues...where Rx Cleanup >= Tx Cleanup.
4508          * Right now, we simply care about how many we'll get; we'll
4509          * set them up later while requesting irq's.
4510          */
4511         while (vectors >= vector_threshold) {
4512                 err = pci_enable_msix(adapter->pdev, adapter->msix_entries,
4513                                       vectors);
4514                 if (!err) /* Success in acquiring all requested vectors. */
4515                         break;
4516                 else if (err < 0)
4517                         vectors = 0; /* Nasty failure, quit now */
4518                 else /* err == number of vectors we should try again with */
4519                         vectors = err;
4520         }
4521
4522         if (vectors < vector_threshold) {
4523                 /* Can't allocate enough MSI-X interrupts?  Oh well.
4524                  * This just means we'll go with either a single MSI
4525                  * vector or fall back to legacy interrupts.
4526                  */
4527                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4528                              "Unable to allocate MSI-X interrupts\n");
4529                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4530                 kfree(adapter->msix_entries);
4531                 adapter->msix_entries = NULL;
4532         } else {
4533                 adapter->flags |= IXGBE_FLAG_MSIX_ENABLED; /* Woot! */
4534                 /*
4535                  * Adjust for only the vectors we'll use, which is minimum
4536                  * of max_msix_q_vectors + NON_Q_VECTORS, or the number of
4537                  * vectors we were allocated.
4538                  */
4539                 adapter->num_msix_vectors = min(vectors,
4540                                    adapter->max_msix_q_vectors + NON_Q_VECTORS);
4541         }
4542 }
4543
4544 /**
4545  * ixgbe_cache_ring_rss - Descriptor ring to register mapping for RSS
4546  * @adapter: board private structure to initialize
4547  *
4548  * Cache the descriptor ring offsets for RSS to the assigned rings.
4549  *
4550  **/
4551 static inline bool ixgbe_cache_ring_rss(struct ixgbe_adapter *adapter)
4552 {
4553         int i;
4554
4555         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
4556                 return false;
4557
4558         for (i = 0; i < adapter->num_rx_queues; i++)
4559                 adapter->rx_ring[i]->reg_idx = i;
4560         for (i = 0; i < adapter->num_tx_queues; i++)
4561                 adapter->tx_ring[i]->reg_idx = i;
4562
4563         return true;
4564 }
4565
4566 #ifdef CONFIG_IXGBE_DCB
4567
4568 /* ixgbe_get_first_reg_idx - Return first register index associated with ring */
4569 static void ixgbe_get_first_reg_idx(struct ixgbe_adapter *adapter, u8 tc,
4570                                     unsigned int *tx, unsigned int *rx)
4571 {
4572         struct net_device *dev = adapter->netdev;
4573         struct ixgbe_hw *hw = &adapter->hw;
4574         u8 num_tcs = netdev_get_num_tc(dev);
4575
4576         *tx = 0;
4577         *rx = 0;
4578
4579         switch (hw->mac.type) {
4580         case ixgbe_mac_82598EB:
4581                 *tx = tc << 2;
4582                 *rx = tc << 3;
4583                 break;
4584         case ixgbe_mac_82599EB:
4585         case ixgbe_mac_X540:
4586                 if (num_tcs == 8) {
4587                         if (tc < 3) {
4588                                 *tx = tc << 5;
4589                                 *rx = tc << 4;
4590                         } else if (tc <  5) {
4591                                 *tx = ((tc + 2) << 4);
4592                                 *rx = tc << 4;
4593                         } else if (tc < num_tcs) {
4594                                 *tx = ((tc + 8) << 3);
4595                                 *rx = tc << 4;
4596                         }
4597                 } else if (num_tcs == 4) {
4598                         *rx =  tc << 5;
4599                         switch (tc) {
4600                         case 0:
4601                                 *tx =  0;
4602                                 break;
4603                         case 1:
4604                                 *tx = 64;
4605                                 break;
4606                         case 2:
4607                                 *tx = 96;
4608                                 break;
4609                         case 3:
4610                                 *tx = 112;
4611                                 break;
4612                         default:
4613                                 break;
4614                         }
4615                 }
4616                 break;
4617         default:
4618                 break;
4619         }
4620 }
4621
4622 /**
4623  * ixgbe_cache_ring_dcb - Descriptor ring to register mapping for DCB
4624  * @adapter: board private structure to initialize
4625  *
4626  * Cache the descriptor ring offsets for DCB to the assigned rings.
4627  *
4628  **/
4629 static inline bool ixgbe_cache_ring_dcb(struct ixgbe_adapter *adapter)
4630 {
4631         struct net_device *dev = adapter->netdev;
4632         int i, j, k;
4633         u8 num_tcs = netdev_get_num_tc(dev);
4634
4635         if (!num_tcs)
4636                 return false;
4637
4638         for (i = 0, k = 0; i < num_tcs; i++) {
4639                 unsigned int tx_s, rx_s;
4640                 u16 count = dev->tc_to_txq[i].count;
4641
4642                 ixgbe_get_first_reg_idx(adapter, i, &tx_s, &rx_s);
4643                 for (j = 0; j < count; j++, k++) {
4644                         adapter->tx_ring[k]->reg_idx = tx_s + j;
4645                         adapter->rx_ring[k]->reg_idx = rx_s + j;
4646                         adapter->tx_ring[k]->dcb_tc = i;
4647                         adapter->rx_ring[k]->dcb_tc = i;
4648                 }
4649         }
4650
4651         return true;
4652 }
4653 #endif
4654
4655 /**
4656  * ixgbe_cache_ring_fdir - Descriptor ring to register mapping for Flow Director
4657  * @adapter: board private structure to initialize
4658  *
4659  * Cache the descriptor ring offsets for Flow Director to the assigned rings.
4660  *
4661  **/
4662 static inline bool ixgbe_cache_ring_fdir(struct ixgbe_adapter *adapter)
4663 {
4664         int i;
4665         bool ret = false;
4666
4667         if ((adapter->flags & IXGBE_FLAG_RSS_ENABLED) &&
4668             (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)) {
4669                 for (i = 0; i < adapter->num_rx_queues; i++)
4670                         adapter->rx_ring[i]->reg_idx = i;
4671                 for (i = 0; i < adapter->num_tx_queues; i++)
4672                         adapter->tx_ring[i]->reg_idx = i;
4673                 ret = true;
4674         }
4675
4676         return ret;
4677 }
4678
4679 #ifdef IXGBE_FCOE
4680 /**
4681  * ixgbe_cache_ring_fcoe - Descriptor ring to register mapping for the FCoE
4682  * @adapter: board private structure to initialize
4683  *
4684  * Cache the descriptor ring offsets for FCoE mode to the assigned rings.
4685  *
4686  */
4687 static inline bool ixgbe_cache_ring_fcoe(struct ixgbe_adapter *adapter)
4688 {
4689         struct ixgbe_ring_feature *f = &adapter->ring_feature[RING_F_FCOE];
4690         int i;
4691         u8 fcoe_rx_i = 0, fcoe_tx_i = 0;
4692
4693         if (!(adapter->flags & IXGBE_FLAG_FCOE_ENABLED))
4694                 return false;
4695
4696         if (adapter->flags & IXGBE_FLAG_RSS_ENABLED) {
4697                 if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE)
4698                         ixgbe_cache_ring_fdir(adapter);
4699                 else
4700                         ixgbe_cache_ring_rss(adapter);
4701
4702                 fcoe_rx_i = f->mask;
4703                 fcoe_tx_i = f->mask;
4704         }
4705         for (i = 0; i < f->indices; i++, fcoe_rx_i++, fcoe_tx_i++) {
4706                 adapter->rx_ring[f->mask + i]->reg_idx = fcoe_rx_i;
4707                 adapter->tx_ring[f->mask + i]->reg_idx = fcoe_tx_i;
4708         }
4709         return true;
4710 }
4711
4712 #endif /* IXGBE_FCOE */
4713 /**
4714  * ixgbe_cache_ring_sriov - Descriptor ring to register mapping for sriov
4715  * @adapter: board private structure to initialize
4716  *
4717  * SR-IOV doesn't use any descriptor rings but changes the default if
4718  * no other mapping is used.
4719  *
4720  */
4721 static inline bool ixgbe_cache_ring_sriov(struct ixgbe_adapter *adapter)
4722 {
4723         adapter->rx_ring[0]->reg_idx = adapter->num_vfs * 2;
4724         adapter->tx_ring[0]->reg_idx = adapter->num_vfs * 2;
4725         if (adapter->num_vfs)
4726                 return true;
4727         else
4728                 return false;
4729 }
4730
4731 /**
4732  * ixgbe_cache_ring_register - Descriptor ring to register mapping
4733  * @adapter: board private structure to initialize
4734  *
4735  * Once we know the feature-set enabled for the device, we'll cache
4736  * the register offset the descriptor ring is assigned to.
4737  *
4738  * Note, the order the various feature calls is important.  It must start with
4739  * the "most" features enabled at the same time, then trickle down to the
4740  * least amount of features turned on at once.
4741  **/
4742 static void ixgbe_cache_ring_register(struct ixgbe_adapter *adapter)
4743 {
4744         /* start with default case */
4745         adapter->rx_ring[0]->reg_idx = 0;
4746         adapter->tx_ring[0]->reg_idx = 0;
4747
4748         if (ixgbe_cache_ring_sriov(adapter))
4749                 return;
4750
4751 #ifdef CONFIG_IXGBE_DCB
4752         if (ixgbe_cache_ring_dcb(adapter))
4753                 return;
4754 #endif
4755
4756 #ifdef IXGBE_FCOE
4757         if (ixgbe_cache_ring_fcoe(adapter))
4758                 return;
4759 #endif /* IXGBE_FCOE */
4760
4761         if (ixgbe_cache_ring_fdir(adapter))
4762                 return;
4763
4764         if (ixgbe_cache_ring_rss(adapter))
4765                 return;
4766 }
4767
4768 /**
4769  * ixgbe_alloc_queues - Allocate memory for all rings
4770  * @adapter: board private structure to initialize
4771  *
4772  * We allocate one ring per queue at run-time since we don't know the
4773  * number of queues at compile-time.  The polling_netdev array is
4774  * intended for Multiqueue, but should work fine with a single queue.
4775  **/
4776 static int ixgbe_alloc_queues(struct ixgbe_adapter *adapter)
4777 {
4778         int rx = 0, tx = 0, nid = adapter->node;
4779
4780         if (nid < 0 || !node_online(nid))
4781                 nid = first_online_node;
4782
4783         for (; tx < adapter->num_tx_queues; tx++) {
4784                 struct ixgbe_ring *ring;
4785
4786                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4787                 if (!ring)
4788                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4789                 if (!ring)
4790                         goto err_allocation;
4791                 ring->count = adapter->tx_ring_count;
4792                 ring->queue_index = tx;
4793                 ring->numa_node = nid;
4794                 ring->dev = &adapter->pdev->dev;
4795                 ring->netdev = adapter->netdev;
4796
4797                 adapter->tx_ring[tx] = ring;
4798         }
4799
4800         for (; rx < adapter->num_rx_queues; rx++) {
4801                 struct ixgbe_ring *ring;
4802
4803                 ring = kzalloc_node(sizeof(*ring), GFP_KERNEL, nid);
4804                 if (!ring)
4805                         ring = kzalloc(sizeof(*ring), GFP_KERNEL);
4806                 if (!ring)
4807                         goto err_allocation;
4808                 ring->count = adapter->rx_ring_count;
4809                 ring->queue_index = rx;
4810                 ring->numa_node = nid;
4811                 ring->dev = &adapter->pdev->dev;
4812                 ring->netdev = adapter->netdev;
4813
4814                 adapter->rx_ring[rx] = ring;
4815         }
4816
4817         ixgbe_cache_ring_register(adapter);
4818
4819         return 0;
4820
4821 err_allocation:
4822         while (tx)
4823                 kfree(adapter->tx_ring[--tx]);
4824
4825         while (rx)
4826                 kfree(adapter->rx_ring[--rx]);
4827         return -ENOMEM;
4828 }
4829
4830 /**
4831  * ixgbe_set_interrupt_capability - set MSI-X or MSI if supported
4832  * @adapter: board private structure to initialize
4833  *
4834  * Attempt to configure the interrupts using the best available
4835  * capabilities of the hardware and the kernel.
4836  **/
4837 static int ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
4838 {
4839         struct ixgbe_hw *hw = &adapter->hw;
4840         int err = 0;
4841         int vector, v_budget;
4842
4843         /*
4844          * It's easy to be greedy for MSI-X vectors, but it really
4845          * doesn't do us much good if we have a lot more vectors
4846          * than CPU's.  So let's be conservative and only ask for
4847          * (roughly) the same number of vectors as there are CPU's.
4848          */
4849         v_budget = min(adapter->num_rx_queues + adapter->num_tx_queues,
4850                        (int)num_online_cpus()) + NON_Q_VECTORS;
4851
4852         /*
4853          * At the same time, hardware can only support a maximum of
4854          * hw.mac->max_msix_vectors vectors.  With features
4855          * such as RSS and VMDq, we can easily surpass the number of Rx and Tx
4856          * descriptor queues supported by our device.  Thus, we cap it off in
4857          * those rare cases where the cpu count also exceeds our vector limit.
4858          */
4859         v_budget = min(v_budget, (int)hw->mac.max_msix_vectors);
4860
4861         /* A failure in MSI-X entry allocation isn't fatal, but it does
4862          * mean we disable MSI-X capabilities of the adapter. */
4863         adapter->msix_entries = kcalloc(v_budget,
4864                                         sizeof(struct msix_entry), GFP_KERNEL);
4865         if (adapter->msix_entries) {
4866                 for (vector = 0; vector < v_budget; vector++)
4867                         adapter->msix_entries[vector].entry = vector;
4868
4869                 ixgbe_acquire_msix_vectors(adapter, v_budget);
4870
4871                 if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4872                         goto out;
4873         }
4874
4875         adapter->flags &= ~IXGBE_FLAG_DCB_ENABLED;
4876         adapter->flags &= ~IXGBE_FLAG_RSS_ENABLED;
4877         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
4878                 e_err(probe,
4879                       "ATR is not supported while multiple "
4880                       "queues are disabled.  Disabling Flow Director\n");
4881         }
4882         adapter->flags &= ~IXGBE_FLAG_FDIR_HASH_CAPABLE;
4883         adapter->atr_sample_rate = 0;
4884         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
4885                 ixgbe_disable_sriov(adapter);
4886
4887         err = ixgbe_set_num_queues(adapter);
4888         if (err)
4889                 return err;
4890
4891         err = pci_enable_msi(adapter->pdev);
4892         if (!err) {
4893                 adapter->flags |= IXGBE_FLAG_MSI_ENABLED;
4894         } else {
4895                 netif_printk(adapter, hw, KERN_DEBUG, adapter->netdev,
4896                              "Unable to allocate MSI interrupt, "
4897                              "falling back to legacy.  Error: %d\n", err);
4898                 /* reset err */
4899                 err = 0;
4900         }
4901
4902 out:
4903         return err;
4904 }
4905
4906 /**
4907  * ixgbe_alloc_q_vectors - Allocate memory for interrupt vectors
4908  * @adapter: board private structure to initialize
4909  *
4910  * We allocate one q_vector per queue interrupt.  If allocation fails we
4911  * return -ENOMEM.
4912  **/
4913 static int ixgbe_alloc_q_vectors(struct ixgbe_adapter *adapter)
4914 {
4915         int q_idx, num_q_vectors;
4916         struct ixgbe_q_vector *q_vector;
4917         int (*poll)(struct napi_struct *, int);
4918
4919         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4920                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4921                 poll = &ixgbe_clean_rxtx_many;
4922         } else {
4923                 num_q_vectors = 1;
4924                 poll = &ixgbe_poll;
4925         }
4926
4927         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4928                 q_vector = kzalloc_node(sizeof(struct ixgbe_q_vector),
4929                                         GFP_KERNEL, adapter->node);
4930                 if (!q_vector)
4931                         q_vector = kzalloc(sizeof(struct ixgbe_q_vector),
4932                                            GFP_KERNEL);
4933                 if (!q_vector)
4934                         goto err_out;
4935                 q_vector->adapter = adapter;
4936                 if (q_vector->txr_count && !q_vector->rxr_count)
4937                         q_vector->eitr = adapter->tx_eitr_param;
4938                 else
4939                         q_vector->eitr = adapter->rx_eitr_param;
4940                 q_vector->v_idx = q_idx;
4941                 netif_napi_add(adapter->netdev, &q_vector->napi, (*poll), 64);
4942                 adapter->q_vector[q_idx] = q_vector;
4943         }
4944
4945         return 0;
4946
4947 err_out:
4948         while (q_idx) {
4949                 q_idx--;
4950                 q_vector = adapter->q_vector[q_idx];
4951                 netif_napi_del(&q_vector->napi);
4952                 kfree(q_vector);
4953                 adapter->q_vector[q_idx] = NULL;
4954         }
4955         return -ENOMEM;
4956 }
4957
4958 /**
4959  * ixgbe_free_q_vectors - Free memory allocated for interrupt vectors
4960  * @adapter: board private structure to initialize
4961  *
4962  * This function frees the memory allocated to the q_vectors.  In addition if
4963  * NAPI is enabled it will delete any references to the NAPI struct prior
4964  * to freeing the q_vector.
4965  **/
4966 static void ixgbe_free_q_vectors(struct ixgbe_adapter *adapter)
4967 {
4968         int q_idx, num_q_vectors;
4969
4970         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED)
4971                 num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
4972         else
4973                 num_q_vectors = 1;
4974
4975         for (q_idx = 0; q_idx < num_q_vectors; q_idx++) {
4976                 struct ixgbe_q_vector *q_vector = adapter->q_vector[q_idx];
4977                 adapter->q_vector[q_idx] = NULL;
4978                 netif_napi_del(&q_vector->napi);
4979                 kfree(q_vector);
4980         }
4981 }
4982
4983 static void ixgbe_reset_interrupt_capability(struct ixgbe_adapter *adapter)
4984 {
4985         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
4986                 adapter->flags &= ~IXGBE_FLAG_MSIX_ENABLED;
4987                 pci_disable_msix(adapter->pdev);
4988                 kfree(adapter->msix_entries);
4989                 adapter->msix_entries = NULL;
4990         } else if (adapter->flags & IXGBE_FLAG_MSI_ENABLED) {
4991                 adapter->flags &= ~IXGBE_FLAG_MSI_ENABLED;
4992                 pci_disable_msi(adapter->pdev);
4993         }
4994 }
4995
4996 /**
4997  * ixgbe_init_interrupt_scheme - Determine proper interrupt scheme
4998  * @adapter: board private structure to initialize
4999  *
5000  * We determine which interrupt scheme to use based on...
5001  * - Kernel support (MSI, MSI-X)
5002  *   - which can be user-defined (via MODULE_PARAM)
5003  * - Hardware queue count (num_*_queues)
5004  *   - defined by miscellaneous hardware support/features (RSS, etc.)
5005  **/
5006 int ixgbe_init_interrupt_scheme(struct ixgbe_adapter *adapter)
5007 {
5008         int err;
5009
5010         /* Number of supported queues */
5011         err = ixgbe_set_num_queues(adapter);
5012         if (err)
5013                 return err;
5014
5015         err = ixgbe_set_interrupt_capability(adapter);
5016         if (err) {
5017                 e_dev_err("Unable to setup interrupt capabilities\n");
5018                 goto err_set_interrupt;
5019         }
5020
5021         err = ixgbe_alloc_q_vectors(adapter);
5022         if (err) {
5023                 e_dev_err("Unable to allocate memory for queue vectors\n");
5024                 goto err_alloc_q_vectors;
5025         }
5026
5027         err = ixgbe_alloc_queues(adapter);
5028         if (err) {
5029                 e_dev_err("Unable to allocate memory for queues\n");
5030                 goto err_alloc_queues;
5031         }
5032
5033         e_dev_info("Multiqueue %s: Rx Queue count = %u, Tx Queue count = %u\n",
5034                    (adapter->num_rx_queues > 1) ? "Enabled" : "Disabled",
5035                    adapter->num_rx_queues, adapter->num_tx_queues);
5036
5037         set_bit(__IXGBE_DOWN, &adapter->state);
5038
5039         return 0;
5040
5041 err_alloc_queues:
5042         ixgbe_free_q_vectors(adapter);
5043 err_alloc_q_vectors:
5044         ixgbe_reset_interrupt_capability(adapter);
5045 err_set_interrupt:
5046         return err;
5047 }
5048
5049 /**
5050  * ixgbe_clear_interrupt_scheme - Clear the current interrupt scheme settings
5051  * @adapter: board private structure to clear interrupt scheme on
5052  *
5053  * We go through and clear interrupt specific resources and reset the structure
5054  * to pre-load conditions
5055  **/
5056 void ixgbe_clear_interrupt_scheme(struct ixgbe_adapter *adapter)
5057 {
5058         int i;
5059
5060         for (i = 0; i < adapter->num_tx_queues; i++) {
5061                 kfree(adapter->tx_ring[i]);
5062                 adapter->tx_ring[i] = NULL;
5063         }
5064         for (i = 0; i < adapter->num_rx_queues; i++) {
5065                 struct ixgbe_ring *ring = adapter->rx_ring[i];
5066
5067                 /* ixgbe_get_stats64() might access this ring, we must wait
5068                  * a grace period before freeing it.
5069                  */
5070                 kfree_rcu(ring, rcu);
5071                 adapter->rx_ring[i] = NULL;
5072         }
5073
5074         adapter->num_tx_queues = 0;
5075         adapter->num_rx_queues = 0;
5076
5077         ixgbe_free_q_vectors(adapter);
5078         ixgbe_reset_interrupt_capability(adapter);
5079 }
5080
5081 /**
5082  * ixgbe_sw_init - Initialize general software structures (struct ixgbe_adapter)
5083  * @adapter: board private structure to initialize
5084  *
5085  * ixgbe_sw_init initializes the Adapter private data structure.
5086  * Fields are initialized based on PCI device information and
5087  * OS network device settings (MTU size).
5088  **/
5089 static int __devinit ixgbe_sw_init(struct ixgbe_adapter *adapter)
5090 {
5091         struct ixgbe_hw *hw = &adapter->hw;
5092         struct pci_dev *pdev = adapter->pdev;
5093         struct net_device *dev = adapter->netdev;
5094         unsigned int rss;
5095 #ifdef CONFIG_IXGBE_DCB
5096         int j;
5097         struct tc_configuration *tc;
5098 #endif
5099         int max_frame = dev->mtu + ETH_HLEN + ETH_FCS_LEN;
5100
5101         /* PCI config space info */
5102
5103         hw->vendor_id = pdev->vendor;
5104         hw->device_id = pdev->device;
5105         hw->revision_id = pdev->revision;
5106         hw->subsystem_vendor_id = pdev->subsystem_vendor;
5107         hw->subsystem_device_id = pdev->subsystem_device;
5108
5109         /* Set capability flags */
5110         rss = min(IXGBE_MAX_RSS_INDICES, (int)num_online_cpus());
5111         adapter->ring_feature[RING_F_RSS].indices = rss;
5112         adapter->flags |= IXGBE_FLAG_RSS_ENABLED;
5113         switch (hw->mac.type) {
5114         case ixgbe_mac_82598EB:
5115                 if (hw->device_id == IXGBE_DEV_ID_82598AT)
5116                         adapter->flags |= IXGBE_FLAG_FAN_FAIL_CAPABLE;
5117                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82598;
5118                 break;
5119         case ixgbe_mac_82599EB:
5120         case ixgbe_mac_X540:
5121                 adapter->max_msix_q_vectors = MAX_MSIX_Q_VECTORS_82599;
5122                 adapter->flags2 |= IXGBE_FLAG2_RSC_CAPABLE;
5123                 adapter->flags2 |= IXGBE_FLAG2_RSC_ENABLED;
5124                 if (hw->device_id == IXGBE_DEV_ID_82599_T3_LOM)
5125                         adapter->flags2 |= IXGBE_FLAG2_TEMP_SENSOR_CAPABLE;
5126                 /* n-tuple support exists, always init our spinlock */
5127                 spin_lock_init(&adapter->fdir_perfect_lock);
5128                 /* Flow Director hash filters enabled */
5129                 adapter->flags |= IXGBE_FLAG_FDIR_HASH_CAPABLE;
5130                 adapter->atr_sample_rate = 20;
5131                 adapter->ring_feature[RING_F_FDIR].indices =
5132                                                          IXGBE_MAX_FDIR_INDICES;
5133                 adapter->fdir_pballoc = 0;
5134 #ifdef IXGBE_FCOE
5135                 adapter->flags |= IXGBE_FLAG_FCOE_CAPABLE;
5136                 adapter->flags &= ~IXGBE_FLAG_FCOE_ENABLED;
5137                 adapter->ring_feature[RING_F_FCOE].indices = 0;
5138 #ifdef CONFIG_IXGBE_DCB
5139                 /* Default traffic class to use for FCoE */
5140                 adapter->fcoe.tc = IXGBE_FCOE_DEFTC;
5141                 adapter->fcoe.up = IXGBE_FCOE_DEFTC;
5142 #endif
5143 #endif /* IXGBE_FCOE */
5144                 break;
5145         default:
5146                 break;
5147         }
5148
5149 #ifdef CONFIG_IXGBE_DCB
5150         /* Configure DCB traffic classes */
5151         for (j = 0; j < MAX_TRAFFIC_CLASS; j++) {
5152                 tc = &adapter->dcb_cfg.tc_config[j];
5153                 tc->path[DCB_TX_CONFIG].bwg_id = 0;
5154                 tc->path[DCB_TX_CONFIG].bwg_percent = 12 + (j & 1);
5155                 tc->path[DCB_RX_CONFIG].bwg_id = 0;
5156                 tc->path[DCB_RX_CONFIG].bwg_percent = 12 + (j & 1);
5157                 tc->dcb_pfc = pfc_disabled;
5158         }
5159         adapter->dcb_cfg.bw_percentage[DCB_TX_CONFIG][0] = 100;
5160         adapter->dcb_cfg.bw_percentage[DCB_RX_CONFIG][0] = 100;
5161         adapter->dcb_cfg.pfc_mode_enable = false;
5162         adapter->dcb_set_bitmap = 0x00;
5163         adapter->dcbx_cap = DCB_CAP_DCBX_HOST | DCB_CAP_DCBX_VER_CEE;
5164         ixgbe_copy_dcb_cfg(&adapter->dcb_cfg, &adapter->temp_dcb_cfg,
5165                            MAX_TRAFFIC_CLASS);
5166
5167 #endif
5168
5169         /* default flow control settings */
5170         hw->fc.requested_mode = ixgbe_fc_full;
5171         hw->fc.current_mode = ixgbe_fc_full;    /* init for ethtool output */
5172 #ifdef CONFIG_DCB
5173         adapter->last_lfc_mode = hw->fc.current_mode;
5174 #endif
5175         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5176         hw->fc.low_water = FC_LOW_WATER(max_frame);
5177         hw->fc.pause_time = IXGBE_DEFAULT_FCPAUSE;
5178         hw->fc.send_xon = true;
5179         hw->fc.disable_fc_autoneg = false;
5180
5181         /* enable itr by default in dynamic mode */
5182         adapter->rx_itr_setting = 1;
5183         adapter->rx_eitr_param = 20000;
5184         adapter->tx_itr_setting = 1;
5185         adapter->tx_eitr_param = 10000;
5186
5187         /* set defaults for eitr in MegaBytes */
5188         adapter->eitr_low = 10;
5189         adapter->eitr_high = 20;
5190
5191         /* set default ring sizes */
5192         adapter->tx_ring_count = IXGBE_DEFAULT_TXD;
5193         adapter->rx_ring_count = IXGBE_DEFAULT_RXD;
5194
5195         /* initialize eeprom parameters */
5196         if (ixgbe_init_eeprom_params_generic(hw)) {
5197                 e_dev_err("EEPROM initialization failed\n");
5198                 return -EIO;
5199         }
5200
5201         /* enable rx csum by default */
5202         adapter->flags |= IXGBE_FLAG_RX_CSUM_ENABLED;
5203
5204         /* get assigned NUMA node */
5205         adapter->node = dev_to_node(&pdev->dev);
5206
5207         set_bit(__IXGBE_DOWN, &adapter->state);
5208
5209         return 0;
5210 }
5211
5212 /**
5213  * ixgbe_setup_tx_resources - allocate Tx resources (Descriptors)
5214  * @tx_ring:    tx descriptor ring (for a specific queue) to setup
5215  *
5216  * Return 0 on success, negative on failure
5217  **/
5218 int ixgbe_setup_tx_resources(struct ixgbe_ring *tx_ring)
5219 {
5220         struct device *dev = tx_ring->dev;
5221         int size;
5222
5223         size = sizeof(struct ixgbe_tx_buffer) * tx_ring->count;
5224         tx_ring->tx_buffer_info = vzalloc_node(size, tx_ring->numa_node);
5225         if (!tx_ring->tx_buffer_info)
5226                 tx_ring->tx_buffer_info = vzalloc(size);
5227         if (!tx_ring->tx_buffer_info)
5228                 goto err;
5229
5230         /* round up to nearest 4K */
5231         tx_ring->size = tx_ring->count * sizeof(union ixgbe_adv_tx_desc);
5232         tx_ring->size = ALIGN(tx_ring->size, 4096);
5233
5234         tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
5235                                            &tx_ring->dma, GFP_KERNEL);
5236         if (!tx_ring->desc)
5237                 goto err;
5238
5239         tx_ring->next_to_use = 0;
5240         tx_ring->next_to_clean = 0;
5241         tx_ring->work_limit = tx_ring->count;
5242         return 0;
5243
5244 err:
5245         vfree(tx_ring->tx_buffer_info);
5246         tx_ring->tx_buffer_info = NULL;
5247         dev_err(dev, "Unable to allocate memory for the Tx descriptor ring\n");
5248         return -ENOMEM;
5249 }
5250
5251 /**
5252  * ixgbe_setup_all_tx_resources - allocate all queues Tx resources
5253  * @adapter: board private structure
5254  *
5255  * If this function returns with an error, then it's possible one or
5256  * more of the rings is populated (while the rest are not).  It is the
5257  * callers duty to clean those orphaned rings.
5258  *
5259  * Return 0 on success, negative on failure
5260  **/
5261 static int ixgbe_setup_all_tx_resources(struct ixgbe_adapter *adapter)
5262 {
5263         int i, err = 0;
5264
5265         for (i = 0; i < adapter->num_tx_queues; i++) {
5266                 err = ixgbe_setup_tx_resources(adapter->tx_ring[i]);
5267                 if (!err)
5268                         continue;
5269                 e_err(probe, "Allocation for Tx Queue %u failed\n", i);
5270                 break;
5271         }
5272
5273         return err;
5274 }
5275
5276 /**
5277  * ixgbe_setup_rx_resources - allocate Rx resources (Descriptors)
5278  * @rx_ring:    rx descriptor ring (for a specific queue) to setup
5279  *
5280  * Returns 0 on success, negative on failure
5281  **/
5282 int ixgbe_setup_rx_resources(struct ixgbe_ring *rx_ring)
5283 {
5284         struct device *dev = rx_ring->dev;
5285         int size;
5286
5287         size = sizeof(struct ixgbe_rx_buffer) * rx_ring->count;
5288         rx_ring->rx_buffer_info = vzalloc_node(size, rx_ring->numa_node);
5289         if (!rx_ring->rx_buffer_info)
5290                 rx_ring->rx_buffer_info = vzalloc(size);
5291         if (!rx_ring->rx_buffer_info)
5292                 goto err;
5293
5294         /* Round up to nearest 4K */
5295         rx_ring->size = rx_ring->count * sizeof(union ixgbe_adv_rx_desc);
5296         rx_ring->size = ALIGN(rx_ring->size, 4096);
5297
5298         rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
5299                                            &rx_ring->dma, GFP_KERNEL);
5300
5301         if (!rx_ring->desc)
5302                 goto err;
5303
5304         rx_ring->next_to_clean = 0;
5305         rx_ring->next_to_use = 0;
5306
5307         return 0;
5308 err:
5309         vfree(rx_ring->rx_buffer_info);
5310         rx_ring->rx_buffer_info = NULL;
5311         dev_err(dev, "Unable to allocate memory for the Rx descriptor ring\n");
5312         return -ENOMEM;
5313 }
5314
5315 /**
5316  * ixgbe_setup_all_rx_resources - allocate all queues Rx resources
5317  * @adapter: board private structure
5318  *
5319  * If this function returns with an error, then it's possible one or
5320  * more of the rings is populated (while the rest are not).  It is the
5321  * callers duty to clean those orphaned rings.
5322  *
5323  * Return 0 on success, negative on failure
5324  **/
5325 static int ixgbe_setup_all_rx_resources(struct ixgbe_adapter *adapter)
5326 {
5327         int i, err = 0;
5328
5329         for (i = 0; i < adapter->num_rx_queues; i++) {
5330                 err = ixgbe_setup_rx_resources(adapter->rx_ring[i]);
5331                 if (!err)
5332                         continue;
5333                 e_err(probe, "Allocation for Rx Queue %u failed\n", i);
5334                 break;
5335         }
5336
5337         return err;
5338 }
5339
5340 /**
5341  * ixgbe_free_tx_resources - Free Tx Resources per Queue
5342  * @tx_ring: Tx descriptor ring for a specific queue
5343  *
5344  * Free all transmit software resources
5345  **/
5346 void ixgbe_free_tx_resources(struct ixgbe_ring *tx_ring)
5347 {
5348         ixgbe_clean_tx_ring(tx_ring);
5349
5350         vfree(tx_ring->tx_buffer_info);
5351         tx_ring->tx_buffer_info = NULL;
5352
5353         /* if not set, then don't free */
5354         if (!tx_ring->desc)
5355                 return;
5356
5357         dma_free_coherent(tx_ring->dev, tx_ring->size,
5358                           tx_ring->desc, tx_ring->dma);
5359
5360         tx_ring->desc = NULL;
5361 }
5362
5363 /**
5364  * ixgbe_free_all_tx_resources - Free Tx Resources for All Queues
5365  * @adapter: board private structure
5366  *
5367  * Free all transmit software resources
5368  **/
5369 static void ixgbe_free_all_tx_resources(struct ixgbe_adapter *adapter)
5370 {
5371         int i;
5372
5373         for (i = 0; i < adapter->num_tx_queues; i++)
5374                 if (adapter->tx_ring[i]->desc)
5375                         ixgbe_free_tx_resources(adapter->tx_ring[i]);
5376 }
5377
5378 /**
5379  * ixgbe_free_rx_resources - Free Rx Resources
5380  * @rx_ring: ring to clean the resources from
5381  *
5382  * Free all receive software resources
5383  **/
5384 void ixgbe_free_rx_resources(struct ixgbe_ring *rx_ring)
5385 {
5386         ixgbe_clean_rx_ring(rx_ring);
5387
5388         vfree(rx_ring->rx_buffer_info);
5389         rx_ring->rx_buffer_info = NULL;
5390
5391         /* if not set, then don't free */
5392         if (!rx_ring->desc)
5393                 return;
5394
5395         dma_free_coherent(rx_ring->dev, rx_ring->size,
5396                           rx_ring->desc, rx_ring->dma);
5397
5398         rx_ring->desc = NULL;
5399 }
5400
5401 /**
5402  * ixgbe_free_all_rx_resources - Free Rx Resources for All Queues
5403  * @adapter: board private structure
5404  *
5405  * Free all receive software resources
5406  **/
5407 static void ixgbe_free_all_rx_resources(struct ixgbe_adapter *adapter)
5408 {
5409         int i;
5410
5411         for (i = 0; i < adapter->num_rx_queues; i++)
5412                 if (adapter->rx_ring[i]->desc)
5413                         ixgbe_free_rx_resources(adapter->rx_ring[i]);
5414 }
5415
5416 /**
5417  * ixgbe_change_mtu - Change the Maximum Transfer Unit
5418  * @netdev: network interface device structure
5419  * @new_mtu: new value for maximum frame size
5420  *
5421  * Returns 0 on success, negative on failure
5422  **/
5423 static int ixgbe_change_mtu(struct net_device *netdev, int new_mtu)
5424 {
5425         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5426         struct ixgbe_hw *hw = &adapter->hw;
5427         int max_frame = new_mtu + ETH_HLEN + ETH_FCS_LEN;
5428
5429         /* MTU < 68 is an error and causes problems on some kernels */
5430         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED &&
5431             hw->mac.type != ixgbe_mac_X540) {
5432                 if ((new_mtu < 68) || (max_frame > MAXIMUM_ETHERNET_VLAN_SIZE))
5433                         return -EINVAL;
5434         } else {
5435                 if ((new_mtu < 68) || (max_frame > IXGBE_MAX_JUMBO_FRAME_SIZE))
5436                         return -EINVAL;
5437         }
5438
5439         e_info(probe, "changing MTU from %d to %d\n", netdev->mtu, new_mtu);
5440         /* must set new MTU before calling down or up */
5441         netdev->mtu = new_mtu;
5442
5443         hw->fc.high_water = FC_HIGH_WATER(max_frame);
5444         hw->fc.low_water = FC_LOW_WATER(max_frame);
5445
5446         if (netif_running(netdev))
5447                 ixgbe_reinit_locked(adapter);
5448
5449         return 0;
5450 }
5451
5452 /**
5453  * ixgbe_open - Called when a network interface is made active
5454  * @netdev: network interface device structure
5455  *
5456  * Returns 0 on success, negative value on failure
5457  *
5458  * The open entry point is called when a network interface is made
5459  * active by the system (IFF_UP).  At this point all resources needed
5460  * for transmit and receive operations are allocated, the interrupt
5461  * handler is registered with the OS, the watchdog timer is started,
5462  * and the stack is notified that the interface is ready.
5463  **/
5464 static int ixgbe_open(struct net_device *netdev)
5465 {
5466         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5467         int err;
5468
5469         /* disallow open during test */
5470         if (test_bit(__IXGBE_TESTING, &adapter->state))
5471                 return -EBUSY;
5472
5473         netif_carrier_off(netdev);
5474
5475         /* allocate transmit descriptors */
5476         err = ixgbe_setup_all_tx_resources(adapter);
5477         if (err)
5478                 goto err_setup_tx;
5479
5480         /* allocate receive descriptors */
5481         err = ixgbe_setup_all_rx_resources(adapter);
5482         if (err)
5483                 goto err_setup_rx;
5484
5485         ixgbe_configure(adapter);
5486
5487         err = ixgbe_request_irq(adapter);
5488         if (err)
5489                 goto err_req_irq;
5490
5491         err = ixgbe_up_complete(adapter);
5492         if (err)
5493                 goto err_up;
5494
5495         netif_tx_start_all_queues(netdev);
5496
5497         return 0;
5498
5499 err_up:
5500         ixgbe_release_hw_control(adapter);
5501         ixgbe_free_irq(adapter);
5502 err_req_irq:
5503 err_setup_rx:
5504         ixgbe_free_all_rx_resources(adapter);
5505 err_setup_tx:
5506         ixgbe_free_all_tx_resources(adapter);
5507         ixgbe_reset(adapter);
5508
5509         return err;
5510 }
5511
5512 /**
5513  * ixgbe_close - Disables a network interface
5514  * @netdev: network interface device structure
5515  *
5516  * Returns 0, this is not allowed to fail
5517  *
5518  * The close entry point is called when an interface is de-activated
5519  * by the OS.  The hardware is still under the drivers control, but
5520  * needs to be disabled.  A global MAC reset is issued to stop the
5521  * hardware, and all transmit and receive resources are freed.
5522  **/
5523 static int ixgbe_close(struct net_device *netdev)
5524 {
5525         struct ixgbe_adapter *adapter = netdev_priv(netdev);
5526
5527         ixgbe_down(adapter);
5528         ixgbe_free_irq(adapter);
5529
5530         ixgbe_free_all_tx_resources(adapter);
5531         ixgbe_free_all_rx_resources(adapter);
5532
5533         ixgbe_release_hw_control(adapter);
5534
5535         return 0;
5536 }
5537
5538 #ifdef CONFIG_PM
5539 static int ixgbe_resume(struct pci_dev *pdev)
5540 {
5541         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5542         struct net_device *netdev = adapter->netdev;
5543         u32 err;
5544
5545         pci_set_power_state(pdev, PCI_D0);
5546         pci_restore_state(pdev);
5547         /*
5548          * pci_restore_state clears dev->state_saved so call
5549          * pci_save_state to restore it.
5550          */
5551         pci_save_state(pdev);
5552
5553         err = pci_enable_device_mem(pdev);
5554         if (err) {
5555                 e_dev_err("Cannot enable PCI device from suspend\n");
5556                 return err;
5557         }
5558         pci_set_master(pdev);
5559
5560         pci_wake_from_d3(pdev, false);
5561
5562         err = ixgbe_init_interrupt_scheme(adapter);
5563         if (err) {
5564                 e_dev_err("Cannot initialize interrupts for device\n");
5565                 return err;
5566         }
5567
5568         ixgbe_reset(adapter);
5569
5570         IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
5571
5572         if (netif_running(netdev)) {
5573                 err = ixgbe_open(netdev);
5574                 if (err)
5575                         return err;
5576         }
5577
5578         netif_device_attach(netdev);
5579
5580         return 0;
5581 }
5582 #endif /* CONFIG_PM */
5583
5584 static int __ixgbe_shutdown(struct pci_dev *pdev, bool *enable_wake)
5585 {
5586         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
5587         struct net_device *netdev = adapter->netdev;
5588         struct ixgbe_hw *hw = &adapter->hw;
5589         u32 ctrl, fctrl;
5590         u32 wufc = adapter->wol;
5591 #ifdef CONFIG_PM
5592         int retval = 0;
5593 #endif
5594
5595         netif_device_detach(netdev);
5596
5597         if (netif_running(netdev)) {
5598                 ixgbe_down(adapter);
5599                 ixgbe_free_irq(adapter);
5600                 ixgbe_free_all_tx_resources(adapter);
5601                 ixgbe_free_all_rx_resources(adapter);
5602         }
5603
5604         ixgbe_clear_interrupt_scheme(adapter);
5605 #ifdef CONFIG_DCB
5606         kfree(adapter->ixgbe_ieee_pfc);
5607         kfree(adapter->ixgbe_ieee_ets);
5608 #endif
5609
5610 #ifdef CONFIG_PM
5611         retval = pci_save_state(pdev);
5612         if (retval)
5613                 return retval;
5614
5615 #endif
5616         if (wufc) {
5617                 ixgbe_set_rx_mode(netdev);
5618
5619                 /* turn on all-multi mode if wake on multicast is enabled */
5620                 if (wufc & IXGBE_WUFC_MC) {
5621                         fctrl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
5622                         fctrl |= IXGBE_FCTRL_MPE;
5623                         IXGBE_WRITE_REG(hw, IXGBE_FCTRL, fctrl);
5624                 }
5625
5626                 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL);
5627                 ctrl |= IXGBE_CTRL_GIO_DIS;
5628                 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl);
5629
5630                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, wufc);
5631         } else {
5632                 IXGBE_WRITE_REG(hw, IXGBE_WUC, 0);
5633                 IXGBE_WRITE_REG(hw, IXGBE_WUFC, 0);
5634         }
5635
5636         switch (hw->mac.type) {
5637         case ixgbe_mac_82598EB:
5638                 pci_wake_from_d3(pdev, false);
5639                 break;
5640         case ixgbe_mac_82599EB:
5641         case ixgbe_mac_X540:
5642                 pci_wake_from_d3(pdev, !!wufc);
5643                 break;
5644         default:
5645                 break;
5646         }
5647
5648         *enable_wake = !!wufc;
5649
5650         ixgbe_release_hw_control(adapter);
5651
5652         pci_disable_device(pdev);
5653
5654         return 0;
5655 }
5656
5657 #ifdef CONFIG_PM
5658 static int ixgbe_suspend(struct pci_dev *pdev, pm_message_t state)
5659 {
5660         int retval;
5661         bool wake;
5662
5663         retval = __ixgbe_shutdown(pdev, &wake);
5664         if (retval)
5665                 return retval;
5666
5667         if (wake) {
5668                 pci_prepare_to_sleep(pdev);
5669         } else {
5670                 pci_wake_from_d3(pdev, false);
5671                 pci_set_power_state(pdev, PCI_D3hot);
5672         }
5673
5674         return 0;
5675 }
5676 #endif /* CONFIG_PM */
5677
5678 static void ixgbe_shutdown(struct pci_dev *pdev)
5679 {
5680         bool wake;
5681
5682         __ixgbe_shutdown(pdev, &wake);
5683
5684         if (system_state == SYSTEM_POWER_OFF) {
5685                 pci_wake_from_d3(pdev, wake);
5686                 pci_set_power_state(pdev, PCI_D3hot);
5687         }
5688 }
5689
5690 /**
5691  * ixgbe_update_stats - Update the board statistics counters.
5692  * @adapter: board private structure
5693  **/
5694 void ixgbe_update_stats(struct ixgbe_adapter *adapter)
5695 {
5696         struct net_device *netdev = adapter->netdev;
5697         struct ixgbe_hw *hw = &adapter->hw;
5698         struct ixgbe_hw_stats *hwstats = &adapter->stats;
5699         u64 total_mpc = 0;
5700         u32 i, missed_rx = 0, mpc, bprc, lxon, lxoff, xon_off_tot;
5701         u64 non_eop_descs = 0, restart_queue = 0, tx_busy = 0;
5702         u64 alloc_rx_page_failed = 0, alloc_rx_buff_failed = 0;
5703         u64 bytes = 0, packets = 0;
5704
5705         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5706             test_bit(__IXGBE_RESETTING, &adapter->state))
5707                 return;
5708
5709         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED) {
5710                 u64 rsc_count = 0;
5711                 u64 rsc_flush = 0;
5712                 for (i = 0; i < 16; i++)
5713                         adapter->hw_rx_no_dma_resources +=
5714                                 IXGBE_READ_REG(hw, IXGBE_QPRDC(i));
5715                 for (i = 0; i < adapter->num_rx_queues; i++) {
5716                         rsc_count += adapter->rx_ring[i]->rx_stats.rsc_count;
5717                         rsc_flush += adapter->rx_ring[i]->rx_stats.rsc_flush;
5718                 }
5719                 adapter->rsc_total_count = rsc_count;
5720                 adapter->rsc_total_flush = rsc_flush;
5721         }
5722
5723         for (i = 0; i < adapter->num_rx_queues; i++) {
5724                 struct ixgbe_ring *rx_ring = adapter->rx_ring[i];
5725                 non_eop_descs += rx_ring->rx_stats.non_eop_descs;
5726                 alloc_rx_page_failed += rx_ring->rx_stats.alloc_rx_page_failed;
5727                 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed;
5728                 bytes += rx_ring->stats.bytes;
5729                 packets += rx_ring->stats.packets;
5730         }
5731         adapter->non_eop_descs = non_eop_descs;
5732         adapter->alloc_rx_page_failed = alloc_rx_page_failed;
5733         adapter->alloc_rx_buff_failed = alloc_rx_buff_failed;
5734         netdev->stats.rx_bytes = bytes;
5735         netdev->stats.rx_packets = packets;
5736
5737         bytes = 0;
5738         packets = 0;
5739         /* gather some stats to the adapter struct that are per queue */
5740         for (i = 0; i < adapter->num_tx_queues; i++) {
5741                 struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
5742                 restart_queue += tx_ring->tx_stats.restart_queue;
5743                 tx_busy += tx_ring->tx_stats.tx_busy;
5744                 bytes += tx_ring->stats.bytes;
5745                 packets += tx_ring->stats.packets;
5746         }
5747         adapter->restart_queue = restart_queue;
5748         adapter->tx_busy = tx_busy;
5749         netdev->stats.tx_bytes = bytes;
5750         netdev->stats.tx_packets = packets;
5751
5752         hwstats->crcerrs += IXGBE_READ_REG(hw, IXGBE_CRCERRS);
5753         for (i = 0; i < 8; i++) {
5754                 /* for packet buffers not used, the register should read 0 */
5755                 mpc = IXGBE_READ_REG(hw, IXGBE_MPC(i));
5756                 missed_rx += mpc;
5757                 hwstats->mpc[i] += mpc;
5758                 total_mpc += hwstats->mpc[i];
5759                 if (hw->mac.type == ixgbe_mac_82598EB)
5760                         hwstats->rnbc[i] += IXGBE_READ_REG(hw, IXGBE_RNBC(i));
5761                 hwstats->qptc[i] += IXGBE_READ_REG(hw, IXGBE_QPTC(i));
5762                 hwstats->qbtc[i] += IXGBE_READ_REG(hw, IXGBE_QBTC(i));
5763                 hwstats->qprc[i] += IXGBE_READ_REG(hw, IXGBE_QPRC(i));
5764                 hwstats->qbrc[i] += IXGBE_READ_REG(hw, IXGBE_QBRC(i));
5765                 switch (hw->mac.type) {
5766                 case ixgbe_mac_82598EB:
5767                         hwstats->pxonrxc[i] +=
5768                                 IXGBE_READ_REG(hw, IXGBE_PXONRXC(i));
5769                         break;
5770                 case ixgbe_mac_82599EB:
5771                 case ixgbe_mac_X540:
5772                         hwstats->pxonrxc[i] +=
5773                                 IXGBE_READ_REG(hw, IXGBE_PXONRXCNT(i));
5774                         break;
5775                 default:
5776                         break;
5777                 }
5778                 hwstats->pxontxc[i] += IXGBE_READ_REG(hw, IXGBE_PXONTXC(i));
5779                 hwstats->pxofftxc[i] += IXGBE_READ_REG(hw, IXGBE_PXOFFTXC(i));
5780         }
5781         hwstats->gprc += IXGBE_READ_REG(hw, IXGBE_GPRC);
5782         /* work around hardware counting issue */
5783         hwstats->gprc -= missed_rx;
5784
5785         ixgbe_update_xoff_received(adapter);
5786
5787         /* 82598 hardware only has a 32 bit counter in the high register */
5788         switch (hw->mac.type) {
5789         case ixgbe_mac_82598EB:
5790                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXC);
5791                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCH);
5792                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCH);
5793                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORH);
5794                 break;
5795         case ixgbe_mac_X540:
5796                 /* OS2BMC stats are X540 only*/
5797                 hwstats->o2bgptc += IXGBE_READ_REG(hw, IXGBE_O2BGPTC);
5798                 hwstats->o2bspc += IXGBE_READ_REG(hw, IXGBE_O2BSPC);
5799                 hwstats->b2ospc += IXGBE_READ_REG(hw, IXGBE_B2OSPC);
5800                 hwstats->b2ogprc += IXGBE_READ_REG(hw, IXGBE_B2OGPRC);
5801         case ixgbe_mac_82599EB:
5802                 hwstats->gorc += IXGBE_READ_REG(hw, IXGBE_GORCL);
5803                 IXGBE_READ_REG(hw, IXGBE_GORCH); /* to clear */
5804                 hwstats->gotc += IXGBE_READ_REG(hw, IXGBE_GOTCL);
5805                 IXGBE_READ_REG(hw, IXGBE_GOTCH); /* to clear */
5806                 hwstats->tor += IXGBE_READ_REG(hw, IXGBE_TORL);
5807                 IXGBE_READ_REG(hw, IXGBE_TORH); /* to clear */
5808                 hwstats->lxonrxc += IXGBE_READ_REG(hw, IXGBE_LXONRXCNT);
5809                 hwstats->fdirmatch += IXGBE_READ_REG(hw, IXGBE_FDIRMATCH);
5810                 hwstats->fdirmiss += IXGBE_READ_REG(hw, IXGBE_FDIRMISS);
5811 #ifdef IXGBE_FCOE
5812                 hwstats->fccrc += IXGBE_READ_REG(hw, IXGBE_FCCRC);
5813                 hwstats->fcoerpdc += IXGBE_READ_REG(hw, IXGBE_FCOERPDC);
5814                 hwstats->fcoeprc += IXGBE_READ_REG(hw, IXGBE_FCOEPRC);
5815                 hwstats->fcoeptc += IXGBE_READ_REG(hw, IXGBE_FCOEPTC);
5816                 hwstats->fcoedwrc += IXGBE_READ_REG(hw, IXGBE_FCOEDWRC);
5817                 hwstats->fcoedwtc += IXGBE_READ_REG(hw, IXGBE_FCOEDWTC);
5818 #endif /* IXGBE_FCOE */
5819                 break;
5820         default:
5821                 break;
5822         }
5823         bprc = IXGBE_READ_REG(hw, IXGBE_BPRC);
5824         hwstats->bprc += bprc;
5825         hwstats->mprc += IXGBE_READ_REG(hw, IXGBE_MPRC);
5826         if (hw->mac.type == ixgbe_mac_82598EB)
5827                 hwstats->mprc -= bprc;
5828         hwstats->roc += IXGBE_READ_REG(hw, IXGBE_ROC);
5829         hwstats->prc64 += IXGBE_READ_REG(hw, IXGBE_PRC64);
5830         hwstats->prc127 += IXGBE_READ_REG(hw, IXGBE_PRC127);
5831         hwstats->prc255 += IXGBE_READ_REG(hw, IXGBE_PRC255);
5832         hwstats->prc511 += IXGBE_READ_REG(hw, IXGBE_PRC511);
5833         hwstats->prc1023 += IXGBE_READ_REG(hw, IXGBE_PRC1023);
5834         hwstats->prc1522 += IXGBE_READ_REG(hw, IXGBE_PRC1522);
5835         hwstats->rlec += IXGBE_READ_REG(hw, IXGBE_RLEC);
5836         lxon = IXGBE_READ_REG(hw, IXGBE_LXONTXC);
5837         hwstats->lxontxc += lxon;
5838         lxoff = IXGBE_READ_REG(hw, IXGBE_LXOFFTXC);
5839         hwstats->lxofftxc += lxoff;
5840         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5841         hwstats->gptc += IXGBE_READ_REG(hw, IXGBE_GPTC);
5842         hwstats->mptc += IXGBE_READ_REG(hw, IXGBE_MPTC);
5843         /*
5844          * 82598 errata - tx of flow control packets is included in tx counters
5845          */
5846         xon_off_tot = lxon + lxoff;
5847         hwstats->gptc -= xon_off_tot;
5848         hwstats->mptc -= xon_off_tot;
5849         hwstats->gotc -= (xon_off_tot * (ETH_ZLEN + ETH_FCS_LEN));
5850         hwstats->ruc += IXGBE_READ_REG(hw, IXGBE_RUC);
5851         hwstats->rfc += IXGBE_READ_REG(hw, IXGBE_RFC);
5852         hwstats->rjc += IXGBE_READ_REG(hw, IXGBE_RJC);
5853         hwstats->tpr += IXGBE_READ_REG(hw, IXGBE_TPR);
5854         hwstats->ptc64 += IXGBE_READ_REG(hw, IXGBE_PTC64);
5855         hwstats->ptc64 -= xon_off_tot;
5856         hwstats->ptc127 += IXGBE_READ_REG(hw, IXGBE_PTC127);
5857         hwstats->ptc255 += IXGBE_READ_REG(hw, IXGBE_PTC255);
5858         hwstats->ptc511 += IXGBE_READ_REG(hw, IXGBE_PTC511);
5859         hwstats->ptc1023 += IXGBE_READ_REG(hw, IXGBE_PTC1023);
5860         hwstats->ptc1522 += IXGBE_READ_REG(hw, IXGBE_PTC1522);
5861         hwstats->bptc += IXGBE_READ_REG(hw, IXGBE_BPTC);
5862
5863         /* Fill out the OS statistics structure */
5864         netdev->stats.multicast = hwstats->mprc;
5865
5866         /* Rx Errors */
5867         netdev->stats.rx_errors = hwstats->crcerrs + hwstats->rlec;
5868         netdev->stats.rx_dropped = 0;
5869         netdev->stats.rx_length_errors = hwstats->rlec;
5870         netdev->stats.rx_crc_errors = hwstats->crcerrs;
5871         netdev->stats.rx_missed_errors = total_mpc;
5872 }
5873
5874 /**
5875  * ixgbe_fdir_reinit_subtask - worker thread to reinit FDIR filter table
5876  * @adapter - pointer to the device adapter structure
5877  **/
5878 static void ixgbe_fdir_reinit_subtask(struct ixgbe_adapter *adapter)
5879 {
5880         struct ixgbe_hw *hw = &adapter->hw;
5881         int i;
5882
5883         if (!(adapter->flags2 & IXGBE_FLAG2_FDIR_REQUIRES_REINIT))
5884                 return;
5885
5886         adapter->flags2 &= ~IXGBE_FLAG2_FDIR_REQUIRES_REINIT;
5887
5888         /* if interface is down do nothing */
5889         if (test_bit(__IXGBE_DOWN, &adapter->state))
5890                 return;
5891
5892         /* do nothing if we are not using signature filters */
5893         if (!(adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE))
5894                 return;
5895
5896         adapter->fdir_overflow++;
5897
5898         if (ixgbe_reinit_fdir_tables_82599(hw) == 0) {
5899                 for (i = 0; i < adapter->num_tx_queues; i++)
5900                         set_bit(__IXGBE_TX_FDIR_INIT_DONE,
5901                                 &(adapter->tx_ring[i]->state));
5902                 /* re-enable flow director interrupts */
5903                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMS_FLOW_DIR);
5904         } else {
5905                 e_err(probe, "failed to finish FDIR re-initialization, "
5906                       "ignored adding FDIR ATR filters\n");
5907         }
5908 }
5909
5910 /**
5911  * ixgbe_check_hang_subtask - check for hung queues and dropped interrupts
5912  * @adapter - pointer to the device adapter structure
5913  *
5914  * This function serves two purposes.  First it strobes the interrupt lines
5915  * in order to make certain interrupts are occuring.  Secondly it sets the
5916  * bits needed to check for TX hangs.  As a result we should immediately
5917  * determine if a hang has occured.
5918  */
5919 static void ixgbe_check_hang_subtask(struct ixgbe_adapter *adapter)
5920 {
5921         struct ixgbe_hw *hw = &adapter->hw;
5922         u64 eics = 0;
5923         int i;
5924
5925         /* If we're down or resetting, just bail */
5926         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
5927             test_bit(__IXGBE_RESETTING, &adapter->state))
5928                 return;
5929
5930         /* Force detection of hung controller */
5931         if (netif_carrier_ok(adapter->netdev)) {
5932                 for (i = 0; i < adapter->num_tx_queues; i++)
5933                         set_check_for_tx_hang(adapter->tx_ring[i]);
5934         }
5935
5936         if (!(adapter->flags & IXGBE_FLAG_MSIX_ENABLED)) {
5937                 /*
5938                  * for legacy and MSI interrupts don't set any bits
5939                  * that are enabled for EIAM, because this operation
5940                  * would set *both* EIMS and EICS for any bit in EIAM
5941                  */
5942                 IXGBE_WRITE_REG(hw, IXGBE_EICS,
5943                         (IXGBE_EICS_TCP_TIMER | IXGBE_EICS_OTHER));
5944         } else {
5945                 /* get one bit for every active tx/rx interrupt vector */
5946                 for (i = 0; i < adapter->num_msix_vectors - NON_Q_VECTORS; i++) {
5947                         struct ixgbe_q_vector *qv = adapter->q_vector[i];
5948                         if (qv->rxr_count || qv->txr_count)
5949                                 eics |= ((u64)1 << i);
5950                 }
5951         }
5952
5953         /* Cause software interrupt to ensure rings are cleaned */
5954         ixgbe_irq_rearm_queues(adapter, eics);
5955
5956 }
5957
5958 /**
5959  * ixgbe_watchdog_update_link - update the link status
5960  * @adapter - pointer to the device adapter structure
5961  * @link_speed - pointer to a u32 to store the link_speed
5962  **/
5963 static void ixgbe_watchdog_update_link(struct ixgbe_adapter *adapter)
5964 {
5965         struct ixgbe_hw *hw = &adapter->hw;
5966         u32 link_speed = adapter->link_speed;
5967         bool link_up = adapter->link_up;
5968         int i;
5969
5970         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE))
5971                 return;
5972
5973         if (hw->mac.ops.check_link) {
5974                 hw->mac.ops.check_link(hw, &link_speed, &link_up, false);
5975         } else {
5976                 /* always assume link is up, if no check link function */
5977                 link_speed = IXGBE_LINK_SPEED_10GB_FULL;
5978                 link_up = true;
5979         }
5980         if (link_up) {
5981                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
5982                         for (i = 0; i < MAX_TRAFFIC_CLASS; i++)
5983                                 hw->mac.ops.fc_enable(hw, i);
5984                 } else {
5985                         hw->mac.ops.fc_enable(hw, 0);
5986                 }
5987         }
5988
5989         if (link_up ||
5990             time_after(jiffies, (adapter->link_check_timeout +
5991                                  IXGBE_TRY_LINK_TIMEOUT))) {
5992                 adapter->flags &= ~IXGBE_FLAG_NEED_LINK_UPDATE;
5993                 IXGBE_WRITE_REG(hw, IXGBE_EIMS, IXGBE_EIMC_LSC);
5994                 IXGBE_WRITE_FLUSH(hw);
5995         }
5996
5997         adapter->link_up = link_up;
5998         adapter->link_speed = link_speed;
5999 }
6000
6001 /**
6002  * ixgbe_watchdog_link_is_up - update netif_carrier status and
6003  *                             print link up message
6004  * @adapter - pointer to the device adapter structure
6005  **/
6006 static void ixgbe_watchdog_link_is_up(struct ixgbe_adapter *adapter)
6007 {
6008         struct net_device *netdev = adapter->netdev;
6009         struct ixgbe_hw *hw = &adapter->hw;
6010         u32 link_speed = adapter->link_speed;
6011         bool flow_rx, flow_tx;
6012
6013         /* only continue if link was previously down */
6014         if (netif_carrier_ok(netdev))
6015                 return;
6016
6017         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
6018
6019         switch (hw->mac.type) {
6020         case ixgbe_mac_82598EB: {
6021                 u32 frctl = IXGBE_READ_REG(hw, IXGBE_FCTRL);
6022                 u32 rmcs = IXGBE_READ_REG(hw, IXGBE_RMCS);
6023                 flow_rx = !!(frctl & IXGBE_FCTRL_RFCE);
6024                 flow_tx = !!(rmcs & IXGBE_RMCS_TFCE_802_3X);
6025         }
6026                 break;
6027         case ixgbe_mac_X540:
6028         case ixgbe_mac_82599EB: {
6029                 u32 mflcn = IXGBE_READ_REG(hw, IXGBE_MFLCN);
6030                 u32 fccfg = IXGBE_READ_REG(hw, IXGBE_FCCFG);
6031                 flow_rx = !!(mflcn & IXGBE_MFLCN_RFCE);
6032                 flow_tx = !!(fccfg & IXGBE_FCCFG_TFCE_802_3X);
6033         }
6034                 break;
6035         default:
6036                 flow_tx = false;
6037                 flow_rx = false;
6038                 break;
6039         }
6040         e_info(drv, "NIC Link is Up %s, Flow Control: %s\n",
6041                (link_speed == IXGBE_LINK_SPEED_10GB_FULL ?
6042                "10 Gbps" :
6043                (link_speed == IXGBE_LINK_SPEED_1GB_FULL ?
6044                "1 Gbps" :
6045                (link_speed == IXGBE_LINK_SPEED_100_FULL ?
6046                "100 Mbps" :
6047                "unknown speed"))),
6048                ((flow_rx && flow_tx) ? "RX/TX" :
6049                (flow_rx ? "RX" :
6050                (flow_tx ? "TX" : "None"))));
6051
6052         netif_carrier_on(netdev);
6053 #ifdef HAVE_IPLINK_VF_CONFIG
6054         ixgbe_check_vf_rate_limit(adapter);
6055 #endif /* HAVE_IPLINK_VF_CONFIG */
6056 }
6057
6058 /**
6059  * ixgbe_watchdog_link_is_down - update netif_carrier status and
6060  *                               print link down message
6061  * @adapter - pointer to the adapter structure
6062  **/
6063 static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter* adapter)
6064 {
6065         struct net_device *netdev = adapter->netdev;
6066         struct ixgbe_hw *hw = &adapter->hw;
6067
6068         adapter->link_up = false;
6069         adapter->link_speed = 0;
6070
6071         /* only continue if link was up previously */
6072         if (!netif_carrier_ok(netdev))
6073                 return;
6074
6075         /* poll for SFP+ cable when link is down */
6076         if (ixgbe_is_sfp(hw) && hw->mac.type == ixgbe_mac_82598EB)
6077                 adapter->flags2 |= IXGBE_FLAG2_SEARCH_FOR_SFP;
6078
6079         e_info(drv, "NIC Link is Down\n");
6080         netif_carrier_off(netdev);
6081 }
6082
6083 /**
6084  * ixgbe_watchdog_flush_tx - flush queues on link down
6085  * @adapter - pointer to the device adapter structure
6086  **/
6087 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
6088 {
6089         int i;
6090         int some_tx_pending = 0;
6091
6092         if (!netif_carrier_ok(adapter->netdev)) {
6093                 for (i = 0; i < adapter->num_tx_queues; i++) {
6094                         struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
6095                         if (tx_ring->next_to_use != tx_ring->next_to_clean) {
6096                                 some_tx_pending = 1;
6097                                 break;
6098                         }
6099                 }
6100
6101                 if (some_tx_pending) {
6102                         /* We've lost link, so the controller stops DMA,
6103                          * but we've got queued Tx work that's never going
6104                          * to get done, so reset controller to flush Tx.
6105                          * (Do the reset outside of interrupt context).
6106                          */
6107                         adapter->flags2 |= IXGBE_FLAG2_RESET_REQUESTED;
6108                 }
6109         }
6110 }
6111
6112 static void ixgbe_spoof_check(struct ixgbe_adapter *adapter)
6113 {
6114         u32 ssvpc;
6115
6116         /* Do not perform spoof check for 82598 */
6117         if (adapter->hw.mac.type == ixgbe_mac_82598EB)
6118                 return;
6119
6120         ssvpc = IXGBE_READ_REG(&adapter->hw, IXGBE_SSVPC);
6121
6122         /*
6123          * ssvpc register is cleared on read, if zero then no
6124          * spoofed packets in the last interval.
6125          */
6126         if (!ssvpc)
6127                 return;
6128
6129         e_warn(drv, "%d Spoofed packets detected\n", ssvpc);
6130 }
6131
6132 /**
6133  * ixgbe_watchdog_subtask - check and bring link up
6134  * @adapter - pointer to the device adapter structure
6135  **/
6136 static void ixgbe_watchdog_subtask(struct ixgbe_adapter *adapter)
6137 {
6138         /* if interface is down do nothing */
6139         if (test_bit(__IXGBE_DOWN, &adapter->state))
6140                 return;
6141
6142         ixgbe_watchdog_update_link(adapter);
6143
6144         if (adapter->link_up)
6145                 ixgbe_watchdog_link_is_up(adapter);
6146         else
6147                 ixgbe_watchdog_link_is_down(adapter);
6148
6149         ixgbe_spoof_check(adapter);
6150         ixgbe_update_stats(adapter);
6151
6152         ixgbe_watchdog_flush_tx(adapter);
6153 }
6154
6155 /**
6156  * ixgbe_sfp_detection_subtask - poll for SFP+ cable
6157  * @adapter - the ixgbe adapter structure
6158  **/
6159 static void ixgbe_sfp_detection_subtask(struct ixgbe_adapter *adapter)
6160 {
6161         struct ixgbe_hw *hw = &adapter->hw;
6162         s32 err;
6163
6164         /* not searching for SFP so there is nothing to do here */
6165         if (!(adapter->flags2 & IXGBE_FLAG2_SEARCH_FOR_SFP) &&
6166             !(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6167                 return;
6168
6169         /* someone else is in init, wait until next service event */
6170         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6171                 return;
6172
6173         err = hw->phy.ops.identify_sfp(hw);
6174         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6175                 goto sfp_out;
6176
6177         if (err == IXGBE_ERR_SFP_NOT_PRESENT) {
6178                 /* If no cable is present, then we need to reset
6179                  * the next time we find a good cable. */
6180                 adapter->flags2 |= IXGBE_FLAG2_SFP_NEEDS_RESET;
6181         }
6182
6183         /* exit on error */
6184         if (err)
6185                 goto sfp_out;
6186
6187         /* exit if reset not needed */
6188         if (!(adapter->flags2 & IXGBE_FLAG2_SFP_NEEDS_RESET))
6189                 goto sfp_out;
6190
6191         adapter->flags2 &= ~IXGBE_FLAG2_SFP_NEEDS_RESET;
6192
6193         /*
6194          * A module may be identified correctly, but the EEPROM may not have
6195          * support for that module.  setup_sfp() will fail in that case, so
6196          * we should not allow that module to load.
6197          */
6198         if (hw->mac.type == ixgbe_mac_82598EB)
6199                 err = hw->phy.ops.reset(hw);
6200         else
6201                 err = hw->mac.ops.setup_sfp(hw);
6202
6203         if (err == IXGBE_ERR_SFP_NOT_SUPPORTED)
6204                 goto sfp_out;
6205
6206         adapter->flags |= IXGBE_FLAG_NEED_LINK_CONFIG;
6207         e_info(probe, "detected SFP+: %d\n", hw->phy.sfp_type);
6208
6209 sfp_out:
6210         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6211
6212         if ((err == IXGBE_ERR_SFP_NOT_SUPPORTED) &&
6213             (adapter->netdev->reg_state == NETREG_REGISTERED)) {
6214                 e_dev_err("failed to initialize because an unsupported "
6215                           "SFP+ module type was detected.\n");
6216                 e_dev_err("Reload the driver after installing a "
6217                           "supported module.\n");
6218                 unregister_netdev(adapter->netdev);
6219         }
6220 }
6221
6222 /**
6223  * ixgbe_sfp_link_config_subtask - set up link SFP after module install
6224  * @adapter - the ixgbe adapter structure
6225  **/
6226 static void ixgbe_sfp_link_config_subtask(struct ixgbe_adapter *adapter)
6227 {
6228         struct ixgbe_hw *hw = &adapter->hw;
6229         u32 autoneg;
6230         bool negotiation;
6231
6232         if (!(adapter->flags & IXGBE_FLAG_NEED_LINK_CONFIG))
6233                 return;
6234
6235         /* someone else is in init, wait until next service event */
6236         if (test_and_set_bit(__IXGBE_IN_SFP_INIT, &adapter->state))
6237                 return;
6238
6239         adapter->flags &= ~IXGBE_FLAG_NEED_LINK_CONFIG;
6240
6241         autoneg = hw->phy.autoneg_advertised;
6242         if ((!autoneg) && (hw->mac.ops.get_link_capabilities))
6243                 hw->mac.ops.get_link_capabilities(hw, &autoneg, &negotiation);
6244         hw->mac.autotry_restart = false;
6245         if (hw->mac.ops.setup_link)
6246                 hw->mac.ops.setup_link(hw, autoneg, negotiation, true);
6247
6248         adapter->flags |= IXGBE_FLAG_NEED_LINK_UPDATE;
6249         adapter->link_check_timeout = jiffies;
6250         clear_bit(__IXGBE_IN_SFP_INIT, &adapter->state);
6251 }
6252
6253 /**
6254  * ixgbe_service_timer - Timer Call-back
6255  * @data: pointer to adapter cast into an unsigned long
6256  **/
6257 static void ixgbe_service_timer(unsigned long data)
6258 {
6259         struct ixgbe_adapter *adapter = (struct ixgbe_adapter *)data;
6260         unsigned long next_event_offset;
6261
6262         /* poll faster when waiting for link */
6263         if (adapter->flags & IXGBE_FLAG_NEED_LINK_UPDATE)
6264                 next_event_offset = HZ / 10;
6265         else
6266                 next_event_offset = HZ * 2;
6267
6268         /* Reset the timer */
6269         mod_timer(&adapter->service_timer, next_event_offset + jiffies);
6270
6271         ixgbe_service_event_schedule(adapter);
6272 }
6273
6274 static void ixgbe_reset_subtask(struct ixgbe_adapter *adapter)
6275 {
6276         if (!(adapter->flags2 & IXGBE_FLAG2_RESET_REQUESTED))
6277                 return;
6278
6279         adapter->flags2 &= ~IXGBE_FLAG2_RESET_REQUESTED;
6280
6281         /* If we're already down or resetting, just bail */
6282         if (test_bit(__IXGBE_DOWN, &adapter->state) ||
6283             test_bit(__IXGBE_RESETTING, &adapter->state))
6284                 return;
6285
6286         ixgbe_dump(adapter);
6287         netdev_err(adapter->netdev, "Reset adapter\n");
6288         adapter->tx_timeout_count++;
6289
6290         ixgbe_reinit_locked(adapter);
6291 }
6292
6293 /**
6294  * ixgbe_service_task - manages and runs subtasks
6295  * @work: pointer to work_struct containing our data
6296  **/
6297 static void ixgbe_service_task(struct work_struct *work)
6298 {
6299         struct ixgbe_adapter *adapter = container_of(work,
6300                                                      struct ixgbe_adapter,
6301                                                      service_task);
6302
6303         ixgbe_reset_subtask(adapter);
6304         ixgbe_sfp_detection_subtask(adapter);
6305         ixgbe_sfp_link_config_subtask(adapter);
6306         ixgbe_check_overtemp_subtask(adapter);
6307         ixgbe_watchdog_subtask(adapter);
6308         ixgbe_fdir_reinit_subtask(adapter);
6309         ixgbe_check_hang_subtask(adapter);
6310
6311         ixgbe_service_event_complete(adapter);
6312 }
6313
6314 static int ixgbe_tso(struct ixgbe_adapter *adapter,
6315                      struct ixgbe_ring *tx_ring, struct sk_buff *skb,
6316                      u32 tx_flags, u8 *hdr_len, __be16 protocol)
6317 {
6318         struct ixgbe_adv_tx_context_desc *context_desc;
6319         unsigned int i;
6320         int err;
6321         struct ixgbe_tx_buffer *tx_buffer_info;
6322         u32 vlan_macip_lens = 0, type_tucmd_mlhl;
6323         u32 mss_l4len_idx, l4len;
6324
6325         if (skb_is_gso(skb)) {
6326                 if (skb_header_cloned(skb)) {
6327                         err = pskb_expand_head(skb, 0, 0, GFP_ATOMIC);
6328                         if (err)
6329                                 return err;
6330                 }
6331                 l4len = tcp_hdrlen(skb);
6332                 *hdr_len += l4len;
6333
6334                 if (protocol == htons(ETH_P_IP)) {
6335                         struct iphdr *iph = ip_hdr(skb);
6336                         iph->tot_len = 0;
6337                         iph->check = 0;
6338                         tcp_hdr(skb)->check = ~csum_tcpudp_magic(iph->saddr,
6339                                                                  iph->daddr, 0,
6340                                                                  IPPROTO_TCP,
6341                                                                  0);
6342                 } else if (skb_is_gso_v6(skb)) {
6343                         ipv6_hdr(skb)->payload_len = 0;
6344                         tcp_hdr(skb)->check =
6345                             ~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
6346                                              &ipv6_hdr(skb)->daddr,
6347                                              0, IPPROTO_TCP, 0);
6348                 }
6349
6350                 i = tx_ring->next_to_use;
6351
6352                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6353                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6354
6355                 /* VLAN MACLEN IPLEN */
6356                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6357                         vlan_macip_lens |=
6358                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6359                 vlan_macip_lens |= ((skb_network_offset(skb)) <<
6360                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6361                 *hdr_len += skb_network_offset(skb);
6362                 vlan_macip_lens |=
6363                     (skb_transport_header(skb) - skb_network_header(skb));
6364                 *hdr_len +=
6365                     (skb_transport_header(skb) - skb_network_header(skb));
6366                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6367                 context_desc->seqnum_seed = 0;
6368
6369                 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
6370                 type_tucmd_mlhl = (IXGBE_TXD_CMD_DEXT |
6371                                    IXGBE_ADVTXD_DTYP_CTXT);
6372
6373                 if (protocol == htons(ETH_P_IP))
6374                         type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_IPV4;
6375                 type_tucmd_mlhl |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6376                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6377
6378                 /* MSS L4LEN IDX */
6379                 mss_l4len_idx =
6380                     (skb_shinfo(skb)->gso_size << IXGBE_ADVTXD_MSS_SHIFT);
6381                 mss_l4len_idx |= (l4len << IXGBE_ADVTXD_L4LEN_SHIFT);
6382                 /* use index 1 for TSO */
6383                 mss_l4len_idx |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6384                 context_desc->mss_l4len_idx = cpu_to_le32(mss_l4len_idx);
6385
6386                 tx_buffer_info->time_stamp = jiffies;
6387                 tx_buffer_info->next_to_watch = i;
6388
6389                 i++;
6390                 if (i == tx_ring->count)
6391                         i = 0;
6392                 tx_ring->next_to_use = i;
6393
6394                 return true;
6395         }
6396         return false;
6397 }
6398
6399 static u32 ixgbe_psum(struct ixgbe_adapter *adapter, struct sk_buff *skb,
6400                       __be16 protocol)
6401 {
6402         u32 rtn = 0;
6403
6404         switch (protocol) {
6405         case cpu_to_be16(ETH_P_IP):
6406                 rtn |= IXGBE_ADVTXD_TUCMD_IPV4;
6407                 switch (ip_hdr(skb)->protocol) {
6408                 case IPPROTO_TCP:
6409                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6410                         break;
6411                 case IPPROTO_SCTP:
6412                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6413                         break;
6414                 }
6415                 break;
6416         case cpu_to_be16(ETH_P_IPV6):
6417                 /* XXX what about other V6 headers?? */
6418                 switch (ipv6_hdr(skb)->nexthdr) {
6419                 case IPPROTO_TCP:
6420                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_TCP;
6421                         break;
6422                 case IPPROTO_SCTP:
6423                         rtn |= IXGBE_ADVTXD_TUCMD_L4T_SCTP;
6424                         break;
6425                 }
6426                 break;
6427         default:
6428                 if (unlikely(net_ratelimit()))
6429                         e_warn(probe, "partial checksum but proto=%x!\n",
6430                                protocol);
6431                 break;
6432         }
6433
6434         return rtn;
6435 }
6436
6437 static bool ixgbe_tx_csum(struct ixgbe_adapter *adapter,
6438                           struct ixgbe_ring *tx_ring,
6439                           struct sk_buff *skb, u32 tx_flags,
6440                           __be16 protocol)
6441 {
6442         struct ixgbe_adv_tx_context_desc *context_desc;
6443         unsigned int i;
6444         struct ixgbe_tx_buffer *tx_buffer_info;
6445         u32 vlan_macip_lens = 0, type_tucmd_mlhl = 0;
6446
6447         if (skb->ip_summed == CHECKSUM_PARTIAL ||
6448             (tx_flags & IXGBE_TX_FLAGS_VLAN)) {
6449                 i = tx_ring->next_to_use;
6450                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6451                 context_desc = IXGBE_TX_CTXTDESC_ADV(tx_ring, i);
6452
6453                 if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6454                         vlan_macip_lens |=
6455                             (tx_flags & IXGBE_TX_FLAGS_VLAN_MASK);
6456                 vlan_macip_lens |= (skb_network_offset(skb) <<
6457                                     IXGBE_ADVTXD_MACLEN_SHIFT);
6458                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6459                         vlan_macip_lens |= (skb_transport_header(skb) -
6460                                             skb_network_header(skb));
6461
6462                 context_desc->vlan_macip_lens = cpu_to_le32(vlan_macip_lens);
6463                 context_desc->seqnum_seed = 0;
6464
6465                 type_tucmd_mlhl |= (IXGBE_TXD_CMD_DEXT |
6466                                     IXGBE_ADVTXD_DTYP_CTXT);
6467
6468                 if (skb->ip_summed == CHECKSUM_PARTIAL)
6469                         type_tucmd_mlhl |= ixgbe_psum(adapter, skb, protocol);
6470
6471                 context_desc->type_tucmd_mlhl = cpu_to_le32(type_tucmd_mlhl);
6472                 /* use index zero for tx checksum offload */
6473                 context_desc->mss_l4len_idx = 0;
6474
6475                 tx_buffer_info->time_stamp = jiffies;
6476                 tx_buffer_info->next_to_watch = i;
6477
6478                 i++;
6479                 if (i == tx_ring->count)
6480                         i = 0;
6481                 tx_ring->next_to_use = i;
6482
6483                 return true;
6484         }
6485
6486         return false;
6487 }
6488
6489 static int ixgbe_tx_map(struct ixgbe_adapter *adapter,
6490                         struct ixgbe_ring *tx_ring,
6491                         struct sk_buff *skb, u32 tx_flags,
6492                         unsigned int first, const u8 hdr_len)
6493 {
6494         struct device *dev = tx_ring->dev;
6495         struct ixgbe_tx_buffer *tx_buffer_info;
6496         unsigned int len;
6497         unsigned int total = skb->len;
6498         unsigned int offset = 0, size, count = 0, i;
6499         unsigned int nr_frags = skb_shinfo(skb)->nr_frags;
6500         unsigned int f;
6501         unsigned int bytecount = skb->len;
6502         u16 gso_segs = 1;
6503
6504         i = tx_ring->next_to_use;
6505
6506         if (tx_flags & IXGBE_TX_FLAGS_FCOE)
6507                 /* excluding fcoe_crc_eof for FCoE */
6508                 total -= sizeof(struct fcoe_crc_eof);
6509
6510         len = min(skb_headlen(skb), total);
6511         while (len) {
6512                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6513                 size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6514
6515                 tx_buffer_info->length = size;
6516                 tx_buffer_info->mapped_as_page = false;
6517                 tx_buffer_info->dma = dma_map_single(dev,
6518                                                      skb->data + offset,
6519                                                      size, DMA_TO_DEVICE);
6520                 if (dma_mapping_error(dev, tx_buffer_info->dma))
6521                         goto dma_error;
6522                 tx_buffer_info->time_stamp = jiffies;
6523                 tx_buffer_info->next_to_watch = i;
6524
6525                 len -= size;
6526                 total -= size;
6527                 offset += size;
6528                 count++;
6529
6530                 if (len) {
6531                         i++;
6532                         if (i == tx_ring->count)
6533                                 i = 0;
6534                 }
6535         }
6536
6537         for (f = 0; f < nr_frags; f++) {
6538                 struct skb_frag_struct *frag;
6539
6540                 frag = &skb_shinfo(skb)->frags[f];
6541                 len = min((unsigned int)frag->size, total);
6542                 offset = frag->page_offset;
6543
6544                 while (len) {
6545                         i++;
6546                         if (i == tx_ring->count)
6547                                 i = 0;
6548
6549                         tx_buffer_info = &tx_ring->tx_buffer_info[i];
6550                         size = min(len, (uint)IXGBE_MAX_DATA_PER_TXD);
6551
6552                         tx_buffer_info->length = size;
6553                         tx_buffer_info->dma = dma_map_page(dev,
6554                                                            frag->page,
6555                                                            offset, size,
6556                                                            DMA_TO_DEVICE);
6557                         tx_buffer_info->mapped_as_page = true;
6558                         if (dma_mapping_error(dev, tx_buffer_info->dma))
6559                                 goto dma_error;
6560                         tx_buffer_info->time_stamp = jiffies;
6561                         tx_buffer_info->next_to_watch = i;
6562
6563                         len -= size;
6564                         total -= size;
6565                         offset += size;
6566                         count++;
6567                 }
6568                 if (total == 0)
6569                         break;
6570         }
6571
6572         if (tx_flags & IXGBE_TX_FLAGS_TSO)
6573                 gso_segs = skb_shinfo(skb)->gso_segs;
6574 #ifdef IXGBE_FCOE
6575         /* adjust for FCoE Sequence Offload */
6576         else if (tx_flags & IXGBE_TX_FLAGS_FSO)
6577                 gso_segs = DIV_ROUND_UP(skb->len - hdr_len,
6578                                         skb_shinfo(skb)->gso_size);
6579 #endif /* IXGBE_FCOE */
6580         bytecount += (gso_segs - 1) * hdr_len;
6581
6582         /* multiply data chunks by size of headers */
6583         tx_ring->tx_buffer_info[i].bytecount = bytecount;
6584         tx_ring->tx_buffer_info[i].gso_segs = gso_segs;
6585         tx_ring->tx_buffer_info[i].skb = skb;
6586         tx_ring->tx_buffer_info[first].next_to_watch = i;
6587
6588         return count;
6589
6590 dma_error:
6591         e_dev_err("TX DMA map failed\n");
6592
6593         /* clear timestamp and dma mappings for failed tx_buffer_info map */
6594         tx_buffer_info->dma = 0;
6595         tx_buffer_info->time_stamp = 0;
6596         tx_buffer_info->next_to_watch = 0;
6597         if (count)
6598                 count--;
6599
6600         /* clear timestamp and dma mappings for remaining portion of packet */
6601         while (count--) {
6602                 if (i == 0)
6603                         i += tx_ring->count;
6604                 i--;
6605                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6606                 ixgbe_unmap_and_free_tx_resource(tx_ring, tx_buffer_info);
6607         }
6608
6609         return 0;
6610 }
6611
6612 static void ixgbe_tx_queue(struct ixgbe_ring *tx_ring,
6613                            int tx_flags, int count, u32 paylen, u8 hdr_len)
6614 {
6615         union ixgbe_adv_tx_desc *tx_desc = NULL;
6616         struct ixgbe_tx_buffer *tx_buffer_info;
6617         u32 olinfo_status = 0, cmd_type_len = 0;
6618         unsigned int i;
6619         u32 txd_cmd = IXGBE_TXD_CMD_EOP | IXGBE_TXD_CMD_RS | IXGBE_TXD_CMD_IFCS;
6620
6621         cmd_type_len |= IXGBE_ADVTXD_DTYP_DATA;
6622
6623         cmd_type_len |= IXGBE_ADVTXD_DCMD_IFCS | IXGBE_ADVTXD_DCMD_DEXT;
6624
6625         if (tx_flags & IXGBE_TX_FLAGS_VLAN)
6626                 cmd_type_len |= IXGBE_ADVTXD_DCMD_VLE;
6627
6628         if (tx_flags & IXGBE_TX_FLAGS_TSO) {
6629                 cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6630
6631                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6632                                  IXGBE_ADVTXD_POPTS_SHIFT;
6633
6634                 /* use index 1 context for tso */
6635                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6636                 if (tx_flags & IXGBE_TX_FLAGS_IPV4)
6637                         olinfo_status |= IXGBE_TXD_POPTS_IXSM <<
6638                                          IXGBE_ADVTXD_POPTS_SHIFT;
6639
6640         } else if (tx_flags & IXGBE_TX_FLAGS_CSUM)
6641                 olinfo_status |= IXGBE_TXD_POPTS_TXSM <<
6642                                  IXGBE_ADVTXD_POPTS_SHIFT;
6643
6644         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6645                 olinfo_status |= IXGBE_ADVTXD_CC;
6646                 olinfo_status |= (1 << IXGBE_ADVTXD_IDX_SHIFT);
6647                 if (tx_flags & IXGBE_TX_FLAGS_FSO)
6648                         cmd_type_len |= IXGBE_ADVTXD_DCMD_TSE;
6649         }
6650
6651         olinfo_status |= ((paylen - hdr_len) << IXGBE_ADVTXD_PAYLEN_SHIFT);
6652
6653         i = tx_ring->next_to_use;
6654         while (count--) {
6655                 tx_buffer_info = &tx_ring->tx_buffer_info[i];
6656                 tx_desc = IXGBE_TX_DESC_ADV(tx_ring, i);
6657                 tx_desc->read.buffer_addr = cpu_to_le64(tx_buffer_info->dma);
6658                 tx_desc->read.cmd_type_len =
6659                         cpu_to_le32(cmd_type_len | tx_buffer_info->length);
6660                 tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
6661                 i++;
6662                 if (i == tx_ring->count)
6663                         i = 0;
6664         }
6665
6666         tx_desc->read.cmd_type_len |= cpu_to_le32(txd_cmd);
6667
6668         /*
6669          * Force memory writes to complete before letting h/w
6670          * know there are new descriptors to fetch.  (Only
6671          * applicable for weak-ordered memory model archs,
6672          * such as IA-64).
6673          */
6674         wmb();
6675
6676         tx_ring->next_to_use = i;
6677         writel(i, tx_ring->tail);
6678 }
6679
6680 static void ixgbe_atr(struct ixgbe_ring *ring, struct sk_buff *skb,
6681                       u32 tx_flags, __be16 protocol)
6682 {
6683         struct ixgbe_q_vector *q_vector = ring->q_vector;
6684         union ixgbe_atr_hash_dword input = { .dword = 0 };
6685         union ixgbe_atr_hash_dword common = { .dword = 0 };
6686         union {
6687                 unsigned char *network;
6688                 struct iphdr *ipv4;
6689                 struct ipv6hdr *ipv6;
6690         } hdr;
6691         struct tcphdr *th;
6692         __be16 vlan_id;
6693
6694         /* if ring doesn't have a interrupt vector, cannot perform ATR */
6695         if (!q_vector)
6696                 return;
6697
6698         /* do nothing if sampling is disabled */
6699         if (!ring->atr_sample_rate)
6700                 return;
6701
6702         ring->atr_count++;
6703
6704         /* snag network header to get L4 type and address */
6705         hdr.network = skb_network_header(skb);
6706
6707         /* Currently only IPv4/IPv6 with TCP is supported */
6708         if ((protocol != __constant_htons(ETH_P_IPV6) ||
6709              hdr.ipv6->nexthdr != IPPROTO_TCP) &&
6710             (protocol != __constant_htons(ETH_P_IP) ||
6711              hdr.ipv4->protocol != IPPROTO_TCP))
6712                 return;
6713
6714         th = tcp_hdr(skb);
6715
6716         /* skip this packet since the socket is closing */
6717         if (th->fin)
6718                 return;
6719
6720         /* sample on all syn packets or once every atr sample count */
6721         if (!th->syn && (ring->atr_count < ring->atr_sample_rate))
6722                 return;
6723
6724         /* reset sample count */
6725         ring->atr_count = 0;
6726
6727         vlan_id = htons(tx_flags >> IXGBE_TX_FLAGS_VLAN_SHIFT);
6728
6729         /*
6730          * src and dst are inverted, think how the receiver sees them
6731          *
6732          * The input is broken into two sections, a non-compressed section
6733          * containing vm_pool, vlan_id, and flow_type.  The rest of the data
6734          * is XORed together and stored in the compressed dword.
6735          */
6736         input.formatted.vlan_id = vlan_id;
6737
6738         /*
6739          * since src port and flex bytes occupy the same word XOR them together
6740          * and write the value to source port portion of compressed dword
6741          */
6742         if (vlan_id)
6743                 common.port.src ^= th->dest ^ __constant_htons(ETH_P_8021Q);
6744         else
6745                 common.port.src ^= th->dest ^ protocol;
6746         common.port.dst ^= th->source;
6747
6748         if (protocol == __constant_htons(ETH_P_IP)) {
6749                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV4;
6750                 common.ip ^= hdr.ipv4->saddr ^ hdr.ipv4->daddr;
6751         } else {
6752                 input.formatted.flow_type = IXGBE_ATR_FLOW_TYPE_TCPV6;
6753                 common.ip ^= hdr.ipv6->saddr.s6_addr32[0] ^
6754                              hdr.ipv6->saddr.s6_addr32[1] ^
6755                              hdr.ipv6->saddr.s6_addr32[2] ^
6756                              hdr.ipv6->saddr.s6_addr32[3] ^
6757                              hdr.ipv6->daddr.s6_addr32[0] ^
6758                              hdr.ipv6->daddr.s6_addr32[1] ^
6759                              hdr.ipv6->daddr.s6_addr32[2] ^
6760                              hdr.ipv6->daddr.s6_addr32[3];
6761         }
6762
6763         /* This assumes the Rx queue and Tx queue are bound to the same CPU */
6764         ixgbe_fdir_add_signature_filter_82599(&q_vector->adapter->hw,
6765                                               input, common, ring->queue_index);
6766 }
6767
6768 static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6769 {
6770         netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
6771         /* Herbert's original patch had:
6772          *  smp_mb__after_netif_stop_queue();
6773          * but since that doesn't exist yet, just open code it. */
6774         smp_mb();
6775
6776         /* We need to check again in a case another CPU has just
6777          * made room available. */
6778         if (likely(IXGBE_DESC_UNUSED(tx_ring) < size))
6779                 return -EBUSY;
6780
6781         /* A reprieve! - use start_queue because it doesn't call schedule */
6782         netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
6783         ++tx_ring->tx_stats.restart_queue;
6784         return 0;
6785 }
6786
6787 static int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, int size)
6788 {
6789         if (likely(IXGBE_DESC_UNUSED(tx_ring) >= size))
6790                 return 0;
6791         return __ixgbe_maybe_stop_tx(tx_ring, size);
6792 }
6793
6794 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb)
6795 {
6796         struct ixgbe_adapter *adapter = netdev_priv(dev);
6797         int txq = smp_processor_id();
6798 #ifdef IXGBE_FCOE
6799         __be16 protocol;
6800
6801         protocol = vlan_get_protocol(skb);
6802
6803         if (((protocol == htons(ETH_P_FCOE)) ||
6804             (protocol == htons(ETH_P_FIP))) &&
6805             (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)) {
6806                 txq &= (adapter->ring_feature[RING_F_FCOE].indices - 1);
6807                 txq += adapter->ring_feature[RING_F_FCOE].mask;
6808                 return txq;
6809         }
6810 #endif
6811
6812         if (adapter->flags & IXGBE_FLAG_FDIR_HASH_CAPABLE) {
6813                 while (unlikely(txq >= dev->real_num_tx_queues))
6814                         txq -= dev->real_num_tx_queues;
6815                 return txq;
6816         }
6817
6818         return skb_tx_hash(dev, skb);
6819 }
6820
6821 netdev_tx_t ixgbe_xmit_frame_ring(struct sk_buff *skb,
6822                           struct ixgbe_adapter *adapter,
6823                           struct ixgbe_ring *tx_ring)
6824 {
6825         unsigned int first;
6826         unsigned int tx_flags = 0;
6827         u8 hdr_len = 0;
6828         int tso;
6829         int count = 0;
6830         unsigned int f;
6831         __be16 protocol;
6832
6833         protocol = vlan_get_protocol(skb);
6834
6835         if (vlan_tx_tag_present(skb)) {
6836                 tx_flags |= vlan_tx_tag_get(skb);
6837                 if (adapter->flags & IXGBE_FLAG_DCB_ENABLED) {
6838                         tx_flags &= ~IXGBE_TX_FLAGS_VLAN_PRIO_MASK;
6839                         tx_flags |= tx_ring->dcb_tc << 13;
6840                 }
6841                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6842                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6843         } else if (adapter->flags & IXGBE_FLAG_DCB_ENABLED &&
6844                    skb->priority != TC_PRIO_CONTROL) {
6845                 tx_flags |= tx_ring->dcb_tc << 13;
6846                 tx_flags <<= IXGBE_TX_FLAGS_VLAN_SHIFT;
6847                 tx_flags |= IXGBE_TX_FLAGS_VLAN;
6848         }
6849
6850 #ifdef IXGBE_FCOE
6851         /* for FCoE with DCB, we force the priority to what
6852          * was specified by the switch */
6853         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED &&
6854             (protocol == htons(ETH_P_FCOE)))
6855                 tx_flags |= IXGBE_TX_FLAGS_FCOE;
6856 #endif
6857
6858         /* four things can cause us to need a context descriptor */
6859         if (skb_is_gso(skb) ||
6860             (skb->ip_summed == CHECKSUM_PARTIAL) ||
6861             (tx_flags & IXGBE_TX_FLAGS_VLAN) ||
6862             (tx_flags & IXGBE_TX_FLAGS_FCOE))
6863                 count++;
6864
6865         count += TXD_USE_COUNT(skb_headlen(skb));
6866         for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
6867                 count += TXD_USE_COUNT(skb_shinfo(skb)->frags[f].size);
6868
6869         if (ixgbe_maybe_stop_tx(tx_ring, count)) {
6870                 tx_ring->tx_stats.tx_busy++;
6871                 return NETDEV_TX_BUSY;
6872         }
6873
6874         first = tx_ring->next_to_use;
6875         if (tx_flags & IXGBE_TX_FLAGS_FCOE) {
6876 #ifdef IXGBE_FCOE
6877                 /* setup tx offload for FCoE */
6878                 tso = ixgbe_fso(adapter, tx_ring, skb, tx_flags, &hdr_len);
6879                 if (tso < 0) {
6880                         dev_kfree_skb_any(skb);
6881                         return NETDEV_TX_OK;
6882                 }
6883                 if (tso)
6884                         tx_flags |= IXGBE_TX_FLAGS_FSO;
6885 #endif /* IXGBE_FCOE */
6886         } else {
6887                 if (protocol == htons(ETH_P_IP))
6888                         tx_flags |= IXGBE_TX_FLAGS_IPV4;
6889                 tso = ixgbe_tso(adapter, tx_ring, skb, tx_flags, &hdr_len,
6890                                 protocol);
6891                 if (tso < 0) {
6892                         dev_kfree_skb_any(skb);
6893                         return NETDEV_TX_OK;
6894                 }
6895
6896                 if (tso)
6897                         tx_flags |= IXGBE_TX_FLAGS_TSO;
6898                 else if (ixgbe_tx_csum(adapter, tx_ring, skb, tx_flags,
6899                                        protocol) &&
6900                          (skb->ip_summed == CHECKSUM_PARTIAL))
6901                         tx_flags |= IXGBE_TX_FLAGS_CSUM;
6902         }
6903
6904         count = ixgbe_tx_map(adapter, tx_ring, skb, tx_flags, first, hdr_len);
6905         if (count) {
6906                 /* add the ATR filter if ATR is on */
6907                 if (test_bit(__IXGBE_TX_FDIR_INIT_DONE, &tx_ring->state))
6908                         ixgbe_atr(tx_ring, skb, tx_flags, protocol);
6909                 ixgbe_tx_queue(tx_ring, tx_flags, count, skb->len, hdr_len);
6910                 ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
6911
6912         } else {
6913                 dev_kfree_skb_any(skb);
6914                 tx_ring->tx_buffer_info[first].time_stamp = 0;
6915                 tx_ring->next_to_use = first;
6916         }
6917
6918         return NETDEV_TX_OK;
6919 }
6920
6921 static netdev_tx_t ixgbe_xmit_frame(struct sk_buff *skb, struct net_device *netdev)
6922 {
6923         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6924         struct ixgbe_ring *tx_ring;
6925
6926         tx_ring = adapter->tx_ring[skb->queue_mapping];
6927         return ixgbe_xmit_frame_ring(skb, adapter, tx_ring);
6928 }
6929
6930 /**
6931  * ixgbe_set_mac - Change the Ethernet Address of the NIC
6932  * @netdev: network interface device structure
6933  * @p: pointer to an address structure
6934  *
6935  * Returns 0 on success, negative on failure
6936  **/
6937 static int ixgbe_set_mac(struct net_device *netdev, void *p)
6938 {
6939         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6940         struct ixgbe_hw *hw = &adapter->hw;
6941         struct sockaddr *addr = p;
6942
6943         if (!is_valid_ether_addr(addr->sa_data))
6944                 return -EADDRNOTAVAIL;
6945
6946         memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
6947         memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);
6948
6949         hw->mac.ops.set_rar(hw, 0, hw->mac.addr, adapter->num_vfs,
6950                             IXGBE_RAH_AV);
6951
6952         return 0;
6953 }
6954
6955 static int
6956 ixgbe_mdio_read(struct net_device *netdev, int prtad, int devad, u16 addr)
6957 {
6958         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6959         struct ixgbe_hw *hw = &adapter->hw;
6960         u16 value;
6961         int rc;
6962
6963         if (prtad != hw->phy.mdio.prtad)
6964                 return -EINVAL;
6965         rc = hw->phy.ops.read_reg(hw, addr, devad, &value);
6966         if (!rc)
6967                 rc = value;
6968         return rc;
6969 }
6970
6971 static int ixgbe_mdio_write(struct net_device *netdev, int prtad, int devad,
6972                             u16 addr, u16 value)
6973 {
6974         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6975         struct ixgbe_hw *hw = &adapter->hw;
6976
6977         if (prtad != hw->phy.mdio.prtad)
6978                 return -EINVAL;
6979         return hw->phy.ops.write_reg(hw, addr, devad, value);
6980 }
6981
6982 static int ixgbe_ioctl(struct net_device *netdev, struct ifreq *req, int cmd)
6983 {
6984         struct ixgbe_adapter *adapter = netdev_priv(netdev);
6985
6986         return mdio_mii_ioctl(&adapter->hw.phy.mdio, if_mii(req), cmd);
6987 }
6988
6989 /**
6990  * ixgbe_add_sanmac_netdev - Add the SAN MAC address to the corresponding
6991  * netdev->dev_addrs
6992  * @netdev: network interface device structure
6993  *
6994  * Returns non-zero on failure
6995  **/
6996 static int ixgbe_add_sanmac_netdev(struct net_device *dev)
6997 {
6998         int err = 0;
6999         struct ixgbe_adapter *adapter = netdev_priv(dev);
7000         struct ixgbe_mac_info *mac = &adapter->hw.mac;
7001
7002         if (is_valid_ether_addr(mac->san_addr)) {
7003                 rtnl_lock();
7004                 err = dev_addr_add(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7005                 rtnl_unlock();
7006         }
7007         return err;
7008 }
7009
7010 /**
7011  * ixgbe_del_sanmac_netdev - Removes the SAN MAC address to the corresponding
7012  * netdev->dev_addrs
7013  * @netdev: network interface device structure
7014  *
7015  * Returns non-zero on failure
7016  **/
7017 static int ixgbe_del_sanmac_netdev(struct net_device *dev)
7018 {
7019         int err = 0;
7020         struct ixgbe_adapter *adapter = netdev_priv(dev);
7021         struct ixgbe_mac_info *mac = &adapter->hw.mac;
7022
7023         if (is_valid_ether_addr(mac->san_addr)) {
7024                 rtnl_lock();
7025                 err = dev_addr_del(dev, mac->san_addr, NETDEV_HW_ADDR_T_SAN);
7026                 rtnl_unlock();
7027         }
7028         return err;
7029 }
7030
7031 #ifdef CONFIG_NET_POLL_CONTROLLER
7032 /*
7033  * Polling 'interrupt' - used by things like netconsole to send skbs
7034  * without having to re-enable interrupts. It's not called while
7035  * the interrupt routine is executing.
7036  */
7037 static void ixgbe_netpoll(struct net_device *netdev)
7038 {
7039         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7040         int i;
7041
7042         /* if interface is down do nothing */
7043         if (test_bit(__IXGBE_DOWN, &adapter->state))
7044                 return;
7045
7046         adapter->flags |= IXGBE_FLAG_IN_NETPOLL;
7047         if (adapter->flags & IXGBE_FLAG_MSIX_ENABLED) {
7048                 int num_q_vectors = adapter->num_msix_vectors - NON_Q_VECTORS;
7049                 for (i = 0; i < num_q_vectors; i++) {
7050                         struct ixgbe_q_vector *q_vector = adapter->q_vector[i];
7051                         ixgbe_msix_clean_many(0, q_vector);
7052                 }
7053         } else {
7054                 ixgbe_intr(adapter->pdev->irq, netdev);
7055         }
7056         adapter->flags &= ~IXGBE_FLAG_IN_NETPOLL;
7057 }
7058 #endif
7059
7060 static struct rtnl_link_stats64 *ixgbe_get_stats64(struct net_device *netdev,
7061                                                    struct rtnl_link_stats64 *stats)
7062 {
7063         struct ixgbe_adapter *adapter = netdev_priv(netdev);
7064         int i;
7065
7066         rcu_read_lock();
7067         for (i = 0; i < adapter->num_rx_queues; i++) {
7068                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->rx_ring[i]);
7069                 u64 bytes, packets;
7070                 unsigned int start;
7071
7072                 if (ring) {
7073                         do {
7074                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7075                                 packets = ring->stats.packets;
7076                                 bytes   = ring->stats.bytes;
7077                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7078                         stats->rx_packets += packets;
7079                         stats->rx_bytes   += bytes;
7080                 }
7081         }
7082
7083         for (i = 0; i < adapter->num_tx_queues; i++) {
7084                 struct ixgbe_ring *ring = ACCESS_ONCE(adapter->tx_ring[i]);
7085                 u64 bytes, packets;
7086                 unsigned int start;
7087
7088                 if (ring) {
7089                         do {
7090                                 start = u64_stats_fetch_begin_bh(&ring->syncp);
7091                                 packets = ring->stats.packets;
7092                                 bytes   = ring->stats.bytes;
7093                         } while (u64_stats_fetch_retry_bh(&ring->syncp, start));
7094                         stats->tx_packets += packets;
7095                         stats->tx_bytes   += bytes;
7096                 }
7097         }
7098         rcu_read_unlock();
7099         /* following stats updated by ixgbe_watchdog_task() */
7100         stats->multicast        = netdev->stats.multicast;
7101         stats->rx_errors        = netdev->stats.rx_errors;
7102         stats->rx_length_errors = netdev->stats.rx_length_errors;
7103         stats->rx_crc_errors    = netdev->stats.rx_crc_errors;
7104         stats->rx_missed_errors = netdev->stats.rx_missed_errors;
7105         return stats;
7106 }
7107
7108 /* ixgbe_validate_rtr - verify 802.1Qp to Rx packet buffer mapping is valid.
7109  * #adapter: pointer to ixgbe_adapter
7110  * @tc: number of traffic classes currently enabled
7111  *
7112  * Configure a valid 802.1Qp to Rx packet buffer mapping ie confirm
7113  * 802.1Q priority maps to a packet buffer that exists.
7114  */
7115 static void ixgbe_validate_rtr(struct ixgbe_adapter *adapter, u8 tc)
7116 {
7117         struct ixgbe_hw *hw = &adapter->hw;
7118         u32 reg, rsave;
7119         int i;
7120
7121         /* 82598 have a static priority to TC mapping that can not
7122          * be changed so no validation is needed.
7123          */
7124         if (hw->mac.type == ixgbe_mac_82598EB)
7125                 return;
7126
7127         reg = IXGBE_READ_REG(hw, IXGBE_RTRUP2TC);
7128         rsave = reg;
7129
7130         for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {
7131                 u8 up2tc = reg >> (i * IXGBE_RTRUP2TC_UP_SHIFT);
7132
7133                 /* If up2tc is out of bounds default to zero */
7134                 if (up2tc > tc)
7135                         reg &= ~(0x7 << IXGBE_RTRUP2TC_UP_SHIFT);
7136         }
7137
7138         if (reg != rsave)
7139                 IXGBE_WRITE_REG(hw, IXGBE_RTRUP2TC, reg);
7140
7141         return;
7142 }
7143
7144
7145 /* ixgbe_setup_tc - routine to configure net_device for multiple traffic
7146  * classes.
7147  *
7148  * @netdev: net device to configure
7149  * @tc: number of traffic classes to enable
7150  */
7151 int ixgbe_setup_tc(struct net_device *dev, u8 tc)
7152 {
7153         struct ixgbe_adapter *adapter = netdev_priv(dev);
7154         struct ixgbe_hw *hw = &adapter->hw;
7155
7156         /* If DCB is anabled do not remove traffic classes, multiple
7157          * traffic classes are required to implement DCB
7158          */
7159         if (!tc && (adapter->flags & IXGBE_FLAG_DCB_ENABLED))
7160                 return 0;
7161
7162         /* Hardware supports up to 8 traffic classes */
7163         if (tc > MAX_TRAFFIC_CLASS ||
7164             (hw->mac.type == ixgbe_mac_82598EB && tc < MAX_TRAFFIC_CLASS))
7165                 return -EINVAL;
7166
7167         /* Hardware has to reinitialize queues and interrupts to
7168          * match packet buffer alignment. Unfortunantly, the
7169          * hardware is not flexible enough to do this dynamically.
7170          */
7171         if (netif_running(dev))
7172                 ixgbe_close(dev);
7173         ixgbe_clear_interrupt_scheme(adapter);
7174
7175         if (tc)
7176                 netdev_set_num_tc(dev, tc);
7177         else
7178                 netdev_reset_tc(dev);
7179
7180         ixgbe_init_interrupt_scheme(adapter);
7181         ixgbe_validate_rtr(adapter, tc);
7182         if (netif_running(dev))
7183                 ixgbe_open(dev);
7184
7185         return 0;
7186 }
7187
7188 static const struct net_device_ops ixgbe_netdev_ops = {
7189         .ndo_open               = ixgbe_open,
7190         .ndo_stop               = ixgbe_close,
7191         .ndo_start_xmit         = ixgbe_xmit_frame,
7192         .ndo_select_queue       = ixgbe_select_queue,
7193         .ndo_set_rx_mode        = ixgbe_set_rx_mode,
7194         .ndo_set_multicast_list = ixgbe_set_rx_mode,
7195         .ndo_validate_addr      = eth_validate_addr,
7196         .ndo_set_mac_address    = ixgbe_set_mac,
7197         .ndo_change_mtu         = ixgbe_change_mtu,
7198         .ndo_tx_timeout         = ixgbe_tx_timeout,
7199         .ndo_vlan_rx_add_vid    = ixgbe_vlan_rx_add_vid,
7200         .ndo_vlan_rx_kill_vid   = ixgbe_vlan_rx_kill_vid,
7201         .ndo_do_ioctl           = ixgbe_ioctl,
7202         .ndo_set_vf_mac         = ixgbe_ndo_set_vf_mac,
7203         .ndo_set_vf_vlan        = ixgbe_ndo_set_vf_vlan,
7204         .ndo_set_vf_tx_rate     = ixgbe_ndo_set_vf_bw,
7205         .ndo_get_vf_config      = ixgbe_ndo_get_vf_config,
7206         .ndo_get_stats64        = ixgbe_get_stats64,
7207         .ndo_setup_tc           = ixgbe_setup_tc,
7208 #ifdef CONFIG_NET_POLL_CONTROLLER
7209         .ndo_poll_controller    = ixgbe_netpoll,
7210 #endif
7211 #ifdef IXGBE_FCOE
7212         .ndo_fcoe_ddp_setup = ixgbe_fcoe_ddp_get,
7213         .ndo_fcoe_ddp_target = ixgbe_fcoe_ddp_target,
7214         .ndo_fcoe_ddp_done = ixgbe_fcoe_ddp_put,
7215         .ndo_fcoe_enable = ixgbe_fcoe_enable,
7216         .ndo_fcoe_disable = ixgbe_fcoe_disable,
7217         .ndo_fcoe_get_wwn = ixgbe_fcoe_get_wwn,
7218 #endif /* IXGBE_FCOE */
7219 };
7220
7221 static void __devinit ixgbe_probe_vf(struct ixgbe_adapter *adapter,
7222                            const struct ixgbe_info *ii)
7223 {
7224 #ifdef CONFIG_PCI_IOV
7225         struct ixgbe_hw *hw = &adapter->hw;
7226         int err;
7227         int num_vf_macvlans, i;
7228         struct vf_macvlans *mv_list;
7229
7230         if (hw->mac.type == ixgbe_mac_82598EB || !max_vfs)
7231                 return;
7232
7233         /* The 82599 supports up to 64 VFs per physical function
7234          * but this implementation limits allocation to 63 so that
7235          * basic networking resources are still available to the
7236          * physical function
7237          */
7238         adapter->num_vfs = (max_vfs > 63) ? 63 : max_vfs;
7239         adapter->flags |= IXGBE_FLAG_SRIOV_ENABLED;
7240         err = pci_enable_sriov(adapter->pdev, adapter->num_vfs);
7241         if (err) {
7242                 e_err(probe, "Failed to enable PCI sriov: %d\n", err);
7243                 goto err_novfs;
7244         }
7245
7246         num_vf_macvlans = hw->mac.num_rar_entries -
7247                 (IXGBE_MAX_PF_MACVLANS + 1 + adapter->num_vfs);
7248
7249         adapter->mv_list = mv_list = kcalloc(num_vf_macvlans,
7250                                              sizeof(struct vf_macvlans),
7251                                              GFP_KERNEL);
7252         if (mv_list) {
7253                 /* Initialize list of VF macvlans */
7254                 INIT_LIST_HEAD(&adapter->vf_mvs.l);
7255                 for (i = 0; i < num_vf_macvlans; i++) {
7256                         mv_list->vf = -1;
7257                         mv_list->free = true;
7258                         mv_list->rar_entry = hw->mac.num_rar_entries -
7259                                 (i + adapter->num_vfs + 1);
7260                         list_add(&mv_list->l, &adapter->vf_mvs.l);
7261                         mv_list++;
7262                 }
7263         }
7264
7265         /* If call to enable VFs succeeded then allocate memory
7266          * for per VF control structures.
7267          */
7268         adapter->vfinfo =
7269                 kcalloc(adapter->num_vfs,
7270                         sizeof(struct vf_data_storage), GFP_KERNEL);
7271         if (adapter->vfinfo) {
7272                 /* Now that we're sure SR-IOV is enabled
7273                  * and memory allocated set up the mailbox parameters
7274                  */
7275                 ixgbe_init_mbx_params_pf(hw);
7276                 memcpy(&hw->mbx.ops, ii->mbx_ops,
7277                        sizeof(hw->mbx.ops));
7278
7279                 /* Disable RSC when in SR-IOV mode */
7280                 adapter->flags2 &= ~(IXGBE_FLAG2_RSC_CAPABLE |
7281                                      IXGBE_FLAG2_RSC_ENABLED);
7282                 return;
7283         }
7284
7285         /* Oh oh */
7286         e_err(probe, "Unable to allocate memory for VF Data Storage - "
7287               "SRIOV disabled\n");
7288         pci_disable_sriov(adapter->pdev);
7289
7290 err_novfs:
7291         adapter->flags &= ~IXGBE_FLAG_SRIOV_ENABLED;
7292         adapter->num_vfs = 0;
7293 #endif /* CONFIG_PCI_IOV */
7294 }
7295
7296 /**
7297  * ixgbe_probe - Device Initialization Routine
7298  * @pdev: PCI device information struct
7299  * @ent: entry in ixgbe_pci_tbl
7300  *
7301  * Returns 0 on success, negative on failure
7302  *
7303  * ixgbe_probe initializes an adapter identified by a pci_dev structure.
7304  * The OS initialization, configuring of the adapter private structure,
7305  * and a hardware reset occur.
7306  **/
7307 static int __devinit ixgbe_probe(struct pci_dev *pdev,
7308                                  const struct pci_device_id *ent)
7309 {
7310         struct net_device *netdev;
7311         struct ixgbe_adapter *adapter = NULL;
7312         struct ixgbe_hw *hw;
7313         const struct ixgbe_info *ii = ixgbe_info_tbl[ent->driver_data];
7314         static int cards_found;
7315         int i, err, pci_using_dac;
7316         u8 part_str[IXGBE_PBANUM_LENGTH];
7317         unsigned int indices = num_possible_cpus();
7318 #ifdef IXGBE_FCOE
7319         u16 device_caps;
7320 #endif
7321         u32 eec;
7322
7323         /* Catch broken hardware that put the wrong VF device ID in
7324          * the PCIe SR-IOV capability.
7325          */
7326         if (pdev->is_virtfn) {
7327                 WARN(1, KERN_ERR "%s (%hx:%hx) should not be a VF!\n",
7328                      pci_name(pdev), pdev->vendor, pdev->device);
7329                 return -EINVAL;
7330         }
7331
7332         err = pci_enable_device_mem(pdev);
7333         if (err)
7334                 return err;
7335
7336         if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)) &&
7337             !dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64))) {
7338                 pci_using_dac = 1;
7339         } else {
7340                 err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
7341                 if (err) {
7342                         err = dma_set_coherent_mask(&pdev->dev,
7343                                                     DMA_BIT_MASK(32));
7344                         if (err) {
7345                                 dev_err(&pdev->dev,
7346                                         "No usable DMA configuration, aborting\n");
7347                                 goto err_dma;
7348                         }
7349                 }
7350                 pci_using_dac = 0;
7351         }
7352
7353         err = pci_request_selected_regions(pdev, pci_select_bars(pdev,
7354                                            IORESOURCE_MEM), ixgbe_driver_name);
7355         if (err) {
7356                 dev_err(&pdev->dev,
7357                         "pci_request_selected_regions failed 0x%x\n", err);
7358                 goto err_pci_reg;
7359         }
7360
7361         pci_enable_pcie_error_reporting(pdev);
7362
7363         pci_set_master(pdev);
7364         pci_save_state(pdev);
7365
7366 #ifdef CONFIG_IXGBE_DCB
7367         indices *= MAX_TRAFFIC_CLASS;
7368 #endif
7369
7370         if (ii->mac == ixgbe_mac_82598EB)
7371                 indices = min_t(unsigned int, indices, IXGBE_MAX_RSS_INDICES);
7372         else
7373                 indices = min_t(unsigned int, indices, IXGBE_MAX_FDIR_INDICES);
7374
7375 #ifdef IXGBE_FCOE
7376         indices += min_t(unsigned int, num_possible_cpus(),
7377                          IXGBE_MAX_FCOE_INDICES);
7378 #endif
7379         netdev = alloc_etherdev_mq(sizeof(struct ixgbe_adapter), indices);
7380         if (!netdev) {
7381                 err = -ENOMEM;
7382                 goto err_alloc_etherdev;
7383         }
7384
7385         SET_NETDEV_DEV(netdev, &pdev->dev);
7386
7387         adapter = netdev_priv(netdev);
7388         pci_set_drvdata(pdev, adapter);
7389
7390         adapter->netdev = netdev;
7391         adapter->pdev = pdev;
7392         hw = &adapter->hw;
7393         hw->back = adapter;
7394         adapter->msg_enable = (1 << DEFAULT_DEBUG_LEVEL_SHIFT) - 1;
7395
7396         hw->hw_addr = ioremap(pci_resource_start(pdev, 0),
7397                               pci_resource_len(pdev, 0));
7398         if (!hw->hw_addr) {
7399                 err = -EIO;
7400                 goto err_ioremap;
7401         }
7402
7403         for (i = 1; i <= 5; i++) {
7404                 if (pci_resource_len(pdev, i) == 0)
7405                         continue;
7406         }
7407
7408         netdev->netdev_ops = &ixgbe_netdev_ops;
7409         ixgbe_set_ethtool_ops(netdev);
7410         netdev->watchdog_timeo = 5 * HZ;
7411         strncpy(netdev->name, pci_name(pdev), sizeof(netdev->name) - 1);
7412
7413         adapter->bd_number = cards_found;
7414
7415         /* Setup hw api */
7416         memcpy(&hw->mac.ops, ii->mac_ops, sizeof(hw->mac.ops));
7417         hw->mac.type  = ii->mac;
7418
7419         /* EEPROM */
7420         memcpy(&hw->eeprom.ops, ii->eeprom_ops, sizeof(hw->eeprom.ops));
7421         eec = IXGBE_READ_REG(hw, IXGBE_EEC);
7422         /* If EEPROM is valid (bit 8 = 1), use default otherwise use bit bang */
7423         if (!(eec & (1 << 8)))
7424                 hw->eeprom.ops.read = &ixgbe_read_eeprom_bit_bang_generic;
7425
7426         /* PHY */
7427         memcpy(&hw->phy.ops, ii->phy_ops, sizeof(hw->phy.ops));
7428         hw->phy.sfp_type = ixgbe_sfp_type_unknown;
7429         /* ixgbe_identify_phy_generic will set prtad and mmds properly */
7430         hw->phy.mdio.prtad = MDIO_PRTAD_NONE;
7431         hw->phy.mdio.mmds = 0;
7432         hw->phy.mdio.mode_support = MDIO_SUPPORTS_C45 | MDIO_EMULATE_C22;
7433         hw->phy.mdio.dev = netdev;
7434         hw->phy.mdio.mdio_read = ixgbe_mdio_read;
7435         hw->phy.mdio.mdio_write = ixgbe_mdio_write;
7436
7437         ii->get_invariants(hw);
7438
7439         /* setup the private structure */
7440         err = ixgbe_sw_init(adapter);
7441         if (err)
7442                 goto err_sw_init;
7443
7444         /* Make it possible the adapter to be woken up via WOL */
7445         switch (adapter->hw.mac.type) {
7446         case ixgbe_mac_82599EB:
7447         case ixgbe_mac_X540:
7448                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7449                 break;
7450         default:
7451                 break;
7452         }
7453
7454         /*
7455          * If there is a fan on this device and it has failed log the
7456          * failure.
7457          */
7458         if (adapter->flags & IXGBE_FLAG_FAN_FAIL_CAPABLE) {
7459                 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP);
7460                 if (esdp & IXGBE_ESDP_SDP1)
7461                         e_crit(probe, "Fan has stopped, replace the adapter\n");
7462         }
7463
7464         /* reset_hw fills in the perm_addr as well */
7465         hw->phy.reset_if_overtemp = true;
7466         err = hw->mac.ops.reset_hw(hw);
7467         hw->phy.reset_if_overtemp = false;
7468         if (err == IXGBE_ERR_SFP_NOT_PRESENT &&
7469             hw->mac.type == ixgbe_mac_82598EB) {
7470                 err = 0;
7471         } else if (err == IXGBE_ERR_SFP_NOT_SUPPORTED) {
7472                 e_dev_err("failed to load because an unsupported SFP+ "
7473                           "module type was detected.\n");
7474                 e_dev_err("Reload the driver after installing a supported "
7475                           "module.\n");
7476                 goto err_sw_init;
7477         } else if (err) {
7478                 e_dev_err("HW Init failed: %d\n", err);
7479                 goto err_sw_init;
7480         }
7481
7482         ixgbe_probe_vf(adapter, ii);
7483
7484         netdev->features = NETIF_F_SG |
7485                            NETIF_F_IP_CSUM |
7486                            NETIF_F_HW_VLAN_TX |
7487                            NETIF_F_HW_VLAN_RX |
7488                            NETIF_F_HW_VLAN_FILTER;
7489
7490         netdev->features |= NETIF_F_IPV6_CSUM;
7491         netdev->features |= NETIF_F_TSO;
7492         netdev->features |= NETIF_F_TSO6;
7493         netdev->features |= NETIF_F_GRO;
7494         netdev->features |= NETIF_F_RXHASH;
7495
7496         switch (adapter->hw.mac.type) {
7497         case ixgbe_mac_82599EB:
7498         case ixgbe_mac_X540:
7499                 netdev->features |= NETIF_F_SCTP_CSUM;
7500                 break;
7501         default:
7502                 break;
7503         }
7504
7505         netdev->vlan_features |= NETIF_F_TSO;
7506         netdev->vlan_features |= NETIF_F_TSO6;
7507         netdev->vlan_features |= NETIF_F_IP_CSUM;
7508         netdev->vlan_features |= NETIF_F_IPV6_CSUM;
7509         netdev->vlan_features |= NETIF_F_SG;
7510
7511         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7512                 adapter->flags &= ~(IXGBE_FLAG_RSS_ENABLED |
7513                                     IXGBE_FLAG_DCB_ENABLED);
7514
7515 #ifdef CONFIG_IXGBE_DCB
7516         netdev->dcbnl_ops = &dcbnl_ops;
7517 #endif
7518
7519 #ifdef IXGBE_FCOE
7520         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7521                 if (hw->mac.ops.get_device_caps) {
7522                         hw->mac.ops.get_device_caps(hw, &device_caps);
7523                         if (device_caps & IXGBE_DEVICE_CAPS_FCOE_OFFLOADS)
7524                                 adapter->flags &= ~IXGBE_FLAG_FCOE_CAPABLE;
7525                 }
7526         }
7527         if (adapter->flags & IXGBE_FLAG_FCOE_CAPABLE) {
7528                 netdev->vlan_features |= NETIF_F_FCOE_CRC;
7529                 netdev->vlan_features |= NETIF_F_FSO;
7530                 netdev->vlan_features |= NETIF_F_FCOE_MTU;
7531         }
7532 #endif /* IXGBE_FCOE */
7533         if (pci_using_dac) {
7534                 netdev->features |= NETIF_F_HIGHDMA;
7535                 netdev->vlan_features |= NETIF_F_HIGHDMA;
7536         }
7537
7538         if (adapter->flags2 & IXGBE_FLAG2_RSC_ENABLED)
7539                 netdev->features |= NETIF_F_LRO;
7540
7541         /* make sure the EEPROM is good */
7542         if (hw->eeprom.ops.validate_checksum(hw, NULL) < 0) {
7543                 e_dev_err("The EEPROM Checksum Is Not Valid\n");
7544                 err = -EIO;
7545                 goto err_eeprom;
7546         }
7547
7548         memcpy(netdev->dev_addr, hw->mac.perm_addr, netdev->addr_len);
7549         memcpy(netdev->perm_addr, hw->mac.perm_addr, netdev->addr_len);
7550
7551         if (ixgbe_validate_mac_addr(netdev->perm_addr)) {
7552                 e_dev_err("invalid MAC address\n");
7553                 err = -EIO;
7554                 goto err_eeprom;
7555         }
7556
7557         /* power down the optics for multispeed fiber and 82599 SFP+ fiber */
7558         if (hw->mac.ops.disable_tx_laser &&
7559             ((hw->phy.multispeed_fiber) ||
7560              ((hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) &&
7561               (hw->mac.type == ixgbe_mac_82599EB))))
7562                 hw->mac.ops.disable_tx_laser(hw);
7563
7564         setup_timer(&adapter->service_timer, &ixgbe_service_timer,
7565                     (unsigned long) adapter);
7566
7567         INIT_WORK(&adapter->service_task, ixgbe_service_task);
7568         clear_bit(__IXGBE_SERVICE_SCHED, &adapter->state);
7569
7570         err = ixgbe_init_interrupt_scheme(adapter);
7571         if (err)
7572                 goto err_sw_init;
7573
7574         if (!(adapter->flags & IXGBE_FLAG_RSS_ENABLED))
7575                 netdev->features &= ~NETIF_F_RXHASH;
7576
7577         switch (pdev->device) {
7578         case IXGBE_DEV_ID_82599_SFP:
7579                 /* Only this subdevice supports WOL */
7580                 if (pdev->subsystem_device == IXGBE_SUBDEV_ID_82599_SFP)
7581                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7582                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7583                 break;
7584         case IXGBE_DEV_ID_82599_COMBO_BACKPLANE:
7585                 /* All except this subdevice support WOL */
7586                 if (pdev->subsystem_device != IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ)
7587                         adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7588                                         IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7589                 break;
7590         case IXGBE_DEV_ID_82599_KX4:
7591                 adapter->wol = (IXGBE_WUFC_MAG | IXGBE_WUFC_EX |
7592                                 IXGBE_WUFC_MC | IXGBE_WUFC_BC);
7593                 break;
7594         default:
7595                 adapter->wol = 0;
7596                 break;
7597         }
7598         device_set_wakeup_enable(&adapter->pdev->dev, adapter->wol);
7599
7600         /* pick up the PCI bus settings for reporting later */
7601         hw->mac.ops.get_bus_info(hw);
7602
7603         /* print bus type/speed/width info */
7604         e_dev_info("(PCI Express:%s:%s) %pM\n",
7605                    (hw->bus.speed == ixgbe_bus_speed_5000 ? "5.0GT/s" :
7606                     hw->bus.speed == ixgbe_bus_speed_2500 ? "2.5GT/s" :
7607                     "Unknown"),
7608                    (hw->bus.width == ixgbe_bus_width_pcie_x8 ? "Width x8" :
7609                     hw->bus.width == ixgbe_bus_width_pcie_x4 ? "Width x4" :
7610                     hw->bus.width == ixgbe_bus_width_pcie_x1 ? "Width x1" :
7611                     "Unknown"),
7612                    netdev->dev_addr);
7613
7614         err = ixgbe_read_pba_string_generic(hw, part_str, IXGBE_PBANUM_LENGTH);
7615         if (err)
7616                 strncpy(part_str, "Unknown", IXGBE_PBANUM_LENGTH);
7617         if (ixgbe_is_sfp(hw) && hw->phy.sfp_type != ixgbe_sfp_type_not_present)
7618                 e_dev_info("MAC: %d, PHY: %d, SFP+: %d, PBA No: %s\n",
7619                            hw->mac.type, hw->phy.type, hw->phy.sfp_type,
7620                            part_str);
7621         else
7622                 e_dev_info("MAC: %d, PHY: %d, PBA No: %s\n",
7623                            hw->mac.type, hw->phy.type, part_str);
7624
7625         if (hw->bus.width <= ixgbe_bus_width_pcie_x4) {
7626                 e_dev_warn("PCI-Express bandwidth available for this card is "
7627                            "not sufficient for optimal performance.\n");
7628                 e_dev_warn("For optimal performance a x8 PCI-Express slot "
7629                            "is required.\n");
7630         }
7631
7632         /* save off EEPROM version number */
7633         hw->eeprom.ops.read(hw, 0x29, &adapter->eeprom_version);
7634
7635         /* reset the hardware with the new settings */
7636         err = hw->mac.ops.start_hw(hw);
7637
7638         if (err == IXGBE_ERR_EEPROM_VERSION) {
7639                 /* We are running on a pre-production device, log a warning */
7640                 e_dev_warn("This device is a pre-production adapter/LOM. "
7641                            "Please be aware there may be issues associated "
7642                            "with your hardware.  If you are experiencing "
7643                            "problems please contact your Intel or hardware "
7644                            "representative who provided you with this "
7645                            "hardware.\n");
7646         }
7647         strcpy(netdev->name, "eth%d");
7648         err = register_netdev(netdev);
7649         if (err)
7650                 goto err_register;
7651
7652         /* carrier off reporting is important to ethtool even BEFORE open */
7653         netif_carrier_off(netdev);
7654
7655 #ifdef CONFIG_IXGBE_DCA
7656         if (dca_add_requester(&pdev->dev) == 0) {
7657                 adapter->flags |= IXGBE_FLAG_DCA_ENABLED;
7658                 ixgbe_setup_dca(adapter);
7659         }
7660 #endif
7661         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED) {
7662                 e_info(probe, "IOV is enabled with %d VFs\n", adapter->num_vfs);
7663                 for (i = 0; i < adapter->num_vfs; i++)
7664                         ixgbe_vf_configuration(pdev, (i | 0x10000000));
7665         }
7666
7667         /* Inform firmware of driver version */
7668         if (hw->mac.ops.set_fw_drv_ver)
7669                 hw->mac.ops.set_fw_drv_ver(hw, MAJ, MIN, BUILD, KFIX);
7670
7671         /* add san mac addr to netdev */
7672         ixgbe_add_sanmac_netdev(netdev);
7673
7674         e_dev_info("Intel(R) 10 Gigabit Network Connection\n");
7675         cards_found++;
7676         return 0;
7677
7678 err_register:
7679         ixgbe_release_hw_control(adapter);
7680         ixgbe_clear_interrupt_scheme(adapter);
7681 err_sw_init:
7682 err_eeprom:
7683         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7684                 ixgbe_disable_sriov(adapter);
7685         adapter->flags2 &= ~IXGBE_FLAG2_SEARCH_FOR_SFP;
7686         iounmap(hw->hw_addr);
7687 err_ioremap:
7688         free_netdev(netdev);
7689 err_alloc_etherdev:
7690         pci_release_selected_regions(pdev,
7691                                      pci_select_bars(pdev, IORESOURCE_MEM));
7692 err_pci_reg:
7693 err_dma:
7694         pci_disable_device(pdev);
7695         return err;
7696 }
7697
7698 /**
7699  * ixgbe_remove - Device Removal Routine
7700  * @pdev: PCI device information struct
7701  *
7702  * ixgbe_remove is called by the PCI subsystem to alert the driver
7703  * that it should release a PCI device.  The could be caused by a
7704  * Hot-Plug event, or because the driver is going to be removed from
7705  * memory.
7706  **/
7707 static void __devexit ixgbe_remove(struct pci_dev *pdev)
7708 {
7709         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7710         struct net_device *netdev = adapter->netdev;
7711
7712         set_bit(__IXGBE_DOWN, &adapter->state);
7713         cancel_work_sync(&adapter->service_task);
7714
7715 #ifdef CONFIG_IXGBE_DCA
7716         if (adapter->flags & IXGBE_FLAG_DCA_ENABLED) {
7717                 adapter->flags &= ~IXGBE_FLAG_DCA_ENABLED;
7718                 dca_remove_requester(&pdev->dev);
7719                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_DCA_CTRL, 1);
7720         }
7721
7722 #endif
7723 #ifdef IXGBE_FCOE
7724         if (adapter->flags & IXGBE_FLAG_FCOE_ENABLED)
7725                 ixgbe_cleanup_fcoe(adapter);
7726
7727 #endif /* IXGBE_FCOE */
7728
7729         /* remove the added san mac */
7730         ixgbe_del_sanmac_netdev(netdev);
7731
7732         if (netdev->reg_state == NETREG_REGISTERED)
7733                 unregister_netdev(netdev);
7734
7735         if (adapter->flags & IXGBE_FLAG_SRIOV_ENABLED)
7736                 ixgbe_disable_sriov(adapter);
7737
7738         ixgbe_clear_interrupt_scheme(adapter);
7739
7740         ixgbe_release_hw_control(adapter);
7741
7742         iounmap(adapter->hw.hw_addr);
7743         pci_release_selected_regions(pdev, pci_select_bars(pdev,
7744                                      IORESOURCE_MEM));
7745
7746         e_dev_info("complete\n");
7747
7748         free_netdev(netdev);
7749
7750         pci_disable_pcie_error_reporting(pdev);
7751
7752         pci_disable_device(pdev);
7753 }
7754
7755 /**
7756  * ixgbe_io_error_detected - called when PCI error is detected
7757  * @pdev: Pointer to PCI device
7758  * @state: The current pci connection state
7759  *
7760  * This function is called after a PCI bus error affecting
7761  * this device has been detected.
7762  */
7763 static pci_ers_result_t ixgbe_io_error_detected(struct pci_dev *pdev,
7764                                                 pci_channel_state_t state)
7765 {
7766         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7767         struct net_device *netdev = adapter->netdev;
7768
7769         netif_device_detach(netdev);
7770
7771         if (state == pci_channel_io_perm_failure)
7772                 return PCI_ERS_RESULT_DISCONNECT;
7773
7774         if (netif_running(netdev))
7775                 ixgbe_down(adapter);
7776         pci_disable_device(pdev);
7777
7778         /* Request a slot reset. */
7779         return PCI_ERS_RESULT_NEED_RESET;
7780 }
7781
7782 /**
7783  * ixgbe_io_slot_reset - called after the pci bus has been reset.
7784  * @pdev: Pointer to PCI device
7785  *
7786  * Restart the card from scratch, as if from a cold-boot.
7787  */
7788 static pci_ers_result_t ixgbe_io_slot_reset(struct pci_dev *pdev)
7789 {
7790         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7791         pci_ers_result_t result;
7792         int err;
7793
7794         if (pci_enable_device_mem(pdev)) {
7795                 e_err(probe, "Cannot re-enable PCI device after reset.\n");
7796                 result = PCI_ERS_RESULT_DISCONNECT;
7797         } else {
7798                 pci_set_master(pdev);
7799                 pci_restore_state(pdev);
7800                 pci_save_state(pdev);
7801
7802                 pci_wake_from_d3(pdev, false);
7803
7804                 ixgbe_reset(adapter);
7805                 IXGBE_WRITE_REG(&adapter->hw, IXGBE_WUS, ~0);
7806                 result = PCI_ERS_RESULT_RECOVERED;
7807         }
7808
7809         err = pci_cleanup_aer_uncorrect_error_status(pdev);
7810         if (err) {
7811                 e_dev_err("pci_cleanup_aer_uncorrect_error_status "
7812                           "failed 0x%0x\n", err);
7813                 /* non-fatal, continue */
7814         }
7815
7816         return result;
7817 }
7818
7819 /**
7820  * ixgbe_io_resume - called when traffic can start flowing again.
7821  * @pdev: Pointer to PCI device
7822  *
7823  * This callback is called when the error recovery driver tells us that
7824  * its OK to resume normal operation.
7825  */
7826 static void ixgbe_io_resume(struct pci_dev *pdev)
7827 {
7828         struct ixgbe_adapter *adapter = pci_get_drvdata(pdev);
7829         struct net_device *netdev = adapter->netdev;
7830
7831         if (netif_running(netdev)) {
7832                 if (ixgbe_up(adapter)) {
7833                         e_info(probe, "ixgbe_up failed after reset\n");
7834                         return;
7835                 }
7836         }
7837
7838         netif_device_attach(netdev);
7839 }
7840
7841 static struct pci_error_handlers ixgbe_err_handler = {
7842         .error_detected = ixgbe_io_error_detected,
7843         .slot_reset = ixgbe_io_slot_reset,
7844         .resume = ixgbe_io_resume,
7845 };
7846
7847 static struct pci_driver ixgbe_driver = {
7848         .name     = ixgbe_driver_name,
7849         .id_table = ixgbe_pci_tbl,
7850         .probe    = ixgbe_probe,
7851         .remove   = __devexit_p(ixgbe_remove),
7852 #ifdef CONFIG_PM
7853         .suspend  = ixgbe_suspend,
7854         .resume   = ixgbe_resume,
7855 #endif
7856         .shutdown = ixgbe_shutdown,
7857         .err_handler = &ixgbe_err_handler
7858 };
7859
7860 /**
7861  * ixgbe_init_module - Driver Registration Routine
7862  *
7863  * ixgbe_init_module is the first routine called when the driver is
7864  * loaded. All it does is register with the PCI subsystem.
7865  **/
7866 static int __init ixgbe_init_module(void)
7867 {
7868         int ret;
7869         pr_info("%s - version %s\n", ixgbe_driver_string, ixgbe_driver_version);
7870         pr_info("%s\n", ixgbe_copyright);
7871
7872 #ifdef CONFIG_IXGBE_DCA
7873         dca_register_notify(&dca_notifier);
7874 #endif
7875
7876         ret = pci_register_driver(&ixgbe_driver);
7877         return ret;
7878 }
7879
7880 module_init(ixgbe_init_module);
7881
7882 /**
7883  * ixgbe_exit_module - Driver Exit Cleanup Routine
7884  *
7885  * ixgbe_exit_module is called just before the driver is removed
7886  * from memory.
7887  **/
7888 static void __exit ixgbe_exit_module(void)
7889 {
7890 #ifdef CONFIG_IXGBE_DCA
7891         dca_unregister_notify(&dca_notifier);
7892 #endif
7893         pci_unregister_driver(&ixgbe_driver);
7894         rcu_barrier(); /* Wait for completion of call_rcu()'s */
7895 }
7896
7897 #ifdef CONFIG_IXGBE_DCA
7898 static int ixgbe_notify_dca(struct notifier_block *nb, unsigned long event,
7899                             void *p)
7900 {
7901         int ret_val;
7902
7903         ret_val = driver_for_each_device(&ixgbe_driver.driver, NULL, &event,
7904                                          __ixgbe_notify_dca);
7905
7906         return ret_val ? NOTIFY_BAD : NOTIFY_DONE;
7907 }
7908
7909 #endif /* CONFIG_IXGBE_DCA */
7910
7911 module_exit(ixgbe_exit_module);
7912
7913 /* ixgbe_main.c */